Isolation amplifier and abnormal condition detection device

Abstract

To convey the occurrence of an abnormal state quickly.SOLUTION: An isolation amplifier includes a primary circuit provided with an analog-digital conversion circuit for converting the input signal given from a device which is the object of detection and an encoder for encoding the output of the analog-digital conversion circuit and outputting the result of encoding, an abnormality detection circuit provided in the primary circuit, for detecting abnormality having occurred to the input signal and generating a detection signal, an isolation unit for conveying the output of the encoder and the detection signal to a secondary circuit while the primary circuit and the secondary circuit are insulated from each other, and a decoder provided in the secondary circuit, for performing decode processing that corresponds to the encode processing, the isolation amplifier further comprising an output circuit for generating an output signal that corresponds to the input signal, and an abnormal input detection-output circuit provided in the secondary circuit, for causing the output signal of the output circuit to be changed by a prescribed law on the basis of the detection signal and taking it as an output signal of the secondary circuit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to an isolation amplifier and an abnormal condition detection device. [Background technology]

[0002] Conventionally, isolation amplifiers have been used as devices that achieve both electrical isolation and signal transmission. Isolation amplifiers are widely used in various applications such as industry, communications, consumer, and automotive fields, and are used, for example, for data transmission between a motor driven by a high power supply voltage and a high current and an MPU (microprocessor unit) that controls the motor. For example, isolation amplifiers are used to realize current sensors and voltage sensors that detect high voltages and large currents in the circuits to be detected.

[0003] However, an abnormality may occur in the circuit to be detected, causing an excessive input to the isolation amplifier. In this case, from the viewpoint of protecting the entire system, the isolation amplifier needs to transmit the occurrence of the abnormality in a short time. However, the transmission speed in the data transmission path of the isolation amplifier is relatively slow, and there is a drawback in that it takes a relatively long time to transmit an abnormal state such as an excessive input.

[0004] One possible solution is to provide a transmission path different from the normal data transmission path of the isolation amplifier to transmit the abnormal state, but this would require a new dedicated pin for the transmission path. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-160096 A Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the embodiments is to provide an isolation amplifier and an abnormal condition detection device that can quickly transmit the occurrence of an abnormal condition. [Means for solving the problem]

[0007] An isolation amplifier according to an embodiment includes a primary circuit including an analog-to-digital conversion circuit that converts an input signal provided from a detection target device into a digital signal and an encoder that encodes and outputs an output of the analog-to-digital conversion circuit; an abnormality detection circuit provided in the primary circuit that detects an abnormality occurring in the input signal and generates a detection signal; an isolation unit that transmits the output of the encoder and the detection signal to the secondary circuit while isolating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit that receives the output of the encoder and the detection signal transmitted by the isolation unit and includes a decoder that performs a decoding process corresponding to the encoding process and generates an output signal corresponding to the input signal; and an abnormal input detection output circuit provided in the secondary circuit that changes the output signal of the output circuit in accordance with a predetermined rule based on the detection signal to produce an output signal of the secondary circuit. The input signal and the output signal are a pair of differential signals, and the abnormal input detection output circuit outputs a signal of a predetermined level instead of the pair of differential signals that are the output signal during a period in which the detection signal indicates that an abnormality has occurred. . [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram showing a specific configuration example of an isolation section 30. [Diagram 3] FIG. 2 is a block diagram showing a specific configuration example of an isolation section 30. [Figure 4] FIG. 2 is a block diagram showing a specific configuration example of an isolation section 30. [Diagram 5] 2 is a circuit diagram showing an example of a specific configuration of the conversion circuit 50 shown in FIG. 1; [Figure 6] FIG. 2 is a circuit diagram showing an example of a specific configuration of the LPF 23 and the abnormal input detection output circuit 26. [Figure 7]It shows waveforms of input / output, etc., with time on the horizontal axis and voltage on the vertical axis. [Figure 8] FIG. [Figure 9] FIG. 4 is a block diagram showing a second embodiment of the present invention. [Figure 10] 10 is a circuit diagram showing an example of a specific configuration of an abnormal input detection output circuit 27 of FIG. 9. [Figure 11] It shows waveforms of input / output, etc., with time on the horizontal axis and voltage on the vertical axis. [Figure 12] FIG. 11 is a block diagram showing a third embodiment of the present invention. [Figure 13] 13 is a circuit diagram showing an example of a specific configuration of a mixer 62 and an external circuit 80 in FIG. 12. [Figure 14] 10 is a timing chart for explaining the operation of the third embodiment. [Figure 15] FIG. 13 is a block diagram showing an example of a specific configuration of a mixer employed in a fourth embodiment of the present invention. [Figure 16] 10 is a timing chart for explaining the operation of the fourth embodiment. [Figure 17] FIG. 13 is a block diagram showing an example of a specific configuration of a mixer employed in the fifth embodiment of the present invention. [Figure 18] 13 is a timing chart for explaining the operation of the fifth embodiment. [Figure 19] FIG. 13 is a block diagram showing an example of a specific configuration of a mixer employed in a sixth embodiment of the present invention. [Figure 20] 13 is a timing chart for explaining the operation of the sixth embodiment. [Figure 21] FIG. 23 is a block diagram showing an example of a specific configuration of a mixer employed in the seventh embodiment of the present invention. [Figure 22] 13 is a timing chart for explaining the operation of the seventh embodiment. [Diagram 23] FIG. 23 is a block diagram showing an example of a specific configuration of a mixer employed in the eighth embodiment of the present invention. [Figure 24]FIG. 24 is a circuit diagram showing an example of a specific configuration of a pulse detector 87 in FIG. 23. [Diagram 25] 4 is a timing chart for explaining generation of a clock MCLK and output data MDAT in the isolation amplifier 8. [Figure 26] 4 is a timing chart for explaining the operation of the pulse detector 87. [Figure 27] Compatible with analog output isolation amplifiers. [Figure 28] FIG. 13 is a block diagram showing a ninth embodiment. [Figure 29] FIG. 23 is a block diagram showing a tenth embodiment. [Diagram 30] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0010] (First embodiment) Fig. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. The semiconductor integrated circuit in Fig. 1 constitutes an isolation amplifier. In this embodiment, a normal data transmission path of the isolation amplifier is used, and output data is changed in response to the occurrence of an abnormality, thereby making it possible to transmit the occurrence of an abnormality at high speed.

[0011] 1, the detection target is assumed to be the motor 55 or the motor drive circuit 56 that drives the motor 55, and an example of detecting an abnormality in voltage or current generated therein will be described, but the detection target is not limited to this. For example, this embodiment can also be applied to a case where a generator is used as the detection target and power abnormality in a sensor for vibration or heat generated in the generator is detected.

[0012] In FIG. 1, the isolation amplifier 1 includes a primary circuit 10, a secondary circuit 20, and an isolation unit 30. The primary circuit 10 outputs a digital value corresponding to a voltage, a current, etc. generated in a detection target such as a motor to the isolation unit 30. The isolation unit 30 transmits the output of the primary circuit 10 to the secondary circuit 20 while electrically insulating the primary circuit 10 from the secondary circuit 20. The secondary circuit 20 receives the digital value transmitted via the isolation unit 30 and restores the value of the voltage or current generated in the detection target. The output of the isolation amplifier 1 is supplied to a control circuit 52 constituted by an MCU (Micro Controller Unit) or the like via a differential to single-phase conversion circuit 50 and an abnormality detection circuit 51, so that the state of the detection target can be grasped in the control circuit 52.

[0013] The primary circuit 10 includes, for example, a ΔΣADC 11, an encoder 12, a clock generator 13, a reference voltage generator 14, and a comparator 15. The primary circuit 10 and the secondary circuit 20 are supplied with independent power sources. In Fig. 1, a power supply voltage VDD1 and a ground voltage GND1 are supplied to the primary circuit 10, and a power supply voltage VDD2 and a ground voltage GND2 are supplied to the secondary circuit 20.

[0014] A signal corresponding to a voltage value, a current value, etc. generated in the detection target is input to the primary circuit 10 as a differential input VIN by a pair of input differential signals VIN+, VIN-. These input differential signals VIN+, VIN- are provided to the ΔΣADC 11. The clock generator 13 generates a clock and provides it to the ΔΣADC 11. In addition, the reference voltage generator 14 generates a reference voltage and provides it to the ΔΣADC 11. Using the reference voltage from the reference voltage generator 14, the ΔΣADC 11 converts the input differential signals VIN+, VIN- into digital signals in synchronization with the clock signal generated by the clock generator 13, and outputs the digital signals to the encoder 12. The encoder 12 encodes the digital signals converted by the ΔΣADC 11, and outputs the encoded digital signals to the isolation unit 30.

[0015] Resistors R1 and R2 are connected in series between a power supply line to which a power supply voltage VDD1 is supplied and a ground line to which a ground voltage GND2 is supplied. A voltage appearing at a connection point between the resistors R1 and R2 is supplied to a negative input terminal of a comparator 15 as a detection voltage VREF. An input differential signal VIN+ is supplied to a positive input terminal of the comparator 15. The comparator 15 outputs a high-level (H-level) detection signal when the input differential signal VIN+ exceeds the detection voltage VREF. By appropriately setting the resistance values ​​of the resistors R1 and R2, the comparator 15 can be configured to output an H-level detection signal when the input differential signal VIN+ is an excessive input. That is, the detection signal from the comparator 15 indicates whether or not an abnormality such as an excessive input has occurred in the differential input VIN when the input differential signal VIN+ and the input differential signal VIN- are fixed to a ground voltage or the like. The comparator 15 outputs the detection signal to the isolation unit 30.

[0016] In the following explanation, it is assumed that an H-level detection signal is generated when an abnormality is detected, and that the detection signal is low level (L-level) when no abnormality is detected; however, conversely, the detection of an abnormality may be indicated by an L-level, and normal (usual) conditions may be indicated by an H-level.

[0017] Figures 2 to 4 are block diagrams showing specific configuration examples of the isolation section 30. Figure 2 shows an optical coupling type, Figure 3 shows a magnetic coupling type, and Figure 4 shows a capacitive coupling type.

[0018] 2, a digital signal is provided from the encoder 12 to a driver 31. A light-emitting element 32a and a current source 33 are connected in series between a power supply line and a ground line. The driver 31 drives the light-emitting element 32a by the input digital signal. As a result, the light-emitting element 32a is driven by the driver 31 to pass a current and emits light with an amount of light corresponding to the current that has passed.

[0019] The current source 33 is also supplied with a detection signal from the comparator 15. In response to the detection signal being at an H level, the current source 33 causes a predetermined amount of current to flow through the light-emitting element 32a. The current from the current source 33 is set to a current larger than the amount of current generated in the light-emitting element 32a by the driver 31 being driven.

[0020] Light from the light-emitting element 32a is received by the photodetector element 32b. The light-emitting element 32a and the photodetector element 32b are electrically insulated from each other. The photodetector element 32b generates a current according to the amount of light emitted by the light-emitting element 32a. A transimpedance amplifier (TIA) 34 converts the current generated by the photodetector element 32b into a voltage. The output voltage of the transimpedance amplifier 34 is supplied to the positive input terminals of comparators 35 and 36.

[0021] The comparator 35 compares the reference voltage VREF1 supplied to the negative input terminal with the output voltage of the transimpedance amplifier 34, and outputs a digital signal of H level when the output voltage of the transimpedance amplifier 34 is large, and a digital signal of low level (L level) when the output voltage is small. That is, the output of the comparator 35 is a digital signal corresponding to the digital signal from the encoder 12.

[0022] The comparator 36 compares a reference voltage VREF2 supplied to the negative input terminal with the output voltage of the transimpedance amplifier 34. The reference voltage VREF2 is set to a voltage that is greater than the reference voltage VREF1 and greater than the voltage generated by the driving of the driver 31. The comparator 36 outputs a digital signal of H level when the output voltage of the transimpedance amplifier 34 is greater than the reference voltage VREF2, and outputs a digital signal of L level when the output voltage is smaller than the reference voltage VREF2. In other words, the output of the comparator 36 is a pulse signal corresponding to the detection signal from the comparator 15.

[0023] 3 shows an isolation unit 40 that can be used as the isolation unit 30. The isolation unit 40 is composed of drivers 41a and 41b, primary and secondary coils 42a and 42b, and receivers 43a and 43b. The driver 41a and the receiver 43a are electrically insulated by the primary and secondary coil 42a, and the driver 41b and the receiver 43b are electrically insulated by the primary and secondary coil 42b. Although not shown, there may be two pairs of coils, providing doubly insulated.

[0024] The driver 41a drives the primary and secondary coils 42a by the digital signal from the encoder 12. The receiver 43a extracts a voltage generated by mutual induction between the primary and secondary coils 42a. Thus, the output of the receiver 43a becomes a digital signal corresponding to the digital signal from the encoder 12.

[0025] In addition, the driver 41b drives the primary and secondary coils 42b in response to the detection signal from the comparator 15. The receiver 43b extracts a voltage generated by mutual induction between the primary and secondary coils 42b. Thus, the output of the receiver 43b becomes a pulse signal corresponding to the detection signal from the comparator 15.

[0026] 4 shows an isolation section 45 that can be used as the isolation section 30. The isolation section 45 is composed of drivers 46a and 46b, coupling capacitors 47a and 47b, and receivers 48a and 48b. The driver 46a and the receiver 48a are electrically insulated by the coupling capacitor 47a, and the driver 46b and the receiver 48b are electrically insulated by the coupling capacitor 47b. Although not shown, there may be two pairs of coupling capacitors, providing double insulation.

[0027] The driver 46a applies the digital signal from the encoder 12 to a coupling capacitor 47a. The receiver 48a extracts the output of the driver 46a via the coupling capacitor 47a. Thus, the output of the receiver 48a is a digital signal corresponding to the digital signal from the encoder 12.

[0028] In addition, the driver 46b applies the detection signal from the comparator 15 to a coupling capacitor 47b. The receiver 48b extracts the output of the driver 46b via the coupling capacitor 47b. Thus, the output of the receiver 48b becomes a pulse signal corresponding to the detection signal from the comparator 15.

[0029] 1, the output of the isolation unit 30 is supplied to a secondary circuit 20. The secondary circuit 20 includes a decoder 21, a 1-bit DAC 22, an LPF (low pass filter) 23, a clock recovery circuit 24, a reference voltage generator 25, and an abnormal input detection output circuit .

[0030] The output (digital signal) of the isolation unit 30 based on the output of the encoder 12 is provided to the decoder 21 and the clock recovery circuit 24. The clock recovery circuit 24 recovers a clock from the input digital signal and outputs it to the decoder 21. In addition, the reference voltage generator 25 generates a reference voltage and outputs it to the decoder 21. The decoder 21 performs a decoding process to restore the signal encoded by the encoder 12 to the signal before encoding, using the clock and the reference voltage from the clock recovery circuit 24. The decoder 21 outputs the decoded digital signal to the 1-bit DAC 22.

[0031] The 1-bit DAC 22 converts the digital signal decoded by the decoder 21 into an analog signal and outputs it to the LPF 23. The LPF 23 removes unnecessary frequency components contained in the analog signal output from the 1-bit DAC 22, and outputs a differential output VOUT from an output terminal based on a pair of output differential signals VOUT+, VOUT-. The output differential signals VOUT+, VOUT- are input to the differential to single-phase conversion circuit 50 as differential signals AIN+, AIN- (hereinafter, when there is no need to distinguish between these, they will be referred to as differential signals AIN). The decoder 21, the 1-bit DAC 22, and the LPF 23 form an output circuit.

[0032] The differential to single-phase conversion circuit 50 converts the differential signals AIN+, AIN- into a single-phase output. For example, the differential to single-phase conversion circuit 50 obtains a difference between the differential signals AIN+, AIN-, converts the differential signals AIN+, AIN- into a single-phase output AOUT, and outputs the single-phase output AOUT to the ADC1 terminal of the control circuit 52. The differential to single-phase conversion circuit 50 also adds the differential signals AIN+, AIN- together, and outputs a voltage of (half) the addition result to the abnormality detection circuit 51.

[0033] FIG. 5 is a circuit diagram showing an example of a specific configuration of the conversion circuit 50 shown in FIG.

[0034] A differential signal AIN+ is supplied to the non-inverting input terminal of the operational amplifier OP1a. The inverting input terminal of the operational amplifier OP1a is connected to the output terminal via a resistor R22a and is also connected to a node r via a resistor R21a. The operational amplifier OP1a and the resistors R21a and R22a form a non-inverting amplifier.

[0035] The differential signal AIN- is supplied to the non-inverting input terminal of the operational amplifier OP1b. The inverting input terminal of the operational amplifier OP1b is connected to the output terminal via a resistor R22b and is also connected to a node r via a resistor R21b. The operational amplifier OP1b and the resistors R21b and R22b form a non-inverting amplifier.

[0036] The output terminal of the operational amplifier OP1a is connected to the inverting input terminal of the operational amplifier OP2 via a resistor R23a, and the output terminal of the operational amplifier OP1b is connected to the non-inverting input terminal of the operational amplifier OP2 via a resistor R23b. The inverting input terminal of the operational amplifier OP2 is connected to the output terminal via a resistor R24a, and the non-inverting input terminal of the operational amplifier OP2 is connected to a reference potential point via a resistor R24b. The operational amplifier OP2 and the resistors R23a, R23b, R24a, and R24b form a differential amplifier.

[0037] The differential signal AIN+ is amplified by a non-inverting amplifier formed by an operational amplifier OP1a and is provided to the inverting input terminal of an operational amplifier OP2 that constitutes a differential amplifier. The differential signal AIN- is amplified by a non-inverting amplifier formed by an operational amplifier OP1b and is provided to the non-inverting input terminal of the operational amplifier OP2. The differential signals AIN+ and AIN- are differentially amplified by the operational amplifier OP2, and a single-phase output AOUT corresponding to the difference between the differential signals AIN+ and AIN- is obtained from the output terminal of the operational amplifier OP2. This single-phase output AOUT is provided to the ADC1 terminal of the control circuit 52.

[0038] The voltage of the differential signal AIN+ appearing at the inverting input terminal of the operational amplifier OP1a and the differential signal AIN- appearing at the inverting input terminal of the operational amplifier OP1b is divided by resistors R21a and R21b. By making the resistance values ​​of the resistors R21a and R21b the same, a voltage that is 1 / 2 the sum of the differential signals AIN+ and AIN- appears at node r. This voltage is supplied to the abnormality detection circuit 51.

[0039] 1, the abnormality detection circuit 51 can be configured by, for example, a comparator. A judgment reference voltage Vref is also provided to the abnormality detection circuit 51. The abnormality detection circuit 51 compares the judgment reference voltage Vref with a voltage based on the addition result from the differential to single-phase conversion circuit 50, and outputs an abnormality detection result indicating whether or not an abnormality such as an excessive input has occurred to the ADC2 terminal of the control circuit 52.

[0040] The control circuit 52 is configured by, for example, an MCU. The control circuit 52 obtains values ​​of voltage, current, etc. generated in the detection target from the single-phase output AOUT input to the ADC1 terminal. The control circuit 52 also grasps an abnormality, such as an excessive input, generated in the detection target from the abnormality detection result input to the ADC2 terminal.

[0041] Incidentally, the isolation amplifier 1 converts a signal to be transmitted in the primary circuit 10 into a digital signal, and converts the transmitted digital signal back into an analog signal in the secondary circuit 20, so that filtering by the LPF 23 is required after D / A conversion. However, the filtering by the LPF 23 inherently generates a relatively large predetermined delay time. Due to the signal delay caused by the LPF 23, it takes a relatively long time for the control circuit 52 to recognize an abnormal state such as an excessive input.

[0042] Therefore, in this embodiment, an abnormal input detection output circuit 26 is provided. When an H-level detection signal indicating the occurrence of an abnormal state such as an excessive input is given, the abnormal input detection output circuit 26 changes the output of the LPF 23 at the timing of this detection signal, thereby making it possible to notify the occurrence of the excessive input or the like to the control circuit 52 in a short time.

[0043] (Abnormal input detection output circuit) FIG. 6 is a circuit diagram showing an example of a specific configuration of the LPF 23 and the abnormal input detection output circuit 26. As shown in FIG.

[0044] The LPF 23 has an LPF section 23b that filters the positive input VINP from the 1-bit DAC 22, and an LPF section 23a that filters the negative input VINN from the 1-bit DAC 22. The LPF section 23b is a second-order active filter composed of resistors R1P, R2P, capacitors C1P, C2P, and an operational amplifier 23P. The LPF section 23a is a second-order active filter composed of resistors R1N, R2N, capacitors C1N, C2N, and an operational amplifier 23N.

[0045] The positive input VINP is input to the non-inverting input terminal in+ of the operational amplifier 23P via resistors R1P and R2P. The non-inverting input terminal in+ of the operational amplifier 23P is connected to the ground line (gnd) via a capacitor C1P, and the output terminal is connected to the inverting input terminal in- and is also connected to the connection point of the resistors R1P and R2P via a capacitor C2P. The LPF unit 23b band-limits the high frequency range of the positive input VINP and then outputs the output differential signal VOUT+.

[0046] On the other hand, the negative input VINN is input to the non-inverting input terminal in+ of the operational amplifier 23N via resistors R1N and R2N. The non-inverting input terminal in+ of the operational amplifier 23N is connected to the ground line (gnd) via a capacitor C1N, and the output terminal is connected to the inverting input terminal in- and is also connected to the connection point of the resistors R1N and R2N via a capacitor C2N. The LPF unit 23a band-limits the high frequencies of the negative input VINN and then outputs the output differential signal VOUT-.

[0047] In this embodiment, the non-inverting input terminal in+ of the operational amplifier 23P is connected to a node b of the abnormal input detection output circuit 26, and the non-inverting input terminal in+ of the operational amplifier 23N is connected to a node a of the abnormal input detection output circuit 26. The abnormal input detection output circuit 26 is composed of a constant voltage generating circuit V0, current sources I0 and I1, resistors R3 and R4, and switches S0 and S1.

[0048] The negative terminal of the constant voltage generating circuit V0 is connected to the ground line (gnd), and the positive terminal is connected to node a via a current source I0 and a switch S0. A resistor R3 is connected in parallel to the current path of the current source I0. The positive terminal of the constant voltage generating circuit V0 is also connected to node b via a current source I1 and a switch S1. A resistor R4 is connected in parallel to the current path of the current source I1.

[0049] The abnormal input detection output circuit 26 receives a detection signal from the isolation unit 30 and controls the switches S0 and S1 to turn on and off based on this detection signal. That is, when the detection signal is at an L level indicating no detection of an excessive input or the like, the switches S0 and S1 are both off, and when the detection signal is at an H level indicating detection of an excessive input or the like, the switches S0 and S1 are both on.

[0050] When the switch S0 is on, a voltage Vcm1 determined by the voltage generated by the constant voltage generating circuit V0, the current generated by the current source I0, and the resistance value of the resistor R3 is applied to the node a. This voltage Vcm1 sets the voltage of the non-inverting input terminal in+ of the operational amplifier 23N, and the common-mode level of the output differential signal VOUT- becomes Vcm1.

[0051] Similarly, when the switch S1 is on, a voltage Vcm2 determined by the voltage generated by the constant voltage generating circuit V0, the current generated by the current source I1, and the resistance value of the resistor R4 is applied to the node b. This voltage Vcm2 sets the voltage of the non-inverting input terminal in+ of the operational amplifier 23P, and the common-mode level of the output differential signal VOUT+ becomes Vcm2. In the following description, Vcm1=Vcm2=Vcm.

[0052] The detection signal from the comparator 15 becomes H level immediately after the input differential signal VIN+ or the differential input VIN becomes excessive, and the nodes a and b of the abnormal input detection output circuit 26 change to the voltage Vcm immediately after the input differential signal VIN+ or the differential input VIN becomes excessive. Therefore, before the output differential signals VOUT+ and VOUT- corresponding to the excessive input of the input differential signals VIN+ and VIN- are output from the LPF 23, the common-mode level of the output differential signals VOUT+ and VOUT- from the LPF 23 shifts to Vcm immediately after the input differential signal VIN+ or the differential input VIN becomes excessive. That is, the common-mode level, which was a predetermined level (for example, 0V) during normal operation, changes to Vcm.

[0053] In a normal state where no abnormal state such as excessive input occurs in the output differential signals VOUT+, VOUT-, the sum of the output differential signals VOUT+, VOUT- is at a certain level. In contrast, when an abnormal state such as excessive input occurs in the output differential signals VOUT+, VOUT-, the sum of the output differential signals VOUT+, VOUT- is at a level corresponding to the voltage Vcm. Therefore, it is possible to determine an abnormal state such as excessive input by the sum result of the output differential signals VOUT+, VOUT-.

[0054] (action) Next, the operation of the embodiment configured in this manner will be described with reference to the waveform diagram of Fig. 7. Fig. 7 shows input / output waveforms with time on the horizontal axis and voltage on the vertical axis. In the upper part of Fig. 7, the dashed line indicates the differential input VIN, which is the difference voltage between the input differential signals VIN+ and VIN-, and the solid line indicates the differential output VOUT, which is the difference voltage between the output differential signals VOUT+ and VOUT-. In the middle part of Fig. 7, the solid line indicates the output differential signal VOUT+, and the dashed line indicates the output differential signal VOUT-. In addition, the lower part of Fig. 7 shows the detection result of an abnormality in the control circuit.

[0055] Now, assume that the differential input VIN shown by the dashed line in the upper part of Fig. 7 is input. Note that from here on, the explanation will be given assuming that the input differential signal VIN- is fixed to the ground voltage. The detection level in the upper part of Fig. 7 indicates the judgment level for excessive input, and if the difference voltage VIN between the input differential signal VIN+ and the input differential signal VIN- is higher than the detection level, it is judged that there is an excessive input. In other words, the period during which the differential input VIN is higher than the detection level is the period during which an abnormality has occurred. Note that the detection voltage VREF corresponding to the detection level in Fig. 7 is set by the power supply voltage VDD1 and resistors R1 and R2.

[0056] The input differential signals VIN+, VIN- input to the primary circuit 10 are converted to digital signals by the ΔΣADC 11, encoded by the encoder 12, and then supplied to the isolation unit 30. The isolation unit 30 transmits the output of the encoder 12 to the secondary circuit 20. The decoder 21 of the secondary circuit 20 decodes the input signal and provides it to the 1-bit DAC 22. The 1-bit DAC 22 converts the output of the decoder 21 back to an analog signal and outputs it to the LPF 23. The LPF 23 outputs a differential output VOUT corresponding to the differential input VIN by filtering the high frequencies of the output of the 1-bit DAC 22.

[0057] A delay occurs in the filtering process of the LPF 23. As a result, as shown in the upper part of FIG 7, the differential output VOUT is output with a comparatively long delay with respect to the differential input VIN.

[0058] Now, assume that the differential input VIN goes into an excessive input state (abnormality occurrence period) exceeding the detection level in the upper part of Fig. 7. The comparator 15 outputs an H-level detection signal in a relatively short time after the occurrence of this excessive input. The H-level period of the detection signal is the abnormality detection period by the primary circuit 10. The detection signal is supplied to the abnormal input detection output circuit 26 via the isolation unit 30, and turns on the switches S0 and S1. As a result, the voltage Vcm is applied to the nodes a and b of the abnormal input detection output circuit 26, and the in-phase outputs of the LPF units 23a and 23b become the voltage Vcm.

[0059] The middle part of Figure 7 shows this state, and the common-mode levels of both output differential signals VOUT+, VOUT- rise by the voltage Vcm. When the excessive input of the differential input VIN is eliminated and the differential input VIN falls below the detection level shown in the upper part of Figure 7, the detection signal from the comparator 15 immediately goes to L level. This detection signal is supplied to the abnormal input detection output circuit 26 via the isolation section 30, and the switches S0 and S1 are turned off. As a result, the common-mode outputs of the LPF sections 23a and 23b return to the normal common-mode voltage.

[0060] The output differential signals VOUT+, VOUT- from the LPF 23 are supplied to a downstream differential to single-phase conversion circuit 50. The differential to single-phase conversion circuit 50 obtains an output corresponding to the differential input VIN based on a difference calculation between the output differential signals VOUT+ and VOUT-, and outputs the output to a control circuit 52. This allows the control circuit 52 to grasp the voltage, current, etc. of the detection target from the differential output VOUT.

[0061] Furthermore, the differential to single-phase conversion circuit 50 obtains the sum of the output differential signal VOUT+ and the output differential signal VOUT-, and outputs the sum to the abnormality detection circuit 51. The abnormality detection circuit 51 compares the reference voltage Vref with the voltage based on the addition result from the differential to single-phase conversion circuit 50, and outputs the comparison result. As shown in the lower part of FIG. 7, in the normal state, 1 / 2 of the sum voltage of the output differential signal VOUT+ and the output differential signal VOUT- is a certain voltage (a voltage equivalent to the common-mode voltage in the normal state). In the abnormal state, 1 / 2 of the sum voltage of the output differential signal VOUT+ and the output differential signal VOUT- is a voltage Vcm. That is, the pulse waveform in the lower part of FIG. 7 shows the detection result of the abnormality detection circuit 51, which indicates the period of an abnormal state such as an excessive input (abnormality detection period). The abnormality detection circuit 51 outputs the abnormality detection result to the ADC2 terminal of the control circuit 52. The pulse waveform in the lower part of FIG. 7 shows an abnormality detection period that is slightly delayed from the abnormality occurrence period, and the isolation amplifier 1 is capable of transmitting the occurrence of an abnormality detected by the primary circuit 10 at high speed.

[0062] Moreover, the output differential signal VOUT+ and the output differential signal VOUT- during the abnormality detection period are obtained by adding a known voltage by the abnormal input detection output circuit 26. Therefore, even during the abnormality detection period, the difference between the output differential signal VOUT+ and the output differential signal VOUT- corresponds to the differential input VIN, as shown in the upper part of Fig. 7. That is, in this embodiment, the output differential signals VOUT+ and VOUT- from the LPF 23 can detect an abnormal period such as an excessive input, and can grasp the voltage, current, etc. of the detection target over the entire period including the abnormal period.

[0063] In this manner, in this embodiment, an abnormality in the differential input VIN is detected on the primary side and a detection signal is transmitted to the secondary side. On the secondary side, the in-phase level of the output differential signals VOUT+, VOUT- of the LPF is shifted during the abnormality detection period based on the detection signal. This makes it possible to quickly transmit the occurrence of an abnormality to the downstream control circuit 52 via the output of the LPF without being subject to processing delays of the LPF.

[0064] (Modification) 8 is a circuit diagram showing a modified example. Fig. 8 shows another configuration example of the LPF 23 and the abnormal input detection output circuit 26. This modified example shows a configuration example in which the LPF 23 uses a fully differential circuit.

[0065] 8, a positive input VINP from a 1-bit DAC 22 is provided to a non-inverting input terminal of a fully differential amplifier OPA1 via a resistor R5P. A negative input VINN from the 1-bit DAC 22 is provided to an inverting input terminal of the fully differential amplifier OPA1 via a resistor R5N. A capacitor C3P is connected between the positive output terminal and the non-inverting input terminal of the fully differential amplifier OPA1, and a capacitor C3N is connected between the negative output terminal and the inverting input terminal of the fully differential amplifier OPA1. The fully differential amplifier OPA1, the resistors R5P and R5N, and the capacitors C3P and C3N form an LPF 23.

[0066] The positive input VINP and negative input VINN are filtered by the fully differential amplifier OPA1, and an output differential signal VOUT+ is output from the positive output terminal of the fully differential amplifier OPA1, and an output differential signal VOUT- is output from the negative output terminal.

[0067] Resistors R6P and R6N are connected in series between the positive and negative output terminals of the full differential amplifier OPA1, and the connection point of the resistors R6P and R6N is connected to the inverting input terminal of the operational amplifier OPA2. A voltage generated by a voltage generating circuit 26a is supplied to the non-inverting input terminal of the operational amplifier OPA2. The operational amplifier OPA2 supplies a voltage based on the difference voltage between the two inputs to the full differential amplifier OPA1. The common-mode voltage of the full differential amplifier OPA1 operates to match the output voltage of the operational amplifier OPA2.

[0068] The negative terminal of the constant voltage generating circuit V0 is connected to the ground line (gnd), and the positive terminal is connected to one terminal of the switch SW1. The negative terminal of the constant voltage generating circuit V1 is connected to the positive terminal of the constant voltage generating circuit V0, and the positive terminal is connected to the other terminal of the switch SW1. The constant voltage generating circuits V0 and V1 generate voltages V0 and V1, respectively.

[0069] The common terminal of the switch SW1 is connected to the non-inverting input terminal of the operational amplifier OPA2. The switch SW1 is controlled by a detection signal from the isolation unit 30. In response to a detection signal indicating that no abnormality has occurred, the switch SW1 applies the voltage V0 generated by the constant voltage generation circuit V0 to the non-inverting input terminal of the operational amplifier OPA2, and in response to a detection signal indicating that an abnormality has occurred, the switch SW1 applies the sum voltage (V0+V1) of the voltages generated by the constant voltage generation circuits V0 and V1 to the non-inverting input terminal of the operational amplifier OPA2.

[0070] 8 is a fully differential circuit, the common-mode voltage of the fully differential amplifier OPA1 is controlled by a detection signal in order to change the output differential signals VOUT+, VOUT- of the LPF 23. Under normal conditions, the output of the operational amplifier OPA2 is fed back to the fully differential amplifier OPA1 so that the voltage at the connection point of the resistors R6P, R6N coincides with the voltage V0.

[0071] Under normal circumstances, the switch SW1 supplies the voltage V0 generated by the constant voltage generation circuit V0 in response to the detection signal to the non-inverting input terminal of the operational amplifier OPA2. As a result, the common-mode voltage of the fully differential amplifier OPA1 becomes V0. When an abnormality such as excessive input occurs and the detection signal becomes H level, the switch SW1 supplies the sum voltage (V0+V1) of the voltages generated by the constant voltage generation circuits V0 and V1 to the non-inverting input terminal of the operational amplifier OPA2. As a result, the common-mode voltage of the fully differential amplifier OPA1 becomes (V0+V1), increasing the output differential signals VOUT+, VOUT- by V1.

[0072] Thus, even when the circuit of FIG. 8 is employed, the same effects as those of the first embodiment can be obtained.

[0073] Second embodiment Fig. 9 is a block diagram showing a second embodiment of the present invention. In Fig. 9, the same components as those in Fig. 1 are given the same reference numerals and their description will be omitted.

[0074] The isolation amplifier 2 of this embodiment quickly notifies the occurrence of an abnormality to a control circuit 52 in the downstream stage by modifying the output of the LPF 23 based on a detection signal transmitted from the primary circuit 10 to the secondary circuit 20 in the downstream stage of the LPF 23. Note that in this embodiment, the differential to single-phase conversion circuit 50 and the control circuit 52 are not shown. Also, in this embodiment, an arithmetic circuit 29 is adopted instead of the abnormality detection circuit 51 as shown in FIG.

[0075] 1 in that the secondary circuit 28 of the present embodiment employs an abnormal input detection output circuit 27 instead of the abnormal input detection output circuit 26. The abnormal input detection output circuit 27 receives the output of the LPF 23 and outputs output differential signals VOUT+, VOUT-. The abnormal input detection output circuit 27 also receives a detection signal indicating the detection result of an abnormality such as an excessive input from the primary circuit 10 via the isolation unit 30. When the detection signal indicates the occurrence of an abnormality, the abnormal input detection output circuit 27 generates an output for notifying the occurrence of the abnormality instead of the differential output VOUT.

[0076] Fig. 10 is a circuit diagram showing an example of a specific configuration of the abnormal input detection output circuit 27 of Fig. 9. Fig. 10 shows only a part of the configuration of the secondary circuit 28 in Fig. 9.

[0077] 10, the abnormal input detection output circuit 27 is composed of two switches S2 and S3 controlled by a detection signal. The output differential signal VOUT+ is input from the LPF 23 to one input terminal of the switch S2, and an internal clock (internal CK) is input to the other input terminal. The output differential signal VOUT- is input from the LPF 23 to one input terminal of the switch S3, and an internal clock (internal CK) is input to the other input terminal. The internal CK is a recovered clock recovered by the clock recovery circuit 24.

[0078] When the detection signal is at an L level indicating that an abnormality has occurred, the switches S2 and S3 select and output the output differential signal VOUT+ or VOUT- of the LPF 23. On the other hand, when the detection signal is at an H level indicating that an abnormality has occurred, the switches S2 and S3 select and output the internal CK.

[0079] The output differential signals VOUT+, VOUT- input to one input terminal of each of the switches S2, S3 are differential signals, whereas the internal CK input to the other input terminal of each of the switches S2, S3 is an in-phase signal. Therefore, in the circuit subsequent to the secondary circuit 28, by providing the output of the abnormal input detection output circuit 27 to an arithmetic circuit 29 such as an AND circuit or an EXOR circuit, it is possible to determine which input terminal of the switches S2, S3 has been selected and which signal has been output.

[0080] Next, the operation of the embodiment configured as above will be described with reference to the waveform diagram of Fig. 11. Fig. 11 shows waveforms of input / output, etc., with time on the horizontal axis and voltage on the vertical axis. In Fig. 11, similar to Fig. 7, the upper part shows the differential input VIN, which is the difference voltage between the input differential signals VIN+ and VIN-, the solid line shows the differential output VOUT, which is the difference voltage between the output differential signals VOUT+ and VOUT-, the middle part shows the output differential signal VOUT+, the dashed line shows the output differential signal VOUT-, and the lower part shows the abnormality detection result input to the control circuit 52.

[0081] The operation from when a signal (VIN+, VIN-) corresponding to the input differential signals VIN+, VIN- is input to the 1-bit DAC 22 and an analog signal is output from the 1-bit DAC 22 is the same as in the first embodiment. Also, the operation from when a detection signal indicating the occurrence of an abnormality is output from the comparator 15 and transmitted to the secondary circuit 28 via the isolation unit 30 is the same as in the first embodiment.

[0082] In this embodiment, the LPF 23 filters the high frequencies of the input signal and outputs the filtered output differential signals VOUT+, VOUT-. In the upper part of Fig. 11, the solid line indicates the difference VOUT between the output differential signal VOUT+ and the output differential signal VOUT- in this case, and the dashed line indicates the difference VIN between the input differential signal VIN+ and the input differential signal VIN-. Note that the dotted waveform shown connecting the curved portions of the differential output VOUT from the abnormal input detection output circuit 27 in Fig. 11 is the output of the LPF 23 (<internal signal (LPF)>), and has the same waveform as the waveform of the differential output VOUT during periods other than the period corresponding to the abnormality occurrence period.

[0083] 11, the detection signal input to the abnormal input detection output circuit 27 is at L level. In this case, the switches S2 and S3 of the abnormal input detection output circuit 27 select and output the output differential signals VOUT+ and VOUT- from the LPF 23.

[0084] Here, it is assumed that the differential input VIN goes into an excessive input state (abnormality occurrence period) exceeding the detection level in the upper part of Fig. 11. The comparator 15 outputs a detection signal indicating the abnormality detection period by an H level in a relatively short time after the occurrence of this excessive input. The detection signal is supplied to the abnormal input detection output circuit 27 via the isolation unit 30, and causes the switches S2 and S3 to select the internal CK. As a result, the output of the abnormal input detection output circuit 27 becomes the clock CK, as shown in the abnormality detection period in the middle part of Fig. 11.

[0085] When the differential input VIN becomes lower than the detection level in the upper part of FIG. 11, the detection signal becomes L level, and the switches S2 and S3 again output the output differential signals VOUT+, VOUT- from the LPF 23 as is (middle part of FIG. 11).

[0086] As shown in the upper part of FIG. 11, the difference between the output differential signal VOUT+ and the output differential signal VOUT- is 0V during the abnormality detection period, and the abnormality detection period can be determined by calculating the output differential signals VOUT+ and VOUT- instead of the difference between the output differential signals. The lower part of FIG. 11 shows 1 / 2 the sum of the output differential signal VOUT+ and the output differential signal VOUT- from the abnormal input detection output circuit 27. As shown in FIG. 11, in the normal state, the sum voltage of the output differential signal VOUT+ and the output differential signal VOUT- is a certain voltage (normal in-phase voltage). In the abnormal state, 1 / 2 the sum voltage of the output differential signal VOUT+ and the output differential signal VOUT- becomes a pulse waveform synchronized with the internal CK. The period of this pulse waveform indicates the period of an abnormal state such as an excessive input (abnormality detection period). The period of the pulse waveform in the lower part of FIG. 11 indicates the abnormality detection period that is slightly delayed from the abnormality occurrence period, and the isolation amplifier 2 can quickly transmit the occurrence of an abnormality detected by the primary circuit 10.

[0087] In this manner, in the present embodiment as well, as in the first embodiment, an abnormality in the differential input VIN is detected on the primary side and a detection signal is transmitted to the secondary side. On the secondary side, based on the detection signal, the output differential signals VOUT+, VOUT- of the LPF are converted to in-phase signals during the abnormality detection period. This makes it possible to transmit the occurrence of an abnormality to a downstream control circuit at high speed by the output of the LPF without being subject to processing delays of the LPF.

[0088] (Third embodiment) Fig. 12 is a block diagram showing a third embodiment of the present invention. In Fig. 12, the same components as those in Fig. 1 are given the same reference numerals and their explanations are omitted.

[0089] In the above first and second embodiments, an example has been described in which the isolation amplifier outputs an analog signal as the differential output VOUT. This embodiment shows an example in which digital data is output from the isolation amplifier. Note that even in this case, low-pass filter processing is required in the circuit downstream of the isolation amplifier, and signal delays occur due to the low-pass filter in a normal signal transmission path.

[0090] 12, the configurations of the primary circuit 10 and the isolation unit 30 of the isolation amplifier 3 are the same as those in Fig. 1. In this embodiment, a decoder 61 of a secondary circuit 60 decodes the differential signal transferred from the isolation unit 30 to generate output data DTI corresponding to the differential input VIN, and also generates a clock CKI recovered in a clock recovery circuit 24.

[0091] In this embodiment, an example will be described in which the clock CKI recovered by the clock recovery circuit 24 in the isolation amplifier 3 is used for data transmission. However, an externally acquired clock may be used as the clock CKI.

[0092] In this embodiment, the output data DTI and the clock CKI from the decoder 61 are not directly output as the output of the isolation amplifier 3, but are provided to a mixer 62. A detection signal from the comparator 15 is provided as a detection signal FLTN via the isolation unit 30 to the mixer 62, which serves as an abnormal input detection output circuit. The decoder 61 and the mixer 62 form an output circuit.

[0093] In this embodiment, the mixer 62, as described later, is adapted to forcibly change the logic of the output data DTI by the detection signal FLTN at H level, thereby transmitting the abnormality occurrence period to the downstream circuit. The downstream circuit detects this forcible change, thereby grasping the abnormality occurrence period. The mixer 62 outputs the output data DTO obtained by changing the output data DTI in response to the detection signal FLTN, and also outputs the clock CKI as it is as the clock CKO. The clock CKO and the output data DTO are output as the clock MCLK and the output data MDAT from the isolation amplifier 3 via buffers 63 and 64, respectively.

[0094] The clock MCLK and output data MDAT from the isolation amplifier 3 are provided to the FPGA 70. The FPGA 70 is composed of a latch 71, an LPF 72, and an MCU interface (I / F) 73. In the following description, the latch may refer to a D-type flip-flop. The clock MCLK is supplied to the latch 71 and the LPF 72 via a clock terminal CLK of the FPGA 70. The output data MDAT is input to the latch 71 via a data terminal DAT of the FPGA 70. The latch 71 takes in the data MDAT in synchronization with the rising edge of the clock MCLK and outputs it to the LPF 72. The LPF 72 uses the clock MCLK to perform a filtering process to limit the high frequency of the data, and outputs the filtered data to the MCUI / F 73. The MCUI / F 73 outputs the data from the LPF 72 to the DIF terminal of the control circuit 90 via the output terminal DIF. The control circuit 90 is composed of, for example, an MCU, takes in the output data from the LPF 72, and restores the data corresponding to the differential input VIN.

[0095] In this embodiment, the clock MCLK and output data MDAT from the isolation amplifier 3 are also supplied to an external circuit 80. The external circuit 80 uses the clock MCLK and the output data MDAT to obtain a detection result FAULTN indicating an abnormality detection period. The external circuit 80 outputs the detection result FAULTN to an interrupt (INT) terminal of a control circuit 90. The control circuit 90 is configured to grasp the period during which an abnormality has occurred based on the detection result FAULTN input to the INT terminal.

[0096] FIG. 13 is a circuit diagram showing an example of a specific configuration of the mixer 62 and the external circuit 80 in FIG.

[0097] 13, the mixer 62 is composed of a rising edge detector DT1, an inverter IN1, latches L1 and L2, and an AND circuit A1. The external circuit 80 is composed of a latch 81. The clock CKI from the decoder 61 is supplied to the latch L1, the rising edge detector DT1, and the inverter IN1, and is also supplied to the buffer 63. The output data DTI from the decoder 61 is supplied to the latch L2. The detection signal FLTN from the isolation unit 30 is supplied to the latch L1.

[0098] The rising edge detector DT1 detects the rising edge of the clock CKI and provides a rising edge detection pulse to one input terminal of the AND circuit A1. The inverter IN1 inverts the clock CKI and provides it to the clock terminal of the latch L2. The latch L1 takes in the detection signal FLTN by the clock CKI and provides it to the other input terminal of the AND circuit A1. The AND circuit A1 provides the result of the AND operation of the two inputs to the S terminal of the latch L2. During the period when the L level is supplied to the S terminal, the latch L2 takes in and outputs the output data DTI at the timing of the falling edge of the clock CKI from the inverter IN1. Furthermore, during the period when the H level is supplied to the S terminal, the latch L2 outputs an H level. The output of the latch L2 becomes the output (output data MDAT) of the isolation amplifier 3 via the buffer 64.

[0099] Since the latch L2 captures and outputs the output data DTI at the falling edge of the clock CKI, the output data MDAT is data whose logic changes while the clock MCLK is at the L level. Also, the clock MCLK is at the H level at the rising edge of the clock CKI immediately after the detection signal FLTN changes to the H level.

[0100] The latch 81 of the external circuit 80 has a data end supplied with the clock MCLK and a clock end supplied with the output data MDAT. That is, the latch 81 takes in and outputs the clock MCLK at the rising edge of the output data MDAT.

[0101] Next, the operation of the embodiment configured in this manner will be described with reference to Fig. 14. Fig. 14 is a timing chart for explaining the operation of the third embodiment.

[0102] A decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with the clock CKI. CKI and DTI in Fig. 14 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 62 and buffers 63 and 64.

[0103] Assume now that the system is in a normal state in which no abnormality such as excessive input has occurred. In this case, the detection signal FLTN is at L level, and the outputs of the latch L1 and AND circuit A1 in the mixer 62 are at L level. Therefore, the latch L2 captures and outputs the output data DTI in synchronization with the falling edge of the clock CKI. In this way, the output data MDAT, which is the same as the output data DTI, is output in synchronization with the clock MCLK. The output data MDAT is switched during the L level period of the clock MCLK.

[0104] Next, assume that an abnormality such as an excessive input occurs, and the detection signal FLTN changes to H level. FLTN in Fig. 14 shows this state. In this embodiment, in order to transmit the abnormality detection result to the control circuit 90 at high speed, the mixer 62 superimposes information on the abnormality detection result on the output data MDAT. In this case, the information on the abnormality detection result is superimposed by utilizing a part of the data period of one clock so that the logic of the output data MDAT can be determined in the subsequent circuit.

[0105] That is, the rising edge detector DT1 detects the rising edge of the clock CKI to determine the superimposition timing, and outputs a rising edge detection pulse (DT1 output in FIG. 14). The latch L1 latches the detection signal FLTN at the timing of the clock CKI and outputs it (L1 output in FIG. 14). The AND circuit A1 performs an AND operation on the rising edge detection pulse and the output of the latch L1. The A1 output in FIG. 14 indicates the result of the AND operation, and the AND circuit A1 outputs a pulse that is generated in synchronization with the rising timing of the clock CKI during the H level period of the detection signal FLTN.

[0106] The latch L2 forcibly changes the level of the output data DTI to H level in synchronization with the rising edge of the output pulse of the AND circuit A1. The output of the latch L2 becomes the output data DTO from the mixer 62. The clock CKI becomes the clock CKO from the mixer 62 as is. The clock CKO and the output data DTO are delayed by the buffers 63 and 64, and then output to the FPGA 70 as the clock MCLK and the output data MDAT. MCLK and MDAT in FIG. 14 indicate these outputs.

[0107] 14 indicates that the output data MDAT is forced to H level at the timing of the output pulse of the AND circuit A1. Even if the output data DTI is L level at the timing of the output pulse of the AND circuit A1, the output data MDAT changes to H level at the timing of the output pulse of the AND circuit A1. The example of FIG. 14 indicates that the data D1, D2, and D3 of the data D0, D1, ... are forced to change to H level.

[0108] The clock MCLK and output data MDAT from the isolation amplifier 3 are supplied to a latch 81 of an external circuit 80. The latch 81 takes in the clock MCLK at the rising edge of the output data MDAT and outputs it as a detection result FAULTN. If a forced level change is not performed, the data value of the output data MDAT switches during the L level period of the clock MCLK. In contrast, by forcibly changing the level to H level midway through the data, it becomes possible to latch the H level of the clock at the rising edge timing of the output data MDAT. In this way, the detection result FAULTN shown in FAULTN in FIG. 14 can be obtained.

[0109] 14 indicates that the detection result FAULTN depends on the output data MDAT. For example, if the data D1 is originally at L level, the data D1 is forcibly changed to H level at the timing of the output pulse of the AND circuit A1. In this case, the H level of the clock MCLK is captured at the rising edge of the data D1. That is, the detection result FAULTN changes to H level at the timing when the data D1 is input to the external circuit 80.

[0110] However, when the data D1 is originally at H level, the data D1 does not rise at the timing of the output pulse of the AND circuit A1, so the detection result FAULTN from the latch 81 remains at L level. That is, the broken line of FAULTN indicates that the detection result FAULTN may change to H level at any timing of the data D1, D2, or D3. Similarly, when the detection signal FLTN becomes L level, the detection result FAULTN takes in and outputs the L level of the clock MCLK at any timing when the data D4, D5, ... rise. For example, if the original data D1 and D4 are L level and the original data D3 is H level, the detection result FAULTN becomes H level at the timing when the data D1 is input to the latch 81, and becomes L level at the timing when the data D4 is input to the latch 81.

[0111] The control circuit 90 determines the high level period of the detection result FAULTN as an abnormality detection result. Furthermore, at the rising timing of the clock MCLK, the information of the data D0, D1, ... maintains the original information, and the control circuit 90 can reliably obtain data corresponding to the differential input VIN.

[0112] In this embodiment, a detection signal indicating the occurrence of an abnormality is acquired in the primary circuit 10 and transmitted to the secondary circuit 60. The secondary circuit 60 uses the transmitted detection signal to superimpose information indicating the period during which the abnormality was detected on the digital data, and extracts the superimposed information without filtering. This makes it possible to transmit the abnormality detection result to a downstream circuit at high speed.

[0113] (Fourth embodiment) Fig. 15 is a block diagram showing an example of a specific configuration of a mixer employed in the fourth embodiment of the present invention. In Fig. 15, the same components as those in Fig. 13 are given the same reference numerals and their description will be omitted. Note that the isolation amplifier 4 of this embodiment differs from Fig. 12 only in that a mixer 100 is employed instead of the mixer 62, and description of the configuration other than the mixer 100 will be omitted.

[0114] In the third embodiment, the detection result FAULTN may not be obtained depending on the logic level of the transmitted output data MDAT. Therefore, in this embodiment, the data at the rising and falling timings of the detection signal FLTN are forcibly rewritten, thereby making it possible to reliably obtain the detection result FAULTN.

[0115] 15, the clock CKI is supplied to inverters IN2 and IN3 and a rising edge detector DT1 constituting the mixer 100, and is also supplied directly to a buffer 63. The output data DTI is supplied to a selector SE1. The detection signal FLTN is supplied to an inverter IN4, an AND circuit A2, and a latch L3.

[0116] The inverter IN2 inverts the clock CKI and provides it to the latch L3. The latch L3 takes in the detection signal FLTN in synchronization with the falling edge of the clock CKI and outputs it to the latch L4 and the AND circuit A4, and also inverts the taken-in detection signal FLTN and provides it to the AND circuit A2. The AND circuit A2 outputs the result of the AND operation of the two inputs to the OR circuit OR1. The latch L4 takes in the output of the latch L3 in synchronization with the falling edge of the clock CKI and outputs it to the AND circuit A3, and also inverts the taken-in output of the latch L3 and outputs it to the AND circuit A4.

[0117] The AND circuit A3 outputs the result of the AND operation of the two inputs to the AND circuit A5 and the OR circuit OR1. The OR circuit OR1 outputs the result of the OR operation of the two inputs as a selection signal to the selector SE1. The detection signal FLTN is inverted by the inverter IN4 and input to the selector SE1, and the selector SE1 selects either the output data DTI or an inverted signal of the detection signal FLTN according to the selection signal from the OR circuit OR1 and outputs the selected signal to the latch L5.

[0118] The AND circuit A5 outputs the AND operation result of the output of the rise detector DT1 and the output of the AND circuit A3 to the R terminal of the latch L5. The AND circuit A6 outputs the AND operation result of the output of the rise detector DT1 and the output of the AND circuit A4 to the S terminal of the latch L5. The latch L5 takes in and outputs the output of the selector SE1 in synchronization with the falling edge of the clock CKI from the inverter IN3, and outputs an H level according to the H level output of the AND circuit A5 and an L level according to the H level output of the AND circuit A6. The output of the latch L5 becomes the output (output data MDAT) of the isolation amplifier 4 via the buffer 64.

[0119] Next, the operation of the embodiment configured as above will be described with reference to Fig. 16. Fig. 16 is a timing chart for explaining the operation of the fourth embodiment.

[0120] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with the clock CKI. CKI and DTI in Fig. 16 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 100 and buffers 63 and 64.

[0121] Assume now that the normal state is not occurring with an abnormality such as an excessive input. In this case, the detection signal FLTN is at L level. Therefore, the outputs of the latches L3, L4, the AND circuits A2 to A6, and the OR circuit OR1 in the mixer 100 are all at L level. As a result, the selector SE1 selects the output data DTI and outputs it to the latch L5. The latch L5 outputs the output of the selector SE1 to the buffer 64 in synchronization with the falling edge of the clock CKI. Thus, in this case, the clock MCLK and the output data MDAT correspond to the clock CKI and the output data DTI, respectively. Note that, in this embodiment as well, the data value of the output data MDAT changes during the L level period of the clock MCLK.

[0122] Next, it is assumed that an abnormality such as an excessive input occurs and the detection signal FLTN changes to H level. FLTN in Fig. 16 shows this state. In this embodiment, when the detection signal FLTN changes to H level, the mixer 100 forcibly sets the output data MDAT to H level during the H level period of the clock MCLK, as in the first embodiment. Furthermore, in this embodiment, when the detection signal FLTN changes to H level, the mixer 100 forcibly sets the output data to L level at a timing corresponding to the timing of this change, and when the detection signal FLTN changes to L level, the mixer 100 forcibly sets the output data to H level at a timing corresponding to this change.

[0123] That is, the latch L3 captures and outputs the detection signal FLTN in synchronization with the falling edge of the clock CKI (L3 output in FIG. 16). The AND circuit A2 outputs to the OR circuit OR1 a pulse (A2 output in FIG. 16) that is at H level during the period from the rising edge of the detection signal FLTN to the falling edge of the clock CKI by ANDing the inverted signal of the output of the latch L3 and the detection signal FLTN.

[0124] Latch L4 outputs the output of latch L3 delayed by one clock to AND circuit A3, and inverts the output and outputs it to AND circuit A4. The output of AND circuit A4 is at H level for one clock period from the falling edge of clock CKI after detection signal FLTN becomes H level (A4 output in FIG. 16). Also, the output of AND circuit A3 is at H level for one clock period from the falling edge of clock CKI after detection signal FLTN becomes L level (A3 output in FIG. 16).

[0125] The OR circuit OR1 performs an OR operation on the output of the AND circuit A2 and the output of the AND circuit A3, and outputs a pulse that is at H level during the period when the two inputs are at H level (OR1 output in FIG. 16). The selector SE1 selects and outputs the output data DTI during the L level period of the selection signal from the OR circuit OR1, and selects and outputs the inverted signal of the detection signal FLTN during the H level period of the selection signal. That is, the output of the selector SE1 during the H level period of the selection signal is at L level immediately after the rise of the detection signal FLTN, and is at H level immediately after the fall of the detection signal FLTN.

[0126] The rising edge detector DT1 detects the rising edge of the clock CKI and outputs a rising edge detection pulse (DT1 output in FIG. 16). The AND circuit A6 outputs the result of an AND operation between the rising edge detection pulse from the rising edge detector DT1 and the output of the AND circuit A4 to the S terminal of the latch L5 (A6 output in FIG. 16). That is, the output of the AND circuit A6 is a rising edge detection pulse generated during the H level period of the output of the AND circuit A4, which becomes H level after the detection signal FLTN rises.

[0127] Moreover, the AND circuit A5 outputs the AND operation result of the output of the rising edge detector DT1 and the output of the AND circuit A3 (A5 output in FIG. 16). That is, the output of the AND circuit A5 is a rising edge detection pulse generated during the H level period of the output of the AND circuit A3 which becomes H level after the detection signal FLTN falls.

[0128] The latch L5 selects and outputs the output of the selector SE1 (output data DTI) during a period when the outputs of the AND circuits A5 and A6 are both at L level. The latch L5 also outputs H level in response to a rising edge detection pulse supplied to the R terminal from the AND circuit A5, and outputs L level in response to a rising edge detection pulse supplied to the S terminal from the AND circuit A6.

[0129] As a result, as shown in Fig. 16, of the data D0, D1, ... of the output data MDAT, the data D2 is forced to the L level and the data D6 is forced to the H level. The clock MCLK and the output data MDAT are supplied to the FPGA 70. Due to the forced level change by the mixer 100, the output data MDAT processed in the FPGA 70 has lost the values ​​of the data D2 and D6, as shown in the FPGA in Fig. 16.

[0130] A latch 81 of an external circuit 80 takes in a clock MCLK at the rising edge of the output data MDAT and outputs it as a detection result FAULTN. As shown in Fig. 16, the detection result FAULTN goes to H level at the timing of a rising edge detection pulse after the detection signal FLTN goes to H level, and goes to L level at the timing of a rising edge detection pulse after the detection signal FLTN goes to L level.

[0131] In this way, the abnormality detection result can be transmitted to the control circuit 90 at high speed by the detection result FAULTN.

[0132] In this manner, the present embodiment can also provide the same effects as those of the third embodiment. In the present embodiment, the data value is forcibly changed at the timing when the detection signal FLTN changes, so that the detection result FAULTN indicating the abnormality detection result can be reliably obtained.

[0133] Fifth embodiment Fig. 17 is a block diagram showing an example of a specific configuration of a mixer employed in the fifth embodiment of the present invention. In Fig. 17, the same components as those in Fig. 13 are given the same reference numerals and their description will be omitted. Note that the isolation amplifier 5 of this embodiment differs from Fig. 12 only in that a mixer 110 is employed instead of the mixer 62, and description of the configuration other than the mixer 110 will be omitted.

[0134] In the fourth embodiment, the output data MDAT was forcibly changed to an L or H level, which resulted in data loss. This embodiment is intended to prevent this data loss. To achieve this, the mixer 110 of this embodiment changes the latter half of the data to an L level and then to an H level during the H level period of the clock MCLK at the rising edge of the detection signal FLTN. Also, the mixer 110 changes the latter half of the data to an L level and then to an H level during the L level period of the clock MCLK at the falling edge of the detection signal FLTN.

[0135] 17, the clock CKI is supplied to inverters IN5, IN6, and IN7 constituting a mixer 110, and is also supplied directly to a buffer 63. The output data DTI is supplied to a latch L6. The detection signal FLTN is supplied to a latch L7.

[0136] The inverters IN5 to IN7 invert the clock CKI and provide it to the latches L8, L6, and L9, respectively. The latch L6 takes in the output data DTI in synchronization with the falling edge of the clock CKI and outputs it to the selector SE2. The latch L7 takes in the detection signal FLTN in synchronization with the clock CKI and outputs it to the latch L8 and the AND circuit A7, and also outputs an inverted signal of the detection signal FLTN to the AND circuit A8. The latch L8 takes in the output of the latch L7 in synchronization with the falling edge of the clock CKI and outputs it to a delay circuit (delay) DE1. The delay circuit DE1 delays the output of the latch L8 and provides a delayed output to the AND circuit A8, and also inverts the delayed output and outputs it to the AND circuit A7.

[0137] The AND circuit A7 outputs the AND operation result of the two inputs as a selection signal to the selector SE2, and also outputs the AND operation result to the delay circuit DE2. The delay circuit DE2 delays the output of the AND circuit A7 and then outputs it to the selector SE2. The selector SE2 selects either the output of the latch L6 or the output of the delay circuit DE2 based on the selection signal from the AND circuit A7, and outputs it to the selector SE3.

[0138] The AND circuit A8 outputs the AND operation result of the two inputs as a selection signal to the selector SE3 and also outputs the AND operation result to the latch L9. The latch L9 captures the output of the AND circuit A8 in synchronization with the falling edge of the clock CKI and outputs it to the selector SE3. The selector SE3 selects the output of the selector SE2 or the output of the latch L9 based on the selection signal from the AND circuit A8 and outputs it to the buffer 64.

[0139] Next, the operation of the embodiment configured as above will be described with reference to Fig. 18. Fig. 18 is a timing chart for explaining the operation of the fifth embodiment.

[0140] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with the clock CKI. CKI and DTI in Fig. 18 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 110 and buffers 63 and 64.

[0141] Assume now that the system is in a normal state in which no abnormality such as excessive input occurs. In this case, the detection signal FLTN is at L level. Therefore, the outputs of the latches L7, L8, and L9, the AND circuits A7 and A8, and the delay circuits DE1 and DE2 in the mixer 110 are all at L level. As a result, the selector SE2 selects the output of the latch L6, and the selector SE3 selects the output of the selector SE2. In this way, the output data DTI is supplied to the buffer 64 via the latch L6 and the selectors SE2 and SE3, and the output data MDAT corresponding to the output data DTI is output from the buffer 64 in synchronization with the clock MCLK.

[0142] Next, it is assumed that an abnormality such as an excessive input occurs and the detection signal FLTN changes to H level. FLTN in FIG. 18 shows this state. In this embodiment, when the detection signal FLTN changes to H level, the mixer 110 forcibly sets the output data MDAT to H level during the H level period of the clock MCLK, as in the first embodiment. Furthermore, in this embodiment, when the detection signal FLTN changes to H level, the mixer 110 forcibly sets the output data to L level and then to H level during the H level period of the clock MCLK in response to this change timing, and when the detection signal FLTN changes to L level, the mixer 110 forcibly sets the output data to L level and then to H level in response to this change timing and during the L level period of the clock MCLK.

[0143] That is, the latch L7 captures the detection signal FLTN in synchronization with the rising edge of the clock CKI and outputs it to the latch L8 (L7 output in FIG. 18). The latch L8 captures the detection signal FLTN from the latch L7 at the falling edge of the clock CKI and outputs it to the delay circuit DE1. The delay circuit DE1 delays and outputs the detection signal FLTN from the latch L8 (DE1 output in FIG. 18). That is, the output of the delay circuit DE1 becomes H level a predetermined period after the first falling edge of the clock CKI after the rising edge of the detection signal FLTN.

[0144] The AND circuit A7 outputs the result of AND operation between the inverted signal of the output of the delay circuit DE1 and the output of the latch L7. As shown in the A7 output in Fig. 18, the output of the AND circuit A7 becomes a pulse that is at H level for a predetermined period (a width of more than half a clock period in Fig. 18) from the first falling edge of the clock CKI after the rising edge of the detection signal FLTN.

[0145] The delay circuit DE2 provides the selector SE2 with an output (DE2 output in FIG. 18) that is a delayed version of the output of the AND circuit A7. The delay time of the delay circuit DE2 is set to a time longer than the period required for sampling the output data DTI from the rising edge of the clock CKI and shorter than a half clock period (the period during which the clock CKI is at H level). Therefore, during the period during which the output of the AND circuit A7 is at H level, the output of the selector SE2 is at L level immediately after the output of the AND circuit A7 becomes H level, and becomes H level after the delay time of the delay circuit DE2 has elapsed after the output of the AND circuit A7 becomes H level.

[0146] The AND circuit A8 outputs the result of AND operation between the inverted signal of the output of the latch L7 and the output of the delay circuit DE1 to the latch L9 and the selector SE2. As shown in the A8 output in Fig. 18, the output of the AND circuit A8 becomes a pulse that is at H level for a predetermined period (a width of more than half a clock period in Fig. 18) from the first falling edge of the clock CKI after the falling edge of the detection signal FLTN.

[0147] The latch L9 captures the output of the AND circuit A8 in synchronization with the falling edge of the clock CKI and provides it to the selector SE3 (L9 output in FIG. 18). The selector SE3 selects the output of the selector SE2 during the L level period of the output of the AND circuit A8, and selects the output of the latch L9 during the H level period. Therefore, when the output of the AND circuit A8 becomes H level, the output of the selector SE3 is L level immediately after the output of the AND circuit A8 becomes H level, and becomes H level at the falling timing of the next clock CKI after the output of the AND circuit A8 becomes H level. The output of the selector SE3 is output from the isolation amplifier 5 as the output data MDAT via the buffer 64.

[0148] 18, at the timing of data D2 of the output data MDAT corresponding to the rising edge of the detection signal FLTN, data D2 is forced to go to L level halfway through and is returned to H level during the H level period of the clock MCLK. Also, at the timing of data D5 of the output data MDAT corresponding to the falling edge of the detection signal FLTN, data D5 is forced to go to L level halfway through and is returned to H level during the L level period of the clock MCLK.

[0149] The clock MCLK and the output data MDAT are supplied to the FPGA 70. The latch 81 of the external circuit 80 takes in the clock MCLK at the rising edge of the output data MDAT and outputs it as the detection result FAULTN. As shown in Fig. 18, the detection result FAULTN becomes H level about one clock after the detection signal FLTN becomes H level, and becomes L level about one and a half clocks after the detection signal FLTN becomes L level.

[0150] In this way, the detection result FAULTN can be used to quickly transmit the abnormality detection result to the control circuit 90. Even if the mixer 110 forcibly changes the level, the output data MDAT processed in the FPGA 70 does not lose data, as shown in the FPGA of FIG.

[0151] In this manner, the present embodiment can also provide the same effects as those of the third embodiment. In the present embodiment, the data level is forcibly changed at the timing of change of the detection signal FLTN while the data value is maintained, so that the detection result FAULTN indicating the abnormality detection result can be reliably obtained without losing data.

[0152] Sixth embodiment Fig. 19 is a block diagram showing an example of a specific configuration of a mixer employed in the sixth embodiment of the present invention. In Fig. 19, the same components as those in Fig. 13 are given the same reference numerals and will not be described. The isolation amplifier 6 of this embodiment differs from that of Fig. 12 only in that a mixer 120 is employed instead of the mixer 62, and descriptions of the configuration other than the mixer 120 will be omitted. In this embodiment, an FPGA 75 capable of processing at double data rate is employed instead of the FPGA 70. In this embodiment, an external circuit 82 is employed instead of the external circuit 80 of Fig. 12.

[0153] This embodiment utilizes a double data rate system that transmits data on both edges of the clock, so that under normal circumstances, data and an L level are transmitted in one clock, and under abnormal circumstances such as excessive input, data and an H level are transmitted in one clock.

[0154] 19, the clock CKI is supplied to the inverter IN8, selector SE4, and two-edge detector DT2 that constitute the mixer 120, and is also supplied directly to the buffer 63. The output data DTI is supplied to the selector SE4. The detection signal FLTN is supplied to the latch L10. The inverter IN8 inverts the clock CKI and supplies it to the latch L10. The latch L10 takes in the output data DTI in synchronization with the falling edge timing of the clock CKI and outputs it to the selector SE4.

[0155] The selector SE4 selects and outputs the output data DTI according to the H level of the clock CKI, and selects and outputs the detection signal FLTN from the latch L10 according to the L level of the clock CKI. The edge detector DT2 detects the rising and falling edges of the clock CKI and outputs an edge detection pulse to the latch L11. The latch L11 takes in the output of the selector SE4 at the timing of the edge detection pulse and outputs it to the buffer 64.

[0156] Therefore, output data DTI is output from latch L11 in synchronization with the rising edge of clock CKI, and detection signal FLTN is output in synchronization with the falling edge of clock CKI. Note that the output of latch L11 is an L level output in synchronization with the falling edge of clock CKI during an L level period of detection signal FLTN when no abnormality such as excessive input occurs, and an H level output in synchronization with the falling edge of clock CKI during an H level period of detection signal FLTN when an abnormality such as excessive input occurs.

[0157] The clock MCLK and output data MDAT from the isolation amplifier 6 are supplied to the FPGA 75. The FPGA 75 has the same configuration as the FPGA 70 in FIG. 12 except that it can handle double data rate signals. The FPGA 75 samples the output data MDAT in synchronization with the rising edge of the clock MCLK to obtain data corresponding to the differential input VIN. The FPGA 75 performs low-pass filtering and other processing on the captured data, and then outputs the data to the control circuit 90.

[0158] In this embodiment, the external circuit 82 is composed of inverters 83 to 85 and a latch 81. The inverter 83 inverts the output data MDAT and provides it to the latch 81, and the inverter 84 inverts the clock MCLK and provides it to the clock end of the latch 81. This allows the latch 81 to take in and output the inverted signal of the output data MDAT in synchronization with the falling edge of the clock MCLK. The output of the latch 81 is provided to an inverter 85. The inverter 85 inverts the output of the latch 81 and outputs it to the INT end of the control circuit 90 as the detection result ALM.

[0159] Next, the operation of the embodiment configured in this manner will be described with reference to Fig. 20. Fig. 20 is a timing chart for explaining the operation of the sixth embodiment.

[0160] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with the clock CKI. CKI and DTI in Fig. 20 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 120 and buffers 63 and 64.

[0161] The edge detector DT2 detects the rising and falling edges of the clock CKI and outputs edge detection pulses (Fig. 20 DT2 output). Using the edge detection pulses generated at the rising and falling edges of the clock CKI, the latch L11 captures and outputs the output of the selector SE4. Therefore, the output from the latch L11 is double data rate.

[0162] Assume now that the system is in a normal state in which no abnormality such as excessive input has occurred. In this case, the detection signal FLTN is at L level. Therefore, the output of the latch L10 in the mixer 120 is at L level. The selector SE4 receives the output data DTI when the clock CKI is at H level and outputs it to L11, and receives the detection signal FLTN when the clock CKI is at L level and outputs it to L11. Therefore, in this case, the output of the latch L11 has information on the output data DTI during the period synchronized with the clock CKI at H level, and is at L level during the period synchronized with the clock CKI at L level.

[0163] Next, assume that an abnormality such as an excessive input occurs and the detection signal FLTN changes to H level. FLTN in FIG. 20 shows this state. The output of the latch L10 becomes H level at the first falling edge of the clock CKI after the detection signal FLTN becomes H level (L10 output in FIG. 20). This H level output of the latch L11 is output from the selector SE4 in synchronization with the falling edge of the clock CKI. Therefore, when the detection signal FLTN becomes H level, the output of the latch L11 has information of the output data DTI during the period synchronized with the H level of the clock CKI, and becomes H level during the period synchronized with the L level of the clock CKI (SE4 output in FIG. 20). The output of the latch L11 is output as the output data MDAT from the isolation amplifier 6 via the buffer 64.

[0164] The clock MCLK and output data MDAT from the isolation amplifier 6 are supplied to the FPGA 75. The FPGA 75 obtains data corresponding to the differential input VIN by sampling the output data MDAT in synchronization with the rising edge of the clock MCLK.

[0165] An inverter 83 of the external circuit 82 inverts the output data MDAT and provides it to the latch 81. Also, an inverter 84 inverts the clock MCLK and provides it to the clock end of the latch 81. This allows the latch 81 to capture and output the inverted signal of the output data MDAT in synchronization with the falling edge of the clock MCLK. Therefore, the latch 81 outputs an H level corresponding to the L level period of the detection signal FLTN, and outputs an L level corresponding to the H level period of the detection signal FLTN. The output of the latch 81 is inverted by an inverter 85 to become the detection result ALM. As shown by ALM in FIG. 20, the detection result ALM is a signal corresponding to the detection signal FLTN. The detection result ALM from the inverter 85 is supplied to the control circuit 90.

[0166] In this way, the detection result ALM makes it possible to quickly transmit the abnormality detection result to the control circuit 90. Furthermore, the output data MDAT processed in the FPGA 75 does not lose data, as shown in the FPGA of FIG.

[0167] In this way, the present embodiment can also provide the same effects as the fifth embodiment.

[0168] Seventh embodiment Fig. 21 is a block diagram showing an example of a specific configuration of a mixer employed in the seventh embodiment of the present invention. In Fig. 21, the same components as those in Fig. 13 are given the same reference numerals and their description will be omitted. Note that the isolation amplifier 7 of this embodiment differs from that of Fig. 12 only in that a mixer 130 is employed instead of the mixer 62, and description of the configuration other than the mixer 130 will be omitted. Note that in this embodiment, an external circuit 86 is employed instead of the external circuit 80 of Fig. 12.

[0169] In the third to sixth embodiments, it has been explained that the clock CKI may be either the clock generated by the clock recovery circuit 24 or a clock taken in from outside the isolation amplifier, but in this embodiment, the clock CKI uses the clock generated by the clock recovery circuit 24.

[0170] In the above third to sixth embodiments, the information of the detection signal FLTN is superimposed on the output data MDAT and transmitted. In the present embodiment, the information of the detection signal FLTN is transmitted by a clock.

[0171] 21, a clock CKI is supplied to latches L12, L13, and L14 and a delay circuit DE3 that constitute a mixer 130. In this embodiment, the mixer 130 supplies the input clock CKI to a buffer 63 via the latch L13. Output data DTI is supplied to the latch L14. The latch L14 latches the output data DTI in synchronization with the clock CKI and outputs it to the buffer 64.

[0172] The detection signal FLTN is supplied to the latch L12. The latch L12 captures the detection signal FLTN in synchronization with the rising edge of the clock CKI and supplies it to the selector SE5 as a selection signal. The delay circuit DE3 delays the clock CKI by a predetermined delay time and outputs the delayed signal to the rising detector DT1 and the falling detector DT3. The rising detector DT1 detects the rising edge of the clock CKI delayed in the delay circuit DE3 and outputs an edge detection pulse to the selector SE5. The falling detector DT3 detects the falling edge of the clock CKI delayed in the delay circuit DE3 and outputs an edge detection pulse to the selector SE5.

[0173] The selector SE5 selects an edge detection pulse from the rise detector DT1 during an H level period of the detection signal FLTN from the latch L12 and supplies it to the R end of the latch L13, and selects an edge detection pulse from the fall detector DT3 during an L level period of the detection signal FLTN from the latch L12 and supplies it to the R end of the latch L13.

[0174] The latch L13 takes in and outputs the H level (logical value "1") of the input at the rising edge of the clock CKI, and returns the output to the L level when an edge detection pulse from the selector SE5 is input to the R terminal. That is, during the L level period of the detection signal FLTN from the latch L12, the output of L13 becomes H level at the rising edge of the clock CKI, and becomes a pulse output with a relatively short pulse width that becomes L level at the timing of the edge detection pulse from the rising edge detector DT1. Also, during the H level period of the detection signal FLTN from the latch L12, the output of L13 becomes H level at the rising edge of the clock CKI, and becomes a pulse output with a relatively wide pulse width that becomes L level at the timing of the edge detection pulse from the falling edge detector DT3. The output of the latch L13 becomes the output of the isolation amplifier 7 as the clock MCLK via the buffer 63.

[0175] The clock MCLK and output data MDAT from the isolation amplifier 7 are also provided to an external circuit 86. The external circuit 86 has a low-pass filter constituted by a capacitor C11 and a resistor R11. One end of the resistor R11 is connected to the output end of the clock MCLK of the isolation amplifier 7, and the other end is connected to a reference potential point via the capacitor C11. The connection point between the capacitor C11 and the resistor R11 is connected to the ADC end of the control circuit 90.

[0176] The external circuit 86 is adapted to obtain an average value of the voltage level of the clock MCLK, and to supply the obtained average value to the ADC terminal of the control circuit 90 as the detection result ALM.

[0177] Next, the operation of the embodiment configured as above will be described with reference to Fig. 22. Fig. 22 is a timing chart for explaining the operation of the seventh embodiment.

[0178] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with the clock CKI. CKI and DTI in Fig. 22 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 130 and buffers 63 and 64.

[0179] The output data DTI is supplied to the latch L14, which outputs the output data DTI to the buffer 64 in synchronization with the rising edge of the clock CKI. In this way, the output data MDAT (MDAT in FIG. 22) from the isolation amplifier 7 is information corresponding to the output data DTI, and is output in synchronization with the rising edge of the clock CKI.

[0180] The clock CKI is supplied to a latch L13. The latch L13 outputs an H level, which is a logical value of "1", at the rising edge of the clock CKI. The output of the latch L13 is output as the clock MCLK via a buffer 63. Therefore, the rising edge of the clock MCLK is synchronized with the rising edge of the clock CKI.

[0181] The clock CKI is also supplied to a delay circuit DE3. The delay circuit DE3 delays the clock CKI and then outputs the delayed signal to a rising edge detector DT1 and a falling edge detector DT3. The rising edge detector DT1 detects the rising edge of the delayed signal and outputs an edge detection pulse to the selector SE5, and the falling edge detector DT3 detects the falling edge of the delayed signal and outputs an edge detection pulse to the selector SE5. The output of the selector SE5 is supplied to the R terminal of the latch L13, and the output of the latch L13 becomes L level at the timing of the output pulse of the selector SE5.

[0182] Now, assume that the system is in a normal state where no abnormality such as excessive input has occurred. In this case, the detection signal FLTN is at L level. Therefore, the selector SE5 selects the edge detection pulse from the rising edge detector DT1 and provides it to the latch L13. In this case, the output of the latch L13 outputs a relatively narrow pulse that goes to H level at the rising edge of the clock CKI and goes to L level at the rising edge of the clock CKI.

[0183] Next, assume that an abnormality such as excessive input occurs and the detection signal FLTN changes to H level. FLTN in FIG. 22 shows this state. The output of latch L12 becomes H level at the first rising edge of clock CKI after the detection signal FLTN becomes H level (L12 output in FIG. 22). The edge detection pulse from the rising edge detector DT1 is a pulse generated after the delay time of delay circuit DE3 from the rising edge of clock CKI (DT1 output in FIG. 22). Also, the output of the falling edge detector DT3 is a pulse generated at the falling edge of clock CKI after the delay time of delay circuit DE3 from the rising edge of clock CKI (DT3 output in FIG. 22).

[0184] The output of the latch L13 becomes a narrow pulse that goes to H level at the rising edge of the clock CKI during a period corresponding to the L level period of the detection signal FLTN, and goes to L level at the timing of the edge detection pulse from the rising edge detector DT1. Also, the output of the latch L13 becomes a wide pulse that goes to H level at the rising edge of the clock CKI during a period corresponding to the H level period of the detection signal FLTN, and goes to L level at the timing of the edge detection pulse from the falling edge detector DT3 (MCLK in FIG. 22).

[0185] The clock MCLK and the output data MDAT are supplied to the FPGA 70. As shown in the FPGA in FIG. 22, the output data MDAT is synchronized with the clock MCLK, and the output data MDAT can be processed in the FPGA 70.

[0186] The clock MCLK is also supplied to an external circuit 86. The clock MCLK is averaged by a low-pass filter formed by capacitors C11 and R11 of the external circuit 86. The external circuit 86 outputs this averaged clock MCLK to the control circuit 90 as the detection result ALM.

[0187] As shown by ALM in Fig. 22, by averaging the clock MCLK by the external circuit 86, the level of the detection result ALM becomes relatively low when the clock MCLK is narrow, and becomes relatively high when the clock MCLK is wide. The control circuit 90 obtains the abnormality detection result by comparing the level of the detection result ALM with the level shown by the dashed line in Fig. 22, for example.

[0188] In this way, the present embodiment can also provide the same effects as the fifth embodiment.

[0189] Eighth embodiment Fig. 23 is a block diagram showing an example of a specific configuration of a mixer employed in the eighth embodiment of the present invention. In Fig. 23, the same components as those in Fig. 13 are given the same reference numerals and their description will be omitted. Note that the isolation amplifier 8 of this embodiment differs from that of Fig. 13 only in that a mixer 140 is employed instead of the mixer 62, and description of the configuration other than the mixer 140 will be omitted. Note that in this embodiment, a pulse detector 87, which is an external circuit, is employed instead of the external circuit 80 of Fig. 13.

[0190] This embodiment is an example in which information of the detection signal FLTN is superimposed and transmitted during an invalid period of the output data MDAT. In the FPGA 70 at the rear stage of the isolation amplifier 8, the output data MDAT is sampled during an H level period of the clock MCLK. Therefore, in this embodiment, the information of the detection signal FLTN is superimposed by utilizing an invalid period of the output data MDAT corresponding to an L level period of the clock MCLK.

[0191] 23, the clock CKI is supplied to the inverter IN9 and latches L16 and L17 constituting the mixer 140, and is also supplied directly to the buffer 63. The output data DTI is supplied to the selector SE6. The detection signal FLTN is supplied to the XOR circuit EX1. The inverter IN9 inverts the clock CKI and supplies it to the latch L15. The latch L15 takes in the output of the XOR circuit EX1 at the timing of the inverted clock of the clock CKI and outputs it to the selector SE6 as a selection signal, and also outputs it to the XOR circuit EX1 and the latch L16.

[0192] The XOR circuit EX1 performs an exclusive OR operation (hereinafter referred to as XOR operation) between the detection signal FLTN and the output of the latch L15, and outputs the XOR operation result to L15. The output of the selector SE6 is given to the latch L17, which takes in the output of the selector SE6 at the rising edge of the clock CKI and outputs it to the selector SE6 and the XOR circuit EX2. The selector SE6 outputs output data DTI when the selection signal is at the L level, and outputs the output of the latch L17 when the selection signal is at the H level.

[0193] The latch L16 captures the output of the latch L15 at the rising edge of the clock CKI and outputs it to the falling edge detector DT3. The falling edge detector DT3 detects the falling edge of the output of the latch L15 and outputs an edge detection pulse to the XOR circuit EX2. The XOR circuit EX2 outputs the XOR operation result of the output of the latch L17 and the output of the falling edge detector DT3 to the buffer 64.

[0194] With this configuration, as will be described later, during invalid periods of the output data MDAT corresponding to the rising and falling edges of the detection signal FLTN, a pulse is generated that inverts the level of the output data MDAT and returns it to its original state.

[0195] The clock MCLK and output data MDAT from the isolation amplifier 8 are supplied to the FPGA 70. The FPGA 70 obtains data corresponding to the differential input VIN by sampling the output data MDAT in synchronization with the rising edge of the clock MCLK.

[0196] In this embodiment, a pulse detector 87 is employed as an external circuit. The clock MCLK from the isolation amplifier 8 is supplied to the CLK terminal of the pulse detector 87, and the output data MDAT from the isolation amplifier 8 is supplied to the DAT terminal. The pulse detector 87 detects a pulse superimposed on an invalid period of the output data MDAT, thereby generating a detection result ALM indicating the detection of an abnormality and outputting it to the control circuit 90.

[0197] FIG. 24 is a circuit diagram showing an example of a specific configuration of the pulse detector 87 in FIG.

[0198] The clock MCLK and output data MDAT from the isolation amplifier 8 are also supplied to the pulse detector 87. That is, the clock MCLK is supplied to latches L18, L20, L21 and a delay circuit DE4. The output data MDAT is supplied to the latch L18 and the match circuit EX3. The latch L18 takes in the output data MDAT at the rising edge of the clock MCLK and outputs it to the match circuit EX3. The match circuit EX3 performs a match operation that outputs an H level when the two inputs are the same logic (match) and an L level when they do not match, and outputs the match operation result to the AND circuit A9. The match operation result of the match circuit EX3 is also inverted and provided to the latch L19.

[0199] The delay circuit DE4 delays the output data MDAT for a predetermined period and outputs it to the latch L19. The latch L19 takes in the inverted signal of the output of the match circuit EX3 during the H level period of the output of the delay circuit DE4 and outputs it to the AND circuit A9, and outputs an L level (logical value "0") to the AND circuit A9 during the L level period of the output of the delay circuit DE4. The AND circuit A9 outputs the result of the AND operation of the two inputs to the OR circuit OR2 and the latch L20.

[0200] The latch L20 takes in the output of the AND circuit A9 at the rising edge of the clock MCLK and outputs it to the OR circuit OR2. The OR circuit OR2 outputs the OR operation result of the two inputs to the latch L21. The latch L21 takes in the output of the OR circuit OR2 at the rising edge of the clock MCLK and outputs it. The output of the latch L21 is supplied to the control circuit 90 as the detection result ALM. As will be described later, a pulse included in the invalid period of the output data MDAT is detected by the pulse detector 87, and the detection result ALM is obtained in accordance with this pulse.

[0201] Next, the operation of the embodiment configured as above will be described with reference to Fig. 25 and Fig. 26. Fig. 25 is a timing chart for explaining the generation of the clock MCLK and the output data MDAT in the isolation amplifier 8, and Fig. 26 is a timing chart for explaining the operation of the pulse detector 87.

[0202] The decoder 61 of the secondary circuit 60 outputs a clock CKI and outputs output data DTI in synchronization with the clock CKI. CKI and DTI in Fig. 25 indicate these clocks and data. The clock CKI and output data DTI are output as a clock MCLK and output data MDAT via a mixer 140 and buffers 63 and 64.

[0203] Now, assume that the current state is normal and no abnormality such as excessive input has occurred. In this case, the detection signal FLTN is at L level. Therefore, the outputs of the latches L15 and L16 are also at L level, and the output of the XOR circuit EX1 continues to be at L level. The selector SE6 selects the output data DTI and outputs it to the latch L17. The latch L17 outputs the output data DTI to the XOR circuit EX2 at the rising edge of the clock CKI.

[0204] Since the output of L16 is at L level, the output of DT3 also becomes L level, and output data DTI is output from the XOR circuit EX2. The output of the XOR circuit EX2 is output as output data MDAT via a buffer 64. Thus, under normal circumstances, the clock CKI and the output data DTI are output as they are as the clock MCLK and the output data MDAT.

[0205] Next, assume that an abnormality such as excessive input occurs and the detection signal FLTN changes to H level. FLTN in Figure 25 shows this state. When the detection signal FLTN changes from L level to H level, the output of the XOR circuit EX1 outputs an H level output. The output of the XOR circuit EX1 is captured by the latch L15 at the falling edge of the clock CKI and returned to the input terminal. Therefore, the output of the XOR circuit EX1 changes at every falling edge of the clock CKI while the detection signal FLTN is at H level. As a result, the output of the latch L15 is also inverted at the falling edge of the clock CKI while the detection signal FLTN is at H level (L15 output in Figure 25).

[0206] Latch L17 takes in the output of selector SE6 at the rising edge of clock CKI and returns it to the input terminal of selector SE6. During the L level period of detection signal FLTN, output data DTI is output as is from selector SE6, and during the H level period, the output data DTI output by latch L17 one clock before is output from selector SE6. Therefore, as shown in the latch L17 output in Figure 25, during the detection signal FLTN period, the same data is output from latch L17 for two clock periods.

[0207] Latch L16 takes in the output of latch L15 at the rising edge of clock CKI and outputs it to falling edge detector DT3. Therefore, the output of latch L16 is the output of latch L15 delayed by half a clock cycle (L16 output in FIG. 25). Falling edge detector DT3 detects the falling edge of latch L16 and outputs an edge detection pulse (DT3 output in FIG. 25). XOR circuit EX2 performs an XOR operation on the output of latch L17 and the output of falling edge detector DT3. From XOR circuit EX2, when the output of latch L16 is at L level, data from latch L17 is output as is, and when the edge detection pulse from latch L16 is at H level, the data from latch L17 is inverted and output. MDAT in FIG. 25 shows this, and the level of data D1 is inverted during the period corresponding to the H level period of the edge detection pulse.

[0208] The clock MCLK and output data MDAT from the isolation amplifier 8 are supplied to the FPGA 70. As shown in the FPGA of Fig. 25, the FPGA 70 acquires the output data MDAT during the H level period of the clock MCLK.

[0209] The clock MCLK and output data MDAT from the isolation amplifier 8 are also supplied to a pulse detector 87. MCLK and MDAT in Fig. 26 show an example of the clock MCLK and output data MDAT supplied to the pulse detector 87. In the example of Fig. 26, the output data MDAT indicates whether the data value is "0" or "1" by an L level or an H level, and protruding pulses in MDAT indicate a pulse P1 corresponding to a change in the detection signal FLTN from an L level to an H level, which are added to the data by the mixer 140, and a pulse P2 corresponding to a change in the detection signal FLTN from an H level to an L level.

[0210] The latch L18 of the pulse detector 87 captures the output data MDAT at the rising edge of the clock MCLK and outputs it to the coincidence circuit EX3. As shown in the L18 output in Fig. 26, the latch L18 outputs the output data MDAT in synchronization with the rising edge of the clock MCLK.

[0211] The output data MDAT from the isolation amplifier 8 is supplied to the match circuit EX3, and the match circuit EX3 outputs to the AND circuit A9 a match operation result that is H level during a match period between the output of the latch L18 and the input output data MDAT and is L level during a mismatch period. The match operation result from the match circuit EX3 is also inverted and supplied to the latch L19.

[0212] The delay circuit DE4 delays the clock MCLK by a predetermined period and outputs the delayed output to the latch L19 (DE4 output in FIG. 26). The latch L19 takes in the inverted signal of the output from the match circuit EX3 while the output of the delay circuit DE4 is at H level and outputs it to the AND circuit A9, and outputs an L level (logical value "0") to the AND circuit A9 while the output of the delay circuit DE4 is at L level.

[0213] As a result, the latch L19 outputs an output that is approximately the inverse of the output of the match circuit EX3, but falls with a delay of the delay time of the delay circuit DE4 from the rising timing of the output of the match circuit EX3. Therefore, as shown in the L19 output in Figure 26, the output of the latch L19 has a waveform with an H level period that is slightly wider than the L level period of the output of the match circuit EX3 at normal data switching timing. On the other hand, at the timing corresponding to pulses P1 and P2, which are narrow pulses, the output of the delay circuit DE4 becomes L level before rising in response to the rising of pulses P1 and P2, so the change in waveform due to pulses P1 and P2 does not appear in the output of L19.

[0214] The AND circuit A9 performs an AND operation on the output of the match circuit EX3 and the output of the latch L19. As shown in the A9 output in Fig. 26, the output of the AND circuit A9 is a narrow pulse waveform, corresponding to the waveform in which the H level period of the output of the latch L19 is wider than the L level period of the match circuit EX3. Also, the output of the AND circuit A9 is a pulse waveform with a wide H level, corresponding to the waveform of the output of the latch L19 in the period corresponding to the pulses P1 and P2.

[0215] Latch L20 takes in the output of AND circuit A9 at the rising edge of clock MCLK and outputs it to OR circuit OR2. The narrow pulse at the output of latch L19 occurs after the rising edge of clock MCLK and does not appear in the output of latch L20. On the other hand, at the rising edge of clock MCLK, an H level period of the wide pulse at the output of latch L19 occurs, and the output of latch L20 has a pulse waveform with a width of one clock cycle corresponding to this wide pulse period (L20 output in FIG. 26).

[0216] The OR circuit OR2 performs an OR operation on the output of the AND circuit A9 and the output of the latch L20 to obtain the output shown as OR2 output in Fig. 26. The output of the OR circuit OR2 is given to the latch L21, which takes in and outputs the output of the OR circuit OR2 at the rising edge of the clock MCLK. The output of the latch L21 becomes the detection result ALM corresponding to the period from pulse P1 to pulse P2, as shown as ALM in Fig. 26. The latch L21 outputs the detection result ALM to the control circuit 90.

[0217] In this manner, the present embodiment can also provide the same effects as the third embodiment.

[0218] Ninth embodiment Figures 27 and 28 are block diagrams showing the ninth embodiment. Figure 27 corresponds to an isolation amplifier with analog output, and Figure 28 corresponds to an isolation amplifier with digital output.

[0219] In each of the above embodiments, the control circuit required two terminals: a data input terminal for inputting data corresponding to the differential input VIN, and an interrupt terminal for inputting the abnormality detection result. This embodiment makes it possible to input the data corresponding to the differential input VIN and the abnormality detection result into the control circuit via a single terminal.

[0220] In FIG. 27, an isolation amplifier 53 is the isolation amplifier 1, 2 of the first or second embodiment. A differential to single-phase conversion circuit 50 adds the output differential signals VOUT+, VOUT- of the isolation amplifier 53 and outputs the addition result to the A terminal of the abnormality detection circuit 51. The abnormality detection circuit 51 is configured with a comparator and compares the addition result A with a judgment reference voltage Vref input to the B terminal. The abnormality detection circuit 51 outputs an H level when the level of the A terminal is equal to or higher than the level of the B terminal, and outputs an L level when the level of the A terminal is lower than the level of the B terminal. In this embodiment, the abnormality detection circuit 51 outputs the comparison result to a selector 54 as a selection signal.

[0221] The selector 54 also receives the single-phase output AOUT from the differential to single-phase conversion circuit 50, selects and outputs the single-phase output AOUT in response to a selection signal of L level, and selects and outputs a predetermined maximum value in response to a selection signal of H level. The output of the selector 54 is output to the ADC1 terminal of the control circuit 91.

[0222] When a normal level signal is input to the ADC1 terminal, the control circuit 91 judges the input signal to be a single-phase output AOUT and performs processing. On the other hand, when a signal of the maximum level that the control circuit 91 handles is input to the ADC1 terminal, the control circuit 91 judges the input signal to be an abnormality detection result indicating the occurrence of an abnormality and performs processing.

[0223] In this way, by adopting the configuration of FIG. 27, it is possible to transmit data and abnormality detection results to the control circuit through a single terminal.

[0224] 28, an isolation amplifier 57, an FPGA 58, and an external circuit 59 are shown as representatives of the isolation amplifiers 3 to 8, FPGAs 70 and 75, and external circuits 80, 82, and 86 of the third to eighth embodiments, respectively. The clock MCLK and output data MDAT from the isolation amplifier 57 are input to the external circuit 59. The external circuit 59 generates a detection result ALM based on the clock MCLK and the output data MDAT.

[0225] In this embodiment, the external circuit 59 outputs the detection result ALM as a selection signal to the selector 92. The filter processed data is also input to the selector 92 from the output terminal DIF of the FPGA 58. The selector 92 selects and outputs data from the FPGA 58 in response to an L-level selection signal, and selects and outputs a predetermined singular value in response to an H-level selection signal. Note that the singular value may be a negative maximum value or the like. The selector 92 outputs the selected output to the DIF terminal of the control circuit 93.

[0226] When a signal of a normal level is input to the DIF terminal, the control circuit 93 determines that the input signal is data from the FPGA 58 and performs processing. On the other hand, when a signal of a singular value is input to the DIF terminal, the control circuit 93 determines that the input signal is an abnormality detection result indicating the occurrence of an abnormality and performs processing.

[0227] In this way, by adopting the configuration of FIG. 28, it is possible to transmit data and abnormality detection results to the control circuit via a single terminal.

[0228] (Tenth embodiment) Fig. 29 is a block diagram showing a tenth embodiment. In Fig. 29, the same components as those in Fig. 12 are given the same reference numerals and their description will be omitted. In the embodiment in Fig. 12, an example was described in which a built-in clock (clock MCLK) generated in the secondary circuit 60 of the isolation amplifier 3 is used, but this embodiment shows an example in which an external clock generated externally is used as the clock MCLK.

[0229] The secondary circuit 151 of the isolation amplifier 150 in FIG. 29 is different from the secondary circuit 60 of the isolation amplifier 3 in that the clock recovery circuit 24 and the buffer 63 are omitted. The isolation amplifier 150 receives a clock MCLK as a clock MCLKIN from the outside via a clock input terminal. The decoder 61 of the secondary circuit 151 decodes the differential signal transferred from the isolation unit 30 using the clock MCLKIN, and generates output data DTI corresponding to the differential input VIN. Similarly to the mixer 62 of the isolation amplifier 3, the mixer 62 of the secondary circuit 151 outputs output data DTO obtained by changing the output data DTI in response to the detection signal FLTN. The mixer 62 of the secondary circuit 151 does not output a clock.

[0230] 29, the clock MCLK is generated by a clock generation circuit 156 provided in an FPGA 155. The FPGA 155 differs from the FPGA 70 in that the clock generation circuit 156 is added. The clock generation circuit 156 provides the generated clock MCLK to the latch 71 and also to the clock input terminal of the isolation amplifier 150.

[0231] This embodiment differs from the embodiment in FIG. 12 only in that an external clock is used instead of the built-in clock, and other configurations and operations are similar to those of the embodiment in FIG.

[0232] Although the present embodiment has been described by way of example as being applied to the third embodiment in FIG. 12, it is applicable to the third to sixth, eighth and ninth embodiments, except for the seventh embodiment in which the clock is processed.

[0233] (Modification) Fig. 30 is a block diagram showing a modified example. In Fig. 30, the same components as those in Fig. 1 are given the same reference numerals and the description thereof will be omitted.

[0234] 1, an example has been described in which the detection information is generated by the external resistors R1 and R2 and the comparator 15, but a circuit for generating the detection information may be built in. FIG 30 shows an example of this case.

[0235] A primary circuit 161 of an isolation amplifier 160 in FIG. 30 differs from the primary circuit 10 of the isolation amplifier 1 in that an abnormality detection circuit 162 is used instead of the comparator 15. In this modification, the resistors R1 and R2 are omitted. The abnormality detection circuit 162 is provided with input differential signals VIN+ and VIN-. The abnormality detection circuit 162 detects the occurrence of an abnormality by the input differential signals VIN+ and VIN-. For example, the abnormality detection circuit 162 may detect the occurrence of an abnormality by dividing the differential input VIN and comparing it with a predetermined detection voltage VREF. The abnormality detection circuit 162 outputs a detection signal indicating the presence or absence of an abnormality to the secondary circuit 20 via the isolation unit 30.

[0236] The other configurations, functions, and effects are the same as those of the first embodiment.

[0237] The present invention is not limited to the above embodiment, and various modifications can be made in the implementation stage without departing from the gist of the invention. In addition, the above embodiment includes inventions at various stages, and various inventions can be extracted by appropriate combinations of the disclosed multiple constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, if the problem described in the "Problem to be Solved by the Invention" column can be solved and the effect described in the "Effect of the Invention" column can be obtained, the configuration from which the constituent elements are deleted can be extracted as the invention. [Explanation of symbols]

[0238] 1 to 8...isolation amplifier, 10...primary circuit, 11...ΔΣADC, 12...encoder, 13...clock generator, 14...reference voltage generator, 15...comparator, 20, 28, 60...secondary circuit, 21...decoder, 22...1-bit DAC, 23...LPF, 24...clock recovery circuit, 25...reference voltage generator, 26, 27...abnormal input detection output circuit, 30...isolation section, 50...differential to single-phase conversion circuit, 51...abnormal detection circuit, 52, 90...control circuit, 55...motor, 56...motor drive circuit, 61...decoder, 62, 100, 110, 120, 130, 140...mixer, 70, 75...FPGA, 72...LPF, 80, 82, 86...external circuit.

Claims

1. a primary circuit including an analog-to-digital conversion circuit for converting an input signal provided from a device to be detected into a digital signal, and an encoder for encoding and outputting the output of the analog-to-digital conversion circuit; an abnormality detection circuit provided in the primary circuit and detecting an abnormality occurring in the input signal to generate a detection signal; an isolation unit that transmits an output of the encoder and the detection signal to the secondary circuit while isolating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit, the output circuit including a decoder that receives the output of the encoder and the detection signal transmitted by the isolation unit, performs a decoding process corresponding to the encoding process, and generates an output signal corresponding to the input signal; an abnormal input detection output circuit provided in the secondary circuit for changing an output signal of the output circuit in accordance with a predetermined rule based on the detection signal to produce an output signal of the secondary circuit; the input signal and the output signal are a pair of differential signals, the abnormal input detection output circuit outputs a signal of a predetermined level instead of the pair of differential signals which are the output signals during a period in which the detection signal indicates that an abnormality has occurred. Isolation amplifier.

2. A primary circuit including an analog-to-digital conversion circuit for converting an input signal provided from a device to be detected into a digital signal, and an encoder for encoding and outputting the output of the analog-to-digital conversion circuit; an abnormality detection circuit provided in the primary circuit and detecting an abnormality occurring in the input signal to generate a detection signal; an isolation unit that transmits an output of the encoder and the detection signal to the secondary circuit while isolating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit, the output circuit including a decoder that receives the output of the encoder and the detection signal transmitted by the isolation unit, performs a decoding process corresponding to the encoding process, and generates an output signal corresponding to the input signal; an abnormal input detection output circuit provided in the secondary circuit for changing an output signal of the output circuit in accordance with a predetermined rule based on the detection signal to produce an output signal of the secondary circuit; the decoder outputs a digital output signal corresponding to the input signal; the output circuit outputs the digital output signal generated by the decoder as an output signal; the abnormal input detection output circuit changes a logic level of the digital output signal from the decoder in response to a period during which the detection signal indicates that an abnormality has occurred; The abnormal input detection output circuit outputs the logic level of the digital output signal from the decoder in synchronization with one edge of a clock during a period in which the detection signal indicates that an abnormality has occurred, and forcibly changes the logic level to one logic level in synchronization with the other edge of the clock.

3. 3. The isolation amplifier according to claim 2, wherein the abnormal input detection output circuit forcibly changes a logic level of the digital output signal from the decoder within an output period of one data at timings corresponding to a start timing and an end timing of the abnormality occurrence indicated by the detection signal.

4. 3. The isolation amplifier according to claim 2, wherein the abnormal input detection output circuit forcibly changes a logic level of the digital output signal from the decoder to one logic level and then to the other logic level within an output period of one data at timings corresponding to a start timing and an end timing of the abnormality occurrence indicated by the detection signal.

5. 3. The isolation amplifier according to claim 2, wherein the abnormal input detection output circuit outputs the digital output signal in synchronization with one edge of a clock, and outputs a logic level different from that in other periods in a period in which the detection signal indicates that an abnormality has occurred in synchronization with the other edge of the clock.

6. A primary circuit including an analog-to-digital conversion circuit for converting an input signal provided from a device to be detected into a digital signal, and an encoder for encoding and outputting the output of the analog-to-digital conversion circuit; an abnormality detection circuit provided in the primary circuit and detecting an abnormality occurring in the input signal to generate a detection signal; an isolation unit that transmits an output of the encoder and the detection signal to the secondary circuit while isolating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit, the output circuit including a decoder that receives the output of the encoder and the detection signal transmitted by the isolation unit, performs a decoding process corresponding to the encoding process, and generates an output signal corresponding to the input signal; an abnormal input detection output circuit provided in the secondary circuit for changing an output signal of the output circuit in accordance with a predetermined rule based on the detection signal to produce an output signal of the secondary circuit; the decoder outputs a digital output signal and a clock corresponding to the input signal; the output circuit outputs the digital output signal and the clock generated by the decoder as output signals; 2. The isolation amplifier according to claim 1, wherein the abnormal input detection output circuit changes a duty ratio of the clock from the decoder between a period in which the detection signal indicates that an abnormality has occurred and a period other than that.

7. A primary circuit including an analog-to-digital conversion circuit for converting an input signal provided from a device to be detected into a digital signal, and an encoder for encoding and outputting an output of the analog-to-digital conversion circuit; an abnormality detection circuit provided in the primary circuit and detecting an abnormality occurring in the input signal to generate a detection signal; an isolation unit that transmits an output of the encoder and the detection signal to the secondary circuit while isolating the primary circuit from the secondary circuit; an output circuit provided in the secondary circuit, the output circuit including a decoder that receives the output of the encoder and the detection signal transmitted by the isolation unit, performs a decoding process corresponding to the encoding process, and generates an output signal corresponding to the input signal; an abnormal input detection output circuit provided in the secondary circuit for changing an output signal of the output circuit in accordance with a predetermined rule based on the detection signal to produce an output signal of the secondary circuit; the decoder outputs a digital output signal corresponding to the input signal; the output circuit outputs the digital output signal generated by the decoder as an output signal; the abnormal input detection output circuit changes a logic level of the digital output signal from the decoder in response to a period during which the detection signal indicates that an abnormality has occurred; the abnormal input detection output circuit changes the logical level of the data from the decoder to a logical level different from that of the data during an invalid period corresponding to the start timing and end timing of the abnormality indicated by the detection signal, and then immediately returns the logical level to the original level, generating a narrow pulse.

8. An isolation amplifier according to any one of claims 1 to 7; a detection circuit that detects the presence or absence of an abnormality in the input signal provided from the device to be detected from the output signal of the isolation amplifier, and outputs the abnormality detection result to a control circuit.

9. a processing circuit that outputs a signal that corresponds to the input signal and is included in an output signal of the isolation amplifier; an abnormality detection device according to claim 8, further comprising: a selector that switches between an output of the processing circuit and a signal indicating that an abnormality has occurred in the input signal based on the abnormality detection result from the detection circuit, and outputs the switched output to a common terminal of the control circuit.

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