Silicon-on-insulator substrate including a trap-rich layer and method for fabricating the same

Abstract

The silicon-on-insulator substrate includes: (1) a high-resistivity base layer including a trap rich region comprising silicon and arsenic diffused into a first side; (2) a silicon dioxide layer positioned on the first side of the high-resistivity base layer and having a thickness in the range of 1000 to 5000 angstroms; and (3) a transfer layer positioned on the silicon dioxide layer. The trap rich region has a thickness in the range of 1 to 10 microns and a transfer layer of 0.8 x 10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 The high resistivity base layer has a resistivity in the range of 50-100 ohm-meters and a thickness in the range of 500-700 microns, and the transfer layer comprises a silicon wafer and has a thickness in the range of 500-5000 angstroms.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is related to and claims the benefit of commonly owned U.S. Provisional Patent Application No. 62 / 911,827, filed October 7, 2019, entitled "Silicon-on-insulator substrates including trap rich layers and methods for making same", U.S. Provisional Patent Application No. 62 / 911,835, filed October 7, 2019, entitled "Silicon-on-insulator substrates including trap rich layers and methods for making same", and U.S. Provisional Patent Application No. 62 / 911,843, filed October 7, 2019, entitled "Silicon-on-insulator substrates including trap rich layers and methods for making same", the entire contents of which are incorporated herein by reference in their entireties.

[0002] The field of the invention relates to silicon-on-insulator substrates and methods for making such substrates, in particular to silicon-on-insulator substrates having a trap rich layer and methods for making such substrates. [Background technology]

[0003] Integrated chips are formed on substrates that include semiconductor material. Traditionally, integrated chips were formed on bulk substrates that include a solid layer of semiconductor material. More recently, silicon-on-insulator substrates have emerged as an alternative. A silicon-on-insulator (SOI) substrate is a substrate that has a thin layer of active silicon separated from an underlying handle wafer. The layer of insulating material electrically insulates the thin layer of active silicon from the handle wafer, thereby reducing current leakage of devices formed within the thin layer of active silicon. The thin layer of active silicon provides fast switching times and low actuation voltages, making SOI substrates widely used for the manufacture of high-capacity radio frequency (RF) systems such as RF switches.

[0004] SOI substrates typically use handle wafers with high resistivity. The use of high resistivity handle wafers allows the SOI substrate to meet application requirements such as isolation between devices and Q-factor of passive components. However, the low doping of such high resistivity handle wafers can cause carriers from the surface and sub-surface regions of the handle wafer to build up along the surface of the high resistivity handle wafer and form accumulation or inversion layers, depending on the type of charge present in the buried oxide layer above the handle wafer. Voltages applied to devices within the thin layer of overlying active silicon can interact with such accumulation layers, resulting in parasitic surface conduction that can lead to undesirable device crosstalk and / or nonlinear distortion in the RF signal. [Brief description of the drawings]

[0005] Certain embodiments of the present invention are herein described, by way of example only, with reference to the accompanying drawings, in which: With specific reference to the drawings in detail, it is stressed that certain details are shown by way of example for the purpose of illustrative description of embodiments of the invention, In this regard, the description taken together with the drawings will make apparent to those skilled in the art how embodiments of the invention may be practiced.

[0006] [Figure 1] FIG. 1 illustrates an exemplary silicon-on-insulator substrate suitable for applications such as the manufacture of RF systems. [Diagram 2] FIG. 2 shows a flow chart of an exemplary fabrication method of the silicon-on-insulator substrate shown in FIG. [Figure 3A] FIG. 3A shows an intermediate product from the first stage of the exemplary method of FIG. [Figure 3B] FIG. 3B illustrates an intermediate product at the second stage of the exemplary method of FIG. [Figure 3C] FIG. 3C illustrates an intermediate product at the third stage of the exemplary method of FIG. [Figure 3D] FIG. 3D illustrates an intermediate product at the fourth stage of the exemplary method of FIG. [Figure 3E] FIG. 3E illustrates an intermediate product at the fifth stage of the exemplary method of FIG. [Figure 3F] FIG. 3F illustrates an intermediate product at the sixth stage of the exemplary method of FIG. [Figure 3G] FIG. 3G illustrates an intermediate product at the seventh stage of the exemplary method of FIG. [Figure 3H] FIG. 3H illustrates an intermediate product at the eighth stage of the exemplary method of FIG. [Figure 3I] FIG. 3I shows the final product after step 9 of the exemplary method of FIG. [Figure 4] FIG. 4 illustrates an exemplary silicon-on-insulator substrate suitable for applications such as the manufacture of RF systems. [Diagram 5] FIG. 5 shows a flow chart of an exemplary fabrication method of the silicon-on-insulator substrate shown in FIG. [Figure 6A] FIG. 6A shows an intermediate product of the first stage of the exemplary method of FIG. [Figure 6B] FIG. 6B illustrates an intermediate product of the second stage of the exemplary method of FIG. [Figure 6C] FIG. 6C illustrates an intermediate product at the third stage of the exemplary method of FIG. [Figure 6D] FIG. 6D illustrates an intermediate product at the fourth stage of the exemplary method of FIG. [Figure 6E] FIG. 6E illustrates an intermediate product at the fifth stage of the exemplary method of FIG. [Figure 6F] FIG. 6F illustrates an intermediate product at the sixth stage of the exemplary method of FIG. [Figure 6G] FIG. 6G illustrates an intermediate product at the seventh stage of the exemplary method of FIG. [Figure 6H] FIG. 6H illustrates an intermediate product at the eighth stage of the exemplary method of FIG. [Figure 6I] FIG. 6I shows the final product after step 9 of the exemplary method of FIG. [Figure 7A] FIG. 7A shows the state of arsenic concentration in an exemplary first silicon wafer into which arsenic has been diffused. [Figure 7B] FIG. 7B shows a plot of arsenic concentration versus depth for the exemplary first silicon wafer shown in FIG. 7A. [Figure 7C] FIG. 7C shows the state of arsenic concentration in an exemplary first silicon wafer into which arsenic has been implanted by ion implantation. [Figure 7D] FIG. 7D shows a plot of arsenic concentration versus depth for the exemplary first silicon wafer shown in FIG. 7C. Summary of the Invention

[0007] In some embodiments, the substrate includes a high resistivity base layer having a first side and a second side, a silicon nitride layer disposed on the first side of the high resistivity base layer, a silicon dioxide layer disposed on the silicon nitride layer opposite the high resistivity base layer, and a silicon layer disposed on the silicon dioxide layer opposite the silicon nitride layer.

[0008] In some embodiments, a method for fabricating a substrate includes providing a first silicon wafer having a first side and a second side, depositing a silicon nitride layer on the first side of the first silicon wafer, depositing a silicon dioxide layer opposite the first side of the silicon nitride layer, providing a second silicon wafer, introducing a hydrogen implant into the second silicon wafer to define a cleavage plane, activating the silicon dioxide layer, bonding the second silicon wafer to the activated silicon dioxide layer thereby producing a monolithic wafer, annealing the monolithic wafer, applying tension to the monolithic wafer in one direction to space the first and second silicon wafers apart from one another, and striking an edge of the second silicon wafer to cleave the second silicon wafer at the cleavage plane, thereby producing a silicon-on-insulator substrate.

[0009] In some embodiments, the step of depositing the silicon nitride layer is performed using a high density plasma chemical vapor deposition process. In some embodiments, the step of depositing the silicon dioxide layer is performed using a high density plasma chemical vapor deposition process.

[0010] In some embodiments, the substrate includes a high resistivity base layer having a first side and a second side, an arsenic layer diffused into the first side of the high resistivity base layer, a silicon dioxide layer disposed on the first side of the high resistivity base layer covering the arsenic layer, and a silicon layer disposed on the silicon dioxide layer opposite the arsenic layer.

[0011] In some embodiments, a method for fabricating a substrate includes providing a first silicon wafer having a first side and a second side, diffusing an arsenic layer into the first side of the first silicon wafer, depositing a silicon dioxide layer on the first side of the high resistivity base layer covering the arsenic layer, providing a second silicon wafer, introducing a hydrogen implant into the second silicon wafer to define a cleavage plane, activating the silicon dioxide layer, bonding the second silicon wafer to the activated silicon dioxide layer, thereby producing a monolithic wafer, annealing the monolithic wafer, applying tension to the monolithic wafer in one direction to space the first and second silicon wafers apart from one another, and striking an edge of the second silicon wafer to cleave the second silicon wafer at the cleavage plane, thereby producing a silicon-on-insulator substrate.

[0012] In some embodiments, diffusing the arsenic layer is performed by spinning a solution containing arsenic and diffusing the arsenic at a controlled temperature for a controlled time, hi some embodiments, depositing the silicon dioxide layer is performed using a high density plasma chemical vapor deposition process.

[0013] In some embodiments, the silicon-on-insulator substrate includes a layer structure including, in order, (1) a high resistivity base layer having a first side and a second side opposite the first side, (2) a silicon dioxide layer positioned on the first side of the high resistivity base layer, and (3) a transfer layer positioned on the silicon dioxide layer, the high resistivity base layer including a trap rich region including (a) silicon, and (b) arsenic diffused into the first side of the high resistivity base layer, the trap rich region having (i) a thickness in the range of 1 to 10 microns, and (ii) a transfer layer having a thickness of 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 the high resistivity base layer (a) has a resistivity in the range of 50 to 100 ohm-meters, and (b) a thickness in the range of 500 to 700 microns, the silicon dioxide layer has a thickness in the range of 1000 to 5000 angstroms, and the transfer layer comprises a silicon wafer and has a thickness in the range of 500 to 5000 angstroms.

[0014] In some embodiments, the trap rich region is 10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 In some embodiments, the trap rich region comprises arsenic interspersed within a crystalline structure of the silicon of the high resistivity base layer. In some embodiments, the trap rich region has a thickness in the range of 4 microns to 7 microns. In some embodiments, the high resistivity base layer has a thickness in the range of 550 to 650 microns. In some embodiments, the silicon dioxide layer has a thickness in the range of 2000 to 4000 angstroms. In some embodiments, the transfer layer has a thickness in the range of 2000 to 3500 angstroms.

[0015] One method includes providing a first silicon wafer having a first side and a second side; applying an arsenic solution, which is a liquid colloidal solution, to the first side of the first silicon wafer; holding the first silicon wafer with the arsenic solution on the first side at a controlled temperature for a controlled time to cause diffused arsenic to form a trap rich region on the first side of the first silicon wafer; depositing a silicon dioxide layer on the first side of the first silicon wafer using a high density plasma chemical vapor deposition (HDPCVD) process; providing a second silicon wafer having a first side and a second side opposite the first side; introducing a hydrogen implant into the second silicon wafer to define a cleavage plane; activating the silicon dioxide layer; contacting a first side of the second silicon wafer with the activated silicon dioxide layer to produce a united wafer; annealing the united wafer; applying tension to the united wafer in one direction to separate the first and second silicon wafers from one another; and striking an edge of the second silicon wafer to cleave the second silicon wafer at the cleavage plane, thereby producing a silicon-on-insulator substrate, wherein during the step of holding the first silicon wafer, the controlled time is in the range of 5 hours to 20 hours, the controlled temperature is in the range of 700 to 1200 degrees Celsius, the trap rich region has a thickness in the range of 1 to 10 microns, and the trap rich region has a diameter of 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1and in the step of depositing the silicon dioxide layer, the HDPCVD process uses an inductively coupled plasma source, the inductively coupled plasma source being driven at a power in the range of 65 watts to 225 watts, the HDPCVD process uses an oxygen gas flow, a silane gas flow, and an argon gas flow, the oxygen gas flow rate being in the range of 20-35 sccm, the silane gas flow rate being in the range of 20-35 sccm, and the argon gas flow rate being in the range of 20-35 sccm, the HDPCVD process being conducted at a pressure in the range of 5 mTorr to 20 mTorr, the HDPCVD process being conducted with a bias power in the range of 0-100 watts, and the HDPCVD process being conducted at a temperature in the range of 100-250 degrees Celsius. a deposition rate of the silicon dioxide layer is in the range of 900-1100 angstroms / min and a thickness of the silicon dioxide layer is in the range of 1500-5000 angstroms; in the step of introducing a hydrogen implant into the second silicon wafer, a thickness of a portion of the second silicon wafer between the first side and the cleavage surface of the second silicon wafer is in the range of 500-5000 angstroms; the step of activating the silicon dioxide layer includes low pressure plasma activated bonding at a pressure in the range of 0.1-100 Pa; and in the step of annealing the integrated wafer, the annealing is performed at a temperature in the range of 200-400 degrees Celsius for a time in the range of 1 hour to 8 hours.

[0016] In some embodiments, applying an arsenic solution to the first side of the first silicon wafer comprises spin-coating the arsenic solution onto the first side of the first silicon wafer. In some embodiments, the liquid colloidal solution comprises arsenic infused glass. In some embodiments, the oxygen gas flow rate, the silane gas flow rate, and the argon gas flow rate are identical to one another. In some embodiments, the oxygen gas flow rate, the silane gas flow rate, and the argon gas flow rate are selected to control the refractive index of the silicon dioxide layer. In some embodiments, the controlled time is selected to control charge dissipation of the trap rich layer. In some embodiments, the trap rich region is 10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 In some embodiments, holding the first silicon wafer with an arsenic solution on the first side at a controlled temperature for a controlled time produces arsenic interspersed within the crystalline structure of the silicon of the high resistivity base layer. In some embodiments, holding the first silicon wafer with an arsenic solution on the first side at a controlled temperature for a controlled time produces a trap rich region having a thickness in the range of 4 microns to 7 microns. In some embodiments, the high resistivity base layer has a thickness in the range of 550 to 650 microns. In some embodiments, the silicon dioxide layer has a thickness in the range of 2000 to 4000 angstroms. In some embodiments, a thickness of a portion of the second silicon wafer between the first side of the second silicon wafer and the cleavage surface of the second silicon wafer is in the range of 2000 to 3500 angstroms. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Other objects and advantages of the present invention, among other benefits and improvements of the disclosed invention, will become apparent from the following description taken in conjunction with the accompanying drawings. Detailed embodiments of the present invention are disclosed herein. However, it will be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Moreover, each of the examples given in connection with various embodiments of the present invention are intended to be illustrative and not limiting.

[0018] Throughout this specification and the claims, the following terms take on the meanings expressly associated therewith, unless the context clearly dictates otherwise. As used herein, the terms "in one embodiment," "in an embodiment," and "in some embodiments" may refer to the same embodiment, but do not necessarily refer to the same embodiment. Furthermore, as used herein, the terms "in another embodiment" and "in some other embodiments" may refer to different embodiments, but do not necessarily refer to different embodiments. Thus, as described below, various embodiments of the invention can be readily combined without departing from the scope or spirit of the invention.

[0019] As used herein, the term "based on" is not exclusive and allows for based on additional unrecited factors unless the context clearly dictates otherwise. Additionally, throughout this specification, the meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0020] Unless otherwise defined, all terms (including technical and scientific terms used herein) have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant art and this disclosure, and should not be interpreted in an ideal or overly formal sense unless expressly defined.

[0021] This disclosure describes exemplary embodiments of a miniaturized, wearable infusion device, although it will be apparent to those skilled in the art that the general principles embodied in the exemplary device may be embodied in other devices.

[0022] As used herein, the term "trap rich layer" or "trap rich region" refers to a layer or region that has a high density of electrically active carrier traps. Incorporation of a trap rich layer or region into an SOI substrate significantly reduces the lifetime and mobility of free charge carriers while preserving the effective resistance of the substrate. In some embodiments, the trap rich layer or region has a density of 10 10 cm 2 eV -1 In some embodiments, the trap rich layer or region has a trap density of greater than 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 In some embodiments, the trap rich layer or region has a trap density of 0.9×10 10 cm 2 eV -1 ~1.1×10 10 cm 2 eV -1 In some embodiments, the trap rich layer or region has a trap density of 10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 In some embodiments, the trap rich layer or region has a trap density of 10 10 cm 2 eV -1 ~1.5×10 10 cm 2 eV -1 In some embodiments, the trap rich layer or region has a trap density of 10 10 cm2 eV -1 ~2×10 10 cm 2 eV -1 In some embodiments, the trap rich layer or region has a trap density of 0.5×10 10 cm 2 eV -1 ~10 10 cm 2 eV -1 has a trap density of

[0023] FIG. 1 shows a schematic diagram of a first exemplary device 100. In some embodiments, the device 100 may be referred to as a silicon-on-insulator ("SOI") substrate. In some embodiments, the device 100 has a layered structure. In some embodiments, the device 100 includes a handle wafer 110 having a first side 112 and a second side 114 opposite the first side 112. In some embodiments, the handle wafer 110 includes high resistivity silicon. In some embodiments, the handle wafer 110 includes another suitable high resistivity material. In some embodiments, the handle wafer 110 includes a material having a resistivity in the range of 50 to 100 ohm meters. In some embodiments, the handle wafer has a thickness in the range of 500 to 700 microns.

[0024] In some embodiments, the device 100 includes a trap rich layer 120 having a first side 122 and a second side 124 opposite the first side 122. In some embodiments, the trap rich layer 120 is disposed adjacent to the handle wafer 110 such that the first side 122 of the trap rich layer 120 abuts the second side 114 of the handle wafer 110. In some embodiments, the trap rich layer 120 includes silicon nitride (or silicon nitride or silicon nitride). In some embodiments, the trap rich layer 120 includes a silicon nitride layer disposed adjacent to the handle wafer 110. In some embodiments, the trap rich layer 120 has a thickness in the range of 100 to 1000 angstroms. In some embodiments, the trap rich layer 120 has a thickness in the range of 100 to 400 angstroms. In some embodiments, the trap rich layer 120 has a thickness in the range of 400 to 700 angstroms. In some embodiments, the trap rich layer 120 has a thickness in the range of 700-1000 angstroms. In some embodiments, the trap rich layer 120 has a thickness in the range of 100-700 angstroms. In some embodiments, the trap rich layer 120 has a thickness in the range of 400-1000 angstroms. In some embodiments, a change in the thickness of the trap rich layer 120 results in a corresponding change in the frequency separation value of an RF device fabricated using the device 100. In some embodiments, an increase in the thickness of the trap rich layer 120 results in an increase in the resistivity of the trap rich layer 120, thereby providing a corresponding increase in the frequency separation of an RF device fabricated using the device 100. In some embodiments, conversely, a decrease in the thickness of the trap rich layer 120 results in a decrease in the resistivity of the trap rich layer 120, thereby providing a corresponding decrease in the frequency separation of an RF device fabricated using the device 100.

[0025] In some embodiments, the device 100 includes a silicon dioxide (or silicon dioxide or silicon oxide; silicon dioxide) ("SiO2") layer 130 having a first side 132 and a second side 134 opposite the first side 132. In some embodiments, the SiO2 layer 130 is positioned adjacent to the trap rich layer 120 such that the first side 132 of the SiO2 layer 130 abuts the second side 124 of the trap rich layer 120. In some embodiments, the SiO2 layer 130 has a thickness in the range of 1000-5000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 1000-2000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 2000-3000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 3000-4000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 4000-5000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 1000-3000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 2000-4000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 3000-5000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 1000-4000 angstroms. In some embodiments, the SiO2 layer 130 has a thickness in the range of 2000-5000 angstroms. In some embodiments, a change in the thickness of the SiO2 layer 130 results in a corresponding change in the resistivity and capacitance of the SiO2 layer 130. In some embodiments, an increase in the thickness of the SiO2 layer 130 results in an increase in the resistivity of the SiO2 layer 130 and a decrease in the capacitance of the SiO2 layer 130. Conversely, in some embodiments, a decrease in the thickness of the SiO 2 layer 130 results in a decrease in the resistivity of the SiO 2 layer 130 and an increase in the capacitance of the SiO 2 layer 130.In some embodiments, an increase in resistance caused by an increase in the resistivity of the SiO2 layer 130 has the effect of increasing the time it takes for a signal to reach the voltage threshold (i.e., a slower "on" speed), while a decrease in resistance caused by a decrease in the resistivity of the SiO2 layer 130 has the effect of decreasing the time it takes for a signal to reach the voltage threshold (i.e., a faster "on" speed). In some embodiments, an increase in the capacitance of the SiO2 layer 130 has the effect of increasing the time it takes for a decreasing signal to bleed off to the point where it is lower than the voltage threshold (i.e., a slower "off" speed), while a decrease in the capacitance of the SiO2 layer 130 has the effect of decreasing the time it takes for a decreasing signal to bleed off to the point where it is lower than the voltage threshold (i.e., a faster "off" speed). In some embodiments, an amplifier made using a device 100 with faster "on" and "off" speeds will have a higher operating speed.

[0026] In some embodiments, the device 100 includes a transfer layer 140 having a first side 142 and a second side 144 opposite the first side 142. In some embodiments, the transfer layer 140 is disposed adjacent to the SiO2 layer 130 such that the first side 142 of the transfer layer 140 abuts the second side 134 of the SiO2 layer 130. In some embodiments, the transfer layer 140 has a thickness in the range of 500 to 5000 angstroms. In some embodiments, the transfer layer 140 has a thickness in the range of 500 to 2000 angstroms. In some embodiments, the transfer layer 140 has a thickness in the range of 2000 to 3500 angstroms. In some embodiments, the transfer layer 140 has a thickness in the range of 3500 to 5000 angstroms. In some embodiments, the transfer layer 140 has a thickness in the range of 500 to 3500 angstroms. In some embodiments, transfer layer 140 has a thickness in the range of 2000-5000 angstroms. In some embodiments, increasing the thickness of transfer layer 140 results in an increase in the voltage threshold of an RF device fabricated using device 100. Conversely, in some embodiments, decreasing the thickness of transfer layer 140 results in a decrease in the voltage threshold of an RF device fabricated using device 100. In some embodiments, transfer layer 140 comprises a silicon wafer.

[0027] FIG. 2 shows a flow chart of an exemplary method 200 for fabricating device 100. FIGS. 3A-3H show various intermediate products present during the performance of exemplary method 200, and FIG. 3I shows the final product from the performance of exemplary method 200. In step 210, a first silicon wafer and a second silicon wafer are provided. In some embodiments, the thickness of each of the first silicon wafer and the second silicon wafer ranges from 500 to 700 microns. In some embodiments, the first silicon wafer is referred to herein as a handle wafer. As described above with reference to FIG. 1, in some embodiments, the handle wafer is high resistivity silicon. FIG. 3A shows a schematic diagram of the first silicon wafer and the second silicon wafer provided in step 210.

[0028] In step 220, a silicon nitride layer is deposited on the handle wafer provided in step 210. In some embodiments, the silicon nitride layer is deposited using a high density plasma chemical vapor deposition ("HDPCVD") process. It will be understood by those skilled in the art that HDPCVD is a specific form of plasma enhanced chemical vapor deposition ("PECVD") that uses either an inductively coupled plasma ("ICP") source or an electron cyclotron resonance source to generate a higher plasma density than standard PECVD systems. In some embodiments, the HDPCVD process of step 220 is performed using an ICP source. In some embodiments, the HDPCVD process of step 220 is performed by introducing a mixture of multiple gas flows to the handle wafer. In some embodiments, the gas mixture includes a flow of nitrogen (e.g., N2) gas, a flow of silane (e.g., SiH4), and a flow of argon (e.g., Ar). In some embodiments, the relative flow rates of N2 gas, silane gas, and argon gas are varied to control the properties of the deposited film, such as the refractive index. For example, in some embodiments, a 1:1 flow ratio between N2 gas and silane gas provides a refractive index of 1.46, and this ratio can be varied to increase or decrease the refractive index. In some embodiments, increasing the flow rate of silane gas relative to the flow rate of N2 gas increases the silicon content of the silicon nitride layer, thereby decreasing the refractive index of the deposited film. Conversely, in some embodiments, decreasing the flow rate of silane gas relative to the flow rate of N2 gas decreases the silicon content of the silicon nitride layer, thereby increasing the refractive index of the deposited film. FIG. 3B shows a schematic diagram of the first and second silicon wafers with the silicon nitride layer deposited thereon after performance of step 220.

[0029] In some embodiments, the HDPCVD process of step 220 is performed using a configured pressure. In some embodiments, the pressure is between 5 mTorr and 20 mTorr. In some embodiments, the pressure is between 5 mTorr and 10 mTorr. In some embodiments, the pressure is between 10 mTorr and 15 mTorr. In some embodiments, the pressure is between 15 mTorr and 20 mTorr. In some embodiments, the pressure is between 5 mTorr and 15 mTorr. In some embodiments, the pressure is between 10 mTorr and 20 mTorr. In some embodiments, the pressure is between 7.5 mTorr and 12.5 mTorr. In some embodiments, the pressure is between 9 mTorr and 11 mTorr. In some embodiments, the pressure is about 10 mTorr. In some embodiments, the pressure is 10 mTorr. In some embodiments, the pressure is between 10 mTorr and 14 mTorr. In some embodiments, the pressure is between 11 mTorr and 13 mTorr. In some embodiments, the pressure is about 12 mTorr. In some embodiments, the pressure is 12 mTorr. In some embodiments, varying the pressure can vary the degree of uniformity of the film. For example, in some embodiments, a pressure of 12 mTorr produces a generally uniform film with about 1% non-uniformity and a slight bias toward the center of the wafer. In some embodiments, varying the pressure can change the rate from center to edge, thereby allowing the uniformity to be adjusted. In some embodiments, a change in pressure results in a corresponding change in the Debye sphere, the area (or sphere) of influence outside of which the charge is shielded. In some embodiments, an increase in the pressure used during the HDPCVD process of step 220 produces a larger Debye sphere, resulting in an increased deposition rate at the edge compared to the center. Conversely, in some embodiments, a decrease in the pressure used during the HDPCVD process of step 220 produces a smaller Debye sphere, resulting in a decreased deposition rate at the edge compared to the center. As a result, in some embodiments, the pressure used during the HDPCVD process of step 220 can be adjusted to adjust the uniformity of the deposited film.

[0030] In some embodiments, the HDPCVD process of step 220 is performed with an ICP source operating at a configured ICP power. In some embodiments, the ICP power is between 65 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 105 watts. In some embodiments, the ICP power is between 105 watts and 145 watts. In some embodiments, the ICP power is between 145 watts and 185 watts. In some embodiments, the ICP power is between 185 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 145 watts. In some embodiments, the ICP power is between 105 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, the ICP power is between 6 ...145 watts and 225 watts. In some embodiments, varying the ICP power varies the degree of uniformity of the film. In some embodiments, a change in ICP power results in a corresponding change to the Debye sphere, which is the area of ​​influence and outside of which the charge is shielded. In some embodiments, an increase in the ICP power used during the HDPCVD process of step 220 produces a smaller Debye sphere, thereby resulting in a decrease in the deposition rate at the edge compared to the center. Conversely, in some embodiments, a decrease in the ICP power used during the HDPCVD process of step 220 produces a larger Debye sphere, thereby increasing the deposition rate at the edge compared to the center. As a result, in some embodiments, the ICP power used during the HDPCVD process of step 220 can be adjusted to adjust the uniformity of the deposited film.

[0031] In some embodiments, the HDPCVD process of step 220 is performed with a configured bias power. In some embodiments, the bias power is between 0 and 100 watts. In some embodiments, the bias power is between 0 and 25 watts. In some embodiments, the bias power is between 25 and 50 watts. In some embodiments, the bias power is between 50 and 75 watts. In some embodiments, the bias power is between 75 and 100 watts. In some embodiments, the bias power is between 0 and 50 watts. In some embodiments, the bias power is between 25 and 75 watts. In some embodiments, the bias power is between 50 and 100 watts. In some embodiments, the bias power is between 0 and 75 watts. In some embodiments, the bias power is between 25 ... varying the bias power changes the density of the film. In some embodiments, varying the bias power changes the percentage of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, increasing the bias power increases the velocity of hydrogen in the plasma state, thereby producing a film with a lower hydrogen content. In some embodiments, conversely, decreasing the bias power decreases the velocity of hydrogen in the plasma state, thereby producing a film with a higher hydrogen content. In some embodiments, changing the bias power changes the uniformity of the film. In some embodiments, increasing the bias power increases the electrode field generated from the bottom electrode, thereby increasing the uniformity of the film. In some embodiments, conversely, decreasing the bias power decreases the electrode field generated from the bottom electrode, thereby decreasing the uniformity of the film.

[0032] In some embodiments, the HDPCVD process of step 220 is performed with the handle wafer held at a configured temperature. In some embodiments, the temperature is between 100 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 150 degrees Celsius. In some embodiments, the temperature is between 150 and 200 degrees Celsius. In some embodiments, the temperature is between 200 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 200 degrees Celsius. In some embodiments, the temperature is between 150 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 200 degrees Celsius. In some embodiments, the temperature is between 150 and 250 degrees Celsius. In some embodiments, varying the temperature of the handle wafer changes the percentage of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, increasing the temperature of the handle wafer decreases the hydrogen content of the film. Conversely, in some embodiments, decreasing the temperature of the handle wafer increases the hydrogen content of the film. In some embodiments, varying the handle wafer temperature changes the deposition rate of the film. In some embodiments, increasing the temperature of the handle wafer reduces the RF energy required to decompose the silane gas into silicon and hydrogen, increasing the time for recombination, thereby increasing the deposition rate. Conversely, in some embodiments, decreasing the temperature of the handle wafer increases the RF energy required to decompose the silane gas into silicon and hydrogen, decreasing the time for recombination, thereby decreasing the deposition rate.

[0033] In some embodiments, the HDPCVD process of step 220 is performed with the flow rate of N2 gas at a configured flow rate. In some embodiments, the flow rate of N2 gas is in the range of 20-35 standard cubic centimeters per minute (sccm). In some embodiments, the flow rate of N2 gas is in the range of 20-25 sccm. In some embodiments, the flow rate of N2 gas is in the range of 25-30 sccm. In some embodiments, the flow rate of N2 gas is in the range of 30-35 sccm. In some embodiments, the flow rate of N2 gas is in the range of 20-30 sccm. In some embodiments, the flow rate of N2 gas is in the range of 25-35 sccm.

[0034] In some embodiments, the HDPCVD process of step 220 is performed with the flow rate of silane gas at the configured flow rate. In some embodiments, the flow rate of silane gas is in the range of 20-35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20-25 sccm. In some embodiments, the flow rate of silane gas is in the range of 25-30 sccm. In some embodiments, the flow rate of silane gas is in the range of 30-35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20-30 sccm. In some embodiments, the flow rate of silane gas is in the range of 25-35 sccm.

[0035] In some embodiments, the HDPCVD process of step 220 is performed with the flow rate of argon gas at the configured flow rate. In some embodiments, the flow rate of argon gas is in the range of 20-35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20-25 sccm. In some embodiments, the flow rate of argon gas is in the range of 25-30 sccm. In some embodiments, the flow rate of argon gas is in the range of 30-35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20-30 sccm. In some embodiments, the flow rate of argon gas is in the range of 25-35 sccm.

[0036] In some embodiments, the parameters of the HDPCVD process of step 220 are configured to provide a controlled deposition rate of the silicon nitride layer on the handle wafer. In some embodiments, the deposition rate of the silicon nitride layer is between 300 and 500 Angstroms / minute. In some embodiments, the deposition rate of the silicon nitride layer is between 350 and 450 Angstroms / minute. In some embodiments, the deposition rate of the silicon nitride layer is between 375 and 425 Angstroms / minute. In some embodiments, the deposition rate of the silicon nitride layer is about 400 Angstroms / minute. In some embodiments, the deposition rate of the silicon nitride layer is 400 Angstroms / minute.

[0037] In some embodiments, the parameters of the HDPCVD process of step 220 are configured to provide a controlled thickness of the silicon nitride layer on the handle wafer. In some embodiments, the parameters of the HDPCVD process of step 220 are configured to provide a silicon nitride layer thickness that is between 300 and 500 angstroms. In some embodiments, the silicon nitride layer thickness is between 350 and 450 angstroms. In some embodiments, the silicon nitride layer thickness is between 375 and 425 angstroms. In some embodiments, the silicon nitride layer thickness is about 400 angstroms. In some embodiments, the silicon nitride layer thickness is 400 angstroms. In some embodiments, the HDPCVD process of step 220 is performed for 1 minute.

[0038] With continued reference to FIG. 2, in step 230, a silicon dioxide layer is deposited on the handle wafer to cover the silicon nitride layer deposited in step 220. In some embodiments, the silicon dioxide layer is deposited by using a HDPCVD process. In some embodiments, the HDPCVD process of step 230 is performed using an ICP source. In some embodiments, the HDPCVD process of step 230 is performed by introducing a mixture of multiple gas flows to the handle wafer with the deposited silicon nitride layer. In some embodiments, the gas mixture includes a flow of oxygen gas (e.g., O 2 ), a flow of silane (e.g., SiH 4 ), and a flow of argon (e.g., Ar). In some embodiments, the HDPCVD process of step 230 is substantially a continuation of the HDPCVD process of step 220, but due to the substitution of oxygen gas used in step 230 for the nitrogen gas used in step 220. FIG. 3C shows a schematic diagram of the first silicon wafer with silicon nitride and silicon dioxide deposited thereon and the second silicon wafer after the performance of step 230.

[0039] In some embodiments, the HDPCVD process of step 230 is performed with a configured pressure. In some embodiments, the pressure is between 5 mTorr and 20 mTorr. In some embodiments, the pressure is between 5 mTorr and 10 mTorr. In some embodiments, the pressure is between 10 mTorr and 15 mTorr. In some embodiments, the pressure is between 15 mTorr and 20 mTorr. In some embodiments, the pressure is between 5 mTorr and 15 mTorr. In some embodiments, the pressure is between 10 mTorr and 20 mTorr. In some embodiments, varying the pressure can change the degree of uniformity of the film. For example, in some embodiments, a pressure of 12 mTorr produces a generally uniform film with about 1% non-uniformity and a slight bias toward the center of the wafer. In some embodiments, varying the pressure can change the center-to-edge velocity, which can allow for tuning the uniformity. In some embodiments, the change in pressure results in a corresponding change in the Debye sphere, which is the range of influence, outside of which the charge is shielded. In some embodiments, increasing the pressure used during the HDPCVD process of step 230 produces larger Debye spheres, thereby resulting in an increased deposition rate at the edges compared to the center. Conversely, in some embodiments, decreasing the pressure used during the HDPCVD process of step 230 produces smaller Debye spheres, thereby resulting in a decreased deposition rate at the edges compared to the center. As a result, in some embodiments, the pressure used during the HDPCVD process of step 230 can be adjusted to adjust the uniformity of the deposited film.

[0040] In some embodiments, the HDPCVD process of step 230 is performed with an ICP source operating at a configured ICP power. In some embodiments, the ICP power is between 65 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 105 watts. In some embodiments, the ICP power is between 105 watts and 145 watts. In some embodiments, the ICP power is between 145 watts and 185 watts. In some embodiments, the ICP power is between 185 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 145 watts. In some embodiments, the ICP power is between 105 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, the ICP power is between 6 ... varied to vary the degree of uniformity of the film. In some embodiments, a change in ICP power results in a corresponding change to the Debye sphere, which is the area of ​​influence outside of which the charge is shielded. In some embodiments, an increase in the ICP power used during the HDPCVD process of step 230 produces a smaller Debye sphere, thereby resulting in a decrease in the deposition rate at the edge compared to the center. Conversely, in some embodiments, a decrease in the ICP power used during the HDPCVD process of step 230 produces a larger Debye sphere, thereby resulting in an increase in the deposition rate at the edge compared to the center. As a result, in some embodiments, the ICP power used during the HDPCVD process of step 230 can be adjusted to adjust the uniformity of the deposited film.

[0041] In some embodiments, the HDPCVD process of step 230 is performed with a bias power configured. In some embodiments, the bias power is between 0 watts and 100 watts. In some embodiments, the bias power is between 0 watts and 25 watts. In some embodiments, the bias power is between 25 watts and 50 watts. In some embodiments, the bias power is between 50 watts and 75 watts. In some embodiments, the bias power is between 75 watts and 100 watts. In some embodiments, the bias power is between 0 watts and 50 watts. In some embodiments, the bias power is between 25 watts and 75 watts. In some embodiments, the bias power is between 50 watts and 100 watts. In some embodiments, the bias power is between 0 watts and 75 watts. In some embodiments, the bias power is between 25 ... varying the bias power changes the density of the film. In some embodiments, varying the bias power changes the percentage of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, increasing the bias power increases the velocity of hydrogen in the plasma state, thereby producing a film with a lower hydrogen content. In some embodiments, conversely, decreasing the bias power decreases the velocity of hydrogen in the plasma state, thereby producing a film with a higher hydrogen content. In some embodiments, varying the bias power varies the uniformity of the film. In some embodiments, increasing the bias power increases the electrode field generated from the bottom electrode, thereby increasing the uniformity of the film. In some embodiments, conversely, decreasing the bias power decreases the electrode field generated from the bottom electrode, thereby decreasing the uniformity of the film.

[0042] In some embodiments, the HDPCVD process of step 230 is performed with the handle wafer held at a configured temperature. In some embodiments, the temperature is between 100 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 150 degrees Celsius. In some embodiments, the temperature is between 150 and 200 degrees Celsius. In some embodiments, the temperature is between 200 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 200 degrees Celsius. In some embodiments, the temperature is between 150 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 200 degrees Celsius. In some embodiments, the temperature is between 150 and 250 degrees Celsius. In some embodiments, varying the handle wafer temperature changes the percentage of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, increasing the temperature of the handle wafer decreases the hydrogen content of the film. In some embodiments, conversely, decreasing the temperature of the handle wafer increases the hydrogen content of the film. In some embodiments, varying the handle wafer temperature results in a change in the deposition rate of the film. In some embodiments, increasing the temperature of the handle wafer reduces the RF energy required to decompose the silane gas into silicon and hydrogen, increasing the time for recombination, thereby increasing the deposition rate. Conversely, in some embodiments, decreasing the temperature of the handle wafer increases the RF energy required to decompose the silane gas into silicon and hydrogen, decreasing the time for recombination, thereby decreasing the deposition rate.

[0043] In some embodiments, the HDPCVD process of step 230 is performed with the flow rate of O2 gas at the configured flow rate. In some embodiments, the flow rate of O2 gas is in the range of 20-35 sccm. In some embodiments, the flow rate of O2 gas is in the range of 20-25 sccm. In some embodiments, the flow rate of O2 gas is in the range of 25-30 sccm. In some embodiments, the flow rate of O2 gas is in the range of 30-35 sccm. In some embodiments, the flow rate of O2 gas is in the range of 20-30 sccm. In some embodiments, the flow rate of O2 gas is in the range of 25-35 sccm.

[0044] In some embodiments, the HDPCVD process of step 230 is performed with the flow rate of silane gas at the configured flow rate. In some embodiments, the flow rate of silane gas is in the range of 20-35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20-25 sccm. In some embodiments, the flow rate of silane gas is in the range of 25-30 sccm. In some embodiments, the flow rate of silane gas is in the range of 30-35 sccm. In some embodiments, the flow rate of silane gas is in the range of 20-30 sccm. In some embodiments, the flow rate of silane gas is in the range of 25-35 sccm.

[0045] In some embodiments, the HDPCVD process of step 230 is performed with the flow rate of argon gas at the configured flow rate. In some embodiments, the flow rate of argon gas is in the range of 20-35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20-25 sccm. In some embodiments, the flow rate of argon gas is in the range of 25-30 sccm. In some embodiments, the flow rate of argon gas is in the range between 30-35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20-30 sccm. In some embodiments, the flow rate of argon gas is in the range of 25-35 sccm.

[0046] In some embodiments, the parameters of the HDPCVD process of step 230 are configured to provide a controlled deposition rate of the silicon dioxide layer on the handle wafer. In some embodiments, the deposition rate of the silicon dioxide layer is between 900 and 1100 Angstroms / minute. In some embodiments, the deposition rate of the silicon dioxide layer is between 950 and 1050 Angstroms / minute. In some embodiments, the deposition rate of the silicon dioxide layer is between 975 and 1025 Angstroms / minute. In some embodiments, the deposition rate of the silicon dioxide layer is about 1000 Angstroms / minute. In some embodiments, the deposition rate of the silicon dioxide layer is 1000 Angstroms / minute.

[0047] In some embodiments, the parameters of the HDPCVD process of step 230 are configured to provide a controlled thickness of the silicon dioxide layer on the handle wafer. In some embodiments, the thickness of the silicon dioxide layer is between 1500 and 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 1500 and 2000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 2000 and 2500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 2500 and 3000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 3000 and 3500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 3500 and 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 4000 and 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 4500 and 5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 1500-2500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2000-3000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2500-3500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 3000-4000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 3500-4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 4000-5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 1500-3000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2000-3500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2500-4000 angstroms. In some embodiments, the silicon dioxide layer has a thickness between 3000 and 4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness between 3500 and 5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness between 1500 and 3500 angstroms.In some embodiments, the silicon dioxide layer has a thickness of 2000-4000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2500-4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 3000-5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 1500-4000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2000-4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2500-5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 1500-4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2000-5000 angstroms. In some embodiments, the HDPCVD process of step 230 is performed for between 2 minutes and 3 minutes to achieve a controlled thickness of the silicon dioxide layer.

[0048] With continued reference to FIG. 2, in step 240, hydrogen implants are implanted into the second wafer. In some embodiments, the hydrogen implants are positioned to define a cleave plane in the second wafer. In some embodiments, the cleave plane defines a desired thickness of the second silicon wafer after completion of method 200. In some embodiments, the hydrogen implants are implanted using an ion implanter. In some embodiments, the ion implanter is an ion implanter such as those commercialized by Nissin Ion Equipment Co., Ltd. of Kyoto, Japan. In some embodiments, the ion implanter is configured to emit a beam of hydrogen ions. In some embodiments, the ion implanter is configured to operate with a power of 5000 volts to 1 megavolts. In some embodiments, the desired thickness is in the range of 500 to 5000 angstroms. In some embodiments, the desired thickness is in the range of 500 to 2000 angstroms. In some embodiments, the desired thickness is in the range of 2000 to 3500 angstroms. In some embodiments, the desired thickness is in the range of 3500 to 5000 angstroms. In some embodiments, the desired thickness is in the range of 500-3500 angstroms. In some embodiments, the desired thickness is in the range of 2000-5000 angstroms. In some embodiments, the implanted hydrogen creates displacement defects in the form of interstitials, vacancies, and complexes. In some embodiments, such defects create regions with a large number of broken bonds called platelets. In some embodiments, hydrogen is trapped at these surfaces, passivating the broken bonds. FIG. 3D shows a schematic diagram of the first silicon wafer with the silicon nitride and silicon dioxide layers deposited thereon and the second silicon wafer with the hydrogen implant after performance of step 240.

[0049] With continued reference to FIG. 2, in step 250, the surface of the silicon dioxide layer deposited in step 230 is activated. In some embodiments, the activation is plasma activation performed by bombarding the surface of the silicon dioxide layer with short-lived species generated in the plasma volume to initiate chemical reactions at the surface and allow bonding. In some embodiments, the activation is low pressure plasma activated bonding at pressures in the range of 0.1-100 Pa. FIG. 3E shows a schematic diagram of a first silicon wafer with a silicon nitride and activated silicon dioxide layer deposited thereon and a second silicon wafer with hydrogen implants after performance of step 250.

[0050] 2, in step 260, the first silicon wafer (on which the silicon nitride and silicon dioxide layers are deposited) is bonded to a second silicon wafer with the activated surface of the silicon dioxide layer facing the second silicon wafer and oriented such that after cleaving along the cleavage plane defined by the hydrogen implantation, a desired portion of the second silicon wafer (i.e., a portion having the thickness described above) remains adjacent to the first silicon wafer. Figure 3F shows a schematic diagram of bonding the first silicon wafer with the silicon nitride and activated silicon dioxide layers deposited thereon to the second silicon wafer with the hydrogen implantation, in accordance with the implementation of step 260.

[0051] With continued reference to FIG. 2, in step 270, the bonded first and second silicon wafers are subjected to a low temperature annealing process. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 250 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 degrees Celsius to 300 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 300 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 350 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 300 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 300 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 degrees Celsius to 400 degrees Celsius. In some embodiments, the duration of the annealing process ranges from 1 hour to 8 hours. In some embodiments, during the annealing process, the trapped hydrogen described above with reference to step 240 dissociates from the complex and diffuses into the platelets to form H2 molecules. In some embodiments, the increase in pressure causes the platelets to expand in the microscopic cracks that bond them together in the same plane, causing delamination of the material. FIG. 3G shows a schematic diagram of the annealing process of step 270.

[0052] With continued reference to FIG. 2, in step 280, the bonded first and second silicon wafers are placed under tension (i.e., tension is applied to pull the first and second silicon wafers apart from one another). In some embodiments, the tension is sufficient to generate a tension in the range of 10-60 pounds per square inch across the bonded area. FIG. 3H shows a schematic diagram of the tensioning process of step 280.

[0053] With continued reference to FIG. 2, in step 290, the second silicon wafer is struck at the cleavage plane defined by the hydrogen implant. In some embodiments, the second silicon wafer is struck with a thin blade-like element with a force in the range of 5-10 pounds per square inch across the target area to generate a peel wave. In some embodiments, the thin blade-like element is any suitable object having a suitable width. In some embodiments, a suitable width is about 50 microns. As a result of this strike, a portion of the second silicon wafer (which may be referred to herein as the "donor wafer") disposed between the hydrogen implant and the first silicon wafer remains attached to the first silicon wafer (which may be referred to herein as the "handle wafer"), while the remaining portion of the second silicon wafer is cleaved. Following this cleaving step, a final finished wafer is produced. FIG. 3I shows a schematic diagram of the finished wafer and the removed portion of the second silicon wafer after performance of step 290.

[0054] FIG. 4 illustrates a schematic diagram of a second exemplary device 400. In some embodiments, the device 400 may be referred to as a silicon-on-insulator ("SOI") substrate. In some embodiments, the device 400 has a layered structure. In some embodiments, the device 400 includes a handle wafer 410 having a first side 412 and a second side 414 opposite the first side 412. In some embodiments, the handle wafer 410 includes high resistivity silicon. In some embodiments, the handle wafer 410 includes another suitable high resistivity material. In some embodiments, the handle wafer 410 includes a material having a resistivity in the range of 50-100 ohm-meters. In some embodiments, the handle wafer has a thickness in the range of 500-700 microns. In some embodiments, the handle wafer has a thickness in the range of 550-650 microns.

[0055] In some embodiments, the device 400 includes a trap rich layer 420 having a first side 422 and a second side 424 opposite the first side 422. In some embodiments, the trap rich layer 420 is positioned within the handle wafer 410 such that the first side 422 of the trap rich layer 420 is positioned between the first side 412 and the second side 414 of the handle wafer 410 and the second side 424 of the trap rich layer 420 is positioned on the second side 414 of the handle wafer 410. In some embodiments, the trap rich layer 420 includes arsenic. In some embodiments, the trap rich layer 420 includes diffused arsenic. In some embodiments, the trap rich layer 420 includes a trap rich arsenic region disposed within the handle wafer 510 (e.g., diffused on its second side 414), e.g., a region where arsenic is interspersed within the crystal structure of the handle wafer 410. In some embodiments, the trap rich layer 420 has a thickness in the range of 1 to 10 microns. In some embodiments, the trap rich layer 420 has a thickness in the range of 1-4 microns. In some embodiments, the trap rich layer 420 has a thickness in the range of 4-7 microns. In some embodiments, the trap rich layer 420 has a thickness in the range of 7-10 microns. In some embodiments, the trap rich layer 420 has a thickness in the range of 1-7 microns. In some embodiments, the trap rich layer 420 has a thickness in the range of 4-10 microns. In some embodiments, a change in the thickness of the trap rich layer 420 results in a corresponding change in the charge dissipation of the trap rich layer 420. In some embodiments, the diffused arsenic forms broken bonds in the silicon lattice of the handle wafer, thereby resulting in faster dissipation paths and faster dissipation rates. As a result, in some embodiments, an increase in the thickness of the trap rich layer 420 results in a chip suitable for lower operating frequencies, where lower frequencies generate deeper current flows. Conversely, in some embodiments, a decrease in the thickness of the trap rich layer 420 results in a chip suitable for higher operating frequencies, where higher frequencies generate shallower current flows.

[0056] In some embodiments, the device 400 includes a silicon dioxide ("SiO2") layer 430 having a first side 432 and a second side 434 opposite the second side 432. In some embodiments, the SiO2 layer 430 is disposed adjacent to the trap rich layer 420 such that the first side 432 of the SiO2 layer 430 is adjacent to the second side 424 of the trap rich layer 420. In some embodiments, the SiO2 layer 430 has a thickness in the range of 1000-5000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 1000-2000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 2000-3000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 3000-4000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 4000-5000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 1000-3000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 2000-4000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 3000-5000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 1000-4000 angstroms. In some embodiments, the SiO2 layer 430 has a thickness in the range of 2000-5000 angstroms. In some embodiments, a change in the thickness of the SiO2 layer 430 results in a corresponding change in the resistivity and capacitance of the SiO2 layer 430. In some embodiments, an increase in the thickness of the SiO2 layer 430 results in an increase in the resistivity of the SiO2 layer 430 and a decrease in the capacitance of the SiO2 layer 430. In some embodiments, conversely, a decrease in the thickness of the SiO2 layer 430 results in a decrease in the resistivity of the SiO2 layer 430 and an increase in the capacitance of the SiO2 layer 430.In some embodiments, an increase in resistance caused by an increase in the resistivity of the SiO2 layer 430 has the effect of making it take longer for the signal to reach the voltage threshold (i.e., slower "on" speed), while a decrease in resistance caused by a decrease in the resistivity of the SiO2 layer 430 has the effect of making it take less time for the signal to reach the voltage threshold (i.e., faster "on" speed). In some embodiments, an increase in the capacitance of the SiO2 layer 430 has the effect of creating a longer time for a decreasing signal to bleed off to the point where it is below the voltage threshold (i.e., slower "off" speed), while a decrease in the capacitance of the SiO2 layer 430 has the effect of creating a shorter time for a decreasing signal to bleed off to the point where it is below the voltage threshold (i.e., faster "off" speed). In some embodiments, amplifiers made with devices 400 with faster "on" and "off" speeds have higher operating speeds.

[0057] In some embodiments, the device 400 includes a transfer layer 440 having a first side 442 and a second side 444 opposite the first side 442. In some embodiments, the transfer layer 440 is disposed adjacent to the SiO2 layer 430 such that the first side 442 of the transfer layer 440 is adjacent to the second side 434 of the SiO2 layer 430. In some embodiments, the transfer layer 440 has a thickness in the range of 500 to 5000 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 500 to 2000 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 2000 to 3500 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 3500 to 5000 angstroms. In some embodiments, the transfer layer 440 has a thickness in the range of 500 to 3500 angstroms. In some embodiments, transfer layer 440 has a thickness in the range of 2000-5000 angstroms. In some embodiments, an increase in the thickness of transfer layer 440 results in an increase in the voltage threshold of an RF device fabricated using device 400. Conversely, in some embodiments, a decrease in the thickness of transfer layer 440 results in a decrease in the voltage threshold of an RF device fabricated using device 400. In some embodiments, transfer layer 440 comprises a silicon wafer.

[0058] FIG. 5 shows a flow chart of an exemplary method 500 for fabricating device 400. FIGS. 6A-6H show various intermediate products present during the performance of exemplary method 500, and FIG. 6I shows the final product of the performance of exemplary method 500. In step 510, a first silicon wafer and a second silicon wafer are provided. In some embodiments, the thickness of each of the first silicon wafer and the second silicon wafer ranges from 500 to 700 microns. In some embodiments, the first silicon wafer is referred to herein as a handle wafer. As described above with reference to FIG. 4, in some embodiments, the handle wafer comprises high resistivity silicon. FIG. 6A shows a schematic diagram of the first silicon wafer and the second silicon wafer provided in step 510.

[0059] In step 520, an arsenic layer is diffused into the handle wafer provided in step 510. In some embodiments, the arsenic layer is applied by spin-coating a liquid colloidal solution containing arsenic onto the handle wafer, followed by diffusing the arsenic into the handle wafer. In some embodiments, the liquid colloidal solution comprises arsenic-doped glass. In some embodiments, the liquid colloidal solution is a solution commercialized under the trade name As-0200 by Desert Silicon, Inc., Tempe, Arizona. In some embodiments, the diffusion occurs for a controlled period of time and at a controlled temperature to produce a layer of diffused arsenic having a desired depth. In some embodiments, when a dopant (e.g., arsenic) is diffused into a silicon crystal (e.g., the handle wafer provided in step 510), the silicon crystal consists of a solid lattice of atoms through which the dopant needs to move. The dopant can continue to diffuse as long as the concentration gradient is balanced or until the temperature is reduced to such an extent that the dopant atoms can no longer move. As a result, a longer period of time during which diffusion is allowed to occur results in a diffused arsenic layer having a greater depth, and a higher controlled temperature during the diffusion process results in a diffused arsenic layer having a greater depth.

[0060] In some embodiments, the diffusion process of step 520 is performed using a configured temperature. In some embodiments, the temperature is between 700 degrees Celsius and 1200 degrees Celsius. In some embodiments, the temperature is between 800 degrees Celsius and 1200 degrees Celsius. In some embodiments, the temperature is between 900 degrees Celsius and 1200 degrees Celsius. In some embodiments, the temperature is between 1000 degrees Celsius and 1200 degrees Celsius. In some embodiments, the temperature is between 1100 degrees Celsius and 1200 degrees Celsius. In some embodiments, the temperature is between 700 degrees Celsius and 1100 degrees Celsius. In some embodiments, the temperature is between 800 degrees Celsius and 1100 degrees Celsius. In some embodiments, the temperature is between 900 degrees Celsius and 1100 degrees Celsius. In some embodiments, the temperature is between 1000 degrees Celsius and 1100 degrees Celsius. In some embodiments, the temperature is between 700 degrees Celsius and 1000 degrees Celsius. In some embodiments, the temperature is between 800 degrees Celsius and 1000 degrees Celsius. In some embodiments, the temperature is between 900 degrees Celsius and 1000 degrees Celsius. In some embodiments, the temperature is between 700 degrees Celsius and 900 degrees Celsius. In some embodiments, the temperature is between 800 degrees Celsius and 900 degrees Celsius. In some embodiments, the temperature is between 700 degrees Celsius and 800 degrees Celsius. In some embodiments, as described above, increasing the temperature increases the depth of the diffused arsenic layer, and decreasing the temperature decreases the depth of the diffused arsenic layer. As a result, in some embodiments, the temperature used during the diffusion process of step 520 can be adjusted to adjust the depth of the trap rich layer. Thereby, the properties (e.g., charge dissipation and frequency of the device as described above) depending on the depth of the trap rich layer can be adjusted.

[0061] In some embodiments, the diffusion process of step 520 is performed by diffusing arsenic for a configured period of time. In some embodiments, the period is between 5 hours and 20 hours. In some embodiments, the period is between 8 hours and 20 hours. In some embodiments, the period is between 11 hours and 20 hours. In some embodiments, the period is between 14 hours and 20 hours. In some embodiments, the period is between 17 hours and 20 hours. In some embodiments, the period is between 5 hours and 17 hours. In some embodiments, the period is between 8 hours and 17 hours. In some embodiments, the period is between 11 hours and 17 hours. In some embodiments, the period is between 14 hours and 17 hours. In some embodiments, the period is between 5 hours and 14 hours. In some embodiments, the period is between 8 hours and 14 hours. In some embodiments, the period is between 11 hours and 14 hours. In some embodiments, the period is between 5 hours and 11 hours. In some embodiments, the period is between 8 hours and 11 hours. In some embodiments, the period is between 5 hours and 8 hours. In some embodiments, as described above, an increase in the period during which diffusion occurs results in an increase in the depth of the diffused arsenic layer, while a decrease in the period during which diffusion occurs results in a decrease in the depth of the diffused arsenic layer. As a result, in some embodiments, the period during which diffusion occurs during the diffusion process of step 520 can be adjusted to adjust the depth of the trap rich layer. This can adjust the characteristics of the trap rich layer depending on the depth (e.g., charge dissipation and device frequency as described above). FIG. 6B shows a schematic diagram of a first silicon wafer with an arsenic layer diffused therein and a second silicon wafer after performing step 520. FIG. 7A shows an exemplary state (or rendering) of the arsenic concentration in the first silicon wafer after performing step 520. FIG. 7B shows a graph of the arsenic concentration versus depth for the exemplary state of FIG. 7A. It can be seen from FIGS. 7A and 7B that arsenic penetrates to a depth in the first silicon wafer (e.g., to a depth of 1 micron to 10 microns as described above) and that the concentration of arsenic is greatest at the surface of the first silicon wafer and decreases below the surface.

[0062] In some embodiments, arsenic is applied to the silicon wafer by ion implantation, rather than applying arsenic by coating it on the silicon wafer and diffusing it into the silicon wafer. In some embodiments, the ion implantation process includes projecting a beam of high-energy arsenic ions into the handle wafer provided in step 510. In some embodiments, the projection of such a beam causes the arsenic to penetrate and remain in the handle wafer. In some embodiments, collisions between the arsenic ions and atoms of the silicon lattice during such a process cause distortion and weakening of the crystal structure of the silicon. In some embodiments, an annealing step is performed following the projection of the beam of high-energy arsenic ions to address such distortion. FIG. 7C illustrates an exemplary state of arsenic concentration in the first silicon wafer after application by ion implantation. FIG. 7D illustrates a graph of arsenic concentration versus depth for the exemplary state of FIG. 7C. It can be seen from Figures 7C and 7D that the arsenic penetrates to a depth within the first silicon wafer (e.g., to a depth of 1 micron to 10 microns as described above), with the concentration of arsenic being greatest slightly below the surface and decreasing both toward the surface and further below the surface.

[0063] With continued reference to FIG. 5, in step 530, a silicon dioxide layer is deposited on the handle wafer to cover the arsenic layer diffused into the handle wafer in step 520. In some embodiments, the silicon dioxide layer is deposited by using a HDPCVD process. In some embodiments, the HDPCVD process of step 530 is performed using an inductively coupled plasma ("ICP") source. In some embodiments, the HDPCVD process of step 530 is performed by introducing a mixture of gas flows to the handle wafer with the arsenic layer diffused therein. In some embodiments, the gas mixture includes a flow of oxygen gas (e.g., O2), a flow of silane (e.g., SiH4), and a flow of argon (e.g., Ar). FIG. 6C shows a schematic diagram of the first silicon wafer with the arsenic layer diffused therein and the silicon dioxide layer deposited thereon after the performance of step 530, and the second silicon wafer.

[0064] In some embodiments, the HDPCVD process of step 530 is performed with a configured pressure. In some embodiments, the pressure is between 5 mTorr and 20 mTorr. In some embodiments, the pressure is between 5 mTorr and 10 mTorr. In some embodiments, the pressure is between 10 mTorr and 15 mTorr. In some embodiments, the pressure is between 15 mTorr and 20 mTorr. In some embodiments, the pressure is between 5 mTorr and 15 mTorr. In some embodiments, the pressure is between 10 mTorr and 20 mTorr. In some embodiments, the pressure is between 10 mTorr and 20 mTorr. In some embodiments, varying the pressure can change the degree of uniformity of the film. For example, in some embodiments, a pressure of 12 mTorr produces a generally uniform film with about 1% non-uniformity and a slight bias toward the center of the wafer. In some embodiments, varying the pressure can change the center-to-edge velocity, which can allow for tuning the uniformity. In some embodiments, the change in pressure results in a corresponding change in the Debye sphere, which is the area of ​​influence, outside of which the charge is shielded. In some embodiments, increasing the pressure used during the HDPCVD process of step 530 produces larger Debye spheres, thereby resulting in an increased deposition rate at the edges compared to the center. Conversely, in some embodiments, decreasing the pressure used during the HDPCVD process of step 530 produces smaller Debye spheres, thereby resulting in a decreased deposition rate at the edges compared to the center. As a result, in some embodiments, the pressure used during the HDPCVD process of step 530 can be adjusted to adjust the uniformity of the deposited film.

[0065] In some embodiments, the HDPCVD process of step 530 is performed with an ICP source operating at a configured ICP power. In some embodiments, the ICP power is between 65 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 105 watts. In some embodiments, the ICP power is between 105 watts and 145 watts. In some embodiments, the ICP power is between 145 watts and 185 watts. In some embodiments, the ICP power is between 185 watts and 225 watts. In some embodiments, the ICP power is between 65 watts and 145 watts. In some embodiments, the ICP power is between 105 watts and 185 watts. In some embodiments, the ICP power is between 145 watts and 225 watts. In some embodiments, the ICP power is between 6 ...145 watts and 225 watts. In some embodiments, the ICP power is changed to result in a change in the degree of film uniformity. In some embodiments, a change in ICP power results in a corresponding change to the Debye sphere, which is the area of ​​influence and outside of which the charge is shielded. In some embodiments, an increase in the ICP power used during the HDPCVD process of step 530 produces a smaller Debye sphere, thereby resulting in a decrease in the deposition rate at the edge compared to the center. Conversely, in some embodiments, a decrease in the ICP power used during the HDPCVD process of step 530 produces a larger Debye sphere, thereby resulting in an increase in the deposition rate at the edge compared to the center. As a result, in some embodiments, the ICP power used during the HDPCVD process of step 530 can be adjusted to adjust the uniformity of the deposited film.

[0066] In some embodiments, the HDPCVD process of step 530 is performed with a configured bias power. In some embodiments, the bias power is between 0 and 100 watts. In some embodiments, the bias power is between 0 and 25 watts. In some embodiments, the bias power is between 25 and 50 watts. In some embodiments, the bias power is between 50 and 75 watts. In some embodiments, the bias power is between 75 and 100 watts. In some embodiments, the bias power is between 0 and 50 watts. In some embodiments, the bias power is between 25 and 75 watts. In some embodiments, the bias power is between 50 and 100 watts. In some embodiments, the bias power is between 0 and 75 watts. In some embodiments, the bias power is between 25 and 100 watts. In some embodiments, the bias power is between 0 and 75 watts. In some embodiments, the bias power is between 25 and 100 watts. In some embodiments, varying the bias power changes the density of the film. In some embodiments, varying the bias power changes the percentage of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, increasing the bias power increases the velocity of hydrogen in the plasma state, thereby producing a film with a lower hydrogen content. In some embodiments, conversely, decreasing the bias power decreases the velocity of hydrogen in the plasma state, thereby producing a film with a higher hydrogen content. In some embodiments, varying the bias power varies the uniformity of the film. In some embodiments, increasing the bias power increases the electrode field generated from the bottom electrode, thereby increasing the uniformity of the film. In some embodiments, conversely, decreasing the bias power decreases the electrode field generated from the bottom electrode, thereby decreasing the uniformity of the film.

[0067] In some embodiments, the HDPCVD process of step 530 is performed with the handle wafer held at a configured temperature. In some embodiments, the temperature is between 100 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 150 degrees Celsius. In some embodiments, the temperature is between 150 and 200 degrees Celsius. In some embodiments, the temperature is between 200 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 200 degrees Celsius. In some embodiments, the temperature is between 150 and 250 degrees Celsius. In some embodiments, the temperature is between 100 and 200 degrees Celsius. In some embodiments, the temperature is between 150 and 250 degrees Celsius. In some embodiments, varying the handle wafer temperature changes the percentage of hydrogen in the deposited film, thereby changing the density of the deposited film. In some embodiments, films with lower hydrogen content are denser and films with higher hydrogen content are less dense. In some embodiments, increasing the temperature of the handle wafer decreases the hydrogen content of the film. Conversely, in some embodiments, decreasing the temperature of the handle wafer increases the hydrogen content of the film. In some embodiments, varying the handle wafer temperature changes the deposition rate of the film. In some embodiments, increasing the temperature of the handle wafer reduces the RF energy required to decompose the silane gas into silicon and hydrogen, increasing the time for recombination, thereby increasing the deposition rate. Conversely, in some embodiments, decreasing the temperature of the handle wafer increases the RF energy required to decompose the silane gas into silicon and hydrogen, decreasing the time for recombination, thereby decreasing the deposition rate.

[0068] In some embodiments, the HDPCVD process of step 530 is performed with the flow rate of O2 gas at the configured flow rate. In some embodiments, the flow rate of O2 gas is in the range of 20-35 sccm. In some embodiments, the flow rate of O2 gas is in the range of 20-25 sccm. In some embodiments, the flow rate of O2 gas is in the range of 25-30 sccm. In some embodiments, the flow rate of O2 gas is in the range of 30-35 sccm. In some embodiments, the flow rate of O2 gas is in the range between 20-30 sccm. In some embodiments, the flow rate of O2 gas is in the range of 25-35 sccm.

[0069] In some embodiments, the HDPCVD process of step 530 is performed with the silane gas flow rate at the configured flow rate. In some embodiments, the silane gas flow rate is in the range of 20-35 sccm. In some embodiments, the silane gas flow rate is in the range of 20-25 sccm. In some embodiments, the silane gas flow rate is in the range of 25-30 sccm. In some embodiments, the silane gas flow rate is in the range of 30-35 sccm. In some embodiments, the silane gas flow rate is in the range of 20-30 sccm. In some embodiments, the silane gas flow rate is in the range of 25-35 sccm.

[0070] In some embodiments, the HDPCVD process of step 530 is performed with the flow rate of argon gas at the configured flow rate. In some embodiments, the flow rate of argon gas is in the range of 20-35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20-25 sccm. In some embodiments, the flow rate of argon gas is in the range of 25-30 sccm. In some embodiments, the flow rate of argon gas is in the range of 30-35 sccm. In some embodiments, the flow rate of argon gas is in the range of 20-30 sccm. In some embodiments, the flow rate of argon gas is in the range of 25-35 sccm.

[0071] In some embodiments, the parameters of the HDPCVD process of step 530 are configured to provide a controlled deposition rate of the silicon dioxide layer on the handle wafer. In some embodiments, the deposition rate of the silicon dioxide layer is between 900 and 1100 Angstroms / minute. In some embodiments, the deposition rate of the silicon dioxide layer is between 950 and 1050 Angstroms / minute. In some embodiments, the deposition rate of the silicon dioxide layer is between 975 and 1025 Angstroms / minute. In some embodiments, the deposition rate of the silicon dioxide layer is about 1000 Angstroms / minute. In some embodiments, the deposition rate of the silicon dioxide layer is 1000 Angstroms / minute.

[0072] In some embodiments, the parameters of the HDPCVD process of step 530 are configured to provide a controlled thickness of the silicon dioxide layer on the handle wafer. In some embodiments, the thickness of the silicon dioxide layer is between 1500 and 5000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 1500 and 2000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 2000 and 2500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 2500 and 3000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 3000 and 3500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 3500 and 4000 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 4000 and 4500 angstroms. In some embodiments, the thickness of the silicon dioxide layer is between 4500 and 5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 1500-2500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2000-3000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2500-3500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 3000-4000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 3500-4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 4000-5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 1500-3000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2000-3500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2500-4000 angstroms. In some embodiments, the silicon dioxide layer has a thickness between 3000 and 4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness between 3500 and 5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness between 1500 and 3500 angstroms.In some embodiments, the silicon dioxide layer has a thickness of 2000-4000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2500-4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 3000-5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 1500-4000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2000-4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2500-5000 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 1500-4500 angstroms. In some embodiments, the silicon dioxide layer has a thickness of 2000-5000 angstroms. In some embodiments, the HDPCVD process of step 530 is performed for 2-3 minutes to achieve a controlled thickness of the silicon dioxide layer.

[0073] With continued reference to FIG. 5, at step 540, the second wafer is implanted with a hydrogen implant. In some embodiments, the hydrogen implant is positioned to define a cleavage plane in the second wafer. In some embodiments, the cleavage plane defines a desired thickness of the second silicon wafer after completion of method 500. In some embodiments, the hydrogen implant is implanted using an ion implanter. In some embodiments, the ion implanter is an ion implanter such as those commercialized by Nissin Ion Equipment Co., Ltd. of Kyoto, Japan. In some embodiments, the ion implanter is configured to emit a beam of hydrogen ions. In some embodiments, the ion implanter is configured to operate with a power of 5000 volts to 1 megavolts. In some embodiments, the desired thickness is in the range of 500 to 5000 angstroms. In some embodiments, the desired thickness is in the range of 500 to 2000 angstroms. In some embodiments, the desired thickness is in the range of 2000 to 3500 angstroms. In some embodiments, the desired thickness is in the range of 3500 to 5000 angstroms. In some embodiments, the desired thickness is in the range of 500-3500 angstroms. In some embodiments, the desired thickness is in the range of 2000-5000 angstroms. In some embodiments, the implanted hydrogen creates displacement defects in the form of interstitials, vacancies, and complexes. In some embodiments, such defects create regions with a large number of broken bonds called platelets. In some embodiments, hydrogen is trapped at these surfaces, passivating the broken bonds. FIG. 6D shows a schematic diagram of a first silicon wafer with an arsenic layer diffused therein and a silicon dioxide layer deposited thereon, and a second silicon wafer with a hydrogen implant implanted therein, after performance of step 540.

[0074] With continued reference to FIG. 5, in step 550, the surface of the silicon dioxide layer deposited in step 530 is activated. In some embodiments, the activation is plasma activation performed by bombarding the surface of the silicon dioxide layer with short-lived chemical species generated in the plasma volume to create a chemical reaction at the surface and enable bonding. In some embodiments, the activation is low pressure plasma activated bonding at a pressure in the range of 0.1-100 Pa. FIG. 6E shows a schematic diagram of a first silicon wafer having an arsenic layer diffused therein and an activated silicon dioxide layer deposited therein, and a second silicon wafer having a hydrogen implant implanted therein, after performance of step 550.

[0075] With continued reference to Figure 5, in step 560, the first silicon wafer (within which the arsenic layer has been diffused and the silicon dioxide layer has been deposited) is bonded to a second silicon wafer (within which the hydrogen implant) with the activated surface of the silicon dioxide layer facing the second silicon wafer and oriented such that after cleaving along the cleavage plane defined by the hydrogen implant, a desired portion of the second silicon wafer (i.e., a portion having the thickness described above) remains adjacent to the first silicon wafer. Figure 6F shows a schematic diagram of bonding a first silicon wafer with an arsenic layer diffused therein and an activated silicon dioxide layer deposited therein to a second silicon wafer with a hydrogen implant, in accordance with the performance of step 560.

[0076] With continued reference to FIG. 5, in step 570, the bonded first and second silicon wafers are subjected to a low temperature annealing process. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 250 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 degrees Celsius to 300 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 300 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 350 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 300 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 300 degrees Celsius to 400 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 200 degrees Celsius to 350 degrees Celsius. In some embodiments, the temperature used in the annealing process ranges from 250 degrees Celsius to 400 degrees Celsius. In some embodiments, the duration of the annealing process ranges from 1 hour to 8 hours. In some embodiments, during the annealing process, the trapped hydrogen described above with reference to step 540 dissociates from the complex and diffuses into the platelets to form H2 molecules. In some embodiments, the increase in pressure causes the platelets to expand in the microscopic cracks that bond them together in the same plane, causing delamination of the material. FIG. 6G shows a schematic diagram of the annealing process of step 570.

[0077] With continued reference to FIG. 5, in step 580, the bonded first and second silicon wafers are placed under tension (i.e., tension is applied to pull the first and second silicon wafers apart from one another). In some embodiments, the tension is sufficient to generate a tension in the range of 10-60 pounds per square inch across the bonded area. FIG. 6H shows a schematic diagram of the tensioning process of step 580.

[0078] With continued reference to FIG. 5, in step 590, the second silicon wafer is struck at the cleavage plane defined by the hydrogen implant. In some embodiments, the second silicon wafer is struck with a thin blade-like element with a force in the range of 5-10 pounds per square inch across the target area to generate a peel wave. In some embodiments, the thin blade-like element is any suitable object having a suitable width. In some embodiments, a suitable width is about 50 microns. As a result of this strike, a portion of the second silicon wafer (which may be referred to herein as the "donor wafer") disposed between the hydrogen implant and the first silicon wafer remains attached to the first silicon wafer (which may be referred to herein as the "handle wafer"), while the remaining portion of the second silicon wafer is cleaved. Following this cleaving step, a final finished wafer is produced. FIG. 6I shows a schematic diagram of the finished wafer and the removed portion of the second silicon wafer after performance of step 590.

[0079] In some embodiments, the exemplary substrate (e.g., the device 100 described above with reference to FIG. 1, the substrate fabricated according to the method 200 shown in FIG. 2, the device 400 described above with reference to FIG. 4, and / or the substrate fabricated according to the method 500 shown in FIG. 5) includes a trap rich layer (e.g., the silicon nitride layer of the device 100 or the diffused arsenic layer of the device 400), the trap rich layer being disposed within the substrate in contact with the top surface of the handle wafer (in the case of the silicon nitride layer of the device 100) or the trap rich layer being disposed within the top surface of the handle wafer (in the case of the arsenic layer of the device 400). In some embodiments, such an exemplary substrate is suitable for use in the manufacture of RF systems. In some embodiments, the trap rich layer operates to trap carriers, i.e., parasitic currents that may be induced by RF radiation. Thus, in some embodiments, such substrates are suitable for use in the manufacture of RF systems, since chip designers can integrate various functions (e.g., switches, power amplifiers, antenna tuners, etc.) on the same chip without having currents induced by the functions interfering with each other.

[0080] Previous techniques for forming SOI substrates suitable for use in the manufacture of RF systems include depositing a trap-rich layer on a handle wafer prior to bonding the handle wafer to an active silicon wafer. For example, a layer of polysilicon may be used in such techniques. However, SOI substrates formed using this process are thermally unstable because high temperature front-end-of-line ("FEOL") processes adversely affect the crystal structure of the polysilicon wafer and its interface with the handle wafer, degrading the trapping properties of the polysilicon layer. In some embodiments, the exemplary embodiments prevent such thermal instability problems. In some embodiments, the exemplary embodiments reduce manufacturing costs associated with depositing a trap-rich material, such as polysilicon, on a handle wafer.

[0081] In some embodiments, the silicon-on-insulator substrate includes a layered structure including, in order, (1) a high resistivity base layer having a first side and a second side opposite the first side, (2) a silicon dioxide layer disposed on the first side of the high resistivity base layer, and (3) a transfer layer disposed on the silicon dioxide layer. The high resistivity base layer includes a trap rich region including (a) silicon, and (b) arsenic diffused into the first side of the high resistivity base layer. The trap rich region has (i) a thickness in the range of 1-10 microns and (ii) a transfer layer in the range of 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1 The high resistivity base layer has a resistivity in the range of 50 to 100 ohm meters.

[0082] In some embodiments, the method includes providing a first silicon wafer having a first side and a second side; applying a sufficient amount of arsenic to a first surface of the first silicon wafer to diffuse the arsenic into the first side of the first silicon wafer to create a trap rich region, where a thickness of the trap rich region is in the range of 1 to 10 microns, and where the trap rich region is greater than or equal to 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1depositing a silicon dioxide layer on a first side of the first silicon wafer using a high density plasma chemical vapor deposition (HDPCVD) process, where the HDPCVD process uses a flow of oxygen gas, a flow of silane gas, and a flow of argon gas; providing a second silicon wafer having a first side and a second side opposite the first side; introducing a hydrogen implant into the second silicon wafer to define a cleavage plane; activating the silicon dioxide layer; contacting the first side of the second silicon wafer with the activated silicon dioxide layer, thereby creating a bonded wafer; annealing the bonded wafers; applying a tension to the bonded wafers in one direction to move the first and second silicon wafers away from each other; and cleaving the second silicon wafer at the cleavage plane, thereby creating a silicon-on-insulator substrate.

[0083] In some embodiments, a method includes providing a first silicon wafer having a first side and a second side; depositing a silicon nitride layer on the first side of the first silicon wafer using a first high density plasma chemical vapor deposition (HDPCVD) process, where the first HDPCVD process uses an inductively coupled plasma source, and the inductively coupled plasma source is operated at a power in a range of 65 watts to 225 watts during the first HDPCVD process, and the first HDPCVD process uses an oxygen gas flow, a silane gas flow, and an argon gas flow, and the flow rate of the nitrogen gas flow during the first HDPCVD process is in the range of 20 to 35 sccm. the silane gas flow rate is in the range of 20-35 sccm, the argon gas flow rate is in the range of 20-35 sccm, the first HDPCVD process is performed at a pressure in the range of 5 mTorr to 20 mTorr, the first HDPCVD process is performed with a bias power in the range of 0-100 Watts, the first HDPCVD process is performed on a first silicon wafer held at a temperature in the range of 100-250 degrees Celsius, a deposition rate of the silicon nitride layer is in the range of 300-500 Angstroms / minute, a thickness of the silicon nitride layer is in the range of 300-500 Angstroms, and the silicon nitride layer has a thickness of 0.8×10 10 cm 2 eV -1 ~1.2×10 10 cm 2 eV -1a trap rich layer having a trap density in the range of 0.5 to 200 nm; depositing a silicon dioxide layer on the silicon nitride layer using a second HDPCVD process, wherein the second HDPCVD process uses an inductively coupled plasma source, the inductively coupled plasma source is operated at a power in the range of 65 watts to 225 watts during the second HDPCVD process, the second HDPCVD process uses an oxygen gas flow, a silane gas flow, and an argon gas flow, wherein a flow rate of the oxygen gas flow during the second HDPCVD process is in the range of 20 to 35 sccm, a flow rate of the silane gas flow during the second HDPCVD process is in the range of 20 to 35 sccm, a flow rate of the argon gas flow during the second HDPCVD process is in the range of 20 to 35 sccm, the second HDPCVD process is conducted at a pressure in the range of 5 mTorr to 20 mTorr, the second HDPCVD process is conducted with a bias power in the range of 0 to 100 watts, and the second HDPCVD process is held at a temperature in the range of 100 to 250 degrees Celsius. providing a second silicon wafer having a first side and a second side opposite the first side, wherein a thickness of the silicon dioxide layer is in the range of 500-5000 angstroms; introducing a hydrogen implant into the second silicon wafer to define a cleavage plane, wherein a thickness of a portion of the second silicon wafer between the first side of the second silicon wafer and the cleavage plane is in the range of 500-5000 angstroms; activating the silicon dioxide layer, wherein the activation step includes low pressure plasma activated bonding at a pressure in the range of 0.1-100 Pa; contacting the first side of the second silicon wafer with the activated silicon dioxide layer, thereby producing a bonded wafer; annealing the bonded wafer, wherein the annealing is performed at a temperature in the range of 200 degrees Celsius to 400 degrees Celsius for a period of time in the range of 1 hour to 8 hours.); applying tension to the bonded wafers in one direction such that the first and second silicon wafers move away from each other; and striking an edge of the second silicon wafer to cleave the second silicon wafer at a cleavage plane, thereby creating a silicon-on-insulator substrate.

[0084] All art-known functional equivalents of such materials and methods are intended to be included in the present invention. The terms and expressions used herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions to exclude the equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention claimed. Thus, although the present invention has been specifically disclosed by preferred embodiments and optional features, it will be understood that modifications and variations of the concepts disclosed herein may be implemented by those skilled in the art, and such modifications and variations are within the scope of this disclosure.

[0085] Although several embodiments of the present invention have been described, it is understood that these embodiments are merely illustrative and not limiting, and that numerous modifications may become apparent to one skilled in the art. For example, all dimensions described herein are provided by way of example only and are intended to be illustrative and not limiting.

Claims

1. (1) a high resistivity base layer having a first side and a second side opposite the first side; (2) a silicon dioxide layer positioned on a first side of the high resistivity base layer; and (3) a transfer layer positioned on the silicon dioxide layer; In particular, the layer structure includes a layer structure including, in order, The high resistivity base layer is (a) silicon, and (b) comprising an arsenic trap rich region diffused into the entire first side of the high resistivity base layer; The trap rich region is (i) a thickness in the range of 1 to 10 microns; and (ii) 0.8×10 １０ cm ２ eV －１ ~1.2 x 10 １０ cm ２ eV －１ and having a trap density in the range The high resistivity base layer is (a) a resistivity in the range of 50 to 100 ohm-meters; and (b) having a thickness in the range of 500 to 700 microns; the silicon dioxide layer having a thickness in the range of 1000 to 5000 angstroms; A silicon-on-insulator substrate, wherein the transfer layer comprises a silicon wafer and has a thickness in the range of 500 to 5000 angstroms.

2. The trap rich region is 10 １０ cm ２ eV －１ ~1.2 x 10 １０ cm ２ eV －１ 10. The silicon-on-insulator substrate of claim 1 having a trap density in the range of

3. 2. The silicon-on-insulator substrate of claim 1 , wherein the trap rich regions comprise arsenic interspersed within a crystalline structure of the silicon of the high resistivity base layer.

4. 2. The silicon-on-insulator substrate of claim 1 , wherein the trap rich region has a thickness in the range of 4 microns to 7 microns.

5. The silicon-on-insulator substrate of claim 1 , wherein the high resistivity base layer has a thickness in the range of 550 to 650 microns.

6. 2. The silicon-on-insulator substrate of claim 1, wherein the silicon dioxide layer has a thickness in the range of 2000 to 4000 Angstroms.

7. The silicon-on-insulator substrate of claim 1 , wherein the transfer layer has a thickness in the range of 2000 to 3500 Angstroms.

8. Providing a first silicon wafer having a first side and a second side; diffusing arsenic into the first side of the first silicon wafer to produce a diffused arsenic layer; depositing a silicon dioxide layer on a first side of the first silicon wafer using a high density plasma chemical vapor deposition (HDPCVD) process; providing a second silicon wafer having a first side and a second side opposite the first side; introducing a hydrogen implant into the second silicon wafer to define a cleavage plane; activating the silicon dioxide layer; contacting a first side of the second silicon wafer with an activated silicon dioxide layer to produce a unitary wafer; annealing the integrated wafer; applying tension to the unidirectionally integrated wafers to separate the first and second silicon wafers from each other; and striking an edge of the second silicon wafer to cleave the second silicon wafer at the cleavage plane, thereby producing a silicon-on-insulator substrate. Including, the diffused arsenic layer has a first side and a second side opposite the first side of the diffused arsenic layer; the diffused arsenic layer is positioned within the first silicon wafer such that the first side of the diffused arsenic layer is positioned between the first side and the second side of the first silicon wafer, and the second side of the diffused arsenic layer is positioned on the second side of the first silicon wafer; the thickness of the diffused arsenic layer is in the range of 1 to 10 microns; The entire diffused arsenic layer is 0.8×10 １０ cm ２ eV －１ ~1.2 x 10 １０ cm ２ eV －１ and having a trap density in the range depositing the silicon dioxide layer, the HDPCVD process using an inductively coupled plasma source, the inductively coupled plasma source being driven at a power in the range of 65 watts to 225 watts; the HDPCVD process using an oxygen gas flow, a silane gas flow, and an argon gas flow; the flow rate of the oxygen gas flow is in the range of 20 to 35 sccm; the flow rate of the silane gas flow is in the range of 20-35 sccm; the argon gas flow rate is in the range of 20-35 sccm; said HDPCVD process being carried out at a pressure ranging from 5 mTorr to 20 mTorr; said HDPCVD process being carried out with a bias power in the range of 0 to 100 watts; performing the HDPCVD process with the first silicon wafer held at a temperature in the range of 100-250 degrees Celsius; the deposition rate of said silicon dioxide layer is in the range of 900 to 1100 angstroms per minute; the thickness of said silicon dioxide layer is in the range of 1500 to 5000 angstroms; introducing a hydrogen implant into the second silicon wafer, wherein a thickness of a portion of the second silicon wafer between the first side and the cleavage surface of the second silicon wafer is in the range of 500 to 5000 angstroms; the step of activating the silicon dioxide layer comprises low pressure plasma activated bonding at a pressure in the range of 0.1 to 100 Pa; The method of claim 1, wherein in the step of annealing the integrated wafer, the annealing is carried out at a temperature ranging from 200 to 400 degrees Celsius for a time ranging from 1 hour to 8 hours.

9. 9. The method of claim 8, wherein the flow rates of the oxygen gas flow, the silane gas flow, and the argon gas flow are identical to one another.

10. 9. The method of claim 8, wherein the oxygen gas flow rate, the silane gas flow rate, and the argon gas flow rate are selected to control the refractive index of the silicon dioxide layer.

11. The diffused arsenic layer is 10 １０ cm ２ eV －１ ~1.2 x 10 １０ cm ２ eV －１ The method of claim 8 , having a trap density in the range of

12. The method of claim 8, wherein the first silicon wafer has a thickness in the range of 550 to 650 microns.

13. The method of claim 8, wherein the silicon dioxide layer has a thickness in the range of 2000 to 4000 Angstroms.

14. 9. The method of claim 8, wherein a thickness of the portion of the second silicon wafer between the first side and the cleaved surface of the second silicon wafer is in the range of 2000 to 3500 angstroms.

15. The method of claim 8, wherein the thickness of the diffused arsenic layer ranges from 4 microns to 7 microns.

16. Diffusing arsenic into the first side of the first silicon wafer comprises: spin coating to apply a liquid colloidal solution containing arsenic to the first side of the first silicon wafer; and diffusing arsenic into the first side of the first silicon wafer at a diffusion temperature for a diffusion period to form the diffused arsenic layer. The method of claim 8 , wherein the method is carried out by

17. 17. The method of claim 16, wherein the liquid colloidal solution comprises arsenic-infused glass.

18. The method of claim 16, wherein the diffusion temperature is in the range of 700 degrees Celsius to 1200 degrees Celsius.

19. The method of claim 16, wherein the diffusion period is in the range of 5 hours to 20 hours.

20. 17. The method of claim 16, wherein at least one of the diffusion temperature or the diffusion duration is selected to control a thickness of the diffused arsenic layer.

21. 9. The method of claim 8, wherein the step of diffusing arsenic into the first side of the first silicon wafer is performed by directing a beam of arsenic ions into the first side of the first silicon wafer to diffuse arsenic by ion implantation.

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