Semiconductor Device

Abstract

A semiconductor device according to an embodiment comprises: a semiconductor chip including a transistor and a drain pad provided on a substrate; a capacitor having an upper electrode and a lower electrode sandwiching a dielectric; a pad; and a vacant pad provided on the substrate of the semiconductor chip. The semiconductor device further comprises a first wire interconnecting the pad and the drain pad of the semiconductor chip, a second wire interconnecting the vacant pad and the upper electrode of the capacitor, and a third wire interconnecting the pad and the vacant pad.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. This application claims priority to Japanese Application No. 2020-149904 filed on September 7, 2020, and incorporates by reference all of the contents of said Japanese application. [Background technology]

[0002] Patent Document 1 describes an internally matched high-power field effect transistor (internal matching FET). The internally matched FET includes two GaAsFET chips arranged in an envelope and an alumina substrate for an input / output matching circuit. The internally matched FET includes an input-side alumina substrate and an output-side alumina substrate. The input-side alumina substrate and the output-side alumina substrate are each provided with a matching circuit for impedance matching. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Unexamined Patent Publication No. 63-86904 Summary of the Invention

[0004] A semiconductor device according to one embodiment includes a semiconductor chip having a transistor and an electrode pad provided on a substrate, a capacitor having an upper electrode and a lower electrode sandwiching a dielectric, a first relay pad, and a second relay pad provided on the substrate of the semiconductor chip. The semiconductor device further includes a first wire connecting the first relay pad and the electrode pad of the semiconductor chip to each other, a second wire connecting the second relay pad and the upper electrode of the capacitor to each other, and a third wire connecting the first relay pad and the second relay pad to each other. [Brief description of the drawings]

[0005] [Figure 1]FIG. 1 is a plan view showing an internal configuration of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a plan view showing a semiconductor chip, a capacitor, and a wire of the semiconductor device of FIG. [Diagram 3] FIG. 3 is a graph showing an example of the relationship between wire length and current. [Figure 4] FIG. 4 is a diagram showing a semiconductor chip, a capacitor, and a wire of the semiconductor device of FIG. [Diagram 5] FIG. 5 is a plan view showing the semiconductor chip, the capacitor, and the wires of the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a semiconductor chip, a capacitor, and a wire of a semiconductor device according to a first modification. [Figure 7] FIG. 7 is a diagram showing the semiconductor chip, capacitor, and wire of FIG. [Figure 8] FIG. 8 is an enlarged perspective view of the wire. [Figure 9] FIG. 9 is a plan view showing a semiconductor chip, a capacitor, and a wire of a semiconductor device according to a second modification. [Figure 10] FIG. 10 is a rear view showing the rear surface of the semiconductor chip and the rear surface of the capacitor in FIG. [Figure 11] FIG. 11 is a plan view showing a semiconductor chip, a first relay pad, a capacitor, and a wire of a semiconductor device according to a third modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] In a conventional internally matched FET, the GaAsFET chip and the matching circuit are connected to each other by bonding wires. However, when the frequency of the signal handled in the high-frequency amplifier is low, it may be required to reduce the number of wires connected to the electrode pads of the semiconductor chip, such as the drain pad, and to increase the length of each wire. If the current per wire is large and the wire length is long, there is a concern that the wire may melt.

[0007] An object of the present disclosure is to provide a semiconductor device capable of shortening wires connected to electrode pads of a semiconductor chip.

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. A semiconductor device according to one embodiment includes a semiconductor chip having a transistor and an electrode pad provided on a substrate, a capacitor having an upper electrode and a lower electrode sandwiching a dielectric, a first relay pad, and a second relay pad provided on the substrate of the semiconductor chip. The semiconductor device further includes a first wire connecting the first relay pad and the electrode pad of the semiconductor chip to each other, a second wire connecting the second relay pad and the upper electrode of the capacitor to each other, and a third wire connecting the first relay pad and the second relay pad to each other.

[0009] In this semiconductor device, the semiconductor chip includes a transistor and an electrode pad on a substrate, and the capacitor includes an upper electrode and a lower electrode sandwiching a dielectric. The first wire connects the electrode pad of the semiconductor chip to the first relay pad. The third wire connects the first relay pad to the second relay pad. The second wire connects the second relay pad to the upper electrode of the capacitor. Thus, the semiconductor chip and the capacitor are connected to each other via the first wire extending from the semiconductor chip, the first relay pad, the third wire, the second relay pad on the semiconductor chip, and the second wire extending toward the capacitor. Thus, by providing the first wire, the first relay pad, the third wire, the second relay pad, and the second wire, it is possible to make the wire connected to the electrode pad of the semiconductor chip only the first wire. By connecting the wires to each other via the first relay pad and the second relay pad, the wires can be shortened.

[0010] The first relay pad may be disposed on the dielectric of the capacitor at a position spaced apart from the upper electrode. The second relay pad may be disposed along one side of the semiconductor chip. In this case, the first relay pad may be disposed on the dielectric of the capacitor, and the second relay pad may be disposed along one side of the semiconductor chip facing the capacitor.

[0011] The electrode pad may be arranged along one side of the semiconductor chip. The second relay pad may be arranged adjacent to the electrode pad. In this case, it is possible to arrange the electrode pad and the second relay pad on the semiconductor chip so as to be aligned along one side of the semiconductor chip facing the capacitor.

[0012] The semiconductor device described above may include a plurality of first relay pads arranged along one side of the capacitor, a plurality of second relay pads arranged along one side of the semiconductor chip, and a plurality of electrode pads. Each of the plurality of second relay pads may be disposed adjacent to the electrode pad. In this case, the plurality of first relay pads can be arranged along one side of the capacitor facing the semiconductor chip, and the electrode pads and the second relay pads can be arranged along one side of the semiconductor chip facing the capacitor.

[0013] The above-mentioned semiconductor device may include a plurality of first wires and a plurality of second wires, and each of the plurality of adjacent first wires may be connected to a common first relay pad. Each of the plurality of adjacent second wires may be connected to a common second relay pad. In this case, since a plurality of wires are connected to each of the first relay pad and the second relay pad, the first relay pad and the second relay pad can be more effectively used as connection portions for the wires.

[0014] The semiconductor device described above may include a back electrode provided on the back surface of the dielectric of the capacitor in an area other than the area facing the first relay pad. In this case, since no back electrode is provided on the back surface of the first relay pad, parasitic capacitance generated in the first relay pad can be suppressed.

[0015] The above-mentioned semiconductor device may have a back electrode provided on the back surface of the semiconductor chip or the back surface of the substrate in an area other than the area facing the second relay pad. In this case, since no back electrode is provided on the back surface of the second relay pad, the parasitic capacitance generated in the second relay pad can be suppressed.

[0016] The first relay pad may be provided between the capacitor and the semiconductor chip, in which case the first relay pad can be disposed at a location spaced apart from both the capacitor and the semiconductor chip.

[0017] The substrate may be made of silicon carbide (SiC), diamond, or metal, which allows the substrate to be made of a material with high heat dissipation properties.

[0018] [Details of the embodiment of the present disclosure] Specific examples of the semiconductor device of the present disclosure will be described below with reference to the drawings. Note that the present invention is not limited to the following examples, but is intended to include all modifications within the scope of the claims and equivalents thereto. In the description of the drawings, the same or corresponding elements are given the same reference numerals, and duplicated descriptions are omitted as appropriate. The drawings are partially simplified or exaggerated for ease of understanding, and the dimensional ratios and the like are not limited to those shown in the drawings.

[0019] Fig. 1 is a diagram showing an internal configuration of a semiconductor device 1 according to an embodiment. As shown in Fig. 1, the semiconductor device 1 includes an input terminal 2, an output terminal 3, a semiconductor chip 10, a branching circuit board 20, a composite circuit board 30, a filter circuit 40, a capacitor 50, and a capacitor 60. The semiconductor device 1 includes, for example, two filter circuits 40 and two capacitors 50 and 60.

[0020] For example, the semiconductor chip 10 is an amplifying element section including two amplifying elements 11. As an example, the output of each amplifying element 11 is 30 W, and the output of the entire semiconductor chip 10 is 60 W. The semiconductor device 1 is, for example, a high-frequency amplifier including a package 4. The package 4 contains the semiconductor chip 10, a branch circuit board 20, a composite circuit board 30, a filter circuit 40, and capacitors 50 and 60.

[0021] The package 4 is made of metal and is connected to a reference potential. For example, the planar shape of the package 4 is rectangular. The package 4 has end walls 4a and 4b facing each other in a first direction A1 and side walls 4c and 4d facing each other in a second direction A2. The first direction A1 and the second direction A2 intersect with each other, and are, for example, perpendicular to each other. The package 4 has a flat rectangular bottom plate 4e.

[0022] The bottom plate 4e has, for example, a plane extending in both the first direction A1 and the second direction A2. The end walls 4a, 4b stand along a pair of sides (sides extending in the second direction A2) of the bottom plate 4e. The side walls 4c, 4d stand along another pair of sides (sides extending in the first direction A1) of the bottom plate 4e. The package 4 further has a lid portion (not shown). The lid portion seals an opening formed by the end walls 4a, 4b and the side walls 4c, 4d.

[0023] The input terminal 2 is a metal wiring pattern that inputs a high-frequency signal from outside the semiconductor device 1. The high-frequency signal is, for example, a signal based on a multi-carrier transmission method, and is formed by superimposing a plurality of signals having different carrier signal frequencies. The frequency band of the carrier signal is, for example, 500 MHz or less. The input terminal 2 is provided at the center of the end wall 4a in the second direction A2. The input terminal 2 extends from the outside to the inside of the package 4.

[0024] For example, the semiconductor chip 10 is disposed on the bottom plate 4e of the package 4 in a region including the center of the package 4 in the first direction A1. Each amplifying element 11 of the semiconductor chip 10 includes a transistor. The transistor is a field effect transistor (FET), and as an example, is a high electron mobility transistor (HEMT). Each amplifying element 11 has a gate pad, a source pad, and a drain pad.

[0025] For example, gate pads (signal input terminals) and source pads are alternately arranged on one side (end side) of each amplifying element 11 on the input terminal 2 side. Drain pads (signal output terminals) are arranged on the end side of each amplifying element 11 on the output terminal 3 side. Each source pad is electrically connected to the bottom plate 4e of the package 4 through a via hole and is set to the reference potential. This via hole penetrates the amplifying element 11 in the thickness direction (for example, the direction perpendicular to the paper surface of FIG. 1). Each amplifying element 11 amplifies a high-frequency signal input to each gate pad and outputs the amplified high-frequency signal from each drain pad. The configuration around the drain pad of the amplifying element 11 will be described in detail later.

[0026] The branch circuit board 20 is disposed on the bottom plate 4e of the package 4. The branch circuit board 20 is disposed alongside the input terminal 2 and the semiconductor chip 10 along the first direction A1. The branch circuit board 20 is located between the input terminal 2 and the semiconductor chip 10. The branch circuit board 20 has a ceramic substrate 21 and a branch circuit 22 provided on a main surface of the substrate 21. For example, the substrate 21 has a rectangular planar shape.

[0027] For example, one long side 21a of the branch circuit board 20 faces the input terminal 2, and the other long side 21b of the branch circuit board 20 faces the semiconductor chip 10 via the capacitor 50. The back surface of the substrate 21 faces the bottom plate 4e of the package 4. One short side 21c of the substrate 21 faces the side wall 4c of the package 4, and the other short side 21d of the substrate 21 faces the side wall 4d of the package 4.

[0028] The branch circuit 22 includes a wiring pattern 23 provided on the main surface of the substrate 21. The wiring pattern 23 is electrically connected to the input terminal 2 via a bonding wire 9a. A high-frequency signal is input to the wiring pattern 23 from the center of the input terminal 2 in the second direction A2 via the bonding wire 9a. The wiring pattern 23 has, for example, a shape that is line-symmetrical with respect to the center line of the substrate 21 along the first direction A1.

[0029] The wiring pattern 23 starts from the connection point with the bonding wire 9a and branches into two, eventually reaching eight metal pads 23a. The eight metal pads 23a are arranged side by side along the long side 21b. The adjacent metal pads 23a are connected to each other via a film resistor, forming a Wilkinson type coupler. This ensures isolation between the multiple gate pads of the semiconductor chip 10, while matching the input impedance of the semiconductor chip 10 as seen from the input terminal 2. FIG. 1 shows only one film resistor 23b as an example. The eight metal pads 23a are electrically connected to the capacitor 50 via the bonding wire 9b.

[0030] The capacitor 50 is disposed on the bottom plate 4e of the package 4. The capacitor 50 is disposed between the branch circuit board 20 and the semiconductor chip 10. The capacitor 50 is, for example, a parallel plate type capacitor (die capacitor) and has a plurality of metal pads (not shown) on the main surface of the dielectric substrate. The number of metal pads of the capacitor 50 is, for example, the same as the number of metal pads 23a. The plurality of metal pads of the capacitor 50 are aligned in a line along the second direction A2. The metal pads are electrically connected to the corresponding metal pads 23a via bonding wires 9b. The metal pads are electrically connected to the corresponding gate pads of the semiconductor chip 10 via bonding wires 9c.

[0031] In the capacitor 50, a T-type filter circuit is formed by the inductance components due to the bonding wires 9b and 9c and the capacitance of a metal pad connected between the node between the inductance components and the reference potential (bottom plate 4e). The capacitor 50 performs impedance conversion using this T-type filter circuit. Normally, the impedance seen from the gate pad to the inside of the transistor in the semiconductor chip 10 is different from the characteristic impedance (e.g., 50Ω) of the transmission line. The capacitor 50 is a matching circuit that converts this impedance to 50Ω seen from the input terminal 2 to the inside of the transistor using the T-type filter circuit.

[0032] The capacitor 60 is disposed on the bottom plate 4e of the package 4. The capacitor 60 is disposed between the semiconductor chip 10 and the composite circuit substrate 30. Like the capacitor 50, the capacitor 60 is, for example, a parallel plate capacitor (die capacitor). The capacitor 60 has an upper electrode and a lower electrode that sandwich a dielectric. That is, like the capacitor 50, the capacitor 60 also has a plurality of metal pads (not shown) on the main surface of the dielectric substrate.

[0033] The number of metal pads of the capacitor 60 is, for example, the same as the number of metal pads 23a. The multiple metal pads of the capacitor 60 are arranged in a row along the second direction A2. The metal pads are electrically connected to corresponding drain pads of the semiconductor chip 10 via a wire group 70 described later. The metal pads are electrically connected to corresponding metal pads 33a of the composite circuit board 30 via a bonding wire 9e. Note that the wire group 70 is illustrated simply in FIG. 1.

[0034] In the capacitor 60, a T-type filter circuit is formed by the inductance components of the wire group 70 and the bonding wire 9e, and the capacitance of a metal pad connected between a node between these inductance components and the reference potential (bottom plate 4e). The capacitor 60 performs impedance conversion using this T-type filter circuit. Normally, in the semiconductor chip 10, the impedance seen from the drain pad to the inside of the transistor is often smaller than 50Ω, unlike the characteristic impedance of the transmission line (e.g., 50Ω). The capacitor 60 is a matching circuit that converts this impedance to 50Ω seen from the output terminal 3 to the inside of the transistor using a T-type filter circuit.

[0035] The composite circuit board 30 is disposed on the bottom plate 4e of the package 4. The composite circuit board 30 is disposed alongside the semiconductor chip 10 and the output terminal 3 along the first direction A1. The composite circuit board 30 is located between the semiconductor chip 10 and the output terminal 3. The composite circuit board 30 has a ceramic substrate 31 and a composite substrate 32 provided on the main surface of the substrate 31. The planar shape of the substrate 31 is, for example, rectangular.

[0036] One long side 31a of the substrate 31 faces the semiconductor chip 10 via the capacitor 60, and the other long side 31b of the substrate 31 faces the output terminal 3. The back surface of the substrate 31 faces the bottom plate 4e of the package 4. One short side 31c of the substrate 31 faces the side wall 4c of the package 4, and the other short side 31d of the substrate 31 faces the side wall 4d of the package 4.

[0037] The composite substrate 32 combines signals output from a plurality of drain pads of the semiconductor chip 10 to generate one output signal. The composite substrate 32 includes a wiring pattern 33 provided on the main surface of the substrate 31. The wiring pattern 33 has, for example, a shape that is line-symmetrical with respect to the center line of the substrate 31 along the first direction A1. The wiring pattern 33 includes four metal pads 33a. The four metal pads 33a are arranged side by side along the long side 31a of the substrate 31.

[0038] Adjacent metal pads 33a are connected to each other via a film resistor to form a Wilkinson type coupler. This ensures isolation between the drain pads of the semiconductor chip 10 while matching the output impedance of the semiconductor chip 10 as seen from the output terminal 3. Note that only one film resistor 33b is shown in FIG. 1 as an example.

[0039] Each metal pad 33a is electrically connected to two corresponding metal pads of the capacitor 60 via a bonding wire 9e. The wiring pattern 33 repeats bonding from the four metal pads 33a and finally reaches a connection point with a bonding wire 9f. The wiring pattern 33 is electrically connected to the output terminal 3 via a bonding wire 9f. The amplified high frequency signal is output to the output terminal 3 from the center of the substrate 31 in the second direction A2.

[0040] The output terminal 3 is a metal wiring pattern. The output terminal 3 outputs the amplified high-frequency signal to the outside of the semiconductor device 1. The output terminal 3 is provided in the center of the end wall 4b in the second direction A2. The output terminal 3 extends from the inside of the package 4 to the outside.

[0041] For example, the semiconductor device 1 includes a pair of filter circuits 40. The filter circuits 40 are provided to reduce third-order intermodulation distortion included in an output signal, for example. One of the filter circuits 40 is disposed between the center of the substrate 31 in the second direction A2 and one corner 31e of the substrate 31 located on the opposite side to the semiconductor chip 10.

[0042] The other filter circuit 40 is disposed between the center of the substrate 31 in the second direction A2 and the other corner 31f located on the opposite side of the substrate 31 from the semiconductor chip 10. That is, one filter circuit 40 is disposed at a position closer to the corner 31e with respect to the center of the main surface of the substrate 31. The other filter circuit 40 is disposed at a position closer to the corner 31f with respect to the center of the main surface of the substrate 31.

[0043] Next, the semiconductor chip 10 and the capacitor 60 will be described in detail with reference to Fig. 2. Fig. 2 is a plan view showing the semiconductor chip 10 and the capacitor 60. The semiconductor chip 10 has an elongated rectangular shape. The semiconductor chip 10 has a long side 12 (one side) facing the capacitor 60.

[0044] For example, the long side 12 extends along the second direction A2. The semiconductor chip 10 includes a substrate 15, a gate pad, an active region, a drain pad 18 (electrode pad), and a dead pad 19 (second relay pad). The substrate 15 has a rectangular shape including the long side 12 described above.

[0045] The semiconductor chip 10 includes, for example, a plurality of drain pads 18 and a plurality of dead pads 19. The drain pads 18 and the dead pads 19 are arranged side by side along the long side 12 facing the capacitor 60. By including the dead pads 19 in the semiconductor chip 10, it is possible to shorten the wire length of each wire in the wire group 70.

[0046] As described above, the capacitor 60 includes the dielectric 61, the upper electrode 62, the lower electrode (not shown), and the pad 63 (first relay pad). The capacitor 60 (dielectric 61) has a long side 64 (one side) facing the semiconductor chip 10. For example, the long side 64 extends along the second direction A2.

[0047] The upper electrode 62 and the pad 63 are disposed on the dielectric 61. The pad 63 is provided on the semiconductor chip 10 side of the upper electrode 62. The dielectric 61 has a rectangular shape with the long side 64 described above. The capacitor 60 has a plurality of pads 63. The plurality of pads 63 are provided on the semiconductor chip 10 side of the upper electrode 62. For example, the plurality of pads 63 are lined up along the long side 64. Each pad 63 has a rectangular shape with a long side extending along the second direction A2.

[0048] As described above, the semiconductor chip 10 and the capacitor 60 are electrically connected to each other via the wire group 70. The wire group 70 includes a first wire 71, a second wire 72, and a third wire 73. The first wire 71 connects the pad 63 and the drain pad 18 of the semiconductor chip 10 to each other. The second wire 72 connects the upper electrode 62 of the capacitor 60 to the dead pad 19 to each other. The third wire 73 connects the dead pad 19 to the pad 63 to each other.

[0049] For example, the first wire 71 connecting the drain pad 18 and the pad 63 to each other, the third wire 73 connecting the dead pad 19 and the pad 63 to each other, and the second wire 72 connecting the dead pad 19 and the upper electrode 62 to each other are arranged in this order along the second direction A2. The length of at least one of the first wire 71, the second wire 72, and the third wire 73 is, for example, 0.6 mm. The second wire 72 may be longer than the first wire 71 and the third wire 73.

[0050] Thus, in this embodiment, the wire group 70 connecting the semiconductor chip 10 and the capacitor 60 to each other includes the first wire 71, the second wire 72, and the third wire 73. This makes it possible to shorten the wire length of each wire constituting the wire group 70. As illustrated in Fig. 3, the shorter the wire length (L), the higher the melting current (I) of each wire.

[0051] Fig. 4 is a diagram showing the semiconductor chip 10, the capacitor 60, and the third wire 73. As shown in Fig. 4, the semiconductor chip 10 includes, for example, an Ag-P layer 10b, an Au layer 10c, a SiC layer 10d, and a GaN layer 10f. The semiconductor chip 10 has a configuration in which the Au layer 10c is provided on the Ag-P layer 10b, the SiC layer 10d is provided on the Au layer 10c, and the GaN layer 10f is provided on the SiC layer 10d.

[0052] The dead pad 19 is provided on the GaN layer 10f. The dead pad 19 contains, for example, gold (Au). In the semiconductor chip 10, heat flows from the dead pad 19 to the SiC layer 10d through the GaN layer 10f. Heat from the wire group 70 (for example, the third wire 73) is dissipated, and melting of the wire group 70 due to heat generation can be suppressed. As an example, the thickness T1 of the bottom plate 4e is 1000 μm, the thickness T2 of the Ag-P layer 10b is 30 μm, and the thicknesses T3 of the Au layer 10c and the SiC layer 10d are 100 μm. The thickness T4 of the GaN layer 10f is 0.6 μm, the thickness T5 of the dead pad 19 is 10 μm, and the rising height H of the pad 63 from the dead pad 19 is 100 μm.

[0053] For example, the substrate 15 of the semiconductor chip 10 includes an Ag-P layer 10b, an Au layer 10c, and an SiC layer 10d. As described above, the substrate 15 functions as a heat sink that dissipates heat generated by the element. The substrate 15 is made of, for example, a material with high heat dissipation properties. For example, the substrate 15 may include a diamond layer or a metal layer together with the SiC layer 10d or instead of the SiC layer 10d. The material of the metal layer of the substrate 15 is, for example, a red-based metal material containing copper or gold, or a silver-white-based metal material containing silver, nickel, or aluminum.

[0054] The capacitor 60 includes, for example, an Ag-P layer 60b, an Au layer 60c, and a ceramic layer 60d. The capacitor 60 has a configuration in which the Au layer 60c is provided on the Ag-P layer 60b, and the ceramic layer 60d is provided on the Au layer 60c. The pad 63 is provided on the ceramic layer 60d. The pad 63 includes, for example, gold (Au). In the capacitor 60, heat from the wire group 70 (for example, the third wire 73) is dissipated from the pad 63 to the ceramic layer 60d. As a result, it is possible to suppress melting of the wire group 70 due to heat generation.

[0055] Fig. 5 is a plan view showing the entire semiconductor chip 10, the capacitor 60, and the wire group 70 shown in Fig. 1. As shown in Fig. 5, the wire group 70 includes a plurality of first wires 71, a plurality of second wires 72, and a plurality of third wires 73. The wire group 70 may include a plurality of sets 75 each consisting of the first wires 71, the second wires 72, and the third wires 73. For example, the plurality of sets 75 are arranged along the second direction A2.

[0056] For example, in each set 75, the first wire 71, the third wire 73, and the second wire 72 are arranged in this order along the second direction A2. As an example, the number of sets 75 is 9. For example, the length L1 of the dead pad 19 in the second direction A2 is longer than the length L2 of the drain pad 18 in the second direction A2. As an example, the length L1 of the dead pad 19 is 250 μm, and the length L2 of the drain pad 18 is 150 μm. The length X from the drain pad 18 located at one end in the second direction A2 to the drain pad 18 located at the other end in the second direction A2 is 5.34 mm.

[0057] Next, the effects obtained from the semiconductor device 1 according to the embodiment will be described. In the semiconductor device 1, the semiconductor chip 10 includes a transistor and a drain pad 18 on the substrate 15. The capacitor 60 includes an upper electrode 62 and a lower electrode sandwiching a dielectric 61. The first wire 71 connects the drain pad 18 and the pad 63 of the semiconductor chip 10 to each other. The third wire 73 connects the pad 63 and the dead pad 19 to each other. The second wire 72 connects the dead pad 19 and the upper electrode 62 of the capacitor 60 to each other. Thus, the semiconductor chip 10 and the capacitor 60 are connected to each other via the first wire 71, the pad 63, the third wire 73, the dead pad 19 on the semiconductor chip 10, and the second wire 72 extending toward the capacitor 60, which extend from the semiconductor chip 10.

[0058] By providing the first wire 71, the pad 63, the third wire 73, the dead pad 19, and the second wire 72, it is possible to connect the first wire 71 to the drain pad 18 of the semiconductor chip 10. By connecting the wires to each other via the pad 63 and the dead pad 19, the wires can be shortened.

[0059] The pad 63 may be arranged at a position spaced apart from the upper electrode 62 on the dielectric 61 of the capacitor 60. The dead pad 19 may be arranged along the long side 12 of the semiconductor chip 10. In this case, the pad 63 can be arranged on the dielectric 61 of the capacitor 60. The dead pad 19 can be arranged along the long side 12 of the semiconductor chip 10 facing the capacitor 60.

[0060] The drain pad 18 is arranged along the long side 12 of the semiconductor chip 10, and the dead pad 19 may be arranged adjacent to the drain pad 18. In this case, it is possible to arrange the drain pad 18 and the dead pad 19 on the semiconductor chip 10 so as to be aligned along the long side 12 of the semiconductor chip 10 facing the capacitor 60.

[0061] The semiconductor device 1 may include a plurality of pads 63 aligned along a long side 64 of the capacitor 60, a plurality of dead pads 19 aligned along a long side 12 of the semiconductor chip 10, and a plurality of drain pads 18. Each of the plurality of dead pads 19 may be disposed adjacent to the drain pad 18. In this case, the plurality of pads 63 can be aligned along the long side 64 of the capacitor 60 facing the semiconductor chip 10, and the drain pads 18 and the dead pads 19 can be aligned along the long side 12 of the semiconductor chip 10 facing the capacitor 60.

[0062] The substrate 15 may be made of silicon carbide (SiC), diamond, or a metal, in which case the substrate 15 can be made of a material with high heat dissipation properties.

[0063] Next, a semiconductor device according to a first modification will be described with reference to Fig. 6. As shown in Fig. 6, the semiconductor device according to the first modification includes a drain pad 18A, a dead pad 19B, a pad 63A, and a wire group 70A. The drain pad 18A is different from the drain pad 18, and the dead pad 19B is different from the dead pad 19. The pad 63A is different from the pad 63, and the wire group 70A is different from the wire group 70. In the following, descriptions that overlap with the description of the semiconductor device 1 described above will be omitted as appropriate.

[0064] 7 is a plan view showing the entire semiconductor chip 10A and the capacitor 60A of the semiconductor device according to the first modification shown in FIG. 6 in the second direction A2. As shown in FIG. 7, the semiconductor chip 10A according to the first modification includes an empty pad 19A and an empty pad 19B. The empty pads 19A are provided on both ends of the semiconductor chip 10A in the second direction A2. The shape, size, and function of the empty pad 19A are the same as, for example, the empty pad 19 described above. The empty pad 19B is disposed on the center side of the semiconductor chip 10A in the second direction A2 as viewed from the empty pad 19A. A plurality of empty pads 19B are sandwiched between a pair of empty pads 19A.

[0065] In the semiconductor device according to the first modification, one or two first wires 71 are connected to the drain pad 18A. Two second wires 72 and two third wires 73 are connected to the dead pad 19B, and one or two first wires 71 and one or two third wires 73 are connected to the pad 63A. In the semiconductor device according to the first modification, the dead pad 19B and the pad 63A are shared as a pad to which a plurality of wires are connected.

[0066] The wire group 70A includes a plurality of first groups 75A and a plurality of second groups 75B, and the order of the wires in the first group 75A and the second group 75B is different from each other. The first group 75A and the second group 75B are alternately arranged along the second direction A2, for example. In the first group 75A, the second wire 72, the third wire 73, and the first wire 71 are arranged so as to be arranged in this order along the second direction A2. In the second group 75B, the first wire 71, the third wire 73, and the second wire 72 are arranged so as to be arranged in this order along the second direction A2. As an example, the number of the first groups 75A and the number of the second groups 75B are 6. For example, the length L3 of the empty pad 19B in the second direction A2 and the length of the pad 63A in the second direction A2 are 500 μm.

[0067] As described above, the semiconductor device according to the first modification includes a plurality of first wires 71 and a plurality of second wires 72. The plurality of adjacent first wires 71 are connected to a common pad 63A. The plurality of adjacent second wires 72 are connected to a common dead pad 19B. Therefore, the pad 63A and the dead pad 19B can be more effectively used as wire connection parts. In addition, the wire length of each wire in the wire group 70A can be further shortened. Since the interval between each wire in the wire group 70A is shortened and the mutual inductance increases, it is possible to shorten the wire length of each wire by the increase in mutual inductance. Therefore, the possibility of each wire in the wire group 70A melting can be further reduced.

[0068] More specifically, as illustrated in Fig. 8, the wire W1 located at the end in the second direction A2 is mainly influenced by the wire W2 closest to it on one side and the next adjacent wire W3. On the other hand, the wire W4 is influenced by the wires W2, W3, W5, and W6 on both sides, so the effective wire length due to the mutual inductance changes significantly compared to the wire W1. If the length of each wire is l, the radius of each wire is r, the height of each wire from the ground is h, the wire spacing is d, and the magnetic permeability of a vacuum is μ0, the mutual inductance is expressed by the following formula (1).

number

[0069] Next, a semiconductor device according to a second modification will be described with reference to Figures 9 and 10. Figure 9 shows the front side of a semiconductor chip 10C and a capacitor 60C according to the second modification. Figure 10 shows the back side of the semiconductor chip 10C and the capacitor 60C. The semiconductor chip 10C has drain pads 18A and 18B, and dead pads 19A and 19B.

[0070] In this modification, the drain pads 18A are provided on both ends of the semiconductor chip 10C in the second direction A2. For example, one first wire 71 is connected to the drain pad 18A. Two first wires 71 are connected to the drain pad 18B. Two second wires 72 and two third wires 73 are connected to the dead pad 19B.

[0071] The capacitor 60C includes a dielectric 61, an upper electrode 62, a pad 63A, and a pad 63B. The pads 63B are provided on both ends of the capacitor 60C in the second direction A2. Two first wires 71 and two third wires 73 are connected to the pad 63A. One first wire 71 and one third wire 73 are connected to the pad 63B. The wire group 70C according to the second modification includes a plurality of first sets 75A and a plurality of second sets 75B arranged along the second direction A2. The second sets 75B and the first sets 75A are arranged alternately along the second direction A2.

[0072] The semiconductor chip 10C further includes a back electrode 10g, and the capacitor 60C further includes a back electrode 67. The back electrode 10g has, for example, a rectangular shape along the long side 12, the long side 13, and the short side 14 of the semiconductor chip 10. The back electrode 10g is provided on the back surface of the semiconductor chip 10C of the gate pad 16 and the active region 17. The back electrode 10g is not provided on the back surface of the semiconductor chip 10C of the drain pads 18A, 18B, and the dead pad 19B. That is, the back electrode 10g is removed from the back side of the drain pads 18A, 18B, and the dead pad 19B in the semiconductor chip 10C.

[0073] The back surface electrode 67 of the capacitor 60C is provided on the back surface of the upper electrode 62. The back surface electrode 67 is not provided on the back surfaces of the pads 63A and 63B of the capacitor 60C. That is, the back surface electrode 67 is removed from the back sides of the pads 63A and 63B in the capacitor 60C.

[0074] As described above, the semiconductor device according to the second modification includes the back surface electrode 67 provided on the back surface of the capacitor 60C in a region other than the region facing the pads 63A and 63B. In this manner, the back surface electrode 67 is not provided on the back surfaces of the pads 63A and 63B, so that the parasitic capacitance generated in the pads 63A and 63B can be suppressed.

[0075] The semiconductor device according to the second modification includes a back surface electrode 10g provided in an area other than the area facing the dead pad 19B on the back surface of the semiconductor chip 10C or the back surface of the substrate 15. In this manner, the back surface electrode 10g is not provided on the back surface of the dead pad 19B, so that the parasitic capacitance generated in the dead pad 19B can be suppressed.

[0076] Next, a semiconductor device according to a third modification will be described with reference to Fig. 11. As shown in Fig. 11, the semiconductor device according to the third modification includes a semiconductor chip 10, a capacitor 60D, and an intermediate substrate 80. The capacitor 60D differs from the above-described capacitor 60 in that it does not have a pad 63. The semiconductor device according to the third modification includes, instead of the pad 63, a intermediate pad 81 (first intermediate pad) provided on an intermediate substrate 80 that is separate from the semiconductor chip 10 and the capacitor 60D.

[0077] The relay board 80 is rectangular in shape with long sides extending in the second direction A2 and short sides extending in the first direction A1. The relay pad 81 is rectangular in shape with long sides extending along the long sides of the relay board 80 and short sides extending along the short sides of the relay board 80. A plurality of first wires 71 extending from each of the plurality of drain pads 18 and a plurality of third wires 73 extending from a plurality of dead pads 19 are connected to the relay pad 81.

[0078] As described above, in the semiconductor device according to the third modified example, the relay pad 81 is provided between the capacitor 60D and the semiconductor chip 10. Therefore, it is possible to arrange the relay pad 81 at a location separated from both the capacitor 60D and the semiconductor chip 10.

[0079] The above describes the embodiments of the semiconductor device according to the present disclosure. However, the present invention is not limited to the above-described embodiments or modifications. In other words, it is easily recognized by those skilled in the art that various modifications and changes are possible within the scope of the present invention without changing the gist of the claims. For example, the shape, size, number, material, and arrangement of each component of the semiconductor device are not limited to the above-described contents and can be appropriately changed.

[0080] For example, in the above embodiment, an example has been described in which the semiconductor chip 10 includes two amplifying elements 11. However, the number of amplifying elements 11 may be one, or may be three or more, and can be changed as appropriate.

[0081] In the above, an example has been described in which relay pads 81 provided on relay substrate 80 separate from semiconductor chip 10 and capacitor 60D are provided instead of pads 63 of capacitor 60. However, relay pads provided on relay substrate 80 separate from semiconductor chip 10 and capacitor 60 may be provided instead of free pads 19 of semiconductor chip 10. In this way, relay pads may be provided integrally with semiconductor chip 10 or capacitor 60, or may be provided separately. The arrangement of relay pads can be changed as appropriate. The number and arrangement of first wire 71, second wire 72, and third wire 73 can also be changed as appropriate. [Explanation of symbols]

[0082] 1...Semiconductor device 2...Input terminal 3...Output terminal 4. Package 4a, 4b...End wall 4c,4d…side wall 4e…Bottom plate 9a, 9b, 9c, 9e, 9f... Bonding wire 10, 10A, 10C...Semiconductor chip 10b…Ag-P layer 10c…Au layer 10d...SiC layer 10f…GaN layer 10g…Back electrode 11...Amplification element 12...Long side (one side) 13…Long side 14…Short side 15...Substrate 16…Gate pad 17…Active region 18, 18A, 18B...Drain pad (electrode pad) 19, 19A, 19B...Empty pads (second relay pads) 20...Branch circuit board 21...Substrate 21a, 21b...Long side 21c, 21d…Short side 22...Branch circuit 23...Wiring pattern 23a…Metal pad 23b…Membrane resistance 30...Composite circuit board 31...Substrate 31a, 31b...Long side 31c, 31d…short side 31e, 31f…corner 32...Synthetic substrate 33...Wiring pattern 33a…Metal pad 33b…Membrane resistance 40...Filter circuit 50…Capacitor 60, 60A, 60C, 60D... Capacitors 60b…Ag-P layer 60c…Au layer 60d…ceramic layer 61...Dielectric 62…Top electrode 63, 63A, 63B...Pad (first relay pad) 64...Long side (one side) 65…Long side 66…Short side 67…Back electrode 70, 70A, 70C...Wire group 71…First wire 72…Second wire 73…Third wire 75...group 75A…1st group 75B…2nd group 80...Relay board 81...Relay pad (first relay pad) A1…first direction A2…Second direction d…Spacing M: Mutual inductance W1, W2, W3, W4, W5, W6…Wire

Claims

1. a semiconductor chip having a transistor and an electrode pad provided on a substrate; a capacitor having upper and lower electrodes sandwiching a dielectric; A first relay pad; a second relay pad provided on the substrate of the semiconductor chip; a first wire connecting the first relay pad and the electrode pad of the semiconductor chip to each other; a second wire connecting the second relay pad and the upper electrode of the capacitor to each other; a third wire connecting the first relay pad and the second relay pad to each other; Equipped with the first relay pad is disposed on the dielectric of the capacitor at a position spaced apart from the upper electrode, The second relay pad is disposed along one side of the semiconductor chip. Semiconductor device.

2. a semiconductor chip having a transistor and an electrode pad provided on a substrate; a capacitor having upper and lower electrodes sandwiching a dielectric; A first relay pad; a second relay pad provided on the substrate of the semiconductor chip; a first wire connecting the first relay pad and the electrode pad of the semiconductor chip to each other; a second wire connecting the second relay pad and the upper electrode of the capacitor to each other; a third wire connecting the first relay pad and the second relay pad to each other; Equipped with The electrode pads are arranged along one side of the semiconductor chip, The second relay pad is disposed adjacent to the electrode pad. Semiconductor device.

3. a semiconductor chip having a transistor and an electrode pad provided on a substrate; a capacitor having upper and lower electrodes sandwiching a dielectric; A first relay pad; a second relay pad provided on the substrate of the semiconductor chip; a first wire connecting the first relay pad and the electrode pad of the semiconductor chip to each other; a second wire connecting the second relay pad and the upper electrode of the capacitor to each other; a third wire connecting the first relay pad and the second relay pad to each other; Equipped with A plurality of the first relay pads arranged along one side of the capacitor; a plurality of the second relay pads and a plurality of the electrode pads arranged along one side of the semiconductor chip; Equipped with Each of the second relay pads is disposed adjacent to the electrode pad. Semiconductor device.

4. A plurality of the first wires and a plurality of the second wires, each of the first wires adjacent to each other is connected to a common first relay pad; Each of the plurality of second wires adjacent to each other is connected to a common second relay pad. The semiconductor device according to claim 1 .

5. a back surface electrode provided on a back surface of the dielectric of the capacitor in an area other than an area facing the first relay pad; The semiconductor device according to claim 1 .

6. a back surface electrode provided on a back surface of the semiconductor chip or a back surface of the substrate in an area other than an area facing the second relay pad; The semiconductor device according to claim 1 .

7. the first relay pad is provided between the capacitor and the semiconductor chip; The semiconductor device according to claim 1 .

8. The substrate is made of silicon carbide (SiC), diamond, or metal. The semiconductor device according to claim 1 .

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