Semiconductor structure, transistor including same, and method for making same - Patents.com

Abstract

To provide a semiconductor structure, a transistor including the same, and a manufacturing method for the transistor.SOLUTION: A semiconductor structure includes a substrate, one or more mask layers disposed apart from the substrate in a first direction, a first semiconductor region with a first conductivity type disposed between the substrate and the mask layer, a second semiconductor region with a second conductivity type disposed on the mask layer, and a third semiconductor region with the first conductivity type disposed on the first semiconductor region and formed in contact with the second semiconductor region so that a PN junction structure is formed in a second direction that is different from the first direction. Thus, the semiconductor structure is used for a vertical type power element, and the withstanding voltage performance can be increased and the on resistance can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor structure, a transistor including the same, and a method for making the same. [Background technology]

[0002] In a power conversion system that receives a main power source, converts it into a voltage required by a large number of elements, and distributes it, the role of a power switching element is important. The power switching element may be realized by a transistor based on a semiconductor material such as silicon, GaN, or SiC, such as a metal oxide semiconductor field effect transistor (MOSFET). Such a power switching element is required to have a high breakdown voltage, and much research is being conducted to reduce the on-resistance, achieve high integration, and obtain a fast switching characteristic.

[0003] Vertical GaN power devices, which are currently being developed by many manufacturers and academia, generally use n-type doped GaN epitaxial layers to create vertical channels and drift regions. In this case, the channel length must be increased to increase the voltage that the device can withstand. However, when the channel is longer, the on-resistance increases. In addition, to increase the channel length, the GaN epitaxial layer must be formed thick, but when a thick GaN is grown on a heterogeneous substrate, warping, defects, and breakage occur due to the difference in lattice constant, and when a homogeneous GaN substrate is used, the cost is very high, the wafer size is small, and mass productivity is low. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem that the present invention aims to achieve is to provide a semiconductor structure that can be applied to a vertical power device.

[0005] Another object of the present invention is to provide a vertical power element that utilizes the semiconductor structure and has a low on-resistance and an improved withstand voltage. [Means for solving the problem]

[0006] According to one type, there is provided a semiconductor structure including a substrate, one or more mask layers spaced apart from the substrate in a first direction, a first semiconductor region of a first conductivity type disposed between the substrate and the mask layers, a second semiconductor region of a second conductivity type disposed on the mask layers, and a third semiconductor region of the first conductivity type disposed on the first semiconductor region and formed in contact with the second semiconductor region such that a PN junction structure is formed along a second direction different from the first direction.

[0007] The third semiconductor region may have a shape extending in the first direction from a surface of the first semiconductor region where the mask layer is not disposed, and extending to an upper region of the mask layer.

[0008] The second semiconductor region is also formed in contact with the mask layer. The mask layer may also be made of an insulating material that inhibits semiconductor growth.

[0009] The semiconductor structure may further include a high concentration layer disposed between the substrate and the first semiconductor region and doped more highly than the first semiconductor region.

[0010] The first semiconductor region, the second semiconductor region, and the third semiconductor region may each include a III-V compound semiconductor, where the III group includes at least one element of boron (B), aluminum (Al), gallium (Ga), and indium (In), and the V group includes a nitrogen element. The first semiconductor region and the third semiconductor region are also made of compound semiconductors having the same composition.

[0011] Also, according to one type, there is provided a transistor including: a drain electrode; one or more mask layers spaced apart from the drain electrode in a first direction; a first drift region of a first conductivity type arranged between the drain electrode and the mask layer; a channel region of a second conductivity type arranged on the mask layer; a second drift region arranged on the first drift region and formed in contact with the channel region such that a PN junction structure is formed along a second direction different from the first direction; a source electrode arranged on the channel region; and a gate electrode arranged on the second drift region.

[0012] The channel region extends in the first direction from a surface of the first drift region where the mask layer is not disposed, and also has a shape extending to an upper region of the mask layer.

[0013] The channel region is also formed in contact with the mask layer. The mask layer may also be made of an insulating material that inhibits semiconductor growth.

[0014] The semiconductor device may further include a drain region disposed between the drain electrode and the first drift region and doped with a first conductivity type dopant at a high concentration.

[0015] The drain region is also formed in direct contact with the first drift region. The first drift region, the channel region, and the second drift region may include III-V compound semiconductors, where the III group includes at least one element of boron (B), aluminum (Al), gallium (Ga), and indium (In), and the V group includes a nitrogen element.

[0016] The source electrode is also formed in direct contact with the channel region. The transistor may further include a source region disposed between the channel region and the source electrode and doped with a high concentration of a dopant of a first conductivity type.

[0017] The source electrode may have a shape in which one end region penetrates the source region and directly contacts the channel region.

[0018] The source electrode may have a shape in which one end region penetrates the source region and extends into the channel region.

[0019] The gate electrode may be disposed adjacent to the channel region and the second drift region, and a gate insulating film may be further provided surrounding the gate electrode such that the gate electrode is insulated from the channel region and the second drift region.

[0020] The transistor may further include a two-dimensional electron gas (2DEG) inducing layer disposed between the second drift region and the source electrode, made of a semiconductor material having a different composition from a semiconductor material constituting the second drift region, and inducing a two-dimensional electron gas (2DEG) layer in the second drift region.

[0021] The source electrode may have a shape in which one end region penetrates the two-dimensional electron gas inducing layer and directly contacts the channel region.

[0022] The source electrode may have a shape in which one end region penetrates the two-dimensional electron gas inducing layer and extends into the channel region. The second drift region has a thickness greater than a thickness of the first drift region.

[0023] Also, according to one type, there is provided a method for manufacturing a transistor, including: forming a first drift region of a first conductivity type on a substrate; forming one or more mask layers on the first drift region; growing a semiconductor from a surface of the first drift region that is not covered by the mask layer to form a second drift region; forming a channel region of a second conductivity type on the mask layer; forming a source electrode on the channel region; forming a gate electrode on the second drift region; and forming a drain electrode below the first drift region.

[0024] The method may further include forming a drain region on the substrate, the drain region being heavily doped with the first conductivity type dopant, before forming the first drift region on the substrate.

[0025] The step of forming the first drift region also includes placing the drain region in direct contact with the first drift region.

[0026] In the step of forming the channel region, the entire surface of the mask layer that is not covered by the first drift region is also covered by the channel region.

[0027] The step of forming the source electrode also includes directly contacting the source electrode to the channel region. Effect of the Invention

[0028] The aforementioned transistor is a vertical transistor including a horizontal PN junction structure, which can effectively reduce the on-resistance (Ron) of the transistor while increasing the withstand voltage. Thus, the above-described transistors are also applicable to a wide variety of high power devices. [Brief description of the drawings]

[0029] [Figure 1] 1 is a cross-sectional view illustrating a schematic structure of a semiconductor structure according to one embodiment. [Diagram 2] 1 is a cross-sectional view showing a schematic structure of a transistor according to an embodiment; [Figure 3A] 3 is a diagram showing the change in the depletion region when the transistor in FIG. 2 is turned on (ON). [Figure 3B] 3 is a diagram showing a change in the depletion region when the transistor of FIG. 2 is turned off (OFF). [Figure 4] FIG. 11 is a cross-sectional view showing a schematic structure of a transistor according to another embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a schematic structure of a transistor according to yet another embodiment. [Figure 6] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 7] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 8] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 9] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 10] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 11] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 12] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 13] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 14] 1 is a diagram illustrating a method of manufacturing a transistor according to an embodiment. [Figure 15] 11 is a diagram illustrating a method of manufacturing a transistor according to another embodiment. [Figure 16] 11 is a diagram illustrating a method of manufacturing a transistor according to another embodiment. [Figure 17]11 is a diagram illustrating a method of manufacturing a transistor according to another embodiment. [Figure 18] 11 is a diagram illustrating a method of manufacturing a transistor according to another embodiment. [Figure 19] 11 is a diagram illustrating a method of manufacturing a transistor according to another embodiment. [Figure 20] 11 is a diagram illustrating a method of manufacturing a transistor according to another embodiment. [Figure 21] FIG. 11 is a cross-sectional view showing a schematic structure of a transistor according to another embodiment. [Figure 22] FIG. 11 is a cross-sectional view showing a schematic structure of a transistor according to another embodiment. [Figure 23] 1 is a diagram showing a schematic configuration of an electronic device according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings. The described embodiment is merely exemplary, and various modifications are possible from such an embodiment. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings is exaggerated for clarity and convenience of description.

[0031] In the following description, the words "upper" or "above" may include not only something that is directly above in contact with something, but also something that is above without contacting something.

[0032] Terms such as first and second may be used to describe various components, but are used only to distinguish one component from another, and are not intended to limit the components to differing materials or structures.

[0033] The singular expression includes the plural expression unless the context clearly indicates otherwise. Furthermore, when a part "includes" a certain element, it does not mean excluding other elements, but means that other elements may be further included, unless otherwise specified to the contrary.

[0034] In addition, terms such as "unit" and "module" used in the specification refer to a unit that processes at least one function or operation, and may be realized by hardware or software, or a combination of hardware and software.

[0035] Use of the terms "said" and similar referents refers to both the singular and the plural.

[0036] The steps constituting the method may be performed in any suitable order unless expressly stated to be performed in the order described. In addition, the use of all exemplary terms (such as, for example, etc.) is merely for the purpose of explaining the technical idea in detail, and the scope of the right is not limited by such terms, except as limited by the claims.

[0037] FIG. 1 is a cross-sectional view showing a schematic structure of a semiconductor structure according to one embodiment. 1, the semiconductor structure 100 includes a substrate SUB, a first semiconductor region 11 formed on the substrate SUB, one or more mask layers 13 disposed on the first semiconductor region 11, a second semiconductor region 14 formed on the mask layer 13, and a third semiconductor region 12 formed on the first semiconductor region 11. A buffer layer 5 may further be provided between the substrate SUB and the first semiconductor region 11.

[0038] The substrate SUB is sapphire (Al 2 O 3 ) substrate, silicon (Si) substrate, silicon carbide (SiC) substrate, metal substrate, GaN substrate, etc. may be used.

[0039] The buffer layer 5 is introduced to reduce the occurrence of defects, cracks, stress, etc. caused by mismatch in lattice constants and thermal expansion coefficients between the substrate SUB and the semiconductor material constituting the first semiconductor region 11, and to realize a semiconductor layer with good quality.

[0040] For example, when the substrate SUB is a silicon substrate and the first semiconductor region 11 includes GaN, if a GaN thin film is grown directly on the silicon substrate, thermal tensile stress is generated in the nitride semiconductor thin film during cooling due to the difference in thermal expansion coefficient between Si and GaN, which may cause warping of the substrate SUB. Furthermore, if the thermal tensile stress exceeds a critical point, cracks may occur. Furthermore, defects may occur due to the difference in lattice constants.

[0041] Although the buffer layer 5 is illustrated as a single layer, it is not limited thereto and may have a multi-layer structure. The material and structure of the buffer layer 5 are determined taking into consideration the material of the substrate SUB and the semiconductor material used for the first semiconductor region 11.

[0042] The first semiconductor region 11 is also a semiconductor layer doped with a dopant of a first conductivity type. The first conductivity type may be n-type. The first semiconductor region 11 may include a III-V compound semiconductor. The first semiconductor region 11 may include a nitride semiconductor that employs at least one of boron (B), aluminum (Al), gallium (Ga), and indium (In) as a group III element, and employs a nitrogen element as a group V element. The first semiconductor region 11 may include n-type GaN.

[0043] A mask layer 13 is formed on the first semiconductor region 11. The mask layer 13 may include an insulating material that inhibits semiconductor growth, and may include, for example, various oxides and nitrides. The mask layer 13 may be SiO 2 or SiN x may include:

[0044] The mask layer 13 is disposed apart from the substrate SUB in a first direction (Z direction), covers a part of the surface of the first semiconductor region 11, and is provided to form a PN junction structure on the upper part of the first semiconductor region 11 along a second direction different from the first direction. The second direction is also the X direction. A semiconductor is grown from the surface of the first semiconductor region 11 that is not covered by the mask layer 13, and then a semiconductor is grown on the mask layer 13, thereby forming a semiconductor structure having a predetermined desired structure. Although two mask layers 13 are illustrated, this is for illustrative purposes only, and one or various multiple mask layers may be used.

[0045] The second semiconductor region 14 is disposed on the mask layer 13. The second semiconductor region 14 is also a semiconductor layer doped with a dopant of a second conductivity type. The second conductivity type may be p-type. The second semiconductor region 14 may include a III-V compound semiconductor. The second semiconductor region 14 may include a nitride semiconductor that employs at least one element of boron (B), aluminum (Al), gallium (Ga), and indium (In) as the III group element, and employs a nitrogen element as the V group. The second semiconductor region 14 may include a p-type GaN.

[0046] The third semiconductor region 12 is disposed on the first semiconductor region 11. The third semiconductor region 12 is also a semiconductor layer doped with a dopant of the first conductivity type, the same as the first semiconductor region 11. The first conductivity type may be n-type. The third semiconductor region 12 may include a semiconductor having the same composition as the first semiconductor region 11. The third semiconductor region 12 may include a III-V compound semiconductor. The third semiconductor region 12 may include a nitride semiconductor that employs at least one element of boron (B), aluminum (Al), gallium (Ga), and indium (In) as a group III element, and employs a nitrogen element as group V. The third semiconductor region 12 may include n-type GaN.

[0047] As shown in the figure, the third semiconductor region 12 extends in a first direction (Z direction) from the surface of the first semiconductor region 11 where the mask layer 13 is not disposed, and also extends to the upper region of the mask layer 13. This is because when a semiconductor is grown from the surface of the first semiconductor region 11 where the mask layer 13 is not disposed, growth occurs not only in the first direction, which is the growth direction, but also in a second direction parallel to the first direction. As a result, a boundary surface BS is formed obliquely on the upper portion of the mask layer 13, and the boundary surface BS becomes a PN junction surface. However, the illustrated shape is merely exemplary, and the boundary surface BS may have a more gentle or steeper inclination with respect to the mask layer 13.

[0048] The thickness t2 of the third semiconductor region 12 is thicker than the thickness t1 of the first semiconductor region 11. Such thickness setting is intended to further enhance the effect of increasing the withstand voltage due to the above-mentioned PN junction surface when the semiconductor structure 100 is employed in, for example, a vertical transistor, which will be described later with reference to Figures 2, 3A, and 3B.

[0049] The semiconductor structure 100 may further include a high concentration layer 10 disposed between the substrate SUB and the first semiconductor region 11 and doped more heavily than the first semiconductor region 11. The high concentration layer 10 may include a semiconductor doped with a dopant of the first conductivity type, similar to the first semiconductor region 11. The high concentration layer 10 is also formed in direct contact with the first semiconductor region 11. The high concentration layer 10 may include GaN.

[0050] The semiconductor structure 100 is a structure that can be used for various electronic devices, and the illustrated shape can be processed in various ways. For example, if the substrate SUB is made of a metal material, it can also be used as an electrode, and if it is made of another material, the substrate SUB can be removed from the semiconductor structure 100 and an electrode can be formed on the lower surface of the high concentration layer 10. In addition, the second semiconductor region 14 is illustrated as a shape in which semiconductor materials formed on the mask layers 13 spaced apart from each other are joined together at the top, but this is merely an example, and the second semiconductor region 14 can be processed into various shapes depending on the shapes of the gate electrode and source electrode provided at the top.

[0051] Various embodiments of electronic devices utilizing the above-described structures will now be described. FIG. 2 is a cross-sectional view showing a schematic structure of a transistor according to one embodiment, and FIGS. 3A and 3B are diagrams showing a comparison of changes in the depletion region when the transistor of FIG. 2 is turned on and off, respectively.

[0052] The transistor 101 according to an embodiment is a field effect transistor, and is also a high power transistor, particularly a high power metal-oxide-semiconductor field-effect transistor (MOSFET), that can be used as a power switching element. The transistor 101 according to an embodiment employs a structure in which a PN junction structure is formed in a direction perpendicular to the direction in which the source electrode S and the drain electrode D are spaced apart, in order to have a withstand voltage characteristic capable of withstanding a high voltage while reducing an on-state resistance (on-resistance (Ron)).

[0053] The detailed structure of the transistor 101 will be described below. The transistor 101 includes a drain electrode D, one or more mask layers 130 spaced apart from the drain electrode D in a first direction (Z direction), a first drift region 121 of a first conductivity type arranged between the drain electrode D and the mask layer 130, a channel region 141 of a second conductivity type arranged on the mask layer 130, a second drift region 122 formed on the first drift region 121 so as to be in contact with the channel region 141, a source electrode S arranged on the channel region 141, and a gate electrode G arranged on the second drift region 122.

[0054] In addition, a drain region 110 doped with a high concentration of a first conductive type dopant may be further provided between the drain electrode D and the first drift region 121, and a source region 160 doped with a high concentration of a first conductive type dopant may be further provided between the source electrode S and the channel region 141. The first drift region 121 may include a III-V compound semiconductor doped with a dopant of a first conductivity type. The first drift region 121 may include, for example, n(-)GaN or n(-)AlGaN. For example, silicon (Si) may be used as the n-type dopant.

[0055] The doping concentration and thickness of the first drift region 121 are major factors in determining the on-resistance (Ron) and voltage resistance of the transistor 101. To improve the voltage resistance, the first drift region 121 can be made thicker and the doping concentration can be made lower. However, making the first drift region 121 thick is generally limited due to defects that occur during the process of forming a nitride semiconductor on a heterogeneous substrate. In addition, lowering the doping concentration of the first drift region 121 results in an increase in the on-resistance, so the doping concentration must be set in consideration of the on-resistance and voltage resistance.

[0056] The mask layer 130 is formed on the first drift region 121. The mask layer 130 may include an insulating material that inhibits semiconductor growth, such as various oxides and nitrides. The mask layer 130 may be SiO 2 or SiN x may include:

[0057] The mask layer 130 is disposed in a first direction (Z direction) away from the substrate SUB, covers a part of the surface of the first drift region 121, and is provided to form a PN junction structure on the upper part of the first drift region 121 along a second direction different from the first direction. The second direction is also the X direction. A semiconductor is grown from the surface of the first drift region 121 that is not covered by the mask layer 130, and then a semiconductor is grown on the mask layer 130, thereby forming a semiconductor structure having a predetermined desired structure. Although two mask layers 130 are illustrated, this is for illustrative purposes only, and one or various multiple mask layers may be set.

[0058] The channel region 141 is disposed on the mask layer 130. The channel region 141 may include a III-V compound semiconductor doped with a dopant of a second conductivity type. The channel region 141 may include, for example, p-type GaN. Alternatively, the channel region 141 may include p-type AlGaN, BAlGaN, BAlInGaN, InGaN, or BInGaN. For example, Mg may be used as the p-type dopant.

[0059] The second drift region 122 is disposed on the first drift region 121. The second drift region 122 and the first drift region 121 constitute the drift region 120. The second drift region 122 may include a III-V compound semiconductor doped with a dopant of the first conductivity type, the same as the first drift region 121. The second drift region 122 may include a semiconductor having the same composition as the first drift region 121. The second drift region 122 may include, for example, n-GaN.

[0060] As shown in the figure, the second drift region 122 extends in a first direction (Z direction) from the surface of the first drift region 121 where the mask layer 130 is not disposed, and also extends to the upper region of the mask layer 130. This is because when a semiconductor is grown from the surface of the first drift region 121 where the mask layer 130 is not disposed, growth occurs not only in the first direction, which is the growth direction, but also in a second direction parallel thereto. As a result, a boundary surface BS is formed obliquely on the upper portion of the mask layer 130, and the boundary surface BS becomes a PN junction surface. However, the illustrated shape is merely exemplary, and the boundary surface BS may have a more gentle or steeper inclination with respect to the mask layer 130.

[0061] In this way, the channel region 141 and the second drift region 122 form a PN junction structure in the X direction by semiconductor growth using the mask layer 130. Such a horizontal PN junction structure can form depletion regions 190 and 195 as shown in Figures 3A and 3B, and can improve the voltage endurance performance, as will be described further below.

[0062] The source electrode S is disposed on the channel region 141, and the source electrode S is also formed to be in direct contact with the channel region 141. The source electrode S may have a shape in which one end region penetrates the source region 160 and directly contacts the channel region 141. As shown in the figure, the source electrode S may have a shape in which one end region penetrates the source region and extends into the channel region 141.

[0063] The gate electrode G is disposed on the second drift region 122 so as to be adjacent to the channel region 141. In addition, a gate insulating film 180 may be provided surrounding the gate electrode G so that the gate electrode G is insulated from the channel region 141 and the second drift region 122.

[0064] A source region 160 between the channel region 141 and the source electrode S may comprise a semiconductor doped with a dopant of the first conductivity type. The source region 160 is also more heavily doped than the channel region 141. The source region 160 may comprise n(+)GaN, n(+)AlGaN, n(+)BAlGaN, n(+)BAlInGaN, n(+)InGaN or n(+)BInGaN.

[0065] The drain region 110 between the drain electrode D and the first drift region 121 may comprise a semiconductor doped with a dopant of the first conductivity type. The drain region 110 is also formed in direct contact with the first drift region 121. The drain region 110 is also more heavily doped than the first drift region 121. The drain region 110 may comprise n(+)GaN or n(+)AlGaN.

[0066] The gate electrode G, the drain electrode D and the source electrode S are also made of a conductive material. For example, the materials of the gate electrode G, the drain electrode D and the source electrode S may include a metal, an alloy, a conductive metal oxide or a conductive metal nitride.

[0067] The gate electrode G is also formed by forming a trench vertically penetrating the source region 160 and the channel region 141 via etching so that a part of the second drift region 122 is exposed to the outside, forming a gate insulating film 180 on the bottom surface and inner wall of the trench, and then filling the inside of the trench with a conductive material. Therefore, both side surfaces of the gate electrode G are also disposed so as to face the side surfaces of the source region 160 and the side surfaces of the channel region 141. In addition, the lower surface of the gate insulating film 180 contacts the second drift region 122, and a part of the side surface of the gate insulating film 180 can also contact the second drift region 122. The gate insulating film 180 can be formed of a material such as silicon nitride (SiN), silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), aluminum oxynitride (AlON), tantalum oxide (Ta2 O 5 ), hafnium oxide (HfO 2 ), or a variety of other high-K dielectric materials.

[0068] When a voltage is applied to the gate electrode G, a current flows between the source region 160 and the drain region 110, so that the drain region 110, the first drift region 121, the second drift region 122, and the source region 160 are doped to have the same electrical polarity. For example, they are all doped to n-type. Among them, the drain region 110 and the source region 160 are doped to a high concentration. The drain region 110 and the source region 160 are also doped to n(+).

[0069] The first drift region 121 and the second drift region 122 are also doped with a low concentration n(-) lower than the n(+) doping concentration in order to provide them with a withstand voltage characteristic capable of withstanding a high voltage. However, as mentioned above, it should be noted that lowering the doping concentration of the regions lowers the on-resistance of the transistor.

[0070] In the transistor 101 according to one embodiment, a PN junction structure is formed by the channel region 141 and the second drift region 122 in the horizontal direction (X direction), i.e., in the direction perpendicular to the direction in which the source electrode S and the drain electrode D are separated (Z direction), as a structure for improving the withstand voltage characteristics. Since this structure serves to improve the withstand voltage performance, the first drift region 121 and the second drift region 122 can have a higher n-type doping concentration than when such a PN junction structure is not provided.

[0071] For example, the drain region 110 and the source region 160 are 10 19 / cm 3 The first drift region 121 and the second drift region 122 are doped to a doping concentration of 10 15 / cm 3 ~10 18 / cm 3It is also doped to a range of doping concentrations.

[0072] Meanwhile, the thickness t2 of the second drift region 122 is thicker than the thickness t1 of the first drift region 121. Here, the thickness t2 of the second drift region 122 refers to the distance from the upper surface of the mask layer 130 to the uppermost end of the boundary surface BS. In the respect that the first drift region 121 and the second drift region 122 are major factors in the on-resistance and withstand voltage performance, the description of the thickness difference does not mean that the thicker the second drift region 122, the more desirable it is. It means that the ratio of the thickness t2 of the second drift region 122 to the total thickness set for the first drift region 121 and the second drift region 122 is higher than the ratio of the thickness t1 of the first drift region 121. The thickness t1 of the first drift region 121 can be minimized within a range appropriate for forming the mask layer 130 and forming a PN junction structure on the mask layer 130.

[0073] Unlike the present embodiment, in the case of a transistor that does not have a horizontal PN junction structure, the doping concentration of the drift region is generally 10 17 / cm 3 , which would result in a high on-resistance.

[0074] In other words, the transistor of the present embodiment employs a structure that allows for high doping of the drift region for a given drift region thickness requirement and voltage resistance requirement, thereby effectively lowering the on-resistance.

[0075] 3A and 3B, the states in which transistor 101 is turned on and off, respectively, will be described.

[0076] 3A shows a state in which transistor 101 is turned on and a turn-on voltage is applied to gate electrode G. A channel path is formed from source electrode S to channel region 141, first drift region 121, second drift region 122, drain region 110, and drain electrode D.

[0077] Due to the arrangement in which the source electrode S is in direct contact with the channel region 141, a channel path from the source electrode S to the drain electrode D is formed such that charge carriers pass through the p-type region, the PN junction, and the n-type region.

[0078] 3B shows a state in which the transistor 101 is turned off, that is, a voltage less than the turn-on voltage is applied to the gate electrode G. As a result, if the voltage of the lower n-type drift region 120 becomes high due to the high voltage of the drain electrode D, a reverse voltage is applied to the PN junction. At this time, the depletion region 190 shown in FIG. 3A becomes wider like the depletion region 195 in FIG. 3B, and the charge carriers are effectively depleted. Due to this phenomenon, the current can be effectively suppressed under high voltage even when the doping concentration of the drift region 120 is high.

[0079] Furthermore, the thickness t2 of the second drift region 122 in which the depletion region is formed is made thicker than the thickness t1 of the first drift region 121, so that the effect of suppressing the current under high voltage can be further improved.

[0080] As such, the horizontal PN junction structure allows for a high breakdown voltage, which allows for a high doping concentration in the drift region 120 without compromising the breakdown voltage performance, resulting in a low on-resistance.

[0081] The above-described structure of the transistor 101 is also called a trench MOSFET, and the concept of the embodiment of increasing the withstand voltage and decreasing the on-resistance can be applied to various types of vertical transistors other than the above-described structure, such as high electron mobility transistors (HEMTs), current-aperture vertical electron transistors (CAVETs), and fin field effect transistors (FinFETs).

[0082] FIG. 4 is a cross-sectional view showing a schematic structure of a transistor according to another embodiment. The transistor 102 according to this embodiment is an example applied as a high electron mobility transistor (HEMT), and differs from the above-described transistor 101 mainly in that a two-dimensional electron gas (2DEG) inductive layer 165 is provided.

[0083] The transistor 102 includes a drain electrode D, one or more mask layers 130 spaced apart from the drain electrode D in a first direction (Z direction), a first drift region 121 of a first conductivity type disposed between the drain electrode D and the mask layer 130, a channel region 142 of a second conductivity type disposed on the mask layer 130, a second drift region 122 formed on the first semiconductor region 11 so as to be in contact with the channel region 142, a source electrode S disposed on the channel region 142, and a gate electrode G disposed on the second drift region 122. In addition, a drain region 110 doped with a high concentration of a first conductivity type dopant may be further provided between the drain electrode D and the first drift region 121.

[0084] A two-dimensional electron gas inducing layer 165 is disposed on the second drift region 122, the two-dimensional electron gas inducing layer 165 being made of a semiconductor material having a different composition from the semiconductor material constituting the second drift region 122 and inducing a two-dimensional electron gas layer 2DEG in the second drift region 122. The two-dimensional electron gas inducing layer 165 is also formed to be in contact with the second drift region 122, and a source electrode S and a drain electrode D are disposed on the two-dimensional electron gas inducing layer 165.

[0085] The source electrode S may have one end region penetrating the two-dimensional electron gas inducing layer 165 and directly contacting the channel region 142. As shown in the figure, the source electrode S may have a shape in which one end region penetrating the two-dimensional electron gas inducing layer 165 and extending into the channel region 142.

[0086] The two-dimensional electron gas inducing layer 165 is formed on the second drift region 122 and is made of a material capable of inducing a two-dimensional electron gas layer 2DEG in the second drift region 122. The two-dimensional electron gas inducing layer 165 may include a III-V group semiconductor. For example, the two-dimensional electron gas inducing layer 165 may include AlGaN, AlInN, etc. Such AlGaN, AlInN, etc. have a higher polarizability than the second drift region 122, and therefore can induce a two-dimensional electron gas layer 2DEG in the second drift region 122. When the second drift region 122 is a GaN layer, the two-dimensional electron gas inducing layer 165 may also be an AlGaN layer or an AlInN layer. When the second drift region 122 is an InN layer, the two-dimensional electron gas inducing layer 165 may also be an AlInN layer. The two-dimensional electron gas inducing layer 165 may also be a layer doped with n-type impurities. The two-dimensional electron gas inducing layer 165 may have a multi-layer structure including a plurality of layers of different materials. The materials of the two-dimensional electron gas inducing layer 165 may be variously changed in addition to those exemplified.

[0087] The two-dimensional electron gas inducing layer 165 allows the two-dimensional electron gas layer 2DEG formed in the second drift region 122 to have a high electron concentration.

[0088] In the transistor 102 of FIG. 4, the concept of the channel region 142 and the second drift region 122 forming a horizontal PN junction structure is applied to the basic structure of a HEMT used in a power device, and the structure can be modified in various ways. For example, a gate insulating layer 180 (FIG. 21) and / or a depletion layer 182 (FIG. 22) may be further provided between the gate electrode G and the two-dimensional electron gas inducing layer 165. Also, a portion of the two-dimensional electron gas inducing layer 165 where the gate electrode G is to be formed may be recessed to a predetermined depth to form a recess region (not shown), and then the gate electrode G may be formed in the recess region. In this case, the characteristics of the two-dimensional electron gas layer 2DEG corresponding to the recess region may change, and the characteristics of the HEMT may be adjusted. In addition, various modifications to the structure are possible within the range in which the source electrode S and the drain electrode D are vertically arranged.

[0089] FIG. 5 is a cross-sectional view showing a schematic structure of a transistor according to still another embodiment. The transistor 104 of this embodiment differs from the above-described transistors 101 and 102 in that it is applied as a fin field effect transistor (Fin FET) structure.

[0090] The transistor 104 includes a drain electrode D, one or more mask layers 130 spaced apart from the drain electrode D in a first direction (Z direction), a first drift region 121 of a first conductivity type disposed between the drain electrode D and the mask layer 130, a channel region 144 of a second conductivity type disposed on the mask layer 130, a second drift region 122 formed on the first drift region 121 so as to be in contact with the channel region 144, a source electrode S disposed on the channel region 144, and a gate electrode G disposed on the second drift region 122. In addition, a drain region 110 doped with a dopant of the first conductivity type at a high concentration may be further provided between the drain electrode D and the first drift region 121, and a source region 160 doped with a dopant of the first conductivity type at a high concentration may be further provided between the source electrode S and the channel region 144.

[0091] The source electrode S is formed to directly contact the channel region 144, and may have a shape extending into the channel region 144 through the source region 160 as shown in the figure. The source electrode S is arranged in a fin shape so as to be repeated with the gate electrode G.

[0092] 6 to 14 are diagrams illustrating a method of manufacturing a transistor according to an embodiment.

[0093] 6, a first drift region 121 is formed on a substrate SUB. Before forming the first drift region 121, a high concentration drain region 110 may be formed. To form the drain region 110, a buffer layer 105 may first be formed on the substrate SUB. The first drift region 121 is also formed to be in direct contact with the drain region 110.

[0094] The substrate SUB is sapphire (Al 2 O 3 A silicon (Si) substrate, a silicon carbide (SiC) substrate, a metal substrate, a GaN substrate, etc. may be used. If the substrate SUB is made of a metal material, it may also be used as the drain electrode. In other cases, the substrate SUB may be removed and a drain electrode may be formed under the drain region 110.

[0095] The buffer layer 105 is introduced to reduce defects, cracks, stress, etc. caused by lattice constant mismatch and thermal expansion coefficient mismatch between the substrate SUB and the semiconductor material constituting the drain region 110, and to realize a semiconductor layer with good quality. Although the buffer layer 105 is illustrated as a single layer, it is not limited thereto and may have a multi-layer structure. The material and structure of the buffer layer 105 are determined taking into consideration the material of the substrate SUB and the semiconductor material used in the drain region 110.

[0096] The drain region 110 and the first drift region 121 include a semiconductor material doped with a dopant of a first conductivity type. The drain region 110 and the first drift region 121 may include a III-V compound semiconductor and are grown by an epitaxial growth process. The epitaxial growth process may include a metal organic chemical vapor deposition process, a liquid phase epitaxy process, a hydride vapor phase epitaxy process, a molecular beam epitaxy process, or a metal organic vapor phase epitaxy growth process. Si may be used as the first conductivity type dopant.

[0097] The drain region 110 is also doped to a higher concentration than the first drift region 121. 19 / cm 3 The first drift region 121 is doped to a doping concentration of 10 15 / cm 3 ~10 18 / cm 3 The first drift region 121 is also doped with a doping concentration in the range of 10 17 / cm 3 ~10 18 / cm 3 The range is also doped.

[0098] 7, a mask layer 130 is formed on the first drift region 121. One or more mask layers 130 may be formed to cover a portion of the surface of the first drift region 121. The mask layer 130 may include an insulating material that inhibits the growth of a semiconductor, and may include, for example, various oxides and nitrides. The mask layer 130 may be formed of SiO 2 , SiN x Or Al 2 O 3The mask layer 130 may also be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

[0099] 8, a semiconductor is grown from a surface of the first drift region 121 that is not covered with the mask layer 130 to form the second drift region 122. The second drift region 122 is disposed on the first drift region 121. The second drift region 122 may include a semiconductor having the same composition as the first drift region 121, and may be grown by any of the various epitaxial growth methods described above.

[0100] As shown in the figure, the second drift region 122 is grown vertically from the surface of the first drift region 121 where the mask layer 130 is not disposed, and is also grown horizontally toward the upper region of the mask layer 130. As a result, the second drift region 122 has a shape having an inclined interface surface BS at its upper portion in the mask layer 130. The interface surface BS also becomes a PN junction surface.

[0101] 9, a channel material layer 140 for a channel region is formed on the mask layer 130. The channel material layer 140 is also formed by growing a semiconductor from the second drift region 122. The channel material layer 140 is also formed to cover the entire surface of the mask layer 130 that is not covered by the first drift region 121.

[0102] The channel material layer 140 may include a semiconductor doped with a dopant of the second conductivity type. The channel material layer 140 may be formed by any of the various epitaxial growth methods described above. Mg may be used as the second conductivity type dopant.

[0103] 10, a source region layer 161 is formed on the channel material layer 140. The source region layer 161 may include a semiconductor doped with a first conductive type dopant at a high concentration. 19 / cm 3And that's all.

[0104] 11, the source region layer 161 and the channel material layer 140 are etched into a predetermined pattern to form a plurality of trenches having a predetermined depth, thereby forming the source region 160 and the channel region 141. The trench H1 is for forming a gate electrode, and is formed to a depth that penetrates the source region 160 and the channel region 141 and exposes the surface of the second drift region 122. The trench H2 is for forming a source electrode, and is formed to a depth that penetrates the source region 160 and exposes the surface of the channel region 141. The depth of the trench H2 is formed to a predetermined depth within the channel region 141, but is not limited thereto, and may be formed to a range in which the source electrode formed therein can directly contact the channel region 141.

[0105] 12, a gate insulating film 180 is formed on the inner surface of the trench H1. The gate insulating film 180 is for insulating the gate electrode from the channel region 141 and the source region 160. The gate insulating film 180 is made of a material such as silicon nitride (SiN), silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), aluminum oxynitride (AlON), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or various other dielectric materials having a high dielectric constant. The mask layer 130 can also be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

[0106] 13, an electrode material is applied inside the trenches H1 and H2 to form a source electrode S and a gate electrode G. The source electrode S and the gate electrode G may be formed of a metal, an alloy, a conductive metal oxide, or a conductive metal nitride.

[0107] Referring to FIG. 14, the substrate and the buffer layer are removed, and a drain electrode D is formed on the lower surface of the drain region 110.

[0108] Removal of the substrate and buffer layer may also be accomplished, for example, by a laser lift-off method.

[0109] By the above-described process, a transistor having a trench MOSFET structure as illustrated in FIG. 2 can be fabricated.

[0110] 15 to 20 are diagrams illustrating a method of manufacturing a transistor according to another embodiment.

[0111] The method for manufacturing a transistor according to this embodiment can also be used to manufacture, for example, the transistor shown in FIG.

[0112] The structure of Figure 15 can be obtained by adding an etching process to the structure manufactured by the steps of Figures 6 to 9. That is, in the structure of Figure 9, an upper portion of the channel material layer 140 can be etched to form a channel region 142.

[0113] Next, referring to FIG. 16, a second drift region 122 is additionally grown on the channel region 142 to cover the upper portion of the channel region 142 .

[0114] Referring to FIG. 17, a two-dimensional electron gas inducing layer 165 is formed on the second drift region 122 .

[0115] 18, a trench H is formed penetrating the two-dimensional electron gas inducing layer 165 and the second drift region 122. The trench H is for forming a source electrode, and the depth of the trench H extends to a predetermined depth inside the channel region 142 as shown in the figure. However, the depth is not limited thereto, and the trench H may be formed to various depths so that the source electrode formed in the trench H can directly contact the channel region 142.

[0116] 19, a source electrode S and a gate electrode G are formed on the two-dimensional electron gas inducing layer 165. The source electrode S is also formed to penetrate the two-dimensional electron gas inducing layer 165 and to directly contact the channel region 142.

[0117] 20, the substrate and the buffer layer are removed, and a drain electrode D is formed on the lower surface of the drain region 110, thereby completing the transistor having the structure illustrated in FIG.

[0118] FIG. 23 is a diagram showing a schematic configuration of an electronic device according to an embodiment. As shown, electronic device 2300 includes one or more electronic components, including a processor (eg, processing circuitry) 2320 and a memory 2330 , communicatively coupled to each other via a bus 2310 .

[0119] The processing circuitry 2320 may include one or more instances of a processing circuit, such as hardware including logic circuitry, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processing circuitry 2320 may include, but is not limited to, a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC) programmable logic unit, a microprocessor, or an application specific integrated circuit (ASIC), etc. The memory 2330 may include a non-transitory computer-readable storage device, such as a solid-state drive (SSD) that stores a program of instructions, and the instruction processing circuitry 2320 is also configured to execute the program of instructions and implement the functionality of the electronic device 2300.

[0120] In some exemplary embodiments, the electronic device 2300 may include one or more additional elements 2340 coupled to the bus 2310, such as a power source, a light sensor, a light emitting device, or any combination thereof. In some exemplary embodiments, one or more of the processing circuitry 2320, memory 2330, or one or more additional elements 2340 may include the semiconductor structure 100 of FIG. 1, or the transistors 101, 102, 103, 104, 106, and 107 described in FIGS. 2, 4-6, 21, and 22. Thus, an electronic device 2300 including such a processing circuitry 2320, memory 2330, or one or more additional elements 2340 may include a power element that can effectively lower the on-resistance while increasing the withstand voltage, and may have improved electrical characteristics and improved performance and / or reliability.

[0121] The above-mentioned semiconductor structure, the transistor using the same, and the manufacturing method of the transistor have been described with reference to the embodiments shown in the drawings, but they are merely illustrative, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. In the above description, many specific matters are described, but they should be interpreted as examples of specific embodiments rather than as limiting the scope of the invention. Therefore, the scope of the present invention should be determined not by the described embodiments, but by the technical ideas described in the claims. [Explanation of symbols]

[0122] 5,105 Buffer layer 10 High concentration layer 11 First semiconductor region 12 Third Semiconductor Region 13,130 Mask Layers 14 Second semiconductor region 101, 102, 103 Transistors 100 Semiconductor structure 110 Drain Region 120 Drift Region 121 First Drift Region 122 Second Drift Region 140 Channel Material Layer 141,142,144 Channel Area 160 Source Region 165 Two-dimensional electron gas induction layer 180 Gate insulating film 190,195 depletion region S source electrode D drain electrode G gate electrode SUB board

Claims

1. A substrate; one or more mask layers spaced apart from the substrate in a first direction; a first semiconductor region of a first conductivity type disposed between the substrate and the mask layer; a second semiconductor region of a second conductivity type disposed on the mask layer; a third semiconductor region of the first conductivity type that is disposed on the first semiconductor region and is formed in contact with the second semiconductor region such that a PN junction structure is formed along a second direction different from the first direction; the third semiconductor region is extended in the first direction from a surface of the first semiconductor region where the mask layer is not disposed, and has an extended shape to an upper region of the mask layer; A semiconductor structure, wherein the third semiconductor region has a thickness greater than a thickness of the first semiconductor region.

2. 2. The semiconductor structure of claim 1 wherein said second semiconductor region is formed in contact with said mask layer.

3. 3. The semiconductor structure of claim 1 or 2, wherein said mask layer comprises an insulating material that inhibits semiconductor growth.

4. 4. The semiconductor structure of claim 1, further comprising a high concentration layer disposed between said substrate and said first semiconductor region, said high concentration layer being more highly doped than said first semiconductor region.

5. the first semiconductor region, the second semiconductor region, and the third semiconductor region each include a III-V compound semiconductor; 5. The semiconductor structure of any one of claims 1 to 4, wherein group III comprises at least one element of boron (B), aluminum (Al), gallium (Ga) and indium (In), and group V comprises an element of nitrogen.

6. 6. The semiconductor structure of claim 1, wherein the first semiconductor region and the third semiconductor region are made of compound semiconductors having the same composition.

7. A drain electrode; one or more mask layers spaced apart from the drain electrode in a first direction; a first drift region of a first conductivity type disposed between the drain electrode and the mask layer; a channel region of a second conductivity type disposed on the mask layer; a second drift region disposed on the first drift region and formed in contact with the channel region such that a PN junction structure is formed along a second direction different from the first direction; a source electrode disposed on the channel region; a gate electrode disposed on the second drift region; the second drift region is extended in the first direction from a surface of the first drift region where the mask layer is not disposed, and has an extended shape to an upper region of the mask layer, The second drift region has a thickness greater than a thickness of the first drift region.

8. The transistor of claim 7 , wherein the channel region is formed in contact with the mask layer.

9. 9. The transistor according to claim 7, wherein the mask layer is made of an insulating material that inhibits semiconductor growth.

10. 10. The transistor of claim 7, further comprising: a drain region disposed between the drain electrode and the first drift region, the drain region being highly doped with a dopant of the first conductivity type.

11. The transistor of claim 10 , wherein the drain region is formed in direct contact with the first drift region.

12. the first drift region, the channel region, and the second drift region include a III-V compound semiconductor; 12. The transistor of claim 7, wherein group III includes at least one element of boron (B), aluminum (Al), gallium (Ga) and indium (In), and group V includes the element nitrogen.

13. The transistor of claim 7 , wherein the source electrode is formed in direct contact with the channel region.

14. 14. The transistor of claim 7, further comprising a source region disposed between the channel region and the source electrode, the source region being highly doped with a dopant of the first conductivity type.

15. The transistor according to claim 14 , wherein the source electrode has one end region penetrating the source region and directly contacting the channel region.

16. The transistor according to claim 15 , wherein the source electrode has one end region penetrating the source region and extending into the channel region.

17. the gate electrode is disposed adjacent to the channel region and the second drift region; The transistor according to claim 7 , further comprising a gate insulating film surrounding the gate electrode such that the gate electrode is insulated from the channel region and the second drift region.

18. 18. The transistor according to claim 7, further comprising a two-dimensional electron gas inducing layer disposed between the second drift region and the source electrode, the two-dimensional electron gas inducing layer being made of a semiconductor material having a different composition from a semiconductor material constituting the second drift region, and inducing a two-dimensional electron gas layer in the second drift region.

19. The transistor of claim 18 , wherein the source electrode has a shape such that one end region penetrates the two-dimensional electron gas inducing layer and directly contacts the channel region.

20. The transistor according to claim 19 , wherein the source electrode has one end region that penetrates the two-dimensional electron gas inducing layer and extends into the channel region.

21. forming a first drift region of a first conductivity type over a substrate; forming one or more mask layers over the first drift region; forming a second drift region by growing a semiconductor from a surface of the first drift region that is not covered by the mask layer and then growing a semiconductor on the mask layer; forming a channel region of a second conductivity type on the mask layer; forming a source electrode on the channel region; forming a gate electrode on the second drift region; forming a drain electrode below the first drift region; A method of manufacturing a transistor, comprising forming the second drift region to have a thickness greater than a thickness of the first drift region.

22. Prior to forming the first drift region on the substrate, 22. The method of claim 21, further comprising forming a drain region on the substrate, the drain region being heavily doped with a dopant of the first conductivity type.

23. 23. The method of claim 22, wherein forming the first drift region causes the drain region to be in direct contact with the first drift region.

24. The step of forming the channel region comprises:

24. A method according to claim 21, wherein the channel region covers the entire surface of the mask layer not covered by the second drift region.

25. The step of forming the source electrode comprises:

25. A method for manufacturing a transistor according to any one of claims 21 to 24, wherein the source electrode is in direct contact with the channel region.

Images