Wafer bump structure

JP7652738B2Active Publication Date: 2025-03-27SITRONIX TECH CORP
View PDF 5 Cites 0 Cited by

Patent Information

Application Number
JP2022063672
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2021-04-06
Filing Date
2022-04-06
Publication Date
2025-03-27
Estimated Expiration
2042-04-06

Smart Images

  • Figure 0007652738000001
    Figure 0007652738000001
  • Figure 0007652738000002
    Figure 0007652738000002
  • Figure 0007652738000003
    Figure 0007652738000003
Patent Text Reader

Abstract

To provide a bump structure in which conductive particles of a conductive medium can be effectively distributed on the surface of a connection bump.SOLUTION: A bump structure 1 includes a plurality of connection bump sets 10 that are mounted on one surface of a wafer 2 and having a first connection bump 12 and a second connection bump 14. The first connection bump and the second connection bump have mutually corresponding blocking structures. When the wafer is mounted on a plate member, the blocking structure of the first connection bump and the blocking structure of the second connection bump block a conductive medium, slow down the flow of the conductive medium, and flow the conductive medium between the first connection bump and the second connection bump, thereby avoiding the conductive particles of the conductive medium leaving the surfaces of the plurality of connection bumps. There is a channel between the plurality of connection bumps, and the width of at least one of the channels is 0.1 μm to 8 μm, and due to the limited space of the channel, it is avoided that the conductive particles located on the surface of the plurality of connection bumps leave the surface of the connection bumps too far into the channel.SELECTED DRAWING: Figure 4
Need to check novelty before this filing date? Find Prior Art

Description

[Technical field]

[0001] The present invention relates to a bump structure for a wafer, and more particularly to a bump structure that is arranged on the surface of a wafer and that can prevent conductive particles of a conductive medium from detaching from the surface of the bump when the wafer is placed on a plate-like member. [Background technology]

[0002] With the evolution of the times, electronic products are rapidly developing to be lighter, thinner and smaller. Most of the electronic products use displays as devices to display information. For example, in products such as video decks, notebook computers, smart mobile phones and other portable devices, displays have become an important device in electronic products.

[0003] A display panel can only display an image when combined with a driver wafer, and the driver wafer operates the driver panel to display an image. Generally speaking, there are several technologies for mounting the driver wafer on the panel. These technologies usually require the use of a conductive medium such as anisotropic conductive film (ACF), which contains conductive particles, and the conductive particles can contact the connection bumps of the driver wafer and the electrical connection members of the panel, so that the driver wafer can be electrically connected to the panel, and thus the driver wafer can transmit a driving signal to the panel, and the driver panel can display an image. Summary of the Invention [Problem to be solved by the invention]

[0004] In the known art, when the driver wafer is placed on a panel, the conductive medium flows randomly over the surface of the driver wafer, and the conductive particles of the conductive medium cannot be effectively distributed on the surface of the connection bumps of the driver wafer, which may adversely affect the ability of the driver wafer to transmit signals to the panel, causing the panel to not function properly. This problem is not limited to the driver wafer of the panel, but also exists in other types of wafers placed on a circuit board, such as microprocessor wafers, so the industry needs a bump structure that prevents the conductive particles from leaving the surface of the connection bumps. [Means for solving the problem]

[0005] In order to solve the above problems, one of the objects of the present invention is to provide a bump structure for a wafer. The bump structure includes a plurality of connection bumps disposed on the surface of a wafer, and has flow paths between the plurality of connection bumps, at least one of the flow paths having a width of 0.1 μm to 8 μm. When the wafer is disposed on a plate-like member, the space of the flow path is limited, so that the conductive particles located on the surface of the connection bumps can be prevented from being excessively separated from the surface of the connection bumps to the flow path, that is, a certain number of conductive particles can be located on the surface of these connection bumps.

[0006] In order to solve the above problems, one of the objectives of the present invention is to provide a wafer bump structure, which includes a plurality of connection bump sets disposed on the surface of a wafer, each connection bump set includes two connection bumps, and each of the two connection bumps has a blocking structure, which can block the conductive medium when the wafer is disposed on a plate-like member, slow down the flow of the conductive medium, prevent the conductive particles located on the surface of the connection bumps from leaving the surface of the connection bumps, and ensure that a certain number of conductive particles are located on the surface of the connection bumps.

[0007] In order to solve the above problems, the present invention provides a wafer bump structure, the bump structure is disposed on a surface of a wafer, and includes a plurality of connection bumps spaced apart from one another and having channels therebetween, at least one of the channels having a width of 0.1 μm to 8 μm.

[0008] In order to solve the above problems, the present invention provides another wafer bump structure, which includes a plurality of connection bump sets, each of which includes a first connection bump and a second connection bump, the first connection bump and the second connection bump are spaced apart from each other, the first connection bump has a first convex portion, the first convex portion is located on one side of the first connection bump, the second connection bump has a second concave portion, the second concave portion is located on one side of the second connection bump, and the first convex portion of the first connection bump corresponds to the second concave portion of the second connection bump. The first convex portion of the first connection bump and the second concave portion of the second connection bump act as a blocking structure to slow down the flow of the conductive medium.

[0009] In order to solve the above problems, the present invention provides another wafer bump structure, which includes a plurality of connecting bump sets, each connecting bump set includes a first connecting bump and a second connecting bump, the first connecting bump and the second connecting bump are spaced apart from each other, the first connecting bump has a first convex portion, the first convex portion is located on one side of the first connecting bump, the second connecting bump has a second convex portion, the second convex portion is located on one side of the second connecting bump, and the first convex portion of the first connecting bump corresponds to the second convex portion of the second connecting bump. The first convex portion of the first connecting bump and the second convex portion of the second connecting bump act as a blocking structure to slow down the flow of the conductive medium. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective view of a first embodiment of the present invention. [Diagram 2] FIG. 1 is a schematic top view of a first embodiment of the present invention. [Diagram 3] FIG. 1 is a schematic cross-sectional view of a first embodiment of the present invention. [Figure 4] FIG. 1 is a schematic perspective view of a second embodiment of the present invention. [Diagram 5] FIG. 1 is a top view of a second embodiment of the present invention. [Figure 6] FIG. 2 is a schematic cross-sectional view of a second embodiment of the present invention. [Figure 7] FIG. 11 is a perspective view of a third embodiment of the present invention. [Figure 8]FIG. 11 is a top view of a third embodiment of the present invention. [Figure 9] FIG. 11 is a schematic cross-sectional view of a third embodiment of the present invention. [Figure 10] FIG. 11 is a perspective view of a fourth embodiment of the present invention. [Figure 11] FIG. 11 is a top view of a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In order to allow you to further understand and appreciate the characteristics and achievable effects of the present invention, the following examples will be given.

[0012] Referring to Fig. 1, Fig. 1 is a perspective view of a first embodiment of the present invention. As shown, a bump structure 1 of the present invention is disposed on one surface 3 of a wafer 2, and the bump structure 1 includes a plurality of connection bumps 11, and the connection bumps 11 are metal bodies.

[0013] 1, 2, and 3 again, Fig. 2 is a schematic top view of the first embodiment of the present invention, and Fig. 3 is a cross-sectional view taken along the line AA in Fig. 2. As shown in the figures, a plurality of connection bumps 11 are spaced apart from one another, and have flow paths 16 between each of the plurality of connection bumps 11, and at least one of the widths W of the flow paths 16 is 0.1 μm (microns) to 8 μm (microns), and preferably 0.1 μm to 6 μm. A conductive medium 30 can flow within the flow paths 16, and the conductive medium 30 includes a plurality of conductive particles 32.

[0014] In this embodiment, the width W is the width of the inlet and / or outlet of the flow path 16, and is also the interval between the multiple connection bumps 11. The width W of the flow path 16 of the multiple connection bumps 11, i.e., the space of the flow path 16 is limited, which corresponds to the limit of the number of conductive particles 30 that can be accommodated in the flow path 16. When the conductive medium 30 is added to the surface 3 of the wafer 2 and the wafer 2 is placed on the plate-like member 20, the wafer 2 is subjected to a force, and the conductive medium 30 flows on the surface 3 of the wafer 2. Since the space of the flow path 16 is limited, the conductive particles 32 located on the surface of the connection bumps 11 can be prevented from being excessively separated from the surface of the connection bumps 11 to the flow path 16, that is, a certain number of conductive particles 32 can be located on the surface of these connection bumps 11. The plate-like member 20 may be a display panel or a circuit board, etc.

[0015] In this embodiment, the flow path 16 may be a straight line or a non-straight line, for example, a diagonal line or a circular arc, and is not limited to this in this embodiment.

[0016] 1, 2 and 3 again, in this embodiment, each of the plurality of connection bumps 11 corresponds to one of the plurality of conductive members 22, and the plurality of conductive members 22 are disposed on the plate-shaped member 20. When the conductive medium 30 is disposed between the wafer 2 and the plate-shaped member 20 and the wafer 2 is disposed on the plate-shaped member 20, the wafer 2 receives a force and the conductive medium 30 flows on the surface 3 of the wafer 2, and since the space of the flow path 16 is limited, only a small amount of the conductive medium 30 and the conductive particles 32 can be accommodated in the flow path 16. This can reduce the number of conductive particles 32 located on the surface of the connection bump 11 that escape from the surface of the connection bump 11 to the flow path 16. That is, a certain number of conductive particles 32 can be positioned on the surface of the connection bump 11, and the connection bump 11 can be reliably electrically connected to the conductive member 22 of the plate-shaped member 20 by the conductive particles 32, and the transmission capacity between the wafer 2 and the plate-shaped member 20 can be ensured. In this embodiment, the conductive medium 30 may be an anisotropic conductive film (ACF), but is not limited to this in this embodiment.

[0017] 1 and 2 again, the connection bumps 11 can be arranged in a plurality of rows, and the rear connection bumps 11 of the rows are staggered with the front connection bumps 11 of the rows, i.e., the flow paths 16 of the rear connection bumps 11 of the rows face the bottoms of the front connection bumps 11 of the rows. The arrows in FIG. 2 indicate the flow of the conductive medium 30, and when the conductive medium 30 flows out of the flow paths 16 located at the rear of the rows, the conductive medium 30 is blocked by the plurality of connection bumps 11 located at the front of the rows and redirected, so that the flow of the conductive medium 30 can be delayed and the number of conductive particles 32 located on the surface of the connection bumps 11 that leave the surface of the connection bumps 11 can be reduced.

[0018] 4, which is a perspective schematic diagram of a second embodiment of the present invention. As shown in the figure, the bump structure 1 of the present invention includes a plurality of connection bump sets 10, which are spaced apart from each other and provided on the front surface 3 of the wafer 2.

[0019] 4, 5, and 6 again, FIG. 5 is a top view of the second embodiment of the present invention. FIG. 6 is a cross-sectional view in the AA direction of FIG. 5. In this embodiment, each connection bump set 10 includes a first connection bump 12 and a second connection bump 14. The first connection bump 12 and the second connection bump 14 are spaced apart from each other to form a flow path 16. The first connection bump 12 has a first convex portion 122, the first convex portion 122 is located on one side of the first connection bump 12, the second connection bump 14 has a second concave portion 142, the second concave portion 142 is located on one side of the second connection bump 14, and the first convex portion 122 corresponds to the second concave portion 142, i.e., the first convex portion 122 faces the second concave portion 142, and the two have complementary shapes, forming a non-linear flow path 16 between the first connection bump 12 and the second connection bump 14.

[0020] In this embodiment, the first connecting bump 12 and the second connecting bump 14 are respectively disposed corresponding to the conductive member 22 of the plate-like member 20. There is a flow path 16 between the first connecting bump 12 and the second connecting bump 14, and the flow path 16 passes through the first convex portion 122 of the first connecting bump 12 and the second concave portion 142 of the second connecting bump 14, and the first convex portion 122 and the second concave portion 142 are blocking structures that can block the conductive medium 30, thereby slowing down the flow of the conductive medium 30 and preventing the conductive particles 32 located on the surfaces of the connecting bumps 12, 14 from leaving the surfaces of the connecting bumps 12, 14, so as to maintain a certain amount of conductive particles 32 located on the surfaces of the connecting bumps 12, 14.

[0021] When an attempt is made to place the conductive medium 30 between the wafer 2 and the plate-like member 20 and place the wafer 2 on the plate-like member 20, the wafer 2 receives a force, causing the conductive medium 30 to flow on the surface 3 of the wafer 2. The conductive medium 30 is blocked by the first convex portion 122 of the first connection bump 12 and the second concave portion 142 of the second connection bump 14, slowing down the flow, and as shown in Figure 5, the arrow indicates the flow direction of the conductive medium 30.

[0022] As in the first embodiment, the width W of the flow path 16 between the first connecting bump 12 and the second connecting bump 14 is 0.1 μm to 8 μm, preferably 0.1 μm to 6 μm, which limits the space between the flow paths 16 and can reduce the number of conductive particles 32 located on the surfaces of the multiple connecting bumps 12, 14 that flow from the surfaces of the multiple connecting bumps 12, 14 to the flow path 16, i.e., can maintain a constant number of conductive particles 32 on the surfaces of the multiple connecting bumps 12, 14. The width W is the width of the inlet and / or outlet of the flow path 16.

[0023] 4, 5 and 6 again, the first connecting bump 12 further has a first recess 124, which is located on a side surface of the first connecting bump 12, and the second connecting bump 14 further has a second protrusion 144, which is located on a side surface of the second connecting bump 14. The first recess 124 corresponds to the second protrusion 144, i.e., the first recess 124 is opposite to and complementary to the second protrusion 144, and the first recess 124 and the second protrusion 144 are also blocking structures, so that the flow path 16 further passes through the first recess 124 and the second protrusion 144, thereby increasing the detour of the flow path 16 and further slowing down the flow of the conductive medium 30. In addition, multiple connection bump sets 10 can be arranged in multiple rows, with multiple connection bump sets 10 located in the rear row intersecting with multiple connection bump sets 10 located in the front row, i.e., the flow paths 16 of multiple connection bump sets 10 located in the rear row face the bottoms of the first connection bumps 12 or second connection bumps 14 of the multiple connection bump sets 10 located in the front row, thereby slowing down the flow of the conductive medium 30.

[0024] In the second embodiment, the first convex portion 122 and the first concave portion 124 are the convex portion and the concave portion of the first connecting bump 12, so the first connecting bump 12 may have a plurality of the first convex portions 122 and a plurality of the first concave portions 124. Similarly, the second convex portion 144 and the second concave portion 142 are the convex portion and the concave portion of the second connecting bump 14, so the second connecting bump 14 may have a plurality of the second convex portions 144 and a plurality of the second concave portions 142.

[0025] 7, 8 and 9, FIG. 7 is a perspective view of the third embodiment of the present invention. FIG. 8 is a top view of the third embodiment of the present invention. FIG. 9 is a cross-sectional view along the AA direction of FIG. 8. As shown in the figures, the difference between the third embodiment and the second embodiment is as follows: the first protrusion 122 of the first connection bump 12 extends into the second recess 142 of the second connection bump 14, i.e., the first protrusion 122 is located in the second recess 142, but they do not contact each other. The flow path 16 between the first connection bump 12 and the second connection bump 14 can be further bypassed, and the conductive medium 30 can be further blocked, and the conductive medium 30 can be caused to change its flow direction, so that the flow of the conductive medium 30 can be further slowed down.

[0026] In this embodiment, the second convex portion 144 of the second connecting bump 14 extends into the first concave portion 124 of the first connecting bump 12, i.e. the second convex portion 144 is located in the first concave portion 124, but they do not contact each other. As can be seen from the above description, the shapes of the first connecting bump 12 and the second connecting bump 14 are complementary to each other. 8, the first convex portion 122 is located in the second concave portion 142, and the second convex portion 144 is located in the first concave portion 124, so that the flow path 16 thus formed has multiple bends, which causes the conductive medium 30 flowing in the flow path 16 to change its flow direction multiple times, slowing down the flow of the conductive medium 30, i.e., preventing the conductive particles 32 located on the surfaces of the plurality of connection bumps 12, 14 from leaving the surfaces of the plurality of connection bumps 12, 14, and guiding the conductive medium 30 to flow around the plurality of connection bumps 12, 14, so that the conductive particles 32 are concentrated on the surfaces of the plurality of connection bumps 12, 14. The other structures and operating relationships of this embodiment are the same as those of embodiment 2, and therefore will not be described here.

[0027] 10, which is a perspective view of a fourth embodiment of the present invention. As shown in the figure, the bump structure 1 includes a plurality of connection bump sets 10, which are spaced apart from each other and disposed on the surface 3 of the wafer 2.

[0028] 10 and 11 again, FIG. 11 is a top view of embodiment 4 of the present invention. As shown, each connecting bump set 10 includes a first connecting bump 12 and a second connecting bump 14, the first connecting bump 12 and the second connecting bump 14 are spaced apart from each other, the first connecting bump 12 has a first convex portion 122, the first convex portion 122 is located on one side of the first connecting bump 12, the second connecting bump 14 has a second convex portion 144, the second convex portion 144 is located on one side of the second connecting bump 14, and the first convex portion 122 corresponds to the second convex portion 144, forming a non-linear flow path 16 between the first connecting bump 12 and the second connecting bump 14. The flow path 16 flows through the first convex portion 122 of the first connecting bump 12 and the second convex portion 144 of the second connecting bump 14.

[0029] In this embodiment, the first connecting bump 12 further has a first recess 124, which is located on the side of the first connecting bump 12, and the second connecting bump 14 further has a second recess 142, which is located on the side of the second connecting bump 14, and the first recess 124 corresponds to the second recess 142. The flow path 16 flows through the first recess 124 of the first connecting bump 12 and the second recess 142 of the second connecting bump 14. The first convex portion 122, the first recess 124, the second convex portion 144, and the second recess 142 are blocking structures that block the conductive medium 30 and slow down the flow of the conductive medium 30. The first convex portion 122 faces the second convex portion 144 to reduce the width of the flow path 16 located between the first convex portion 122 and the second convex portion 144. Also, the first recess 124 faces the second recess 142, and thus the width of the flow passage 16 located between the first recess 124 and the second recess 142 is increased. The width of the flow passage 16 in this embodiment can be changed, and thus the flow rate of the conductive medium 30 can be changed, and the first protrusion 122, the first recess 124, the second protrusion 144, and the second recess 142 are added to block the conductive medium 30, thereby slowing down the flow of the conductive medium 30.

[0030] In this embodiment, at least one width W of the flow passage 16 formed between the first connection bump 12 and the second connection bump 14 is 0.1 μm to 8 μm, preferably 0.1 μm to 6 μm, and the width W is the width of the inlet and / or outlet of the flow passage 16. Other structures and operational relationships of this embodiment are the same as those of embodiment 2, so the description will be omitted.

[0031] Therefore, since the present invention is indeed novel, inventive and industrially applicable, there is no doubt that it meets the patent application requirements of Taiwan’s Patent Law. We have filed an application for an invention patent in accordance with the law, and sincerely hope that your Office will grant us the patent at an early date.

[0032] However, the above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. All equivalent changes and modifications based on the shape, structure, characteristics and spirit described in the scope of the patent application of the present invention are included in the scope of the patent application of the present invention. [Explanation of symbols]

[0033] 1. Bump structure 2 Wafer 3 surface 10 Connection bump set 11 Connection Bump 12 1st connection bump 122 First protrusion 124 First recess 14 2nd Connection Bump 142 Second recess 144 Second convex part 16 Flow Path 20 Plate-shaped member 22 Conductive materials 30 Conductive Media 32 Conductive particles W width

Claims

1. A wafer bump structure disposed on one surface of the wafer, the bump structure including: a plurality of connection bump sets, each set including a first connection bump and a second connection bump, the first connection bump and the second connection bump being spaced apart from each other, the first connection bump having a plurality of first convex portions, the first convex portions being located on one side surface of the first connection bump, the second connection bump having a plurality of second concave portions, the second concave portions being located on one side surface of the second connection bump, the plurality of first convex portions of the first connection bump corresponding to the plurality of second concave portions of the second connection bump; A wafer bump structure, characterized in that the multiple first convex portions and the multiple second concave portions function as a blocking structure to block the flow of a conductive medium, the conductive medium including multiple conductive particles, and the conductive medium and the conductive particles are positioned on the surfaces of the first connection bump and the second connection bump.

2. the first connection bump has a plurality of first recesses, the first recesses being disposed between two first protrusions and located on the side surfaces of the first connection bump; the second connection bump has a plurality of second protrusions, the second protrusions being located on the side surfaces of the second connection bump, the second recesses being disposed between two second protrusions, the plurality of first recesses corresponding to the plurality of second protrusions, the plurality of first protrusions extending to the second recesses, and the second protrusions extending to the first recesses; 2. The wafer bump structure according to claim 1.

3. a flow path is formed between the first connection bump and the second connection bump, the flow path passing through the first protruding portions of the first connection bump, the second protruding portions of the second connection bump, the first protruding portions of the first connection bump, and the second protruding portions of the second connection bump; 3. The wafer bump structure according to claim 2.

4. a flow path is formed between the first connection bump and the second connection bump, the flow path passing through the first convex portions of the first connection bump and the second concave portions of the second connection bump; 2. The wafer bump structure according to claim 1.

5. The width of the flow channel is 0.1 μm to 8 μm.

5. The wafer bump structure according to claim 4.

6. The width is the width of one of the inlets and / or outlets of the flow path.

6. The wafer bump structure according to claim 5.

7. The flow path is a non-linear flow path.

5. The wafer bump structure according to claim 4.

8. A wafer bump structure disposed on one surface of the wafer, the bump structure including: a plurality of connection bump sets, each set including a first connection bump and a second connection bump, the first connection bump and the second connection bump being spaced apart from each other, the first connection bump having a plurality of first convex portions and one first concave portion, the plurality of first convex portions and the first concave portion being located on one side of the first connection bump, the first concave portion being disposed between two first convex portions, the second connection bump having a plurality of second convex portions and one second concave portion, the plurality of second convex portions and the second concave portion being located on one side of the second connection bump, the second concave portion being disposed between two second convex portions, the plurality of first convex portions of the first connection bump corresponding to the plurality of second convex portions of the second connection bump, and the first concave portion corresponding to the second concave portion; the plurality of first convex portions and the plurality of second convex portions function as a blocking structure for blocking a flow of a conductive medium, the conductive medium including a plurality of conductive particles, the conductive medium and the conductive particles being located on the surfaces of the first connection bump and the second connection bump; a flow path is formed between the first connection bump and the second connection bump, the flow path passing through one of the multiple first convex portions of the first connection bump, one of the multiple second convex portions of the second connection bump, the first concave portion of the first connection bump, the second concave portion of the second connection bump, another of the multiple first convex portions, and another of the multiple second convex portions, wherein a width of the flow path between one of the multiple first convex portions and one of the multiple second convex portions is reduced, a width of the flow path between the first concave portion and the second concave portion is increased, and a width of the flow path between the other of the multiple first convex portions and the other of the multiple second convex portions is reduced.

9. The width of the flow channel is 0.1 μm to 8 μm.

9. The wafer bump structure according to claim 8.

10. The width is the width of one of the inlets and / or outlets of the flow path.

10. The wafer bump structure according to claim 9.

11. The flow path is a non-linear flow path.

9. The wafer bump structure according to claim 8.

Citation Information

Patent Citations

  • Semiconductor device

    JP2006041413A

  • Semiconductor device

    JP2007194305A

  • Semiconductor device and its manufacturing method

    JP2008098402A

  • Semiconductor device and display apparatus with semiconductor device

    JP2008135468A

  • Semiconductor element and electronic apparatus including the semiconductor element

    JP2011233624A