Hybrid wafer dicing technique using spatially multiple focused laser beam laser scribing and plasma etching processes

Abstract

A method for dicing a semiconductor wafer having a plurality of integrated circuits each thereon is described. In an example, the method for dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask over the semiconductor wafer, the mask comprising a layer that covers and protects the integrated circuits. The mask is then patterned in a laser scribing process with multiple spatially focused laser beams to provide gaps in the patterned mask and expose areas of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Non-Provisional Patent Application No. 16 / 533,590, filed August 6, 2019, the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of semiconductor processing, and in particular to a method for dicing a semiconductor wafer having multiple integrated circuits each having the wafer. [Background technology]

[0003] During semiconductor wafer processing, integrated circuits are formed on wafers (also called substrates) made of silicon or other semiconductor materials. Generally, layers of various materials that are either semiconductors, conductors, or insulators are utilized to form the integrated circuits. These materials are doped, deposited, and etched using a variety of well-known processes to form the integrated circuits. Each wafer is processed to form many individual regions that contain the integrated circuits, known as dice.

[0004] Following processing to form integrated circuits, the wafer is "diced" to separate the individual dies from one another for packaging or for use in a larger circuit in unpackaged form. The two main techniques used for wafer dicing are scribing and sawing. In scribing, a diamond-tipped scribe is moved across the wafer surface along pre-formed scribe lines. These scribe lines extend along the spaces between the dies. These spaces are commonly referred to as "streets." The diamond scribe creates shallow scratches along the streets in the wafer surface. Upon application of pressure, such as with a roller, the wafer separates along the scribe lines. The cracks in the wafer follow the crystal lattice structure of the wafer substrate. Scribing can be used for wafers that are about 10 mils (10 thousandths of an inch) thick or less. For thicker wafers, sawing is currently the preferred method for dicing.

[0005] In sawing, a diamond-tipped saw rotating at high revolutions per minute contacts the wafer surface and saws the wafer along the streets. The wafer is mounted on a support, such as an adhesive film stretched across a film frame, and the saw is applied repeatedly to both the vertical and horizontal streets. One problem with either scribing or sawing is that chips and dents can form along the cut edge of the die. Also, cracks can form and propagate from the edge of the die into the substrate, rendering the integrated circuit inoperable. Chip formation and crack formation can occur specifically when only one side of a square or rectangular die has a crystalline structure. <110> This is a problem with scribing because the die can be scribed in the same direction. As a result, cleaving the other side of the die results in a jagged separation line. Due to chipping and cracking, additional spacing is required between the dies on the wafer to prevent damage to the integrated circuits, e.g., chips and cracks are kept at a distance from the actual integrated circuits. As a result of the spacing requirements, not many dies can be formed on a standard sized wafer, and wafer real estate that could otherwise be used for circuits is wasted. The use of saws increases real estate waste in semiconductor wafers. The saw blade is approximately 15 microns thick. Therefore, the circuits of each die must often be separated by 300 to 500 microns to ensure that cracks and other damage around the cuts made by the saw do not damage the integrated circuits. Additionally, after sawing, each die requires substantial cleaning to remove particles and other contaminants resulting from the sawing process.

[0006] Plasma dicing has also been used, but may have limitations as well. For example, one limitation that may prevent plasma dicing from being implemented may be cost. Standard lithography operations to pattern resists may make implementation cost prohibitive. Another limitation that may prevent plasma dicing from being implemented is that plasma processing of metals (e.g., copper), commonly encountered in dicing along the streets, may cause productivity issues or throughput limitations. Summary of the Invention

[0007] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure include methods of dicing semiconductor wafers and apparatus for dicing semiconductor wafers.

[0008] In an embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask over the semiconductor wafer, the mask being comprised of a layer that covers and protects the integrated circuits. The mask is then patterned in a laser scribing process with multiple spatially focused laser beams to provide gaps in the patterned mask and expose areas of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

[0009] In another embodiment, a method of dicing a semiconductor wafer containing a plurality of integrated circuits involves laser scribing the semiconductor wafer with a laser scribing process of multiple spatially focused laser beams to singulate the plurality of integrated circuits.

[0010] In another embodiment, a system for dicing a semiconductor wafer having a plurality of integrated circuits includes a factory interface. The system also includes a laser scribing apparatus coupled to the factory interface and having a laser assembly configured to provide multiple spatially focused laser beams. The system also includes a plasma etch chamber coupled to the factory interface. [Brief description of the drawings]

[0011] [Figure 1] 1 is a flow chart illustrating operations in a method for dicing a semiconductor wafer comprising a plurality of integrated circuits according to an embodiment of the present disclosure. [Figure 2A] 1A-1C are cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performance of a method of dicing the semiconductor wafer, corresponding to operation 102 of the flowchart of FIG. 1, in accordance with an embodiment of the present disclosure. [Figure 2B] 2 is a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performance of a method of dicing the semiconductor wafer, corresponding to operation 104 of the flowchart of FIG. 1, in accordance with an embodiment of the present disclosure. [Figure 2C] 1A-1C are cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performance of a method of dicing the semiconductor wafer, corresponding to operation 108 of the flowchart of FIG. 1, in accordance with an embodiment of the present disclosure. [Diagram 3] 1A-1C are cross-sectional views of a laser scribing process using multiple focused laser beams according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a cross-sectional view of a laser scribed trench in a substrate, where the laser scribed trench is formed with a single focused laser beam. [Diagram 5] 1A-1C are cross-sectional views of laser scribed trenches in a substrate, where the laser scribed trenches are formed with multiple focused laser beams, according to an embodiment of the present disclosure. [Figure 6] FIG. 1 illustrates the effect of using laser pulse widths in the femtosecond range, picosecond range, and nanosecond range, in accordance with an embodiment of the present disclosure. [Figure 7] 1 is a cross-sectional view of a stack of materials that may be used in the street region of a semiconductor wafer or substrate according to an embodiment of the present disclosure. [Figure 8A-8D] 1A-1D are cross-sectional views of various operations in a method of dicing a semiconductor wafer according to an embodiment of the present disclosure. [Figure 9]FIG. 2 is a block diagram of a tool layout for laser and plasma dicing of a wafer or substrate according to an embodiment of the present disclosure. [Figure 10] FIG. 1 is a block diagram of an example computer system according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] A method for dicing a semiconductor wafer, each having a plurality of integrated circuits, is described. In the following description, several specific details are described, such as spatially multiple focused laser beams, laser scribing techniques, and plasma etching conditions and materials, to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to one of ordinary skill in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known aspects, such as the fabrication of integrated circuits, have not been described in detail in order to not unnecessarily obscure the embodiments of the present disclosure. Furthermore, it is understood that the various embodiments shown in the figures are illustrative depictions and are not necessarily drawn to scale.

[0013] A hybrid wafer or substrate dicing process with an initial laser scribe and a subsequent plasma etch can be performed for die singulation. A laser scribe process can be used to cleanly remove mask layers, organic and inorganic dielectric layers, and device layers. A laser etch process can then be terminated at the exposure or partial etch of the wafer or substrate. A plasma etch portion of the dicing process can then be employed to etch through the bulk of the wafer or substrate, such as through bulk single crystal silicon, to produce die or chip singulation or dicing. More specifically, one or more embodiments are directed to performing a laser scribing process of spatially multiple focused laser beams, for example for dicing applications.

[0014] A spatially multi-focused laser beam for wafer dicing using a hybrid laser scribing and plasma etch approach is described. By way of background, laser scribing processes may require precise focus depth control. Currently, most scribing applications have only one focus depth setting. Non-uniform trench formation may result from scribing processes based on such processes. The embodiments described herein are directed to multi-focus processing in a single scribing pass. Controlled groove / trench shapes may be achieved from such scribing processes.

[0015] To provide further background, a hybrid technique combining laser scribing and plasma etching can enable the cutting of thin semiconductor device dies from silicon (Si) wafers. The use of an ultrashort pulsed laser can be an essential component in achieving fine scribing of the die streets for subsequent singulation of the wafer in a plasma etching process. The spatial geometry of the laser scribe can dictate the cleanliness and smoothness of the singulated device dies.

[0016] A single laser beam scribing process is typically associated with the formation of a conical opening in the surface of a Si substrate. Such a conical trench can undesirably provide a non-uniform trench that may not be well suited for a subsequent plasma etching process. For example, for high quality die singulation, a uniform and deep initial scribed trench may be beneficial or even essential. The embodiments described herein involve the use of multiple focused laser scribing processes used to generate deep uniform cylindrical trench openings.

[0017] The implementation of the embodiments described herein can provide a suitable scribed trench that can enable etch rate and shape uniformity during the initial opening by laser scribing or the plasma dicing process followed by scribing. Advantages of implementing one or more of the embodiments described herein can include one or more of: (1) achieving precisely controlled and refined trench shape; (2) using a diffractive optical element (DOE) to manage the cleanliness and smoothness of the opened trench for the subsequent etching process; (3) a soft scribing configuration, such as a combination of DOE and optics, can be positioned to provide a suitable beam path to control the scribing process; (4) achieving high product quality by improving the scribed trench shape; and / or (5) adjustability of the scribed trench to match the kerf width and depth depending on the requirements of the subsequent etching process.

[0018] According to one or more embodiments of the present disclosure, multiple focused laser beams are created by a combination of optical elements and differential optical elements with additional optics such as one or more lenses. The number of multiple focused laser beams and the beam separation can be controlled by the order of the diffractive optics. Also, the beam delivery optics can be used to reconfigure the laser scribing system to provide a proper beam path within the system. By controlling the overlap of multiple laser beam spots, scanning speed, laser beam wavelength, etc., a proper scribed trench quality can be produced in the scribed substrate.

[0019] In embodiments, precisely controlled laser scribe shapes enable high quality singulated device dies and cost-effective etching processes. In contrast, previous implementations have involved the use of lasers in wafer singulation where the beam is focused only to a single point instead of at multiple planes. Such configurations lack the flexibility to be finely tuned and are fairly difficult to change settings, which can result in increased costs required for subsequent etching processes.

[0020] Also, in a hybrid wafer or substrate dicing process involving initial laser scribing of a surface-covered wafer and subsequent plasma etch, a femtosecond laser can be applied to remove the mask and device layers in the dicing streets until the silicon substrate is exposed. A plasma etch follows to separate the dies to achieve die singulation. Typically, a single-focused beam is used for the femtosecond laser scribing process. However, a single-focused beam may limit the process flexibility and / or control of the trench shape.

[0021] According to one or more embodiments of the present disclosure, the scribing laser beam is multi-focused to improve the laser scribing process in hybrid laser dicing. Thereby, in an aspect of the present disclosure, a combination of a laser scribing process of a spatially multi-focused laser beam with a plasma etching process can be used to dice a semiconductor wafer into singulated integrated circuits. FIG. 1 is a flow chart 100 illustrating operations in a method of dicing a semiconductor wafer with multiple integrated circuits according to an embodiment of the present disclosure. FIG. 2A-2C show cross-sectional views of a semiconductor wafer including multiple integrated circuits during the performance of a method of dicing a semiconductor wafer corresponding to the operations of flow chart 100 according to an embodiment of the present disclosure.

[0022] 2A, a mask 202 is formed over a semiconductor wafer or substrate 204. The mask 202 is comprised of a layer that covers and protects the integrated circuits 206 formed on the surface of the semiconductor wafer 204. The mask 202 also covers the interstitial streets 207 formed between each of the integrated circuits 206.

[0023] According to an embodiment of the present disclosure, forming the mask 202 includes forming a layer such as, but not limited to, a photoresist layer or an I-line patterning layer. For example, a polymer layer such as a photoresist layer may be comprised of a material suitable for use in lithography processes. In one embodiment, the photoresist layer is comprised of a positive photoresist material such as, but not limited to, a 248 nanometer (nm) resist, a 193 nm resist, a 157 nm resist, an extreme ultraviolet (EUV) resist, or a phenolic resin-based matrix with a diazonaphthoquinone sensitizer. In another embodiment, the photoresist layer is comprised of a negative photoresist material such as, but not limited to, polycis-isoprene and polyvinyl cinnamate.

[0024] In other embodiments, forming the mask 202 involves forming a layer that is deposited in a plasma deposition process. For example, in one such embodiment, the mask 202 comprises a Teflon or Teflon-like (polymeric CF2) layer. In a particular embodiment, the polymeric CF2 layer is deposited in a plasma deposition process involving the gas C4F8.

[0025] In other embodiments, forming the mask 202 involves forming a water-soluble mask layer. In embodiments, the water-soluble mask layer is readily dissolvable in an aqueous medium. For example, in one embodiment, the water-soluble mask layer is comprised of a material that is soluble in one or more of an alkaline solution, an acidic solution, or deionized water. In an embodiment, the water-soluble mask layer maintains its water solubility upon exposure to a heat treatment, such as heating in the range of approximately 50-160° C. For example, in one embodiment, the water-soluble mask layer is dissolvable in an aqueous solution following exposure to chamber conditions used in a laser or plasma etching singulation process. In one embodiment, the water-soluble mask layer is comprised of a material such as, but not limited to, polyvinyl alcohol, polyacrylic acid, dextran, polymethacrylic acid, polyethyleneimine, or polyethylene oxide. In a particular embodiment, the water-soluble mask layer has an etch rate in an aqueous solution in the range of approximately 1-15 microns per minute, more specifically, approximately 1.3 microns per minute.

[0026] In other embodiments, forming the mask 202 involves forming a UV-curable mask layer. In an embodiment, the mask layer has a sensitivity to UV light that reduces the adhesiveness of the UV-curable layer by at least approximately 80%. In some such embodiments, the UV layer is comprised of a polyvinyl chloride or acrylic-based material. In an embodiment, the UV-curable layer is comprised of a material, or a stack of such materials, with adhesive properties that weaken upon exposure to UV light. In an embodiment, the UV-curable adhesive film is sensitive to approximately 365 nm UV light. In some such embodiments, this sensitivity allows for the use of LED light to effect the cure.

[0027] In an embodiment, the semiconductor wafer or substrate 204 is made of a material suitable for withstanding fabrication processes and on which semiconductor processing layers may be appropriately disposed. For example, in one embodiment, the semiconductor wafer or substrate 204 is made of a Group IV based material, such as, but not limited to, crystalline silicon, germanium, or silicon / germanium. In a particular embodiment, providing the semiconductor wafer 204 includes providing a monocrystalline silicon substrate. In a specific embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, the semiconductor wafer or substrate 204 is made of a III-V material, such as, for example, a III-V material substrate used in the fabrication of light emitting diodes (LEDs).

[0028] In an embodiment, the semiconductor wafer or substrate 204 has an array of semiconductor devices disposed thereon as part of an integrated circuit 206. Examples of semiconductor devices include, but are not limited to, memory devices or complementary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate and encapsulated in a dielectric layer. A number of metal interconnects can be formed above the devices or transistors and in the surrounding dielectric layer and used to electrically couple the devices or transistors to form the integrated circuit 206. The materials making up the streets 207 can be similar or the same as the materials used to form the integrated circuit 206. For example, the streets 207 can be comprised of layers of dielectric materials, semiconductor materials, and metallization. In one embodiment, one or more of the streets 207 include test devices similar to the actual devices of the integrated circuit 206.

[0029] 2B, the mask 202 is patterned with a laser scribing process of spatially multiple focused laser beams to provide gaps 210 in the patterned mask 208 and expose areas of the semiconductor wafer or substrate 204 between the integrated circuits 206. The laser scribing process is thereby used to remove material of the streets 207 originally formed between the integrated circuits 206. According to an embodiment of the present disclosure, patterning the mask 202 with a laser scribing process of spatially multiple focused laser beams includes forming trenches 212 in the areas of the semiconductor wafer 204 between the integrated circuits 206, as depicted in FIG.

[0030] Diffractive optical element (DOE) optics can be used to generate uniform deep trenches through multiple focusing. As an example, Figure 3 shows a cross-sectional view of a laser scribing process using multiple focused laser beams according to an embodiment of the present disclosure.

[0031] 3, a diffractive optical element 304 is positioned above a substrate 302. The diffractive optical element 304 provides a beam 306 having a first portion 308A with a first focal depth A into the substrate 302. The diffractive optical element 304 simultaneously provides a beam 306 having a second portion 308B with a second focal depth B into the substrate 302. Depth B is vertically below depth A. In a specific embodiment, the diffractive optical element 304 simultaneously provides a beam 306 having a third portion 308C with a third focal depth C into the substrate 302. Depth C is vertically below depth B. It is understood that additional focal depths corresponding to still further beam portions may be provided.

[0032] 3, in an embodiment, the spatially multiple focused laser beam laser scribing process provides a first beam portion 308A focused to a first depth A in the semiconductor wafer 302 and a second beam portion 308 focused to a second depth B in the semiconductor wafer 302, the second depth B being vertically below the first depth A. In one such embodiment, the spatially multiple focused laser beam laser scribing process further provides a third beam portion 308C focused to a third depth C in the semiconductor wafer 302, the third depth C being vertically below the second depth B.

[0033] In an embodiment, the spatially multi-focused laser beam laser scribing process includes passing the laser beam through a diffractive optical element (DOE), such as diffractive optical element 304. In an embodiment, the spatially multi-focused laser beam laser scribing process involves using a Gaussian source laser beam. In such an embodiment, scribing with a spatially multi-focused laser beam laser scribing process involves scribing with a spatially multi-focused femtosecond based laser beam.

[0034] It is understood that the embodiments herein are contrasted with laser scribing with distinct front and back beam portions. For example, in an embodiment, beam portions 308A, 308B, and 308C of FIG. 3 are aligned vertically and are not separated in time. It is understood that different depths A, B, C, etc. are achieved in a single pass as opposed to being achieved in multiple passes in an additive manner.

[0035] Uniform scribed trenches can be produced by laser scribing processes using multiple focal optics, such as the laser scribing process described above in connection with Figure 3. For comparison, Figure 4 shows a cross-sectional view of a laser scribed trench in a substrate where the laser scribed trench is formed with a single focal laser beam.

[0036] 4, a substrate 400 is scribed with a single-focused laser beam to form a trench 402. The trench 402 has tapered or sloping sidewalls 404 and a pointed or apex bottom. Such a trench 402 may be considered a non-uniform trench and may present difficulties in subsequent plasma etching processes.

[0037] In contrast to FIG. 4, FIG. 5 shows a cross-sectional view of a laser scribed trench in a substrate, where the laser scribed trench is formed with multiple focused laser beams according to an embodiment of the present disclosure.

[0038] 5, a substrate 500 is scribed with multiple focused laser beams to form trenches 402. The trenches 502 have essentially vertical sidewalls 504 and may have rounded bottoms 506. Such trenches 502 may be considered uniform or substantially uniform trenches, allowing for a highly uniform subsequent plasma etch process.

[0039] In embodiments, femtosecond-based lasers are used as sources for the spatially multi-focused laser beam scribing process. For example, in embodiments, lasers with wavelengths in the visible spectrum, as well as the ultraviolet (UV) and infrared (IR) ranges (together resulting in a broadband optical spectrum) can be used with pulse widths on the femtosecond scale (10 -15203 is used to provide femtosecond-based laser pulses having a wavelength of 0.1 s (0.1 s). In one embodiment, the ablation is not wavelength-dependent or essentially not wavelength-dependent, and therefore suitable for complex films such as those on mask 202, street 207, and possibly portions of semiconductor wafer or substrate 204.

[0040] FIG. 6 illustrates the effect of using laser pulse widths in the femtosecond, picosecond, and nanosecond ranges according to an embodiment of the present disclosure. With reference to FIG. 6, using a laser beam in the femtosecond range reduces or eliminates the thermal damage issue (e.g., minimal to no damage 602C due to femtosecond processing of via 600C) for longer pulse widths (e.g., significant damage 602A due to nanosecond processing of via 600A). The elimination or reduction of damage during the formation of via 600C may be due to little energy recombination (as seen for picosecond-based laser ablation of 600B / 602B) or no thermal equilibrium (as seen for nanosecond-based laser ablation), as depicted in FIG. 6.

[0041] Selection of laser parameters such as beam shape can be important to develop a successful laser scribing and dicing process that minimizes chipping, microcracks, and delamination to achieve clean laser scribe cuts. The cleaner the laser scribe cuts, the smoother the etching process that can be performed for final die singulation. In a semiconductor device wafer, many functional layers of different material types (e.g., conductors, insulators, semiconductors) and thicknesses are typically arranged. Such materials can include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as silicon dioxide and silicon nitride.

[0042] The streets between individual integrated circuits disposed on a wafer or substrate may comprise similar or the same layers as the integrated circuits themselves. For example, Figure 7 shows a cross-sectional view of a stack of materials that may be used in the street region of a semiconductor wafer or substrate according to an embodiment of the present disclosure.

[0043] 7, a street region 700 comprises a top portion 702 of a silicon substrate, a first silicon dioxide layer 704, a first etch stop layer 706, a first low k dielectric layer 708 (e.g., having a dielectric constant lower than the dielectric constant of 4.0 for silicon dioxide), a second etch stop layer 710, a second low k dielectric layer 712, a third etch stop layer 714, an undoped silica glass (USG) layer 716, a second silicon dioxide layer 718, and a layer of photoresist 720, with relative thicknesses as depicted. Copper metallization 722 is disposed between the first etch stop layer 706 and the third etch stop layer 714 and through the second etch stop layer 710. In a particular embodiment, the first etch stop layer 706, the second etch stop layer 710, and the third etch stop layer 714 are comprised of silicon nitride, and the low k dielectric layers 708 and 712 are comprised of a silicon oxide material doped with carbon.

[0044] Under conventional laser irradiation (such as nanosecond-based irradiation), the materials of the street 700 behave quite differently in terms of light absorption and ablation mechanisms. For example, dielectric layers such as silicon dioxide are essentially transparent to all commercially available laser wavelengths under normal conditions. In contrast, metals, organics (e.g., low k materials) and silicon can very easily couple photons together, especially in response to nanosecond-based irradiation. In an embodiment, a laser scribing process of spatially multiple focused laser beams is used to pattern a layer of silicon dioxide, a layer of low k material, and a layer of copper by ablating the layer of silicon dioxide before ablating the layer of low k material and the layer of copper.

[0045] When the spatially multi-focused laser beam is a femtosecond-based laser beam, in an embodiment, suitable femtosecond-based laser processing is characterized by a high peak intensity (irradiance) that typically results in nonlinear interactions in various materials. In one such embodiment, the femtosecond laser source has a pulse width in the range of approximately 10 femtoseconds to 500 femtoseconds, preferably in the range of 100 femtoseconds to 400 femtoseconds. In one embodiment, the femtosecond laser source has a wavelength in the range of approximately 1570 nanometers to 200 nanometers, preferably in the range of 540 nanometers to 250 nanometers. In one embodiment, the laser and corresponding optical system provide a focal spot on the workpiece surface in the range of approximately 3 microns to 15 microns, preferably in the range of 5 microns to 10 microns, or between 10-15 microns.

[0046] In an embodiment, the laser source has a pulse repetition rate in the range of approximately 200 kHz to 10 MHz, preferably in the range of approximately 500 kHz to 5 MHz. In an embodiment, the laser source delivers pulse energies to the workpiece surface in the range of approximately 0.5 uJ to 100 uJ, preferably in the range of approximately 1 uJ to 5 uJ. In an embodiment, the laser scribing process advances along the workpiece at a speed in the range of approximately 500 m / sec to 5 m / sec, preferably in the range of approximately 600 m / sec to 2 m / sec.

[0047] The scribing process may proceed in just a single pass or in multiple passes, but in embodiments, preferably proceeds in 1-2 passes. In one embodiment, the scribe depth in the workpiece is in the range of approximately 5 microns to 50 microns deep, and preferably in the range of approximately 10 microns to 20 microns deep. In an embodiment, the kerf width of the laser beam produced is in the range of approximately 2 microns to 15 microns as measured at the device / silicon interface, but preferably in the range of approximately 6 microns to 10 microns for scribing / dicing silicon wafers.

[0048] Laser parameters may be selected for convenience and advantage, such as achieving ionization of inorganic dielectrics (e.g., silicon dioxide) and achieving a high enough laser intensity to minimize layer peeling and chipping caused by damage to the underlying layer before direct ablation of the inorganic dielectric. Parameters may also be selected to provide significant processing throughput for industrial applications with precisely controlled ablation widths (e.g., kerf widths) and depths. In an embodiment, the laser scribing process of spatially multiple focused laser beams is suitable for providing such advantages.

[0049] It is understood that if laser scribing is used to pattern the mask and to scribe sufficiently through the wafer or substrate to singulate the dies, the dicing or singulation process may be stopped after the laser scribing described above. Thus, no further singulation process is required in such cases. However, the following embodiments may be considered in cases where laser scribing alone is not performed for total singulation.

[0050] Referring now to optional operation 106 of flow diagram 100, a post intermediate mask opening cleaning operation is performed. In an embodiment, the post mask opening cleaning operation is a plasma-based cleaning process. In a first example, as described below, the plasma-based cleaning process is reactive to the areas of substrate 204 exposed by gap 210. In the case of a reactive plasma-based cleaning process, the cleaning process itself may form or extend trench 212 in substrate 204, as the reactive plasma-based cleaning process is at least somewhat of an etchant for substrate 204. In a second, different example, also described below, the plasma-based cleaning process is non-reactive to the areas of substrate 204 exposed by gap 210.

[0051] According to a first embodiment, the plasma-based cleaning process is reactive to the exposed areas of the substrate 204 in that the exposed areas are partially etched during the cleaning process. In one such embodiment, Ar or other non-reactive gas (or mixture) is combined with SF6 for a highly biased plasma process for cleaning the scribed openings. A plasma process using the mixed gas Ar+SF6 under high bias power is performed to bombard the mask opening areas with particles to achieve cleaning of the mask opening areas. In a reactive breakthrough process, both physical particle bombardment from Ar and SF6 and chemical etching by SF6 and F ions contribute to cleaning of the mask opening areas. This approach can be suitable for photoresist or plasma deposited Teflon masks 202, and the breakthrough process results in a fairly uniform mask thickness reduction and mild Si etching. However, such a breakthrough etching process may not be optimal for water-soluble mask materials.

[0052] According to a second embodiment, the plasma-based cleaning process is non-reactive to the exposed areas of the substrate 204 in that the exposed areas are not etched or are negligibly etched during the cleaning process. In one such embodiment, only non-reactive gas plasma cleaning is used. For example, Ar or other non-reactive gas (or mixture) is used to perform a highly biased plasma treatment for both mask condensation and cleaning the scribed openings. This approach may be suitable for water-soluble masks or thinner plasma-deposited Teflon 202. In other such embodiments, separate mask condensation and cleaning the scribed trenches are used, for example, a highly biased plasma treatment of Ar or a non-reactive gas (or mixture) for mask condensation is performed first, and then an Ar+SF6 plasma cleaning of the laser scribed trenches is performed. This embodiment may be suitable when the Ar cleaning is not sufficient for trench cleaning due to too thick mask material. Although the cleaning efficiency is improved for thinner masks, the mask etch rate is much smaller and is hardly consumed in the subsequent deep silicon etching process. In yet other such embodiments, three cleaning operations are performed: (a) highly biased plasma treatment of Ar or a non-reactive gas (or mixture) for mask condensation, (b) highly biased plasma cleaning of Ar+SF6 of the laser scribed trenches, and (c) highly biased plasma treatment of Ar or a non-reactive gas (or mixture) for mask condensation. According to other embodiments of the present disclosure, the plasma cleaning operation involves a first use of a reactive plasma cleaning process, such as that described above in the first aspect of operation 106. Thus, the reactive plasma cleaning process is followed by a non-reactive plasma cleaning process, such as that described in connection with the second aspect of operation 106.

[0053] With reference to operation 108 of flowchart 100 and corresponding FIG. 2C, the semiconductor wafer 204 is etched through the gaps 210 in the patterned mask 208 to singulate the integrated circuits 206. According to an embodiment of the present disclosure, etching the semiconductor wafer 204 includes ultimately etching all the way through the semiconductor wafer 204 by etching the trenches 212 formed earlier with a laser scribing process of multiple spatially focused laser beams, as depicted in FIG.

[0054] In an embodiment, patterning the mask with a laser scribing process involves forming trenches in areas of the semiconductor wafer between the integrated circuits, and plasma etching the semiconductor wafer involves extending the trenches to form corresponding trench extensions, In one such embodiment, each of the trenches has a width and each of the corresponding trench extensions has a width.

[0055] According to embodiments of the present disclosure, the roughness resulting from the mask opening from laser scribing can affect the quality of the die sidewall resulting from the subsequent formation of the plasma etched trench. Lithographically opened masks often have smooth features, resulting in correspondingly smooth sidewalls of the plasma etched trench. In contrast, conventional laser opened masks can have very rough features along the scribing direction (such as overlapping spots resulting in rough sidewalls of the plasma etched trench in the horizontal direction) if improper laser processing parameters are selected. While the surface roughness can be smoothed by additional plasma processing, there is a cost and throughput penalty to correcting such issues. Thus, the embodiments described herein can be advantageous in providing a smoother scribing process and / or a more reliable trench formation process from the laser scribing portion of the singulation process.

[0056] In an embodiment, etching the semiconductor wafer 204 includes using a plasma etch process. In one embodiment, a through silicon via type etch process is used. For example, in a particular embodiment, the etch rate of the material of the semiconductor wafer 204 is greater than 25 microns per minute. An ultra-high density plasma source may be used for the plasma etch portion of the die singulation process. An example of a process chamber suitable for performing such a plasma etch process is the Applied Centura® Silvia™ Etch system available from Applied Materials of Sunnyvale, CA, USA. The Applied Centura® Silvia™ Etch system combines capacitive and inductive RF coupling, which provides control of ion density and ion energy that is much more independent than is possible with capacitive coupling alone, with the enhancement provided by magnetic enhancement. This combination allows for an effective decoupling of ion density from ion energy, thereby achieving a relatively high density plasma without large, potentially damaging DC bias levels, even at very low pressures. This results in an exceptionally wide process window. However, any plasma etch chamber capable of etching silicon can be used. In an exemplary embodiment, a deep silicon etch is used to etch the single crystal silicon substrate or wafer 204 at an etch rate approximately 40% greater than conventional silicon etch rates, while maintaining essentially precise shape control and virtually scallop-free sidewalls. In a particular embodiment, a through silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, which is typically a fluorine-based gas such as SF6, C4F8, CHF3, XeF2, or any other reactive gas capable of etching silicon at a relatively fast etch rate. In an embodiment, the mask layer 208 is removed after the singulation process, as depicted in FIG. 2C.In another embodiment, the plasma etch operation described in connection with Figure 2C employs a conventional Bosch dep / etch / dep process to etch through the substrate 204. Generally, the Bosch process consists of three sub-operations: deposition, directional particle bombardment etch, and isotropic chemical etch that are performed through many iterations (cycles) until the silicon is etched through.

[0057] Thus, referring back to flow chart 100 and Figures 2A-2C, wafer dicing may be performed by initial ablation using a laser scribing process of multiple spatially focused laser beams to penetrate the mask layer, penetrate the wafer streets (including metallization), and partially ablate into the silicon substrate. Die singulation may be completed by a subsequent deep through-silicon plasma etch. Specific examples of material stacking for dicing, according to embodiments of the present disclosure, are described below in conjunction with Figures 8A-8D.

[0058] Referring to FIG. 8A, a material stack for hybrid laser ablation and plasma etch dicing comprises a mask layer 802, a device layer 804, and a substrate 806. The mask layer, device layer, and substrate are disposed above a die attach film 808, which is secured to a backing tape 810. In an embodiment, the mask layer 802 is a water-soluble layer, such as the water-soluble layer described above in connection with the mask 202. The device layer 804 comprises an inorganic dielectric layer (such as silicon dioxide) disposed above one or more metal layers (such as a copper layer), and one or more low k dielectric layers (carbon doped oxide layers). The device layer 804 also comprises streets disposed between the integrated circuits, the streets comprising the same or similar layers as the integrated circuits. The substrate 806 is a bulk single crystal silicon substrate.

[0059] In an embodiment, the bulk single crystal silicon substrate 806 is thinned from the backside before being secured to the die attach film 808. The thinning may be performed by a backside grinding process. In one embodiment, the bulk single crystal silicon substrate 806 is thinned to a thickness in the range of approximately 50-100 microns. It is important to note that in an embodiment, the thinning is performed prior to the laser ablation and plasma etch dicing processes. In an embodiment, the photoresist layer 802 has a thickness of approximately 5 microns and the device layer 804 has a thickness in the range of approximately 2-3 microns. In an embodiment, the die attach film 808 (or any suitable substitute capable of bonding the thinned or thinned wafer or substrate to the backing tape 810) has a thickness of approximately 20 microns.

[0060] Referring to Figure 8B, the mask 802, device layer 804, and a portion of the substrate 806 are patterned with a laser scribing process 812 of multiple spatially focused laser beams to form trenches 814 in the substrate 806. Referring to Figure 8C, a deep through-silicon plasma etch process 816 is used to extend the trenches 814 down to the die attach film 808, expose an upper portion of the die attach film 808, and singulate the silicon substrate 806. The device layer 804 is protected by the mask layer 802 during the deep through-silicon plasma etch process 816.

[0061] 8D, the singulation process may further include patterning the die attach film 808, exposing a top portion of the backing tape 810, and singulating the die attach film 808. In an embodiment, the die attach film is singulated by a laser process or an etching process. Further embodiments may include subsequently removing the singulated portions of the substrate 806 (e.g., as individual integrated circuits) from the backing tape 810. In an embodiment, the singulated die attach film 808 is retained on the backside of the singulated portions of the substrate 806. Other embodiments may include removing the mask layer 802 from the device layer 804. In an alternative embodiment, if the substrate 806 is thinner than approximately 50 microns, a laser scribing process 812 of spatially multiple focused laser beams is used to completely singulate the substrate 806 without additional plasma processing.

[0062] A single processing tool may be configured to perform many or all of the operations in a spatially multiple focused laser beam ablation and plasma etch singulation process. For example, Figure 9 shows a block diagram of a tool arrangement for laser and plasma dicing of a wafer or substrate according to an embodiment of the present disclosure.

[0063] 9, a processing tool 900 includes a factory interface 902 (FI) to which a number of load holds 904 are coupled. A cluster tool 906 is coupled to the factory interface 902. The cluster tool 906 includes one or more plasma etch chambers, such as a plasma etch chamber 908. A laser scribing apparatus 910 is also coupled to the factory interface 902. The overall footprint of the processing tool 900, in one embodiment, can be approximately 3500 millimeters (3.5 meters) by approximately 3800 millimeters (3.8 meters), as depicted in FIG.

[0064] In an embodiment, the laser scribing apparatus 910 contains a laser assembly configured to provide a spatially multiple focused laser beam. In one such embodiment, the laser assembly is configured to provide a spatially multiple focused laser beam having a first beam portion focused to a first depth and a second beam portion focused to a second depth, the second depth being vertically below the first depth, as described in connection with FIG. 3. In a further such embodiment, the laser assembly is configured to provide a third beam portion focused to a third depth, the third depth being vertically below the second depth, also as described in connection with FIG. 3. In an embodiment, the laser assembly comprises a diffractive optical element (DOE). In an embodiment, the laser assembly comprises a Gaussian source laser beam. In an embodiment, the laser assembly comprises a femtosecond source laser beam.

[0065] In an embodiment, the laser is suitable for performing the laser ablation portion of a hybrid laser and etch singulation process, such as the laser ablation process described above. In one embodiment, a movable stage is also included in the laser scribing apparatus 910, configured to move the wafer or substrate (or its carrier) relative to the laser. In certain embodiments, the laser is also movable. The overall footprint of the laser scribing apparatus 910, in one embodiment, can be approximately 2240 millimeters by approximately 1270 millimeters, as depicted in FIG. 9.

[0066] In an embodiment, the one or more plasma etch chambers 908 are configured to etch the wafer or substrate through gaps in a patterned mask to singulate a plurality of integrated circuits. In one such embodiment, the one or more plasma etch chambers 908 are configured to perform a deep silicon etch process. In a particular embodiment, the one or more plasma etch chambers 808 are Applied Centura® Silvia™ Etch systems available from Applied Materials of Sunnyvale, CA, USA. The etch chambers may be specifically designed for deep silicon etching used to create singulated integrated circuits housed in single crystal silicon substrates or wafers. In an embodiment, a high density plasma source is included in the plasma etch chamber 908 to facilitate a high silicon etch rate. In an embodiment, two or more etch chambers are included in the cluster tool 906 portion of the processing tool 900 to enable high manufacturing throughput of the singulation or dicing process.

[0067] Factory interface 902 may be a suitable atmospheric port to interface between the outside of the fabrication facility and the cluster tool 906 with the laser scribing apparatus 910. Factory interface 902 may include a robot with an arm or blade to transport wafers (or their carriers) from a storage unit (front-opening unified pod) to the cluster tool 906, the laser scribing apparatus 910, or both.

[0068] The cluster tool 906 may include other chambers suitable for performing functions in the singulation method. For example, in one embodiment, instead of an additional etch chamber, a deposition chamber 912 is included. The deposition chamber 912 may be configured for mask deposition on or above a device layer of a wafer or substrate prior to laser scribing of the wafer or substrate. In one such embodiment, the deposition chamber 912 is suitable for depositing a photoresist layer. In another embodiment, instead of an additional etch chamber, a wet / dry station 914 is included. The wet / dry station may be suitable for cleaning residues and fragments or for removing a mask following a laser scribe and plasma etch singulation process of a substrate or wafer. In yet another embodiment, instead of an additional deep silicon etch chamber, a plasma etch chamber is included and configured for performing a plasma-based cleaning process. In an embodiment, a metrology station is also included as a component of the processing tool 900.

[0069] The embodiments of the present disclosure may be provided as a computer program product or software that may comprise a machine-readable medium having instructions stored thereon that may be used to program a computer system (or other electronic device) to perform processes according to the embodiments of the present disclosure. In one embodiment, the computer system is coupled to a processing tool 900, as described in connection with FIG. 9. A machine-readable medium comprises any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium (e.g., read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustic, or other form of propagated signals (e.g., infrared signals, digital signals, etc.), etc.

[0070] FIG. 10 shows a diagrammatic depiction of a machine in the exemplary form of a computer system 1000 upon which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies described herein. In alternative embodiments, the machine may be coupled (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed. Furthermore, although only a single machine is shown, the term "machine" shall be understood to include any collection of machines (e.g., computers) that individually or collectively execute a set (or sets) of instructions to perform one or more of the methodologies described herein.

[0071] The exemplary computer system 1000 includes a processor 1002, a main memory 1004 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), MRAM, etc.), and a secondary memory 1018 (e.g., a data storage device), which communicate with each other via a bus 1030.

[0072] The processor 1002 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processor 1002 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processor 1002 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processor 1002 is configured to execute processing logic 1026 for performing the operations described herein.

[0073] The computer system 1000 may further include a network interface device 1008. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LDC), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), and a signal generating device 1016 (e.g., a speaker).

[0074] The secondary memory 1018 may comprise a machine-accessible storage medium (or, more specifically, a computer-readable storage medium) 1032 on which is stored one or more sets of instructions (e.g., software 1022) embodying any one or more of the methods or functions described herein. The software 1022 may reside, in whole or at least in part, within the main memory 1004 and / or the processor 1002 during its execution by the computer system 1000, with the main memory 1004 and the processor 1002 also constituting a machine-readable storage medium. The software 1022 may further be transmitted or received over the network 1020 via the network interface device 1008.

[0075] While the machine-accessible storage medium 1032 is shown in the illustrated embodiment to be a single medium, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to comprise any medium that can store or encode a set of instructions for execution by a machine, causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state storage devices, and optical and magnetic media.

[0076] According to an embodiment of the present disclosure, a machine-accessible storage medium stores instructions for causing a data processing system to perform a method for dicing a semiconductor wafer having a plurality of integrated circuits. The method includes forming a mask over the semiconductor wafer comprising a layer that covers and protects the integrated circuits. The mask is then patterned with a laser scribing process of multiple spatially focused laser beams to provide gaps in the patterned mask and expose areas of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

[0077] Thus, a hybrid wafer dicing approach using multiple spatially focused laser beams and a plasma etching process is disclosed.

Claims

1. 1. A method for dicing a semiconductor wafer having a plurality of integrated circuits, comprising: forming a mask over the semiconductor wafer comprising a layer covering and protecting the integrated circuit; patterning the mask with a laser scribing process of multiple spatially focused laser beams to provide gaps in the patterned mask and expose areas of the semiconductor wafer between the integrated circuits; plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits; Including, wherein patterning the mask with the laser scribing process includes forming trenches in the areas of the semiconductor wafer between the integrated circuits, the trenches having essentially vertical sidewalls and rounded bottoms.

2. 2. The method of claim 1, wherein the spatially multiple focused laser beam laser scribing process provides a first beam portion focused to a first depth in the semiconductor wafer and a second beam portion focused to a second depth in the semiconductor wafer, the second depth being vertically below the first depth.

3. 3. The method of claim 2, wherein the spatially multiple focused laser beam laser scribing process provides a third beam portion that is focused to a third depth in the semiconductor wafer, the third depth being vertically below the second depth.

4. The method of claim 1 , wherein the laser scribing of the spatially multiple focused laser beams comprises passing the laser beams through a diffractive optical element (DOE).

5. The method of claim 1 , wherein the laser scribing process of the spatially multiple focused laser beams comprises using a Gaussian source laser beam.

6. The method of claim 5 , wherein the laser scribing process of the spatially multiple focused laser beams includes using a femtosecond source laser beam.

7. 10. The method of claim 1, wherein scribing with the spatially multiple focused laser beam laser scribing process comprises scribing with spatially multiple focused femtosecond based laser beams.

8. The method of claim 1, wherein plasma etching the semiconductor wafer includes extending the trench to form a corresponding trench extension.

9. 1. A method for dicing a semiconductor wafer having a plurality of integrated circuits, comprising:

11. A method for laser scribing a semiconductor wafer with a laser scribing process of a spatially focused laser beam to singulate the plurality of integrated circuits, wherein laser scribing the semiconductor wafer with a laser scribing process of a spatially focused laser beam includes forming trenches in areas of the semiconductor wafer between the integrated circuits, the trenches having essentially vertical sidewalls and a rounded bottom.

10. 10. The method of claim 9, wherein the spatially multiple focused laser beam laser scribing process provides a first beam portion focused to a first depth in the semiconductor wafer and a second beam portion focused to a second depth in the semiconductor wafer, the second depth being vertically below the first depth.

11. 11. The method of claim 10, wherein the spatially multiple focused laser beam laser scribing process provides a third beam portion that is focused to a third depth in the semiconductor wafer, the third depth being vertically below the second depth.

12. The method of claim 10 , wherein the laser scribing of the spatially multiple focused laser beams comprises passing the laser beams through a diffractive optical element (DOE).

13. The method of claim 10 , wherein the laser scribing process of the spatially multiple focused laser beams comprises using a Gaussian source laser beam.

14. The method of claim 10 , wherein the laser scribing process of the spatially multiple focused laser beams comprises using a femtosecond source laser beam.

15. 1. A system for dicing a semiconductor wafer having a plurality of integrated circuits, comprising: A factory interface; a laser scribing apparatus coupled to the factory interface, the laser scribing apparatus comprising a laser assembly configured to provide multiple spatially focused laser beams, the laser scribing apparatus configured to form trenches in areas of the semiconductor wafer between the integrated circuits, the trenches having essentially vertical sidewalls and a rounded bottom; a plasma etch chamber coupled to the factory interface; A system comprising:

16. 16. The system of claim 15, wherein the laser assembly is configured to provide the spatially multiple focused laser beams having a first beam portion focused to a first depth and a second beam portion focused to a second depth, the second depth being vertically below the first depth.

17. 17. The system of claim 16, wherein the laser assembly is configured to provide a third beam portion focused to a third depth, the third depth being vertically below the second depth.

18. The system of claim 15 , wherein the laser assembly comprises a diffractive optical element (DOE).

19. The system of claim 15 , wherein the laser assembly comprises a Gaussian source laser beam.

20. The system of claim 15 , wherein the laser assembly comprises a femtosecond source laser beam.

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