Semiconductor Device

Abstract

To reduce on-resistance of a semiconductor device to be used for an application where large current flows.SOLUTION: A semiconductor device 10 includes a source terminal lead SL that is positioned between a gate terminal lead GL and a Kelvin terminal lead KL in a plan view and is electrically connected to a source terminal ST via a plurality of wires W3.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device that is a component of an inverter, for example. [Background technology]

[0002] JP 2008-294384 A (Patent Document 1) describes a technique for reducing the on-resistance of a semiconductor device in which a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed.

[0003] Japanese Patent Laid-Open Publication No. 2009-231805 (Patent Document 2) also describes a technique for reducing the on-resistance of a semiconductor device in which a power MOSFET is formed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-294384 A [Patent Document 2] JP 2009-231805 A Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, it has been considered to pass a large current through a semiconductor device in which a power semiconductor element is formed. For example, it has been considered to pass a current of about 300 A through a semiconductor device used in a three-phase inverter. In this regard, when a large current is passed through a semiconductor device, the on-resistance present in the semiconductor device has a significant effect on the performance of the semiconductor device. Therefore, in semiconductor devices used for applications in which a large current is passed, it is desired to devise a way to reduce the on-resistance. [Means for solving the problem]

[0006] In one embodiment, a semiconductor device has a force terminal lead that is located between a gate terminal lead and a sense terminal lead in a planar view and is electrically connected to a force terminal via a force terminal connection member among a plurality of connection members.

[0007] In addition, a semiconductor device in another embodiment has a force terminal lead that is located between the gate terminal lead and the multi-function terminal lead in a planar view and is electrically connected to the force terminal via a force terminal connection member among the multiple connection members. Effect of the Invention

[0008] According to one embodiment, the performance of a semiconductor device can be improved. [Brief description of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing a circuit configuration including an inverter circuit and a three-phase induction motor. [Diagram 2] FIG. 1 is a schematic diagram showing an example of a mounting layout for implementing an inverter circuit. [Diagram 3] FIG. 1 is a diagram illustrating an internal structure of a semiconductor device. [Figure 4] FIG. 1 is a circuit diagram showing a schematic connection configuration of a power MOSFET when no Kelvin terminal lead is provided. [Diagram 5] FIG. 1 is a circuit diagram showing a schematic connection configuration of a power MOSFET when a Kelvin terminal lead is provided. [Figure 6] 1 is a schematic diagram showing a package configuration of a semiconductor device according to an embodiment; [Figure 7] 1 is a cross-sectional view of a main part of a semiconductor chip showing an n-channel trench-gate power MOSFET, which is an example of a power MOSFET. [Figure 8] FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a first modified example. [Figure 9] FIG. 11 is a diagram showing a schematic configuration of a semiconductor device according to a second modified example. [Figure 10] FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a third modified example. [Figure 11] FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a fourth modified example. [Figure 12] FIG. 13 is a diagram showing a schematic configuration of a semiconductor device according to a fifth modified example. [Figure 13] 1A to 1C are diagrams illustrating a wire arrangement that embodies the technical idea of ​​an embodiment. [Figure 14] FIG. 1 is a diagram showing a schematic diagram of a wire arrangement embodying an example of related art. [Figure 15] FIG. 13 is a diagram showing a schematic diagram of a wire arrangement embodying another example of the related art. [Figure 16] 1A and 1B are diagrams illustrating a configuration for arranging wires that embodies the technical idea of ​​the present embodiment, assuming that the area occupied by a semiconductor chip is fixed. [Figure 17] FIG. 1 is a diagram showing a schematic diagram of a configuration for arranging wires according to a related art technique. [Figure 18] FIG. 1 is a circuit diagram of a bidirectional thyristor. [Figure 19] FIG. 2 is a diagram illustrating a structure of a bidirectional thyristor. [Figure 20] 1 is a diagram showing a configuration of a semiconductor device including a bidirectional thyristor according to the related art; [Figure 21] FIG. 1 is a diagram showing a configuration of a semiconductor device including a power MOSFET according to the related art. [Figure 22] 1 is a diagram showing an example of a semiconductor device in which a bidirectional thyristor is formed and to which a layout of a plurality of leads according to an embodiment is applied; [Diagram 23] 11 is a diagram showing another example of a semiconductor device in which a bidirectional thyristor is formed and to which a layout of a plurality of leads according to an embodiment is applied; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0011] <Example of a three-phase inverter circuit> The semiconductor device in this embodiment is used in, for example, a drive circuit for a three-phase induction motor used in an air conditioner, etc. Specifically, this drive circuit includes an inverter circuit, and this inverter circuit is a circuit having a function of converting DC power into AC power.

[0012] FIG. 1 is a circuit diagram showing the configuration of a motor circuit including an inverter circuit and a three-phase induction motor. In FIG. 1, the motor circuit has a three-phase induction motor MT and an inverter circuit INV. The three-phase induction motor MT is configured to be driven by three-phase voltages with different phases. Specifically, the three-phase induction motor MT uses three-phase AC currents called U-phase, V-phase, and W-phases, which are 120 degrees out of phase, to generate a rotating magnetic field around the rotor RT, which is a conductor. In this case, the magnetic field rotates around the rotor RT. This means that the magnetic flux that crosses the rotor RT, which is a conductor, changes. As a result, electromagnetic induction occurs in the rotor RT, which is a conductor, and an induced current flows in the rotor RT. And, the flow of an induced current in a rotating magnetic field means that a force is applied to the rotor RT according to Fleming's left-hand rule, and this force causes the rotor RT to rotate. In this way, it can be seen that the three-phase induction motor MT can rotate the rotor RT by using three-phase AC currents. In other words, the three-phase induction motor MT requires three-phase AC currents. Therefore, the motor circuit uses an inverter circuit INV that creates AC from DC to supply three-phase AC to the three-phase induction motor.

[0013] A configuration example of this inverter circuit INV will be described below.

[0014] As shown in Fig. 1, for example, the inverter circuit INV is provided with a switching element Q1 and a diode FWD corresponding to three phases. That is, in the inverter circuit INV, for example, the components of the inverter circuit INV are realized by a configuration in which the switching element Q1 and the diode FWD are connected in anti-parallel as shown in Fig. 1. For example, in Fig. 1, the upper arm and the lower arm of the first leg LG1, the upper arm and the lower arm of the second leg LG2, and the upper arm and the lower arm of the third leg LG3 are each composed of a component in which the switching element Q1 and the diode FWD are connected in anti-parallel.

[0015] In other words, in the inverter circuit INV, the switching element Q1 and the diode FWD are connected in anti-parallel between the positive potential terminal PT and each phase (U-phase, V-phase, W-phase) of the three-phase induction motor MT, and the switching element Q1 and the diode FWD are also connected in anti-parallel between each phase of the three-phase induction motor MT and the negative potential terminal NT. That is, two switching elements Q1 and two diodes FWD are provided for each phase, and six switching elements Q1 and six diodes FWD are provided in three phases. A gate control circuit GCC is connected to the gate electrode of each switching element Q1, and the switching operation of the switching element Q1 is controlled by this gate control circuit GCC. In the inverter circuit INV configured in this way, the gate control circuit GCC controls the switching operation of the switching element Q1 to convert DC power into three-phase AC power, and the three-phase AC power is supplied to the three-phase induction motor MT.

[0016] <Types of switching elements> For example, the switching element Q1 used in the inverter circuit INV may be a power MOSFET or an IGBT (Insulated Gate Bipolar Transistor).

[0017] <The need for diodes> As described above, the inverter circuit INV uses the switching element Q1. When an IGBT is used as this switching element Q1, it is necessary to provide a diode FWD connected in anti-parallel to the IGBT.

[0018] Simply from the viewpoint of realizing a switching function by the switching element Q1, an IGBT is necessary as the switching element Q1, but it is considered that there is no need to provide a diode FWD. In this regard, when the load connected to the inverter circuit INV includes an inductance, such as when the load is a motor, it is necessary to provide a diode FWD. The reason for this will be explained below.

[0019] The diode FWD is not necessary if the load is a pure resistor that does not contain inductance, since there is no energy to return. However, if a circuit that contains inductance, such as a motor, is connected to the load, there is a mode in which the load current flows in the opposite direction to the on switch. In other words, if the load contains inductance, energy may return from the load inductance to the inverter circuit INV (current may flow backwards).

[0020] At this time, the IGBT alone does not have the function to allow this return current to flow, so a diode FWD must be connected in anti-parallel to the IGBT. In other words, in the inverter circuit INV, if the load includes an inductance, such as in motor control, when the IGBT is turned off, the energy stored in the inductance (1 / 2LI 2) must be released. However, an IGBT alone cannot pass a return current to release the energy stored in the inductance. Therefore, a diode FWD is connected in anti-parallel to the IGBT in order to return the electrical energy stored in the inductance. In other words, the diode FWD has the function of passing a return current to release the electrical energy stored in the inductance. From the above, it can be seen that in an inverter circuit connected to a load including an inductance, when an IGBT is used as the switching element Q1, it is necessary to provide a diode FWD in anti-parallel to the IGBT. This diode FWD is called a freewheeling diode.

[0021] On the other hand, when a power MOSFET is used as the switching element Q1, in principle, there is no need to provide a freewheel diode connected in anti-parallel to the power MOSFET, because the device structure of the power MOSFET inevitably includes a body diode, which is a pn junction diode, formed parasitically, and this body diode functions as a freewheel diode.

[0022] However, even when a power MOSFET is used as the switching element Q1, a Schottky diode, which has a smaller forward voltage drop than a pn junction diode, may be used as the freewheel diode.

[0023] The technical idea of ​​this embodiment is applicable to a configuration in which either an IGBT or a power MOSFET is used for the switching element Q1, but in the following explanation, an example in which the switching element Q1 is configured from a power MOSFET is taken up. Since the presence or absence of a freewheel diode is not directly related to the explanation of the technical idea of ​​this embodiment, the technical idea of ​​this embodiment will be explained below for simplicity, assuming that a freewheel diode does not exist.

[0024] <Inverter circuit mounting layout example> FIG. 2 is a schematic diagram showing an example of a mounting layout for realizing an inverter circuit.

[0025] 2, a power supply wiring VL, wiring WL1 to WL3, and a ground wiring GL are formed on the motherboard. A power supply potential is supplied to the power supply wiring VL, while a ground potential (earth potential) is supplied to the ground wiring GL. The wiring WL1 is connected to the U-phase of a three-phase induction motor, the wiring WL2 is connected to the V-phase of the three-phase induction motor, and the wiring WL3 is connected to the W-phase of the three-phase induction motor.

[0026] As shown in Fig. 2, the semiconductor device SA1 is connected between the power supply wiring VL and the wiring WL1, while the semiconductor device SA2 is connected between the wiring WL1 and the ground wiring GL. That is, the semiconductor devices SA1 and SA2 are connected in series between the power supply wiring VL and the ground wiring GL, and constitute the first leg LG1 of the inverter circuit INV shown in Fig. 1. That is, the semiconductor device SA1 constitutes the upper arm of the first leg LG1, and the semiconductor device SA2 constitutes the lower arm of the first leg LG1. Each of the semiconductor devices SA1 and SA2 has a semiconductor chip on which a power MOSFET functioning as a switching element Q1 is formed.

[0027] Similarly, the semiconductor device SA3 is connected between the power supply wiring VL and the wiring WL2, while the semiconductor device SA4 is connected between the wiring WL2 and the ground wiring GL. That is, the semiconductor devices SA3 and SA4 are connected in series between the power supply wiring VL and the ground wiring GL, and constitute the second leg LG2 of the inverter circuit INV shown in FIG. 1. That is, the semiconductor device SA3 constitutes the upper arm of the second leg LG2, and the semiconductor device SA4 constitutes the lower arm of the second leg LG2. Each of the semiconductor devices SA3 and SA4 has a semiconductor chip on which a power MOSFET functioning as a switching element Q1 is formed.

[0028] Furthermore, the semiconductor device SA5 is connected between the power supply wiring VL and the wiring WL3, while the semiconductor device SA6 is connected between the wiring WL3 and the ground wiring GL. That is, the semiconductor devices SA5 and SA6 are connected in series between the power supply wiring VL and the ground wiring GL, and constitute the third leg LG3 of the inverter circuit INV shown in FIG. 1. That is, the semiconductor device SA5 constitutes the upper arm of the third leg LG3, and the semiconductor device SA6 constitutes the lower arm of the third leg LG3. Each of the semiconductor devices SA5 and SA6 has a semiconductor chip on which a power MOSFET functioning as a switching element Q1 is formed.

[0029] In this manner, by arranging the six semiconductor devices SA1 to SA6 on a motherboard on which the power supply wiring VL1, wiring WL1 to wiring WL3 and ground wiring GL are formed as shown in FIG. 2, a mounting layout corresponding to an inverter circuit can be realized.

[0030] <Advantages of the "TO Package"> In this embodiment, for example, as shown in FIG. 2, a "TO (Transistor Outline) package" is adopted as a package structure of a semiconductor device SA having a semiconductor chip on which a power MOSFET is formed. Here, the "TO package" is defined as a package structure in which a plurality of leads are arranged only on a first side of a semiconductor device in a plan view. In this respect, the "TO package" is different from a "SON (Small Outline Non-Leaded) package" or a "SOP (Small Outline Package) package" in which a plurality of leads are arranged not only on a first side of a semiconductor device but also on a second side opposite to the first side in a plan view, and is also different from a "QFN (Quad Flat Non-leaded) package" or a "QFP (Quad Flat Package) package" in which a plurality of leads are arranged on all four sides of a semiconductor device. According to the "TO package" adopted in this embodiment, for example, as shown in FIG. 2, a plurality of leads are arranged only on a first side of a semiconductor device SA, so that the advantage of easier wiring on a motherboard is obtained compared to the other packages mentioned above. In other words, by adopting the "TO package", it is possible to realize a mounting layout compatible with the inverter circuit with a simplified layout (see Figure 2).

[0031] The present inventors have conducted research from the perspective of reducing the on-resistance of the semiconductor device SA, assuming that the semiconductor device SA is constructed from a "TO package" having the advantages described above, and as a result have newly discovered that there is room for improvement in the "TO package" from the perspective of realizing a reduction in the on-resistance, as described below. This point will now be described.

[0032] <Room for improvement> FIG. 3 is a diagram showing a schematic internal structure of the semiconductor device SA.

[0033] In Fig. 3, for example, a die pad DP is disposed inside a sealing body MR made of resin. A semiconductor chip CHP is mounted on the die pad DP. A power MOSFET is formed on the semiconductor chip CHP. A gate terminal GT electrically connected to the gate electrode of the power MOSFET, and a Kelvin terminal KT and a source terminal ST electrically connected to the source region of the power MOSFET are formed on the front surface of the semiconductor chip CHP. On the other hand, although not shown in Fig. 3, a drain electrode of the power MOSFET is formed on the back surface of the semiconductor chip CHP, and this drain electrode is electrically connected to the die pad DP.

[0034] Next, a plurality of leads are arranged on a side S1 of the sealing body MR so as to protrude from the sealing body MR. Specifically, the plurality of leads include a gate terminal lead GL, a Kelvin terminal lead KL, and a source terminal lead SL.

[0035] The gate terminal lead GL is electrically connected to the gate terminal GT via a wire W1 which is a gate terminal connecting member. The Kelvin terminal lead KL is electrically connected to the Kelvin terminal KT via a wire W2 which is a Kelvin terminal connecting member. The source terminal lead SL is electrically connected to the source terminal ST by a plurality of wires W3 which are source terminal connecting members.

[0036] In this manner, the semiconductor device SA, which is a "TO package", is constructed.

[0037] 3, in the semiconductor device SA, the Kelvin terminal lead KL is disposed next to the gate terminal lead GL. As a result, the relative positions of the source terminal ST and the source terminal lead SL are shifted, and the wire W3 connecting the source terminal ST and the source terminal lead SL is bent. That is, in the semiconductor device SA, the source terminal ST and the source terminal lead SL are connected using a bent wire W3. When such a bent wire W3 is used, the source terminal ST and the source terminal lead SL cannot be connected in the shortest distance, which leads to an increase in the resistance value of the wire W3.

[0038] In this regard, the present inventor has considered passing a large current of about 300A through the semiconductor device SA, and has newly found that in this case, the increase in resistance due to the bent wire W3 has a non-negligible effect on reducing the on-resistance. In particular, the bent wire W3 connects the source terminal ST, through which a large current flows, to the source terminal lead SL, and a large current flows through the bent wire W3 itself. As a result, even a slight increase in resistance due to bending leads to a large voltage drop and Joule heat generation, so that the bent wire W3 becomes a factor that leads to a non-negligible performance degradation when applied to a semiconductor device SA for use in passing a large current. Thus, there is room for improvement in the semiconductor device SA, which is a "TO package", from the perspective of improving performance, as typified by the reduction of the on-resistance.

[0039] The present inventors have therefore carried out a detailed study of the reasons why bent wires W3 must be used in the semiconductor device SA which is a "TO package", and this point will be explained below.

[0040] 3, the reason why the bent wire W3 must be used is believed to be mainly because the Kelvin terminal lead KL is arranged next to the gate terminal lead GL, making it impossible to arrange the source terminal lead SL in the center of the side S1 corresponding to the arrangement position of the source terminal ST. Regarding this point, before explaining why it is necessary to arrange the Kelvin terminal lead KL next to the gate terminal lead GL, the technical significance of providing the Kelvin terminal lead KL will first be explained.

[0041] <<The technical significance of providing leads for Kelvin terminals>> Fig. 4 is a circuit diagram showing a typical connection configuration of the power MOSFET 100 when the Kelvin terminal lead KL is not provided. As shown in Fig. 4, the power MOSFET 100 is provided between a die pad DP and a source terminal lead SL, and a "resistance R" represents, for example, a package resistance including a resistance value due to a wire W3. The gate electrode of the power MOSFET 100 is electrically connected to the gate terminal lead GL.

[0042] Here, a voltage V1 between the source terminal lead SL and the gate terminal lead GL is input to, for example, the gate control circuit GCC shown in Fig. 1. The gate control circuit GCC controls the switching operation of the power MOSFET 100 based on the input voltage V1. At this time, in order for the gate control circuit GCC to stably control the power MOSFET 100, it is required that the voltage V1 is equal to the voltage VGS shown in Fig. 4.

[0043] However, in the connection configuration shown in Fig. 4, a large drain current ID flows between the die pad DP and the source terminal lead SL. This causes a large current to flow through the package resistance ("resistance R"), resulting in a large voltage drop. This means that the voltage V1 will have a value significantly different from the voltage VGS. Therefore, in the connection configuration of the power MOSFET 100 shown in Fig. 4, there is a risk that the control of the power MOSFET 100 by the gate control circuit GCC will become unstable.

[0044] In contrast, Fig. 5 is a circuit diagram showing a schematic connection configuration of the power MOSFET 100 when a Kelvin terminal lead KL is provided. In the connection configuration shown in Fig. 5, not only a source terminal lead SL connected to the source (source terminal) of the power MOSFET 100 but also a Kelvin terminal lead KL connected to the source (Kelvin terminal) of the power MOSFET 100 is provided. As a result, as shown in Fig. 5, even if a large drain current ID flows between the die pad DP and the source terminal lead SL, the drain current ID does not flow through the Kelvin terminal lead KL. This means that the voltage V1 between the Kelvin terminal lead KL and the gate terminal lead GL is not affected by a voltage drop caused by the drain current ID flowing through the package resistance ("resistance R"). As a result, the voltage V1 between the Kelvin terminal lead KL and the gate terminal lead GL becomes approximately equal to the voltage VGS.

[0045] 5, it is possible to stabilize the control of the power MOSFET 100 by the gate control circuit GCC. That is, the Kelvin terminal lead KL has the technical significance of stabilizing the control of the power MOSFET 100 by the gate control circuit GCC by inputting a voltage V1 that is approximately equal to the voltage VGS to the gate control circuit GCC without being affected by the voltage drop caused by the drain current ID.

[0046] <<Reason for placing the Kelvin terminal lead next to the gate terminal lead>> Considering the technical significance of providing the Kelvin terminal lead KL described above, in order to make the voltage V1 between the gate terminal lead GL and the Kelvin terminal lead KL approximately equal to the voltage VGS, it is desirable for the parasitic resistance between the gate terminal lead GL and the Kelvin terminal lead KL to be small. For this reason, the Kelvin terminal lead KL is disposed next to the gate terminal lead GL. In the "TO package", the wire W3 connecting the source terminal ST and the source terminal lead SL is bent as a result of disposing the Kelvin terminal lead KL next to the gate terminal lead GL.

[0047] In this regard, in the above-mentioned packages other than the "TO package", since the side on which the multiple leads are arranged is not only the first side but also the other sides, even if it is necessary to arrange the Kelvin terminal lead KL next to the gate terminal lead GL, for example, by arranging the gate terminal lead GL and the Kelvin terminal lead KL adjacent to each other on a second side different from the first side, and arranging the source terminal lead SL on the first side, a configuration that does not require bending the source terminal lead SL can be easily realized. However, in the above-mentioned packages other than the "TO package", the wiring on the motherboard becomes complicated.

[0048] In contrast, in the "TO package", the side on which the multiple leads are arranged is limited to side S1, which provides the advantage of facilitating wiring on the motherboard. On the other hand, in the "TO package", the side on which the multiple leads are arranged is limited to side S1, so if the Kelvin terminal lead KL is arranged next to the gate terminal lead GL, the source terminal lead SL cannot be arranged in the center of side S1 corresponding to the arrangement position of the source terminal ST. For this reason, the Kelvin terminal lead KL gets in the way, making it difficult to connect the source terminal ST and the source terminal lead SL with the shortest wire W3, and it becomes necessary to bend the wire W3. In other words, the room for improvement of bending the wire W3 is a room for improvement that becomes apparent in the "TO package" including the Kelvin terminal lead KL.

[0049] Therefore, in this embodiment, a device is provided to overcome the room for improvement caused by the bending of the wire W3 that occurs in a "TO package" including the Kelvin terminal lead KL. The technical concept of this embodiment that provides this device will be described below.

[0050] <Package configuration of semiconductor device> FIG. 6 is a schematic diagram showing a package configuration of the semiconductor device 10 in this embodiment.

[0051] In FIG. 6, the semiconductor device 10 is a "TO package" and has a die pad DP arranged inside a sealing body MR made of resin, for example. A semiconductor chip CHP is mounted on the die pad DP. A power MOSFET is formed on the semiconductor chip CHP. A gate terminal GT electrically connected to the gate electrode of the power MOSFET, a source terminal ST electrically connected to the source region of the power MOSFET, and a Kelvin terminal KT electrically connected to the source region of the power MOSFET are formed on the surface of the semiconductor chip CHP. At this time, as shown in FIG. 6, in a plan view, the source terminal ST includes a portion located between the gate terminal GT and the Kelvin terminal KT. On the other hand, although not shown in FIG. 6, a drain electrode is formed on the back surface of the semiconductor chip CHP, and this drain electrode is electrically connected to the die pad DP.

[0052] The source terminal ST is a "force terminal" for the purpose of passing current, and the Kelvin terminal KT is a "sense terminal" for the purpose of sensing voltage.

[0053] Next, as shown in FIG. 6, a plurality of leads are arranged on a side S1 of the sealing body MR so as to protrude from the sealing body MR. In other words, a plurality of leads are arranged along a first side of the semiconductor chip parallel to the side S1 of the sealing body MR. Specifically, the plurality of leads include a gate terminal lead GL, a Kelvin terminal lead KL, and a source terminal lead SL. The gate terminal lead GL is electrically connected to the gate terminal GT via a wire (bonding wire) W1 which is a gate terminal connection member. Furthermore, the Kelvin terminal lead KL is electrically connected to the Kelvin terminal KT via a wire (bonding wire) W2 which is a Kelvin terminal connection member. Furthermore, the source terminal lead SL is electrically connected to the source terminal ST by a plurality of wires (bonding wires) W3 which are source terminal connection members. In this embodiment, each of the wires W1, W2, and W3 is made of, for example, gold (Au), but wires made of copper (Cu) may also be used.

[0054] Here, in this embodiment, as shown in FIG. 6, the gate terminal lead GL and the Kelvin terminal lead KL are not arranged adjacent to each other, and a plurality of source terminal leads SL are arranged between the gate terminal lead GL and the Kelvin terminal lead KL.

[0055] Each of the wires W3 electrically connecting the source terminal ST and the source terminal lead SL has a straight shape extending in the y direction (second direction) perpendicular to the x direction (first direction) in which the side S1 extends. In other words, each of the wires W3 has a straight shape extending only in the y direction perpendicular to the x direction.

[0056] As shown in FIG. 6, each of the wires W3 is connected to the source terminal ST at multiple points. For example, each wire W3 is connected to the source terminal ST at a junction point P1 and a junction point P2. That is, the number of junction points between the wire W1 and the gate terminal GT is one, and the number of junction points between the wire W2 and the Kelvin terminal KT is one, whereas the number of junction points between each wire W3 and the source terminal ST is two. That is, by increasing the number of junction points between the source terminal ST and each of the wires W3, the on-resistance on the current path between the source terminal ST and the source terminal lead SL can be reduced. As shown in FIG. 6, the source terminal ST and the source terminal lead SL are not only electrically connected to each other via the wires W3, but also each wire W3 is connected to the source terminal ST at multiple points, so that a large current (300 A) can be passed between the source terminal ST and the source terminal lead SL. In the present embodiment, as shown in FIG. 6, the number of junction points between each wire W3 and the source terminal ST is two, but it may be two or more.

[0057] On the other hand, each wire W3 and the source terminal lead SL are connected at a junction point P3. That is, the number of junction points between each wire W3 and the source terminal lead SL is one. This is because, as shown in FIG. 6, the area of ​​the source terminal lead SL (particularly, the length of the source terminal lead SL along the y direction in which the wire W3 extends) is smaller (shorter) than the area of ​​the source terminal ST (particularly, the length of the source terminal ST along the y direction in which the wire W3 extends).

[0058] In this manner, the semiconductor device 10, which is a "TO package", is configured to be capable of passing a current of, for example, 300 A.

[0059] <Power MOSFET device structure> Next, the device structure of the power MOSFET formed in the semiconductor chip CHP will be described. Fig. 7 is a cross-sectional view of a main part of the semiconductor chip CHP, showing an n-channel trench gate type power MOSFET as an example of the power MOSFET.

[0060] In Figure 7, n + The surface of the semiconductor substrate 20 made of n-type single crystal silicon is - An epitaxial layer 21 made of type single crystal silicon is formed on the semiconductor substrate 20. The semiconductor substrate 20 and the epitaxial layer 21 form the drain of the power MOSFET.

[0061] A p-type well 22 is formed in a part of the epitaxial layer 21. A silicon oxide film 23 is formed in a part of the surface of the epitaxial layer 21, and a plurality of grooves 24 are formed in another part. Of the surface of the epitaxial layer 21, a region covered with the silicon oxide film 23 constitutes an element isolation region, while a region in which the grooves 24 are formed constitutes an element formation region (active region). Although not shown, the planar shape of the grooves 24 is a polygon such as a square, hexagon, or octagon, or a stripe shape extending in one direction.

[0062] A silicon oxide film 25 constituting the gate insulating film of the power MOSFET is formed on the bottom and side walls of the groove 24. A polycrystalline silicon film 26A constituting the lower layer gate electrode of the power MOSFET is buried inside the groove 24. Meanwhile, a gate extraction electrode 26B made of a polycrystalline silicon film deposited in the same process as the polycrystalline silicon film 26A is formed on the upper part of the silicon oxide film 23. The lower layer gate electrode (polycrystalline silicon film 26A) and the gate extraction electrode 26B are electrically connected in a region not shown.

[0063] In the epitaxial layer 21 in the element forming region, a p - A p-type semiconductor region 27 is formed. - The type semiconductor region 27 is called a body region, and is a region in which the channel region (inversion layer) of the power MOSFET is formed. - The upper portion of the p-type semiconductor region 27 is - A p-type semiconductor region 28 having a higher impurity concentration than the n-type semiconductor region 27 is formed. +The p-type semiconductor region 28 constitutes a punch-through stopper layer of the power MOSFET, while the n-type semiconductor region 29 is formed. + The type semiconductor region 29 constitutes the source region of the power MOSFET.

[0064] Two layers of silicon oxide film 30 and silicon oxide film 31 are formed on the upper part of the element formation region in which the power MOSFET is formed and on the upper part of the element isolation region in which the gate lead electrode 26B is formed. In the element formation region, the silicon oxide film 30, the silicon oxide film 31, the p-type semiconductor region 28 and the n-type semiconductor region 26B are formed. + The p-type semiconductor region 29 is penetrated - A contact hole 32 is formed in the element isolation region 27, and the contact hole 33 is formed in the element isolation region 27, penetrating the silicon oxide film 30 and the silicon oxide film 31 and reaching the gate extraction electrode 26B.

[0065] A source electrode 40 and a gate electrode 41 are formed on the silicon oxide film 31 including the insides of the contact holes 32 and 33. The source electrode 40 formed in the element formation region is electrically connected to the source region of the power MOSFET through the contact hole 32. A source terminal ST and a gate electrode 41 are formed on the bottom of the contact hole 32. - For making ohmic contact with the p-type semiconductor region 27 + A type semiconductor region 35 is formed in the element isolation region. A gate electrode 41 formed in the element isolation region is connected to the lower gate electrode (polycrystalline silicon film 26A) of the power MOSFET via a gate extraction electrode 26B in the lower part of the contact hole 33.

[0066] A surface protective film 42 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the source electrode 40 and the gate electrode 41. A source terminal ST is formed by removing a part of the surface protective film 42 to expose the source electrode 40, and a gate terminal GT is formed by removing another part of the surface protective film to expose the gate electrode 41. Although not shown in FIG. 7, a Kelvin terminal is also formed.

[0067] In this manner, the gate terminal GT, the Kelvin terminal (KT), and the source terminal ST are formed on the main surface of the semiconductor chip CHP.

[0068] <Features of the embodiment> Next, features of this embodiment will be described.

[0069] A feature of this embodiment is that, for example, as shown in Fig. 6, the source terminal lead SL is disposed between the gate terminal lead GL and the Kelvin terminal lead KL in a plan view. This allows the source terminal lead SL to be disposed in the center of the side S1 corresponding to the arrangement position of the source terminal ST, thereby preventing the wire W3 connecting the source terminal ST and the source terminal lead SL from bending. That is, according to the feature of this embodiment, the wire W3 connecting the source terminal ST and the source terminal lead SL can be configured in a straight shape extending in the y direction perpendicular to the x direction in which the side S1 extends. In other words, according to the feature of this embodiment, each of the multiple wires W3 can be configured in a straight shape extending only in the y direction perpendicular to the x direction.

[0070] As a result, according to this embodiment, since the multiple wires W3 through which a large current of about 300 A flows are not bent, it is possible to suppress non-negligible performance degradation, typified by an increase in on-resistance and an increase in parasitic inductance, caused by bending of the wires W3. In other words, according to this embodiment, the source terminal ST and the source terminal lead SL can be connected with the wires W3 of the shortest length, thereby improving the performance of the semiconductor device 10.

[0071] As explained in the section "<<Reason for arranging the Kelvin terminal lead next to the gate terminal lead>>", in order to make the voltage V1 between the gate terminal lead GL and the Kelvin terminal lead KL approximately equal to the voltage VGS, it is desirable that the parasitic resistance between the gate terminal lead GL and the Kelvin terminal lead KL is small. For this reason, the configuration in which the Kelvin terminal lead KL is arranged next to the gate terminal lead GL has been adopted.

[0072] In this regard, the circuit for detecting the voltage V1 using the gate terminal lead GL and the Kelvin terminal lead KL is not a circuit for passing a current but a sense circuit for detecting a voltage. This means that even if some resistance is added to the sense circuit, a large current does not flow, and therefore the present inventor considered that the effect of the voltage drop on the detection of the voltage V1 would be small. In other words, the present inventor concluded that increasing the distance between the gate terminal lead GL and the Kelvin terminal lead KL would not have a large effect on the detection of the voltage V1. Rather, the present inventor considered that in a semiconductor device 10 used for applications in which a large current of about 300 A flows, the increase in on-resistance and parasitic inductance caused by bending of the wire W3 through which the large current flows would have a greater effect on the degradation of the performance of the semiconductor device 10.

[0073] Considering the above, the present inventor has come to adopt a configuration characteristic of this embodiment in which "the source terminal lead SL is disposed between the gate terminal lead GL and the Kelvin terminal lead KL in a plan view," instead of the configuration in which the gate terminal lead GL and the Kelvin terminal lead KL are disposed adjacent to each other. As a result, this embodiment makes it possible to suppress non-negligible performance degradation, typified by an increase in on-resistance and an increase in parasitic inductance, caused by bending of the wire W3, and thereby obtains a remarkable effect of improving the performance of the semiconductor device 10.

[0074] <<Superior conception of terminals>> In this embodiment, a power MOSFET is taken as an example of the switching element Q1 formed in the semiconductor chip CHP. In this case, a gate terminal GT, a Kelvin terminal KT, and a source terminal ST are formed on the surface of the semiconductor chip CHP.

[0075] However, the technical idea of ​​this embodiment is not limited to the embodiment in which the switching element Q1 is configured from a power MOSFET, but can also be applied to the embodiment in which the switching element Q1 is configured from an IGBT. In this case, the gate terminal GT, the Kelvin terminal KT, and the emitter terminal are formed on the surface of the semiconductor chip CHP.

[0076] The Kelvin terminal KT is a terminal for detecting a voltage, and a terminal for detecting a voltage is called a "sense terminal," so the Kelvin terminal KT is one aspect of a "sense terminal." The source terminal ST and the emitter terminal are terminals for passing a current, and a terminal intended to pass a current is called a "force terminal," so the source terminal ST and the emitter terminal are one aspect of a "force terminal."

[0077] Furthermore, as will be explained in the modified examples described later, considering that each wire (bonding wire) W1 to W3 may be replaced with a "ribbon" or a "clip," the "wire," "ribbon," and "clip" are aspects of the connecting member.

[0078] Taking the above into consideration, the terms can be categorized into higher concepts as follows: (1) Gate terminal GT (2) Kelvin terminal KT → "sense terminal" (3) Source terminal ST and emitter terminal → "Force terminal" (4) Gate terminal lead GL (5) Kelvin terminal lead KL → "Sense terminal lead" (6) Source terminal lead SL (emitter terminal lead) → "Force terminal lead" (7) Wire W1 → "Gate terminal connection member" (8) Wire W2 → "Sense terminal connection material" (9) Wire W3 (ribbon, clip) → "Connection material for force terminal"

[0079] Considering the broader conceptualization of such terms, a feature of this embodiment is that the "force terminal lead" is disposed between the gate terminal lead GL and the "sense terminal lead" in a plan view. This allows the "force terminal lead" to be disposed in the center of the side corresponding to the arrangement position of the "force terminal", thereby preventing the "force terminal connecting member" connecting the "force terminal" and the "force terminal lead" from bending. In other words, according to the feature of this embodiment, the "force terminal connecting member" connecting the "force terminal" and the "force terminal lead" can be configured to have a straight shape. In other words, according to the feature of this embodiment, the "force terminal connecting member" can be configured to have a straight shape.

[0080] <Variation 1> FIG. 8 is a diagram showing a schematic configuration of a semiconductor device 10A in the present first modification.

[0081] As shown in Fig. 8, in the semiconductor device 10A in the present modified example 1, the position of the gate terminal GT and the position of the Kelvin terminal KT formed on the semiconductor chip CHP are swapped with respect to the semiconductor device 10 shown in Fig. 6. As a result, in the semiconductor device 10A, the positions of the gate terminal lead GL connected to the gate terminal GT via the wire W1 and the Kelvin terminal lead KL connected to the Kelvin terminal KT via the wire W2 are also swapped.

[0082] As described above, by adopting the feature of the present embodiment that "the source terminal lead SL is disposed between the gate terminal lead GL and the Kelvin terminal lead KL in a plan view," a mounting configuration that is symmetrical with respect to the gate terminal lead GL and the Kelvin terminal lead KL is realized. As a result, by adopting the feature of the present embodiment, not only the configuration of the semiconductor device 10 shown in Fig. 6 but also the configuration of the semiconductor device 10A shown in Fig. 8 can be realized. For this reason, the technical idea of ​​the present embodiment is also useful in that it can increase the variations in mounting layout.

[0083] <Variation 2> FIG. 9 is a diagram showing a schematic configuration of a semiconductor device 10B according to the second modification.

[0084] 9, by adopting the characteristic points of this embodiment, the source terminal lead SL can be disposed at the center of the side S1 corresponding to the position of the source terminal ST. Therefore, instead of the wire W3 shown in FIG. 6, a ribbon RBN made of aluminum (Al) can be used as a source terminal connecting member that connects the source terminal ST and the source terminal lead SL.

[0085] In this case, as shown in FIG. 9, the ribbon RBN is joined to the source terminal ST at a plurality of points. For example, the ribbon RBN and the source terminal ST are connected at the junction points P4 and P5. That is, the number of junction points between the wire W1 and the gate terminal GT is one, and the number of junction points between the wire W2 and the Kelvin terminal KT is one, whereas the number of junction points between the ribbon RBN and the source terminal ST is two. That is, as in the above embodiment, by increasing the number of junction points between the source terminal ST and the ribbon RBN, the on-resistance on the current path between the source terminal ST and the source terminal lead SL can be reduced. Here, the width of the ribbon RBN used in this modified example 2 is larger than the width of each of the wires W1 to W3 used in the above embodiment. And, as shown in FIG. 9, not only are the source terminal ST and the source terminal lead SL electrically connected to each other through one ribbon RBN, but also a large current (300A) can be passed between the source terminal ST and the source terminal lead SL by joining the ribbon RBN to the source terminal ST at a plurality of points. In addition, in the present modified example 2, as shown in Fig. 9, the number of junction points between the ribbon RBN and the source terminal ST is two, but it may be more than two. Also, the ribbon RBN and the source terminal lead SL are connected at a junction point P6. That is, the number of junction points between the ribbon RBN and the source terminal lead SL is one.

[0086] <Modification 3> FIG. 10 is a diagram showing a schematic configuration of a semiconductor device 10C according to the third modification.

[0087] In Fig. 10, when the characteristic point of this embodiment is adopted, the source terminal lead SL can be disposed at the center of the side S1 corresponding to the arrangement position of the source terminal ST. Therefore, as a source terminal connecting member that connects the source terminal ST and the source terminal lead SL, not only the ribbon RBN shown in Fig. 9 can be used instead of the wire W3 shown in Fig. 6, but also ribbons RBN1 and RBN2 can be used as shown in Fig. 10.

[0088] <Modification 4> FIG. 11 is a diagram showing a schematic configuration of a semiconductor device 10D according to the fourth modification.

[0089] 11, by adopting the feature of this embodiment, the source terminal lead SL can be disposed at the center of the side S1 corresponding to the position of the source terminal ST. Therefore, instead of the wire W3 shown in FIG. 6, the wide wire W4 shown in FIG. 11 can be used as a source terminal connecting member that connects the source terminal ST and the source terminal lead SL.

[0090] <Variation 5> FIG. 12 is a diagram showing a schematic configuration of a semiconductor device 10E according to the fifth modification.

[0091] 12, by adopting the feature of this embodiment, the source terminal lead SL can be disposed at the center of the side S1 corresponding to the position of the source terminal ST. Therefore, instead of the wire W3 shown in FIG. 6, the clip CLP shown in FIG. 12 can be used as a source terminal connecting member that connects the source terminal ST and the source terminal lead SL.

[0092] In this case, as shown in FIG. 12, the clip CLP is joined to the source terminal ST at one point. For example, the clip CLP and the source terminal ST are connected at a junction point P7. That is, the number of junction points between the wire W1 and the gate terminal GT is one, the number of junction points between the wire W2 and the Kelvin terminal KT is one, and the number of junction points between the clip CLP and the source terminal ST is also one. Here, the width of the clip CLP used in this modification 5 is larger than the width of each of the wires W1 to W3 used in the above embodiment. Also, the thickness of the clip CLP used in this modification 5 is larger than the thickness of the ribbon RBN used in the above modification 2. Therefore, unlike the above embodiment and modification 2, by using the clip CLP having the above width and thickness and made of copper (Cu), it is possible to reduce the on-resistance on the current path between the source terminal ST and the source terminal lead SL without increasing the number of junction points between the source terminal ST and the clip CLP. The clip CLP and the source terminal lead SL are connected at a junction point P8. That is, the number of junction points between the clip CLP and the source terminal lead SL is one.

[0093] <Additional advantages of the embodiment> For example, in a "TO package" in which the gate terminal lead GL and the Kelvin terminal lead KL are arranged adjacent to each other, as a configuration example in which the wire W3 connecting the source terminal ST and the source terminal lead SL is not bent, a configuration in which the unbent straight wire W3 is arranged obliquely is also conceivable. If this technology is called the related technology, it will be described that the technical idea of ​​this embodiment has an advantage over the related technology.

[0094] Fig. 13 is a diagram showing a schematic arrangement of wires W3 that realizes the technical idea of ​​this embodiment. In Fig. 13, the wires W3 are configured in a linear shape extending only in the y direction, and the wire angle θ indicating the inclination of the wires W3 from the y direction is 0°. In this case, for example, the area of ​​the semiconductor chip required to arrange six wires W3 is represented by an occupied area of ​​200A.

[0095] Next, Fig. 14 is a diagram showing a schematic arrangement of wires W3 that realizes an example of the related art. In Fig. 14, the wires W3 are configured in a linear shape tilted from the y direction, and the wire angle θ indicating the tilt of the wires W3 from the y direction is 12°. In this case, for example, the area of ​​the semiconductor chip required to arrange six wires W3 is represented by an occupied area 200B.

[0096] Next, Fig. 15 is a diagram showing a schematic arrangement of wires W3 embodying another example of the related art. In Fig. 15, the wires W3 are configured in a linear shape tilted from the y direction, and the wire angle θ indicating the tilt of the wires W3 from the y direction is 45°. In this case, for example, the area of ​​the semiconductor chip required to arrange six wires W3 is represented by an occupied area 200C.

[0097] As can be seen from FIG. 13 to FIG. 15, the area of ​​the semiconductor chip required to arrange six wires W3 is occupying area 200A<occupying area 200B<occupying area 200C. In other words, when the technical idea of ​​this embodiment is embodied to configure the wires W3 in a straight shape extending only in the y direction, it is possible to reduce the area occupied by the wires W3 in the semiconductor chip compared to when the related technology is embodied to configure the wires W3 in a straight shape inclined from the y direction. This means that, according to this embodiment, when the number of wires W3 used is the same, the size of the semiconductor chip can be shrunk more than in the related technology. In this way, the technical idea of ​​this embodiment is excellent in that it can not only reduce the on-resistance but also reduce the size of the semiconductor chip.

[0098] Furthermore, the superiority of the technical idea of ​​this embodiment over the related art will be explained using another expression. Fig. 16 is a diagram showing a schematic configuration of arranging wires W3 that embody the technical idea of ​​this embodiment when the occupied area of ​​a semiconductor chip is area 200. As shown in Fig. 16, when wires W3 configured with a linear shape extending only in the y direction are used, seven wires W3 can be arranged in area 200.

[0099] 17 is a diagram showing a schematic configuration for arranging wires W3 embodying the related art when the occupied area of ​​a semiconductor chip is taken as area 200. As shown in FIG. 17, when wires W3 configured in a linear shape inclined from the y direction are used, it is understood that only six wires W3 can be arranged in the area 200.

[0100] In this way, it can be seen that, when the technical idea of ​​this embodiment is applied to the shape of the wires W3, the number of wires W3 that can be arranged in the same semiconductor chip area 200 can be increased compared to the related art. This means that, when using a semiconductor chip of the same size, this embodiment can increase the number of wires W3 that can be arranged on the semiconductor chip compared to the related art, and as a result, the on-resistance can be reduced. Therefore, from this viewpoint as well, it can be said that the technical idea of ​​this embodiment is superior.

[0101] <Application Examples> Next, an application example of the technical idea of ​​this embodiment will be described. Specifically, it will be described that the layout of the multiple leads in this embodiment is applicable not only to semiconductor devices including power MOSFETs, but also to semiconductor devices including bidirectional thyristors. In other words, it will be described that the ingenuity regarding the layout of the multiple leads contributes to the commonality of semiconductor devices including power MOSFETs and semiconductor devices including bidirectional thyristors.

[0102] Fig. 18 is a circuit diagram of a bidirectional thyristor, and Fig. 19 is a schematic diagram showing the structure of a bidirectional thyristor.

[0103] A bidirectional thyristor is a type of power semiconductor element, and is a semiconductor element that can control bidirectional current with one gate electrode. In principle, a bidirectional thyristor is configured to control bidirectional current by connecting a thyristor 300A and a thyristor 300B that can control a current in one direction in inverse parallel, as shown in Figs. 18 and 19. Bidirectional thyristors are widely used to control AC power supplies because they can pass current in both directions. As shown in Figs. 18 and 19, a bidirectional thyristor has three terminals, a main terminal MT1, a main terminal MT2, and a gate terminal GT. By applying a control signal to the gate terminal GT, not only can a current be passed from the main terminal MT1 to the main terminal MT2, but also, conversely, a current can be passed from the main terminal MT2 to the main terminal MT1. The main terminal MT1 is also called a first anode terminal, and the main terminal MT2 is also called a second anode terminal.

[0104] FIG. 20 is a diagram showing a schematic configuration of a semiconductor device 50A including a bidirectional thyristor. As shown in FIG. 20, a semiconductor chip CHP1 on which a bidirectional thyristor is formed is mounted on a die pad DP that serves as a main terminal MT2. A main terminal MT1 and a gate terminal GT are formed on the surface of the semiconductor chip CHP1. A gate terminal lead GL and a main terminal lead MTL are arranged along one side of the sealing body MR. Here, the gate terminal GT and the gate terminal lead GL are electrically connected by a wire W1, while the main terminal MT1 and the main terminal lead MTL are electrically connected by a wire W5. Here, as shown in FIG. 20, each of the multiple wires W5 is joined to the main terminal MT1 at multiple points. For example, each wire W5 and the main terminal MT1 are connected at a junction point P1 and a junction point P2. That is, the number of junction points between each wire W5 and the main terminal MT1 is two. Meanwhile, each wire W5 and the main terminal lead MTL are connected at a junction point P3. That is, the number of junction points between each wire W5 and the main terminal lead MTL is 1. In this manner, the semiconductor device 50A is configured.

[0105] In contrast, FIG. 21 is a diagram that illustrates a schematic configuration of a semiconductor device 50B including a power MOSFET. As illustrated in FIG. 21, a semiconductor chip CHP2 on which a power MOSFET is formed is mounted on a die pad DP that serves as a drain. A source terminal ST and a gate terminal GT are formed on the surface of the semiconductor chip CHP2. A gate terminal lead GL and a source terminal lead SL are disposed along one side of the sealing body MR. Here, the gate terminal GT and the gate terminal lead GL are electrically connected by a wire W1, while the source terminal ST and the source terminal lead SL are electrically connected by a wire W3. Here, as illustrated in FIG. 21, each of the multiple wires W3 is joined to the source terminal ST at multiple points. For example, each wire W3 and the source terminal ST1 are connected at a junction point P1 and a junction point P2. That is, the number of junction points between each wire W3 and the source terminal ST1 is two. Meanwhile, each wire W3 and the source terminal lead SL are connected at a junction point P3. That is, the number of junction points between each wire W3 and the source terminal lead SL is one. In this manner, the semiconductor device 50B is constructed.

[0106] As can be seen from FIG. 20 and FIG. 21, the arrangement position of the gate terminal GT of the semiconductor chip CHP1 in which the bidirectional thyristor is formed is reversed to the arrangement position of the gate terminal GT of the semiconductor chip CHP2 in which the power MOSFET is formed. As a result, the arrangement of the gate terminal lead GL and the main terminal lead MTL in the semiconductor device 50A is different from the arrangement of the gate terminal lead GL and the source terminal lead SL in the semiconductor device 50B. Therefore, it is found that it is difficult to standardize the layout of the multiple leads in the current semiconductor device 50A and the semiconductor device 50B. In this regard, by applying the ingenuity regarding the layout of the multiple leads in this embodiment, it is possible to standardize the layout of the multiple leads in the semiconductor device 50A including the bidirectional thyristor and the semiconductor device 50B including the power MOSFET. This point will be described below.

[0107] First, FIG. 6 shows a semiconductor device 10 in which a power MOSFET is formed and to which the layout of a plurality of leads according to this embodiment is applied.

[0108] On the other hand, FIG. 22 shows a semiconductor device 60A having a bidirectional thyristor formed therein, to which the layout of a plurality of leads according to this embodiment is applied.

[0109] As can be seen by comparing FIG. 6 with FIG. 22, by applying the arrangement layout of multiple leads in this embodiment, it is possible to realize both the semiconductor device 10 including a power MOSFET and the semiconductor device 60A including a bidirectional thyristor.

[0110] In particular, the multifunction terminal lead FL shown in FIG. 22 is configured to be electrically connected to the main terminal MT1 via the wire W5A in the semiconductor device 60A including a bidirectional thyristor. On the other hand, in the semiconductor device 10 including a power MOSFET, the multifunction terminal lead FL functions as a Kelvin terminal lead KL connected to the Kelvin terminal KT via the wire W2. As a result, by applying the layout of the multiple leads in this embodiment, both the semiconductor device 10 including a power MOSFET and the semiconductor device 60A including a bidirectional thyristor are realized. In other words, according to this embodiment, it is possible to standardize the layout of the multiple leads in both the semiconductor device 10 including a power MOSFET and the semiconductor device 60A including a bidirectional thyristor by skillfully using the multifunction terminal lead FL. Therefore, it can be said that the technical idea of ​​this embodiment is excellent in versatility in that it is possible to standardize the layout of the multiple leads in semiconductor devices having different functions.

[0111] 22, the wire W5A is joined to the main terminal MT1 at multiple points. For example, the wire W5A and the main terminal MT1 are connected at a junction point P1 and a junction point P2. That is, the number of junction points between the wire W5A and the main terminal MT1 is two. On the other hand, the wire W5A and the multifunction terminal lead FL are connected at a junction point P3A. That is, the number of junction points between the wire W5A and the multifunction terminal lead FL is one.

[0112] 22, the wire W5B is joined to the main terminal MT1 at multiple points. For example, the wire W5B and the main terminal MT1 are connected to each other at a junction point P1 and a junction point P2. That is, the number of junction points between the wire W5B and the main terminal MT1 is two. On the other hand, the wire W5B and the main terminal lead MTL are connected to each other at a junction point P3B. That is, the number of junction points between the wire W5B and the main terminal lead MTL is one.

[0113] 22 shows a semiconductor device 60A in which a bidirectional thyristor is formed and in which the layout of a plurality of leads in this embodiment is applied, but the present invention is not limited to this and may be configured as, for example, a semiconductor device 60B shown in Fig. 23. In this case, since the wire W5B included in the semiconductor device 60B does not have a bent portion, it is considered that the on-resistance can be reduced more than that of the semiconductor device 60A.

[0114] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0115] CHP Semiconductor Chip CHP1 Semiconductor Chip CHP2 Semiconductor Chip CLP Clip DP die pad KT Kelvin terminal (sense terminal) KL Kelvin terminal lead (sense terminal lead) FL Multi-function terminal lead GT Gate terminal GL Gate terminal lead P1 junction P2 junction P3 junction P3A junction P3B junction P4 junction P5 junction P6 junction P7 junction P8 junction RBN Ribbon RBN1 Ribbon RBN2 Ribbon ST Source terminal (force terminal) SL Source terminal lead (Force terminal lead) W1 Wire (bonding wire) W2 Wire (Bonding Wire) W3 Wire (bonding wire) W4 Wire (bonding wire) W5A Wire (Bonding Wire) W5B Wire (Bonding Wire)

Claims

1. A die pad; a semiconductor chip having a front surface and a back surface opposite to the front surface, the back surface being mounted on the die pad such that the back surface faces the die pad; a plurality of leads arranged along a first side of the semiconductor chip in a plan view; a plurality of connection members electrically connecting the semiconductor chip and the plurality of leads; Including, A power MOSFET is formed on the semiconductor chip, The semiconductor chip comprises: a gate terminal formed on the surface and electrically connected to a gate electrode of the power MOSFET; a Kelvin terminal formed on the surface and electrically connected to a source region of the power MOSFET; a source terminal formed on the surface, electrically connected to the source region of the power MOSFET, and including a portion located between the gate terminal and the Kelvin terminal in a plan view; a drain electrode formed on the back surface and electrically connected to a drain of the power MOSFET; having The types of terminals formed on the surface of the semiconductor chip are only three types, namely, the gate terminal, the Kelvin terminal, and the source terminal; The plurality of leads are disposed only on the first side, The plurality of leads include a gate terminal lead electrically connected to the gate terminal via a gate terminal connection member among the plurality of connection members; a Kelvin terminal lead electrically connected to the Kelvin terminal via a Kelvin terminal connection member among the plurality of connection members; a source terminal lead located between the gate terminal lead and the Kelvin terminal lead in a plan view and electrically connected to the source terminal via a source terminal connection member among the plurality of connection members; The semiconductor device has

2. 2. The semiconductor device according to claim 1, The source terminal connection member is configured to have a linear shape extending in a second direction perpendicular to a first direction in which the first side extends.

3. 2. The semiconductor device according to claim 1, The source terminal connection member is configured to have a shape that extends only in a second direction perpendicular to a first direction in which the first side extends.

4. 4. The semiconductor device according to claim 3, The semiconductor device, wherein the source terminal connection member is a wire made of gold (Au) or copper (Cu).

5. 5. The semiconductor device according to claim 4, the number of joint points between the gate terminal connection member and the gate terminal is one; The number of joint points between the Kelvin terminal connection member and the Kelvin terminal is one, The number of junction points between the source terminal connection member and the source terminal is two or more.

6. 6. The semiconductor device according to claim 5, A semiconductor device, wherein the number of the source terminal connecting members is greater than the number of the gate terminal connecting members and the number of the Kelvin terminal connecting members.

7. 7. The semiconductor device according to claim 6, The semiconductor device is configured to be capable of passing a current of 300 A.

8. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the source terminal connection member is a ribbon made of aluminum (Al).

9. 9. The semiconductor device according to claim 8, the number of joint points between the gate terminal connection member and the gate terminal is one; The number of joint points between the Kelvin terminal connection member and the Kelvin terminal is one, The number of junction points between the source terminal connection member and the source terminal is two or more.

10. 10. The semiconductor device according to claim 9, The semiconductor device is configured to be capable of passing a current of 300 A.

11. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the source terminal connecting member is a clip made of copper (Cu).

12. 12. The semiconductor device according to claim 11, the number of joint points between the gate terminal connection member and the gate terminal is one; The number of joint points between the Kelvin terminal connection member and the Kelvin terminal is one, The semiconductor device, wherein the number of junction points between the source terminal connection member and the source terminal is one.

13. 13. The semiconductor device according to claim 12, The semiconductor device is configured to be capable of passing a current of 300 A.

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