Semiconductor Device

Abstract

Provided is a semiconductor device which can hold analog data. Two holding circuits, two bootstrap circuits, and one source follower circuit are constituted by using two capacitive elements and four transistors. Storage nodes are provided to the two holding circuits, respectively. Data potential is written in one storage node, and reference potential is stored in the other storage node. During data reading, the potential of the one storage node is boosted at one bootstrap circuit, and the potential of the other storage node is boosted at the other bootstrap circuit. A potential difference between the two storage nodes is outputted by using the source follower circuit. By using the source follower circuit, output impedance can be reduced.

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, examples of the technical field of one embodiment of the present invention disclosed in this specification more specifically include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof. [Background technology]

[0003] In recent years, electronic components such as central processing units (CPUs), graphics processing units (GPUs), storage devices, and sensors are used in a variety of electronic devices, including personal computers, smartphones, and digital cameras. These electronic components have been improved in various aspects, including miniaturization and low power consumption.

[0004] In particular, in recent years, the amount of data handled by electronic devices has been increasing, and there is a demand for memory devices with large storage capacity. For this reason, the development of memory devices that hold multi-value data or analog data in one memory element is being considered. Patent Documents 1 and 2 disclose semiconductor devices that enable writing and reading of multi-value data. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2012-256400 A [Patent Document 2] JP 2014-199707 A Summary of the Invention [Problem to be solved by the invention]

[0006] There is a demand for a semiconductor device that can hold analog data for a long period of time and accurately read the held analog data.

[0007] In transistors that contain silicon in the semiconductor layer in which the channel is formed (also called "Si transistors"), the element size is being miniaturized as process rules are reduced. In addition, as the element size is reduced, the gate insulating film is also becoming thinner, which causes a problem of leakage current through the gate insulating film.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device capable of holding analog data. Another object of one embodiment of the present invention is to provide a semiconductor device capable of accurately reading held analog data. Another object of one embodiment of the present invention is to provide a semiconductor device with a reduced occupation area. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device with large storage capacity. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and other problems. One embodiment of the present invention does not need to solve all of the problems listed above and other problems. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device including two holding circuits, two bootstrap circuits, and one source follower circuit using four transistors and two capacitors. A storage node is provided in each of the two holding circuits, and a data potential is written to one storage node and a reference potential is written to the other storage node. When reading data, the potential of one storage node is boosted by one bootstrap circuit, and the potential of the other storage node is boosted by the other bootstrap circuit. A potential difference between the two storage nodes is output using a source follower circuit. By using a source follower circuit, output impedance can be reduced.

[0011] Another embodiment of the present invention is a semiconductor device having first to fifth circuits, in which the first circuit has a function of holding a first potential, the second circuit has a function of boosting the first potential, the third circuit has a function of holding a second potential, the fourth circuit has a function of boosting the second potential, and the fifth circuit has a function of outputting a third potential that corresponds to a potential difference between the boosted first potential and the boosted second potential.

[0012] The above semiconductor device may include, for example, first to fourth transistors, a first capacitive element, and a second capacitive element. Also, the first circuit may include a first transistor and a first capacitive element, the second circuit may include a second transistor and a first capacitive element, the third circuit may include a third transistor and a second capacitive element, the fourth circuit may include a fourth transistor and a second capacitive element, and the fifth circuit may include a second transistor and a fourth transistor.

[0013] Another embodiment of the present invention includes first to fourth transistors, a first capacitor, and a second capacitor, in which one of a source or a drain of the first transistor is electrically connected to a first terminal, the other of the source or the drain of the first transistor is electrically connected to a gate of a second transistor, the gate of the first transistor is electrically connected to a second terminal, one of a source or a drain of a third transistor is electrically connected to a third terminal, the other of the source or the drain of the third transistor is electrically connected to a gate of a fourth transistor, the gate of the third transistor is electrically connected to a fourth terminal, and the source of the second transistor is electrically connected to a fourth terminal. one of the source or drain of the second transistor is electrically connected to a fifth terminal, the other of the source or drain of the second transistor is electrically connected to a seventh terminal, one of the source or drain of the fourth transistor is electrically connected to a sixth terminal and the other of the source or drain of the fourth transistor is electrically connected to the seventh terminal, one electrode of the first capacitance element is electrically connected to a gate of the second transistor and the other electrode of the first capacitance element is electrically connected to the seventh terminal, one electrode of the second capacitance element is electrically connected to a gate of the fourth transistor, and the other electrode of the second capacitance element is electrically connected to the seventh terminal.

[0014] The third terminal and the sixth terminal may be electrically connected. The first transistor and the third transistor preferably include an oxide semiconductor in a semiconductor layer in which a channel is formed. In addition, the second transistor and the fourth transistor preferably include an oxide semiconductor in a semiconductor layer in which a channel is formed. The oxide semiconductor preferably includes at least one of indium and zinc. Effect of the Invention

[0015] According to one embodiment of the present invention, a semiconductor device capable of holding analog data can be provided. Alternatively, a semiconductor device capable of accurately reading held analog data can be provided. Alternatively, a semiconductor device with a reduced occupation area can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. Alternatively, a semiconductor device with a large storage capacity can be provided. Alternatively, a semiconductor device with high reliability can be provided. Alternatively, a novel semiconductor device can be provided.

[0016] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description of the specification or drawings, and can be appropriately extracted from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above. [Brief description of the drawings]

[0017] 1A and 1B are circuit diagrams of a semiconductor device according to one embodiment of the present invention. 2A and 2B are circuit diagrams of a semiconductor device according to one embodiment of the present invention. 3A and 3B are circuit diagrams of a semiconductor device according to one embodiment of the present invention. 4A and 4B are diagrams showing circuit symbols for transistors. 5A and 5B are diagrams illustrating a source follower circuit. FIG. 6 is a timing chart illustrating an example of the operation of the semiconductor device. 7A and 7B are diagrams illustrating an example of the operation of the semiconductor device. 8A and 8B are diagrams illustrating an example of the operation of the semiconductor device. FIG. 9 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. Fig. 10A is a block diagram illustrating a configuration example of a semiconductor device, and Fig. 10B is a perspective view of the semiconductor device. FIG. 11 is a block diagram illustrating the CPU. 12A and 12B are perspective views of a semiconductor device. 13A and 13B are perspective views of the semiconductor device. 14A and 14B are perspective views of a semiconductor device. 15A and 15B are diagrams for explaining an example of the configuration of a neural network. FIG. 16 is a diagram showing an example of the structure of a semiconductor device. 17A to 17C are diagrams showing configuration examples of transistors. FIG. 18A is a diagram for explaining the classification of IGZO crystal structures, FIG. 18B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 18C is a diagram for explaining the ultrafine electron beam diffraction pattern of crystalline IGZO. FIG. 19A is a perspective view showing an example of a semiconductor wafer, FIG. 19B is a perspective view showing an example of a chip, and FIGS. 19C and 19D are perspective views showing an example of an electronic component. 20A to 20J are diagrams illustrating an example of an electronic device. 21A to 21E are diagrams illustrating an example of an electronic device. 22A to 22C are diagrams illustrating an example of an electronic device. 23A and 23B are diagrams according to an embodiment. FIG. 24 is a diagram according to an embodiment. FIG. 25 is a diagram according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the embodiment and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0019] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, an electronic device, etc. are themselves semiconductor devices and may have a semiconductor device.

[0020] In addition, when it is stated in this specification that X and Y are connected, the following cases are also disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is also disclosed in the figure or text. X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0021] As an example of a case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitive element, an inductor, a resistive element, a diode, a display device, a light-emitting device, a load, etc.) that enable electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling its on and off state. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controls whether or not a current flows.

[0022] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0023] In addition, when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without having another element or circuit between them).

[0024] Also, for example, it can be expressed as "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished to determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0025] In addition, even when components that are independent on a circuit diagram are shown as being electrically connected to each other, one component may have the functions of multiple components. For example, when a part of a wiring also functions as an electrode, one conductive film has both the functions of a wiring and an electrode. Therefore, the term "electrical connection" in this specification also includes such a case where one conductive film has the functions of multiple components.

[0026] In addition, in this specification, the term "resistance element" may be, for example, a circuit element or wiring having a resistance value higher than 0Ω. Therefore, in this specification, the term "resistance element" includes wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance", "load", and "region having a resistance value", and conversely, the terms "resistance", "load", and "region having a resistance value" can be replaced with terms such as "resistance element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0027] In addition, in this specification, the term "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification, the term "capacitive element" refers not only to a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also to a parasitic capacitance appearing between wirings, a gate capacitance appearing between one of the source or drain of a transistor and the gate, and the like. In addition, the terms "capacitive element", "parasitic capacitance", "gate capacitance", and the like can be rephrased as "capacitance", and conversely, the term "capacitance" can be rephrased as "capacitive element", "parasitic capacitance", "gate capacitance", and the like. In addition, the term "pair of electrodes" in "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", and the like. The value of the electrostatic capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 μF or less.

[0028] In addition, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals becomes a source and the other becomes a drain depending on the conductivity type (n-channel type, p-channel type) of the transistor and the level of the potential applied to the three terminals of the transistor. For this reason, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or the first electrode, or the first terminal) and "the other of the source or drain" (or the second electrode, or the second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the above-mentioned three terminals. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as a first gate, a second gate, a third gate, and so on.

[0029] In this specification, the term "on-state current" may refer to a current that flows between a source and a drain when a transistor is on, and the term "off-state current" may refer to a current that flows between a source and a drain when a transistor is off.

[0030] In addition, in this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc., depending on the circuit configuration and / or device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0031] In addition, in this specification and the like, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to a potential difference from a reference potential, and if the reference potential is the ground potential (earth potential), for example, "voltage" can be interchanged as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also change.

[0032] In this specification and the like, high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than low power supply potential VSS (hereinafter also simply referred to as "VSS"). Also, VSS refers to a power supply potential that is lower than VDD. Also, ground potential (hereinafter also simply referred to as "GND") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0033] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). In addition, the "direction of current" in wiring, etc. is the direction in which positive carriers move, and is described as a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive and negative (or current direction) of the current, a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A" etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0034] In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0035] In addition, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] In addition, the positional relationship of the components changes appropriately depending on the direction in which each component is depicted. Therefore, it is not limited to the words and phrases described in the specification, etc., and can be appropriately rephrased depending on the situation. For example, in this specification, etc., words and phrases indicating the arrangement, such as "above" and "below," may be used for convenience in order to explain the positional relationship of the components with reference to the drawings. Therefore, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing by 180 degrees. Also, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the left surface (or right surface) of the conductor" by rotating the orientation of the drawing by 90 degrees.

[0037] Similarly, in this specification and the like, the term "overlap" does not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state where "electrode B is formed on insulating layer A", but does not exclude the state where "electrode B is formed under insulating layer A" or "electrode B is formed on the right (or left) side of insulating layer A", etc.

[0038] In addition, in this specification, the terms "adjacent" and "close to" do not limit components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0039] In addition, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulating body".

[0040] In addition, the terms "electrode", "wiring", "terminal" and the like in this specification do not limit the functions of these components. For example, "electrode" may be used as a part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where a plurality of "electrodes" and "wiring" are integrally formed. Furthermore, for example, "terminal" may be used as a part of "wiring" and "electrode", and vice versa. Furthermore, the term "terminal" includes cases where a plurality of "electrodes", "wiring", "terminals", and the like are integrally formed. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", and for example, a "terminal" can be a part of a "wiring" or "electrode". Furthermore, the terms "electrode", "wiring", "terminal" and the like may be replaced with terms such as "region" depending on the circumstances.

[0041] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line". For example, the term "wiring" may be changed to the term "power line". The opposite is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring". The term "power line" may be changed to the term "signal line". The opposite is also true, and terms such as "signal line" may be changed to the term "power line". The term "potential" applied to the wiring may be changed to the term "signal" depending on the circumstances. The opposite is also true, and terms such as "signal" may be changed to the term "potential".

[0042] In this specification and the like, the impurity of a semiconductor refers to, for example, other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The inclusion of an impurity may cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, the impurity that changes the characteristics of the semiconductor may be, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and transition metals other than the main component, and in particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. Specifically, when the semiconductor is silicon, the impurity that changes the characteristics of the semiconductor may be, for example, oxygen, and Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements, and the like.

[0043] In this specification and the like, a switch refers to a device that has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has a function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0044] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits that combine these. When a transistor is used as a switch, the "conductive state (on state)" of the transistor refers to a state in which the source and drain of the transistor can be considered to be electrically short-circuited. Also, the "non-conductive state (off state)" of the transistor refers to a state in which the source and drain of the transistor can be considered to be electrically cut off. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0045] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical system) technology. The switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0046] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes the case of -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case of 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0047] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0048] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0049] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0050] In addition, the content (or a part of the content) described in one embodiment may be applied, combined, or replaced with at least one of another content (or a part of the content) described in that embodiment and the content (or a part of the content) described in one or more other embodiments.

[0051] The contents described in the embodiments refer to the contents described in each embodiment (or example) using various figures, or the contents described using text in the specification.

[0052] Furthermore, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with at least one figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0053] The embodiments described in this specification will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and those skilled in the art will easily understand that the form and details can be changed in various ways without departing from the spirit and scope of the invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, in order to make the drawings easier to understand, the description of some components may be omitted in perspective views or top views.

[0054] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately according to the situation.

[0055] In addition, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the size and aspect ratio are not necessarily limited. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include signal, voltage, or current variations due to noise, or signal, voltage, or current variations due to timing deviations.

[0056] In this specification and the like, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification reference numeral such as “_1”, “[n]”, “[m,n]”, etc. may be added to the reference numeral. For example, one of two wirings GL may be described as wiring GL[1] and the other as wiring GL[2].

[0057] (Embodiment 1) A semiconductor device 100 according to one embodiment of the present invention will be described with reference to the drawings.

[0058] <Configuration Example of Semiconductor Device 100> 1A shows a circuit diagram of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 can function as a memory circuit capable of holding analog data. The semiconductor device 100 can also function as a memory element capable of holding analog data. The semiconductor device 100 includes transistors Tr11, Tr12, Tr21, and Tr22, as well as capacitors Cb1 and Cb2.

[0059] The semiconductor device 100 also includes a holding circuit 110a, a holding circuit 110b, a bootstrap circuit 120a, a bootstrap circuit 120b, and a source follower circuit .

[0060] The holding circuit 110a includes a transistor Tr11 and a capacitance element Cb1, and the holding circuit 110b includes a transistor Tr21 and a capacitance element Cb2. The bootstrap circuit 120a includes a transistor Tr12 and a capacitance element Cb1, and the bootstrap circuit 120b includes a transistor Tr22 and a capacitance element Cb2. The source follower circuit 130 includes a transistor Tr12 and a transistor Tr22.

[0061] The gate of the transistor Tr11 is electrically connected to the terminal WW1, one of the source and the drain of the transistor Tr11 is electrically connected to the terminal IN1, and the other is electrically connected to the gate of the transistor Tr12. One of the source and the drain of the transistor Tr12 is electrically connected to the terminal PS1, and the other is electrically connected to the terminal OUT.

[0062] The gate of the transistor Tr21 is electrically connected to the terminal WW2, one of the source and the drain of the transistor Tr21 is electrically connected to the terminal IN2, and the other is electrically connected to the gate of the transistor Tr22. One of the source and the drain of the transistor Tr22 is electrically connected to the terminal OUT, and the other is electrically connected to the terminal PS2.

[0063] The capacitance element Cb1 has one electrode electrically connected to the gate of the transistor Tr12 and the other electrode electrically connected to the terminal OUT, and the capacitance element Cb2 has one electrode electrically connected to the terminal OUT and the other electrode electrically connected to the gate of the transistor Tr22.

[0064] A node where the other of the source or drain of transistor Tr11, the gate of transistor Tr12, and one of the electrodes constituting capacitance element Cb1 are electrically connected functions as node SN1. A node where the other of the source or drain of transistor Tr21, the gate of transistor Tr22, and the other of the electrodes constituting capacitance element Cb2 are electrically connected functions as node SN2. A node where the other of the electrodes constituting capacitance element Cb1, one of the electrodes constituting capacitance element Cb2, and the terminal OUT are electrically connected functions as node BN. Each of nodes SN1 and SN2 functions as a storage node.

[0065] The holding circuit 110a has a function of holding a potential (charge) written to the node SN1 via a transistor Tr11, and the holding circuit 110b has a function of holding a potential (charge) written to the node SN2 via a transistor Tr21.

[0066] Specifically, a potential that turns on transistor Tr11 is supplied to the gate of transistor Tr11, and charge is supplied to node SN1 via the source and drain of transistor Tr11 to set node SN1 to a predetermined potential. Then, a potential that turns off transistor Tr11 is supplied to the gate of transistor Tr11. By turning off transistor Tr11, the charge written to node SN1 is held.

[0067] Similarly, a potential that turns on transistor Tr21 is supplied to the gate of transistor Tr21, and charge is supplied to node SN2 via the source and drain of transistor Tr21 to set node SN2 to a predetermined potential. Then, a potential that turns off transistor Tr21 is supplied to the gate of transistor Tr21. By turning off transistor Tr21, the charge written to node SN2 is retained. Therefore, nodes SN1 and SN2 are also called "retention nodes." Moreover, transistors Tr11 and Tr21 are also called "write transistors."

[0068] For the semiconductor layers of the transistors Tr11, Tr12, Tr21, and Tr22, single crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, or the like can be used alone or in combination. For the semiconductor material, for example, silicon or germanium can be used. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0069] Note that the semiconductor layer used in the transistor may be a stack of a plurality of semiconductor layers. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for each of the semiconductor layers.

[0070] In particular, the transistors Tr11 and Tr21 are preferably transistors including an oxide semiconductor in a semiconductor layer in which a channel is formed (also referred to as "OS transistors"). An oxide semiconductor has a band gap of 2 eV or more and therefore has an extremely small off-state current. When the transistors Tr11 and Tr21 are OS transistors, charge written to a retention node can be retained for a long period of time. When the transistors Tr11 and Tr21 are OS transistors, the semiconductor device 100 can be called an "OS memory."

[0071] The OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered as a non-volatile memory.

[0072] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0073] In addition, since OS memory uses a method of writing charge to a node via an OS transistor, it does not require the high voltage required for conventional flash memory, and can achieve high-speed write operations. In addition, OS memory does not require the erase operation before rewriting data, which is performed in flash memory. In addition, since no charge is injected or extracted from the floating gate or charge trapping layer, OS memory can write and read data an unlimited number of times. OS memory is less susceptible to deterioration and is highly reliable compared to conventional flash memory.

[0074] In addition, the OS memory does not involve structural changes at the atomic level, as in magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), etc. Therefore, the OS memory has better rewrite endurance than the magnetoresistive random access memory and the resistive random access memory.

[0075] Moreover, the off-current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. Moreover, the on-current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory is stable in operation and highly reliable even in a high-temperature environment. Moreover, the OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that is stable in operation and has good reliability even in a high-temperature environment can be realized. Therefore, it is preferable to use an OS transistor as the transistor Tr11, the transistor Tr21, the transistor Tr12, and the transistor Tr22.

[0076] Furthermore, if the gate insulating films of transistors Tr12 and Tr22 are extremely thin, the charges written to nodes SN1 and SN2 may leak out through the gate insulating films (also called "gate leakage"). It is preferable that the thicknesses of the gate insulating films of transistors Tr12 and Tr22 are approximately the same as the thicknesses of the gate insulating films of transistors Tr11 and Tr21.

[0077] Alternatively, for example, OS transistors may be used as the transistors Tr11 and Tr21, and Si transistors may be used as the transistors Tr12 and Tr22. The Si transistors used as the transistors Tr12 and Tr22 may have a structure with low gate leakage.

[0078] Since Si transistors have a higher operating speed than OS transistors, the data read speed can be increased by using Si transistors for the transistors Tr12 and Tr22.

[0079] As shown in FIG. 1B, the gate of the transistor Tr11 and the gate of the transistor Tr21 may be electrically connected to the wiring WWL.

[0080] As shown in Fig. 2A, transistors having back gates may be used as the transistors Tr12 and Tr22. Fig. 2A shows an example in which the back gate of the transistor Tr12 is electrically connected to the terminal BG14, and the back gate of the transistor Tr22 is electrically connected to the terminal BG24. The threshold voltage of the transistor Tr12 can be changed by controlling the potential of the terminal BG14. The threshold voltage of the transistor Tr22 can be changed by controlling the potential of the terminal BG24.

[0081] As shown in Fig. 2B, transistors Tr11 and Tr21 may each have a back gate. Fig. 2B shows an example in which the back gate of the transistor Tr11 is electrically connected to a terminal BG13, and the back gate of the transistor Tr21 is electrically connected to a terminal BG23. The threshold voltage of the transistor Tr11 can be changed by controlling the potential of the terminal BG13. The threshold voltage of the transistor Tr21 can be changed by controlling the potential of the terminal BG23.

[0082] 3A shows an example in which the gate and the backgate are electrically connected in each of the transistors Tr11, Tr12, Tr21, and Tr22. FIG 3B shows an example in which the backgate of the transistor Tr22 is electrically connected to the other of the source and the drain of the transistor Tr22. By providing the backgate, an electric field generated outside the transistor is less likely to act on the channel formation region, so that the operation of the semiconductor device is stabilized and the reliability of the semiconductor device can be improved.

[0083] In addition, each of the transistors Tr11, Tr12, Tr21, and Tr22 may be a double-gate transistor. An example of a circuit symbol for a double-gate transistor 180A is shown in FIG 4A.

[0084] The transistor 180A has a configuration in which a transistor Tr1 and a transistor Tr2 are connected in series. Fig. 4A shows a state in which one of the source or drain of the transistor Tr1 is electrically connected to a terminal S, the other of the source or drain of the transistor Tr1 is electrically connected to one of the source or drain of the transistor Tr2, and the other of the source or drain of the transistor Tr2 is electrically connected to a terminal D. Fig. 4A also shows a state in which the gates of the transistor Tr1 and the transistor Tr2 are electrically connected and also electrically connected to a terminal G.

[0085] 4A has a function of switching the state between the terminal S and the terminal D between conductive and non-conductive states by changing the potential of the terminal G. Thus, the transistor 180A, which is a double-gate transistor, includes a transistor Tr1 and a transistor Tr2 and functions as one transistor. That is, in FIG. 4A, one of the source or the drain of the transistor 180A is electrically connected to the terminal S, the other of the source or the drain is electrically connected to the terminal D, and the gate is electrically connected to the terminal G.

[0086] In addition, each of the transistors Tr11, Tr12, Tr21, and Tr22 may be a triple-gate transistor. An example of a circuit symbol of a triple-gate transistor 180B is shown in FIG.

[0087] The transistor 180B has a configuration in which a transistor Tr1, a transistor Tr2, and a transistor Tr3 are connected in series. In FIG. 4B, one of the source or drain of the transistor Tr1 is electrically connected to a terminal S, the other of the source or drain of the transistor Tr1 is electrically connected to one of the source or drain of the transistor Tr2, the other of the source or drain of the transistor Tr2 is electrically connected to one of the source or drain of the transistor Tr3, and the other of the source or drain of the transistor Tr3 is electrically connected to a terminal D. In addition, in FIG. 4B, the gates of the transistors Tr1, Tr2, and Tr3 are electrically connected to a terminal G.

[0088] The transistor 180B shown in FIG. 4B has a function of switching the state between the terminal S and the terminal D between conductive and non-conductive states by changing the potential of the terminal G. Thus, the transistor 180B, which is a triple-gate transistor, includes the transistors Tr1, Tr2, and Tr3 and functions as one transistor. That is, in FIG. 4B, one of the source or the drain of the transistor 180B is electrically connected to the terminal S, the other of the source or the drain is electrically connected to the terminal D, and the gate is electrically connected to the terminal G.

[0089] A transistor having multiple gates electrically connected to each other, such as the transistor 180A and the transistor 180B, may be referred to as a "multi-gate transistor" or a "multi-gate transistor".

[0090] <Operation Example of Semiconductor Device 100> An example of the operation of the semiconductor device 100 will be described with reference to the drawings. As described above, the semiconductor device 100 according to one embodiment of the present invention configures the source follower circuit 130 using the transistor Tr12 and the transistor Tr22.

[0091] Here, the source follower circuit will be described. FIG. 5A is a circuit diagram of a source follower circuit 901 including a transistor M1 and a resistor element R1. The transistor M1 is an n-channel transistor. In the source follower circuit 901 shown in FIG. 5A, the source of the transistor M1 is electrically connected to one terminal of the resistor element R1. In addition, VDD is supplied to the drain of the transistor M1, and VSS is supplied to the other terminal of the resistor element. The gate of the transistor M1 is electrically connected to the terminal IN, and an input voltage Vin is input via the terminal IN. The source of the transistor M1 is electrically connected to the terminal OUT, and an output voltage Vout is output via the terminal OUT.

[0092] The transistors constituting the source follower circuit need to be operated in the saturation region. Therefore, if the threshold voltage of the transistor M1 is Vth, the transistor M1 needs to be operated under conditions that satisfy the relationship of the following formula 1:

[0093]

number

[0094] Next, a description will be given of the operation of the source follower circuit 901. Since the output voltage Vout is the source voltage of the transistor M1, the output voltage Vout is always approximately equal to a voltage obtained by subtracting Vth from Vin. More precisely, the output voltage Vout changes so as to satisfy the formula 2.

[0095]

number

[0096] In formula 2, μ n is the mobility, C OX is the gate capacitance, W is the channel width, L is the channel length, Vin is the voltage input via the terminal IN (the gate voltage of the transistor M1), Vth is the threshold voltage of the transistor M1, and R1 is the resistance value of the resistor element R1.

[0097] In the source follower circuit 901, when the input voltage Vin changes, the output voltage Vout changes following the change in the input voltage Vin.

[0098] Next, consider the case where the input voltage Vin is constant and the input impedance of the load connected to the terminal OUT varies. Let Id be the current flowing between the source and drain of the transistor M1, Ir be the current flowing through the resistor element R1, and Vgs be the gate-source voltage (gate voltage) of the transistor M1.

[0099] When no load is connected to the terminal OUT, Id and Ir are equal. When a load is connected to the terminal OUT and the input impedance of the load decreases, part of Id is supplied to the load, and Ir decreases. This reduces the voltage generated across the resistor element R1. In other words, Vout decreases.

[0100] On the other hand, a decrease in Vout means a decrease in the source potential of the transistor M1. Therefore, Vgs increases and Id increases. The increase in Id continues until Vout = Vin - Vth is reached. More precisely, the output voltage Vout increases until it satisfies Equation 2.

[0101] In addition, when the input impedance of the load connected to the terminal OUT increases, the current supplied to the load decreases, and the current Ir flowing through the resistor element R1 increases. This increases the voltage generated across the resistor element R1. In other words, Vout rises.

[0102] On the other hand, an increase in Vout means an increase in the source potential of the transistor M1. Therefore, Vgs becomes smaller and Id decreases. The decrease in Id continues until approximately Vout = Vin - Vth. More precisely, the output voltage Vout decreases until it satisfies the formula 2.

[0103] In this way, the source follower circuit has the function of always supplying a constant voltage even if the input impedance of the load varies. In other words, the source follower circuit has the function of performing power amplification (amplifying the current value without changing the output voltage).

[0104] 5B, the resistor element R1 of the source follower circuit 901 can be replaced with a transistor M2. The transistor M2 is an n-channel transistor. In the source follower circuit 902, the transistors M1 and M2 are also operated in the saturation region.

[0105] In the source follower circuit 902, a gate of the transistor M1 is electrically connected to a terminal IN1, a gate of the transistor M2 is electrically connected to a terminal IN2, a drain of the transistor M2 is electrically connected to a terminal OUT, and a low power supply voltage VSS is supplied to a source of the transistor M2.

[0106] The source follower circuit 902 also has a function of performing power amplification. In the source follower circuit 902, if a current flowing between the source and drain of the transistor M1 operating in the saturation region is Id1 and a current flowing between the source and drain of the transistor M2 operating in the saturation region is Id2, then Id1 can be expressed by Equation 3 and Id2 by Equation 4.

[0107]

number

[0108] In formula 3, μ n is the mobility, C OXis the gate capacitance, W is the channel width, L is the channel length, Vin1 is the voltage input via terminal IN1 (the gate voltage of transistor M1), and Vth1 is the threshold voltage of transistor M1.

[0109]

number

[0110] In Formula 4, μ n is the mobility, C OX is the gate capacitance, W is the channel width, L is the channel length, Vin2 is the voltage input via terminal IN2 (the gate voltage of transistor M2), and Vth2 is the threshold voltage of transistor M2.

[0111] Id1 and Id2 are equal in the source follower circuit 902. In addition, when the configurations and transistor characteristics of the transistors M1 and M2 are equal, the output voltage Vout of the source follower circuit 902 can be expressed by Equation 5.

[0112]

number

[0113] Returning to the description of the operation example of the semiconductor device 100, Fig. 6 is a timing chart for explaining the operation of the semiconductor device 100. Figs. 7 and 8 are diagrams for explaining the operating states of the semiconductor device 100.

[0114] In drawings, etc., symbols indicating potential such as "VDD" or "VSS" (also called "potential symbols") may be written next to terminals, wiring, etc. In order to make potential changes in terminals and wiring easier to understand, the potential symbols attached to terminals and wiring that have experienced a potential change may be written in letters enclosed. In addition, an "x" symbol may be placed over a transistor that is in the off state.

[0115] [Data write operation] Before the data write operation is started, the potentials of terminals WW1 and WW2 are set to the L potential, and the potentials of terminals PS1, PS2, IN1, IN2, node SN1, node SN2, and terminal OUT are set to VSS. In this specification and the like, a potential that can turn a transistor into an OFF state is called an L potential. The L potential may be, for example, VSS, but does not mean any specific potential. In this specification and the like, a potential that can turn a transistor into an ON state is called an H potential. The H potential may be, for example, VDD, but does not mean any specific potential.

[0116] For example, when it is stated that "an L potential is supplied" to each of two wires, the L potentials supplied to the two wires do not have to be equal to each other. Similarly, when it is stated that "an H potential is supplied" to each of two wires, the H potentials supplied to the two wires do not have to be equal to each other.

[0117] In a period T31, an H potential is supplied to the terminals WW1 and WW2 to turn on the transistors Tr11 and Tr21 (see FIG. 7A). In addition, a voltage (Vdata+Vref) obtained by adding a reference voltage Vref (reference potential) to the data Vdata is supplied to the node SN1 via the terminal IN1 and the transistor Tr11.

[0118] Also, a reference voltage Vref is supplied as Vin2 to node SN2 via terminal IN2 and transistor Tr21. Because transistor Tr22 needs to operate in the saturation region during a read operation, it is preferable that the reference voltage Vref is equal to or lower than the threshold voltage Vth2 of transistor Tr22. Note that when transistors Tr12 and Tr22 have the same transistor characteristics, Vref=Vth1=Vth2.

[0119] In period T32, an L potential is supplied to terminals WW1 and WW2, and transistors Tr11 and Tr21 are turned off (see FIG. 7B). With transistor Tr11 turned off, node SN1 is brought into a floating state, and the potential (charge) of node SN1 is maintained. With transistor Tr21 turned off, node SN2 is brought into a floating state, and the potential (charge) of node SN2 is maintained.

[0120] [Data read operation] In a period T41, VDD is supplied to the terminal PS1. Then, a current flows from the terminal PS1 through the transistor Tr12, and a charge is supplied to the node BN. Fig. 8A shows the state immediately after the start of the period T41.

[0121] Supplying charge to node BN increases the potential of node BN. In period T41, node SN1 is in a floating state and is capacitively coupled to node BN via capacitance element Cb1, so the potential of node SN1 (also referred to as "Vsn1") also increases due to the bootstrap effect. Similarly, in period T41, node SN2 is in a floating state and is capacitively coupled to node BN via capacitance element Cb2, so the potential of node SN2 (also referred to as "Vsn2") also increases due to the bootstrap effect (see FIG. 8B).

[0122] As described above, the semiconductor device 100 includes a bootstrap circuit 120a including a transistor Tr12 and a capacitance element Cb1. The bootstrap circuit 120a functions to boost the potential of the node SN1. The semiconductor device 100 also includes a bootstrap circuit 120b including a transistor Tr22 and a capacitance element Cb2. The bootstrap circuit 120b functions to boost the potential of the node SN2.

[0123] In the semiconductor device 100, the potential of the node BN can be interpreted as the output voltage Vout. The potential of the node BN (output voltage Vout) becomes a potential equivalent to the potential difference between the nodes SN1 and SN2. The potential of the node BN (output voltage Vout) changes until it satisfies the above-mentioned formula 5. Specifically, it changes until it becomes Vsn1-Vsn2. Therefore, the potential of the node BN (output voltage Vout) finally becomes Vdata.

[0124] At this time, it can be said that the transistor Tr22 is operating in the saturation region. In order to operate the transistor Tr12 in the saturation region, the potential Vin1 supplied to the terminal IN1 during a write operation must satisfy the formula 6.

[0125]

number

[0126] Moreover, by setting the potential supplied to the terminal IN2 to VSS, it is possible to make Vin1=Vdata. For example, as shown in FIG. 9, one of the source or drain of the transistor Tr21 electrically connected to the terminal IN2 may be electrically connected to the terminal PS2 instead of the terminal IN2. By setting the potential supplied to the terminal IN2 to VSS, it becomes unnecessary to add Vref to Vin1, so that the driving circuit of the semiconductor device 100 can be made smaller. Therefore, the occupied area of ​​the semiconductor device including the semiconductor device 100 can be reduced. Furthermore, the degree of freedom in designing the semiconductor device is improved. Furthermore, the reliability of the semiconductor device can be improved.

[0127] When the potential supplied to the terminal IN2 is VSS, Vdata needs to satisfy the formula 7.

[0128]

number

[0129] In this way, the semiconductor device 100 according to one embodiment of the present invention has a function of storing analog data and a function of power-amplifying and outputting the stored analog data. Since the stored data is power-amplified when it is read, it is possible to eliminate the need for a power amplifier circuit or the like used after the data is read. Alternatively, the number or size of the power amplifier circuit can be reduced.

[0130] Furthermore, the semiconductor device 100 according to one embodiment of the present invention can stably output (read) stored data even if the impedance of a load connected to an output terminal (terminal OUT) fluctuates. Note that the semiconductor device 100 according to one embodiment of the present invention can store not only analog data but also digital data.

[0131] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0132] (Embodiment 2) In this embodiment, a semiconductor device 400 including a memory device or a semiconductor device according to one embodiment of the present invention will be described.

[0133] Fig. 10A shows a block diagram illustrating a configuration example of a semiconductor device 400. The semiconductor device 400 shown in Fig. 10A has a driver circuit 410 and a memory array 420. The memory array 420 has a plurality of semiconductor devices 100. The semiconductor device 100 functions as a memory cell. Fig. 10A shows an example in which the memory array 420 has a plurality of semiconductor devices 100 arranged in a matrix.

[0134] The drive circuit 410 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 415. The peripheral circuit 415 includes a peripheral circuit 411, a control circuit 412, and a voltage generating circuit 428.

[0135] In the semiconductor device 400, each circuit, each signal, and each voltage can be appropriately selected or omitted as necessary. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0136] Moreover, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 412.

[0137] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine an operation mode (e.g., a write operation, a read operation) of the semiconductor device 400. Alternatively, the control circuit 412 generates a control signal for the peripheral circuit 411 so that this operation mode is executed.

[0138] The voltage generating circuit 428 has a function of generating a negative voltage. WAKE has a function of controlling the input of CLK to the voltage generating circuit 428. For example, when an H-level signal is given to WAKE, the signal CLK is input to the voltage generating circuit 428, and the voltage generating circuit 428 generates a negative voltage.

[0139] The peripheral circuit 411 is a circuit for writing and reading data to and from the semiconductor device 100. The peripheral circuit 411 includes a row decoder 441, a column decoder 442, a row driver 423, a column driver 424, an input circuit 425, and an output circuit 426. A sense amplifier or the like may be provided as necessary.

[0140] The row decoder 441 and the column decoder 442 have a function of decoding the signal ADDR. The row decoder 441 is a circuit for specifying a row to be accessed, and the column decoder 442 is a circuit for specifying a column to be accessed. The row driver 423 has a function of selecting a wiring specified by the row decoder 441. The column driver 424 has a function of writing data to the semiconductor device 100, a function of reading data from the semiconductor device 100, a function of holding the read data, and the like.

[0141] The input circuit 425 has a function of holding a signal WDA. The data held by the input circuit 425 is output to the column driver 424. The output data of the input circuit 425 is data (Din) to be written to the semiconductor device 100. The data (Dout) read by the column driver 424 from the semiconductor device 100 is output to the output circuit 426. The output circuit 426 has a function of holding Dout. In addition, the output circuit 426 has a function of outputting Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is a signal RDA.

[0142] The PSW241 has a function of controlling the supply of VDD to the peripheral circuit 415. The PSW242 has a function of controlling the supply of VHM to the row driver 423. Here, the high power supply voltage of the semiconductor device 400 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD. The on / off of the PSW241 is controlled by a signal PON1, and the on / off of the PSW242 is controlled by a signal PON2. In FIG. 10A, the number of power supply domains to which VDD is supplied in the peripheral circuit 415 is one, but it may be multiple. In this case, a power switch may be provided for each power supply domain.

[0143] The driving circuit 410 and the memory array 420 of the semiconductor device 400 may be provided on the same plane. Also, as shown in Fig. 10B, the driving circuit 410 and the memory array 420 may be provided so as to overlap each other. By providing the driving circuit 410 and the memory array 420 so as to overlap each other, the signal propagation distance can be shortened.

[0144] Furthermore, the semiconductor device 400 may use an arithmetic processing device such as a CPU (Central Processing Unit) and / or a GPU (Graphics Processing Unit) for the control circuit 412 of the drive circuit 410. By using a CPU and / or a GPU, the semiconductor device 400 having an arithmetic processing function can be realized.

[0145] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0146] (Embodiment 3) In this embodiment, an example of a processing device which can include the semiconductor device described in the above embodiment will be described.

[0147] Fig. 11 shows a block diagram of a processing device 1100. Fig. 11 shows a configuration example of a CPU as a configuration example that can be used for the processing device 1100.

[0148] The arithmetic processing device 1100 shown in FIG. 11 has an ALU 1191 (ALU: arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a cache 1199, and a cache interface 1189 on a substrate 1190. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may be provided on separate chips.

[0149] The cache 1199 is connected to a main memory provided on a separate chip via a cache interface 1189. The cache interface 1189 has a function of supplying a portion of the data held in the main memory to the cache 1199. The cache 1199 has a function of holding that data.

[0150] The arithmetic processing device 1100 shown in Fig. 11 is merely one example of a simplified configuration, and the actual arithmetic processing device 1100 has a wide variety of configurations depending on its application. For example, the arithmetic processing device 1100 shown in Fig. 11 or a configuration including an arithmetic circuit may be one core, and a configuration including multiple such cores and each core may operate in parallel, that is, a configuration like a GPU. In addition, the number of bits that the arithmetic processing device 1100 can handle in the internal arithmetic circuit and data bus may be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0151] An instruction input to the processor 1100 via the bus interface 1198 is input to an instruction decoder 1193 , decoded, and then input to an ALU controller 1192 , an interrupt controller 1194 , a register controller 1197 , and a timing controller 1195 .

[0152] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes interrupt requests from external input / output devices or peripheral circuits based on their priority and mask state while the arithmetic processing device 1100 is executing a program. The register controller 1197 generates an address for the register 1196, and reads and writes to the register 1196 according to the state of the arithmetic processing device 1100.

[0153] Furthermore, the timing controller 1195 generates signals that control the timing of the operations of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0154] 11, a memory device is provided in a register 1196 and a cache 1199. As the memory device, for example, the semiconductor device 100 described in the above embodiment may be used.

[0155] In the arithmetic processing device 1100 shown in FIG. 11, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is to be held by a flip-flop or by a capacitive element in the memory cell of the register 1196. When holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When holding data in a capacitive element is selected, data is rewritten to the capacitive element, and the supply of power supply voltage to the memory cell in the register 1196 can be stopped.

[0156] The arithmetic processing device 1100 is not limited to a CPU, but may be a GPU, a DSP (Digital Signal Processor), an FPGA (Field-Programmable Gate Array), or the like.

[0157] The semiconductor device 400 and the arithmetic processing device 1100 described in the above embodiment can be provided overlapping each other. Fig. 12A and Fig. 12B are perspective views of a semiconductor device 1150A. The semiconductor device 1150A has a semiconductor device 400 functioning as a memory device on the arithmetic processing device 1100. The arithmetic processing device 1100 and the semiconductor device 400 have an overlapping region. In order to make the configuration of the semiconductor device 1150A easier to understand, the arithmetic processing device 1100 and the semiconductor device 400 are shown separately in Fig. 12B.

[0158] By stacking the semiconductor device 400 and the arithmetic processing device 1100, the connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows power consumption to be reduced.

[0159] Also, a plurality of semiconductor devices 400 may be provided overlapping the arithmetic processing device 1100. Fig. 13A and Fig. 13B are perspective views of a semiconductor device 1150B. The semiconductor device 1150B has a semiconductor device 400a and a semiconductor device 400b on the arithmetic processing device 1100. The arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. In order to make the configuration of the semiconductor device 1150B easier to understand, Fig. 13B shows the arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b separately.

[0160] The semiconductor device 400a and the semiconductor device 400b function as storage devices. For example, a NOR type storage device may be used for one of the semiconductor device 400a and the semiconductor device 400b, and a NAND type storage device may be used for the other. Both the semiconductor device 400a and the semiconductor device 400b may be NAND type storage devices, or may be NOR type storage devices. Examples of NOR type storage devices include DRAM and SRAM. Since a NOR type storage device can operate faster than a NAND type storage device, for example, a part of the semiconductor device 400a can be used as a main memory and / or a cache 1199. The semiconductor device 400a and the semiconductor device 400b may be stacked in the reverse order.

[0161] 14A and 14B are perspective views of the semiconductor device 1150C. The semiconductor device 1150C has a configuration in which the arithmetic processing device 1100 is sandwiched between the semiconductor device 400a and the semiconductor device 400b. The arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b have overlapping regions. In order to make the configuration of the semiconductor device 1150C easier to understand, the arithmetic processing device 1100, the semiconductor device 400a, and the semiconductor device 400b are shown separately in FIG. 14B.

[0162] The configuration of the semiconductor device 1150C can increase the communication speed between the semiconductor device 400a and the arithmetic processing device 1100 and the communication speed between the semiconductor device 400b and the arithmetic processing device 1100. In addition, the power consumption can be reduced more than that of the semiconductor device 1150B.

[0163] The semiconductor device according to one embodiment of the present invention can be used in an artificial neural network. A configuration example of an artificial neural network will be described below.

[0164] FIG. 15A shows an example of the configuration of a neural network NN. The neural network NN can be configured with an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL, and the intermediate layer HL each have one or more neurons (units). The intermediate layer HL may be one layer or two or more layers. A neural network with two or more intermediate layers HL can be called a DNN (deep neural network), and learning using a deep neural network can be called deep learning.

[0165] Input data is input to each neuron in the input layer IL, the output signal of a neuron in the previous or next layer is input to each neuron in the hidden layer HL, and the output signal of a neuron in the previous layer is input to each neuron in the output layer OL. Each neuron may be connected to all neurons in the previous or next layer (full connection), or may be connected to only a portion of the neurons.

[0166] FIG. 15B shows an example of a computation by a neuron. Here, neuron N and two neurons in the previous layer that output signals to neuron N are shown. Neuron N receives output x1 from a neuron in the previous layer and output x2 from a neuron in the previous layer. Neuron N then calculates the sum x1w1+x2w2 of the multiplication result (x1w1) of output x1 and weight w1 and the multiplication result (x2w2) of output x2 and weight w2, and then adds bias b as necessary to obtain value a=x1w1+x2w2+b. Value a is then transformed by activation function h, and output signal y=h(a) is output from neuron N.

[0167] In this way, the calculations performed by neurons include the calculation of adding up the product of the output of a neuron in the previous layer and the weight, that is, the product-sum calculation (x1w1+x2w2 above). This product-sum calculation may be performed on software using a program, or it may be performed by hardware. When the product-sum calculation is performed by hardware, a product-sum calculation circuit can be used. As this product-sum calculation circuit, either a digital circuit or an analog circuit can be used. When an analog circuit is used for the product-sum calculation circuit, it is possible to reduce the circuit scale of the product-sum calculation circuit or to reduce the number of memory accesses, thereby improving the processing speed and reducing power consumption.

[0168] Furthermore, when an analog circuit is used for the product-sum calculation circuit, analog data is used as the weight information. The semiconductor device 100 according to one embodiment of the present invention can hold analog data without converting it into a digital value. This makes it possible to reduce conversion circuits such as a digital to analog converter (DAC) and / or an analog to digital converter (ADC), thereby realizing reductions in power consumption and occupied area.

[0169] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0170] (Embodiment 4) In this embodiment mode, a configuration example of a transistor applicable to the semiconductor device described in the above embodiment mode will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked will be described. By using this configuration, the degree of freedom in designing the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of the semiconductor device can be increased.

[0171] FIG. 16 illustrates a part of a cross-sectional structure of the semiconductor device. The semiconductor device illustrated in FIG. 16 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 17A is a top view of the transistor 500. FIG. 17B is a cross-sectional view of the transistor 500 taken along a portion L1-L2 indicated by a dashed line in FIG. 17A, which is a cross-sectional view in the channel length direction. FIG. 17C is a cross-sectional view of the transistor 500 taken along a portion W1-W2 indicated by a dashed line in FIG. 17A, which is a cross-sectional view in the channel width direction. For example, the transistor 500 corresponds to an OS transistor included in the semiconductor device 100 described in the above embodiment, that is, a transistor having an oxide semiconductor in a channel formation region. The transistor 550 corresponds to a Si transistor included in the driver circuit 410 described in the above embodiment, that is, a transistor having silicon in a channel formation region.

[0172] The transistor 500 is an OS transistor. An OS transistor has an extremely small off-state current. Therefore, a data voltage or charge written to a storage node through the transistor 500 can be held for a long period of time. That is, the frequency of a refresh operation of the storage node can be reduced or the refresh operation is not required, so that the power consumption of a semiconductor device can be reduced.

[0173] In FIG. 16, the transistor 500 is provided above the transistor 550 , and the capacitor 600 is provided above the transistor 550 and the transistor 500 .

[0174] The transistor 550 is provided on a substrate 371. The substrate 371 is, for example, a p-type silicon substrate. The substrate 371 may be an n-type silicon substrate. The oxide layer 374 is preferably an insulating layer (also referred to as a BOX layer) formed by a buried oxide (Burried oxide) in the substrate 371, for example, silicon oxide. The transistor 550 is provided on single crystal silicon provided on the substrate 371 via the oxide layer 374, that is, a so-called SOI (Silicon On Insulator) substrate.

[0175] A substrate 371 in the SOI substrate is provided with an insulator 373 functioning as an element isolation layer. The substrate 371 also has a well region 372. The well region 372 is a region to which n-type or p-type conductivity is imparted according to the conductivity type of the transistor 550. A semiconductor region 375, and low-resistance regions 376a and 376b functioning as source and drain regions are provided in the single crystal silicon in the SOI substrate. Also, a low-resistance region 376c is provided on the well region 372.

[0176] The transistor 550 can be provided overlapping a well region 372 to which an impurity element that imparts conductivity is added. The well region 372 can function as a bottom gate electrode of the transistor 550 by independently changing the potential through the low-resistance region 376c. Therefore, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 372, the threshold voltage of the transistor 550 can be increased and the off-current can be reduced. Therefore, by applying a negative potential to the well region 372, the drain current when the potential applied to the gate electrode of the Si transistor is 0 V can be reduced. As a result, power consumption based on a through current or the like in an arithmetic circuit having the transistor 550 can be reduced, and arithmetic efficiency can be improved.

[0177] The transistor 550 is preferably a so-called fin type in which a top surface of a semiconductor layer and side surfaces in a channel width direction are covered with a conductor 378 via an insulator 377. By making the transistor 550 a fin type, the effective channel width is increased, and thus the on characteristics of the transistor 550 can be improved. In addition, the contribution of the electric field of the gate electrode can be increased, and thus the off characteristics of the transistor 550 can be improved.

[0178] Note that the transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0179] The conductor 378 may function as a first gate (also called a top gate) electrode. The well region 372 may function as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the well region 372 can be controlled via the low resistance region 376c.

[0180] The region where the channel of the semiconductor region 375 is formed, the region nearby, the low resistance region 376a which becomes the source region or drain region, the low resistance region 376b, the low resistance region 376c which is connected to the electrode which controls the potential of the well region 372, and the like preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon. Alternatively, they may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 550 may be a HEMT by using GaAs and GaAlAs, or the like.

[0181] Well region 372, low resistance region 376a, low resistance region 376b, and low resistance region 376c include the semiconductor material applied to semiconductor region 375 as well as an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0182] The conductor 378 functioning as the gate electrode can be a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material. The conductor 378 can also be a silicide such as nickel silicide.

[0183] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and in particular, it is preferable to use tungsten in terms of heat resistance.

[0184] The low-resistance region 376a, the low-resistance region 376b, and the low-resistance region 376c may be formed by stacking another conductor, for example, a silicide such as nickel silicide. This structure can increase the conductivity of the region functioning as an electrode. In addition, in this case, an insulator functioning as a sidewall spacer (also called a sidewall insulating layer) may be provided on the side surface of the conductor 378 functioning as the gate electrode and the side surface of the insulator functioning as the gate insulating film. This structure can prevent the conductor 378 from being electrically connected to the low-resistance region 376a and the low-resistance region 376b.

[0185] An insulator 379, an insulator 381, an insulator 383, and an insulator 385 are stacked in this order to cover the transistor 550.

[0186] As insulator 379, insulator 381, insulator 383, and insulator 385, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used.

[0187] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen, silicon nitride oxide refers to a material having a higher nitrogen content than oxygen, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen.

[0188] The insulator 381 may function as a planarizing film that planarizes steps caused by the transistor 550 or the like provided thereunder. For example, the top surface of the insulator 381 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0189] The insulator 383 is preferably a film having a barrier property that prevents diffusion of hydrogen and impurities from the substrate 371, the transistor 550, or the like to a region where the transistor 500 is provided.

[0190] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film that releases a small amount of hydrogen.

[0191] The amount of desorption of hydrogen can be analyzed, for example, by using thermal desorption spectrometry (TDS). For example, the amount of desorption of hydrogen from the insulator 383 is calculated as 10×10 per area of ​​the insulator 383 when the surface temperature of the film is in the range of 50° C. to 500° C. in the TDS analysis. 15 atoms / cm 2 Less than or equal to 5×10 15 atoms / cm 2 The following is acceptable.

[0192] Note that the insulator 385 preferably has a lower dielectric constant than the insulator 383. For example, the relative dielectric constant of the insulator 385 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 385 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 383. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0193] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 379, 381, 383, and 385. The conductors 328 and 330 function as plugs or wiring. A plurality of conductors that function as plugs or wiring may be collectively assigned the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0194] As the material for each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used in a single layer or a laminated layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form it from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, it is possible to reduce the wiring resistance.

[0195] A wiring layer may be provided over the insulator 385 and the conductor 330. For example, in FIG. 16, the insulator 350, the insulator 352, and the insulator 354 are stacked in this order. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 550. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0196] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against hydrogen, like the insulator 383. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0197] Note that, for example, tantalum nitride or the like may be used as a conductor having a barrier property against hydrogen. By stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

[0198] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 16, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0199] Note that, for example, the insulator 360 is preferably an insulator having a barrier property against hydrogen, like the insulator 383. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0200] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 16, an insulator 370, an insulator 369, and an insulator 368 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 369, and the insulator 368. The conductor 376 functions as a plug or a wiring. The conductor 376 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0201] Note that, for example, the insulator 370 is preferably an insulator having a barrier property against hydrogen, like the insulator 383. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0202] A wiring layer may be provided over the insulator 368 and the conductor 376. For example, in FIG. 16, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0203] Note that, for example, the insulator 380 is preferably an insulator having a barrier property against hydrogen, similar to the insulator 383. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0204] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device of this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0205] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order on the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made of a substance that has a barrier property against oxygen and hydrogen.

[0206] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property against hydrogen and impurities in a region where the transistor 500 is provided, such as the substrate 371 or a region where the transistor 550 is provided. Therefore, a material similar to that of the insulator 383 can be used.

[0207] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, a film that suppresses the diffusion of hydrogen is preferably used between the transistor 500 and the transistor 550.

[0208] As a film having a barrier property against hydrogen, for example, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0209] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0210] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 379. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 512 and the insulator 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0211] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be provided using a material similar to that of the conductor 328 and the conductor 330.

[0212] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0213] Above the insulator 516 is a transistor 500 .

[0214] As shown in Figures 17A to 17C, transistor 500 has a conductor 503 arranged so as to be embedded in insulator 514 and insulator 516, an insulator 520 arranged on insulator 516 and conductor 503, an insulator 522 arranged on insulator 520, an insulator 524 arranged on insulator 522, an oxide 530a arranged on insulator 524, an oxide 530b arranged on oxide 530a, conductors 542a and 542b arranged apart from each other on oxide 530b, an insulator 580 arranged on conductor 542a and conductor 542b and having an opening formed therein overlapping with conductor 542a and conductor 542b, an insulator 545 arranged on the bottom and side surfaces of the opening, and a conductor 560 arranged on the formation surface of insulator 545.

[0215] 17B and 17C, an insulator 544 is preferably disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. As shown in FIGS. 17A to 17C, the conductor 560 preferably has a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. As shown in FIGS. 17B and 17C, an insulator 574 is preferably disposed on the insulator 580, the conductor 560, and the insulator 545.

[0216] In this specification and other documents, oxide 530a and oxide 530b may be collectively referred to as oxide 530.

[0217] Note that, in the transistor 500, a two-layer structure of the oxide 530a and the oxide 530b is shown in the region where the channel is formed and in the vicinity thereof, but the present invention is not limited to this structure. For example, a single layer of the oxide 530b or a stacked structure of three or more layers may be used.

[0218] Although the transistor 500 has a two-layer structure, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a three-or-more-layer structure. The transistor 500 illustrated in FIGS. 16 and 17A to 17C is merely an example and is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and / or driving method.

[0219] Here, the conductor 560 functions as the gate electrode of the transistor 500, and the conductors 542a and 542b function as the source electrode and drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangement of the conductors 560, 542a, and 542b is selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged in a self-aligned manner between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing a margin for alignment, so that the area occupied by the transistor 500 can be reduced. This allows the semiconductor device to be miniaturized and highly integrated.

[0220] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This makes it possible to reduce the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This makes it possible to improve the switching speed of the transistor 500 and provide high frequency characteristics.

[0221] The conductor 560 may function as a first gate (also referred to as a gate or a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a back gate or a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be increased and the off-current can be reduced. Therefore, the drain current when the potential applied to the conductor 560 is 0 V can be reduced by applying a negative potential to the conductor 503 compared to the case where a negative potential is not applied.

[0222] The conductor 503 is disposed so as to overlap the oxide 530 and the conductor 560. In this manner, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and a channel formation region formed in the oxide 530 can be covered.

[0223] In this specification and the like, a transistor configuration in which a channel formation region is electrically surrounded by the electric field of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. The S-channel configuration disclosed in this specification and the like is different from a fin type configuration and a planar type configuration. By adopting the S-channel configuration, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0224] The conductor 503 has a structure similar to that of the conductor 518, and the conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and the conductor 503b is formed further inside. Note that, although the transistor 500 shows a structure in which the conductor 503a and the conductor 503b are stacked, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0225] Here, the conductor 503a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate through). Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate through). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0226] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and the conductivity from decreasing.

[0227] In addition, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b is made of a highly conductive material containing tungsten, copper, or aluminum as a main component. Note that, although the conductor 503 is illustrated in this embodiment as a stack of the conductors 503a and 503b, the conductor 503 may have a single layer structure.

[0228] The insulators 520, 522, and 524 function as a second gate insulating film.

[0229] Here, it is preferable that the insulator 524 in contact with the oxide 530 is an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxygen is easily released from the film by heating. In this specification and the like, oxygen released by heating may be called "excess oxygen." In other words, it is preferable that the insulator 524 has a region containing excess oxygen (also called "excess oxygen region"). By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O In addition, when hydrogen enters an oxygen vacancy in the oxide 530, the defect (hereinafter, V O H.) may function as a donor and generate electrons as carriers. Some of the hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily moved by stress such as heat or an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (also called "dehydration" or "dehydrogenation treatment") and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (also called "oxygenation treatment"). O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0230] Specifically, it is preferable to use an oxide material from which some oxygen is released by heating as an insulator having an excess oxygen region. An oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0231] In addition, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By carrying out such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the bond of VoH, in other words, "V O The reaction "H → Vo + H" occurs, and dehydrogenation can be achieved. Some of the hydrogen generated at this time may combine with oxygen to become HO and be removed from the oxide 530 or the insulator in the vicinity of the oxide 530. Also, some of the hydrogen may be gettered to the conductor 542a and the conductor 542b.

[0232] In addition, the microwave treatment is preferably performed using, for example, a device having a power source that generates high-density plasma or a device having a power source that applies RF to the substrate side. For example, high-density oxygen radicals can be generated by using a gas containing oxygen and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. In addition, the pressure of the microwave treatment may be set to 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, for example, oxygen and argon are used as gases to be introduced into the microwave treatment device, and the oxygen flow rate ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0233] In addition, in a manufacturing process of the transistor 500, it is preferable to perform heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this way, oxygen is supplied to the oxide 530 to reduce oxygen deficiencies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0234] By subjecting the oxide 530 to oxygen addition treatment, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo+O→null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 530, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0235] When the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate).

[0236] Since the insulator 522 has a function of suppressing diffusion of oxygen and impurities, the oxygen contained in the oxide 530 does not diffuse toward the insulator 520, which is preferable. In addition, the conductor 503 can be suppressed from reacting with the oxygen contained in the insulator 524 and / or the oxide 530.

[0237] The insulator 522 is preferably a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator that functions as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0238] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials having a function of suppressing the diffusion of impurities and oxygen (the oxygen is unlikely to permeate through them). As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0239] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0240] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, by combining a high-k material insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable and high dielectric constant laminate structure.

[0241] 17A to 17C, the second gate insulating film has a three-layer stack structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single layer, two layers, or four or more layers. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0242] In the transistor 500, a metal oxide functioning as an oxide semiconductor is used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like) may be used for the oxide 530.

[0243] The metal oxide functioning as an oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide functioning as an oxide semiconductor will be described in detail in another embodiment.

[0244] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. In this manner, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0245] The oxide 530 has the oxide 530a below the oxide 530b, and thus can suppress the diffusion of impurities from components formed below the oxide 530a to the oxide 530b.

[0246] The oxide 530 preferably has a laminated structure of a plurality of oxide layers having different atomic ratios of metal atoms. Specifically, the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 530b. In addition, the atomic ratio of element M to In in the metal oxide used for the oxide 530a is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 530b. In addition, the atomic ratio of In to element M in the metal oxide used for the oxide 530b is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0247] In addition, it is preferable that the energy of the conduction band minimum of the oxide 530a is higher than that of the oxide 530b, or, in other words, it is preferable that the electron affinity of the oxide 530a is smaller than that of the oxide 530b.

[0248] Here, at the junction between the oxide 530a and the oxide 530b, the energy level of the conduction band minimum changes gradually. In other words, it can be said that the energy level of the conduction band minimum at the junction between the oxide 530a and the oxide 530b changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0249] Specifically, the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0250] At this time, the main carrier path is the oxide 530b. By configuring the oxide 530a as described above, the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0251] Conductors 542a and 542b functioning as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, and are therefore preferable.Furthermore, metal nitride films such as tantalum nitride are preferable because they have barrier properties against hydrogen or oxygen.

[0252] 17B, ​​the conductor 542a and the conductor 542b are shown as a single layer, but may be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. A titanium film and an aluminum film may be laminated. A two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, or a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0253] In addition, there are three-layer structures in which a titanium film or titanium nitride film is laminated with an aluminum film or copper film on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated with an aluminum film or copper film on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0254] 17B, ​​regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the regions 543a and 543b.

[0255] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier density in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0256] The insulator 544 is provided to cover the conductor 542a and the conductor 542b and suppresses oxidation of the conductor 542a and the conductor 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0257] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0258] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in a heat treatment in a later process. Note that when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or a material whose conductivity does not decrease significantly even when oxygen is absorbed, the insulator 544 is not an essential component. It may be designed appropriately depending on the desired transistor characteristics.

[0259] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing into the oxide 530b. In addition, oxidation of the conductor 542 due to excess oxygen contained in the insulator 580 can be prevented.

[0260] The insulator 545 functions as a first gate insulating film. Like the insulator 524 described above, the insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating.

[0261] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0262] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied from the insulator 545 to the channel formation region of the oxide 530b. Similarly to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 545 is preferably reduced. The thickness of the insulator 545 is preferably 1 nm or more and 20 nm or less. The microwave treatment described above may be performed before and / or after the formation of the insulator 545.

[0263] Furthermore, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 545 to the conductor 560 can be suppressed. That is, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0264] The insulator 545 may have a layered structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by making the insulator that functions as the gate insulating film have a layered structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, a layered structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0265] Although the conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 17B and 17C, it may have a single-layer structure or a laminated structure of three or more layers.

[0266] The conductor 560a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). The conductor 560a has a function of suppressing the diffusion of oxygen, so that it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 545 and its conductivity from decreasing. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. In addition, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, the conductor 560b can be formed by a sputtering method to reduce the electrical resistance value of the conductor 560a and make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0267] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b also functions as wiring, so it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0268] The insulator 580 is provided on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably has silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or a resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having voids are preferable because they can easily form an excess oxygen region in a later step.

[0269] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0270] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b, so that conductor 560 is formed so as to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0271] In miniaturizing a semiconductor device, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased for that purpose, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580, so that even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0272] The insulator 574 is preferably provided in contact with a top surface of the insulator 580, a top surface of the conductor 560, and a top surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. This allows oxygen to be supplied from the excess oxygen region into the oxide 530.

[0273] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0274] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as a barrier film against impurities such as hydrogen as well as an oxygen source.

[0275] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0276] Conductor 540a and conductor 540b are arranged in openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductor 540a and conductor 540b are provided facing each other with conductor 560 interposed therebetween. Conductor 540a and conductor 540b have the same configuration as conductor 546 and conductor 548, which will be described later.

[0277] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0278] In particular, aluminum oxide has a high blocking effect of preventing the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. In addition, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0279] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 379. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0280] In addition, conductors 546, 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0281] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0282] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively surrounded by an insulator having a high barrier property against hydrogen or water. When an opening is formed to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the insulator having a high barrier property is formed in contact with the insulator 522 or the insulator 514, which is preferable because it serves as part of the manufacturing process of the transistor 500. Note that the insulator having a high barrier property against hydrogen or water may be made of a material similar to that of the insulator 522 or the insulator 514, for example.

[0283] Next, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0284] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0285] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-mentioned element (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide can also be used.

[0286] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0287] The conductor 620 is provided so as to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. When the conductor 620 is formed simultaneously with other components such as a conductor, a low resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0288] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be provided using a material similar to that of the insulator 379. The insulator 640 may also function as a planarizing film that covers the uneven shape thereunder.

[0289] With this structure, miniaturization or high integration can be achieved in a semiconductor device including a transistor including an oxide semiconductor.

[0290] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0291] (Embodiment 5) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0292] The metal oxide preferably contains either indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0293] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 18A. Fig. 18A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0294] As shown in FIG. 18A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystalline" includes single crystal and poly crystal.

[0295] The structure in the bold frame shown in Fig. 18A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" or "Crystal".

[0296] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. FIG. 18B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 18B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in FIG. 18B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 18B is 500 nm.

[0297] As shown in Figure 18B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 18B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0298] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 18C. FIG. 18C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in FIG. 18C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0299] As shown in FIG. 18C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0300] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 18A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0301] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0302] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0303] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0304] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0305] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0306] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0307] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In addition, in the CAAC-OS, no clear grain boundary can be confirmed even in the vicinity of the distortion. That is, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms in the ab-plane direction is not dense and the bond distance between atoms changes due to the substitution of metal atoms.

[0308] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0309] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities and the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0310] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor depending on the analysis method. For example, when the structure of the nc-OS film is analyzed using an XRD device, no peak indicating crystallinity is detected in the out-of-plane XRD measurement using θ / 2θ scanning. In addition, when the nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0311] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0312] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0313] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0314] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0315] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0316] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0317] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0318] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0319] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0320] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0321] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0322] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0323] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0324] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0325] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0326] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0327] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0328] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentrations of silicon and carbon in the oxide semiconductor and those in the vicinity of the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2×1017 atoms / cm 3 The following applies.

[0329] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of an alkali metal or an alkaline earth metal in an oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0330] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0331] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0332] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0333] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0334] (Embodiment 6) In this embodiment mode, an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed and an electronic component in which the semiconductor device is incorporated will be described.

[0335] <Semiconductor wafer> First, an example of a semiconductor wafer on which semiconductor devices and the like are formed will be described with reference to FIG. 19A.

[0336] 19A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0337] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0338] The next step is a dicing step. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) shown by dashed lines. In order to facilitate the dicing step, it is preferable that the spacing 4803 is arranged so that the multiple scribe lines SCL1 are parallel to each other, the multiple scribe lines SCL2 are parallel to each other, and the scribe lines SCL1 and SCL2 are perpendicular to each other.

[0339] By performing a dicing process, a chip 4800a as shown in FIG. 19B can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. It is preferable that the spacing 4803a is as small as possible. In this case, it is sufficient that the width of the spacing 4803 between adjacent circuit portions 4802 is approximately equal to the cutting allowance of the scribe line SCL1 or the cutting allowance of the scribe line SCL2.

[0340] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Fig. 19A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process of the element and the device for manufacturing the element.

[0341] <Electronic components> 19C shows a perspective view of an electronic component 4700 and a substrate (a mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in Fig. 19C includes a chip 4800a in a mold 4711. A memory device according to one embodiment of the present invention or the like can be used as the chip 4800a.

[0342] 19C omits a portion of electronic component 4700 in order to show the inside of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0343] 19D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 provided on interposer 4731.

[0344] The semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), etc. The semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0345] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0346] The interposer 4731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 4731, and the integrated circuits and the package substrate 4732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

[0347] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult to form with a resin interposer.

[0348] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0349] In addition, in SiP and MCM using silicon interposers, the reliability is less likely to decrease due to the difference in the expansion coefficient between the integrated circuit and the interposer. In addition, since the surface of the silicon interposer is highly flat, connection failure between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0350] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 4730. When providing a heat sink, it is preferable to make the height of an integrated circuit provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in this embodiment, it is preferable to make the height of the semiconductor device 4710 and the height of the semiconductor device 4735 uniform.

[0351] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. FIG. 19D shows an example in which electrodes 4733 are formed of solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Electrodes 4733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0352] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA. For example, a mounting method such as a Staggered Pin Grid Array (SPGA), a Land Grid Array (LGA), a Quad Flat Package (QFP), a Quad Flat J-leaded package (QFJ), or a Quad Flat Non-leaded package (QFN) can be used.

[0353] This embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0354] (Embodiment 7) In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention will be described.

[0355] The semiconductor device according to one embodiment of the present invention can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, and the like). It can also be used in image sensors, the Internet of Things (IoT), healthcare, and the like. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0356] An example of an electronic device including a semiconductor device according to one embodiment of the present invention will be described. Note that each of the electronic devices includes an electronic component 4700 or an electronic component 4730 including the semiconductor device.

[0357] [mobile phone] 20A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0358] By applying the semiconductor device according to one embodiment of the present invention, the information terminal 5500 can hold a temporary file (eg, a cache when using a web browser) generated when an application is executed.

[0359] [Wearable devices] 20B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.

[0360] Like the above-described information terminal 5500, the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0361] [Information terminal] 20C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0362] Like the information terminal 5500 described above, the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0363] In the above description, a smartphone, a wearable terminal, and a desktop information terminal are illustrated in Fig. 20A to Fig. 20C as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0364] [electric appliances] 20D illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0365] The semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the ingredients to an information terminal or the like via the Internet or the like. The electric refrigerator-freezer 5800 can hold a temporary file generated when transmitting the information in the semiconductor device.

[0366] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0367] [Game consoles] 20E illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0368] Furthermore, FIG. 20F illustrates a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 has a main body 7520 and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not illustrated in FIG. 20F, the controller 7522 can include a display unit for displaying game images, a touch panel as an input interface other than buttons, a stick, a rotary knob, a sliding knob, and the like. The shape of the controller 7522 is not limited to the shape illustrated in FIG. 20F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller with a trigger as a button and a shape imitating a gun can be used. For example, in a music game, a controller with a shape imitating a musical instrument, a musical device, or the like can be used. Furthermore, a stationary game machine may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0369] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television sets, personal computer displays, game displays, and head-mounted displays.

[0370] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the semiconductor device described in the above embodiment to the portable game machine 5200 or the stationary game machine 7500. In addition, the low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0371] Furthermore, by applying the semiconductor device described in the above embodiments to the portable game machine 5200 or the stationary game machine 7500, temporary files necessary for calculations occurring during game execution can be stored.

[0372] As an example of a game machine, a portable game machine is shown in Fig. 20E. Also, a home-use stationary game machine is shown in Fig. 20F. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include an arcade game machine installed in an entertainment facility (such as a game center or an amusement park) and a pitching machine for batting practice installed in a sports facility.

[0373] [Mobile object] The semiconductor device described in the above embodiment can be applied to automobiles, which are moving objects, and to the vicinity of the driver's seat of an automobile.

[0374] FIG. 20G illustrates an automobile 5700 as an example of a moving object.

[0375] An instrument panel that provides various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows such information may also be provided around the driver's seat.

[0376] In particular, the display device can display an image from an imaging device (not shown) provided on the automobile 5700, thereby compensating for visibility blocked by pillars and blind spots around the driver's seat, thereby improving safety. In other words, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0377] Since the semiconductor device described in the above embodiment can temporarily hold information, the computer can be used to hold necessary temporary information in an automatic driving system of the automobile 5700, a system in which the computer performs road guidance, risk prediction, and the like. The display device may be configured to display temporary information such as road guidance and risk prediction. In addition, the display device may be configured to hold video of a driving recorder provided in the automobile 5700.

[0378] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, the moving body may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc.

[0379] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0380] 20H shows a digital camera 6240 as an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, and the like, and a detachable lens 6246 is attached to the digital camera 6240. Note that, here, the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, and the like can be separately attached.

[0381] A low power consumption digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment to the digital camera 6240. In addition, the low power consumption can reduce heat generation from the circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0382] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0383] FIG. 20I illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0384] When recording a video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the above-described semiconductor device, the video camera 6300 can hold a temporary file generated during encoding.

[0385] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0386] 20J is a cross-sectional schematic diagram showing an example of an ICD. An ICD body 5400 has at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0387] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0388] The ICD main body 5400 has a function as a pacemaker, and performs pacing on the heart when the heart rate is out of a specified range. In addition, if the heart rate does not improve by pacing (fast ventricular tachycardia or ventricular fibrillation, etc.), treatment with an electric shock is performed.

[0389] The ICD main body 5400 needs to constantly monitor the heart rate in order to perform pacing and electric shock appropriately. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. In addition, the ICD main body 5400 can store in the electronic component 4700 the heart rate data acquired by the sensor, the number of times pacing treatment was performed, the time, and the like.

[0390] Moreover, the antenna 5404 can receive power, which is then charged in the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can still function, so that the ICD main body 5400 also functions as an auxiliary power source.

[0391] In addition to the antenna 5404 capable of receiving power, an antenna capable of transmitting physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0392] [Extension device for PC] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0393] Fig. 21A shows, as an example of such an expansion device, an expansion device 6100 that is portable and equipped with a chip capable of storing information and that is attached externally to a PC. The expansion device 6100 can store information using the chip by connecting to a PC, for example, via a Universal Serial Bus (USB). Note that, although Fig. 21A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0394] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with a circuit for driving the semiconductor device described in the above embodiment. For example, an electronic component 4700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0395] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card which can be attached to electronic devices such as information terminals and digital cameras.

[0396] FIG. 21B is a schematic diagram of the appearance of an SD card, and FIG. 21C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a board 5113. The connector 5112 functions as an interface for connecting to an external device. The board 5113 is housed in the housing 5111. The board 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the board 5113 is provided with an electronic component 4700 and a controller chip 5115. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and may be changed as appropriate depending on the situation. For example, a write circuit, a row driver, a read circuit, and the like provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 4700.

[0397] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip having a wireless communication function may be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and allows data to be read and written to the electronic component 4700.

[0398] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0399] FIG. 21D is a schematic diagram of the appearance of an SSD, and FIG. 21E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the substrate 5153 is provided with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing the electronic component 4700 on the back side of the substrate 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0400] [Calculator] 22A is an example of a large-scale computer. The computer 5600 includes a rack 5610 and a plurality of rack-mounted computers 5620 stored therein.

[0401] The computer 5620 can have the configuration shown in the perspective view of Fig. 22B, for example. In Fig. 22B, the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0402] A PC card 5621 shown in FIG. 22C is an example of a processing board including a CPU, a GPU, a semiconductor device, and the like. The PC card 5621 has a board 5622. The board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that FIG. 22C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 may be referred to.

[0403] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0404] The connection terminals 5623, 5624, and 5625 can be interfaces for supplying power and inputting signals to the PC card 5621, for example. They can also be interfaces for outputting signals calculated by the PC card 5621, for example. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0405] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0406] The semiconductor device 5627 has a plurality of terminals, and the terminals can be soldered, for example, by reflow soldering, to wiring provided on the board 5622, so that the semiconductor device 5627 and the board 5622 can be electrically connected to each other. Examples of the semiconductor device 5627 include a field programmable gate array (FPGA), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0407] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to each other by, for example, soldering the terminals to wiring of the board 5622 by a reflow method. The semiconductor device 5628 can be, for example, a semiconductor device. For example, the electronic component 4700 can be used as the semiconductor device 5628.

[0408] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference of artificial intelligence, for example.

[0409] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, the electronic devices can be made smaller, faster, or consume less power. Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, so heat generation from a circuit can be reduced. Therefore, adverse effects of the heat on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, an electronic device that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be improved.

[0410] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. EXAMPLES

[0411] 1A was verified using a circuit simulator. SmartSpice from SILVACO Corporation was used as the circuit simulator.

[0412] As the verification conditions, the transistors Tr11 and Tr21 were assumed to be OS transistors with a channel length and width of 60 nm. The transistors Tr12 and Tr22 were assumed to be Si transistors with a channel length and width of 1 μm. The capacitance values ​​of the capacitors Cb1 and Cb2 were each set to 1 pF. VSS was set to 0.0 V and VDD was set to 6.0 V.

[0413] We assumed five levels of Vin1 held at node SN1 (0.9V, 1.1V, 1.3V, 1.5V, 1.7V) and two levels of Vref held at node SN2 (0.0V, 0.7V), and calculated the output voltage Vout for all combinations using a circuit simulator. Each of the five levels of Vin1 satisfies the formula 6 and formula 7 shown in the above embodiment.

[0414] The calculation results are shown in Figures 23A and 23B. The vertical axis of Figures 23A and 23B indicates the output voltage Vout, and the horizontal axis indicates time. In this example, it is assumed that the write operation described in the above embodiment is completed at time 0.0 μs. More specifically, it is assumed that the period T32 described in the above embodiment is completed, and the potentials of the nodes SN1 and SN2 are maintained.

[0415] 23A shows the output voltage Vout for each Vin1 level when Vref is 0.7 V. FIG 23B shows the output voltage Vout for each Vin1 level when Vref is 0.0 V.

[0416] In the semiconductor device 100, VSS is supplied to the terminals PS1 and PS2 until time 0.5 μs. At time 0.5 μs, the read operation starts. During the read operation, VDD is supplied to the terminal PS1, and the output voltage Vout is supplied to the terminal OUT.

[0417] 24 shows the calculation result of the source-drain voltage Vds_Tr12 of transistor Tr12 after the start of the read operation. Since the potential of node BN is VSS (0.0 V) until just before the start of the read operation, Vds_Tr12 is approximately 6 V immediately after the potential of terminal PS1 changes from VSS to VDD (6.0 V).

[0418] Furthermore, because Vin1 is equal to or greater than the threshold voltage of transistor Tr12, when the potential of terminal PS1 becomes VDD, a current flows between the source and drain of transistor Tr12, causing the potential of node BN to rise. The larger Vin1 is, the greater the current that flows between the source and drain of transistor Tr12. Therefore, the larger Vin1 is, the higher the potential of node BN becomes. In other words, the larger Vin1 is, the smaller Vds_Tr12 becomes. As a result, when Vref is constant, the larger Vin1 is, the larger Vout becomes.

[0419] 23A and 23B show that a voltage corresponding to the formula 5 described in the above embodiment is obtained as the output voltage Vout. In this embodiment, Vin2 included in the formula 5 corresponds to Vref.

[0420] 25 is a graph showing the relationship between Vin1 and Vout calculated by a circuit simulator. In the figure, a circle ("○") indicates the relationship between Vin1 and Vout when Vref is 0.0V, and a square ("□") indicates the relationship between Vin1 and Vout when Vref is 0.7V.

[0421] 25 also shows approximate lines 851 and 852. Approximate line 851 is the aforementioned circle ("○") approximation line, and approximates the relationship between Vin1 and Vout when Vref is 0.0V. Approximate line 852 is the aforementioned square ("□") approximation line, and approximates the relationship between Vin1 and Vout when Vref is 0.7V. The coefficient of determination R of approximate line 851 is 2 (Contribution ratio) is 0.9966, and the coefficient of determination R of the approximation line 852 2The contribution rate was 0.9955. This shows that when Vref is constant, the output voltage Vout also changes in response to changes in Vin1.

[0422] By verification using a circuit simulator, it was found that in the semiconductor device 100 according to an embodiment of the present invention, when Vref is constant, the output voltage Vout also changes in response to a change in Vin1. It was also found that the semiconductor device 100 according to an embodiment of the present invention can accurately read out the analog data held therein. [Explanation of symbols]

[0423] 100: semiconductor device, 110a: holding circuit, 110b: holding circuit, 120a: bootstrap circuit, 120b: bootstrap circuit, 130: source follower circuit, Tr11: transistor, Tr12: transistor, Tr21: transistor, Tr22: transistor, SN1: node, SN2: node, BN: node, Cb1: capacitance element, Cb2: capacitance element, IN1: terminal, IN2: terminal, PS1: terminal, PS2: terminal, WW1: terminal, WW2: terminal

Claims

1. A semiconductor device including first to fifth circuits, first to fourth transistors, a first capacitance element, and a second capacitance element, the first circuit has a function of holding a first potential; the second circuit has a function of boosting the first potential, the third circuit has a function of holding a second potential; the fourth circuit has a function of boosting the second potential, The fifth circuit is a function of outputting a third potential corresponding to a potential difference between the boosted first potential and the boosted second potential; the first circuit includes the first transistor and the first capacitive element, the second circuit includes the second transistor and the first capacitive element, the third circuit includes the third transistor and the second capacitive element, the fourth circuit includes the fourth transistor and the second capacitive element, The fifth circuit includes the second transistor and the fourth transistor.

2. In claim 1, The first transistor and the third transistor are semiconductor devices in which a channel is formed and the semiconductor contains an oxide semiconductor.

3. In claim 2, The second transistor and the fourth transistor are semiconductor devices in which a channel is formed and the semiconductor contains an oxide semiconductor.

4. In claim 2 or 3, The semiconductor device, wherein the oxide semiconductor contains at least one of indium and zinc.

5. The transistor includes first to fourth transistors, a first capacitance element, and a second capacitance element, one of a source and a drain of the first transistor is electrically connected to a first terminal; the other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; a gate of the first transistor electrically connected to a second terminal; one of a source and a drain of the third transistor is electrically connected to a third terminal; the other of the source and the drain of the third transistor is electrically connected to the gate of the fourth transistor; a gate of the third transistor electrically connected to a fourth terminal; one of a source and a drain of the second transistor is electrically connected to a fifth terminal; the other of the source and the drain of the second transistor is electrically connected to a seventh terminal; one of a source and a drain of the fourth transistor is electrically connected to a sixth terminal; the other of the source and the drain of the fourth transistor is electrically connected to the seventh terminal; one electrode of the first capacitance element is electrically connected to a gate of the second transistor; the other electrode of the first capacitance element is electrically connected to the seventh terminal; one electrode of the second capacitance element is electrically connected to a gate of the fourth transistor; the other electrode of the second capacitive element is electrically connected to the seventh terminal.

6. In claim 5, The semiconductor device is configured such that analog data is supplied to the first terminal.

7. In claim 5 or claim 6, The third terminal and the sixth terminal are electrically connected to each other.

8. In any one of claims 5 to 7, The first transistor and the third transistor are semiconductor devices each including an oxide semiconductor in a semiconductor layer in which a channel is formed.

9. In claim 8, The second transistor and the fourth transistor are semiconductor devices each including an oxide semiconductor in a semiconductor layer in which a channel is formed.

10. In claim 8 or claim 9, The semiconductor device, wherein the oxide semiconductor contains at least one of indium and zinc.

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