A voltage boosting circuit

Abstract

A boosting circuit (102, 103, 104, 105, 106, 107) for providing a boosted signal voltage (108) for driving a switch of a CDAC is disclosed. It comprises an inverter stage (102, 103) comprising a first inverter (102) connected in series with a second inverter (103). The first inverter (102) is arranged for receiving an input control signal voltage. An output of said second inverter (103) is connected to a storage capacitor (107). It further comprises a charge pump (104, 105, 106). The storage capacitor (107) has an input branch connected to said output of said second inverter (103) and an output branch connected to said charge pump (104, 105, 106). Said output branch is arranged to be connected to said switch of said CDAC. The charge pump (104, 105, 106) is arranged to connect a shift voltage to said output branch of said storage capacitor (107) during an OFF-phase of said input control signal voltage and disconnect said shift voltage from said output branch of said storage capacitor (107) during an ON-phase of said input control signal voltage. The first inverter (102) is biased between a supply voltage (110) and a low voltage, said first low voltage (111) being higher than zero volt.

Description

[0001] A Voltage Boosting Circuit

[0002] Technical field

[0003] The present disclosure generally relates to the field of clock circuits and, more specifically, to a clock boosting circuit for boosting the drive voltage of switches in a Capacitive Digital-to-Analog Converter, CDAC.

[0004] Background

[0005] The present disclosure relates to the field of data converters like Digital- to-Analog converters, DACs and, more specifically, to Capacitive Digital-to-Analog Converters, CDACs. DACs often play an important role in electronic systems, where the need to convert digital signals into analog voltages is required. Such conversion may be required for various applications, including audio reproduction, communication systems, control systems, and scientific instrumentation.

[0006] Conventional DACs, such as Resistor Digital-to-Analog Converters, RDACs, have been widely utilized for many years. RDACs employ a string of resistors to convert digital data into analog voltages, but they suffer from inherent limitations, particularly in terms of power consumption and precision. As technology demands ever-increasing resolutions and efficiency, the shortcomings of RDACs have prompted researchers and engineers to explore alternative solutions.

[0007] The Capacitor Digital-to-Analog Converter, CDAC, addresses these challenges and represents a significant improvement in digital-to-analog conversion technology. CDACs operate on a fundamentally different principle than RDACs, employing an array of capacitors to perform the conversion process. Each capacitor in the array corresponds to a specific digital input bit, and the voltage across each capacitor determines the analog output level.

[0008] The CDACs principle is founded upon the ability of capacitors to store electric charge, making them ideal for precise analog voltage generation. By controlling the charge stored within each capacitor, CDACs can accurately represent a wide range of analog output values corresponding to the digital input, ensuring high fidelity and linearity. One of the advantages of CDACs is their scalability and resolution. Unlike RDACs, which require a growing number of resistors to achieve higher resolution, CDACs can be easily augmented with additional capacitors to achieve finer granularity in the analog output voltage. This scalability enables CDACs to cater to various application scenarios, from low-resolution consumer electronics to ultra-high precision scientific instruments.

[0009] Advanced CMOS process technologies in the nano-scale range may have low gate overdrive voltage. Not scaling the threshold voltages of mixed-signal devices as fast as supply voltages makes the analog and mixed-signal design more difficult in deep-submicron CMOS technologies.

[0010] To have a reliable design that technology limits, it may be of importance to take into account device breakdown mechanism. The Vgs, gate-source voltage, and Vgd, gate-drain voltage, are typically limited by gate oxide breakdown. Device damage and performance degradation are the result of this breakdown. If the Vgs, Vgd, and Vds, drain-source voltage, are kept within the supply voltage Vdd, the device reliability can be assured. Some techniques to increase the Vgs are proposed like boosting circuits, bootstrapping and charge pump-based circuits.

[0011] Such boosting circuits may especially be useful in combination with Capacitive Digital-to-Analog Converters, CDACs. There is a need for an improved boosting circuit with a reduced number of components while the boosting is done adequately.

[0012] Summary

[0013] It is an object of the present disclosure to provide for a boosting circuit for boosting an input control signal voltage thereby providing a boosted signal voltage for driving a switch of a Capacitive Digital to Analog Converter, CDAC. Further objects include associated devices as well as an associated method.

[0014] In a first aspect of the present disclosure, there is provided a boosting circuit for boosting an input control signal voltage thereby providing a boosted signal voltage for driving a switch of a Capacitive Digital to Analog Converter, CDAC.

[0015] The boosting circuit comprising an inverter stage comprising a first inverter connected in series with a second inverter, wherein the first inverter is arranged for receiving said input control signal voltage, and wherein an output of said second inverter is connected to a storage capacitor.

[0016] The boosting circuit further comprising a charge pump and comprising a storage capacitor having an input branch connected to said output of said second inverter and having an output branch connected to said charge pump, and wherein said output branch is arranged to be connected to said switch of said CDAC.

[0017] The charge pump is arranged to connect a shift voltage to said output branch of said storage capacitor during an OFF-phase of said input control signal voltage thereby charging said storage capacitor to said shift voltage Vshift, and is arranged to disconnect said shift voltage from said output branch of said storage capacitor during an ON-phase of said input control signal voltage.

[0018] The first inverter is biased between a supply voltage and a first low voltage, said first low voltage being higher than ground.

[0019] The inventor has found that it may be beneficial to boost the voltage at the output branch, as the boosted voltage is provided to the gate of the switch comprised by, for example, the CDAC.

[0020] The boosting circuit operates in two different phases, which may be explained as follows.

[0021] First, the situation is considered wherein the control signal is a clock signal, and considering first that the clock input is low. In this particular case, the first inverter will provide a high voltage, for example Vdd, to the input of the second inverter. The second inverter will provide a second low voltage to the input branch of the storage capacitor. The second low voltage may, for example, be zero volt, depending on the biasing of the second inverter.

[0022] During this situation, i.e. when the clock input is low (the OFF-phase of the clock signal), a shift voltage Vshift is connected to the output branch of the storage capacitor. This will ensure that the storage capacitor is charged to the shift voltage Vshift. As such, during the OFF-phase of the clock signal, the shift voltage Vshift is to be provided to the switch of the CDAC.

[0023] Second, the situation is considered wherein the clock input is high, for example equals the supply voltage Vdd. In this particular case, the first inverter will provide a first low voltage V|OWto the input of the second inverter. The second inverter will thus provide a high voltage to the input branch of the storage capacitor. The high voltage may, for example, be Vdd.

[0024] During this situation, i.e. when the clock input is high (the ON-phase of the clock signal), the shift voltage Vshift is disconnected from the output branch of the storage capacitor. The result is that the output branch of the capacitor is voltage boosted. The boosted voltage will then equal the shift voltage Vshift plus the high voltage provided by the second inverter Vdd. This boosted voltage is to be provided to the switch of the CDAC.

[0025] In accordance with the present disclosure, the first inverter is biased between a high voltage, for example the supply voltage Vdd, and a first low voltage Viow. The first low voltage V|OWis higher than zero volt.

[0026] The inventors have found that the boosted voltage at the output branch of the storage capacitor may result in a gate-source voltage, Vgs, of a switch in the charge pump to exceed the supply voltage Vdd thereby risking to break the corresponding switch. In order to combat that potential risk, it was found to not bias the first inverter to zero volt, but to a first low voltage V|OWhigher than zero volt. This would make the voltage difference between this first low voltage V|OWand the boosted voltage smaller, thereby reducing the risk of failure in any of the switches in the charge pump.

[0027] Following the above, the first inverter may be biased between a first low voltage V|OW(logic low level) and the supply voltage Vdd (logic high level). This means that the output of the first inverter varies between the first low voltage level V|OW, which is higher than zero volt, and the supply voltage level Vdd.

[0028] The second inverter may be biased between zero volt and the supply voltage Vdd (logic high level). In this case, the input of the second inverter is connected to a signal that varies between the low voltage V|OWand the supply voltage level Vdd . The output of the second inverter varies between zero volt and the supply voltage level Vdd.

[0029] The underlying concept of the above described example is that the first low voltage V|OWbiasing of the first inverter reduces the voltage over a switch in the charge pump when a boosted voltage is provided at the output branch of the storage capacitor. The maximum voltage of this particular switch may be determined by subtracting the first low voltage V|OWfrom the boosted voltage. The first low voltage may, preferably, be chosen such that the above identified maximum voltage is lower than the supply voltage thereby reducing the risk of failure of the corresponding switch.

[0030] In accordance with the present disclosure, a charge pump is comprised by the boosting circuit. Following the above, the charge pump effectively operates in two main phases: the charging phase and the discharging phase. During the charging phase, the charge pump accumulates charge on the storage capacitor by connecting the storage capacitor to the shift voltage Vshift- Then, during the discharging phase, the charge pump switches the storage capacitor in series with the load, in this case, the output of the second inverter, and disconnects the output branch of the storage capacitor from the shift voltage Vshift, thereby effectively boosting the voltage level.

[0031] It is noted that the present disclosure is directed to a boosting circuit for boosting an input control signal voltage. The input control signal may be related to a clock signal or a data signal.

[0032] In the present disclosure, the wording shift voltage is used as a descriptive label to identify a particular voltage. The shift voltage may be provided by a voltage source, identified as a shift voltage source.

[0033] In an example, the charge pump comprises: a Complementary metal oxide semiconductor, CMOS, inverter comprising a P-Metal Oxide Semiconductor, P-MOS, Field Effect Transistor, FET and an N-MOS FET, wherein a source of said PMOS FET is connected to said output branch of said storage capacitor, wherein an input of said CMOS inverter is connected to said output of said first inverter.

[0034] The CMOS inverter, also known as a complementary metal-oxide- semiconductor inverter, is typically a digital logic gate that performs the basic logic function of inversion. The CMOS inverter is constructed using complementary MOSFET pairs, consisting of both an N-channel MOSFET and a P-channel MOSFET.

[0035] The NMOS conducts when its gate voltage is high, while the PMOS conducts when its gate voltage is low. By arranging these MOSFETs in a specific configuration, the CMOS inverter can effectively switch between two complementary output voltage levels: a high voltage level and a low voltage level.

[0036] When the input to the CMOS inverter is at a logic low, i.e. the first low voltage V|OWprovided by the first inverter, the NMOS is turned off, and the PMOS is turned on. Conversely, when the input is at a logic high, for example equal to the supply voltage Vdd, the NMOS is turned on, connecting the output of the CMOS inverter to zero volt.

[0037] The present disclosure is especially useful for protecting the P-MOS FET of the above identified CMOS inverter. By ensuring that the gate-source voltage of this particular P-MOS FET is reduced, a potential break down of the P-MOS FET is prevented.

[0038] The first low voltage output of the first inverter is provided to the gate terminal of the P-MOS FET when the boosted voltage is present at the source terminal of the P-MOS FET. By ensuring that the first low voltage output of the first inverter is larger than zero volt, the gate-source voltage of the P-MOS FET is reduced.

[0039] It is noted that it may be beneficial to ensure that the first low voltage Viow with which the first inverter is biased, is lower than a threshold voltage of the N- MOS FET of the CMOS inverter.

[0040] This will ensure that the N-MOS FET will not start conducting when a first low voltage is provided to the corresponding gate terminal of the N-MOS FET. The underlying idea is that the P-MOS FET will conduct when the input of the CMOS inverter is low.

[0041] A threshold voltage refers to the gate-source voltage level at which the MOSFET starts to conduct current between its drain and source terminals.

[0042] In more technical terms, the threshold voltage represents the gate voltage required to create an inversion layer in the semiconductor channel between the source and drain regions of the MOSFET. This inversion layer allows the flow of charge carriers, i.e. electrons or holes, to form a conductive channel, enabling current flow between the drain and source terminals.

[0043] For an N-MOS FET, the threshold voltage is positive, and when the gatesource voltage exceeds this value, the MOSFET starts conducting current. Conversely, for a P-MOS FET, the threshold voltage is negative, and the MOSFET begins conducting when the gate-source voltage falls below this negative value.

[0044] Typical threshold voltage values for N-MOS FETs in CMOS technologies are usually in the range of 0.2 to 0.6 volts. In a further example, the first low voltage V|OWis at least equal to the shift voltage Vshitt- This would make sure that the gate-source voltage of the P-MOS FET is lower than the supply voltage.

[0045] It is noted that the boosting circuit may comprise the shift voltage source that is arranged for providing the shift voltage Vshitt-

[0046] It may be advantageous if the shift voltage Vshift is equal or lower than said first low voltage V|OW, and said first low voltage V|OWis equal or lower than said threshold voltage of said NMOS FET of said CMOS inverter.

[0047] In a second aspect of the present disclosure, there is provided a capacitive Digital to Analog Converter, CDAC, assembly comprising a boosting circuit in accordance with any of the previous examples and comprising: a CDAC comprising a plurality of capacitors for converting a digital input code to an analog output voltage.

[0048] It is noted that the advantages as explained with reference to the first aspect of the present disclosure, being the boosting circuit for boosting a voltage, are also applicable to the second aspect of the present disclosure, being the CDAC assembly.

[0049] Using a boosting circuit to provide a higher voltage to the gate of a MOSFET in a Capacitive Digital-to-Analog Converter, CDAC, may be advantageous to reduce the on-resistance of the corresponding MOSFET.

[0050] When a MOSFET operates in its "on" state, it typically acts as a low- resistance channel between its drain and source terminals, allowing current to flow. However, the MOSFET's on-resistance, i.e. Rds(on), is typically not constant and can vary depending on several factors, including the gate-source voltage.

[0051] By applying a higher voltage to the MOSFET gate through the boosting circuit, the MOSFET can operate such that it has relatively low on-resistance values.

[0052] Reducing the on-resistance of the MOSFET is advantageous for multiple reasons.

[0053] A lower on-resistance results in reduced power dissipation across the MOSFET, leading to higher power efficiency in the CDAC circuit. This may especially be of importance in battery-operated devices and energy-efficient systems. A lower on-resistance means the MOSFET dissipates less heat during operation. This translates to lower thermal stress on the MOSFET and the surrounding components, enhancing the overall reliability and longevity of the CDAC.

[0054] Lower on-resistance reduces voltage drops across the MOSFET, ensuring that a higher percentage of the supply voltage is available for the conversion process. This helps maintain accuracy in the analog output voltage and minimizes the impact of power supply variations.

[0055] A lower on-resistance results in reduced signal distortion, allowing the CDAC to provide a more faithful representation of the digital input as an analog output signal.

[0056] In a specific example, the CDAC comprises a plurality of Field Effect Transistors, FETs, wherein each of said plurality of FETs is arranged to connect one of said plurality of capacitors to a voltage.

[0057] In another example, each of said plurality of FETs is arranged to connect one of said plurality of capacitors to a voltage, said voltage being any of: a common-mode voltage; an input voltage; a reference voltage.

[0058] The common-mode voltage, i.e. Vcm, is typically the voltage level that appears at the common node of the capacitors in the CDAC circuit. This common node is typically connected to the output of the inverter chain, which is used to control the charging and discharging of the capacitors.

[0059] The common-mode voltage is used for maintaining the proper operating range of the CDAC circuit. It may ensure that the capacitors stay within the valid voltage range during the digital-to-analog conversion process. Any deviation of the common-mode voltage from its specified value could result in non-linearities, reduced dynamic range, or potential distortion in the analog output signal.

[0060] The input voltage, i.e. Vin, in a CDAC may refer to the analog input voltage of the SAR ADC.

[0061] In a typical example, the capacitive DAC comprises a plurality of capacitors cascaded in parallel. The above referenced shared terminal, i.e. the common terminal, may be connected to the input of a comparator. The free ends of the capacitors may be connected to an analog input voltage, to a reference voltage or to a common-mode voltage.

[0062] In an acquisition phase, the common terminal may be connected to common-mode voltage and all free terminals of the capacitors may be connected to the input voltage. Once the acquisition phase has completed, the common terminal may be disconnected from common-mode voltage, and the free terminals of the capacitors, i.e. the bottom-plate of the capacitors, may be disconnected from the input voltage. This effectively traps a charge proportional to the input voltage on the plurality of capacitors. The free terminals of the capacitors may then be connected to commonmode voltage, such that the common terminal voltage is driven to a negative voltage.

[0063] In a first step, the free end of the capacitor resembling the Most Significant Bit, MSB, is disconnected from the common-mode voltage and may be connected to a reference voltage. This effectively drives the common terminal of the plurality of capacitors in a positive direction by an amount that may be equal to half the reference voltage.

[0064] The comparator may compare the voltage at the common terminal of the plurality of capacitors with a common-mode voltage. A logic “1” will appear at the output of the comparator if the voltage at the common terminal is smaller than the common-mode voltage. If that’s the case, then the bottom plate of the next capacitor will be connected to the reference voltage, etc. This process may continue until all the bits have been determined.

[0065] In an example, the output branch of said storage capacitor is connected to one or more gate terminals of said plurality of FETs of said CDAC.

[0066] In a further example, the boosting circuit further comprises a shift voltage source arranged for providing said shift voltage Vshift, and wherein said provided shift voltage Vshift is equal to, or lower than, said reference voltage.

[0067] In a third aspect of the present disclosure, there is provided a Successive-Approximation-Register, SAR, Analog-to-Digital Converter, ADC, SAR- ADC comprising a CDAC assembly in accordance with any of the previous examples.

[0068] In a fourth aspect of the present disclosure, there is provided a receiver comprising such an SAR-ADC.

[0069] In a fifth aspect of the present disclosure, there is provided an electronic apparatus comprising such a SAR-ADC. The electronic apparatus may, for example, be a communication apparatus like a User Equipment, UE, for a cellular communications system or a radio base station for a cellular communications system.

[0070] In another aspect of the present disclosure, there is provided a method of operating a boosting circuit in accordance with any of the previous examples, wherein said method comprises the steps of: connecting a shift voltage Vshift to said output branch of said storage capacitor during an OFF-phase of said input control signal voltage thereby charging said storage capacitor to said shift voltage; disconnecting said shift voltage Vshift from said output branch of said storage capacitor during an ON-phase of said input control signal voltage; wherein said method further comprises the step of: biasing said first inverter between a supply voltage dd and a first low voltage V|OW, said first low voltage V|OWbeing higher than zero volt.

[0071] In the appended figures, similar components and / or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

[0072] The above and other aspects of the disclosure will be apparent from and elucidated with reference to the examples described hereinafter.

[0073] Brief description of the drawings

[0074] Fig. 1 discloses a single-ended CDAC in accordance with the prior art;

[0075] Fig. 2 discloses a boosting circuit in accordance with the present disclosure;

[0076] Fig. 3 discloses a timing diagram of the boosting circuit in accordance with the present disclosure;

[0077] Fig. 4 discloses a flow chart of a method in accordance with the present disclosure; Fig. 5 discloses an electronic apparatus in accordance with the present disclosure.

[0078] Detailed description

[0079] It is noted that in the description of the figures, same reference numerals refer to the same or similar components performing a same or essentially similar function.

[0080] A more detailed description is made with reference to particular examples, some of which are illustrated in the appended drawings, such that the manner in which the features of the present disclosure may be understood in more detail. It is noted that the drawings only illustrate typical examples and are therefore not to be considered to limit the scope of the subject matter of the claims. The drawings are incorporated for facilitating an understanding of the disclosure and are thus not necessarily drawn to scale. Advantages of the subject matter as claimed will become apparent to those skilled in the art upon reading the description in conjunction with the accompanying drawings.

[0081] The ensuing description above and below provides preferred exemplary embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment of the disclosure, it being understood that various changes may be made in the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the disclosure.

[0082] Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” As used herein, the terms “connected,” “coupled,” or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, electromagnetic, or a combination thereof. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or,” in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0083] Embodiments of the particular invention are specifically useful in combination with a capacitive Digital-to-Analog Converter, CDAC. A Capacitive Digital-to-Analog Converter, CDAC, is a type of digital-to-analog converter that converts digital signals into analog signals using capacitors. It's commonly used in applications such as digital communication systems, instrumentation, and analog signal processing.

[0084] In the following, embodiments are described in the context of a capacitive DAC, CDAC, being a sub component of a Successive Approximation Register Analog-to-Digital Converter, SAR ADC. Fig. 1 shows a schematic 1 of the capacitive DAC, CDAC, adjusted to bottom-plate, BP, sampling where the analog input 2 is sampled on the bottom plate of the capacitor bank during sampling phase while the top-plate, TP, of the capacitor may be connected to Vcm3.

[0085] The above referenced analog input 2 may be the analog input 2 of the corresponding SAR ADC that comprises the capacitive DAC. The analog input signal 2 thus represents the analog signal that is to be converted to a digital signal by the SAR ADC.

[0086] When sampling is completed, the bottom plate of the capacitors may first be connected to common-mode voltage Vcmand may then be switched consecutively to either positive reference voltage Vref_P4 or negative reference voltage Vref_m 5, depending on the digital output of the SAR logic. To provide maximum switch overdrive voltage and consequently reduce the switches on-resistance, Vdd and Vss, being a zero voltage source, can also be used as Vref_Pand Vref_m, respectively.

[0087] One of the techniques that is being used in the conversion process is referred to as the bottom plate sampling technique, as shown in Fig. 1.

[0088] The basic CDAC structure typically comprises an array of capacitors, each corresponding to a specific bit of the digital input. The capacitors are connected in parallel to a common node, which is the analog output node, that is to be connected to the input of the comparator. The other terminals of each capacitor are connected to switches, controlled by the controlling signals of the digital logic, i.e. the digital signal coming from the SAR logic of the SAR ADC.

[0089] In bottom plate sampling, the term "bottom plate" refers to one of the plates of each capacitor in the CDAC.

[0090] When a specific digital code is applied to the CDAC's switches, the corresponding switches are closed, connecting the capacitors associated with the active bits to either Vcm, the Vref_p or Vref_m.

[0091] In essence, a charge redistribution will take place among the capacitors resulting in an analog voltage that is input to the comparator. The charge redistribution is controlled by connecting the bottom plates of the capacitors to the different voltages Vcm, the Vref_p or Vref_m, which is based on controlling signals which control the switches.

[0092] It is explicitly noted that the present disclosure is not limited to bottom plate sampling as discussed above. This technique is merely described to provide a topology that benefits from the invention set forward in this disclosure.

[0093] Fig. 2 discloses 101 a boosting circuit in accordance with the present disclosure.

[0094] The boosting circuit is arranged to boost the gate of CDAC switches and results in increasing the overdrive voltages. In conclusion, the on-resistance of the switches is decreased compared to when the switches are driven by supply voltage.

[0095] The boosting circuit comprises a pair of inverters 102, 103, two PMOS transistors 104, 105 and one NMOS transistor 106 and a storage capacitor 107 to provide the gate-boosting voltage to the CDAC switches 113. The boosting circuit has two output ports, boosted supply 108 and boosted clock 109. The boosted supply 108 is the output port used in the embodiments disclosed herein.

[0096] The above is explained in detail here below.

[0097] A CDAC is used as one of the main building blocks in SAR ADCs. Designing a low resistance and linear enough switch which will drive the CDAC may have a significant effect on the ADC performance. Especially designing the switches in low-voltage regimes becomes challenging because of their low overdrive voltages that result in high on-resistance.

[0098] Fig. 2 shows the boosting circuit 101 in accordance with embodiments of the present disclosure and a model of the CDAC and the voltage boosting circuit. The voltage boosting circuit comprises the switches M1-M3 104, 105, 106 which behave as a charge pump, storage capacitor C 107, and two inverters 102, 103. The first inverter 102 is biased between Vdd 110 and V|OW111 and its output drives the gates of the switches Mi 106 and M2 104.

[0099] Viow 111 is higher than zero volt 112, preferably equal or larger than Vshift 114, to ensure that the Vgsof M2 104 does not exceed the supply voltage and break the M2. As a result, the Vgsof M2 104 may be kept below or within Vdd 110.

[0100] The second inverter 103 is typically biased between dd 110 and zero volt 112 and the second inverter 103 may be stronger than the first inverter 102 as the second inverter 103 is to drive the storage capacitor C 107.

[0101] The boosting circuit works in two phases; when the control input 115 is low, for example zero, the gate of Mi and M2 is connected to Vdd. As the initial voltage of the storage capacitor is zero and the gate of M2 is connected to Vdd, M2 is off, and the Clkboosted port 109 is connected to zero volt through Mi.

[0102] This turns M3 on and as a result, the boosted signal voltage port 108, Vboosted, is connected to the voltage source, Vshift. The capacitor will then be charged tO Vshift-

[0103] When choosing the Vshift value, it may be noted that the Vgsof M4 should preferably not exceed the Vdd. That means the Vshift should preferably be less than Vref_Pwhen Vref_Pis connected to the source of M4 and less than Vref_m when Vref_m is connected to the source of M4.

[0104] Once the control signal goes up, the gate of Mi and M2 are connected to Viow which is preferably less than Vth of the Mi such that Mi is turned off. The voltage over the storage capacitor is then equal to Vdd + Vshift and causes the M2 to turn on.

[0105] As a result, the Clkboosted and Vboosted are connected through M2 and turn M3off and Clkboosted and Vboosted are boosted to Vdd + Vshift.

[0106] Thus, the gate of M4 which models the CDAC switches is boosted to Vdd + Vshift, and the switch on-resistance reduces. It is further noted that the gate-source voltage of M2 is Vdd + Vshift - V|OW. The voltage V|OWis the voltage with which the first inverter is biased. By choosing V|OWappropriately, it may be ensured that the gate-source voltage of M2 does not exceed Vdd to thereby ensure that the M2 will not break down during operation.

[0107] Fig. 3 shows the timing diagrams 201 associated with the boosting circuit, wherein the shift voltage VShift=275mV.

[0108] The control input, being a clock signal, is indicated with reference numeral 202. The boosted clock signal Cl kboosted is indicated with reference numeral 203 and the boosted signal voltage boosted is indicated with reference numeral 204.

[0109] The circuit drives the switch M4 with a source voltage chosen as Vref_m=275rnV. When the Clk is low, Cl kboosted is “0” and Vboosted is very close to Vshift, i.e. 275mV, which turns off M4, i.e. Vgs=0V. Once the control signal goes high, both voltages reach about Vdd + Vshift, which equals 750mV+275mV, and M4 is turned on, i.e. Vgs=750mV. This demonstrates that the Vgsof the CDAC switch is maximized to 750mV, improved gate overdrive, which leads to the reduced on-resistance of the switch.

[0110] Fig. 4 discloses a flow chart 301 of a method in accordance with the present disclosure.

[0111] The flow chart is related to a method of operating a boosting circuit in accordance with any of the examples provided above.

[0112] The method comprises a step of connecting 302 a shift voltage to said output branch of said storage capacitor during an OFF-phase of said input control signal voltage thereby charging said storage capacitor to said shift voltage.

[0113] The method further comprises a step of disconnecting 303 said shift voltage from said output branch of said storage capacitor during an ON-phase of said input control signal voltage.

[0114] The method also comprises the step of biasing 304 said first inverter between a supply voltage and a first low voltage, said first low voltage being higher than zero volt.

[0115] Fig. 5 discloses an electronic apparatus in accordance with the present disclosure.

[0116] The electronic apparatus 42 comprises an input terminal 44, an input device 43, an output terminal 46 and an output device 45. The electronic apparatus may further comprise a processor 47 connected to a memory 48.

[0117] On top of the above, the electronic apparatus may comprise a CDAC as indicated with reference numeral 49. The CDAC comprises a boosting circuit in accordance with the present disclosure.

[0118] The electronic apparatus 42 may be a communication apparatus such as a User Equipment, UE, or a base station like an eNodeB or a gNodeB.

[0119] It should be noted that the above-mentioned examples illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative examples without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims.

[0120] Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

CLAIMS1. A boosting circuit (102, 103, 104, 105, 106, 107) for boosting an input control signal voltage thereby providing a boosted signal voltage (108) for driving a switch of a Capacitive Digital to Analog Converter, CDAC, said boosting circuit (102, 103, 104, 105, 106, 107) comprising: an inverter stage (102, 103) comprising a first inverter (102) connected in series with a second inverter (103), wherein the first inverter (102) is arranged for receiving said input control signal voltage, and wherein an output of said second inverter (103) is connected to a storage capacitor (107); a charge pump (104, 105, 106); said storage capacitor (107) having an input branch connected to said output of said second inverter (103) and having an output branch connected to said charge pump (104, 105, 106), and wherein said output branch is arranged to be connected to said switch of said CDAC; wherein said charge pump (104, 105, 106) is arranged to connect a shift voltage to said output branch of said storage capacitor (107) during an OFF-phase of said input control signal voltage thereby charging said storage capacitor (107) to said shift voltage; disconnect said shift voltage from said output branch of said storage capacitor (107) during an ON-phase of said input control signal voltage; wherein said first inverter (102) is biased between a supply voltage (110) and a low voltage, said first low voltage (111) being higher than zero volt.

2. A boosting circuit (102, 103, 104, 105, 106, 107) in accordance with claim 1 , wherein said charge pump (104, 105, 106) comprises: a Complementary metal oxide semiconductor, CMOS, inverter comprising a P-Metal Oxide Semiconductor, P-MOS, Field Effect Transistor, FET and an N-MOS FET, wherein a source of said PMOS FET is connected to said output branch of said storage capacitor (107),wherein an input of said CMOS inverter is connected to said output of said first inverter (102).

3. A boosting circuit (102, 103, 104, 105, 106, 107) in accordance with claim 3, wherein said charge pump (104, 105, 106) further comprises: a P-MOS FET arranged for connecting said shift voltage to said output branch, wherein a gate of said P-MOS FET is connected to an output of said CMOS inverter.

4. A boosting circuit (102, 103, 104, 105, 106, 107) in accordance with any of the claims 2 - 3, wherein said first low voltage (111) is lower than a threshold voltage of said N-MOS FET of said CMOS inverter.

5. A boosting circuit (102, 103, 104, 105, 106, 107) in accordance with any of the claims 2 - 4, wherein said first low voltage (111) is at least equal to said shift voltage.

6. A boosting circuit (102, 103, 104, 105, 106, 107) in accordance with any of the previous claims, wherein said boosting circuit (102, 103, 104, 105, 106, 107) further comprises: a shift voltage source (114) arranged for providing said shift voltage.

7. A boosting circuit in accordance with claim 6, wherein said shift voltage source (114) is arranged for providing said shift voltage, wherein said shift voltage is equal or lower than said first low voltage (111), and wherein said first low voltage (111) is equal or lower than said threshold voltage of said NMOS FET of said CMOS inverter.

8. A capacitive Digital to Analog Converter, CDAC, assembly comprising a boosting circuit (102, 103, 104, 105, 106, 107) in accordance with any of the previous claims and comprising: a CDAC comprising a plurality of capacitors for converting a digital input code to an analog output voltage.

9. A CDAC assembly in accordance with claim 8, wherein said CDAC comprises a plurality of Field Effect Transistors, FETs, wherein each of said plurality of FETs is arranged to connect one of said plurality of capacitors to a voltage.

10. A CDAC assembly in accordance with claim 9, wherein each of said plurality of FETs is arranged to connect one of said plurality of capacitors to a voltage, said voltage being any of: a common-mode voltage; an input voltage; a reference voltage.

11. A CDAC in accordance with any of the claims 9 - 10, wherein said output branch of said storage capacitor (107) is connected to one or more gate terminals of said plurality of FETs of said CDAC.

12. A CDAC assembly in accordance with any of the claims 8 - 11 , wherein said boosting circuit (102, 103, 104, 105, 106, 107) further comprises a shift voltage source (114) arranged for providing said shift voltage, and wherein said provided shift voltage is equal to, or lower than, said reference voltage.

13. A Successive-Approximation-Register, SAR, Analog-to-Digital Converter, ADC, SAR-ADC comprising a CDAC assembly in accordance with any of the claims 8 - 12.

14. A receiver comprising the SAR-ADC in accordance with claim 13.

15. An electronic apparatus comprising the SAR-ADC in accordance with claim 13.

16. An electronic apparatus in accordance with claim 15, wherein the electronic apparatus is a communication apparatus.

17. An electronic apparatus in accordance with claim 16, wherein the communication apparatus is a User Equipment, UE, for a cellular communications system.

18. An electronic apparatus in accordance with claim 16, wherein the communication apparatus is a radio base station for a cellular communications system.

19. A method of operating a boosting circuit (102, 103, 104, 105, 106, 107) in accordance with any of the claims 1 - 7, wherein said method comprises the steps of: connecting a shift voltage to said output branch of said storage capacitor (107) during an OFF-phase of said input control signal voltage thereby charging said storage capacitor (107) to said shift voltage; disconnecting said shift voltage from said output branch of said storage capacitor (107) during an ON-phase of said input control signal voltage; wherein said method further comprises the step of: biasing said first inverter (102) between a supply voltage (110) and a first low voltage (111), said first low voltage (111) being higher than zero volt.

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