Semiconductor device and method for manufacturing the same

Abstract

To improve the characteristics of a semiconductor device including a power MOSFET.SOLUTION: In a lateral reduced surface field (RESURF) semiconductor device 100, a drift region 12 is configured to have a dopant concentration that varies multiple times such that, in the region extending from under a gate electrode 24 to a drain region 16b, there are a low dopant region having a dopant concentration that is completely depleted when a first voltage lower than a rated operating voltage is applied, and a high dopant region having a dopant concentration that is not depleted when the first voltage is applied.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] Semiconductor devices such as power transistors that can withstand high currents and voltages are used, for example, the laterally diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) is one type of power MOSFET.

[0003] In LDMOSFET devices, a drift region is provided between the channel region and the drain region. Dielectric breakdown due to application of high voltage to the drain region is often prevented by a lateral reduced surface field (RESURF) structure. The RESURF structure is designed to deplete the drift space of LDMOSFET devices both vertically and laterally, thereby reducing the electric field near the surface of the drift region and enhancing the breakdown voltage (BVdss) in the off-state of the device.

[0004] Various RESURF structures have been proposed so far (Patent Documents 1 to 3, Non-Patent Document 1). For example, a RESURF region consisting of two mutually different conductivity types (double RESURF), one RESURF region of a first conductivity type and two RESURF regions of a second conductivity type (triple RESURF), etc. are known. Furthermore, a RESURF region including two RESURF regions of a first conductivity type and two RESURF regions of a second conductivity type (quadruple RESURF) has also been disclosed. These technologies are widely used as AC / DC flyback SMPS. In such applications, a breakdown voltage BVdss of 650 to 700 V or more is required.

[0005] Also disclosed is a configuration in which a drift region, a source region, and a drain region are provided in a substrate of a first conductivity type, and the drift region is of a second conductivity type and is arranged so that the dopant concentration distribution changes periodically (Patent Document 4). A lateral reduced surface field type (RESURF) configuration is disclosed in which a surface breakdown voltage region is provided near the center of a second conductivity type formed in a substrate of a first conductivity type, the surface breakdown voltage region having an average effective impurity density that gradually or stepwise decreases with distance from the center (Patent Document 5). A configuration is disclosed in which a drift region of a second conductivity type is provided in a substrate of a first conductivity type, and a multi-region field limiting ring of a second conductivity type is formed by forming a plurality of doped regions of the first conductivity type on the surface of the drift region (Patent Document 6). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 8,106,451 [Patent Document 2] U.S. Patent No. 6,168,983 [Patent Document 3] U.S. Patent No. 6,724,041 [Patent Document 4] China Patent Publication No. 102694008 [Patent Document 5] China Patent Publication No. 1124408 [Patent Document 6] China Patent Publication No. 113745309 [Non-patent literature]

[0007] [Non-Patent Document 1] DR Disney, AK Paul, M. Darwish, R. Basecki and V. Rumennik, “A New 800V Lateral MOSFET with Dual Conduction Paths,” International Symposium on Power Semiconductor Devices and Ics (ISPSD), pp. 399-402, 2001. Summary of the Invention [Problem to be solved by the invention]

[0008] Typically, there is a trade-off between the breakdown voltage BVdss in the off-state of the device and the on-state resistance Rdson between the drain and source. The breakdown voltage BVdss determines the voltage rating that can be output by the device. The on-resistance Rdson determines the device area required to output the rated current or power rating of the device.

[0009] Designing a device to have a higher breakdown voltage BVdss often results in an increased on-resistance Rdson, and therefore a lower current rating per unit area. For example, the breakdown voltage BVdss can be increased by increasing the length of the drift region of the device or by decreasing the dopant concentration in the drift region, but in both cases the on-resistance Rdson increases. This requires that the device width be increased to achieve the desired on-resistance Rdson. Such methods of reducing the on-resistance Rdson increase the device area, which increases the cost of manufacturing the device. Conversely, designing a device to have a lower on-resistance Rdson reduces the breakdown voltage BVdss and also reduces the operating voltage of the device. For example, increasing the dopant concentration in the drift region reduces the on-resistance Rdson, but also reduces the breakdown voltage BVdss.

[0010] In addition, a device structure having multiple RESURF regions can improve the trade-off between on-resistance Rdson and off-state breakdown voltage BVdss compared to a conventional device structure having a single RESURF region. However, in order to realize such a device structure having RESURF regions, the number of masks in the manufacturing process increases, the manufacturing process becomes more complicated, and the device area increases, which increases the manufacturing cost of the device. [Means for solving the problem]

[0011] 1. A lateral reduced surface field (RESURF) semiconductor device comprising: a substrate of a first conductivity type; a drift region of a second conductivity type formed in the substrate and having a RESURF structure; a body region formed in the substrate; a source region formed in the body region; a drain region formed in the drift region; and a gate electrode formed on the body region, wherein the gate electrode forms a channel in the lateral direction between the source region and a position adjacent to a surface of the drift region, the gate electrode controls a flow of current in the channel by a field effect, and the drift region has a dopant concentration that varies multiple times in a region from under the gate electrode to the drain region such that a low dopant region has a dopant concentration at which all carriers are completely depleted when a first voltage lower than a rated operating voltage is applied, and a high dopant region has a dopant concentration at which carriers are not completely depleted when the first voltage is applied.

[0012] Here, the width of the low dopant region is preferably 1 to 1.5 times the depth of the drift region.

[0013] It is also preferable that the drift region is made up of n (n is an integer of 1 or more) of the high dopant regions and n-1 of the low dopant regions.

[0014] Moreover, the n is preferably 2 or more and 4 or less.

[0015] It is also preferable that the total amount of dopant implanted in the depth direction per unit area of ​​the surface of the substrate is an amount that causes carriers to be completely depleted in both the high dopant region and the low dopant region when a second voltage that is lower than the rated operating voltage and higher than the first voltage is applied.

[0016] The low dopant region has a dopant concentration per unit area of ​​2.0×10 10 / cm 2 More than 2.5 x 10 11 / cm 2 It is preferred that:

[0017] The high dopant region has a dopant concentration per unit area higher than that of the low dopant region, and is 1.2×10 12 / cm 2 More than 2.8 x 10 12 / cm 2 It is preferred that:

[0018] In addition, a medium dopant region, which is half the depth of the low dopant region and the high dopant region in the drift region, has a dopant concentration per unit area higher than that of the low dopant region and lower than that of the high dopant region, and is 2.0×10 11 / cm 2 Above 9.0×10 11 / cm 2 It is preferred that:

[0019] The gate electrode is preferably a metal oxide semiconductor (MOS) gate electrode.

[0020] It is also preferable to provide a source contact that is formed in the body region and makes ohmic contact with the source region, and a drain contact that is formed in the drift region and makes ohmic contact with the drain region.

[0021] Another aspect of the present invention is a method for manufacturing the above-mentioned semiconductor device, comprising forming a photoresist on the substrate so that a region corresponding to the drift region is partially opened, and applying 2.0×10 12 / cm 2 This is a method for manufacturing a semiconductor device, comprising the steps of: injecting a dopant of the second conductivity type as described above to form a drift injection region in the substrate; and diffusing the dopant in the substrate to form the drift region in which the dopant concentration varies a plurality of times in a region extending from under the gate electrode to the drain region. Effect of the Invention

[0022] According to the present invention, it is possible to improve the characteristics of semiconductor devices including power MOSFETs. [Brief description of the drawings]

[0023] [Figure 1] 1 is a schematic cross-sectional view showing a basic configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 2] 1A to 1C are diagrams illustrating a method for manufacturing a basic configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 3] 1A to 1C are diagrams illustrating a method for manufacturing a basic configuration of a semiconductor device according to an embodiment of the present invention. [Figure 4] FIG. 2 is a diagram illustrating divided drift regions of a semiconductor device according to an embodiment of the present invention. [Diagram 5] FIG. 4 is a diagram showing dopant concentrations in divided drift regions of a semiconductor device according to an embodiment of the present invention. [Figure 6] FIG. 1 is a diagram showing the spread of a depletion layer in a drift region of a conventional semiconductor device. [Figure 7] 4A and 4B are diagrams showing the spread of a depletion layer in a drift region of a semiconductor device according to an embodiment of the present invention; [Figure 8]11A and 11B are diagrams showing the results of a simulation of the spread of the electric field and the depletion layer in the drift region of the semiconductor device according to the embodiment of the present invention. [Figure 9] FIG. 2 is a diagram for explaining a dopant concentration in a drift region of a semiconductor device according to an embodiment of the present invention. [Figure 10] FIG. 11 is a diagram showing a simulation result of the relationship between the drain current and the breakdown voltage in the semiconductor device according to the embodiment of the present invention. [Figure 11] FIG. 11 is a diagram showing a simulation result of the relationship between the on-resistance and the breakdown voltage in the semiconductor device according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] [Semiconductor device configuration] As shown in the schematic cross-sectional view of Fig. 1, a semiconductor device 100 according to an embodiment of the present invention includes a semiconductor substrate 10, a drift region 12, a body region 14a, a pickup region 14b, a source region 14c, a well region 16a, a drain region 16b, an insulating region 18, an insulating region 20, a gate insulating layer 22, and a gate electrode 24. Note that Fig. 1 is a schematic diagram for explaining the basic configuration of the semiconductor device 100, and each part is shown with emphasis, and the dimensions in the planar direction and the dimensions in the thickness direction of each part may not show the actual ratio.

[0025] In the following description, the preferred dimensions of each part refer to the dimensions along the length direction (X direction) along the channel movement direction and the film thickness direction (Z direction) in the schematic cross-sectional view of the basic configuration of the semiconductor device 100. The dimensions along the width direction (Y direction) may be set appropriately depending on the maximum capacitance required for the LDMOSFET.

[0026] Hereinafter, the semiconductor device 100 will be described as an n-type channel semiconductor device. In this case, in the following description, the first conductivity type is p-type, and the second conductivity type opposite to the first conductivity type is n-type. However, the semiconductor device 100 is not limited to an n-type channel, and may have a p-type channel. In this case, the first conductivity type is n-type, and the second conductivity type opposite to the first conductivity type is p-type. Note that examples of n-type dopants include phosphorus (P) and arsenic (As), and examples of p-type dopants include boron (B).

[0027] The semiconductor substrate 10 is a substrate on which the semiconductor device 100 is formed. The semiconductor substrate 10 may be, for example, a silicon substrate. The semiconductor substrate 10 is of a first conductivity type.

[0028] The drift region 12 is a region in which a depletion layer is formed and carriers drift during operation of the semiconductor device 100. The drift region 12 is of a second conductivity type opposite to the first conductivity type. It is preferable that one end of the drift region 12 extends to below the gate electrode 24 and the other end is located at a position several μm to several tens of μm away from the end of the gate electrode 24 on the drain region 16b side. By providing the drift region 12, the semiconductor device 100 functions as a lateral reduced surface field (RESURF) power semiconductor device.

[0029] In this embodiment, the drift region 12 is doped so that the dopant concentration varies along the channel movement direction (X direction). The drift region 12 will be described in detail later.

[0030] The body region 14a, the pickup region 14b, and the source region 14c function as the source of the semiconductor device 100. The body region 14a has a conductivity type opposite to that of the drift region 12, i.e., a first conductivity type. The dopant concentration of the body region 14a is 5×10 17 / cm 3 5×10 or more 18 / cm 3It is preferable that the thickness of the body region 14a is set to the thickness of the body region 14a or less. The body region 14a extends to a region overlapping the gate insulating layer 22 and the gate electrode 24. That is, the body region 14a extends to a channel region below the gate electrode 24. The body region 14a is formed in a region shallower than the drift region 12 from the surface of the semiconductor substrate 10. The pickup region 14b has the same conductivity type as the body region 14a, i.e., the first conductivity type. The dopant concentration of the pickup region 14b is set to be higher than that of the body region 14a, and is set to 1×10 19 / cm 3 More than 1×10 21 / cm 3 The source region 14c has the same conductivity type as the drift region 12, i.e., the second conductivity type. The dopant concentration of the source region 14c is preferably 1×10 19 / cm 3 More than 1×10 21 / cm 3 In the present embodiment, the source region 14c extends in the body region 14a from an end of the insulating region 20 to near the end of the gate insulating layer 22 on the source region 14c side or to the gate electrode 24 side beyond the end.

[0031] The well region 16a is formed in a surface region within the drift region 12. The well region 16a is of the second conductivity type. The dopant concentration of the well region 16a is higher than that of the drift region 12, and is 1×10 16 / cm 3 5×10 or more 17 / cm 3It is preferable that the drain region 16b is the following. The drain region 16b is a region that functions as the drain of the semiconductor device 100. The drain region 16b is disposed in a region in the well region 16a away from the gate insulating layer 22 and the gate electrode 24. Specifically, the drain region 16b is disposed at a position farther from the gate electrode 24 than the source region 14c along the channel movement direction (X direction). That is, the source region 14c and the drain region 16b are disposed so as to be asymmetric with respect to the gate electrode 24. The drain region 16b has the same conductivity type as the drift region 12, i.e., the second conductivity type. The dopant concentration of the drain region 16b is higher than that of the well region 16a, and is 1×10 19 / cm 3 More than 1×10 21 / cm 3 It is preferable to have the following:

[0032] The insulating region 18 is an insulating region provided to relax the electric field between the drain region 16b and the gate electrode 24. The insulating region 18 may be, but is not limited to, a shallow trench isolation region (STI region). When the semiconductor substrate 10 is silicon, the insulating region 18 is a silicon oxide film (SiO 2 ), a silicon nitride film (SiN), or the like. The insulating region 18 is disposed in the drift region 12, from a region overlapping with the gate insulating layer 22 and the gate electrode 24 to a region adjacent to the drain region 16b. The thickness of the insulating region 18 in the depth direction of the semiconductor substrate 10 is preferably 250 nm or more and 300 nm or less.

[0033] The insulating region 20 is a region for insulating components of the semiconductor device 100 from each other. When the semiconductor substrate 10 is made of silicon, the insulating region 20 is made of a silicon oxide film (SiO 2 ) or silicon nitride film (SiN), etc.

[0034] The gate insulating layer 22 is an insulating layer that constitutes the gate of the semiconductor device 100. When the semiconductor substrate 10 is made of silicon, the gate insulating layer 22 is a silicon oxide layer (SiO 2 ), a silicon nitride layer (SiN), or a silicon oxynitride film (SiOxNy). The gate insulating layer 22 is provided on a region extending from the source region 14c to the insulating region 18 formed in the surface region of the drift region 12. The thickness of the gate insulating layer 22 is preferably 15 nm or more and 30 nm or less.

[0035] The gate electrode 24 is an electrode for applying a gate voltage to the gate insulating layer 22. The gate electrode 24 can be a polycrystalline silicon layer, a metal layer, a silicide, or a laminated structure of these. The gate electrode 24 is provided in a region on the gate insulating layer 22. When the gate electrode 24 is a polycrystalline silicon layer, it is preferable that the film thickness of the gate electrode 24 is 100 nm or more and 200 nm or less. In addition, it is preferable that the end of the gate electrode 24 is extended so as to reach the insulating region 18.

[0036] [Manufacturing method] Figures 2 and 3 show a method for manufacturing the semiconductor device 100. Figures 2 and 3 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 100, and each part constituting the semiconductor device 100 is shown with emphasis, and the dimensions in the planar direction and the dimensions in the thickness direction of each part may not show the actual ratio.

[0037] Hereinafter, a method for manufacturing an n-type channel semiconductor device 100 will be described. The semiconductor substrate 10 will be described as a silicon substrate doped with p-type as the first conductivity type. In the case of a p-type channel semiconductor device 100, the first conductivity type should be interpreted as n-type and the second conductivity type as p-type.

[0038] In step S10, the drift region 12 is formed. The drift region 12 is formed by ion implantation of a dopant and diffusion by annealing.

[0039] A resist layer R that functions as a mask having an opening region corresponding to the drift region 12 is formed on the surface of the semiconductor substrate 10. The resist layer R can be patterned using a photolithography technique.

[0040] At this time, the resist layer R is formed so that the drift region 12 is divided into at least two regions, as shown in Fig. 4. The number of divisions may be two or more, and is more preferably 2 to 4. The width Wr of the resist layer R that divides the divided regions of the drift region 12 is preferably 1.0 to 2.0 times, and more preferably 1 to 1.5 times, the depth Dr of the drift region 12 to be formed.

[0041] When the second conductivity type is n-type, the ion implantation region 12a is formed by ion implanting an n-type dopant (phosphorus P or arsenic As) into the surface of the semiconductor substrate 10 using the resist layer R as a mask. The ion implantation is performed by implanting phosphorus P at a concentration of 2×10 12 It is preferable to implant ions to a density of 2×10 or more. 12 More than 4×10 12 / cm 2 It is preferable to implant ions so as to obtain a density below 100 nm. A two-stage implantation may be performed by combining ion implantation into a shallow region with ion implantation into a deeper region using an implantation energy higher than that of the ion implantation into the shallow region. However, the density and implantation depth of the dopant to be ion-implanted may be appropriately set according to the size and characteristics of the semiconductor device 100. After the ion implantation, the resist layer R is removed.

[0042] In step S12, an ion diffusion process is performed on the ion implantation region 12a. After the dopant is implanted into the ion implantation region 12a, the semiconductor substrate 10 is annealed (heated) at a high temperature of about 900° C. to 1300° C. to diffuse the dopant into the semiconductor substrate 10. For example, the annealing process is performed at 1100° C. for six hours. However, the heating temperature and time may be appropriately set according to the size and characteristics of the semiconductor device 100. The region into which the second conductivity type dopant is diffused becomes the drift region 12.

[0043] As shown in FIG. 5, the drift region 12 is doped so that the dopant concentration varies along the channel movement direction (X direction). That is, in step S10, ion implantation is performed using a resist layer R that covers a part of the drift region 12 as a mask, so that dopants from other regions diffuse under the region where the resist layer R is provided, and the region where the resist layer R is provided becomes a low dopant region with a low dopant concentration, and the region where the resist layer R is not provided becomes a high dopant region with a high dopant concentration. In FIG. 5, the dopant concentration in the drift region 12 is shown by shading when the number of divisions of the drift region 12 is n=2 to 4. The drift region 12 has a dopant concentration that varies multiple times along the channel movement direction (X direction) so that there are a low dopant region with a dopant concentration that is completely depleted even when a voltage lower than a predetermined rated operating voltage is applied to the gate electrode 24, and a high dopant region with a dopant concentration that is not depleted when the voltage is applied. That is, drift region 12 is made up of n high dopant regions and n-1 low dopant regions. The number of divisions n is preferably 2 to 4. A suitable dopant concentration for drift region 12 will be described later.

[0044] In step S14, the insulating region 18 and the insulating region 20 are formed. The insulating region 18 and the insulating region 20 can be formed by the existing LOCOS process or STI process using a mask. In the LOCOS process, a silicon oxide film (SiO 2 ) or silicon nitride film (SiN) as a mask, and oxygen (O2 ), the semiconductor substrate 10 is heated to thermally oxidize the opening regions of the mask on the surface of the semiconductor substrate 10, thereby forming the insulating region 18 or the insulating region 20. In the STI process, the opening regions are trench-etched, an insulating film is filled into the trenches using high-density plasma CVD or the like, and then the region is planarized by chemical mechanical polishing (CMP), thereby forming the insulating region 18 or the insulating region 20.

[0045] In step S16, an ion implantation process is performed for the body region 14a of the semiconductor device 100. A resist layer that functions as a mask is formed in an area other than the area where the body region 14a is to be formed. The resist layer can be patterned using a photolithography technique. Using the resist layer as a mask, a p-type dopant (boron B or boron difluoride BF 2 ) is ion-implanted into the surface of the semiconductor substrate 10. In the ion implantation, for example, boron B is implanted at a dose of 1.0×10 13 Above 2.0×10 13 / cm 2 Ions are implanted to achieve the following density: However, the density of the dopant to be ion-implanted, the implantation depth, etc. may be set appropriately depending on the size and characteristics of the semiconductor device 100. After the ion implantation, the resist layer is removed.

[0046] In step S18, an ion implantation process for the well region 16a is performed. A resist layer that functions as a mask is formed in an area other than the area where the well region 16a is to be formed. The resist layer can be patterned using a photolithography technique. Using the resist layer as a mask, an n-type dopant (phosphorus P or arsenic As) is ion-implanted into the surface of the semiconductor substrate 10. In the ion implantation, for example, phosphorus P is implanted at 1×10 with an ion implantation energy of 150 keV to 250 keV. 13 More than 3×10 13 / cm 2Ions are implanted to achieve the following density: However, the density of the dopant to be ion-implanted, the implantation depth, etc. may be set appropriately depending on the size and characteristics of the semiconductor device 100. After the ion implantation, the resist layer is removed.

[0047] After the dopants are injected into the body region 14a and the well region 16a, the semiconductor substrate 10 is annealed (heated) at a high temperature of about 900° C. to 1200° C. to diffuse the dopants into the semiconductor substrate 10. For example, the annealing process is performed at 1000° C. for two hours. However, the heating temperature and time may be appropriately set depending on the size and characteristics of the semiconductor device 100.

[0048] In step S20, a gate insulating layer 22 is formed. The gate insulating layer 22 is formed of oxygen (O 2 ) and nitrogen (N 2 The gate insulating layer 22 may be formed by a thermal oxidation method using a nitrogen-containing gas such as tetraethoxysilane (TEOS). The gate insulating layer 22 may be formed by a chemical vapor deposition (CVD) method using tetraethoxysilane (TEOS). The gate insulating layer 22 is etched simultaneously with etching of the gate electrode 24 in the next step S22 so that the gate insulating layer 22 remains in a region on the surface of the semiconductor substrate 10 that spans a part of the drift region 12 and a part of the insulating region 18. In this step, photolithography and etching using a resist may be applied so that the gate insulating layer 22 remains in a region on the surface of the semiconductor substrate 10 that spans a part of the drift region 12 and a part of the insulating region 18. The thickness of the gate insulating layer 22 is preferably 15 nm to 30 nm.

[0049] In step S22, the gate electrode 24 is formed. The method for forming the gate electrode 24 is not particularly limited. However, when a polycrystalline silicon layer is to be formed, silane (SiH 4) or other silicon-containing gas. When the gate electrode 24 is a metal layer, deposition, sputtering, chemical vapor deposition, or other methods can be used. Photolithography and etching using a resist are used to form the gate electrode 24 of the semiconductor device 100 in a required region.

[0050] In step S24, ion implantation processes are performed for the pickup region 14b, the source region 14c, and the drain region 16b. The pickup region 14b and the source region 14c are formed in the body region 14a. A resist layer that functions as a mask is formed in the region other than the region where the pickup region 14b is to be formed. The resist layer can be patterned using a photolithography technique. Using the resist layer as a mask, a p-type dopant (boron B or boron difluoride BF 2 ) is ion-implanted into the surface of the semiconductor substrate 10. In the ion implantation, for example, boron difluoride BF 2 2.0×10 with ion implantation energy of 5 keV to 20 keV 15 Above 5.0×10 15 / cm 2 Ions are implanted to achieve the following density: However, the density of the dopant to be ion-implanted, the implantation depth, etc. may be set appropriately depending on the size and characteristics of the semiconductor device 100. After the ion implantation, the resist layer is removed.

[0051] Next, a resist layer that functions as a mask is formed in an area other than the area where the source region 14c and the drain region 16b are to be formed. The resist layer can be patterned using a photolithography technique. Using the resist layer as a mask, an n-type dopant (phosphorus P or arsenic As) is ion-implanted into the surface of the semiconductor substrate 10. In the ion implantation, for example, arsenic As is implanted at a concentration of 2×10 with an ion implantation energy of 20 keV to 25 keV. 15 / cm 2 5×10 or more 15 / cm 2Ions are implanted to achieve the following density: However, the density of the dopant to be ion-implanted, the implantation depth, etc. may be set appropriately depending on the size and characteristics of the semiconductor device 100. After the ion implantation, the resist layer is removed.

[0052] Then, an ion activation process is performed. After dopants are implanted into the pickup region 14b, the source region 14c, and the drain region 16b of the semiconductor device 100, the semiconductor substrate 10 is annealed (heated) at a high temperature of about 900°C to 1050°C to activate the dopants in the semiconductor substrate 10. For example, the annealing process is performed at 1030°C for 20 seconds. However, the heating temperature and time may be appropriately set depending on the characteristics required for the semiconductor device 100.

[0053] [Characteristics of the semiconductor device according to this embodiment] The following describes the characteristics of the semiconductor device 100. The semiconductor device 100 is a lateral reduced surface field (RESURF: REduced SURface Field) power semiconductor device. RESURF is a technology for increasing the withstand voltage of lateral FETs.

[0054] In the semiconductor device 100, the drift region 12 has a dopant concentration per unit area that is completely depleted when a voltage lower than the rated operating voltage is applied to the entire drift region 12. FIG. 6 is a schematic diagram illustrating the depletion of the drift region 12 in a conventional semiconductor device having an undivided drift region 12. FIG. 7 is a schematic diagram illustrating the depletion of the drift region 12 in the present embodiment having a divided drift region 12. FIGS. 6(a) and 7(a) show the spread of the depletion layer in the drift region 12 in a state where a voltage Vd smaller than the rated operating voltage is applied between the gate electrode G and the drain electrode D. FIGS. 6(b) and 7(b) show the spread of the depletion layer in the drift region 12 in a state where a voltage Vd approximately equal to the rated operating voltage is applied between the gate electrode G and the drain electrode D. In FIGS. 6 and 7, the spread of the depletion layer in the drift region 12 is indicated by a thick dashed line.

[0055] In conventional semiconductor devices, the dopant concentration in the drift region 12 does not change along the channel movement direction (X direction), so as shown in Fig. 6(a), when the source electrode S and the gate electrode G are shorted and a voltage Vd is applied between the drain electrode D and the source electrode S (gate electrode G), the depletion layer expands toward the inside of the drift region 12 along the interface shape between the semiconductor substrate 10 and the drift region 12. Therefore, as shown in Fig. 6(b), even if the voltage Vd applied to the gate electrode G is increased to the rated operating voltage, the depletion layer width W D does not extend to the vicinity of the drain well region 16a, the electric field is not sufficiently relaxed, and the breakdown voltage BVdss in the off state decreases.

[0056] In contrast, in the semiconductor device 100 of this embodiment, regions with high and low dopant concentrations are provided in the drift region 12 along the channel movement direction (X direction), and as shown in FIG. 7(a), when the source electrode S and the gate electrode G are shorted and a voltage Vd is applied between the drain electrode D and the source electrode S (gate electrode G), a depletion layer spreads toward the inside of the drift region 12 along the interface shape between the semiconductor substrate 10 and the drift region 12. At this time, the depletion layer spreads more easily in the region with a low dopant concentration, and the depletion layer spreads more widely toward the inside of the drift region 12. Therefore, as shown in FIG. 7(b), the depletion layer width W D The electric field is sufficiently relaxed and the breakdown voltage BVdss in the off state is increased.

[0057] FIG. 8 shows the electric field and the depletion layer width W D The simulation results are shown below. The width of the drift region 12 is 50 μm, and phosphorus is 2.0×10 12 / cm 2The ion implantation was performed under the condition that the density of the ions was 100 μm and the voltage Vd of 700 V was applied between the drain electrode D and the gate electrode G. As shown in FIG. 8, when the drift region 12 was not divided (number of divisions n=1), the depletion layer width W D In contrast, when the drift region 12 is divided into at least two or more (number of divisions n ≧ 2), the depletion layer width W D It was found that the MOSFET was sufficiently extended to the vicinity of the drain region.

[0058] 9 is a diagram for explaining a suitable dopant concentration of the drift region 12. In FIG. 9, the high dopant region and the low dopant region in the drift region 12 are shown enlarged. In the drift region 12, the region with the highest dopant concentration per unit area along the channel movement direction (X direction) is shown as the high dopant region, and the region with the lowest dopant concentration per unit area along the channel movement direction (X direction) is shown as the low dopant region. In addition, a position corresponding to an intermediate depth between the depth from the surface of the semiconductor substrate 10 of the high dopant region and the depth from the surface of the semiconductor substrate 10 of the low dopant region is defined as the medium dopant region.

[0059] If the drain current in the on-state is to be 30nA / um or more and the breakdown voltage BVdss is to be 700V or more, the dopant concentration per unit area of ​​the low dopant region should be 2.0×10 10 / cm 2 More than 2.5 x 10 11 / cm 2 In the following, the dopant concentration per unit area of ​​the middle dopant region is 2.0×10 11 / cm 2 Above 9.0×10 11 / cm 2 In the following, the dopant concentration per unit area of ​​the high dopant region is 1.2 × 10 12 / cm 2 More than 2.8 x 10 12 / cm 2More specifically, when the division number n of the drift region 12 is 2 or 3, the dopant concentration per unit area of ​​the low dopant region is preferably 2.0×10 10 / cm 2 Above 6.0×10 10 / cm 2 In the following, the dopant concentration per unit area of ​​the middle dopant region is 2.0×10 11 / cm 2 Above 4.0×10 11 / cm 2 In the following, the dopant concentration per unit area of ​​the high dopant region is 1.2 × 10 12 / cm 2 More than 2.8 x 10 12 / cm 2 In addition, when the number of divisions n of the drift region 12 is 4 or 5, the dopant concentration per unit area of ​​the low dopant region is preferably 8.0×10 10 / cm 2 More than 2.5 x 10 11 / cm 2 In the following, the dopant concentration per unit area of ​​the middle dopant region is 4.0×10 11 / cm 2 Above 9.0×10 11 / cm 2 In the following, the dopant concentration per unit area of ​​the high dopant region is 1.2 × 10 12 / cm 2 More than 2.8 x 10 12 / cm 2 It is preferable that the dopant concentration per unit area is as follows: Here, the dopant concentration per unit area means the total amount of dopant implanted in the depth direction per unit area of ​​the surface of the semiconductor substrate 10.

[0060] 10 shows the results of a simulation using TCAD on the relationship between the drain current Id and the breakdown voltage BVdss in the semiconductor device 100 according to the embodiment of the present invention. When the drift region 12 is not divided (number of divisions n=1: shown as "single" in the figure), the drain current Id drops sharply as the breakdown voltage BVdss increases. In contrast, when the drift region 12 is divided (number of divisions n=2 to 5: shown as "2 to 5-stripes" in the figure), the drain current Id is higher for the same breakdown voltage BVdss than when the drift region 12 is not divided.

[0061] 11 shows the results of a simulation using TCAD on the relationship between the on-resistance ARon per area and the breakdown voltage BVdss in the semiconductor device 100 according to the embodiment of the present invention. Under the condition that the breakdown voltage BVdss is equal, the on-resistance ARon is lower when the drift region 12 is divided (number of divisions n=2 to 4: shown as 2 to 4-stripes in the figure) compared to when the drift region 12 is not divided (number of divisions n=1: shown as single in the figure). Also, as the number of divisions n of the drift region 12 increases, the on-resistance ARon shows a characteristic of decreasing further.

[0062] As described above, according to the semiconductor device 100 of the embodiment of the present invention, a high breakdown voltage BVdss and a low on-resistance ARon can be simultaneously achieved. Furthermore, when forming the divided drift regions 12, the characteristics of the semiconductor device 100 can be improved without increasing the number of masks, complicating the manufacturing process, or increasing the device area, as compared to when forming a conventional drift region.

[0063] [Configuration of the invention] [Configuration 1] A lateral reduced surface field (RESURF) semiconductor device, comprising: A substrate of a first conductivity type; formed on the substrate, a drift region of a second conductivity type having a RESURF structure; a body region formed in the substrate; a source region formed within the body region; a drain region formed within the drift region; a gate electrode formed on the body region; having the gate electrode defines a lateral channel between the source region and a location adjacent a surface of the drift region; the gate electrode controls current flow in the channel by field effect; a first voltage that is lower than a rated operating voltage, and a high dopant region having a dopant concentration that is not completely depleted of carriers when the first voltage is applied, the drift region having a dopant concentration that varies multiple times in a region extending from beneath the gate electrode to the drain region. [Configuration 2] 2. The semiconductor device according to claim 1, A semiconductor device, characterized in that the width of the low dopant region is 1 to 1.5 times the depth of the drift region. [Configuration 3] A semiconductor device according to configuration 1 or 2, A semiconductor device, wherein the drift region comprises n (n is an integer of 1 or more) of the high dopant regions and n-1 of the low dopant regions. [Configuration 4] 4. The semiconductor device according to configuration 3, A semiconductor device, wherein n is 2 or more and 4 or less. [Configuration 5] 5. The semiconductor device according to configuration 3 or 4, A semiconductor device characterized in that a total amount of dopant implanted in a depth direction per unit area of ​​the surface of the substrate is an amount that causes carriers to be completely depleted in both the high dopant region and the low dopant region when a second voltage that is lower than the rated operating voltage and higher than the first voltage is applied. [Configuration 6] The semiconductor device according to any one of configurations 1 to 5, The low dopant region has a dopant concentration per unit area of ​​2.0×10 10 / cm 2 More than 2.5 x 10 11 / cm 2 1. A semiconductor device comprising: [Configuration 7] 7. The semiconductor device according to claim 6, The high dopant region has a dopant concentration per unit area higher than that of the low dopant region, and is 1.2×10 12 / cm 2 More than 2.8 x 10 12 / cm 2 1. A semiconductor device comprising: [Configuration 8] 8. The semiconductor device according to claim 7, A medium dopant region, which is half the depth of the low dopant region and the high dopant region in the drift region, has a dopant concentration per unit area higher than that of the low dopant region and lower than that of the high dopant region, and is 2.0×10 11 / cm 2 Above 9.0×10 11 / cm 2 1. A semiconductor device comprising: [Configuration 9] The semiconductor device according to any one of configurations 1 to 8, The semiconductor device, wherein the gate electrode is a metal-oxide-semiconductor (MOS) gate electrode. [Configuration 10] The semiconductor device according to any one of configurations 1 to 9, a source contact formed in the body region and in ohmic contact with the source region; a drain contact formed in the drift region and in ohmic contact with the drain region; A semiconductor device comprising: [Configuration 11] A method for producing a semiconductor device according to configuration 1, comprising the steps of: forming a photoresist on the substrate so that a region corresponding to the drift region is partially opened; Through the opening defined by the photoresist, 2.0×10 12 / cm 2 forming a drift injection region in the substrate by injecting the second conductivity type dopant; forming the drift region in which the dopant concentration varies a plurality of times in a region extending from under the gate electrode to the drain region by diffusing a dopant into the substrate; 1. A method for manufacturing a semiconductor device comprising the steps of: [Explanation of symbols]

[0064] 10 semiconductor substrate, 12 drift region, 12a ion implantation region, 14a body region, 14b pickup region, 14c source region, 16a well region, 16b drain region, 18 insulating region, 20 insulating region, 22 gate insulating layer, 24 gate electrode, 100 semiconductor device.

Claims

1. A lateral reduced surface field (RESURF) semiconductor device, comprising: a substrate of a first conductivity type; formed on the substrate, a drift region of a second conductivity type having a RESURF structure; a body region formed in the substrate; a source region formed within the body region; a drain region formed within the drift region; a gate electrode formed on the body region; having the gate electrode defines a lateral channel between the source region and a location adjacent a surface of the drift region; the gate electrode controls current flow in the channel by field effect; a first voltage lower than a rated operating voltage is applied between the drain region and the gate electrode when the source region and the gate electrode are short-circuited, and a high dopant region having a dopant concentration that does not completely deplete carriers when the first voltage is applied is provided between the drain region and the gate electrode.

2. 2. The semiconductor device of claim 1, A semiconductor device, wherein the width of the low dopant region is 1 to 1.5 times the depth of the drift region.

3. 2. The semiconductor device of claim 1 , A semiconductor device, wherein the drift region comprises n (n is an integer of 2 or more) of the high dopant regions and n-1 of the low dopant regions.

4. 4. The semiconductor device of claim 3, A semiconductor device, wherein n is 2 or more and 4 or less.

5. 4. The semiconductor device of claim 3, a total amount of dopant implanted in a depth direction per unit area of ​​the surface of the substrate is an amount that causes carriers to be completely depleted in both the high dopant region and the low dopant region when a second voltage that is lower than the rated operating voltage and higher than the first voltage is applied between the drain region and the gate electrode with the source region and the gate electrode shorted.

6. The semiconductor device according to any one of claims 1 to 5, The low dopant region has a dopant concentration per unit area of ​​2.0×10 １０ / cm ２ Above 2.5 x 10 １１ / cm ２ 1. A semiconductor device comprising:

7. 7. The semiconductor device of claim 6, The high dopant region has a dopant concentration per unit area higher than that of the low dopant region, and is 1.2×10 １２ / cm ２ Above 2.8 x 10 １２ / cm ２ 1. A semiconductor device comprising:

8. 8. The semiconductor device of claim 7, In the drift region, a dopant concentration per unit area at a depth half the depth of the light dopant region and the heavy dopant region is higher than that of the light dopant region and lower than that of the heavy dopant region, and is 2.0×10 １１ / cm ２ Above 9.0 x 10 １１ / cm ２ 1. A semiconductor device comprising:

9. 2. The semiconductor device of claim 1 , A semiconductor device, wherein the gate electrode is a MOS gate electrode.

10. 2. The semiconductor device of claim 1 , a source contact formed in the body region and in ohmic contact with the source region; a drain contact formed in the drift region and in ohmic contact with the drain region; A semiconductor device comprising:

11. 2. A method for manufacturing a semiconductor device according to claim 1, comprising the steps of: forming a photoresist on the substrate so that a region corresponding to the drift region is partially opened; Through the opening defined by the photoresist, １２ / cm ２ forming a drift injection region in the substrate by injecting the second conductivity type dopant; forming the drift region in which the dopant concentration varies a plurality of times in a region extending from under the gate electrode to the drain region by diffusing a dopant into the substrate; 1. A method for manufacturing a semiconductor device comprising the steps of:

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