System and method for high speed memory access - Patents.com

Abstract

A system and method for fast memory access is disclosed. In one aspect, a processor, e.g., a control circuit in a system-on-chip (SoC), couples to an external memory, e.g., a universal file system (UFS) memory (e.g., a NAND flash memory) having a partial logical-physical (L2P) mapping table stored in the external memory and a local L2P mapping table stored in a local memory (e.g., a dynamic random access memory (DRAM)). The control circuit can evaluate what percentage of the entries in the local L2P mapping table are active compared to inactive. If the number of inactives exceeds the number of actives, the control circuit can send a read command without accessing the local L2P mapping table.

Description

[Technical field]

[0001] Priority Application

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 453,572, entitled "SYSTEMS AND METHODS FOR FAST MEMORY ACCESS," filed Nov. 4, 2021, the entire contents of which are incorporated by reference into this specification.

[0002] I. Field of Disclosure The technology of this disclosure relates generally to accessing data stored in NAND flash memory. [Background technology]

[0003] II. Background technology

[0003] In modern society, computing devices galore, and more specifically, mobile communication devices, are becoming more and more common. The popularity of these mobile communication devices is driven in part by the many functions now possible on such devices. The increase in processing power within such devices means that mobile communication devices will evolve from pure communication tools to advanced mobile entertainment centers, thereby enabling an enhanced user experience. Almost all computing devices rely on various levels of memory to store data and operating instructions. For example, there may be a system memory that accesses a NAND flash memory. Since access to the NAND flash memory is relatively slow, there may be a cache memory associated with the processor that facilitates address mapping to make memory access faster. There are various ways to improve memory access, but at first glance, there is always room for improved memory access. Summary of the Invention

[0004]

[0004] Aspects disclosed in the detailed description include systems and methods for fast memory access. In particular, exemplary aspects of the present disclosure contemplate a processor, such as, for example, a control circuit in a system-on-chip (SoC), coupled to an external memory, such as, for example, a universal flash storage (UFS) memory (e.g., a NAND flash memory) having a partial logical-to-physical (L2P) mapping table stored in the external memory and a local L2P mapping table stored in a local memory (e.g., a dynamic random access memory (DRAM)). The control circuit may evaluate what percentage of entries in the local L2P mapping table are active compared to inactive. If the number of inactives exceeds the number of actives, the control circuit may send a read command without accessing the local L2P mapping table. Skipping the local memory in this manner relies on more recent entries in the external memory, which is likely to result in faster memory calls to the UFS memory, resulting in a better user experience.

[0005] In this regard, in one aspect, an SoC is disclosed. The SoC includes a memory bus interface configured to couple to a UFS memory having an external cache memory. The external cache memory includes a partial L2P mapping table of the UFS memory. The SoC also includes a local cache memory including the local L2P mapping table of the UFS memory. The SoC also includes a control circuit coupled to the memory bus interface and the local cache memory. The control circuit is configured to determine an active size of an active portion of the local L2P mapping table in the local cache memory. The control circuit is also configured to compare the active size of the active portion to a threshold.

[0006]

[0006] In another aspect, a SoC is disclosed. The SoC includes a memory bus interface configured to couple to a UFS memory having an external cache memory. The external cache memory includes a partial L2P mapping table of the UFS memory. The SoC also includes a local cache memory including the local L2P mapping table of the UFS memory. The SoC also includes control circuitry coupled to the memory bus interface and the local cache memory. The control circuitry is configured to determine an inactive size of an inactive portion of the local L2P mapping table in the local cache memory. The control circuitry is also configured to compare the inactive size of the inactive portion to a threshold.

[0007] In another aspect, a method for accessing memory from a host is disclosed. The method includes determining an active size of an active portion of a local L2P mapping table in a local cache memory associated with the host relative to a partial L2P mapping table in an external cache memory in a remote memory device. The method also includes comparing the active size of the active portion to a threshold value. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a conventional computing system having an associated host and universal flash storage (UFS) memory. [Diagram 2]

[0009] FIG. 1 is a block diagram of an example computing system with associated UFS memory that uses a host performance booster (HPB) to improve memory access times and that can further improve memory access times using example aspects of the present disclosure. [Diagram 3]

[0010] FIG. 2 is a signal versus time diagram of a conventional memory access time with a cache hit and a cache miss. [Figure 4]

[0011] FIG. 2 is a block diagram of a computing device having a host and associated UFS memory illustrating memory access under an exemplary aspect of the present disclosure. [Diagram 5]

[0012] 4 is a signal versus time diagram of memory access time according to an exemplary aspect of the present disclosure. [Figure 6]

[0013] 1 is a flow chart of a process associated with an example aspect of the present disclosure operating on legacy and enabled devices. [Figure 7]

[0014] FIG. 1 is a block diagram of a computing device having a host and UFS memory that can operate in accordance with the high speed memory access aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0015] Some exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0010]

[0016] Aspects disclosed in the detailed description include systems and methods for fast memory access. In particular, exemplary aspects of the present disclosure contemplate a processor, e.g., a control circuit in a system-on-chip (SoC), coupling to an external memory, e.g., a universal flash storage (UFS) memory (e.g., a NAND flash memory) having a partial logical-to-physical (L2P) mapping table stored in the external memory as well as a local L2P mapping table stored in a local memory (e.g., a dynamic random access memory (DRAM)). The control circuit may evaluate what percentage of entries in the local L2P mapping table are active compared to inactive. If the number of inactives exceeds the number of actives, the control circuit may send a read command without accessing the local L2P mapping table. Skipping the local memory in this manner relies on more recent entries in the external memory, which is likely to result in faster memory calls to the UFS memory, resulting in a better user experience.

[0011]

[0017] A simple overview of a computing device having a host and UFS memory is shown in Figure 1. Figure 2 shows a similar computing device with Host Performance Booster (HPB) enabled and capable of implementing exemplary aspects of the present disclosure. Figure 3 illustrates a situation in which a memory call resulting in a cache miss can adversely affect performance, and highlights how exemplary aspects of the present disclosure can improve performance, as better shown beginning with Figure 4.

[0012]

[0018] In this regard, FIG. 1 illustrates a computing device 100 having a system-on-chip (SoC) 102 having a UFS controller 104 therein. The SoC 102 may be a single integrated circuit (IC) having multiple functions therein, on different layers as is possible using three-dimensional (3D) IC manufacturing IC manufacturing techniques, a set of stacked dies (e.g., a flip-chip configuration), and the like. The SoC 102 may be coupled to a UFS memory 106 by a UFS bus 108. The UFS memory 106 may include a NAND memory element 110 and an SRAM memory element 112. The NAND memory element 110 may store an entire L2P mapping table therein, which is always up to date. The SRAM memory element 112 may include an external cache that includes a partial L2P mapping table with entries corresponding to the most recently (and / or most frequently) accessed logical addresses. The NAND memory element 110 may have a relatively slow read time compared to the SRAM memory element 112.

[0013]

[0019] It should be appreciated that in use, the UFS controller 104 may generate a read command that first queries the SRAM memory element 112 to find the physical address. If the partial L2P mapping table contains an L2P mapping for the requested address, the UFS memory 106 retrieves the L2P map entry from the SRAM memory element 112. The UFS memory 106 then reads the logical block from the NAND memory element 110 and transfers the data to the SoC 102 (see general signaling case 300 in FIG. 3). However, if the partial L2P mapping table does not contain the logical address, the UFS memory 106 receives the read command and reads the physical address from the entire L2P mapping table in the NAND memory element 110. The UFS memory 106 stores the entry in the partial L2P mapping table in the SRAM memory element 112. The L2P map entry is then retrieved from the SRAM memory element 112. The UFS memory 106 then reads the logical block from the NAND memory element 110 and transfers the data to the SoC 102 (see general signaling case 310 in FIG. 3).

[0014]

[0020] Although using a cache such as provided in SRAM memory element 112 may make it faster to access logical blocks in NAND memory element 110 when there are entries in the partial L2P mapping table, there may be a cache miss resulting in signaling case 310. The additional time to retrieve an address from the entire L2P mapping table in NAND memory element 110 may adversely affect the user experience and add unacceptable latency to certain operations in computing device 100.

[0015]

[0021] To improve performance, the industry is moving towards adopting the HPB concept of moving the entire L2P mapping table to the SoC, as better illustrated in FIG. 2 with cases 320 and 330 in FIG. 3. In this regard, FIG. 2 shows a computing device 200 having a SoC 202 with a UFS controller 204 therein. The SoC 202 may be coupled to a UFS memory 206 by a UFS bus 208. The UFS memory 206 may include a NAND memory element 210 and an SRAM memory element 212. The NAND memory element 210 may store the entire L2P mapping table therein, which is always up to date. The SRAM memory element 212 may include a cache that includes a partial L2P mapping table with entries corresponding to the most recently (and / or most frequently) accessed logical addresses. In addition, the SoC 202 may also include a DRAM element 214 that stores a local L2P mapping table therein. The DRAM element 214 acts as a cache, allowing the SoC 202 to have immediate access to the physical address. The SoC 202 can then send the physical address along with a read command to the UFS memory 206 (see general signaling case 320 in FIG. 3).

[0016]

[0022] However, entries in the local L2P mapping table in the DRAM element 214 may be out of date or inaccurate. For example, sometimes data needs to be moved to another physical area of ​​the NAND memory element 210 for internal maintenance purposes (e.g., refresh operations, garbage collection, read reclaim, read disturb, etc.). In such cases, the local L2P mapping table in the DRAM element 214 may not be synchronized with the entire L2P mapping table in the NAND memory element 210. Traditionally, the HPB allows the UFS memory 206 to send updates to the SoC 202. However, the updates are periodic and not instantaneous. Thus, read operations directed to out-of-sync addresses may result in cache misses as well (see generally signaling case 330 in FIG. 3). Such cache misses may adversely affect the user experience and / or may result in unacceptable latency for the computing device 200.

[0017]

[0023] 3 provides a comparison of signaling cases 300, 310, 320, and 330. Signaling case 300 begins with a read command 302 being issued and sent to UFS memory 106, which retrieves an L2P map entry from a partial L2P mapping table in SRAM memory element 112 at 304. Using a logical address from the partial L2P mapping table, UFS memory 106 reads the logical block from NAND memory element 110 and transfers the data to SoC 102 at 306. While not to scale, the size of 306 illustrates the relative slowness of accessing NAND memory element 110 compared to accessing SRAM memory element 112 at 304.

[0018]

[0024] Signaling case 310 begins with a read command 312 being issued and sent to UFS memory 106, indicating a cache miss in computing device 100. UFS memory 106 looks in SRAM memory element 112 and does not find a mapping entry, therefore, at 314, reads an entry from the entire L2P mapping table in NAND memory element 110 and stores it in SRAM memory element 112, introducing delay. Next, at 316, an address is retrieved from SRAM memory element 112. At 318, using the logical address from the partial L2P mapping table, UFS memory 106 reads the logical block from NAND memory element 110 and transfers the data to SoC 102. The additional delay introduced by the cache miss may prove to be unacceptable.

[0019]

[0025] Signaling case 320 begins with UFS controller 204 accessing DRAM element 214 to retrieve a logical address from the local L2P mapping table at 322. A read command with the logical address is then sent to UFS memory 206 at 324. Using the logical address, UFS memory 206 reads the logical block from NAND memory element 210 and transfers the data to SoC 202 at 326. Using the HPB in this manner reduces the delay caused by the cache miss in signaling case 310. However, there is still a cache miss, as shown in signaling case 330.

[0020]

[0026] Signaling case 330 begins with UFS controller 204 accessing DRAM element 214 to retrieve a logical address from a local L2P mapping table at 332. A read command with the logical address is then sent to UFS memory 206 at 334. However, the logical address provided in the read command is incorrect and the UFS device must read the L2P entry from the full L2P mapping table in NAND memory element 210 at 336. Using an address from the full L2P mapping table, UFS memory 206 reads the logical block from NAND memory element 210 and transfers the data to SoC 202 at 338. Again, this cache miss may result in unacceptable delays.

[0021]

[0027] Exemplary aspects of the present disclosure reduce the probability of a cache miss occurring as shown in signaling case 330 by estimating how much of a local L2P mapping table in a local cache (e.g., DRAM) is active versus how much is inactive. Based on this estimation, the SoC uses the HPB methodology only when the inactive portion is smaller than the active portion. Essentially, when the active portion is larger than the inactive portion, the SoC determines that the address is probably in the active portion and therefore likely to be correct and up-to-date. Conversely, when the inactive portion is larger than the active portion, the SoC determines that the address is probably in the inactive portion and likely not to be correct or up-to-date and therefore should not be used. In such cases, using a partial L2P mapping table in an external cache (e.g., SRAM) and its possible cache misses is more efficient than using the possible cache misses of the HPB methodology.

[0022]

[0028] Active is a term defined in the HPB industry, and as used herein, means that an entry in the local L2P mapping table is identical to an entry in the partial L2P mapping table. Similarly, inactive, as used herein, means that an entry in the local L2P mapping table has no entry or a different entry in the partial L2P mapping table. In an exemplary aspect, the UFS memory can proactively (assuming device control mode is initiated) transfer active and inactive addresses or regions to the SoC, such as after or during maintenance activities (e.g., refresh operations) in the UFS memory. Based on these updates, the SoC can make updates to the local L2P mapping table in a local cache (e.g., DRAM).

[0023]

[0029] In this regard, FIG. 4 illustrates a computing device 400 including a SoC 402 having a UFS host controller or control circuit 404 therein. The SoC 402 is coupled to a UFS memory 406 by a memory bus 408, which may be a UFS bus. The SoC 402 may include a memory bus interface 408A, which may be a UFS bus interface. Similarly, the UFS memory 406 may include a memory bus interface 408B. The SoC 402 may further include a local cache memory, e.g., a DRAM 410, that stores a local L2P mapping table 412 for the UFS memory 406. In an exemplary embodiment, the local L2P mapping table 412 is an entire L2P mapping table having a physical address per logical address. In another exemplary embodiment, the local L2P mapping table 412 is a partial L2P mapping table. The presence of the DRAM 410 having the local L2P mapping table 412 contemplates that a HPB methodology is possible for read commands to the UFS memory 406.

[0024]

[0030] The UFS memory 406 may include a memory controller 414, an external cache memory, such as an SRAM 416, and a NAND memory element 418. The NAND memory element 418 may store an entire L2P mapping table 420 internally, which is always up to date. The SRAM 416 may be or include an external cache that contains a partial L2P mapping table 422 of the UFS memory 406 with entries corresponding to the last (and / or most frequently) accessed logical addresses.

[0025]

[0031] As mentioned above, the exemplary aspects of the present disclosure contemplate determining an active size of an active portion of the local L2P mapping table 412 in the DRAM 410 and comparing the active size of the active portion to a threshold value. The threshold value may be an inactive size of an inactive portion of the local L2P mapping table 412. There are various ways in which the active size may be determined. In the exemplary aspects, the circuit 430 may include one or more counters, registers, and comparators. When there is an update from the UFS memory 406, the counters count each active entry and optionally count each inactive entry. The comparators may then compare the value of the counter(s) to the total size of the local L2P mapping table 412 stored in the register to determine a percentage, or the like. Equivalently, the present disclosure contemplates determining an inactive size of an inactive portion of the local L2P mapping table 412 and comparing the inactive size of the inactive portion to a threshold value. Similarly, there are various ways in which the inactive size may be determined.

[0026]

[0032] Based on the comparison, two possible signaling cases 500 and 510 may occur, as shown in FIG. 5. Specifically, signaling case 500 occurs when control circuitry 404 determines, using, for example, circuitry 430, that the active portion is greater than the inactive portion. From this determination, control circuitry 404 likely infers that the information in local L2P mapping table 412 is correct, and blindly goes to local L2P mapping table 412 for all read transactions. Thus, signaling case 500 begins with retrieving a logical address from local L2P mapping table 412 in DRAM 410, at 502, similar to signaling case 320, after a determination that the active portion exceeds a threshold, and then sending a read command including the logical address to UFS memory 406, at 504. This general process is illustrated by dotted line 500 in FIG. 4. UFS memory 406 then reads the logical block from NAND memory element 418. The read data is then transferred to the SoC 402 at 506 .

[0027]

[0033] However, when the control circuitry 404 determines that the active size of the active portion does not exceed a threshold (e.g., the inactive size of the inactive portion), despite the presence of the HPB methodology, the exemplary aspects of the present disclosure may skip or omit the use of the local L2P mapping table 412 in the DRAM 410 and use signaling case 510. Signaling case 510 is based on the assumption that a random read transaction is likely to have an incorrect address in the local L2P mapping table 412. Thus, in signaling case 510, at 512, the control circuitry 404 sends a read command to the UFS memory 406, and in particular to the SRAM 416, via the memory bus 408. At 514, the SRAM 416 checks the partial L2P mapping table 422 for the logical address. Then, at 516, the UFS memory 406 reads the logical block from the NAND memory element 418, and the read data is transferred to the SoC 402. Signaling case 510 avoids the cache misses of signaling case 330 and improves performance.

[0028]

[0034] A more complete description of a process 600 relevant to the present disclosure is provided with reference to Figure 6. The process 600 begins with a read request initiation from a file system in the SoC 402 (block 602). The host controller or control circuitry 404 initiates a command lookup (block 604). The control circuitry 404 may determine whether the HPB is valid (block 606).

[0029]

[0035] If the answer to block 606 is no, the HPB is not enabled, and the process 600 enters legacy mode and fetches an address from the memory controller 414 (block 608), which updates an entry in the SRAM 416 (block 610), and reads data from the raw NAND memory element 418 (block 612). Note that this path corresponds to possible signaling cases 300 and 310.

[0030]

[0036] However, if the answer to block 606 is yes, HPB is enabled and the process 600 determines the active size of the active portion in the local L2P mapping table 412 in the DRAM 410 (block 614). Similarly, although not shown, the process 600, and in particular the control circuitry 404, may determine the inactive size of the inactive portion. This determination of the active size may be done directly (e.g., how many addresses are active) or indirectly (e.g., find how many addresses are inactive and then subtract the number of inactive addresses from the total number of addresses to determine how many addresses are active). The control circuitry 404 may then compare the active size to a threshold (block 616). As discussed above, an exemplary threshold is the number of inactive addresses or inactive sub-regions. Note that this threshold may be a scaled value of the inactive addresses. For example, the active size is greater than 55 percent of the inactive size. As another example, if the number of active addresses exceeds the number of inactive addresses, then the number of inactive addresses is effectively the threshold.

[0031]

[0037] Based on the comparison, the process 600 branches. In a first pass, the control circuitry 404 determines that the active size in the DRAM 410 exceeds the inactive size (block 618). Thus, the control circuitry 404 fetches a physical address from the DRAM 410, specifically from the local L2P mapping table 412 (block 620). Upon receiving a read command with a physical address, the UFS memory 406 executes a transaction to read raw data from the NAND memory element 418 (block 622).

[0032]

[0038] In the second pass, the control circuitry 404 determines that the active size in the DRAM 410 is less than the threshold (block 624). Thus, the control circuitry 404 fetches the physical address from the SRAM 416 (block 626), and in particular, fetches from the partial L2P mapping table 422 instead of the DRAM 410. If there is no entry in the SRAM 416, the process may protect the address by entering legacy mode as described above. Once the physical address is identified, the UFS memory 406 performs a transaction to read the raw data from the NAND memory element 418 (block 622).

[0033]

[0039] Systems and methods for fast memory access according to aspects disclosed herein may be provided within or integrated into any processor-based device, including, but not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0034]

[0040] In this regard, Figure 7 illustrates an example of a processor-based system 700 that can employ the high speed memory access processes illustrated in Figures 4-6. While mobile terminals having UFS memory are particularly contemplated as being able to benefit from the exemplary aspects of the present disclosure, it should be understood that the present disclosure is not so limited and may be useful in any system having NAND-based memory elements.

[0035]

[0041] 7, the processor-based system 700 includes an application processor 704 (sometimes referred to as a host) that communicates with a mass storage element 706 (e.g., UFS memory 406) through a UFS bus 708 (e.g., UFS bus 408). The application processor 704 may be further connected to a display 710 through a display serial interface (DSI) bus 712 and to a camera 714 through a camera serial interface (CSI) bus 716. Various audio elements, such as a microphone 718, a speaker 720, and an audio codec 722, may be coupled to the application processor 704 through a serial low power inter-chip multimedia bus (SLIMbus) 724. In addition, the audio elements may communicate with each other through a SOUNDWIRE bus 726. A modem 728 may also be coupled to the SLIMbus 724 and / or the SOUNDWIRE bus 726. The modem 728 may further be connected to the application processor 704 through a peripheral component interconnect (PCI) or PCI Express (PCIe) bus 730 and / or a system power management interface (SPMI) bus 732.

[0036]

[0042] 7, the SPMI bus 732 may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 734, a power management integrated circuit (PMIC) 736, a companion IC (sometimes referred to as a bridge chip) 738, and a radio frequency IC (RFIC) 740. It should be appreciated that separate PCI buses 742 and 744 may also couple the application processor 704 to the companion IC 738 and the WLAN IC 734. The application processor 704 may be further connected to sensors 746 through a sensor bus 748. The modem 728 and the RFIC 740 may communicate using a bus 750.

[0037]

[0043] 7, the RFIC 740 may couple to one or more RFFE elements, such as an antenna tuner 752, a switch 754, and a power amplifier 756, through a radio frequency front end (RFFE) bus 758. Additionally, the RFIC 740 may couple to an envelope tracking power supply (ETPS) 760 through a bus 762, which may communicate with the power amplifier 756. Collectively, the RFFE elements including the RFIC 740 may be considered to be an RFFE system 764. It should be understood that the RFFE bus 758 may be formed from clock and data lines (not shown).

[0038]

[0044] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, as instructions stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The master device and the slave device described herein may be used in any circuit, hardware component, IC, or IC chip, as examples. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0039]

[0045] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0040]

[0046] Aspects disclosed herein may be embodied in hardware and instructions stored in the hardware and may reside in, for example, a random access memory (RAM), a flash memory, a read-only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0041]

[0047] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and explanations. The described operations may be performed in many different orders other than the order shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. In addition, one or more operational steps described in the exemplary aspects may be combined. It should be understood that many different modifications may be made to the operational steps shown in the flowchart diagrams, as would be readily apparent to one of ordinary skill in the art. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0042]

[0048] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other examples. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0043]

[0049] The following numbered clauses describe example implementations. 1. a memory bus interface configured to couple to a universal flash storage (UFS) memory having an external cache memory, the external cache memory comprising a local logical-to-physical (L2P) mapping table for the UFS memory; a local cache memory having a local L2P mapping table for the UFS memory; a control circuit coupled to the memory bus interface and to the local cache memory, determining an active size of an active portion of the local L2P mapping table in the local cache memory; comparing the active size of the active portion with a threshold; A control circuit configured as follows: A system-on-chip (SoC) comprising: 2. The SoC of clause 1, wherein the control circuit configured to determine the active size is configured to determine the active size by determining an inactive size of an inactive portion of a local L2P mapping table in a local cache memory. 3. The SoC of clause 1 or 2, wherein the threshold comprises an inactive size of an inactive portion of a local L2P mapping table in a local cache memory. 4. The control circuit detects when the active size does not meet the threshold. The SoC of clauses 1-3, further configured to perform the read call by sending a read command to an external cache memory without consulting a local L2P mapping table in the local cache memory. 5. The SoC of clause 4, wherein the control circuitry is further configured to retrieve an L2P map entry from the partial L2P mapping table in the external cache memory in response to a read command. 6. The SoC of clause 4 or 5, wherein the control circuit is further configured to issue a call directly to a NAND memory element in the UFS memory when, for a read command, the partial L2P mapping table does not have an entry for the logical address in the read command. 7. The SoC described in any one of clauses 1 to 6, wherein the control circuit is further configured to access an address in a local L2P mapping table in the local cache memory when the active size exceeds a threshold value. 8. The SoC of any one of clauses 1 to 7, wherein the control circuit is further configured to synchronize a local L2P mapping table in the local cache memory with an address table in the UFS memory. 9. The SoC of any of clauses 1-8, wherein the control circuitry is further configured to determine whether host performance boost is enabled. 10. The SoC of any of clauses 1 to 9, wherein the control circuit configured to determine the active size determines the active size based on how many entries are identical between the local L2P mapping table and the partial L2P mapping table. 11. The SoC of any one of clauses 1 to 10, wherein the local cache memory includes dynamic random access memory (DRAM). 12. a memory bus interface configured to couple to a universal flash storage (UFS) memory having an external cache memory, the external cache memory comprising a partial logical-to-physical (L2P) mapping table of the UFS memory; a local cache memory having a local L2P mapping table for the UFS memory; a control circuit coupled to the memory bus interface and to the local cache memory, determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory; comparing the inactive size of the inactive portion to a threshold; A control circuit configured as follows: A system-on-chip (SoC) comprising: 13. The SoC of clause 12, wherein the control circuit configured to determine the inactive size is configured to determine the inactive size by determining an active size of an active portion of a local L2P mapping table in a local cache memory. 14. The SoC of clause 12 or 13, wherein the threshold comprises an active size of an active portion of a local L2P mapping table in a local cache memory. 15. The control circuit detects when the inactive size does not meet the threshold. The SoC of any of clauses 12-14, further configured to perform the read call by sending a read command to an external cache memory without referring to a local L2P mapping table in the local cache memory. 16. The SoC of clause 15, wherein the control circuitry is further configured to retrieve an L2P map entry from the partial L2P mapping table in the external cache memory in response to a read command. 17. The SoC of clause 15, wherein the control circuitry is further configured to, for a read command, issue a call directly to a NAND memory element in the UFS memory when the partial L2P mapping table does not have an entry for the logical address in the read command. 18. The SoC described in any one of clauses 12 to 17, wherein the control circuit is further configured to access an address in a local L2P mapping table in the local cache memory when the inactive size exceeds a threshold. 19. The SoC of any one of clauses 12-18, wherein the control circuit is further configured to synchronize a local L2P mapping table in the local cache memory with an address table in the UFS memory. 20. The SoC described in any one of clauses 12 to 19, wherein the control circuit is further configured to determine whether the host performance booster is enabled. 21. The SoC of any of clauses 12-20, wherein the control circuit configured to determine the inactive size determines the inactive size based on how many entries in the partial L2P mapping table are not found in the local L2P mapping table. 22. A method for accessing memory from a host, comprising: determining an active size of an active portion of a local logical-to-physical (L2P) mapping table in a local cache memory associated with the host relative to a partial L2P mapping table in an external cache memory in a remote memory device; comparing an active size of the active portion to a threshold; A method comprising: 23. The method of clause 22, wherein determining the active size includes determining an inactive size of an inactive portion of a local L2P mapping table in a local cache memory. 24. The method of clause 22 or 23, wherein comparing the active size includes comparing the active size to an inactive size of an inactive portion of a local L2P mapping table in a local cache memory. 25. When the active size does not meet the threshold, 25. The method of any of clauses 22-24, further comprising performing the read call by sending a read command to the external cache memory without consulting a local L2P mapping table in the local cache memory. 26. The method of clause 25, further comprising retrieving an L2P map entry from a partial L2P mapping table in the external cache memory for a read command. 27. The method of clause 25 or 26, further comprising, for a read command, issuing a call directly to a NAND memory element in the UFS memory when the partial L2P mapping table does not have an entry for the logical address in the read command. 28. The method of any of clauses 22-27, further comprising accessing an address in a local L2P mapping table in a local cache memory when the active size exceeds a threshold. 29. The method of any of clauses 22-28, further comprising determining whether a host performance booster is enabled. The invention as described in the claims of the original application is set forth below. [C1] a memory bus interface configured to couple to a universal flash storage (UFS) memory having an external cache memory, the external cache memory comprising a partial logical-to-physical (L2P) mapping table of the UFS memory; a local cache memory having a local L2P mapping table for said UFS memory; a control circuit coupled to the memory bus interface and to the local cache memory, determining an active size of an active portion of the local L2P mapping table in the local cache memory; comparing the active size of the active portion to a threshold; A control circuit configured as follows: A system-on-chip (SoC) comprising: [C2] The SoC described in C1, wherein the control circuitry configured to determine the active size is configured to determine the active size by determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory. [C3] The SoC of C1, wherein the threshold comprises an inactive size of an inactive portion of the local L2P mapping table in the local cache memory. [C4] When the active size does not meet the threshold, the control circuit: The SoC of C1, further configured to perform a read call by sending a read command to the external cache memory without referencing the local L2P mapping table in the local cache memory. [C5] The SoC of C4, wherein the control circuitry is further configured to retrieve an L2P map entry from the partial L2P mapping table in the external cache memory for the read command. [C6] The SoC of C4, wherein the control circuitry is further configured to issue a call directly to a NAND memory element in the UFS memory when, for the read command, the partial L2P mapping table does not have an entry for the logical address in the read command. [C7] The SoC of C1, wherein the control circuitry is further configured to access an address in the local L2P mapping table in the local cache memory when the active size exceeds the threshold. [C8] The SoC of C1, wherein the control circuitry is further configured to synchronize the local L2P mapping table in the local cache memory with an address table in the UFS memory. [C9] The SoC of C1, wherein the control circuitry is further configured to determine whether a host performance boost is enabled. [C10] The SoC of C1, wherein the control circuitry configured to determine the active size determines the active size based on how many entries are identical between the local L2P mapping table and the partial L2P mapping table. [C11] The SoC of C1, wherein the local cache memory includes dynamic random access memory (DRAM). [C12] a memory bus interface configured to couple to a universal flash storage (UFS) memory having an external cache memory, the external cache memory comprising a partial logical-to-physical (L2P) mapping table of the UFS memory; a local cache memory having a local L2P mapping table for said UFS memory; a control circuit coupled to the memory bus interface and to the local cache memory, determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory; comparing the inactive size of the inactive portion to a threshold; A control circuit configured as follows: A system-on-chip (SoC) comprising: [C13] The SoC of C12, wherein the control circuitry configured to determine the inactive size is configured to determine the inactive size by determining an active size of an active portion of the local L2P mapping table in the local cache memory. [C14] The SoC of C12, wherein the threshold comprises an active size of an active portion of the local L2P mapping table in the local cache memory. [C15] When the inactive size does not meet the threshold, the control circuit: The SoC of C12, further configured to perform a read call by sending a read command to the external cache memory without referencing the local L2P mapping table in the local cache memory. [C16] The SoC of C15, wherein the control circuitry is further configured to retrieve an L2P map entry from the partial L2P mapping table in the external cache memory for the read command. [C17] The SoC of C15, wherein the control circuitry is further configured to issue a call directly to a NAND memory element in the UFS memory when, for the read command, the partial L2P mapping table does not have an entry for the logical address in the read command. [C18] The SoC of C12, wherein the control circuitry is further configured to access an address in the local L2P mapping table in the local cache memory when the inactive size exceeds the threshold. [C19] The SoC of C12, wherein the control circuitry is further configured to synchronize the local L2P mapping table in the local cache memory with an address table in the UFS memory. [C20] The SoC of C12, wherein the control circuitry is further configured to determine whether a host performance booster is enabled. [C21] The SoC of C12, wherein the control circuitry configured to determine the inactive size determines the inactive size based on how many entries in the partial L2P mapping table are not found in the local L2P mapping table. [C22] 1. A method for accessing a memory from a host, comprising: determining an active size of an active portion of a local logical-to-physical (L2P) mapping table in a local cache memory associated with the host relative to a partial L2P mapping table in an external cache memory in a remote memory device; comparing the active size of the active portion to a threshold; A method comprising: [C23] The method of C22, wherein determining the active size includes determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory. [C24] The method of C22, wherein comparing the active size includes comparing the active size to an inactive size of an inactive portion of the local L2P mapping table in the local cache memory. [C25] When the active size does not meet the threshold, The method of C22, further comprising: performing a read call by sending a read command to the external cache memory without referencing the local L2P mapping table in the local cache memory. [C26] The method of C25, further comprising retrieving an L2P map entry from the partial L2P mapping table in the external cache memory for the read command. [C27] The method of C25, further comprising, for the read command, issuing a call directly to a NAND memory element in the UFS memory when the partial L2P mapping table does not have an entry for the logical address in the read command. [C28] The method of C22, further comprising: accessing an address in the local L2P mapping table in the local cache memory when the active size exceeds the threshold. [C29] The method of C22, further comprising determining whether a host performance booster is enabled.

Claims

1. a memory bus interface configured to couple to a universal flash storage (UFS) memory having an external cache memory, the external cache memory comprising a partial logical-to-physical (L2P) mapping table of the UFS memory; a local cache memory containing a local L2P mapping table for said UFS memory; a control circuit coupled to the memory bus interface and to the local cache memory, determining an active size of an active portion of the local L2P mapping table in the local cache memory; comparing the active size of the active portion to a threshold; accessing an address in the local L2P mapping table in the local cache memory when the active size exceeds the threshold; A control circuit configured as follows: A system on chip (SoC) comprising:

2. 2. The SoC of claim 1, wherein the control circuitry configured to determine the active size is configured to determine the active size by determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

3. The SoC of claim 1 , wherein the threshold comprises an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

4. When the active size does not exceed the threshold, the control circuit: The SoC of claim 1 , further configured to execute a read call by sending a read command to the external cache memory without referencing the local L2P mapping table in the local cache memory.

5. The SoC of claim 4 , wherein the control circuitry is further configured to retrieve an L2P map entry from the partial L2P mapping table in the external cache memory for the read command.

6. 5. The SoC of claim 4, wherein the control circuitry is further configured to issue a call directly to a NAND memory element in the UFS memory when, for the read command, the partial L2P mapping table does not have an entry for the logical address in the read command.

7. The SoC of claim 1 , wherein the control circuitry is further configured to synchronize the local L2P mapping table in the local cache memory with an address table in the UFS memory.

8. The SoC of claim 1 , wherein the control circuitry is further configured to determine if a host performance booster is enabled.

9. 2. The SoC of claim 1, wherein the control circuitry configured to determine the active size determines the active size based on how many entries are identical between the local L2P mapping table and the partial L2P mapping table.

10. The SoC of claim 1 , wherein the local cache memory comprises a dynamic random access memory (DRAM).

11. a memory bus interface configured to couple to a universal flash storage (UFS) memory having an external cache memory, the external cache memory comprising a partial logical-to-physical (L2P) mapping table of the UFS memory; a local cache memory containing a local L2P mapping table for said UFS memory; a control circuit coupled to the memory bus interface and to the local cache memory, determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory; comparing the inactive size of the inactive portion to a threshold; accessing an address in the local L2P mapping table in the local cache memory when the inactive size does not exceed the threshold; A control circuit configured as follows: A system on chip (SoC) comprising:

12. 12. The SoC of claim 11, wherein the control circuitry configured to determine the inactive size is configured to determine the inactive size by determining an active size of an active portion of the local L2P mapping table in the local cache memory.

13. The SoC of claim 11 , wherein the threshold comprises an active size of an active portion of the local L2P mapping table in the local cache memory.

14. When the inactive size exceeds the threshold, the control circuit:

12. The SoC of claim 11, further configured to execute a read call by sending a read command to the external cache memory without referencing the local L2P mapping table in the local cache memory.

15. 15. The SoC of claim 14, wherein the control circuitry is further configured to retrieve an L2P map entry from the partial L2P mapping table in the external cache memory for the read command.

16. The control circuit, in response to the read command, 15. The SoC of claim 14, further configured to issue a call directly to a NAND memory element in the UFS memory when the partial L2P mapping table does not have an entry for the logical address in the read command.

17. 12. The SoC of claim 11, wherein the control circuitry is further configured to synchronize the local L2P mapping table in the local cache memory with an address table in the UFS memory.

18. The SoC of claim 11 , wherein the control circuitry is further configured to determine if a host performance booster is enabled.

19. 12. The SoC of claim 11, wherein the control circuitry configured to determine the inactive size determines the inactive size based on how many entries in the partial L2P mapping table are not found in the local L2P mapping table.

20. A method for accessing a Universal Flash Storage (UFS) memory having an external cache memory in a remote memory device from a host having control circuitry, the method comprising: determining an active size of an active portion of a local logical-to-physical (L2P) mapping table in a local cache memory associated with a host for a partial L2P mapping table in the external cache memory in the remote memory device; comparing the active size of the active portion to a threshold; accessing an address in the local L2P mapping table in the local cache memory when the active size exceeds the threshold; A method comprising:

21. 21. The method of claim 20, wherein determining the active size comprises determining an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

22. 21. The method of claim 20, wherein comparing the active size comprises comparing the active size to an inactive size of an inactive portion of the local L2P mapping table in the local cache memory.

23. When the active size does not exceed the threshold, 21. The method of claim 20, further comprising: executing a read call by sending a read command to the external cache memory without referencing the local L2P mapping table in the local cache memory.

24. 24. The method of claim 23, further comprising retrieving an L2P map entry from the partial L2P mapping table in the external cache memory for the read command.

25. For the read command, 24. The method of claim 23, further comprising: issuing a call directly to a NAND memory element in the UFS memory when the partial L2P mapping table does not have an entry for the logical address in the read command.

26. 21. The method of claim 20, further comprising: accessing an address in the local L2P mapping table in the local cache memory when the active size exceeds the threshold.

27. 21. The method of claim 20, further comprising determining whether a host performance booster is enabled.

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