Semiconductor device manufacturing method

Abstract

To improve the electric characteristics of a semiconductor device.SOLUTION: An n-type MISFET1Tr includes a semiconductor layer SI1 formed of silicon on a semiconductor substrate SB, a channel layer BD1, an n-type source SR1, and an n-type drain SR1 formed on the semiconductor layer SI1, a gate electrode GE1 formed on the channel layer BD1 through a gate insulating film GI1, and an embedded electrode BE1 formed below the channel layer BD1 through an embedded insulating film BZ1. The n-type source SR1 and the embedded electrode BE1 are connected with a wire M1 to which a reference potential is supplied. The embedded electrode BE1 is formed of a metal layer with a work function of more than 4.6 eV.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a technique that is effective when applied to a semiconductor device using an SOI substrate and a manufacturing method thereof. [Background technology]

[0002] The function of a transistor is to control the amount of current carriers that flow from the source through the channel to the drain by applying a voltage to the gate electrode. Therefore, the performance index is that the current value in the ON state is as large as possible and the leakage current in the OFF state is as small as possible. In addition, for high frequency applications, a transistor with a small capacitance and a cutoff frequency f T In particular, for low power consumption applications such as mobile devices and IoT (Internet of Things) devices, a small off-state current is an essential requirement.

[0003] In transistors with a conventional structure (n-type MISFET4Tr in Figure 13), improvements in performance and integration have been achieved through miniaturization. However, with gate lengths of 100 nm or less, it has become difficult to improve characteristics through miniaturization. This is because an increase in the Off current, which is one of the phenomena of the short channel effect, becomes significant. As the source / drain distance, i.e., the channel length, becomes smaller, the number of carriers that are drawn out from the source and leak out due to the action of the voltage applied to the drain increases, and the Off current increases.

[0004] To reduce this, it is necessary to increase the doping impurity concentration added to the channel (the upper part of the well region PW4 in FIG. 13). However, increasing the impurity concentration increases carrier scattering (scattering by impurities and scattering at the interface between the gate insulating film and the semiconductor substrate due to increasing the electric field strength toward the gate), which reduces the mobility and decreases the ON current. In addition, there is also the disadvantage that the transistor characteristics, especially the threshold voltage, vary due to variations in the impurity concentration, particularly the statistical variation in the number of dopant atoms contained in the channel, which is unavoidable in principle. Therefore, in order to increase the ON current and reduce the variation in transistor characteristics, it is desirable to keep the doping impurity concentration of the channel as small as possible.

[0005] As a means of solving this problem, a transistor using an SOI (Silicon On Insulator) substrate has been proposed (MISFET3Tr in Fig. 13). By limiting the thickness of the channel layer (semiconductor layer BD3) to a range where the effect of the gate electrode is effective, the effect of the drain voltage, i.e., the short channel effect, can be reduced and the doping impurity concentration of the channel layer can be lowered, which is effective in suppressing the off current. Furthermore, the potential of the channel layer can be controlled by the potential of the well region PW3 provided on the silicon substrate surface, which has a significant effect of shielding the influence of the drain voltage on the source.

[0006] However, in miniaturized transistors with gate lengths of 50 nm or less, it has been difficult to reduce the short channel effect. The reason is that the thickness of the channel layer (semiconductor layer BD3) and the thickness of the buried insulating layer BZ3 cannot be reduced indefinitely. Making the channel thinner leads to interface scattering, which reduces carrier mobility. In addition, variations in the film thickness of the channel layer increase the variation in transistor characteristics. Furthermore, since the impurity concentration of the well region PW3 provided on the surface of the silicon substrate cannot be increased indefinitely, the voltage applied to the channel layer is also distributed to the voltage drop occurring near the surface of the well region PW3, and in miniaturized transistors, the effect of the well region PW3 (back gate) in controlling the potential of the channel layer is limited, which has been an issue.

[0007] As a means for solving such problems, a double-gate type SOI-MISFET is known.

[0008] Patent Document 1 describes a metal backgate type thin-film SOI device.

[0009] On page 104 of Non-Patent Document 1, "Multiple-Gate FD SOI MOSFET" is described. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Special Publication No. 2013-522908 [Non-patent literature]

[0011] [Non-Patent Document 1] IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL.4,NO.1,MARCH 2004, pages 99-109 Summary of the Invention [Problem to be solved by the invention]

[0012] There is a demand for technology that can reduce the short channel effect in SOI-MISFETs with gate lengths of 50 nm or less.

[0013] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0014] A semiconductor device according to an embodiment has an n-type double-gate type SOI-MISFET, which includes a semiconductor layer made of silicon formed on a semiconductor substrate, a channel layer formed in the semiconductor layer, an n-type source and an n-type drain, a gate electrode formed on the channel layer via a gate insulating film, and a buried electrode (backgate) formed under the channel layer via a buried insulating film. The n-type source and the buried electrode are connected by a wiring to which a reference potential is supplied, and the buried electrode is formed of a metal layer having a work function larger than 4.6 eV.

[0015] A semiconductor device according to an embodiment has a p-type double-gate type SOI-MISFET, which includes a semiconductor layer made of silicon formed on a semiconductor substrate, a channel layer formed in the semiconductor layer, a p-type source and a p-type drain, a gate electrode formed on the channel layer via a gate insulating film, and a buried electrode (backgate) formed under the channel layer via a buried insulating film. The p-type source and the buried electrode are connected by a wiring to which a power supply potential is supplied, and the buried electrode is formed of a metal layer having a work function of 4.6 eV or less.

[0016] A semiconductor device according to an embodiment has an n-type double-gate type SOI-MISFET and a p-type double-gate type SOI-MISFET, the n-type MISFET including a first semiconductor layer made of silicon formed on a semiconductor substrate, a first channel layer, an n-type source, and an n-type drain formed in the first semiconductor layer, a first gate electrode formed on the first channel layer via a first gate insulating film, and a first buried electrode made of a first metal layer formed under the first channel layer via a first buried insulating film, and the p-type MISFET including a second semiconductor layer made of silicon formed on a semiconductor substrate, a second channel layer, a p-type source, and a p-type drain formed in the second semiconductor layer, a second gate electrode formed on the second channel layer via a second gate insulating film, and a second buried electrode made of a second metal layer formed under the second channel layer via a second buried insulating film. The n-type source and the first buried electrode are connected to a first wiring to which a reference potential is supplied, the p-type source and the second buried electrode are connected to a second wiring to which a power supply potential is supplied, and the first metal layer and the second metal layer have work functions different from each other.

[0017] A manufacturing method of a semiconductor device according to one embodiment includes the steps of sequentially forming a first semiconductor layer and a second semiconductor layer made of silicon on a main surface of a semiconductor substrate, defining an active region in the semiconductor substrate by an element isolation layer, sequentially forming a gate insulating film and a gate electrode on the second semiconductor layer, introducing impurities into the second semiconductor layer at both ends of the gate electrode to form a first semiconductor region and a second semiconductor region, forming a mask layer covering the gate electrode and a portion of the first semiconductor region, and removing the second semiconductor layer and the first semiconductor layer exposed from the mask layer to form an opening exposing a main surface of the semiconductor substrate, removing the first semiconductor layer present between the semiconductor substrate and the second semiconductor layer to form a cavity connected to the opening, forming an insulating film around the main surface of the semiconductor substrate and around a stacked structure made of the second semiconductor layer and the mask layer, forming a buried electrode made of a metal layer so as to fill the opening and the cavity, and forming wiring connecting the buried electrode and the first semiconductor region. Effect of the Invention

[0018] According to one embodiment, the electrical characteristics of a semiconductor device can be improved. [Brief description of the drawings]

[0019] [Figure 1] 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment; [Diagram 2] 1 is a plan view of a semiconductor device according to an embodiment; [Diagram 3] 2'。 FIG. 2' is a cross-sectional view. [Figure 4] 1 is a table showing electrical characteristics of the semiconductor device according to the embodiment. [Diagram 5] 4 is a graph showing electrical characteristics of the semiconductor device according to the embodiment; [Figure 6] 3A to 3C are cross-sectional views showing a manufacturing process of the semiconductor device according to the embodiment; [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device following FIG. 6. [Figure 8] 8 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 11] 11 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. 11. [Figure 13] FIG. 1 is a cross-sectional view showing a semiconductor device according to a conventional technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for components having the same functions, and the repeated description thereof will be omitted. In order to make the drawings easier to understand, hatching may be used even in plan views. The semiconductor substrate SB has a main surface SBa and a back surface SBb, and the side on which the MISFET is formed is called the main surface SBa.

[0021] (Embodiment) The semiconductor device of this embodiment includes a fully depleted double-gate SOI-MISFET with a gate length of 50 nm or less. The double-gate SOI-MISFET includes a semiconductor layer made of silicon formed on a semiconductor substrate, a semiconductor layer (channel layer) formed in the semiconductor layer, two semiconductor regions functioning as a source and a drain, a gate electrode formed on the channel layer via a gate insulating film, and a buried electrode (backgate) formed under the channel layer via a buried insulating film. The buried electrode (backgate) made of a metal layer and the semiconductor region functioning as a source are connected by wiring, and the work function of this metal layer is greater than 4.6 eV in the case of an n-type MISFET and is less than 4.6 eV in the case of a p-type MISFET.

[0022] Moreover, a CMOS type semiconductor device including an n-type MISFET and a p-type MISFET is characterized in that a metal layer constituting a buried electrode (backgate) of the n-type MISFET and a metal layer constituting a buried electrode (backgate) of the p-type MISFET have different work functions.

[0023] With this configuration, the electric field caused by the potential difference between the drain and source is effectively shielded by the buried electrode, suppressing the short channel effect (called the "shielding effect"). In other words, by connecting the buried electrode (backgate) to the source potential, the electric field from the drain is prevented from extending from the back side of the channel layer to the channel layer, suppressing the short channel effect. In addition, the electric field caused by the contact potential difference corresponding to the work function difference between the source in which n-type or p-type impurities are introduced and the metal layer constituting the buried electrode is applied to the source and channel layer, effectively reducing the OFF current (called the "carrier suppression effect"). In addition, by configuring the buried electrode with a metal layer, the aforementioned "voltage drop occurring on the surface of the well region that becomes the backgate" can be suppressed, so there is no need to make the thickness of the channel layer and the buried insulating layer extremely thin. Therefore, the decrease in carrier mobility can be suppressed, and the ON current can be increased. Furthermore, the variation in the film thickness of the channel layer can be reduced, reducing the variation in transistor characteristics such as threshold value.

[0024] <Regarding the semiconductor device according to the present embodiment> FIG. 1 is an equivalent circuit diagram of the semiconductor device of this embodiment, and is an equivalent circuit diagram of an inverter circuit as an example. FIG. 2 is a plan view of the semiconductor device of this embodiment, and is a plan view of an n-type MISFET1Tr and a p-type MISFET2Tr constituting the inverter circuit. FIG. 3 is a cross-sectional view taken along the line XX' in FIG. 2. In FIG. 2, the horizontal direction of the paper is called the X direction, and the vertical direction is called the Y direction. The X direction and the Y direction are perpendicular to each other. In the n-type MISFET1Tr and the p-type MISFET2Tr, the X direction is the gate length direction, and the Y direction is the gate width direction. In FIG. 2, the semiconductor substrate SB, the support insulating layers SZ1 and SZ2, the buried insulating layers BZ1 and BZ2, the gate insulating films GI1 and GI2, and the interlayer insulating film IL are omitted.

[0025] 1, the inverter circuit is composed of an n-type MISFET1Tr and a p-type MISFET2Tr connected in series, with the source of the p-type MISFET2Tr connected to a wiring M3 that supplies a power supply potential VDD, and the source of the n-type MISFET1Tr connected to a wiring M1 that supplies a reference potential VSS. The gates of the n-type MISFET1Tr and the p-type MISFET2Tr are connected to a wiring M4 for the input of the inverter circuit, and the drains of the n-type MISFET1Tr and the p-type MISFET2Tr are connected to a wiring M2 for the output of the inverter circuit.

[0026] 2, n-type MISFET1Tr is formed in an active region ACT1, p-type MISFET2Tr is formed in an active region ACT2, and the two are isolated by an element isolation layer STI. In other words, the active regions ACT1 and ACT2 are each surrounded by an element isolation layer STI, and the active regions ACT1 and ACT2 are each defined by the element isolation layer STI.

[0027] In the active region ACT1, a buried electrode BE1 and a semiconductor layer SI1 are arranged in the X direction, and the two are electrically separated by an insulating film ZF1. In the semiconductor layer SI1, a semiconductor region SR1 functioning as a source, a semiconductor layer BD1, and a semiconductor layer SR1 functioning as a drain are formed in this order, and a gate electrode GE1 is arranged on the semiconductor layer BD1, which is a channel layer. In addition, under the semiconductor layer SI1, a buried electrode BE1 extends so as to overlap the semiconductor region SR1, the semiconductor layer BD1, and the semiconductor region SR1. A part of the buried electrode BE1 is exposed from the semiconductor layer SI1 in the vicinity of the semiconductor region SR1 functioning as a source, and the buried electrode BE1 and the semiconductor region SR1 functioning as a source are connected by a wiring M1 to which a reference potential VSS is supplied via a plug made of a metal layer. The semiconductor region SR1 functioning as a drain is connected to an output wiring M2 via a plug, and the gate electrode GE1 is connected to an input wiring M4 via a plug.

[0028] In the active region ACT2, a semiconductor layer SI2 and a buried electrode BE2 are arranged in the X direction, and the two are electrically separated by an insulating film ZF1. In the semiconductor layer SI2, a semiconductor region SR2 functioning as a drain, a semiconductor layer BD2, and a semiconductor layer SR2 functioning as a source are formed in this order, and a gate electrode GE2 is arranged on the semiconductor layer BD2, which is a channel layer. In addition, a buried electrode BE2 extends under the semiconductor layer SI2, overlapping with the semiconductor region SR2, the semiconductor layer BD2, and the semiconductor region SR2. A part of the buried electrode BE2 is exposed from the semiconductor layer SI2 in the vicinity of the semiconductor region SR2 functioning as a source, and the buried electrode BE2 and the semiconductor region SR2 functioning as a source are connected by a wiring M3 to which a power supply potential VDD is supplied via a plug made of a metal layer. The semiconductor region SR2 functioning as a drain is connected to the wiring M2 for output via a plug, and the gate electrode GE2 is connected to the wiring M4 for input via a plug.

[0029] As shown in FIG. 3, the n-type MISFET 1Tr is formed on the main surface SBa of the semiconductor substrate SB made of silicon via a support insulating layer SZ1. The n-type MISFET 1Tr includes a semiconductor layer SI1, a gate electrode GE1 formed on the semiconductor layer SI1 via a gate insulating film GI1, and a buried electrode (backgate) BE1 formed under the semiconductor layer SI1 via a buried insulating film BZ1. The support insulating layer SZ1 and the buried insulating layer BZ1 are, for example, silicon oxide layers. The semiconductor layer SI1 made of silicon has two semiconductor regions SR1 functioning as a source and a drain, and a semiconductor layer (channel layer) BD1 disposed between the two semiconductor regions SR1. The buried electrode BE1 and the semiconductor region SR1 functioning as a source are connected by a wiring M1 to which a reference potential VSS is supplied via a plug made of a metal layer (for example, tungsten).

[0030] In order to reduce the short channel effect, taking into consideration the electric field that the gate potential and drain potential exert on the semiconductor layer (channel layer) BD1, the thickness of the semiconductor layer (channel layer) SI1 is preferably less than 1 / 3 of the gate length. The thickness of the buried insulating film BZ1 is preferably in the range of 1 / 10 to 1 / 1 of the gate length so that the buried electrode BE1 shields the electric field lines that detouring from the drain to the semiconductor layer (channel layer) BD1 due to the drain voltage.

[0031] The two semiconductor regions SR1 functioning as a source and a drain are n-type semiconductor regions doped with, for example, phosphorus, arsenic, or both, and the impurity concentration is 1e19 / cm 3 ~1e22 / cm 3 The semiconductor layer (channel layer) BD1 is an intrinsic semiconductor layer, and its dopant impurity concentration is 1e18 / cm 3 It is preferable that the concentration is not more than this value, because if the concentration exceeds this value, the decrease in carrier mobility becomes significant.

[0032] The buried electrode BE1 is made of a metal film (metal layer) MF, and it is essential that the metal film (metal layer) MF is made of a metal material having a work function larger than the mid-gap 4.6 eV of silicon constituting the semiconductor layer SI1. The metal film (metal layer) MF is, for example, platinum (Pt), iridium (Ir), nickel (Ni) or titanium nitride (TiN). The respective work functions are Pt (5.65 eV), Ir (5.4 eV), Ni (5.15 eV), TiN (4.7 to 4.9 eV), and alloys thereof.

[0033] The semiconductor region SR1 serving as the source is doped with n-type impurities (donor impurities), so the Fermi level is higher than the midgap and close to the conduction band edge. The semiconductor region SR1 serving as the source and the buried electrode BE1 are connected by the wiring M1, so the buried electrode BE1 has a negative potential due to the contact potential difference between the semiconductor region SR1 serving as the source and the buried electrode BE1. The buried electrode BE1 at the negative potential exerts an electric field on the source and the semiconductor layer (channel layer) BD1 in a direction that suppresses negatively charged electron carriers, so that the Off current can be reduced.

[0034] The p-type MISFET2Tr is formed on the main surface SBa of the semiconductor substrate SB made of silicon via a support insulating layer SZ2. The p-type MISFET2Tr includes a semiconductor layer SI2, a gate electrode GE2 formed on the semiconductor layer SI2 via a gate insulating film GI2, and a buried electrode (backgate) BE2 formed under the semiconductor layer SI2 via a buried insulating film BZ2. The support insulating layer SZ2 and the buried insulating layer BZ2 are, for example, silicon oxide layers. The semiconductor layer SI2 made of silicon has two semiconductor regions SR2 functioning as a source and a drain, and a semiconductor layer (channel layer) BD2 disposed between the two semiconductor regions SR2. The buried electrode BE2 and the semiconductor region SR2 functioning as a source are connected to a wiring M3 to which a power supply potential VDD is supplied via a plug made of a metal layer (for example, tungsten).

[0035] In order to reduce the short channel effect, the thickness of the semiconductor layer (channel layer) SI2 is preferably less than 1 / 3 of the gate length, taking into consideration the electric field that the gate potential and drain potential exert on the semiconductor layer (channel layer) BD2. The thickness of the buried insulating film BZ2 is preferably in the range of 1 / 10 to 1 / 1 of the gate length, so that the buried electrode BE2 shields the electric field lines that detouring from the drain to the semiconductor layer (channel layer) BD2 due to the drain voltage.

[0036] The two semiconductor regions SR2 functioning as a source and a drain are, for example, p-type semiconductor regions doped with boron, and the impurity concentration is 1e19 / cm 3 ~1e22 / cm 3 The semiconductor layer (channel layer) BD2 is an intrinsic semiconductor layer, and its dopant impurity concentration is 1e18 / cm 3 It is preferable that the concentration is not more than this value, because if the concentration exceeds this value, the decrease in carrier mobility becomes significant.

[0037] The buried electrode BE2 is made of a metal film (metal layer), and it is essential that this metal film (metal layer) is made of a metal material having a work function equal to or less than the mid-gap 4.6 eV of silicon constituting the semiconductor layer SI2. The metal film (metal layer) is made of, for example, aluminum (Al) or tungsten silicide (WSin (n=6 to 12)). The respective work functions are Al (4.1 eV) and WSin (4.0 eV).

[0038] The semiconductor region SR2 serving as the source is doped with p-type impurities (acceptor impurities), so the Fermi level is lower than the midgap and close to the valence band edge. The semiconductor region SR2 serving as the source and the buried electrode BE2 are connected by wiring M3, so the buried electrode BE2 has a positive potential due to the contact potential difference between the semiconductor region SR2 serving as the source and the buried electrode BE2. The buried electrode BE2 at a positive potential applies an electric field to the source and the semiconductor layer (channel layer) BD2 in a direction that suppresses positively charged hole carriers, so that the Off current can be reduced.

[0039] Fig. 4 is a graph showing the electrical characteristics of the semiconductor device of this embodiment, and shows the relationship between the gate voltage and the ON current of the n-type MISFET1Tr of this embodiment and the n-type MISFET3Tr of the conventional structure. This corresponds to A2(N) and EX1(N) shown in Fig. 5. The MISFET1Tr of this embodiment has an improved ON current compared to the MISFET3Tr, regardless of the gate voltage.

[0040] FIG. 5 is a table showing electrical characteristics of the semiconductor device of this embodiment. Device types EX1(N) and EX2(N) are n-type MISFET3Tr of a conventional structure, and A1(N) to A4(N) and B1(N) to B4(N) are n-type MISFET1Tr of this embodiment. EX3(P) is a P-type MISFET version of the MISFET3Tr of a conventional structure, and C1(P) to C4(P) are p-type MISFET2Tr of this embodiment. As can be seen from FIG. 5, at a gate length of 45 nm, the thickness T GE When the gate length is 28 nm, the thickness TGE When the thickness of the buried insulating films BZ1 and BZ2 is set to 20 nm or less, the ON current and the cutoff frequency are significantly improved compared to the conventional structure. From the simulation results, it was confirmed that the electrical characteristics of the semiconductor device of this embodiment are improved by setting the thickness of the buried insulating films BZ1 and BZ2 to 1 / 10 to 1 / 1 of the gate length of the gate electrodes GE1 and GE2. However, if the thickness of the buried insulating films BZ1 and BZ2 is made too thin, the carrier suppression effect of the buried electrodes (back gates) BE1 and BE2 described above will dominate the controllability of the channel layer by the gate electrodes GE1 and GE2, and the ON current will decrease. In addition, if the thickness of the buried insulating layers BZ1 and BZ2 exceeds the gate length of the gate electrodes GE1 and GE2, the above-mentioned "shielding effect" and "carrier suppression effect" will decrease, and the short channel effect will not be suppressed.

[0041] Moreover, according to this embodiment, the buried electrode BE1 of MISFET1Tr and the semiconductor region SR1 functioning as the source are connected by the wiring M1 to which a reference potential is supplied, so that the semiconductor device can be miniaturized. When a potential different from the reference potential VSS is supplied to the buried electrode BE1, a wiring for supplying power to the buried electrode BE1 is required in addition to the wiring connected to the semiconductor region SR1 functioning as the source, which may result in an increase in size of the semiconductor device. Furthermore, when a potential other than the reference potential VSS or the power supply potential VDD is supplied to the buried electrode BE1, a voltage generating circuit must be provided, which may result in an even larger size. According to this embodiment, the effect of miniaturization can be achieved in the case of MISFET2Tr as well.

[0042] <Regarding the manufacturing method of the semiconductor device according to this embodiment> A method for manufacturing the semiconductor device of this embodiment will be described below with reference to Fig. 3 and Fig. 6 to Fig. 12. Here, the manufacturing method will be described by taking an n-type MISFET 1Tr as an example.

[0043] FIG. 6 shows a process for forming the semiconductor layer SG1 and the semiconductor layer SI1. The semiconductor layer SG1 and the semiconductor layer SI1 are formed in order on the main surface SBa of the semiconductor substrate SB, which is a support substrate. Next, an element isolation layer STI is formed in the semiconductor substrate SB to define an active region ACT1. In the active region ACT1, the semiconductor substrate SB is made of, for example, a single crystal silicon layer. The semiconductor layer SI1 is a silicon layer made of an intrinsic semiconductor layer. The semiconductor layer SG1 is made of a film having a large etching rate relative to the semiconductor layer SI1 in a desired etching method. For example, it is a silicon germanium layer that can be selectively etched with hydrogen chloride gas. Here, a process can also be used in which the active region ACT1 is first defined in the semiconductor substrate SB, which is a support substrate, by the element isolation layer STI, and then the semiconductor layer SG1 and the semiconductor layer SI1 are formed in order in the active region ACT1 on the main surface SBa of the semiconductor substrate SB.

[0044] 7 shows a process of forming a gate electrode GE1 and a semiconductor region SR1. A first stack structure consisting of a gate insulating film GI1 and a gate electrode GE1 is selectively formed on the semiconductor layer SI1, and a sidewall spacer SW is provided on the sidewall of the first stack structure. Next, n-type impurities are ion-implanted into the semiconductor layer SI1 in the region exposed from the first stack structure and the sidewall spacer SW to form an n-type semiconductor region SR1. In this way, a semiconductor layer (channel layer) BD1 arranged below the gate electrode GE1 and two semiconductor regions SR1 located on both sides of the semiconductor layer (channel layer) BD1 are formed in the semiconductor layer SI1.

[0045] 8 shows an etching process of the semiconductor layers SI1 and SG1. A mask layer MK is provided to cover the first stack structure, the sidewall spacer SW, and the two semiconductor regions SR1. The mask layer MK exposes the regions of the two semiconductor regions SR1 adjacent to the element isolation layer STI. The semiconductor layers SI1 and SG1 exposed from the mask layer MK are etched to provide openings OP1 and OP2 reaching the main surface SBa of the semiconductor substrate SB.

[0046] Next, Fig. 9 shows a process of removing the semiconductor layer SG1. The semiconductor layer SG1 shown in Fig. 8 is removed, and a cavity CV communicating with the openings OP1 and OP2 is formed between the semiconductor layer SI1 and the main surface SBa of the semiconductor substrate SB. In this way, a second stacked structure is formed, which is made up of the semiconductor layer SI1, the first stacked structure, the sidewall spacer SW, and the mask layer MK. Here, in the YY' cross section of Fig. 2, the first stacked structure including the gate electrode GE1 is supported by the element isolation layer STI, so that even if the openings OP1 and OP2 and the cavity CV are provided, the second stacked structure is not lost from the semiconductor substrate SB.

[0047] 10 shows a process of forming the insulating film ZF1. The insulating film ZF1 is formed so as to cover the main surface SBa of the semiconductor substrate SB and the periphery of the second stacked structure. The insulating film ZF1 is, for example, a silicon oxide film, and its thickness is set so that the opening OP1 and the cavity CV are not filled, but the opening OP2 is filled. Since the insulating film ZF1 covering the lower surface of the second stacked structure becomes the buried insulating film BZ1 shown in FIG. 3, the sizes of the openings OP1 and OP2 and the cavity CV shown in FIG. 9 are set so that the insulating film ZF1 is 1 / 10 to 1 / 1 of the gate length of the gate electrode GE1.

[0048] 11 shows a process of forming a metal film MF. The metal film MF is formed on the semiconductor substrate SB so as to fill the opening OP1 and the cavity CV.

[0049] 12 shows an etching process of the metal film MF. The metal film MF is removed from the upper surface and sidewalls of the second stacked structure and from the element isolation layer STI, leaving the metal film MF so as to fill the opening OP1 and the cavity CV. In this way, a buried electrode BE1 is formed in the opening OP1 and the cavity CV that communicate with each other.

[0050] Next, the wiring formation process will be described with reference to FIG. 3. An interlayer insulating film IL made of, for example, a silicon oxide film is formed on the semiconductor substrate SB. Next, a plurality of plugs (plug electrodes) PG are selectively formed in the interlayer insulating film IL. The plugs (plug electrodes) PG are made of, for example, tungsten. Next, a plurality of wirings M1 to M4 are formed on the interlayer insulating film IL. The wiring M1 connects the buried electrode BE1 and the semiconductor region SR1 functioning as a source via the plug (plug electrode) PG.

[0051] In this manner, the semiconductor device of the present embodiment is manufactured.

[0052] 13 is a cross-sectional view showing a semiconductor device according to the prior art. In the semiconductor device of the present embodiment, MISFETs 3Tr and 4Tr may be provided on the same semiconductor substrate SB in addition to the above-mentioned MISFETs 1Tr and 2Tr.

[0053] The MISFET3Tr is an SOI-MISFET, and a semiconductor layer SI3 is provided on the main surface SBa of the semiconductor substrate SB via a buried insulating film BZ3, and two semiconductor regions SR3 functioning as a source and a drain and a semiconductor layer (channel layer) BD3 are formed in the semiconductor layer SI3. A gate electrode GE3 is disposed on the semiconductor layer (channel layer) BD3 via a gate insulating film GI3, and a well region PW3 is disposed below the semiconductor layer (channel layer) BD3. A desired potential is applied to the well region PW3 to control the potential of the semiconductor layer (channel layer) BD3, and the influence of the drain voltage on the source is shielded, thereby suppressing the short channel effect.

[0054] The MISFET4Tr has a gate electrode GE4 formed on the main surface SBa of the semiconductor substrate SB via a gate insulating film GI4, and two semiconductor regions SR4 functioning as a source and a drain. The MISFET4Tr is provided in a well region PW4 formed in the semiconductor substrate SB, and a channel is formed in the well region PW4.

[0055] The invention made by the inventor of the present application has been specifically described above based on the embodiments thereof. However, it goes without saying that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0056] 1Tr, 2Tr, 3Tr, 4Tr MISFET ACT1,ACT2 active region BD1, BD2, BD3 Semiconductor layer (channel layer) BE1, BE2, BE3 Buried electrode (back gate) BZ1, BZ2, BZ3 Buried insulating layer cv cavity DNW Well Region GE1, GE2, GE3, GE4 gate electrodes GI1, GI2, GI3, GI4 Gate insulating film IL Interlayer insulating film MF metal film (metal layer) MK Mask Layer M1,M2,M3,M4 wiring OP1,OP2 opening PG plug (plug electrode) PW3, PW4 well area SB Semiconductor Substrate SBa principal surface SBb back SG1 Semiconductor layer SI1, SI2, SI3 Semiconductor layer (SOI layer) SR1, SR2, SR3, SR4 Semiconductor regions (source, drain) STI element isolation layer SW Sidewall spacer SZ1, SZ2, SZ3 Support insulation layer VDD power supply potential VSS reference potential ZF1 Insulation film

Claims

1. (a) forming a first semiconductor layer and a second semiconductor layer made of silicon in sequence on a major surface of a semiconductor substrate; (b) defining an active region in the semiconductor substrate by an isolation layer; (c) forming a gate insulating film and a gate electrode in sequence on the second semiconductor layer; (d) introducing impurities into the second semiconductor layer at both ends of the gate electrode to form a first semiconductor region and a second semiconductor region; (e) forming a mask layer covering the gate electrode and a portion of the first semiconductor region, and removing the second semiconductor layer and the first semiconductor layer exposed from the mask layer to form an opening exposing the main surface of the semiconductor substrate; (f) removing the first semiconductor layer present between the semiconductor substrate and the second semiconductor layer to form a cavity communicating with the opening; (g) forming an insulating film on the main surface of the semiconductor substrate and around a stacked structure including the second semiconductor layer and the mask layer; (h) forming a buried electrode made of a metal layer so as to fill the opening and the cavity; (i) forming wiring connecting the buried electrode and the first semiconductor region; The method for manufacturing a semiconductor device comprising the steps of:

2. 2. The method of manufacturing a semiconductor device according to claim 1, the impurity is an n-type impurity, A reference potential is supplied to the wiring, A method for manufacturing a semiconductor device, wherein the metal layer has a work function greater than 4.6 eV.

3. 2. The method of manufacturing a semiconductor device according to claim 1, the impurity is a p-type impurity, A power supply potential is supplied to the wiring, The method for manufacturing a semiconductor device, wherein the metal layer has a work function of 4.6 eV or less.

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