Multi-finger semiconductor structure

Abstract

To connect PNBT SOI-FETs in parallel without disturbing the Id-Vg characteristics.SOLUTION: A multi-finger semiconductor structure 5 includes a MOSFET including a source, a drain, a first gate 20 and a body contact portion 24, and a plurality of unit semiconductor structures 1A, 1B, and 1C including semiconductor layers 26 having a type opposite to the impurity type of the body contact portion 24 between the body contact portion 24 and the source and drain are multi-finger-connected in parallel, and the body contact portion 24 and the semiconductor layer 26 are integrated.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a multi-finger semiconductor structure. [Background technology]

[0002] Large scale integrated circuits (hereinafter referred to as "LSI") used in various industrial fields are required to have low power consumption. Among LSIs, MOS field effect transistors (hereinafter referred to as "MOSFETs") are widely used due to their low power consumption.

[0003] For example, in a CMOS inverter using MOSFETs, the power consumption in the on state is P active and power consumption in the off state P standby is expressed by the following formula: P active ∝f C load ·V DD 2 (1) P standby ∝I leak ·V DD (2) where f is the operating frequency, C load is the load capacitance, V DD is the supply voltage, I leak is the off-leak current. Thus, P active is proportional to the square of the power supply voltage (equation (1)), and P standby is proportional to the power supply voltage (equation (2)). Therefore, the key to reducing the power consumption of a MOSFET is how to reduce the power supply voltage.

[0004] The on-off switching characteristics of a transistor are expressed by the subthreshold coefficient (the rise characteristic of the drain current when the gate voltage is changed in the subthreshold region). In other words, the subthreshold coefficient S is expressed as the ratio of the drain current I d The gate voltage V required to increase g And,

number

[0005] Various researches are being conducted with the aim of developing semiconductor devices that can switch at a power supply voltage below the theoretical lower limit mentioned above. For example, tunnel field effect transistors that use the tunnel effect and negative capacitance effect transistors that use the negative capacitance effect that is said to occur when a ferroelectric capacitor is connected to a normal capacitor are some of the examples. However, while these devices are expected to have excellent performance in theory, the actual measurements have not yet shown sufficient characteristics. [Prior art documents] [Patent documents]

[0006] [Non-Patent Document 1] J. Ida et al., “Super steep subthreshold slope PN-body tied SOI FET with ultra low drain voltage down to 0.1V,” in IEDM Tech. Dig., Washington, DC, USA, Dec. 2015, pp. 624.627, doi: 10.1109 / IEDM.2015.7409761. Summary of the Invention [Problem to be solved by the invention]

[0007] The present inventors have devised a semiconductor structure (PN body-tied (PNBT) SOI-FET, hereinafter referred to as "PNBT SOI-FET") that has a semiconductor layer of an impurity type opposite to that of a body contact portion of a MOSFET, adjacent to the body contact portion, as a device having a subthreshold slope (hereinafter referred to as "Super Steep Subthreshold Slope") that is lower than the theoretical lower limit of conventional MOSFETs (see, for example, Non-Patent Document 1).

[0008] When such PNBT SOI-FETs are connected in parallel using a conventional multi-finger connection, the gate voltage (V g ) versus drain current (I d ) characteristics (I d -V g However, there is a problem in that the drain current characteristic is disturbed in a step-like manner when the drain current rises.

[0009] The present invention has been made in view of the above circumstances, and its object is to d -V g To connect PNBT SOI-FETs in parallel without disturbing the characteristics. [Means for solving the problem]

[0010] In order to solve the above problems, a multi-finger semiconductor structure according to one embodiment of the present invention comprises a MOSFET including a source, a drain, a first gate, and a body contact portion, and is a multi-finger semiconductor structure in which a plurality of unit semiconductor structures including a semiconductor layer of an opposite type to the impurity type of the body contact portion are connected in parallel in a multi-finger manner between the body contact portion and the source and drain, and the body contact portion and the semiconductor layer are integrated.

[0011] In an embodiment, each of the unit semiconductor structures may include a second gate adjacent to the first gate over the semiconductor layer.

[0012] In one embodiment, the distance between the first gate and the second gate may be 50 nm or less.

[0013] In one embodiment, the impurity type of the source and drain may be N-type, the impurity type of the body contact may be P-type, and the impurity type of the semiconductor layer may be N-type.

[0014] In one embodiment, the impurity type of the source and drain may be P-type, the impurity type of the body contact may be N-type, and the impurity type of the semiconductor layer may be P-type.

[0015] In one embodiment, the MOSFET may be a SOI MOSFET.

[0016] In an embodiment, the first gates of the unit semiconductor structures may be separated for each of the unit semiconductor structures.

[0017] Any combination of the above components and any conversion of the present invention between a method, an apparatus, a system, etc. are also valid aspects of the present invention. Appropriate combinations of the above elements may also be included in the scope of the invention for which patent protection is sought by this patent application. Effect of the Invention

[0018] According to the present invention, d -V g PNBT SOI-FETs can be connected in parallel without causing any disturbance in the characteristics. [Brief description of the drawings]

[0019] [Figure 1] 1 is a perspective view showing a configuration of a PNBT SOI-FET used as a unit semiconductor structure of a multi-finger semiconductor structure according to a first embodiment. FIG. [Diagram 2] FIG. 2 is a front view showing the configuration of the PNBT SOI-FET of FIG. [Diagram 3]FIG. 2 is a plan view showing the configuration of the PNBT SOI-FET of FIG. [Figure 4] FIG. 2 is a cross-sectional view showing the structure of the PNBT SOI-FET of FIG. [Diagram 5] 5 is a graph showing characteristics of a drain current versus a first gate voltage of the PNBT SOI-FET of FIGS. 1 to 4. [Figure 6] FIG. 5 is a perspective view showing a configuration of a multi-finger semiconductor structure in which the PNBT SOI-FETs of FIGS. 1 to 4 are used as unit semiconductor structures and are connected in parallel using a normal multi-finger connection. [Figure 7] 7 is a plan view showing the configuration of the multi-finger semiconductor structure of FIG. 6. [Figure 8] 8 is a graph showing characteristics of a drain current versus a first gate voltage in the multi-finger semiconductor structure of FIGS. 6 to 7. [Figure 9] 1 is a perspective view showing a configuration of a multi-finger semiconductor structure according to a first embodiment. [Figure 10] 10 is a plan view showing the configuration of the multi-finger semiconductor structure of FIG. 9. [Figure 11] 11 is a graph showing characteristics of a drain current versus a first gate voltage in the multi-finger semiconductor structure of FIGS. 9 and 10. [Figure 12] FIG. 11 is a perspective view showing the configuration of a PNBT SOI-FET used as a unit semiconductor structure of a multi-finger semiconductor structure according to a second embodiment. [Figure 13] FIG. 13 is a front view showing the configuration of the PNBT SOI-FET of FIG. [Figure 14] FIG. 13 is a plan view showing the configuration of the PNBT SOI-FET of FIG. [Figure 15] FIG. 13 is a cross-sectional view showing the structure of the PNBT SOI-FET of FIG. [Figure 16] FIG. 11 is a perspective view showing the configuration of a PNBT SOI-FET used as a unit semiconductor structure of a multi-finger semiconductor structure according to a third embodiment. [Figure 17] FIG. 13 is a plan view showing a configuration of a multi-finger semiconductor structure according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The present invention will be described below based on preferred embodiments with reference to the drawings. In the embodiments and modified examples, identical or equivalent components and members are given the same reference numerals, and duplicated descriptions are omitted as appropriate. The dimensions of the components in each drawing are enlarged or reduced as appropriate for ease of understanding. Some components that are not important for explaining the embodiments are omitted in each drawing. Terms including ordinal numbers such as first and second are used to describe various components, but these terms are used only for the purpose of distinguishing one component from other components, and the components are not limited by these terms.

[0021] In this specification, with regard to the type of semiconductor impurity, N-type with a high concentration of N-type impurities is represented as "N+", N-type with a low concentration of N-type impurities is represented as "N-", P-type with a high concentration of P-type impurities is represented as "P+", and P-type with a low concentration of P-type impurities is represented as "P-".

[0022] [PNBT SOI-FET] Before describing specific embodiments, the PNBT SOI-FET will be described as basic knowledge with reference to FIGS. 1 to 5. FIG. 1 is a perspective view showing the configuration of the PNBT SOI-FET1. Hereinafter, the x-axis, y-axis, z-axis, and origin shown in FIG. 1 are set for the PNBT SOI-FET1 to define a three-dimensional orthogonal coordinate system. FIG. 2 is a front view showing the configuration of the PNBT SOI-FET1. That is, FIG. 2 is a yz plan view of the PNBT SOI-FET1 at x=0. FIG. 3 is a plan view showing the configuration of the PNBT SOI-FET1. That is, FIG. 3 is an xy plan view of the PNBT SOI-FET1 at z=z3. FIG. 4 is a cross-sectional view of the AA line showing the configuration of the PNBT SOI-FET1. That is, FIG. 4 is a zx plan view of the PNBT SOI-FET1 at y=y4.

[0023] The PNBT SOI-FET 1 includes a substrate 10, a buried oxide film 12, a source 14, a drain 16, a first gate oxide film 18, a first gate 20, a channel 22, a body contact portion 24, and a semiconductor layer 26. The source 14, the drain 16, the first gate 20, and the body contact portion 24 include a source terminal, a drain terminal, a first gate terminal, and a body terminal, respectively (none of which are shown).

[0024] The substrate 10 is, for example, a silicon (Si) substrate, and is formed in the region of 0≦x≦x6, 0≦y≦y3, and 0≦z≦z1. The buried oxide film 12 is, for example, a silicon dioxide (SiO2) film, and is formed in the region of 0≦x≦x6, 0≦y≦y3, and z1≦z≦z2. The source 14 is formed in the region of 0≦x≦x1, y2≦y≦y3, and z2≦z≦z3. The drain 16 is formed in the region of 0≦x≦x1, 0≦y≦y1, and z2≦z≦z3. The source 14 and the drain 16 are N+. The first gate oxide film 18 is, for example, a silicon dioxide (SiO2) film, and is formed in the region of 0≦x≦x1, y1≦y≦y2, and z3≦z≦z4. That is, the thickness of the first gate oxide film 18 is z4-z3. The first gate 20 is, for example, polysilicon, and is formed in the region of 0≦x≦x1, y1≦y≦y2, z4≦z≦z5. In this example, the first gate 20 and the first gate oxide film 18 are extended to the region of x1≦x≦x3, 0≦y≦y3, z3≦z≦z5 for the convenience of manufacturing, etc., and are T-shaped when viewed from above. However, such extension is not essential. The channel 22 is formed between the source 14 and the drain 16, that is, in the region of 0≦x≦x1, y1≦y≦y2, z2≦z≦z3. The channel 22 is further extended to the region of x1≦x≦x2, 0≦y≦y3, z2≦z≦z3, and the region of x2≦x≦x3, y1≦y≦y2, z2≦z≦z3. As a result, the channel 22 is cross-shaped when viewed from above as shown in FIG. 3. In this manner, an N-type SOI (Silicon On Insulator) MOSFET is formed in the region where 0≦x≦x1, 0≦y≦y3, and 0≦z≦z5.

[0025] The body contact portion 24 is formed in the region of x5≦x≦x6, y1≦y≦y2, z2≦z≦z3 to fix the body potential. The body contact portion 24 is P+. The semiconductor layer 26 is formed in the region of x4≦x≦x5, y1≦y≦y2, z2≦z≦z3. That is, the semiconductor layer 26 is formed between the body contact portion 24 and the channel 22. Furthermore, the semiconductor layer 26 is N-. That is, the impurity type (N type) of the semiconductor layer 26 is opposite to the impurity type (P type) of the body contact portion 24. As a result, the semiconductor structure of this comparative example is a structure in which the N type semiconductor layer 26 is added to a conventional body tied structure having a P type body contact portion. As a result, a PNPN junction is formed between the body contact portion 24 and the source 14 and the drain 16.

[0026] FIG. 5 shows the characteristics (I d -V g 5 is a graph showing the body voltage (voltage applied to the body contact portion 24) V b 1 shows the dependency of the drain current on the first gate voltage when Lg (length of the first gate)=y2-y1=1(μm), Wg (width of the first gate)=x1=1(μm), Wb (width of the semiconductor layer 26)=x5-x4=1.2(μm), V d (Drain voltage) = 0.1 (V), V sub (Substrate voltage) = 0 (V). According to Figure 5, V b It can be seen that when the first gate voltage is >0.6(V), the rise in drain current with respect to the first gate voltage becomes very steep. That is, V bWhen the potential is >0.6 (V), the subthreshold coefficient falls below 60 (mV / dec), and the SS subthreshold gradient is realized. One of the reasons for the occurrence of the SS subthreshold gradient is believed to be that the addition of the semiconductor layer 26 to the conventional body-tie structure causes a floating body effect by supplying holes from the body contact portion 24 to the channel 22.

[0027] [PNBT SOI-FET finger connection (comparison example)] FIG. 6 is a perspective view showing a configuration of a multi-finger semiconductor structure 4 in which unit semiconductor structures 1A, 1B, 1C, ... are connected in parallel using a normal multi-finger connection. FIG. 7 is a plan view showing a configuration of the multi-finger semiconductor structure 4. The unit semiconductor structures 1A, 1B, 1C, ... are the PNBT SOI-FETs shown in FIG. 1, respectively. The multi-finger semiconductor structure 4 is a comparative example devised for comparison in the process of devising the embodiment. Although three unit semiconductor structures 1A, 1B, 1C are shown in FIGS. 6 and 7, it should be understood that any number of unit semiconductor structures are actually connected in parallel by multi-finger connection. As shown in the figure, in this multi-finger connection, the body contact portion is separated for each of the body contact portions 24A, 24B, 24C, ... of the unit semiconductor structures 1A, 1B, 1C, ....

[0028] FIG. 8 shows the first gate voltage (V g ) versus drain current (I d ) characteristics (I d -V g As shown in the figure, this I d -V g Although the characteristics show a steep SS subthreshold slope, V g For I d This causes a step-like disturbance in the signal strength, which degrades the performance of the multi-finger semiconductor structure.

[0029] [First embodiment] A multi-finger semiconductor structure 5 according to a first embodiment will be described with reference to Figs. 9 and 10. Descriptions of parts common to the multi-finger semiconductor structure 4 of the comparative example described above will be omitted, and the description will focus on the differences. Fig. 9 is a perspective view showing the configuration of the multi-finger semiconductor structure 5. Fig. 10 is a plan view showing the configuration of the multi-finger semiconductor structure 5.

[0030] The multi-finger semiconductor structure 5 is a multi-finger semiconductor structure in which a plurality of unit semiconductor structures 1A, 1B, 1C, ... are connected in parallel by multi-finger connection, each unit semiconductor structure having a semiconductor layer 26 of an impurity type opposite to that of the body contact portion 24 between the body contact portion 24 and the source and drain, and the body contact portion 24 and the semiconductor layer 26 are integrated. That is, the multi-finger semiconductor structure 5 is formed by connecting the unit semiconductor structures 1A, 1B, 1C, ... in parallel using multi-finger connection, but has a feature that the body contact portion 24 and the semiconductor layer 26 are integrated, which is not found in a normal multi-finger connection. In this embodiment, not only the body contact portion 24 but also the first gate 20 are integrated. Each of the unit semiconductor structures 1A, 1B, 1C, ... is formed by the PNBT SOI-FET 1 shown in Figs. 1 to 4.

[0031] FIG. 11 shows the first gate voltage (V g ) versus drain current (I d ) characteristics (I d -V g As shown in the figure, this I d -V g In terms of characteristics, no step-like disturbances are observed, and a steep SS subthreshold gradient with a large ON / OFF ratio is realized. d -V g Since there is no step-like disturbance in the characteristics, there is no degradation in performance.

[0032] According to this embodiment, I d -V g PNBT SOI-FETs can be connected in parallel without causing any disturbance in the characteristics.

[0033] [Second embodiment] A multi-finger semiconductor structure according to a second embodiment will be described with reference to Figures 12 to 15. In this embodiment, the method of finger connection is the same as in the first embodiment, but the configuration of the unit semiconductor structure is different.

[0034] FIG. 12 is a perspective view showing the configuration of a PNBT SOI-FET2 used as a unit semiconductor structure of a multi-finger semiconductor structure according to the second embodiment. FIG. 13 is a front view showing the configuration of the PNBT SOI-FET2. That is, FIG. 13 is a yz plan view of the PNBT SOI-FET2 at x=0. FIG. 14 is a plan view showing the configuration of the PNBT SOI-FET2. That is, FIG. 14 is an xy plan view of the PNBT SOI-FET2 at z=z3. FIG. 15 is a BB line cross-sectional view showing the configuration of the PNBT SOI-FET2. That is, FIG. 15 is a zx plan view of the PNBT SOI-FET2 at y=y4.

[0035] The PNBT SOI-FET2 includes a substrate 10, a buried oxide film 12, a source 14, a drain 16, a first gate oxide film 18, a first gate 20, a channel 22, a body contact portion 24, a semiconductor layer 26, a second gate oxide film 28, and a second gate 30. That is, the PNBT SOI-FET2 includes the second gate oxide film 28 and the second gate 30 in addition to the configuration of the PNBT SOI-FET1. The second gate 30 includes a second gate terminal (not shown). The other configuration of the PNBT SOI-FET2 is the same as that of the PNBT SOI-FET1.

[0036] The second gate oxide film 28 is, for example, a silicon dioxide (SiO2) film, and is formed in the region of x4≦x≦x5, y1≦y≦y2, and z3≦z≦z4. That is, the second gate oxide film 28 is formed on the semiconductor layer 26, and its thickness is z4-z3. The second gate 30 is, for example, polysilicon, and is formed in the region of x4≦x≦x5, 0≦y≦y3, and z4≦z≦z5. That is, the second gate 30 is formed on the semiconductor layer 26 adjacent to the first gate 20. The second gate 30 is insulated from the semiconductor layer 26 by the second gate oxide film 28. The second gate 30 is insulated from the first gate 20 by the buried oxide film 12. The distance between the first gate 20 and the second gate 30 (i.e., the thickness of the buried oxide film 12 in this region) is x3-x2.

[0037] By configuring the second gate 30 as described above, when the PNBT SOI-FET2 is viewed in the x-direction, it can be seen that a P-type SOIMOSFET is formed in which the body contact portion 24 (P+) serves as the source region, the channel 22 (P-) serves as the drain region, and the second gate 30 serves as the gate region.

[0038] It is expected that by controlling the second gate voltage applied to the second gate 30 of the PNBT SOI-FET 2, it is possible to realize a SS subthreshold slope at an operating voltage of 0.1 (V) or less. b This has a significant advantage over the PNBT SOI-FET1, which can achieve a SS subthreshold slope only when >0.6 (V). Specifically, the PNBT SOI-FET2 can switch with lower power consumption than the PNBT SOI-FET1.

[0039] According to this embodiment, since the SS subthreshold slope can be obtained at a low body voltage, a semiconductor device capable of switching with low power consumption can be realized.

[0040] It is desirable that the distance between the first gate 20 and the second gate 30 be shorter than a predetermined length. Simulations have shown that the switching performance is significantly improved, particularly when the distance between the first gate 20 and the second gate 30 is 50 nm or less.

[0041] [Third embodiment] 16 is a perspective view showing the structure of a PNBT SOI-FET3 used as a unit semiconductor structure of a multi-finger semiconductor structure according to the third embodiment. The PNBT SOI-FET3 includes a substrate 10, a buried oxide film 12, a source 140, a drain 160, a first gate oxide film 18, a first gate 200, a channel 220, a body contact portion 240, a semiconductor layer 260, a second gate oxide film 280, and a second gate 300. The PNBT SOI-FET3 has a structure similar to that of the PNBT SOI-FET2, but differs from the PNBT SOI-FET2 in that the type of impurities in each component is opposite to that of the PNBT SOI-FET2. That is, with respect to each component of the PNBT SOI-FET3, the source 140 corresponds to the source 14 of the PNBT SOI-FET2, the drain 160 corresponds to the drain 16 of the PNBT SOI-FET2, the first gate 200 corresponds to the first gate 20 of the PNBT SOI-FET2, the channel 220 corresponds to the channel 22 of the PNBT SOI-FET2, the body contact portion 240 corresponds to the body contact portion 24 of the PNBT SOI-FET2, the semiconductor layer 260 corresponds to the semiconductor layer 26 of the PNBT SOI-FET2, and the second gate 300 corresponds to the second gate 30 of the PNBT SOI-FET2. The source 140 and the drain 160 are P+. The body contact portion 240 is N+. The semiconductor layer 260 is P-. That is, in the PNBT SOI-FET3, a P-type SOIMOSFET is formed by the substrate 10, the buried oxide film 12, the source 140, the drain 160, the first gate oxide film 18, the first gate 200, and the channel 220. The voltage applied to each terminal of the PNBT SOI-FET3 is opposite in polarity to the voltage applied to each terminal of the PNBT SOI-FET2. The position and dimensions of each component of the PNBT SOI-FET3 are similar to the corresponding components of the PNBT SOI-FET2.

[0042] The PNBT SOI-FET 3 also provides an SS subthreshold slope at a low body voltage, similar to the PNBT SOI-FET 2. Therefore, according to this embodiment, a semiconductor device capable of switching with low power consumption can be realized.

[0043] The above-described embodiment is based on a Si-based SOIMOSFET, but the present invention is not limited to this and can be realized with other semiconductor materials such as germanium (Ge) and silicon germanium (SiGe).

[0044] [Fourth embodiment] 17 is a plan view showing a configuration of a multi-finger semiconductor structure 6 according to a fourth embodiment. The multi-finger semiconductor structure 6 includes a MOSFET including a source, a drain, first gates 20A, 20B, 20C, ..., and a body contact portion 24, and is a multi-finger semiconductor structure in which a plurality of unit semiconductor structures 2A, 2B, 2C, ..., each including a semiconductor layer 26 of an impurity type opposite to that of the body contact portion 24, are connected in parallel in a multi-finger manner between the body contact portion 24 and the source and drain, and the body contact portion 24 and the semiconductor layer 26 are integrated. The first gates 20A, 20B, 20C, ... of the unit semiconductor structures 2A, 2B, 2C, ... are separated for each unit semiconductor structure. That is, the multi-finger semiconductor structure 5 is formed by connecting unit semiconductor structures 2A, 2B, 2C, ... in parallel using a multi-finger connection, but differs from the multi-finger semiconductor structure 5 in Fig. 1 in that the first gates 20A, 20B, 20C, ... of the unit semiconductor structures 2A, 2B, 2C, ... are not integrated but are separated for each unit semiconductor structure. Each of the unit semiconductor structures 2A, 2B, 2C, ... is formed by the PNBT SOI-FET 1 shown in Figs. 1 to 4.

[0045] According to this embodiment, the body contact portion and the semiconductor layer are integrated to form an I d -V gBy isolating the first gate for each semiconductor structure, the volume of the first gate can be reduced while preventing the occurrence of disturbance in characteristics.

[0046] Although the present invention has been described above with reference to the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and suitable combinations or substitutions of the configurations of the embodiments are also included in the present invention. In addition, it is possible to suitably rearrange the combinations and order of steps in each embodiment based on the knowledge of a person skilled in the art, and to make modifications such as various design changes to each embodiment, and such modified embodiments are also included in the scope of the present invention.

[0047] In the embodiment, a basic structure of a MOSFET capable of switching with low power consumption has been exemplified. However, the present invention is not limited to this, and for example, the first and second embodiments may be combined to configure a CMOS (Complementary MOS) or a transmission gate.

[0048] These modifications provide the same functions and effects as the embodiment.

[0049] Any combination of the above-described embodiments and modifications is also useful as an embodiment of the present invention. A new embodiment resulting from the combination has the combined effects of each of the combined embodiments and modifications. [Explanation of symbols]

[0050] 1. PNBT SOI-FET, 1A··Unit semiconductor structure, 1B: Unit semiconductor structure; 1C··Unit semiconductor structure, 2. PNBT SOI-FET, 2A··Unit semiconductor structure, 2B: Unit semiconductor structure; 2C··Unit semiconductor structure, 3. PNBT SOI-FET, 4. Multi-finger semiconductor structure, 5. Multi-finger semiconductor structure, 6. Multi-finger semiconductor structure, 10... Substrate, 12. Buried oxide film, 14. Source, 16··Drain, 18 - First gate oxide film, 20. First Gate, 20A··First gate, 20B: First Gate, 20C··First Gate, 22 channels, 24 Body contact part, 24A··Body contact part, 24B Body contact part, 24C··Body contact part, 26 Semiconductor layer, 26A Semiconductor layer, 26B Semiconductor layer, 26C Semiconductor layer, 28...Second gate oxide film, 30. Second Gate, 140··Source, 160··Drain, 200··First Gate, 220 channels, 240··Body contact part, 260 Semiconductor layer, 280··Second gate oxide film, 300··Gate 2.

Claims

1. A multi-finger semiconductor structure includes a MOSFET including a source, a drain, a first gate, and a body contact portion, and a plurality of unit semiconductor structures including a semiconductor layer of an impurity type opposite to that of the body contact portion are connected in parallel in a multi-finger manner between the body contact portion and the source and the drain, A multi-finger semiconductor structure, wherein the body contact portion and the semiconductor layer are integrated.

2. 2. The multi-finger semiconductor structure of claim 1, wherein each of the unit semiconductor structures comprises a second gate adjacent to the first gate on the semiconductor layer.

3. The multi-finger semiconductor structure according to claim 2 , wherein the distance between the first gate and the second gate is 50 nm or less.

4. 4. The multi-finger semiconductor structure according to claim 1, wherein the impurity types of the source and the drain are N-type, the impurity type of the body contact portion is P-type, and the impurity type of the semiconductor layer is N-type.

5. 4. The multi-finger semiconductor structure according to claim 1, wherein the impurity types of the source and the drain are P-type, the impurity type of the body contact portion is N-type, and the impurity type of the semiconductor layer is P-type.

6. 6. The multi-finger semiconductor structure according to claim 1, wherein the MOSFET is a SOI MOSFET.

7. 7. The multi-finger semiconductor structure according to claim 1, wherein the first gate of each of the unit semiconductor structures is separated for each of the unit semiconductor structures.

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