Ising Machine Based on Coupled Bistable Nodes for Solving Combinatorial Problems

Abstract

An Ising machine having a network of resistively coupled circuit nodes, at least one of which includes a capacitor having a voltage across its terminals representing a state variable of the node, the voltage being resistively coupled to at least one other node of the network, and a two-terminal active electronic device connected in parallel with the capacitor that supplies energy to the node, the device having an odd-symmetric current-voltage characteristic that exhibits a negative current slope for the voltage across its terminals whose magnitude is less than a predetermined threshold, and a positive slope otherwise, and zero current for three voltage instances (0 volts, +V1 volts, and −V1 volts), where V1 is a constant greater than a predetermined threshold.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit under 35 U.S.C. §119(e) of the following U.S. provisional patent applications, which are incorporated herein by reference:

[0002] U.S. Provisional Patent Application No. 63 / 011,245, filed April 16, 2020, by Ignjatovic et al. (Attorney Docket No. URNVP001.P1), and entitled “ISING MACHINE BASED ON COUPLED BISTABLE NODES FOR SOLVING COMBINATORIAL PROBLEMS.” [Background technology]

[0003] 1.Technical Field The present invention relates to Ising machines, and in particular to Ising machines implemented in a network of resistively coupled circuit nodes, where the nodes have capacitors connected in parallel with active electronic elements.

[0004] 2. Description of Related Technology Computing capabilities have improved by orders of magnitude over the past several decades. Over the same period, the need for computation has been driven by improvements, and better mechanisms are continually required to solve a variety of modern problems. For a long time, the industry has focused on improving general-purpose computing systems. In recent years, specialized designs have increasingly been employed to excel at certain types of tasks, such as encryption and network operation.

[0005] Recently, machine learning tasks have become a new focus, and many specialized architectures have been proposed to speed up these operations. Much of this work has been directed towards building more efficient architectures that require much less control overhead and operational costs than traditional designs.

[0006] In a related but different work track, researchers are trying to map entire algorithms onto physical processes so that the resulting states represent answers to the mapped algorithm. The quantum computers sold by D-Wave Systems are a notable example. Unlike circuit-model quantum computers, the D-Wave machines perform quantum annealing. (Bunyk et al., “Architectural considerations in the design of a superconducting quantum annealing processor,” IEEE Transactions on Applied Superconductivity, 24(4):1-10, 2014, which is incorporated herein by reference.) The idea is to map a combinatorial optimization problem onto a system of qubits such that the energy of the system maps onto a metric of minimization. Then, once the system naturally settles into a ground state, one can read out the state of the qubits, which represents a solution to the mapped problem.

[0007] It is not yet conclusive whether D-Wave's system can reach any kind of quantum speedup. However, one thing is clear: such a machine can indeed find some good solutions to optimization problems very quickly. In fact, many alternative designs have recently emerged, all of which have shown high-quality solutions for nontrivial sizes with millisecond or microsecond latency (sometimes finding results that outperform the best known answers from all previous attempts). (Inagaki et al. “A coherent ising machine for 2000-node optimization problems,” Science, 354(6312):603-606, 2016; Wang et al., “Oim: Oscillator-based ising machines for solving combinatorial optimisation problems,” In International Conference on Unconventional Computation and Natural Computation, pages 232-256, June 2019; and Roques-Carmes et al., “Heuristic recurrent algorithms for photonic ising machines,” Nature Communications, 11(1):249, 2020.) All of these prior art systems share the property that a problem can be mapped onto a machine setup, and then the state of the machine evolves according to the physics of the system. This evolution has the effect of optimizing a certain equation called the Ising model. Reading out the state of such a system at the end of the evolution therefore has the effect of obtaining a solution (usually a very good solution) of the mapped problem.

[0008] For example, in some systems, the Hamiltonian is closely related to the Ising formula. Naturally, the system will try to enter a low-energy state. In other systems, it can be shown that the Lyapunov function of the system is related to the Ising formula. In general, these systems can be thought of as optimizing a physics-based objective function (in the form of the Ising formula). They are therefore generally referred to as Ising machines. Obviously, unlike von Neumann machines, there is no explicit algorithm to follow. Instead, they perform the computation naturally and effectively. Ising machines are implemented in different ways that involve very different (and often complex) physical principles. It may not be clear that some Ising machine forms have fundamental advantages that manifest themselves at very large scales.

[0009] Although there is no guarantee that an Ising machine system will actually achieve the ground state, there may be theoretical guarantees for ideal setups that are generally unattainable. For example, adiabatic quantum computing theory shows that when the annealing schedule is slow enough and there is no noise (i.e., at zero Kelvin), the system is guaranteed to remain in the ground state. Thus, there is no guarantee that the corresponding answer is the best of all possible cases. Nevertheless, the speed and energy efficiency with which an Ising machine system finds a suitable answer is very attractive.

[0010] Because this area of ​​research is still relatively new and new methods are constantly being developed, there is a clear need for a CMOS-based Ising machine design that is more suitable for on-chip integration than other designs. Additionally, there is a need for an Ising machine design that is faster, more energy efficient, and equally reliable in producing high-quality results compared to conventional designs. These and other needs are met by the present invention, which is described in detail below. Summary of the Invention

[0011] Ising machines use physics to naturally drive dynamical systems to optimal states that can be read as heuristic solutions to combinatorial optimization problems. Such designs that use nature as a computing mechanism can result in higher performance and / or lower operational costs. Quantum annealers are a notable existing example of such machines. However, existing Ising machines are typically large, cumbersome, and energy intensive. Such drawbacks may provide substantial advantages at larger scales in the future. However, for now, integrated circuit designs allow for more immediate application. An embodiment of the present invention is directed to a design that uses bistable nodes coupled with programmable variable strength. The design is fully CMOS compatible for on-chip applications and exhibits competitive metrics in performance, area, and energy.

[0012] An exemplary embodiment of the present invention may include a network of resistively coupled circuit nodes having at least one node including a capacitor, where the voltage across the capacitor represents a state variable of the node, and the voltage is resistively coupled to at least one other node of the network, and an active electronic element having two terminals connected in parallel with the capacitor to supply energy to the node, the active electronic element having an odd symmetric current-voltage characteristic exhibiting a negative current slope of the voltage between the two terminals whose magnitude is less than a predefined threshold, a positive slope otherwise, and zero current for three voltage instances (0 volts, +V1 volts, and -V1 volts), where V1 is a constant greater than a predefined threshold. Further embodiments may include a programmable resistor connected in parallel with the active electronic element to adjust the odd symmetric current-voltage characteristic and the negative and positive current slopes at V1. Further embodiments may include a bipolar junction transistor connected in parallel with the active electronic device to adjust the odd symmetric current-voltage characteristic and the negative and positive current slopes at V1 by varying the base current of the bipolar junction transistor. Further embodiments may include a field effect transistor connected in parallel with the active electronic device to adjust the odd symmetric current-voltage characteristic and the negative and positive current slopes at V1 by varying the gate voltage of the field effect transistor.

[0013] Another embodiment of the present invention may include a network of coupled circuit nodes having at least one node, the at least one node including a capacitor, where the voltage across the capacitor represents a state variable of the node and the voltage is converted to a current before being coupled to at least one other node of the network, and an active electronic element having two terminals connected in parallel with the capacitor that supplies energy to the node, the element having an odd symmetric current-voltage characteristic exhibiting a negative current slope for voltages between the two terminals whose magnitude is less than a predefined threshold, a positive slope otherwise, and zero current for three voltage instances (zero volts, +V1 volts, and -V1 volts), where V1 is a constant greater than a predefined threshold. This embodiment of the present invention may be further modified to conform with any other network, device, or method described herein.

[0014] An exemplary method for solving a maximum cut problem on a graph may include mapping vertices of the graph to nodes of a network of resistively coupled circuit nodes and mapping edge weights of the graph to coupling resistances of the network, the network including at least one node including a capacitor, where a voltage across the capacitor represents a state variable of the node, the voltage being resistively coupled to at least one other node of the network, and an active electronic element having two terminals connected in parallel with the capacitor that supplies energy to the node, the active electronic element having an odd symmetric current-voltage characteristic exhibiting a negative current slope for voltages across its terminals whose magnitude is less than a predetermined threshold, a positive slope otherwise, and zero current for three voltage instances (zero volts, +V1 volts, and -V1 volts), where V1 is a constant greater than a predetermined threshold. The method may further include: a coupling resistance between any two nodes of the network corresponding to two vertices on the graph is inversely proportional to the weight of the edge between the two vertices; any two nodes of the network corresponding to positively connected vertices on the graph (i.e., positive edge weights) are cross-coupled to the terminals of the capacitors of the two corresponding nodes of opposite polarity via coupling resistor(s); and any two nodes of the network corresponding to negatively connected vertices on the graph (i.e., negative edge weights) are parallel-coupled to the terminals of the capacitors of the two corresponding nodes of the same polarity via coupling resistor(s). This embodiment of the invention may be further modified to conform with any other network, device, or method described herein.

[0015] Another exemplary method for solving a maximum cut problem on a graph includes mapping vertices of the graph to nodes of a network of coupled circuit nodes and mapping edge weights of the graph to coupled currents of the network, the network having at least one node including a capacitor, where a voltage across the capacitor represents a state variable of the node and the voltage is converted to a current before being coupled to at least one other node of the network, and an active electronic element having two terminals connected in parallel with the capacitor that supplies energy to the node, the element having an odd symmetric current-voltage characteristic exhibiting a negative current slope for voltages across its terminals whose magnitude is less than a predetermined threshold, a positive slope otherwise, and zero current for three voltage instances (zero volts, +V1 volts, and -V1 volts), where V1 is a constant greater than a predetermined threshold. The coupling current between any two nodes of the network corresponding to two vertices on the graph is proportional to the weight of the edge between the two vertices, any two nodes of the network corresponding to positively connected vertices on the graph (i.e., positive edge weights) are cross-coupled such that the coupling current charges the capacitors of the two corresponding nodes with opposite polarity, and any two nodes of the network corresponding to negatively connected vertices on the graph (i.e., negative edge weights) are parallel-coupled such that the coupling current charges the capacitors of the two corresponding nodes with the same polarity. This embodiment of the invention can be further modified to conform to any other network, device, or method described herein.

[0016] Another exemplary embodiment of the invention may include a device for solving a maximum cut problem in a graph, the vertices of the graph corresponding to nodes of a network of resistively coupled circuit nodes, the weights of the edges of the graph corresponding to the coupling resistances of the network, the network including at least one node, the at least one node including a capacitor, the voltage across the capacitor representing a state variable of the node, the voltage being resistively coupled to at least one other node of the network, and an active electronic element having two terminals connected in parallel with the capacitor that supplies energy to the node, the element having an odd symmetric current-voltage characteristic, the odd symmetric current-voltage characteristic having a negative current slope for a voltage across its terminals that is less than a predetermined threshold in magnitude and a positive slope otherwise, and three voltage inversions. and zero current for any of the three voltages (zero volts, +V1 volts, and -V1 volts), where V1 is a constant greater than a predefined threshold, the coupling resistance between any two nodes of the network corresponding to two vertices on the graph is inversely proportional to the weight of the edge between the two vertices, any two nodes of the network corresponding to positively connected vertices on the graph (i.e., positive edge weights) are cross-coupled to the terminals of the capacitors of the two corresponding nodes of opposite polarity via coupling resistor(s), and any two nodes of the network corresponding to negatively connected vertices on the graph (i.e., negative edge weights) are parallel-coupled to the terminals of the capacitors of the two corresponding nodes of the same polarity via coupling resistor(s). This embodiment of the present invention may be further modified to conform with any other network, device, or method described herein.

[0017] Yet another exemplary embodiment of the present invention may include a device for solving a maximum cut problem in a graph, the vertices of the graph corresponding to nodes of a network of coupled circuit nodes and the weights of the edges of the graph corresponding to coupled currents in the network, the network including at least one node, the at least one node including a capacitor, a voltage across the capacitor representing a state variable of the node, the voltage being converted to a current before being coupled to at least one other node of the network, and a two-terminal active electronic device connected in parallel with the capacitor that supplies energy to the node, the device having an odd symmetric current-voltage characteristic, the odd symmetric current-voltage characteristic being a negative current slope for a voltage between the two terminals that is less than a predetermined threshold in magnitude, and a negative current slope for a voltage between the two terminals that is less than a predetermined threshold in magnitude otherwise. indicates a positive slope and zero current for three voltage instances (zero volts, +V1 volts, and -V1 volts), where V1 is a constant greater than a predefined threshold, the combined current between any two nodes of the network corresponding to two vertices on the graph is proportional to the weight of the edge between the two vertices, any two nodes of the network corresponding to positively connected vertices on the graph (i.e., positive edge weights) are cross-coupled such that the combined current charges the capacitors of the two corresponding nodes with opposite polarity, and any two nodes of the network corresponding to negatively connected vertices on the graph (i.e., negative edge weights) are parallel-coupled such that the combined current charges the capacitors of the two corresponding nodes with the same polarity. This embodiment of the present invention may be further modified to conform with any other network, device, or method described herein.

[0018] Reference is now made to the drawings in which like reference numbers represent corresponding parts throughout. [Brief description of the drawings]

[0019] [Figure 1] 1 illustrates an exemplary bistable resistively coupled Ising machine (BRIM) architecture. [Diagram 2] An exemplary Ni-balanced BRIM node is shown showing the connections between the Ni node and two other nodes (Nj and Nk). [Diagram 3] An example of a balanced ZIV diode implemented as a discrete component with the polarity of the diode terminals chosen arbitrarily is shown. [Figure 4] 4 shows exemplary IV curves of a balanced ZIV diode loaded with various load resistances RL, the curves being taken from the ZIV diode of FIG. [Diagram 5] 1 illustrates an exemplary 6-node discrete BRIM implementation using LF412 opamps. [Figure 6] 6 illustrates an example voltage waveform at the output of a node in the discrete BRIM of FIG. 5. [Figure 7] FIG. 2 shows a block diagram illustrating components of an exemplary BRIM with nodes Ni and coupling units CUij. [Figure 8] 1 illustrates a balanced structure of an exemplary integrated circuit BRIM node considering the application of both negative and positive coupling coefficients to the circuit. [Figure 9] 1 shows an example of a circuit diagram of a coupling unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] 1. Ising model The Ising model is used to describe the Hamiltonian of a system of spins (the total energy of a given system, such as the kinetic potential). Although it is commonly called the Ising model, the model itself existed before Ernst Ising solved one-dimensional systems analytically. The model is a general model for representing systems with many nodes (e.g. atoms), where each node has only two values, σ i The energy of the system is determined by the pairwise coupling of the spins (J ij ) and some external field interaction with each spin (h i ) The resulting Hamiltonian is

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[0021] Physical systems with such Hamiltonians naturally tend to low-energy states, and therefore serve as convenient machines for solving problems with formulations equivalent to the Ising Hamiltonian. ij ) can be configured to match the parameters of the problem.

[0022] 2. Optimization Problem A group of optimization problems naturally maps onto Ising machines. Perhaps the easiest problem to map is the max-cut. Given a graph G = (V,E), a cut divides the vertices into two sets, say V1 and V -1

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[0023] It is easy to see the similarity between equation (2) and equation (3). In fact, the weights of the connections (J ij ) is the negative edge weight (-W ij), then the Ising Hamiltonian is simply the negative cut value plus a constant:

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[0024] Finally, note that we only focus on max-cut problems when evaluating our Ising machine designs. This is because max-cut is NP-complete, so all other NP-complete problems can be transformed as max-cut problems with polynomial complexity. (See Karp, “Reducibility among Combinatorial Problems,” pages 85-103, Springer US, Boston, MA, 1972, which is incorporated herein by reference.) This means that other NP-complete problems can be solved with additional pre- and post-processing time, or additional nodes for mapping. Both time and space overhead are bounded by the polynomial complexity.

[0025] 3. Quantum mechanics and optical Ising machines There are many systems in nature that can be represented by the Ising model. For example, consider two existing systems with relatively large footprints: D-Wave's machine is a different style of quantum computer. Recent theoretical work claims equivalence between quantum annealers and more traditional circuit models of quantum computing. (See Yu, et al., “Exact equivalence between quantum adiabatic algorithm and quantum circuit algorithm,” Chinese Physics Letters, 35(11):110303, Oct 2018, and Dam et al., “How powerful is adiabatic quantum computation?,” Proceedings 2001 IEEE International Conference on Cluster Computing, pages 279-287, 2001, which are incorporated herein by reference.) In the machine, D-Wave uses superconducting qubits as the basic building blocks. These bits are then coupled together with couplers that form a connection topology known as a Chimera graph. This is an important architectural constraint that limits the type of problems that can be mapped to the machine. In practice, an abstract problem is ensured to be mappable to the machine by a transformation (called minor embedding). This process involves mapping logical nodes onto multiple physical nodes where the physical nodes themselves are strongly coupled together. Thus, in the solutions found, most of the time the nodes are spun in the same direction that can be considered as one logical node. This shows that it limits the number of valid nodes (spins) that the machine can provide. Considering the extreme example of a fully connected graph, the number of nodes required in the minor embedded version grows quadratically with the number of logical nodes. Another drawback of the system is the cryogenic operating conditions (15mK) required for the quantum annealer. This requirement consumes a significant amount of the machine's 25KW power.

[0026] The coherent Ising machine (CIM) is another modern example of an Ising sampling machine. (See Inagaki et al., “A coherent Ising machine for 2000-node optimization problems,” Science, 354, 10 2016, which is incorporated herein by reference.) In the CIM, an optical device called an OPO (optical parametric oscillator) is used to generate and manipulate signals to represent one spin. Unlike the D-Wave machine, the coupling between spins is relatively simple in principle. As a result, CIM implementations have always supported all-to-all coupling. It should therefore be emphasized that the 2000-node CIM is much more capable than the D-Wave 2000Q, which can only map a problem size of 64 (or 61 after subtracting the defective nodes). (See Hamerly et al., “Experimental investigation of performance differences between coherent Ising machines and a quantum annealer,” In Science advances, 2019, which is incorporated herein by reference.) In practice, the difference in capabilities is less extreme, since not all problems of practical interest are on the complete graph. CIM is not without its drawbacks: many kilometers of fiber are needed to support 2000 spins. Thus, the temperature stability of the system is a serious engineering challenge. Attempts to scale beyond the currently achieved size (about 2000) have not been successful, as the system faces stability problems. It is also worth noting that the coupling between nodes, at least in its current form, is implemented by computation outside the optical cavity. The amplitude and phase of every pulse are detected and their interactions with every other pulse are calculated in an auxiliary computer (FPGA), which is then used to modulate the new pulses that are injected into the cavity. Strictly speaking, the current implementation is a natural simulation hybrid Ising machine.Thus, beyond the challenge of constructing a cavity, CIMs also require significant supporting structures that involve high-speed conversion between optical and electrical signals, as well as fairly intensive computational demands (e.g., hundreds of GFLOPS).

[0027] These room-sized Ising machines could certainly be valuable creations for science. In particular, both models have a theoretical basis for reaching a ground-state solution (i.e., an optimal solution). However, as we will show below, practical designs do not guarantee that the ground state will be reached. As practical computing platforms, both models have considerable room for improvement.

[0028] 4. Electronic Oscillator-Based Ising Machine A network of coupled oscillators is another physical implementation of an Ising machine. As an example, consider a network of coupled oscillators. After a sufficient amount of time, the oscillators will synchronize to form a stable relative phase relationship. (Observations of such synchronization date back to at least the 17th century, when Huygens observed the synchronization of two pendulums; see Rosenblum et al., “Phase synchronization of chaotic oscillators,” Physical review letters, 76(11):1804, March 1996, which is incorporated herein by reference. The phenomenon of synchronization is a topic of research addressed in a variety of fields. The large-scale synchronization of firefly lights and rhythmic applause in a large audience are just two examples of this general fundamental principle in non-mechanical objects.) Many factors (e.g., amplitude, stochastic noise) can affect the phase of each oscillator, but a simplified description of the phase relationship in the steady state is given by

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[0029] This means that the system will generally evolve along a trajectory that minimizes the Lyapunov function. In other words, a network of coupled oscillators will ij ), the steady state of the system represents a good solution that minimizes equation (6) on the right-hand side.

[0030] A detailed examination confirms the similarity of equation (6) and the Ising model (equation (2)). Specifically, for all phases (φ i ) are all 0 or π, the two equations are the same. In fact, the formulation of equation (6) allows the phase (φ i ) in the classical XY spin model. The Ising model is therefore a special case of the XY model. In other words, a system of coupled oscillators forms an "XY machine" (not an Ising machine). The XY state can be transformed into an Ising state (φ i =0,π). For the purposes of this disclosure, we can consider direct quantization, which rounds the phase to the nearest multiple of π.

[0031] Recently, many oscillator-based Ising machines have been proposed. (See Wang et al., “OIM: oscillator-based Ising machines for solving combinatorial optimisation problems,” CoRR, abs / 1903.07163, 2019, which is incorporated herein by reference.) However, all of these examples use LC tank oscillators. While this is a common practice for analog circuit designers and relatively easy to prototype with discrete elements, the use of LC tanks poses significant practical challenges for integrated circuit (IC) design. The lack of high-quality inductors and the typically high area cost of incorporating them are common challenges for RF integrated circuits. These desktop Ising machines are significantly smaller than other room-sized Ising machines. However, for full-scale widespread applications, designing a clean-state IC-specific Ising machine is a worthwhile pursuit. There may be a great deal of interaction between the different approaches, and future practice may very well lead to a confluence of the three (or more) styles of Ising machines.

[0032] 5.Mock sampling machine Although Ising machines using physical substrates are obviously faster and more efficient, Ising machines can be emulated with conventional machines. Indeed, the classical technique simulated annealing is a good example. (See Kirkpatrick et al., “Optimization by simulated annealing,” Science, 220(4598):671-680, 1983, which is incorporated herein by reference.) The principles behind simulated annealing have been widely adopted in a variety of algorithms, from Hopfield networks to Boltzmann machines. One of the most relevant examples is in particular modern CMOS designs, which use conventional memory and relatively simple logic to speed up simulated sampling. (See Yamaoka et al., “24.3 20k-spin ising chip for combinatorial optimization problem with cmos annealing,” 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers, pages 1-3, February 2015, and Takemoto et al., “2.6 a 230k-spin multichip scalable annealing processor based on a processing-in-memory approach for solving large-scale combinatorial optimization problems,” IEEE International Solid-State Circuits Conference, February 2019, which are incorporated by reference herein.) In these machines, there is no physical mechanism that naturally drives the system state to some energy ground state; instead, energy differences are calculated and state transitions are determined probabilistically.Note that our design does not follow a typical annealing approach, but uses a unique heuristic (which can be thought of as a simplified Metropolis heuristic): we accept new states when their energy is low and apply random changes according to a linear annealing schedule.

[0033] 6.CMOS IC Ising Machine In this section, an overview of an embodiment of the present invention is provided and then proceeds to describe a chip-scale design using a small discrete component implementation as an example of a functioning system.

[0034] As mentioned above, existing Ising machine designs have different advantages and disadvantages. Room-sized machines are an excellent means for the ongoing scientific exploration of fundamental principles. However, at present, the machines have no obvious advantages for immediate applications. Electronic oscillator-based Ising machines have already demonstrated good problem-solving capabilities, but IC implementation poses real technical challenges. For example, machines that require LC tanks at each node for operation may not be suitable for integration into advanced CMOS technologies due to challenges associated with inductor scaling. While it is theoretically possible to scale on-chip inductors to smaller sizes, this comes at the cost of requiring higher resonant frequencies (e.g., in the GHz range). Large-scale Ising machines necessarily contain many nodes distributed over long distances with the attendant parasitic elements of interconnect lines. Proper coupling at such high operating frequencies while maintaining phase coherence is a very challenging engineering challenge, if possible at all. Furthermore, purely resistive coupling of oscillators at GHz operating frequencies can be difficult to achieve. It is therefore desirable to explore IC-specific designs with good performance characteristics and ease of CMOS integration.

[0035] There are possibly many different approaches to designing an Ising machine. The embodiments of the present invention can be explained starting from a simple intuitive basis. In the Ising model, when two nodes (e.g., i and j) are strongly and positively connected (i.e., J ij is large and positive), their spins are likely to be parallel (σ i = σ j ). Thus, the term J ij σ i σ j Conversely, strong negative bonds (J ij is large and negative) has antiparallel spin (σ i =-σ j Finally, the weak bond (J ij ) suggests that the two spins are likely to be independent.

[0036] This behavior can be easily mimicked with resistive coupling capacitors. Consider representing the nodes with capacitors in a differential manner where the polarity of the voltage represents the spin of the node. Then the nodes can be connected differently with conductance / resistance. Stronger coupling means that the voltages of the two nodes can be more easily balanced due to higher conductance values ​​(i.e. lower resistance values). The sign of the coupling can also be achieved by connecting either the same or opposite polarities in a differential circuit. When initialized with random voltages, these coupling capacitors may actually try to achieve some temporary equilibrium. It is temporary because the energy stored in the capacitors will eventually dissipate through the coupling resistance and all the nodes will decay to a value of 0 instead of staying at the desired ±1. To induce the nodes to stay at ±1, a local feedback unit can be introduced to make the node voltages bistable. Such a bistable resistive coupled Ising machine can be called a BRIM.

[0037] To show that this is a viable approach, we now describe a concrete example using discrete components, and then we can explore the principles behind the operation and the properties of some of the circuit elements required for the machine to function predictably. A detailed architecture and circuit design of a complete Ising machine for an integrated circuit is described below.

[0038] 7. Example of Ising machine design using discrete electronics An exemplary implementation of BRIM in discrete electronics involving operational amplifiers is described herein using passive components such as capacitors and resistors. An example of BRIM for an Ising machine can employ a design using nodes with a single state variable (e.g., the voltage of a capacitor) whose trajectory follows a first-order ordinary differential equation. To derive a suitable first-order phase space model, a Lyapunov function of the form shown in equation (7) can be used, where:

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[0039] A sufficient condition for monotonic convergence of the Lyapunov function of equation (7) to the minimum stable point (i.e.,

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[0040] The Lyapunov function in equation (7) is a continuous function in N-dimensional space, and its global minimum is the Ising Hamiltonian in the discrete N-dimensional space.

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[0041] Figure 1 shows an overview of the topology of a discrete BRIM. At the heart of our discrete implementation system is an array of bistable nodes (e.g., N i , i = 1, 2, ... N). ij Each bistable node N i is the differential output (for example, v i + and v i - ) is provided to the mesh of coupling units. Each coupling unit CU ij is a network of two nodes (e.g., N i and N j ) resistor R ij The positive coupling coefficient J ij If, then node N i Positive output from v i + is the node N j Positive node v from j + is connected to the negative output v i - is v j - Alternatively, the coupling coefficient J ijIf is negative, node N i and N j The differential outputs from are cross-coupled. The resistance of the coupling unit is R ij =R C / J ij where R C is a constant resistance whose value is appropriately chosen to allow each node to converge to one of the bistable states.

[0042] Figure 2 shows a bistable node N implemented with discrete electronic components for use in the topology of Figure 1. i An exemplary circuit of N i The balanced BRIM node is N i node and two other nodes (N j and N k ) The circuit has a connection between the state variable v i (t), and its trajectory is represented by the ordinary differential equation shown in equation (9).

[0043] Figure 3 shows an example of a balanced ZIV diode implemented with two op-amps that can be incorporated into the exemplary circuit of Figure 2. The balanced ZIV diode can be implemented with discrete components with arbitrarily chosen polarity of the diode terminals.

[0044] Figure 4 shows an example of the IV curve (i = gD(v)) of a ZIV diode. The IV curve of a balanced ZIV diode is plotted against various load resistances R L The curve is taken from the ZIV diode in Figure 3, where R1 = 9.1k, R2 = 2.6k, and LF 412 The opamp is driven with + / - 9V. The IV curve has three equilibrium points (i=0), one unstable point at the origin (i=0 and v=0) and two stable equilibrium points (e.g. v=-2.3V and v=+2.3V for a 1.5K load resistor) that result in a bistable behavior of the BRIM node.

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[0045] FIG. 5 shows an example of a discrete BRIM prototype implementing six bistable nodes from the circuit elements described in FIGS. 2 and 3. FIG. 6 shows the voltage v i ( t ) converges to one of the stable states and voltages from the example embodiment of FIG.

[0046] Exemplary voltage waveforms in Figure 6 are shown at the output of the nodes of the discrete BRIM of Figure 5. The output voltages from nodes N1, N2, N3, and N5 converge to +1.15V representing "up" spin, while the voltages from nodes N4 and N6 converge to -1.15V representing "down" spin. After convergence is complete, the voltages are compared to a 0V threshold to measure polarity, and the result is presented to the user as a "spin" value, and the maximum cut solution of the corresponding graph is determined.

[0047] 8. Exemplary BRIM Integrated Circuit Design Architecture Here we describe an exemplary implementation of BRIM in CMOS integrated circuit technology. The design shares a general structure with the simplified example using discrete components, but introduces a number of variations that help improve the flexibility of the system. Figure 7 shows an exemplary BRIM system (node ​​N) that can be implemented in CMOS, defined by the following group of components: i and the coupling unit CU ij (having).

[0048] Nodes and Couplers: On the left side of Figure 7 are bistable nodes N1, N2, N3, and N4. Each of the bistable nodes N1, N2, N3, and N4 includes a pair of capacitors, two resistors, and a special diode, and has two differential terminals (V i + and V i -) across terminals "output+" 102 and "input+" 104, and "output-" 106 and "input-" 108, respectively. FIG. 8 shows an example of a transistor-level implementation of an integrated bistable node with four terminals "output+" 102 and "input+" 104, and "output-" 106 and "input-" 108. Each of the bistable nodes is connected from its terminals to a coupling unit (CU ij , where i=1 to 4, j=1 to 4, except j=i), each of the coupling units involves four terminals, two terminals connected to two input nodes and two terminals connected to output nodes. Note that here the coupling is directed / unidirectional. This is achieved by buffers (e.g., transistors M5 to M9 in Fig. 8). In principle, undirected / bidirectional couplings have a similar effect. However, empirically, directed couplings lead to better solution quality at the expense of increased circuit area.

[0049] Programming Unit: The resistance of the coupling is programmable. FIG. 9 shows an example coupling unit circuit diagram using transistors with adjustable gate voltages to achieve programmable resistance. To the right of the coupling unit array in FIG. 7, there are i coupling units CU ij There is a programming array coupled to each string of CUs. This array includes a digital memory (MEM) for storing weights that drive an array of digital-to-analog converters (DACs) by means of multiplexers MUX1 to MUX4. Such a small number of DACs is sufficient to program all the combiner units in a time-interleaved manner. In the figure, N DACs are shown programming N×(N-1) combiner units. In such a configuration, the combiner units CUs ij 1. In order to achieve this, a corresponding column selector 110 and pull-down logic 112, shown above and below, are required.

[0050] Annealing Scheduler: The coupling strength can be adjusted over time for annealing. Exponential annealing is used as both can be conveniently achieved using a discharge capacitor as a global annealing scheduler. The annealing operation in this exemplary IC design is accomplished by transistors M10 and M21 in FIG. 8. The gate bias voltage of the transistors sets the channel resistance, which then loads the buffer, reducing the buffer gain and overall coupling strength. For example, V anneal Setting V to a high value reduces the gain of the buffer to almost zero, eliminating any coupling to other nodes altogether. Conversely, V anneal Setting to zero volts allows maximum gain from the buffer and maximum coupling strength limited only by the coupling unit. At the end of the annealing, the state of the node is read out from the node. With the stable voltages appropriately adjusted, the readout can be achieved with a simple flip-flop.

[0051] Perturbation Unit: Finally, the perturbation unit is useful because of its ability to invert the state of selected nodes. This gives the system the ability to escape its current field of attraction. Note that this is a form of introducing a perturbation. An alternative is to add circuit-level noise. Both can achieve similar results, but introducing analog noise is harder to control and leads to a greater mismatch between the simulation and the actual hardware.

[0052] The described exemplary BRIM can be used like any other Ising machine: first you program the weights, then you select the annealing length, and finally you read out the state of the nodes. Using the described elements, the system can be used in several different ways. For example, the annealing time can be adjusted. The perturbation units can be turned on at different frequencies. The machine can be used with software-based search algorithms (e.g., simulated annealing).

[0053] This concludes the description including the preferred embodiments of the present invention. The foregoing description including the preferred embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations are possible within the scope of the above teachings. Additional variations of the present invention may be devised without departing from the inventive concept as set forth in the claims.

Claims

1. A network of resistively coupled circuit nodes, comprising: At least one node, the at least one node comprising: a capacitor, the voltage across which represents a state variable of the node, the voltage being resistively coupled to at least one other node of the network; an active electronic element having two terminals connected in parallel with the capacitor for supplying energy to the node, the active electronic element having an odd symmetric current-voltage characteristic, the odd symmetric current-voltage characteristic being: a negative current gradient for a voltage between the two terminals whose magnitude is less than a predetermined threshold, and a positive gradient otherwise; Three voltage instances (zero volts, +V 1 Volts and -V 1 volts), and V 1 is a constant greater than the predefined threshold,

2. A programmable resistor is connected in parallel with the active electronic device to determine the odd symmetric current-voltage characteristic and V 1 2. The network of claim 1, wherein said negative current gradient and said positive current gradient are adjusted in

3. A bipolar junction transistor is connected in parallel with the active electronic device, and the odd symmetric current-voltage characteristic and V 1 2. The network of claim 1, wherein said negative current gradient and said positive current gradient are adjusted in

4. A field effect transistor is connected in parallel with the active electronic device, and the odd symmetric current-voltage characteristic and V 1 2. The network of claim 1, wherein said negative current gradient and said positive current gradient are adjusted in

5. A network of coupling circuit nodes, comprising: At least one node, the at least one node comprising: a capacitor, a voltage across the capacitor representing a state variable of the node, the voltage being converted to a current before being coupled to at least one other node of the network; an active electronic element having two terminals connected in parallel with the capacitor for supplying energy to the node, the element having an odd symmetric current-voltage characteristic, the odd symmetric current-voltage characteristic being: a negative current gradient for a voltage between the two terminals whose magnitude is less than a predetermined threshold, and a positive gradient otherwise; Three voltage instances (zero volts, +V 1 Volts and -V 1 volts), and V 1 is a constant greater than the predefined threshold,

6. A programmable resistor is connected in parallel with the active electronic device to determine the odd symmetric current-voltage characteristic and V 1 6. The network of claim 5, wherein said negative current gradient and said positive current gradient are adjusted in

7. A bipolar junction transistor is connected in parallel with the active electronic device, and the odd symmetric current-voltage characteristic and V 1 6. The network of claim 5, wherein said negative current gradient and said positive current gradient are adjusted in

8. A field effect transistor is connected in parallel with the active electronic device, and the odd symmetric current-voltage characteristic and V 1 6. The network of claim 5, wherein said negative current gradient and said positive current gradient are adjusted in

9. 1. A method for solving a maximum cut problem on a graph, comprising the steps of: mapping vertices of the graph to nodes of a network of resistively coupled circuit nodes; and mapping edge weights of the graph to connection resistances of the network, the network comprising: At least one node, the at least one node comprising: a capacitor, the voltage across which represents a state variable of the node, the voltage being resistively coupled to at least one other node of the network; an active electronic element having two terminals connected in parallel with the capacitor for supplying energy to the node, the active electronic element having an odd symmetric current-voltage characteristic, the odd symmetric current-voltage characteristic being: a negative current gradient for a voltage between the two terminals whose magnitude is less than a predetermined threshold, and a positive gradient otherwise; Three voltage instances (zero volts, +V 1 Volts and -V 1 volts), and V 1 is a constant greater than the predetermined threshold, a connection resistance between any two nodes of the network corresponding to two vertices on the graph is inversely proportional to the weight of the edge between the two vertices; Any two nodes of the network corresponding to positively connected vertices on the graph are cross-coupled to the capacitors of the two corresponding nodes with opposite polarity via the coupling resistors; Any two nodes of the network corresponding to negatively connected vertices on the graph are coupled in parallel to the capacitors of the two corresponding nodes with the same polarity via the coupling resistors.

10. 1. A method for solving a maximum cut problem on a graph, comprising the steps of: mapping vertices of the graph to nodes of a network of combined circuit nodes; and mapping edge weights of the graph to connection currents of the network, the network comprising: At least one node, the at least one node comprising: a capacitor, the voltage across which represents a state variable of the node, the voltage being converted to a current before being coupled to at least one other node of the network; an active electronic element having two terminals connected in parallel with the capacitor for supplying energy to the node, the element having an odd symmetric current-voltage characteristic, the odd symmetric current-voltage characteristic being: a negative current gradient for a voltage between the two terminals whose magnitude is less than a predetermined threshold, and a positive gradient otherwise; Three voltage instances (zero volts, +V 1 Volts and -V 1 volts), and V 1 is a constant greater than the predetermined threshold, a coupling current between any two nodes of the network corresponding to two vertices on the graph is proportional to the weight of the edge between the two vertices; any two nodes of the network corresponding to positively connected vertices on the graph are cross-coupled such that the combined current charges the capacitors of the two corresponding nodes with opposite polarities; A method according to claim 1, wherein any two nodes of the network corresponding to negatively connected vertices on the graph are coupled in parallel such that the combined current charges the capacitors of the two corresponding nodes with the same polarity.

11. 1. A device for solving a maximum cut problem on a graph, the vertices of the graph corresponding to nodes of a network of resistor-coupled circuit nodes, the weights of the edges of the graph corresponding to coupling resistances of the network, the network comprising: At least one node, the at least one node comprising: a capacitor, the voltage across which represents a state variable of the node, the voltage being resistively coupled to at least one other node of the network; an active electronic element having two terminals connected in parallel with the capacitor for supplying energy to the node, the element having an odd symmetric current-voltage characteristic, the odd symmetric current-voltage characteristic being: a negative current gradient for a voltage between the two terminals whose magnitude is less than a predetermined threshold, and a positive gradient otherwise; Three voltage instances (zero volts, +V 1 Volts and -V 1 volts), and V 1 is a constant greater than the predetermined threshold, a connection resistance between any two nodes of the network corresponding to two vertices on the graph is inversely proportional to the weight of the edge between the two vertices; Any two nodes of the network corresponding to positively connected vertices on the graph are cross-coupled to the terminals of the capacitors of the two corresponding nodes with opposite polarities via the coupling resistors; A device, wherein any two nodes of the network corresponding to negatively connected vertices on the graph are coupled in parallel to the capacitors of the two corresponding nodes having the same polarity via the coupling resistors.

12. 1. A device for solving a maximum cut problem on a graph, the vertices of the graph corresponding to nodes of a network of coupled circuit nodes, the weights of the edges of the graph corresponding to coupling currents of the network, the network comprising: At least one node, the at least one node comprising: a capacitor, the voltage across which represents a state variable of the node, the voltage being converted to a current before being coupled to at least one other node of the network; a two-terminal active electronic device connected in parallel with the capacitor for supplying energy to the node, the device having an odd symmetric current-voltage characteristic, the odd symmetric current-voltage characteristic being: a negative current gradient for a voltage between the two terminals whose magnitude is less than a predetermined threshold, and a positive gradient otherwise; Three voltage instances (zero volts, +V 1 Volts and -V 1 volts), and V 1 is a constant greater than the predetermined threshold, a coupling current between any two nodes of the network corresponding to two vertices on the graph is proportional to the weight of the edge between the two vertices; any two nodes of the network corresponding to positively connected vertices on the graph are cross-coupled such that the combined current charges the capacitors of the two corresponding nodes with opposite polarities; A device, wherein any two nodes of the network corresponding to negatively connected vertices on the graph are coupled in parallel such that the combined current charges the capacitors of the two corresponding nodes with the same polarity.

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