Compound semiconductor substrate and compound semiconductor device

Abstract

To provide a compound semiconductor substrate and a compound semiconductor device with high quality.SOLUTION: A compound semiconductor substrate CS1 includes an Si substrate 1 with O concentration of 3×1017 pieces / cm3 or more and 3×1018 pieces / cm3 or less, a SiC layer 2 formed on the Si substrate 1, a first nitride semiconductor layer 4 formed on the SiC layer 2, which includes an insulating or semi-insulating layer and is composed of AlxGa1-xN (0.1≤x≤1), a second nitride semiconductor layer 5 formed on the first nitride semiconductor layer 4, which includes a C-GaN layer 51, and an electron traveling layer 6 formed on the second nitride semiconductor layer 5 and composed of AlzGa1-zN (0≤z<0.1). The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron traveling layer 6 is 6 μm or more and 10 μm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a compound semiconductor substrate and a compound semiconductor device, and more particularly to a compound semiconductor substrate and a compound semiconductor device that include an electron transport layer and a barrier layer. [Background technology]

[0002] In recent years, communication devices such as smartphones have become widespread. Accordingly, there is an increasing need to improve the communication capacity and communication speed between communication devices in mobile wireless communication systems. In recent mobile wireless communication systems, LTE (Long Term Evolution), a mobile phone communication standard, has been implemented. The practical application of the next generation communication standard after LTE is also being considered.

[0003] As a key technology in the above mobile communication systems, HEMTs (High Electron Mobility Transistors) made of nitride semiconductors such as GaN (Gallium Nitride) and AlGaN (Aluminum Gallium Nitride) have been attracting attention. HEMT technology made of nitride semiconductors has been rapidly developed in recent years.

[0004] A HEMT includes an electron transport layer and a barrier layer formed on the electron transport layer. The material that constitutes the barrier layer has a band gap wider than the band gap of the material that constitutes the electron transport layer. In a HEMT, two-dimensional electron gas is formed in the electron transport layer near the interface with the barrier layer. This two-dimensional electron gas is used to operate the HEMT. HEMTs made of nitride semiconductors can generate more two-dimensional electron gas and have a higher current density than field effect transistors made of GaAs (gallium arsenide)-based semiconductor materials.

[0005] As an example, the difference in lattice constant between AlGaN and GaN is larger than the difference in lattice constant between AlGaAs (aluminum gallium arsenide) and GaAs. Therefore, the AlGaN layer in the AlGaN / GaN laminate structure is distorted more than the AlGaAs layer in the AlGaAs / GaAs laminate structure. Therefore, a larger piezoelectric field is generated in the AlGaN layer in the AlGaN / GaN laminate structure than the AlGaAs layer in the AlGaAs / GaAs laminate structure. Due to this larger piezoelectric field, more two-dimensional electron gas is induced in the AlGaN / GaN laminate structure than in the AlGaAs / GaAs laminate structure. In addition, unlike the AlGaAs layer, the AlGaN layer is highly spontaneously polarized. Due to the polarization field caused by the spontaneous polarization of the AlGaN layer, a lot of two-dimensional electron gas is induced in the GaN layer near the boundary with the AlGaN layer. As a result, a HEMT made of AlGaN / GaN, which is a nitride semiconductor, can generate about 10 times more two-dimensional electron gas than a field effect transistor made of AlGaAs / GaAs, which is a GaAs system.

[0006] Therefore, HEMTs made of nitride semiconductors are capable of operating with high output and high efficiency, and are therefore expected to be the next generation of high-power amplifiers.

[0007] In order to use a HEMT made of a nitride semiconductor as a radio-frequency amplifier in the above-mentioned mobile communication system, it is important to suppress the loss of radio-frequency signals when a radio-frequency voltage is applied to the gate electrode of the HEMT. The main causes of this radio-frequency signal loss are the parasitic capacitance and parasitic resistance of the semiconductor device. If the parasitic capacitance of the semiconductor device is large and a parasitic resistance component exists in parallel with the parasitic capacitance, these parasitic elements contribute to the loss of radio-frequency signals and hinder the high-speed operation of the semiconductor device.

[0008] In order to prevent the attenuation of high-frequency signals due to the above-mentioned causes, it is effective to construct the region around the two-dimensional electron gas with a highly insulating material. The above-mentioned parasitic elements can be reduced by using a semi-insulating substrate or a high-resistance substrate as the substrate of the HEMT. On the other hand, when a conductive substrate is used as the substrate of the HEMT, the above-mentioned parasitic elements can be reduced by interposing a thick semi-insulating or high-resistance compound semiconductor layer between the conductive substrate and the components of the semiconductor device. From this viewpoint, various structures have been proposed in the past. For example, the following Patent Document 1 and Non-Patent Document 1 disclose a structure shown in FIG. 22.

[0009] FIG. 22 is a cross-sectional view showing a schematic diagram of a first example of a structure of a conventional HEMT.

[0010] 22, the first example HEMT 1010 includes a semi-insulating SiC (silicon carbide) substrate 1051, a nitride buffer layer 1052, an electron transit layer 1053 made of GaN, a barrier layer 1054 made of AlGaN, a source electrode 1055, a drain electrode 1056, and a gate electrode 1057. The nitride buffer layer 1052 is formed on the semi-insulating SiC substrate 1051. The electron transit layer 1053 is formed on the nitride buffer layer 1052. The barrier layer 1054 is formed on the electron transit layer 1053. The source electrode 1055, the drain electrode 1056, and the gate electrode 1057 are formed on the barrier layer 1054. The source electrode 1055, the drain electrode 1056, and the gate electrode 1057 are formed at intervals from each other.

[0011] In the HEMT 1010, a two-dimensional electron gas 1053a is formed in the electron transit layer 1053 near the boundary with the barrier layer 1054. In order to configure the area around the two-dimensional electron gas 1053a with a highly insulating material, the electron transit layer 1053, the nitride buffer layer 1052, and the SiC substrate 1051 are configured with highly insulating materials. However, there is a problem with the semi-insulating SiC substrate in that it is difficult to obtain a large-sized substrate. This is presumably because it is difficult to grow a crystal of semi-insulating SiC. Specifically, it is difficult to obtain a semi-insulating SiC substrate with a diameter exceeding 4 inches. In addition, the semi-insulating SiC substrate is expensive compared to other substrates.

[0012] Therefore, as a technology that does not use a semi-insulating SiC substrate, the structures shown in Fig. 23 and Fig. 24 have been proposed. The structure shown in Fig. 23 is disclosed in the following Non-Patent Document 2. The structure shown in Fig. 24 is disclosed in the following Patent Document 2 and Non-Patent Document 3.

[0013] FIG. 23 is a cross-sectional view showing a schematic diagram of a second example of the structure of a conventional HEMT.

[0014] 23, the HEMT 1020 as the second example differs from the structure shown in FIG 22 in that a high-resistance Fz-Si (silicon) substrate 1061 is used as the substrate instead of the semi-insulating SiC substrate. The Fz-Si substrate is a Si substrate fabricated by the Fz method (Floating zone method). The nitride buffer layer 1052 in the HEMT 1020 has a thickness of, for example, 1 μm.

[0015] 23, the region around the two-dimensional electron gas 1053a is made of a highly insulating material, so that the electron transit layer 1053, the nitride buffer layer 1052, and the Fz-Si substrate 1061 are made of a highly insulating material. In addition, the Fz-Si substrate 1061 is less expensive than a semi-insulating SiC substrate.

[0016] FIG. 24 is a cross-sectional view showing a schematic diagram of a third example of the structure of a conventional HEMT.

[0017] 24, a HEMT 1030 as a third example differs from the structure shown in FIG 22 in that an n-type SiC substrate 1062 is used as the substrate instead of a semi-insulating SiC substrate, and the nitride buffer layer 1052 is thick. The n-type SiC substrate 1062 has a hexagonal crystal structure. The nitride buffer layer 1052 has a thickness of 10 μm or more.

[0018] In the structure shown in FIG. 24, the nitride buffer layer 1052 and the electron transit layer 1053 are made of highly insulating materials in order to configure the region around the two-dimensional electron gas 1053a with a highly insulating material. The nitride buffer layer 1052 is formed with a thickness of more than 10 μm. In addition, it is easy to obtain a large-sized n-type SiC substrate 1062 compared to a semi-insulating SiC substrate. Specifically, it is possible to obtain an n-type SiC substrate 1062 with a diameter of 6 inches. [Prior art documents] [Patent documents]

[0019] [Patent Document 1] Special Publication No. 2006-517726 (Patent No. 4990496) [Patent Document 2] International Publication No. 2007 / 116517 (Patent No. 5274245) [Non-patent literature]

[0020] [Non-Patent Document 1] ST Sheppard et al. "High-Power Microwave GaN / AlGaN HEMT's on Semi-Insulating Silicon Carbide Substrates", IEEE Electron Device Lett., vol.20, No.4, pp.161-163, Apr 1999. [Non-Patent Document 2] JW Johnson et al. "12 W / mm AlGaN-GaN HFETs on Silicon Substrates", IEEE Electron Device Lett., vol.25, No.7, pp.459-461, Jul 2004. [Non-Patent Document 3] Toshihide Kikkawa et al. "Highly Uniform AlGaN / GaN Power HEMT on a 3-inch Conductive N-SiC Substrate for Wireless Base Station Application", Technical Digest of IEEE CSIC 2005 Symposium, vol.25, No.7, pp.77-80. Summary of the Invention [Problem to be solved by the invention]

[0021] However, the structures shown in Figures 23 and 24 have the problem of low quality.

[0022] In the HEMT 1020 shown in FIG. 23, an insulating Fz-Si substrate 1061 is used as a substrate. The elastic limit of the Fz-Si substrate 1061 is low. Therefore, during the growth of the nitride buffer layer 1052, the substrate is easily plastically deformed by the stress from the nitride buffer layer 1052 due to the difference in lattice constant between the Fz-Si substrate 1061 and the nitride buffer layer 1052. As a result, there was a problem that the warp of the substrate increased to an inappropriate level in the manufacturing process of the HEMT. In addition, since Si has a smaller band gap than SiC, it is easily reduced in resistance at high temperatures. Therefore, when the temperature of the substrate rises due to the amplification operation of the HEMT, there was a problem that the resistance of the Si contained in the substrate easily decreased, resulting in significant loss of high-frequency signals.

[0023] In the HEMT 1030 shown in FIG. 24, an n-type SiC substrate 1062 is used as a substrate. The n-type SiC substrate 1062 has high electrical conductivity. For this reason, it was necessary to thicken the nitride buffer layer 1052 in order to configure the region around the two-dimensional electron gas 1053a with a highly insulating material. When the nitride buffer layer 1052 is made thick, there are problems in that cracks are easily generated in the nitride buffer layer 1052 and that the warping of the substrate becomes large. In addition, from the viewpoint of manufacturing cost, the advantage of replacing the semi-insulating SiC substrate with the n-type SiC substrate is offset by the disadvantage of forming a thick nitride buffer layer. For this reason, from the viewpoint of manufacturing cost, the HEMT 1030 shown in FIG. 24 was not superior to the HEMT 1010 shown in FIG. 22.

[0024] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a high-quality compound semiconductor substrate and a compound semiconductor device. [Means for solving the problem]

[0025] The compound semiconductor substrate according to one aspect of the present invention has a surface area of ​​3×10 17 pieces / cm 3 More than 3×10 18 pieces / cm 3A Si substrate having the following O concentration, a SiC layer formed on the Si substrate, and a first nitride semiconductor layer formed on the SiC layer, the first nitride semiconductor layer including an insulating or semi-insulating layer, and an Al x Ga 1-x A first nitride semiconductor layer made of N (0.1≦x≦1) and a second nitride semiconductor layer formed on the first nitride semiconductor layer, the second nitride semiconductor layer being insulating or semi-insulating Al y Ga 1-y A second nitride semiconductor layer including a main layer made of N (0≦y<0.1); and an AlN layer formed on the second nitride semiconductor layer. z Ga 1-z N (0≦z<0.1), and a barrier layer formed on the electron transport layer and having a band gap wider than the band gap of the electron transport layer, the first and second nitride semiconductor layers and the electron transport layer having a total thickness of 6 μm or more and 10 μm or less. Further, the first nitride semiconductor layer includes at least one of a first region made of Al x Ga 1-x N (0.4 < x ≦ 1) and a second region made of Al x Ga 1-x N (0.1 ≦ x ≦ 0.4) having a thickness of 0.5 μm or more. The first region has an Si concentration of 0 atoms / cm 3 or more and 5×10 17 atoms / cm 3 or less, an O concentration of 0 atoms / cm 3 or more and 5×10 17 atoms / cm 3 or less, and an Mg concentration of 0 atoms / cm 3 or more and 5×10 17 atoms / cm 3 or less. The second region has an Si concentration of 0 atoms / cm 3 or more and 2×10 16 atoms / cm 3 or less, an O concentration of 0 atoms / cm 3 or more and 2×10 16 atoms / cm 3 or less, and an Mg concentration of 0 atoms / cm 3 or more and 2×10 16 atoms / cm 3 or less. At least one of the C concentration or the Fe concentration in the second region is higher than any of the Si concentration, the O concentration, and the Mg concentration in the second region and is 5×10 19atoms / cm 3 or less. The main layer has an Si concentration of 0 atoms / cm 3 or more and 2×10 16 atoms / cm 3 or less, an O concentration of 0 atoms / cm 3 or more and 2×10 16 atoms / cm 3 or less, and an Mg concentration of 0 atoms / cm 3 or more and 2×10 16 atoms / cm 3 or less. At least one of the C concentration or the Fe concentration in the second nitride semiconductor layer is higher than any of the Si concentration, the O concentration, and the Mg concentration in the second nitride semiconductor layer and is 5×10 19 atoms / cm 3 or less. The main layer includes a region having an activated donor ion concentration of 0 atoms / cm 3 or more and 2×10 14 atoms / cm 3 or less. The electron transport layer has an Si concentration of 0 atoms / cm 3 or more and 1×10 16 atoms / cm 3 or less, an O concentration of 0 atoms / cm 3 or more and 1×10 16 atoms / cm 3 or less, an Mg concentration of 0 atoms / cm 3 or more and 1×10 16 atoms / cm 3 or less, a C concentration of 0 atoms / cm 3 or more and 1×10 17 atoms / cm 3 or less, and an Fe concentration of 0 atoms / cm 3 or more and 1×10 17 atoms / cm 3 or less. Effect of the Invention

[0041] According to the present invention, it is possible to provide a high-quality compound semiconductor substrate and a compound semiconductor device. [Brief description of the drawings]

[0042]

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[0043] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0044] [First embodiment]

[0045] FIG. 1 is a cross-sectional view showing the configurations of a compound semiconductor device DC1 and a compound semiconductor substrate CS1 according to a first embodiment of the present invention.

[0046] 1, a compound semiconductor device DC1 (an example of a compound semiconductor device) in this embodiment includes a HEMT structure. The compound semiconductor device DC1 includes a compound semiconductor substrate CS1 (an example of a compound semiconductor substrate), a source electrode 11 (an example of a first electrode), a drain electrode 12 (an example of a second electrode), and a gate electrode 13 (an example of a third electrode). The source electrode 11, the drain electrode 12, and the gate electrode 13 are formed on a barrier layer 8 of the compound semiconductor substrate CS1. The gate electrode 13 controls a current flowing between the source electrode 11 and the drain electrode 12 by an applied voltage.

[0047] The compound semiconductor substrate CS1 includes a Si substrate 1 (an example of a Si substrate), a SiC layer 2 (an example of a SiC layer), a first nitride semiconductor layer 4 (an example of a first nitride semiconductor layer), a second nitride semiconductor layer 5 (an example of a second nitride semiconductor layer), an electron transit layer 6 (an example of an electron transit layer), and a barrier layer 8 (an example of a barrier layer).

[0048] The Si substrate 1 is fabricated by the Cz method (Czochralski method). In the Cz method, a Si seed crystal is gradually pulled up from molten Si in a quartz crucible into a specified atmosphere such as Ar. The Si attached to the seed crystal is cooled in the atmosphere and crystallized. This results in a single crystal of Si. In the Cz method, when Si crystallizes, O (oxygen) contained in the quartz material that makes up the crucible is incorporated into the crystal. For this reason, the Si substrate 1 has a higher O concentration than Si substrates fabricated by the Fz method. Specifically, the Si substrate 1 has an O concentration of 3×10 17 pieces / cm 3 More than 3×10 18 pieces / cm 3 The Si substrate 1 has the following O concentration. Since the Si substrate 1 has a high O concentration, it has a higher elastic limit than a Si substrate fabricated by the Fz method. It is easy to obtain a large-sized Si substrate 1 (e.g., 8-inch diameter) and it is inexpensive compared to a SiC substrate.

[0049] The Si substrate 1 is, for example, p +The Si substrate 1 is made of type Si. The Si substrate 1 does not need to be intentionally doped. The (111) plane is exposed on the upper surface of the Si substrate 1. The upper surface of the Si substrate 1 has an off angle of 0 to 1 degree, and more preferably has an off angle of 0.5 degrees or less. The Si substrate 1 preferably has a single crystal diamond structure.

[0050] When the Si substrate 1 contains B (boron) and has a p-type conductivity, the Si substrate 1 has a resistivity of, for example, 0.1 mΩcm to 100 mΩcm, preferably 0.5 mΩcm to 20 mΩcm, more preferably 1 mΩcm to 5 mΩcm.

[0051] Preferably, the Si substrate 1 has a diameter of about 50 mm (for example, 47 mm to 53 mm) and a thickness of 270 μm to 1600 μm. The Si substrate 1 has a diameter of about 50.8 mm (for example, 47.8 mm to 53.8 mm) and a thickness of 270 μm to 1600 μm. The Si substrate 1 has a diameter of about 75 mm (for example, 72 mm to 78 mm) and a thickness of 350 μm to 1600 μm. The Si substrate 1 has a diameter of about 76.2 mm (for example, 73.2 mm to 79.2 mm) and a thickness of 350 μm to 1600 μm. The Si substrate 1 has a diameter of about 100 mm (for example, 97 mm to 103 mm) and a thickness of 500 μm to 1600 μm. The Si substrate 1 has a diameter of about 125 mm (for example, 122 mm to 128 mm) and a thickness of 600 μm or more and 1600 μm or less. The Si substrate 1 has a diameter of about 150 mm (for example, 147 mm to 153 mm) and a thickness of 600 μm or more and 1600 μm or less. Alternatively, the Si substrate 1 has a diameter of about 200 mm (for example, 197 mm to 203 mm) and a thickness of 700 μm or more and 2100 μm or less.

[0052] More preferably, the Si substrate 1 has a diameter of about 100 mm (for example, 99.5 mm to 100.5 mm) and a thickness of 700 μm or more and 1100 μm or less. The Si substrate 1 has a diameter of about 125 mm (for example, 124.5 mm to 125.5 mm) and a thickness of 700 μm or more and 1100 μm or less. The Si substrate 1 has a diameter of about 150 mm (for example, 149.8 mm to 150.2 mm) and a thickness of 900 μm or more and 1100 μm or less. Alternatively, the Si substrate 1 has a diameter of about 200 mm (for example, 199.8 mm to 200.2 mm) and a thickness of 900 μm or more and 1600 μm or less.

[0053] The Si substrate 1 may have an n-type conductivity. The Si substrate 1 may have an exposed (100) or (110) surface on its upper surface.

[0054] The SiC layer 2 is in contact with the Si substrate 1 and is formed on the Si substrate 1. The SiC layer 2 is made of 3C-SiC, 4H-SiC, 6H-SiC, or the like. In particular, when the SiC layer 2 is epitaxially grown on the Si substrate 1, the SiC layer 2 is generally made of 3C-SiC.

[0055] The SiC layer 2 may be formed by homoepitaxially growing SiC on a base layer made of SiC obtained by carbonizing the upper surface of the Si substrate 1 using a molecular beam epitaxy (MBE) method, a chemical vapor deposition (CVD) method, a liquid phase epitaxy (LPE) method, or the like. The SiC layer 2 may be formed only by carbonizing the upper surface of the Si substrate 1. Furthermore, the SiC layer 2 may be formed by heteroepitaxially growing on the upper surface of the Si substrate 1 (or with a buffer layer sandwiched therebetween). The SiC layer 2 is doped with, for example, N (nitrogen) and has an n-type conductivity. The SiC layer 2 may have a p-type conductivity or may be semi-insulating.

[0056] The SiC layer 2 has a thickness of, for example, 0.5 μm or more and 2 μm or less. By making the thickness of the SiC layer 2 0.5 μm or more, it is possible to suppress a reaction (melt-back etching) between Si of the Si substrate 1 and Ga (gallium) contained in the upper layer of the Si substrate 1. In addition, the state of the upper surface of the SiC layer 2 can be made suitable for the growth of a material constituting the first nitride semiconductor layer 4. By making the thickness of the SiC layer 2 2 μm or less, it is possible to suppress the occurrence of cracks in the SiC layer 2, and it is possible to suppress the occurrence of warping of the Si substrate 1 caused by the SiC layer 2. The SiC layer 2 preferably has a thickness of 0.7 μm or more and 1.5 μm or less. It is more preferable that the SiC layer 2 has a thickness of 0.9 μm or more and 1.2 μm or less.

[0057] The first nitride semiconductor layer 4 is in contact with the SiC layer 2 and is formed on the SiC layer 2. The first nitride semiconductor layer 4 is made of Al x Ga 1-x N (0.1≦x≦1). The first nitride semiconductor layer 4 functions as a buffer layer that reduces the difference in lattice constant between the SiC layer 2 and the second nitride semiconductor layer 5. The first nitride semiconductor layer 4 has a thickness of, for example, 600 nm to 4 μm, preferably 1 μm to 3 μm, and more preferably 1.5 μm to 2.5 μm. The first nitride semiconductor layer 4 is formed by using a metal organic chemical vapor deposition (MOCVD) method. At this time, as the Al (aluminum) source gas, for example, TMA (tri methyl aluminum) or TEA (tri ethyl aluminum) is used. As the Ga source gas, for example, TMG (tri methyl gallium) or TEG (tri ethyl gallium) is used. As the N source gas, for example, NH3 (ammonia) is used. The first nitride semiconductor layer 4 preferably has a thickness equal to or less than the thickness of the second nitride semiconductor layer 5 described later.

[0058] The first nitride semiconductor layer 4 has insulating or semi-insulating properties. However, the region (lower layer) of the first nitride semiconductor layer 4 close to the SiC layer 2 may have extremely low crystallinity. Therefore, the region of the first nitride semiconductor layer 4 close to the SiC layer 2 may not necessarily have local insulating or semi-insulating properties. Even in this case, the region (upper layer) of the first nitride semiconductor layer 4 close to the electron traveling layer 6 has insulating or semi-insulating properties. The first nitride semiconductor layer 4 is composed of an unintentional doping layer (uid layer), a layer doped with C (carbon), or a layer doped with a transition metal, etc.

[0059] The uid layer means a layer in which no intentional introduction of impurities is performed during layer formation. The uid layer slightly contains impurities unintentionally introduced during layer formation (impurities in the atmosphere during layer formation).

[0060] The first nitride semiconductor layer 4 may be composed of a plurality of layers made of different materials from each other as described later. The first nitride semiconductor layer 4 contains at least one of a first region made of Al x Ga 1-x N (0.4 < x ≤ 1) and a second region made of Al x Ga 1-x N (0.1 ≤ x ≤ 0.4) having a thickness of 0.5 μm or more. The first nitride semiconductor layer 4 includes both the first region and the second region, and preferably, the distance between the first region and the SiC layer 2 is smaller than the distance between the second region and the SiC layer 2.

[0061] When the first nitride semiconductor layer 4 is a uid layer, the first region of the first nitride semiconductor layer 4 has an Si concentration of 0 atoms / cm 3 or more and 5×10 17 atoms / cm 3 or less, an O concentration of 0 atoms / cm 3 or more and 5×10 17 atoms / cm 3 or less, and an N concentration of 0 atoms / cm 3 or more and 5×10 17 atoms / cm 3The second region of the first nitride semiconductor layer 4 has a Mg concentration of 0 / cm 3 More than 2×10 16 pieces / cm 3 Si concentration below 0 particles / cm 3 More than 2×10 16 pieces / cm 3 O concentration below 0 particles / cm 3 More than 2×10 16 pieces / cm 3 Furthermore, at least one of the C concentration and the Fe concentration in the second region of the first nitride semiconductor layer 4 is higher than any of the Si concentration, the O concentration, and the Mg concentration in the second region of the first nitride semiconductor layer 4 by 5×10 19 pieces / cm 3 This makes it possible to improve the insulating properties of the first nitride semiconductor layer.

[0062] The second nitride semiconductor layer 5 is in contact with the first nitride semiconductor layer 4 and is formed on the first nitride semiconductor layer 4. The second nitride semiconductor layer 5 is formed between the first nitride semiconductor layer 4 and the electron transport layer 6. It is preferable that C or Fe is intentionally introduced into the second nitride semiconductor layer 5. In this case, at least one of the C concentration and the Fe concentration in the second nitride semiconductor layer 5 is higher than any of the Si concentration, the O concentration, and the Mg concentration in the second nitride semiconductor layer 5 by 5×10 19 pieces / cm 3 It is preferable that the second nitride semiconductor layer 5 is as follows: The second nitride semiconductor layer 5 includes a C-GaN layer 51 (an example of a main layer) and an intermediate layer 52 (an example of an intermediate layer).

[0063] The C-GaN layer 51 is a GaN layer containing C (a GaN layer into which C is intentionally introduced). C plays a role in enhancing the insulating properties of GaN. No impurities other than C are intentionally introduced into the C-GaN layer 51 during the formation of the layer. In this case, the C-GaN layer 51 has a density of 0 atoms / cm 3 More than 2×10 16 pieces / cm 3 Si concentration below 0 particles / cm 3 More than 2×1016 pieces / cm 3 O concentration below 0 particles / cm 3 More than 2×10 16 pieces / cm 3 The C-GaN layer 51 has an activated donor ion concentration of 0 ions / cm 3 More than 2×10 14 pieces / cm 3 It includes the following areas:

[0064] The main layer constituting the second nitride semiconductor layer 5 is not limited to the C-GaN layer 51, but may be an insulating or semi-insulating Al y Ga 1-y N (0≦y<0.1). The main layer constituting the second nitride semiconductor layer 5 preferably has at least one of a C concentration higher than the C concentration of the electron transit layer 6 and an Fe concentration higher than the Fe concentration of the electron transit layer 6. On the other hand, it is preferable that no impurities other than the above-mentioned C and Fe are intentionally introduced into the main layer constituting the second nitride semiconductor layer 5 during the formation of the layer.

[0065] The intermediate layer 52 is formed at least either inside the C-GaN layer 51 or on the C-GaN layer 51. The intermediate layer 52 is made of Al y Ga 1-y The intermediate layer 52 is preferably made of AlN (0.5≦y≦1). The intermediate layer 52 may be one or more layers. The intermediate layer 52 is preferably two layers or less, and more preferably one layer.

[0066] The second nitride semiconductor layer 5 of this embodiment includes two intermediate layers 52a and 52b. The intermediate layers 52a and 52b are formed inside the C-GaN layer 51. The C-GaN layer 51 is divided into three C-GaN layers 51a, 51b, and 51c by the intermediate layers 52a and 52b. The C-GaN layer 51a is the lowest layer among the layers constituting the second nitride semiconductor layer 5, and is in contact with the first nitride semiconductor layer 4. The intermediate layer 52a is in contact with the C-GaN layer 51a and is formed on the C-GaN layer 51a. The C-GaN layer 51b is in contact with the intermediate layer 52a and is formed on the intermediate layer 52a. The intermediate layer 52b is in contact with the C-GaN layer 51b and is formed on the C-GaN layer 51b. The C-GaN layer 51c is in contact with the intermediate layer 52b and is formed on the intermediate layer 52b. The C-GaN layer 51 c is the uppermost layer among the layers constituting the second nitride semiconductor layer 5 , and is in contact with the electron transit layer 6 .

[0067] In the C-GaN layer 51 (each of the C-GaN layers 51a, 51b, and 51c in this embodiment), the average carbon concentration in the depth direction at the center PT1 (FIG. 4) is 3×10 18 pieces / cm 3 5×10 or more 20 pieces / cm 3 ≦3×10 18 pieces / cm 3 More than 2×10 19 pieces / cm 3 When the C-GaN layer 51 is divided into a plurality of C-GaN layers, each of the plurality of C-GaN layers may have the same average carbon concentration or may have a different average carbon concentration. Of the plurality of C-GaN layers, the uppermost C-GaN layer preferably has a higher C concentration than the C concentration of the electron transit layer 6.

[0068] In addition, when the C-GaN layer 51 is divided into a plurality of C-GaN layers, each of the plurality of C-GaN layers has a thickness of, for example, 550 nm to 3000 nm, and preferably 800 nm to 2500 nm. Each of the plurality of C-GaN layers may have the same thickness or different thicknesses.

[0069] When the second nitride semiconductor layer 5 includes two or more intermediate layers 52 (intermediate layers 52a and 52b in this embodiment), each of the two or more intermediate layers may have the same thickness or different thicknesses. Each of the two or more intermediate layers preferably has a thickness of 10 nm or more and 30 nm or less. Each of the two or more intermediate layers is preferably formed at an interval of 0.5 μm or more and 10 μm or less.

[0070] The second nitride semiconductor layer 5 is formed by using the MOCVD method. In general, when forming a C-GaN layer, the growth temperature of the GaN layer is set lower than the growth temperature of the GaN layer when C is not incorporated (specifically, the temperature is set to about 300° C. lower than the growth temperature of the GaN layer when C is not intentionally doped). As a result, C contained in the Ga source gas is incorporated into the GaN layer, and the GaN layer becomes a C-GaN layer. On the other hand, if the growth temperature of the GaN layer is lowered, the quality of the C-GaN layer is degraded, and the in-plane uniformity of the C concentration of the C-GaN layer is degraded.

[0071] Therefore, the inventors of the present application have found a method of introducing a hydrocarbon as a C source gas (C precursor) together with a Ga source gas and an N source gas into a reaction chamber when forming a C-GaN layer. This method promotes the incorporation of C into the GaN layer, so that the C-GaN layer can be formed while setting the GaN growth temperature at a high temperature (specifically, at a temperature about 200° C. lower than the growth temperature of a GaN layer that is not intentionally doped with C). As a result, the quality of the C-GaN layer is improved, and the in-plane uniformity of the C concentration in the C-GaN layer is improved.

[0072] Specifically, the C source gas may be a hydrocarbon such as methane, ethane, propane, butane, pentane, hexane, heptane, octane, ethylene, propylene, butene, pentene, hexene, heptene, octene, acetylene, propyne, butyne, pentyne, hexyne, heptyne, or octyne. Hydrocarbons containing double bonds or triple bonds are particularly preferred because of their high reactivity. Only one type of hydrocarbon may be used as the C source gas, or two or more types of hydrocarbons may be used.

[0073] Moreover, the first nitride semiconductor layer 4 preferably has a thickness equal to or less than that of the second nitride semiconductor layer 5. When forming a nitride layer containing Al using MOCVD, a source gas containing an organometallic gas of Al and ammonia is introduced onto the substrate. At this time, if the flow rate of the source gas is high, the organometallic gas of Al and ammonia react unnecessarily to generate particles in the gas phase. For this reason, the flow rate of the source gas cannot be increased, and it takes a long time to form a nitride layer containing Al. The Al composition ratio of the first nitride semiconductor layer 4 is higher than the Al composition ratio of the main layer of the second nitride semiconductor layer 5. For this reason, by having the first nitride semiconductor layer 4 have a thickness equal to or less than that of the second nitride semiconductor layer 5, the time required to form the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5 can be shortened.

[0074] Note that another layer such as a GaN layer that is a uid layer (uid-GaN layer) may be interposed between the first nitride semiconductor layer 4 and the second nitride semiconductor layer 5. The second nitride semiconductor layer 5 may include layers other than the intermediate layer, or the intermediate layer may be omitted.

[0075] The electron transit layer 6 is in contact with the second nitride semiconductor layer 5 and is formed on the second nitride semiconductor layer 5. The electron transit layer 6 is made of Al z Ga 1-zN (0≦z<0.1). The electron transit layer 6 is preferably a uid layer, and it is preferable that no impurities are intentionally introduced during the formation of the layer to make it n-type, p-type, or semi-insulating. In this case, the Si concentration, O concentration, Mg concentration, C concentration, and Fe concentration of the electron transit layer 6 are all greater than 0 and less than 1×10 17 pieces / cm 3 The electron transit layer 6 has a density of 0 electrons / cm 3 More than 1×10 16 pieces / cm 3 Si concentration below 0 particles / cm 3 More than 1×10 16 pieces / cm 3 O concentration below 0 particles / cm 3 More than 1×10 16 pieces / cm 3 Mg concentration below 0 particles / cm 3 More than 1×10 17 pieces / cm 3 The following C concentrations and 0 particles / cm 3 More than 1×10 17 pieces / cm 3 It is more preferable that the Fe concentration is as follows: The electron transit layer 6 has a thickness of, for example, 0.3 μm or more and 5 μm or less The electron transit layer 6 is formed by using an MOCVD method.

[0076] In particular, in the region of the electron transit layer 6 within 0.5 μm from the boundary with the barrier layer 8, the 17 pieces / cm 3 When the region of the electron transit layer 6 within 0.5 μm from the boundary with the barrier layer 8 has the above C concentration, the region of the electron transit layer 6 within 3 μm from the boundary with the barrier layer 8 has a C concentration of 0 to 1×10 18 pieces / cm 3 It is preferable that the C concentration in the region near the two-dimensional electron gas 6a is within the above range, thereby making it possible to suppress current collapse and to suppress deterioration of the high frequency characteristics of the HEMT.

[0077] The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron traveling layer 6 is 6 μm or more and 10 μm or less. The thickness W is preferably 7.5 μm or more and 8.5 μm or less.

[0078] The barrier layer 8 is in contact with the electron traveling layer 6 and is formed on the electron traveling layer 6. The barrier layer 8 is made of a nitride semiconductor having a bandgap wider than that of the electron traveling layer 6. The barrier layer 8 is made of, for example, a nitride semiconductor containing Al, for example, Al a Ga 1-a N (0 < a ≤ 1). The barrier layer 8 is preferably made of Al a Ga 1-a N (0.17 ≤ a ≤ 0.27), and more preferably made of Al a Ga 1-a N (0.19 ≤ a ≤ 0.22). The barrier layer 8 has a thickness of, for example, 10 nm or more and 50 nm or less. The barrier layer 8 preferably has a thickness of, for example, 25 nm or more and 34 nm or less. When the barrier layer 8 is made of a material represented by Al a Ga 1-a N (0 < a ≤ 1), the growth temperature when forming the barrier layer 8 is, for example, 1000 °C or more and 1100 °C or less. The barrier layer 8 is formed using the MOCVD method.

[0079] Note that a spacer layer or the like may be interposed between the electron traveling layer 6 and the barrier layer 8. A cap layer or a passivation layer may be formed on the barrier layer 8.

[0080] FIG. 2 is a diagram showing the distribution of the Al composition ratio inside the first nitride semiconductor layer 4 in the first embodiment of the present invention.

[0081] Referring to FIG. 2, the composition ratio of Al inside the first nitride semiconductor layer 4 decreases from the lower part to the upper part. The first nitride semiconductor layer 4 includes an AlN layer 40 and an AlGaN layer 4a. The AlN layer 40 is in contact with the SiC layer 2 and is formed on the SiC layer 2.

[0082] The AlGaN layer 4a is in contact with the AlN layer 40 and is formed on the AlN layer 40. The composition ratio of Al inside the AlGaN layer 4a decreases from the lower part to the upper part. The AlGaN layer 4a is composed of an Al 0.75 Ga 0.25 N layer 41 (AlGaN layer with an Al composition ratio of 0.75), an Al 0.5 Ga 0. 5 N layer 42 (AlGaN layer with an Al composition ratio of 0.5), and an Al 0.25 Ga 0.75 N layer 43 (AlGaN layer with an Al composition ratio of 0.25). The Al 0.75 Ga 0.25 N layer 41 is in contact with the AlN layer 40 and is formed on the AlN layer 40. The Al 0.5 Ga 0.5 N layer 42 is in contact with the Al 0.75 Ga 0.25 N layer 41 and is formed on the Al 0.75 Ga 0.25 N layer 41. The Al 0.25 Ga 0.75 N layer 43 is in contact with the Al 0.5 Ga 0.5 N layer 42 and is formed on the Al 0.5 Ga 0.5 N layer 42.

[0083] Each of the AlN layer 40, the Al 0.75 Ga 0.25 N layer 41, and the Al 0.5 Ga 0. 5 N layer 42 corresponds to a first region of the first nitride semiconductor layer 4 made of Al x Ga 1-x N (0.4 < x ≤ 1). The Al 0.25 Ga 0.75 N layer 43 corresponds to a second region of the first nitride semiconductor layer 4 made of Al x Ga 1-x N (0.1 ≤ x ≤ 0.4).

[0084] The Al composition ratio inside the first nitride semiconductor layer 4 is arbitrary. When the first nitride semiconductor layer 4 is composed of a plurality of layers, the bottommost layer is preferably an AlN layer.

[0085] In this embodiment, the total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transit layer 6 is 6 μm or more and 10 μm or less. Since the thickness W is 6 μm or more, the direction toward the substrate side as viewed from the two-dimensional electron gas 6a is covered with a thick insulating or semi-insulating layer. As a result, high-frequency loss due to the parasitic capacitance and parasitic resistance of the substrate can be suppressed, and the high-frequency characteristics of the HEMT can be improved. In addition, since the thickness W is 10 μm or less, it is possible to suppress the occurrence of cracks and the occurrence of warping of the substrate due to the increase in the total thickness of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transit layer 6. Specifically, the amount of warping of the compound semiconductor substrate CS1 can be suppressed to a range of more than 0 and 50 μm or less.

[0086] The Si substrate 1 is fabricated by the Cz method. 17 pieces / cm 3 More than 1×10 19 pieces / cm 3 The Si substrate 1 has a high O concentration of 0.01 to 0.1 μm, and has a high elastic limit. By using the Si substrate 1 produced by the Cz method, it is possible to suppress warping of the substrate caused by the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transport layer 6 formed to a total thickness W of 6 μm to 10 μm. In addition, by forming the SiC layer 2 between the Si substrate 1 and the first nitride semiconductor layer 4, it is possible to suppress melt-back etching caused by a reaction between Ga contained in the layer formed on the Si substrate 1 and Si of the Si substrate 1. In addition, by forming the SiC layer 2 between the Si substrate 1 and the first nitride semiconductor layer 4, the SiC layer 2 serves as a buffer layer between the Si substrate 1 and the first nitride semiconductor layer 4, and it is possible to suppress the occurrence of cracks in the first nitride semiconductor layer 4. As a result, it is possible to provide a compound semiconductor substrate and a compound semiconductor device having high quality.

[0087] Furthermore, according to the present embodiment, in the second nitride semiconductor layer 5, by forming the intermediate layer 52 at least either inside or on the C-GaN layer 51, it is possible to prevent the Si substrate 1 from warping and to prevent the occurrence of cracks in the C-GaN layer 51 or the electron transit layer 6 on the intermediate layer 52. This will be described below.

[0088] When the intermediate layer 52 is formed inside the C-GaN layer 51, the base of the intermediate layer 52 is the C-GaN layer 51, and the layer formed on the intermediate layer 52 is also the C-GaN layer 51. When the intermediate layer 52 is formed on the C-GaN layer 51, the base of the intermediate layer 52 is the C-GaN layer 51, and the layer formed on the intermediate layer 52 is the electron transit layer 6.

[0089] Al constituting the intermediate layer 52 y Ga 1-y N (0.5≦y≦1) is the GaN that constitutes the C-GaN layer 51 (or more generally, the Al that constitutes the main layer). y Ga 1-y On the other hand, the GaN constituting the C-GaN layer 51 on the intermediate layer 52 or the Al constituting the electron transport layer 6 is epitaxially grown on the C-GaN layer 51 in a mismatched state (a state where slippage occurs) with respect to the crystal of N (0≦y<0.1). z Ga 1-z N (0≦z<0.1) is Al constituting the intermediate layer 52 as the base. y Ga 1-y In other words, the GaN constituting the C-GaN layer 51 on the intermediate layer 52 or the Al constituting the electron transport layer 6 is affected by the crystallinity of 0.5≦y≦1. z Ga 1-z N (0≦z<0.1) is Al constituting the intermediate layer 52. y Ga 1-y It grows epitaxially on the intermediate layer 52 so as to inherit the crystal structure of GaN (0.5≦y≦1). z Ga 1-z The lattice constant of N(0≦z<0.1) is Al y Ga 1-ySince the lattice constant of GaN is larger than that of AlN (0.5≦y≦1), the lattice constant of GaN and Al z Ga 1-z The lattice constant in the lateral direction in Fig. 1 for N(0≦z<0.1) is the same as that for typical (compressively strained) GaN and Al z Ga 1-z The lattice constant is smaller than N(0≦z<0.1). In other words, the C-GaN layer 51 or the electron transport layer 6 on the intermediate layer 52 contains compressive strain therein.

[0090] During the temperature drop after the formation of the C-GaN layer 51 and the electron transport layer 6, GaN and Al z Ga 1-z Due to the difference in the thermal expansion coefficient between N (0≦z<0.1) and Si, the C-GaN layer 51 and the electron transit layer 6 are subjected to stress from the underlying intermediate layer 52. This stress can cause the Si substrate 1 to warp and can cause cracks to occur in the C-GaN layer 51 and the electron transit layer 6. However, this stress is alleviated by compressive strain introduced into the C-GaN layer 51 or the electron transit layer 6 on the intermediate layer 52 when the C-GaN layer 51 and the electron transit layer 6 are formed. As a result, warping of the Si substrate 1 can be prevented, and cracks can be prevented from occurring in the C-GaN layer 51 or the electron transit layer 6.

[0091] Moreover, the compound semiconductor substrate CS1 includes the C-GaN layer 51, which has a breakdown voltage higher than that of GaN, the intermediate layer 52, and the first nitride semiconductor layer 4. As a result, the withstand voltage in the vertical direction of the compound semiconductor substrate can be improved.

[0092] According to the present embodiment, the compound semiconductor substrate CS1 includes the first nitride semiconductor layer 4 between the Si substrate 1 and the electron transit layer 6. Therefore, the lattice constant of Si and the Al of the electron transit layer 6 are z Ga 1-z The difference in lattice constant between the first nitride semiconductor layer 4 and AlN (0≦z<0.1) can be reduced. x Ga 1-x The lattice constant of N (0.1≦x≦1) is the same as that of Si and Al z Ga1-z This is because z has a value between the lattice constants of N (0≦z<0.1). As a result, it is possible to improve the crystal quality of the electron transit layer 6. In addition, it is possible to prevent the Si substrate 1 from warping, and to prevent cracks from occurring in the C-GaN layer 51 and the electron transit layer 6.

[0093] Furthermore, according to this embodiment, since the occurrence of warping of the Si substrate 1 and the occurrence of cracks in the electron transit layer 6 are suppressed as described above, the electron transit layer 6 can be made thicker.

[0094] Furthermore, the compound semiconductor substrate CS1 includes a SiC layer 2 as an underlayer of the electron transit layer 6. The lattice constant of SiC is smaller than that of Si. z Ga 1-z It is close to the lattice constant of N (0≦z<0.1). By forming the C-GaN layer 51 and the electron transit layer 6 on the SiC layer 2, the crystal quality of the C-GaN layer 51 and the electron transit layer 6 can be improved.

[0095] As described above, according to the present embodiment, by separating the functions of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the SiC layer 2, it is possible to enhance the effects of suppressing warpage of the Si substrate 1, suppressing cracks in the C-GaN layer 51 and the electron transit layer 6, improving the withstand voltage of the compound semiconductor substrate CS1, and improving the crystal quality of the C-GaN layer 51 and the electron transit layer 6. In particular, in the present embodiment, the use of the SiC layer 2 as an underlayer contributes greatly to improving the crystal quality of the electron transit layer 6.

[0096] According to this embodiment, the presence of the SiC layer 2 improves the crystal quality of the C-GaN layer 51 and the electron transit layer 6, and therefore the intermediate layer 52 in the second nitride semiconductor layer 5 can more efficiently suppress the occurrence of warping and cracks. Furthermore, the presence of the SiC layer 2 improves the crystal quality of the C-GaN layer 51, and therefore the C-GaN layer 51 and the electron transit layer 6 can be thickened, thereby further improving the withstand voltage. The performance of the HEMT can also be improved.

[0097] In this embodiment, the second nitride semiconductor layer 5 is one or more intermediate layers 52 formed in or on the C-GaN layer 51, and is made of Al y Ga 1-y The nitride semiconductor layer 51 includes an intermediate layer 52 made of N (0.5≦y≦1). The C-GaN layer 51 has at least one of a C concentration higher than the C concentration of the electron transit layer 6 and an Fe concentration higher than the Fe concentration of the electron transit layer 6. This can improve the insulation of the nitride semiconductor layer while suppressing the occurrence of warping and cracks.

[0098] According to this embodiment, in a compound semiconductor substrate (large-diameter compound semiconductor substrate) having a disk shape and a diameter of 100 mm to 200 mm, the amount of warpage defined below can be made to be 0 to 50 μm. Also, it is possible to prevent cracks from being included in the region on the upper surface of the compound semiconductor substrate other than the region that is 5 mm or less away from the outer peripheral edge. Furthermore, it is possible to prevent the upper surface of the compound semiconductor substrate from including any trace of melt-back etching.

[0099] Furthermore, by introducing a hydrocarbon as a C source gas when forming the C-GaN layer 51, the GaN growth temperature can be set high while the C-GaN layer 51 is formed. Since the GaN growth temperature is high, the quality of the C-GaN layer 51 is improved.

[0100] 3A and 3B are diagrams showing the two-dimensional growth of GaN that constitutes the C-GaN layer 51. Fig. 3(a) shows the growth when the GaN growth temperature is low, and Fig. 3(b) shows the growth when the GaN growth temperature is high.

[0101] Referring to FIG. 3(a), when the growth temperature of GaN is low, the two-dimensional growth (lateral direction in FIG. 3) of the C-GaN layer 51 is slow, so that defects DF such as pits present in the lower layer of the C-GaN layer 51 are not covered by the C-GaN layer 51, and the defects DF tend to spread into the interior of the C-GaN layer 51.

[0102] 3(b), in this embodiment, the growth temperature of GaN is high, which promotes two-dimensional growth of GaN, and defects DF such as pits that existed in the lower layer of the C-GaN layer 51 are covered by the C-GaN layer 51. As a result, the defect density of the C-GaN layer 51 can be reduced, and it is possible to prevent the defect DF from penetrating the compound semiconductor substrate in the vertical direction, thereby preventing a significant decrease in the breakdown voltage of the compound semiconductor substrate.

[0103] FIG. 4 is a plan view showing a configuration of a compound semiconductor substrate CS1 in the first embodiment of the present invention.

[0104] 4, the compound semiconductor substrate CS1 may have any planar shape. When the compound semiconductor substrate CS1 has a circular planar shape, the diameter of the compound semiconductor substrate CS1 is 6 inches or more. When viewed in a planar view, the center of the compound semiconductor substrate CS1 is defined as a center PT1, and a position 71.2 mm away from the center PT1 (corresponding to a position 5 mm away from the outer circumferential edge of a substrate with a diameter of 6 inches) is defined as an edge PT2.

[0105] The improved quality of the C-GaN layer 51 improves the in-plane uniformity of the film thickness of the C-GaN layer 51, and improves the in-plane uniformity of the C concentration of the C-GaN layer 51. Furthermore, the intrinsic breakdown voltage value in the vertical direction of the compound semiconductor substrate CS1 improves, and the defect density of the C-GaN layer 51 decreases. As a result, the in-plane uniformity of the vertical current-voltage characteristics can be improved.

[0106] Specifically, if the carbon concentration at the center position in the depth direction (vertical direction in FIG. 1) at the center PT1 of the C-GaN layer 51 is defined as concentration C1, and the carbon concentration at the center position in the depth direction at the edge PT2 of the C-GaN layer 51 is defined as concentration C2, then the concentration error ΔC, expressed as ΔC (%) = |C1-C2|×100 / C1, is between 0 and 50%, and preferably between 0 and 33%.

[0107] Furthermore, when the thickness of the center PT1 in the C-GaN layer 51 is defined as W1 and the thickness of the edge PT2 in the C-GaN layer 51 is defined as W2, the thickness error ΔW expressed as ΔW (%) = |W1-W2| × 100 / W1 is greater than 0 and less than or equal to 8%, and preferably greater than 0 and less than or equal to 4%.

[0108] The compound semiconductor substrate CS1 has an intrinsic breakdown voltage in the vertical direction of 1200 V or more and 1600 V or less. The defect density in the center PT1 of the C-GaN layer 51 that causes dielectric breakdown at a voltage value of 80% or less of the intrinsic breakdown voltage is greater than 0 and less than 100 defects / cm. 2 or less, preferably greater than 0 and 2 particles / cm 2 The defect density at the edge PT2 of the C-GaN layer 51 that causes dielectric breakdown at a voltage value equal to or less than 80% of the intrinsic breakdown voltage is greater than 0 and is equal to or less than 7 defects / cm. 2 or less, preferably greater than 0 and 2 particles / cm 2 The following is the result.

[0109] [Second embodiment]

[0110] FIG. 5 is a cross-sectional view showing configurations of a compound semiconductor device DC2 and a compound semiconductor substrate CS2 according to the second embodiment of the present invention.

[0111] 5, a compound semiconductor device DC2 (an example of a compound semiconductor device) in this embodiment includes a compound semiconductor substrate CS2 (an example of a compound semiconductor substrate) instead of the compound semiconductor substrate CS1. The compound semiconductor substrate CS2 is different from the compound semiconductor substrate CS1 in the internal configuration of the second nitride semiconductor layer 5. Specifically, the second nitride semiconductor layer 5 in this embodiment includes only one intermediate layer 52. The intermediate layer 52 is formed on a C-GaN layer 51. The intermediate layer 52 is the uppermost layer among the layers constituting the second nitride semiconductor layer 5, and is in contact with the electron transit layer 6. In order to compensate for the reduction in thickness W caused by the reduction in the number of layers constituting the second nitride semiconductor layer 5, the thickness of the electron transit layer 6 is made thicker than that of the electron transit layer in the first embodiment.

[0112] The configurations of the compound semiconductor device DC2 and the compound semiconductor substrate CS2 other than those described above are similar to the configurations of the compound semiconductor device DC1 and the compound semiconductor substrate CS1 in the first embodiment, so the same components are given the same symbols and their descriptions will not be repeated.

[0113] According to this embodiment, it is possible to obtain the same effects as those of the first embodiment. In addition, since the number of layers constituting the second nitride semiconductor layer 5 is reduced, the compound semiconductor substrate and the compound semiconductor device have simple configurations.

[0114] [Modifications of the first and second embodiments]

[0115] In this modification, a configuration of a modification of the first nitride semiconductor layer 4 of each of the compound semiconductor substrates CS1 and CS2 will be described.

[0116] FIG. 6 is a diagram showing the distribution of the Al composition ratio inside the first nitride semiconductor layer 4 in the first modified example of the first and second embodiments of the present invention.

[0117] Referring to FIG. 6, the first nitride semiconductor layer 4 in this modification example includes an AlN layer 40, an AlGaN layer 4a, an AlN layer 44, and an AlGaN layer 4b. The AlN layer 40 is in contact with the SiC layer 2 and is formed on the SiC layer 2.

[0118] The AlGaN layer 4a is in contact with the AlN layer 40 and is formed on the AlN layer 40. The AlGaN layer 4a is composed of an Al 0.75 Ga 0.25 N layer 41 (an AlGaN layer with an Al composition ratio of 0.75). The Al composition ratio inside the AlGaN layer 4a is constant.

[0119] The AlN layer 44 is in contact with the AlGaN layer 4a and is formed on the AlGaN layer 4a. The AlGaN layer 4b is in contact with the AlN layer 44 and is formed on the AlN layer 44. The Al composition ratio inside the AlGaN layer 4b decreases from the bottom to the top. The AlGaN layer 4b is composed of an Al 0.5 Ga 0. 5 N layer 42 (an AlGaN layer with an Al composition ratio of 0.5) and an Al 0.25 Ga 0.75 N layer 43 (an AlGaN layer with an Al composition ratio of 0.25). The Al 0.5 Ga 0.5 N layer 42 is in contact with the AlN layer 44 and is formed on the AlN layer 44. The Al 0.25 Ga 0.75 N layer 43 is in contact with the Al 0.5 Ga 0.5 N layer 42 and is formed on the Al 0.5 Ga 0.5 N layer 42.

[0120] Each of the AlN layers 40 and 44, the Al 0.75 Ga 0.25 N layer 41, and the Al 0.5 Ga 0. 5 N layer 42 corresponds to the first region of the first nitride semiconductor layer 4 composed of Al x Ga 1-x N (0.4 < x ≦ 1). The Al 0.25 Ga 0.75The N layer 43 is Al x Ga 1-x This corresponds to the second region of the first nitride semiconductor layer 4 consisting of N (0.1≦x≦0.4).

[0121] FIG. 7 is a diagram showing the distribution of the Al composition ratio inside the first nitride semiconductor layer 4 in the second modification of the first and second embodiments of the present invention.

[0122] 7, the first nitride semiconductor layer 4 in this modification includes an AlN layer 40, an AlGaN layer 4a, an AlN layer 44, and an AlGaN layer 4b. The AlN layer 40 is in contact with the SiC layer 2 and is formed on the SiC layer 2.

[0123] The AlGaN layer 4a is in contact with the AlN layer 40 and is formed on the AlN layer 40. The Al composition ratio in the AlGaN layer 4a decreases from the bottom to the top. 0.75 Ga 0.25 N layer 41 (AlGaN layer with an Al composition ratio of 0.75) and Al 0.5 Ga 0.5 The AlGaN layer 42 has an Al composition ratio of 0.5. 0.75 Ga 0.25 The N layer 41 is in contact with the AlN layer 40 and is formed on the AlN layer 40. 0.5 Ga 0.5 The N layer 42 is Al 0.75 Ga 0.25 In contact with the N layer 41, Al 0.75 Ga 0.25 It is formed on the N layer 41.

[0124] The AlN layer 44 is in contact with the AlGaN layer 4a and is formed on the AlGaN layer 4a. The AlGaN layer 4b is in contact with the AlN layer 44 and is formed on the AlN layer 44. The AlGaN layer 4b is 0.25 Ga 0.75 The AlGaN layer 4b is made of an N layer 43 (an AlGaN layer having an Al composition ratio of 0.25). The Al composition ratio in the interior of the AlGaN layer 4b is constant.

[0125] AlN layers 40 and 44, Al 0.75 Ga 0.25 N layer 41, and Al 0.5 Ga 0. 5 Each of the N layers 42 is equivalent to a first region of the first nitride semiconductor layer 4 made of Al x Ga 1-x N (0.4 < x ≦ 1). Al 0.25 Ga 0.75 The N layer 43 is equivalent to a second region of the first nitride semiconductor layer 4 made of Al x Ga 1-x N (0.1 ≦ x ≦ 0.4).

[0126] In addition, the configurations other than those described above in each of the compound semiconductor substrates of the first and second modified examples are the same as those in the case of the above-described embodiment. Therefore, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

[0127] The AlN layer 44 functions to cause compressive strain in the AlGaN layer 4b. By providing the AlN layer 44 as in the first and second modified examples, warping and cracking can be further suppressed.

[0128] [Third Embodiment]

[0129] FIG. 8 is a cross-sectional view showing the configurations of the compound semiconductor device DC3 and the compound semiconductor substrate CS3 in the third embodiment of the present invention.

[0130] Referring to FIG. 8, the compound semiconductor device DC3 (an example of a compound semiconductor device) in the present embodiment includes a compound semiconductor substrate CS3 (an example of a compound semiconductor substrate) instead of the compound semiconductor substrate CS1. In the compound semiconductor substrate CS3, the first nitride semiconductor layer 4 includes an AlN layer 40, an Al 0.75 Ga 0.25 N layer 41, an AlN layer 44, an Al 0.5 Ga 0.5 N layer 42, an AlN layer 45, an Al 0.25 Ga 0.75It includes an AlN layer 43. The AlN layer 40 is in contact with the SiC layer 2 and is formed on the SiC layer 2. Al 0.75 Ga 0.25 The AlGaN layer 41 is in contact with the AlN layer 40 and is formed on the AlN layer 40. The AlN layer 44 is Al 0.75 Ga 0.25 in contact with the AlGaN layer 41 and is Al 0.75 Ga 0.25 formed on the AlGaN layer 41. Al 0.5 Ga 0.5 The AlGaN layer 42 is in contact with the AlN layer 44 and is formed on the AlN layer 44. The AlN layer 45 is Al 0.5 Ga 0.5 in contact with the AlGaN layer 42 and is Al 0.5 Ga 0.5 formed on the AlGaN layer 42. Al 0.25 Ga 0.75 The AlN layer 43 is in contact with the AlN layer 45 and is formed on the AlN layer 45.

[0131] Each of the AlN layers 40, 44, and 45, the Al 0.75 Ga 0.25 GaN layer 41, and the Al 0.5 Ga 0. 5 GaN layer 42 corresponds to a first region of the first nitride semiconductor layer 4 made of Al x Ga 1-x N (0.4 < x ≤ 1). Al 0.25 Ga 0.75 The AlN layer 43 corresponds to a second region of the first nitride semiconductor layer 4 made of Al x Ga 1-x N (0.1 ≤ x ≤ 0.4).

[0132] Note that the configurations of the compound semiconductor device DC3 and the compound semiconductor substrate CS3 other than those described above are the same as those of the compound semiconductor device DC1 and the compound semiconductor substrate CS1 in the first embodiment. Therefore, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

[0133] According to this embodiment, the same effects as those of the first embodiment can be obtained.

[0134] [Fourth embodiment]

[0135] FIG. 9 is a cross-sectional view showing the configurations of a compound semiconductor device DC4 and a compound semiconductor substrate CS4 according to the fourth embodiment of the present invention.

[0136] 9, a compound semiconductor device DC4 (an example of a compound semiconductor device) in the present embodiment includes a compound semiconductor substrate CS4 (an example of a compound semiconductor substrate) instead of the compound semiconductor substrate CS1. In the compound semiconductor substrate CS4, the first nitride semiconductor layer 4 has a configuration similar to that of the first nitride semiconductor layer of the compound semiconductor substrate CS3 in the third embodiment. Specifically, the first nitride semiconductor layer 4 includes an AlN layer 40 and an Al 0.75 Ga 0.25 The N layer 41, the AlN layer 44, and the Al 0.5 Ga 0.5 The AlN layer 42, the AlN layer 45, and the Al 0.25 Ga 0.75 The AlN layer 43 is in contact with the SiC layer 2 and is formed on the SiC layer 2. 0.75 Ga 0.25 The N layer 41 is in contact with the AlN layer 40 and is formed on the AlN layer 40. The AlN layer 44 is 0.75 Ga 0.25 In contact with the N layer 41, Al 0.75 Ga 0.25 It is formed on the N layer 41. 0.5 Ga 0.5 The N layer 42 is in contact with the AlN layer 44 and is formed on the AlN layer 44. The AlN layer 45 is 0.5 Ga 0.5 In contact with the N layer 42, Al 0.5 Ga 0.5 It is formed on the N layer 42. 0.25 Ga 0.75 The N layer 43 is in contact with the AlN layer 45 and is formed on the AlN layer 45 .

[0137] AlN layers 40, 44, and 45, Al 0.75 Ga 0.25The N layer 41, and Al 0.5 Ga 0. 5 Each of the N layers 42 is Al x Ga 1-x corresponds to the first region of the first nitride semiconductor layer 4 made of Al 0.25 Ga 0.75 N (0.4 < x ≦ 1). Al 0.25 Ga 0.75 The N layer 43 is Al x Ga 1-x corresponds to the second region of the first nitride semiconductor layer 4 made of Al x Ga 1-x N (0.1 ≦ x ≦ 0.4).

[0138] Also, in the compound semiconductor substrate CS4, the second nitride semiconductor layer 5 has the same configuration as the second nitride semiconductor layer of the compound semiconductor substrate CS2 in the second embodiment. Specifically, the second nitride semiconductor layer 5 includes only one intermediate layer 52. The intermediate layer 52 is formed on the C-GaN layer 51. The intermediate layer 52 is the uppermost layer among the layers constituting the second nitride semiconductor layer 5 and is in contact with the electron traveling layer 6.

[0139] In addition, since the configurations of the compound semiconductor device DC4 and the compound semiconductor substrate CS4 other than those described above are the same as the configurations of the compound semiconductor device DC1 and the compound semiconductor substrate CS1 in the first embodiment, the same members are denoted by the same reference numerals and the description thereof will not be repeated.

[0140] According to the present embodiment, the same effects as those of the first embodiment can be obtained.

[0141] [Examples]

[0142] As a first example, the inventors of the present application manufactured each of Samples 1 to 3 having the configurations described below as samples.

[0143] Sample 1 (Example of the present invention): Using a 6-inch Si substrate manufactured by the Cz method, a structure similar to the compound semiconductor substrate CS3 shown in FIG. 8 was manufactured. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron traveling layer 6 was set to 7 μm.

[0144] Sample 2 (example of the present invention): Using a 6-inch Si substrate produced by the Cz method, a structure similar to that of the compound semiconductor substrate CS3 shown in Fig. 8 was manufactured. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transport layer 6 was set to 8 µm.

[0145] Sample 3 (example of the present invention): Using a 6-inch Si substrate produced by the Cz method, a structure similar to that of the compound semiconductor substrate CS4 shown in Fig. 9 was manufactured. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transport layer 6 was set to 8 µm.

[0146] Sample 4 (Comparative Example): A structure similar to that of the compound semiconductor substrate CS3 shown in Fig. 8 was manufactured, except that a 6-inch Si substrate produced by the Fz method was used. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transit layer 6 was set to 7 µm.

[0147] Sample 5 (Comparative Example): A structure similar to that of the compound semiconductor substrate CS3 shown in Fig. 8 was manufactured, except that a 6-inch Si substrate produced by the Fz method was used. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transit layer 6 was set to 8 µm.

[0148] Sample 6 (Comparative Example): A structure similar to that of the compound semiconductor substrate CS4 shown in Fig. 9 was manufactured, except that a 6-inch Si substrate produced by the Fz method was used. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transit layer 6 was set to 8 µm.

[0149] Sample 7 (Comparative Example): A structure similar to that of the compound semiconductor substrate CS3 shown in FIG. 8 was manufactured, except that the SiC layer 2 was omitted. For this comparative example, a 6-inch Si substrate manufactured by the Cz method was used. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transit layer 6 was set to 7 μm.

[0150] Sample 8 (Comparative Example): A structure similar to that of the compound semiconductor substrate CS3 shown in FIG. 8 was manufactured, except that the SiC layer 2 was omitted. For this comparative example, a 6-inch Si substrate manufactured by the Cz method was used. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transit layer 6 was set to 8 μm.

[0151] Sample 9 (Comparative Example): A structure similar to that of the compound semiconductor substrate CS4 shown in FIG. 9 was manufactured, except that the SiC layer 2 was omitted. For this comparative example, a 6-inch Si substrate manufactured by the Cz method was used. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transit layer 6 was set to 8 μm.

[0152] The inventors of the present application performed CV measurements on each of the obtained samples 1 to 3 using a surface two-tip mercury probe as a surface measurement. Then, from the obtained CV data, the depth direction distribution of the donor ion concentration in each of samples 1 to 3 was obtained. For the CV measurements, a "CV92M Manual Mercury Prober (registered trademark)" manufactured by "Four Dimensions (registered trademark)" and an "E4980A LCR Meter (registered trademark)" manufactured by "Keysight Technologies (registered trademark)" were used. As a result, for all of samples 1 to 3, a 2×10 14 pieces / cm 3 Sufficiently resistive or semi-insulating regions were identified in the C-GaN layer 51 (main layer) having the following donor ion concentrations:

[0153] The inventors of the present application measured the amount of warpage for each of the obtained Samples 1 to 6. To measure the amount of warpage, a flatness measuring instrument called "Flatmaster" manufactured by "Corning Tropel (registered trademark)" was used. The amount of warpage was calculated according to the SORI standard. Specifically, a least-squares plane of the upper surface of the sample was calculated (defined). Then, the sum of the absolute value of the distance from the calculated least-squares plane to the highest point on the upper surface of the sample and the absolute value of the distance from the calculated least-squares plane to the lowest point on the upper surface of the sample was calculated as the amount of warpage.

[0154] Fig. 10 is a diagram showing the distribution of the amount of warping on the upper surface of each of samples 1 to 3 in the first example of the present invention. Fig. 10(a) is a diagram showing the distribution of the amount of warping on the upper surface of sample 1. Fig. 10(b) is a diagram showing the distribution of the amount of warping on the upper surface of sample 2. Fig. 10(c) is a diagram showing the distribution of the amount of warping on the upper surface of sample 3.

[0155] Referring to FIG. 10, the amount of warpage of sample 1 was 34.260 μm. The amount of warpage of sample 2 was 13.461 μm. The amount of warpage of sample 3 was 19.526 μm. The inventors of the present application manufactured a plurality of samples as sample 1, and calculated the amount of warpage of each of the obtained plurality of samples 1. The inventors of the present application manufactured a plurality of samples as sample 2, and calculated the amount of warpage of each of the obtained plurality of samples 2. Furthermore, the inventors of the present application manufactured a plurality of samples as sample 3, and calculated the amount of warpage of each of the obtained plurality of samples 3. As a result, the amount of warpage of each of samples 1 to 3 was 0 or more and 50 μm or less. In contrast, the amount of warpage of each of samples 4 to 6 exceeded 50 μm. From this result, it can be seen that the amount of warpage of samples 1 to 3 is suppressed more than that of samples 4 to 6.

[0156] Next, the inventors of the present application confirmed the occurrence of cracks and the occurrence of melt-back etching for each of the obtained samples 1 to 3 and 7 to 9. A laser beam was irradiated onto the upper surface of the sample, and a laser scattering image was created based on the scattered light received. From the created laser scattering image, the occurrence of cracks and the occurrence of melt-back etching were confirmed. A "CANDELA (registered trademark)" manufactured by "KLA-TENCOR (registered trademark)" was used to create the laser scattering image.

[0157] Fig. 11 shows laser scattering images of the upper surface of each of samples 1 and 7 in the first embodiment of the present invention. Fig. 10(a) shows a laser scattering image of the upper surface of sample 1. Fig. 10(b) shows a laser scattering image of the upper surface of sample 7.

[0158] Referring to FIG. 11, the thickness W of each of Samples 1 and 7 is 7 μm. Slight cracks were observed in the region near the outer periphery of the upper surface of Sample 1 (the region 5 mm or less away from the outer periphery). No cracks were observed in other regions. No traces of melt-back etching were observed on the upper surface of Sample 1. Meanwhile, a huge crack with a length of 10 mm or more was observed in the region near the outer periphery of the upper surface of Sample 7.

[0159] Fig. 12 shows laser scattering images of the top surface of each of samples 2 and 8 in the first embodiment of the present invention. Fig. 12(a) is a laser scattering image of the top surface of sample 2. Fig. 12(b) is a laser scattering image of the top surface of sample 8.

[0160] 12, the thickness W of each of Samples 2 and 8 is 8 μm. Slight cracks were observed in the region near the outer periphery of the upper surface of Sample 2 (the region 5 mm or less away from the outer periphery). No cracks were observed in other regions. On the other hand, large cracks were observed over the entire upper surface of Sample 8.

[0161] Figure 13 is a partial enlarged view of the laser scattering image shown in Figure 12. Figure 13(a) is a partial enlarged view of the laser scattering image shown in Figure 12(a). Figure 13(b) is a partial enlarged view of the laser scattering image shown in Figure 12(b).

[0162] Referring to Fig. 13, no traces of melt-back etching were found on the top surface of Sample 2. On the other hand, metallized Si was exposed at the bottom of a crack near the outer periphery of the top surface of Sample 8 (the part indicated by the arrow in Fig. 13(b)). The metallized Si is a trace of melt-back etching.

[0163] Fig. 14 shows laser scattering images of the upper surface of each of samples 3 and 9 in the first embodiment of the present invention. Fig. 14(a) is a laser scattering image of the upper surface of sample 3. Fig. 14(b) is a laser scattering image of the upper surface of sample 9.

[0164] Referring to FIG. 14, the thickness W of each of Samples 3 and 9 is 8 μm. Slight cracks were observed in the region near the outer peripheral edge of the upper surface of Sample 3 (the region 5 mm or less away from the outer peripheral edge). No cracks were observed in other regions. No traces of melt-back etching were observed on the upper surface of Sample 3. On the other hand, large cracks were observed all over the upper surface of Sample 9.

[0165] 11 to 14, it can be seen that, even when the thickness W is 6 μm or more, Samples 1 to 3 can prevent the occurrence of cracks in regions other than the region that is 5 mm or less away from the outer peripheral edge of the upper surface of the compound semiconductor substrate. It can also be seen that, in Samples 1 to 3, the occurrence of melt-back etching can be prevented over the entire upper surface of the compound semiconductor substrate.

[0166] Next, the inventors of the present application fabricated a compound semiconductor device DC4 using the obtained sample 3. Then, the cutoff frequency of the fabricated compound semiconductor device DC4 was measured at room temperature. Here, the composition of the barrier layer 8 was Al 0.26 Ga 0.74 The result was N.

[0167] The compound semiconductor device DC4 was fabricated by the following method. First, the peripheral region of the device was isolated. During isolation, the sample 3 was deep mesa etched to a depth of 300 nm from its surface using BCl3 plasma-based reactive ion etching (RIE).

[0168] Subsequently, a Ti / Al / Ni / Au metal stack was deposited using ultraviolet (UV) photolithography and electron beam evaporation, thereby forming the source electrode 11 and the drain electrode 12. Ohmic contacts between each of the source electrode 11 and the drain electrode 12 and the surface of the sample 3 were created by performing rapid thermal annealing (RTA) at 850°C for 30 seconds in a N2 atmosphere. The gate electrode 13, which is a Schottky electrode, was formed by depositing a Ni / Au metal stack using electron beam evaporation.

[0169] The gate pad was formed in a region that had been deep mesa etched to a depth of 300 nm from the surface of sample 3. Therefore, the effective thickness of the nitride layer corresponding to the S-parameter measurement of the open gate pad described later was 7.7 μm.

[0170] When measuring the cutoff frequency, a device in which two gate electrodes 13 were formed in parallel was used. The gate length of the gate electrode 13 was 2 μm, and the gate width was 50 μm. The cutoff frequency was measured using a P5400A Vector Network Analyzer (registered trademark) manufactured by Keysight Technologies (registered trademark). This measurement system was accurately calibrated using an open-short-load-through calibration standard.

[0171] The cutoff frequency was measured in the frequency range of 0.5 to 20 GHz by applying a drain voltage of 10 V and a gate voltage of -0.8 V to turn the device on. This resulted in the frequency dependence curve of the current gain (|H21|). Then, |H21| versus the logarithm of the frequency was plotted. 2 The data plotted with the values ​​of |H21| was extrapolated with a straight line, and the frequency at which |H21|=0 dB was determined as the cutoff frequency.

[0172] FIG. 15 is a diagram showing the relationship between the cutoff frequency and the gate length of the compound semiconductor device DC4 fabricated using the sample 3 in the first embodiment of the present invention. FIG. 15 also shows the relationship between the cutoff frequency and the gate length of a conventional compound semiconductor device for high frequency applications. The circle plot in FIG. 15 shows the relationship between the cutoff frequency and the gate length of the compound semiconductor device DC4 fabricated using the sample 3. The diamond plot in FIG. 15 shows the relationship between the cutoff frequency and the gate length of the HEMT1010 shown in FIG. 22. The triangle plot in FIG. 15 shows the relationship between the cutoff frequency and the gate length of the HEMT1020 shown in FIG. 23. The square plot in FIG. 15 shows the relationship between the cutoff frequency and the gate length of the HEMT1020 shown in FIG. 23, in which a thin SiC layer is added between the Fz-Si substrate 1061 and the nitride buffer layer 1052.

[0173] 15, a straight line L is drawn connecting multiple plots showing the relationship between cutoff frequency and gate length of conventional compound semiconductor devices for high frequency applications. The plot showing the relationship between cutoff frequency and gate length of compound semiconductor device DC4 fabricated using sample 3 is on straight line L. This result shows that compound semiconductor device DC4 has high frequency characteristics comparable to those of conventional compound semiconductor devices for high frequency applications.

[0174] Next, the inventors of the present application fabricated compound semiconductor devices DC3 and DC4 using samples 2 and 3, respectively, in the same manner as in the case of measuring the cutoff frequency (FIG. 15). Then, the temperature change of the small signal characteristics of each of the fabricated compound semiconductor devices DC3 and DC4 was evaluated. Specifically, the S-parameter S11 for the gate open pad structure was measured at temperatures of 25° C., 50° C., 75° C., 100° C., and 125° C. The S-parameter was measured using a P5400A Vector Network Analyzer (registered trademark) manufactured by Keysight Technologies (registered trademark). This measurement system was accurately calibrated using an open-short-load-through calibration standard.

[0175] When measuring the S parameter S11, a device with no gate electrode on the electron transport layer and only a gate pad formed thereon, i.e., a device with a gate open pad structure, was used. The area of ​​the gate pad region was 4.9 × 10 -5 cm 2 It was decided.

[0176] The gate pad was formed in a region that had been deep mesa etched to a depth of 300 nm from the surface of sample 3. Therefore, the effective thickness of the nitride layer corresponding to the S-parameter measurement of the open gate pad was 7.7 μm.

[0177] Fig. 16 is a diagram showing frequency characteristics of the S parameter S11 of sample 2 in the first embodiment of the present invention. Fig. 17 is a diagram showing frequency characteristics of the S parameter S11 of sample 3 in the first embodiment of the present invention. Note that Figs. 16 and 17 only show the S parameter S11 at temperatures of 25°C and 125°C.

[0178] 16 and 17, using a device having the above-mentioned gate open pad structure, a frequency dependency curve of the S parameter S11 was obtained in the frequency range of 0.5 to 20 GHz and plotted on a Smith chart.

[0179] 16 and 17, the S parameter S11 of samples 2 and 3 showed almost constant behavior regardless of temperature. This result shows that compound semiconductor devices DC3 and DC4, unlike the conventional HEMT1020 shown in Figure 23, have low attenuation of high-frequency signals even at high temperatures, just as they do at room temperature.

[0180] Furthermore, by fitting the data in Figure 17 with a simple RC series circuit, the pad capacitance and resistance were measured to be 0.059 pF and 9.5 Ω, respectively. The pad resistance of 9.5 Ω is 4.9 × 10 -5 cm 2When normalized by , the resistance per unit area is sufficiently high. This shows that in sample 3, the parasitic conductive elements that lead to degradation of high frequency characteristics are sufficiently suppressed.

[0181] In addition, the capacitance of the pad was normalized by the area of ​​the gate pad region, and the normalized value was used to estimate the thickness of the highly insulating part of the nitride as the thickness of the dielectric layer of the pad capacitance. As a result, the estimated value was 7.1 μm. This value is close to the effective nitride layer thickness of 7.7 μm corresponding to the S-parameter measurement of the gate pad. This shows that most of the nitride layer in sample 3 maintains the properties of a dielectric layer (i.e., semi-insulating or sufficiently highly resistive).

[0182] Thus, when a thick nitride layer is formed on a thick SiC layer in the configuration of the present application, most of the nitride layer can maintain the properties of a dielectric layer, i.e., semi-insulating or sufficiently highly resistive. Furthermore, by providing a SiC layer below the nitride layer, the thickness of the nitride layer can be made sufficiently thick to reduce degradation of high frequency characteristics. As a result, the high frequency performance of the device can be improved. Furthermore, attenuation of high frequency signals can be reduced even at high temperatures, similar to that at room temperature.

[0183] As a second example, the inventors of the present application manufactured a structure similar to that of the compound semiconductor substrate CS3 shown in Fig. 8 under two different manufacturing conditions to obtain samples 10 and 11. Samples 10 and 11 were manufactured using a 6-inch Si substrate prepared by the Cz method.

[0184] Sample 10: When each of the C-GaN layers 51a, 51b, and 51c was formed, the film formation temperature was set to a high temperature (a temperature approximately 200°C lower than the growth temperature of the GaN layer not doped with C) and a hydrocarbon was introduced as a C source gas. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transport layer 6 was set to 7 μm.

[0185] Sample 11: When each of the C-GaN layers 51a, 51b, and 51c was formed, the film formation temperature was set to a low temperature (a temperature about 300°C lower than the growth temperature of the GaN layer not doped with C) and no C source gas was introduced. The total thickness W of the first nitride semiconductor layer 4, the second nitride semiconductor layer 5, and the electron transport layer 6 was set to 7 μm.

[0186] The inventors of the present application then visually inspected the compound semiconductor substrate CS3 for the presence or absence of cracks, and found that neither Samples 10 nor 11 had any cracks.

[0187] Next, the inventors of the present application confirmed by observation with an optical microscope whether melt-back etching (a phenomenon in which crystals are altered by a reaction between Si and Ga) occurred on the Si substrate 1 of the compound semiconductor substrate CS3. As a result, melt-back etching did not occur in either sample 10 or 11 (both samples 10 and 11 were melt-back free over the entire substrate surface).

[0188] Next, the inventors of the present application measured the carbon concentration distribution in the depth direction at the center PT1 and the carbon concentration distribution in the depth direction at the edge PT2 for each of the C-GaN layers 51a, 51b, and 51c of the compound semiconductor substrate CS3. This measurement was performed using SIMS (Secondary Ion Mass Spectrometry). Next, based on the measured carbon concentration distribution, a concentration C1, which is the carbon concentration at the center position in the depth direction at the center PT1, and a concentration C2, which is the carbon concentration at the center position in the depth direction at the edge PT2, were calculated. Next, based on the calculated concentrations C1 and C2, a concentration error ΔC expressed as ΔC (%) = |C1-C2|×100 / C1 was calculated.

[0189] FIG. 18 is a diagram showing values ​​of concentration error ΔC calculated in the second embodiment of the present invention.

[0190] 18, in sample 10, the range of carbon concentration in the depth direction at the center PT1 of each of C-GaN layers 51a, 51b, and 51c is 4×1018 pieces / cm 2 8×10 or more 18 pieces / cm 2 The carbon concentration range in the depth direction at edge PT2 is 4.3×10 18 pieces / cm 2 More than 7×10 18 pieces / cm 2 In sample 10, the carbon concentration at the center PT1 and the carbon concentration at the edge PT2 were approximately the same value, and the concentration errors ΔC of the C-GaN layers 51a, 51b, and 51c were 33%, 21%, and 0%, respectively. The inventors of the present application manufactured a plurality of samples 10 and measured the concentration error ΔC of each of the obtained samples 10 by the above-mentioned method. As a result, the concentration error ΔC of each sample 10 was within the range of 0 to 50%.

[0191] On the other hand, in sample 11, the range of carbon concentration in the depth direction at the center PT1 of each of the C-GaN layers 51a, 51b, and 51c is 5×10 18 pieces / cm 2 More than 1.5 x 10 19 pieces / cm 2 The range of carbon concentration in the depth direction at edge PT2 is 2.3×10 19 pieces / cm 2 More than 4.2 x 10 19 pieces / cm 2 In sample 11, the carbon concentration at the edge PT2 was higher than the carbon concentration at the center PT1, and the concentration errors ΔC of the C-GaN layers 51a, 51b, and 51c were 448%, 312%, and 258%, respectively.

[0192] From the above results, it is found that in Sample 10, the in-plane uniformity of the carbon concentration in the C-GaN layer is improved compared to Sample 11.

[0193] Next, the inventors measured the thickness W1 at the center PT1 and the thickness W2 at the edge PT2 for each of the C-GaN layers 51a, 51b, and 51c of the compound semiconductor substrate CS3. This measurement was performed by observing the cross section of the compound semiconductor substrate CS3 using a transmission electron microscope (TEM). Next, based on the measured thicknesses W1 and W2, a thickness error ΔW expressed as ΔW(%)=|W1-W2|×100 / W1 was calculated.

[0194] FIG. 19 is a diagram showing values ​​of film thickness error ΔW calculated in the second embodiment of the present invention.

[0195] 19, in sample 10, the thickness errors ΔW of C-GaN layers 51a, 51b, and 51c were 3.9%, 1.8%, and 1.2%, respectively, all of which were small values. The inventors of the present application manufactured a plurality of samples 10, and measured the thickness error ΔW of each of the obtained samples 10 by the above-mentioned method. As a result, the thickness error ΔW of each of samples 10 was in the range of more than 0 and 8% or less.

[0196] On the other hand, in sample 11, the thickness errors ΔW of the C-GaN layers 51a, 51b, and 51c were 9%, 11%, and 11%, respectively, all of which were large values.

[0197] From the above results, it is found that in Sample 10, the in-plane uniformity of the film thickness of the C-GaN layer is improved compared to Sample 11.

[0198] Next, the inventors of the present application measured the intrinsic breakdown voltage of each of Samples 10 and 11. The measurement of the intrinsic breakdown voltage was performed in the following manner.

[0199] FIG. 20 is a cross-sectional view showing a method for measuring the intrinsic breakdown voltage in the second embodiment of the present invention.

[0200] 20, a compound semiconductor substrate CS3 as a sample to be measured was fixed on a copper plate 22 attached to a glass plate 21. An electrode 23 made of Al was provided on barrier layer 8 of the fixed compound semiconductor substrate CS3 so as to be in contact with barrier layer 8.

[0201] An electrode having a sufficiently small area (specifically, an electrode having a diameter of 0.1 cm) was used as the electrode 23, and the electrode 23 was successively brought into contact with four different positions on the surface of the barrier layer 8 of the compound semiconductor substrate CS3, and the density of the current (current flowing vertically through the sample) flowing between the copper plate 22 and the electrode 23 when the electrode 23 was brought into contact with each position was measured. The measured current density was 1×10 -1 A / mm 2 When the voltage reached 100 V, it was deemed that the sample had undergone dielectric breakdown, and the voltage between the copper plate 22 and the electrode 23 at this time was measured. The highest and lowest values ​​of the four voltages obtained were excluded, and the average of the remaining two values ​​was taken as the intrinsic breakdown voltage. A number of samples were prepared as sample 10, and the intrinsic breakdown voltage of each sample was measured. As a result, the intrinsic breakdown voltage of sample 10 was always between 1200V and 1600V.

[0202] Furthermore, the inventors of the present application measured the defect density of the GaN layer of compound semiconductor substrate CS3 (any of GaN layers 51a, 51b, and 51c) by the following method. First, electrode 23 was brought into contact with five different positions in the vicinity of center PT1 of the surface of barrier layer 8 of compound semiconductor substrate CS3 in sequence, and the density of the current (current flowing vertically through the sample) flowing between copper plate 22 and electrode 23 when electrode 23 was brought into contact with each position was measured. When the measured current density was 1×10 -1 A / mm 2 When the dielectric breakdown voltage reached 100%, the sample was deemed to have broken down, and the voltage between the copper plate 22 and the electrode 23 at this time was taken as the dielectric breakdown voltage of the center PT1. The position where the measured dielectric breakdown voltage was 80% or less of the intrinsic dielectric breakdown voltage was then determined to be the position where a defect existed. The ratio of the number of positions where defects existed to the five positions where the dielectric breakdown voltage was measured was calculated as the defect density D of the center PT1.

[0203] The above calculation of the defect density D of the center PT1 was carried out for four different areas S (0.283 cm 2 , 0.126cm 2 , 0.031cm 2 , 0.002cm 2 As a result, four pairs of electrode area S and defect density D at the center PT1 were obtained.

[0204] Next, the yield Y for each of the four different areas S was calculated using equation (1), which is a general Poisson equation that shows the relationship between the yield Y, the electrode area S, and the defect density D.

[0205] Y = exp(-S × D) (1)

[0206] Next, the electrode with area S for which the calculated yield Y was closest to 50% was determined to be the optimal electrode for calculating the defect density, and the defect density D corresponding to the area S of the optimal electrode was adopted as the defect density of the center PT1.

[0207] In addition, the position where the electrode 23 was in contact was changed to five different positions near the edge PT2 of the surface of the barrier layer 8, and the defect density at the edge PT2 was measured in the same manner as described above.

[0208] FIG. 21 is a diagram showing values ​​of defect density measured in the second embodiment of the present invention.

[0209] Referring to FIG. 21, the defect density at the center PT1 of sample 10 is 1.8 / cm 2 The defect density of the edge PT2 of sample 10 is 1.8 / cm 2 The inventors of the present application manufactured a number of samples 10 and measured the defect density at the center PT1 and edge PT2 of each of the obtained samples 10 by the above-mentioned method. As a result, the defect density of each sample 10 was greater than 0 and was 7 / cm. 2 The defect density at the center PT1 of sample 11 was 207 / cm 2 The defect density of the edge PT2 of sample 11 is 7.1 / cm 2 It was.

[0210] From the above results, it is apparent that the defect density of the GaN layer of Sample 10 is reduced compared to Sample 11.

[0211] [others]

[0212] The compound semiconductor substrate according to the above embodiment is not limited to use in high frequency devices, but is also suitable for use in power devices. When the compound semiconductor substrate according to the above embodiment is used in a power device, it is possible to reduce vertical leakage current.

[0213] In each of the compound semiconductor substrates CS1, CS2, CS3, and CS4, the Si substrate 1 and the SiC layer 2 have a resistivity of 0.1 Ωcm or more and 1×10 5 The nitride semiconductor layer 51 may be replaced with a conductive SiC substrate having a resistivity of less than Ωcm. In this case, the C-GaN layer 51 and the intermediate layer 52 act to improve the insulating properties of the nitride semiconductor layer while suppressing the occurrence of warping and cracks. As a result, a high-quality compound semiconductor substrate and compound semiconductor device can be provided.

[0214] The configurations and manufacturing methods of the above-mentioned embodiments, modifications, and examples can be appropriately combined. For example, the first nitride semiconductor layer 4 of each of the compound semiconductor substrates CS1, CS2, CS3, and CS4 may have the configuration of Fig. 2, Fig. 6, Fig. 7, or Fig. 8. The second nitride semiconductor layer 5 of each of the compound semiconductor substrates CS1, CS2, CS3, and CS4 may have the configuration of Fig. 1 or Fig. 5.

[0215] The above-mentioned embodiments, modifications, and examples should be considered as illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0216] 1. Si (silicon) substrate (an example of a Si substrate) 2. SiC (silicon carbide) layer (an example of a SiC layer) 4. First nitride semiconductor layer (an example of the first nitride semiconductor layer) 4a, 4b AlGaN (aluminum gallium nitride) layer 5. Second nitride semiconductor layer (an example of the second nitride semiconductor layer) 6,1053 Electron transport layer (an example of an electron transport layer) 6a,1053a Two-dimensional electron gas 8,1054 Barrier layer (an example of a barrier layer) 11,1055 Source electrode (an example of a first electrode) 12,1056 Drain electrode (an example of the second electrode) 13,1057 Gate electrode (an example of a third electrode) 21 Glass Plate 22 Copper plate 23 electrodes 40,44,45 AlN (aluminum nitride) layer 41 Al 0.75 Ga 0.25 N layer 42 Al 0.5 Ga 0.5 N layer 43 Al 0.25 Ga 0.75 N layer 51, 51a, 51b, 51c C-GaN (gallium nitride) layer (an example of the main layer) 52, 52a, 52b Intermediate layer (an example of an intermediate layer) 1051 SiC substrate 1052 Nitride buffer layer 1061 Fz-Si substrate 1062 n-type SiC substrate CS1, CS2, CS3, CS4 Compound semiconductor substrate (example of compound semiconductor substrate) DC1, DC2, DC3, DC4 Compound semiconductor device (example of compound semiconductor device) PT1 center PT2 Edge

Claims

[Claim 1] A Si substrate having an O concentration of 3×10 17 / cm 3 or more and 3×10 18 / cm 3 or less; a SiC layer formed on the Si substrate; a first nitride semiconductor layer formed on the SiC layer, the first nitride semiconductor layer including an insulating or semi-insulating layer and made of Al x Ga 1-x N (0.1≦x≦1); a second nitride semiconductor layer formed on the first nitride semiconductor layer, the second nitride semiconductor layer including a main layer made of insulating or semi-insulating Al y Ga 1-y N (0≦y<0.1); an electron transport layer formed on the second nitride semiconductor layer and made of AlzGa1-zN (0≦z<0.1); a barrier layer formed on the electron transit layer and having a band gap wider than a band gap of the electron transit layer; a total thickness of the first and second nitride semiconductor layers and the electron transport layer is 6 μm or more and 10 μm or less; the Si concentration, the O concentration, the Mg concentration, the C concentration, and the Fe concentration in the electron transport layer are all greater than 0 and equal to or less than 1×10 17 / cm 3 , The first nitride semiconductor layer is Al x G 1-x A first region made of N (0.4<x≦1) and an Al having a thickness of 0.5 μm or more. x G 1-x N (0.1≦x≦0.4), The first region has a density of 0 particles / cm 3 Above 5 x 10 17 pieces / cm 3 The following Si concentration: 0 ions / cm 3 Above 5 x 10 17 pieces / cm 3 The following O concentrations and 0 particles / cm 3 Above 5 x 10 17 pieces / cm 3 having a Mg concentration of The second region has a density of 0 particles / cm 3 Above 2 x 10 16 pieces / cm 3 The following Si concentration: 0 ions / cm 3 Above 2 x 10 16 pieces / cm 3 The following O concentrations and 0 particles / cm 3 Above 2 x 10 16 pieces / cm 3 having a Mg concentration of At least one of the C concentration and the Fe concentration in the second region is higher than any one of the Si concentration, the O concentration, and the Mg concentration in the second region by 5×10 19 pieces / cm 3 is as follows: The main layer has a density of 0 particles / cm 3 Above 2 x 10 16 pieces / cm 3 The following Si concentration: 0 ions / cm 3 Above 2 x 10 16 pieces / cm 3 The following O concentrations and 0 particles / cm 3 Above 2 x 10 16 pieces / cm 3 having a Mg concentration of At least one of the C concentration and the Fe concentration in the second nitride semiconductor layer is higher than any one of the Si concentration, the O concentration, and the Mg concentration in the second nitride semiconductor layer by 5×10 19 pieces / cm 3 is as follows: The main layer has an activated donor ion concentration of 0 ions / cm 3 Above 2 x 10 14 pieces / cm 3 This includes the following areas: The electron transport layer has a density of 0 electrons / cm 3 Above 1 x 10 16 pieces / cm 3 The following Si concentration: 0 ions / cm 3 Above 1 x 10 16 pieces / cm 3 The O concentration is 0 / cm 3 Above 1 x 10 16 pieces / cm 3 The following Mg concentration: 0 particles / cm 3 Above 1 x 10 17 pieces / cm 3 The following C concentrations and 0 particles / cm 3 Above 1 x 10 17 pieces / cm 3 A compound semiconductor substrate having an Fe concentration of:

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