Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device that can be made smaller than before.SOLUTION: A semiconductor device 10 includes an insulating layer 21 covering the surface of a substrate 20, a conductor 110 provided on the insulating layer 21, a conductor 120 provided in the insulating layer 21 at a position facing the conductor 110 along the first direction parallel to the surface of the substrate 20, and an insulating film 130 provided between the conductor 110 and the conductor 120. The thickness of the insulating film 130 along the first direction is smaller than the thickness of the conductor 110 along the first direction and the thickness of the conductor 120 along the first direction.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art In a semiconductor device such as a NAND flash memory, a circuit including a transistor, a capacitance element, and a wiring layer is formed inside an insulating layer that covers the surface of a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4574145 Summary of the Invention [Problem to be solved by the invention]

[0004] The capacitance elements included in the circuits need to be of a certain size in order to ensure a capacitance as designed, and the shape and layout of the capacitance elements can be an obstacle to miniaturizing the semiconductor device.

[0005] According to the disclosed embodiment, a semiconductor device that can be made smaller than conventional ones is provided. [Means for solving the problem]

[0006] The semiconductor device according to the embodiment includes an insulating layer covering a surface of a substrate, a first conductor provided in the insulating layer, a second conductor provided in the insulating layer at a position facing the first conductor along a first direction parallel to the surface of the substrate, and a first insulating film formed between the first conductor and the second conductor. The thickness of the first insulating film along the first direction is smaller than both the thickness of the first conductor along the first direction and the thickness of the second conductor along the first direction. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system according to the first embodiment. [Diagram 2] FIG. 2 is a block diagram showing the configuration of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a diagram showing an equivalent circuit of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing the configuration of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. [Figure 9] FIG. 9 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] FIG. 13 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] FIG. 14 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] FIG. 15 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] FIG. 16 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17]FIG. 17 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] FIG. 18 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] FIG. 19 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] FIG. 20 is a diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment. [Figure 22] FIG. 22 is a diagram for explaining the method for manufacturing the semiconductor device according to the second embodiment. [Figure 23] FIG. 23 is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing the configuration of a semiconductor device according to the fourth embodiment. [Diagram 25] FIG. 25 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In order to facilitate understanding of the description, the same components in each drawing are denoted by the same reference numerals as much as possible, and duplicated description will be omitted.

[0009] A first embodiment will be described. A semiconductor device 10 according to this embodiment is a non-volatile storage device configured as a NAND type flash memory. FIG. 1 shows a configuration example of a memory system including the semiconductor device 10 as a block diagram. This memory system includes a memory controller 1 and the semiconductor device 10. Note that, although a plurality of semiconductor devices 10 are actually provided in the memory system of FIG. 1, only one of them is shown in FIG. 1. A specific configuration of the semiconductor device 10 will be described later. This memory system can be connected to a host (not shown). The host is, for example, an electronic device such as a personal computer or a mobile terminal.

[0010] The memory controller 1 controls writing of data to the semiconductor device 10 in accordance with a write request from the host, and also controls reading of data from the semiconductor device 10 in accordance with a read request from the host.

[0011] The following signals are transmitted and received between the memory controller 1 and the semiconductor device 10: chip enable signal / CE, ready / busy signal / RB, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals RE, / RE, write protect signal / WP, data signal DQ<7:0>, and data strobe signals DQS, / DQS.

[0012] The chip enable signal / CE is a signal for enabling the semiconductor device 10. The ready / busy signal / RB is a signal for indicating whether the semiconductor device 10 is in a ready state or a busy state. The "ready state" is a state in which an external command is accepted. The "busy state" is a state in which an external command is not accepted. The command latch enable signal CLE is a signal for indicating that the signal DQ<7:0> is a command. The address latch enable signal ALE is a signal for indicating that the signal DQ<7:0> is an address. The write enable signal / WE is a signal for loading a received signal into the semiconductor device 10, and is asserted by the memory controller 1 each time a command, address, and data are received. The memory controller 1 instructs the semiconductor device 10 to load the signal DQ<7:0> while the signal / WE is at the "L (Low)" level.

[0013] The read enable signals RE and / RE are signals for the memory controller 1 to read data from the semiconductor device 10. These are used, for example, to control the operation timing of the semiconductor device 10 when outputting the signal DQ<7:0>. The write protect signal / WP is a signal for instructing the semiconductor device 10 to prohibit data writing and erasing. The signal DQ<7:0> is the substance of data transmitted and received between the semiconductor device 10 and the memory controller 1, and includes a command, an address, and data. The data strobe signals DQS and / DQS are signals for controlling the timing of input and output of the signal DQ<7:0>.

[0014] The memory controller 1 includes a RAM 301, a processor 302, a host interface 303, an ECC circuit 304, and a memory interface 305. The RAM 301, the processor 302, the host interface 303, the ECC circuit 304, and the memory interface 305 are connected to each other via an internal bus 306.

[0015] The host interface 303 outputs requests, user data (write data), etc. received from the host to the internal bus 306. In addition, the host interface 303 transmits user data read from the semiconductor device 10, responses from the processor 302, etc. to the host.

[0016] The memory interface 305 controls the process of writing user data and the like to the semiconductor device 10 and the process of reading the data from the semiconductor device 10 based on instructions from the processor 302 .

[0017] The processor 302 performs overall control of the memory controller 1. The processor 302 is, for example, a CPU or an MPU. When the processor 302 receives a request from the host via the host interface 303, the processor 302 performs control according to the request. For example, the processor 302 instructs the memory interface 305 to write user data and parity to the semiconductor device 10 in accordance with the request from the host. The processor 302 also instructs the memory interface 305 to read user data and parity from the semiconductor device 10 in accordance with the request from the host.

[0018] The processor 302 determines a storage area (memory area) on the semiconductor device 10 for user data accumulated in the RAM 301. The user data is stored in the RAM 301 via the internal bus 306. The processor 302 determines the memory area for data (page data) in units of pages, which are writing units. User data stored in one page of the semiconductor device 10 is also referred to as "unit data" below. The unit data is generally encoded and stored in the semiconductor device 10 as a code word. In this embodiment, encoding is not essential. The memory controller 1 may store the unit data in the semiconductor device 10 without encoding it, but FIG. 1 shows a configuration in which encoding is performed as an example. When the memory controller 1 does not perform encoding, the page data matches the unit data. In addition, one code word may be generated based on one unit data, or one code word may be generated based on divided data into which the unit data is divided. In addition, one code word may be generated using multiple unit data.

[0019] The processor 302 determines a memory area of ​​the semiconductor device 10 to which the unit data is to be written for each unit data. A physical address is assigned to the memory area of ​​the semiconductor device 10. The processor 302 manages the memory area to which the unit data is to be written using the physical address. The processor 302 instructs the memory interface 305 to specify the determined memory area (physical address) and write the user data to the semiconductor device 10. The processor 302 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. When the processor 302 receives a read request including a logical address from the host, it identifies the physical address corresponding to the logical address and instructs the memory interface 305 to read the user data by specifying the physical address.

[0020] The ECC circuit 304 generates a codeword by encoding the user data stored in the RAM 301. The ECC circuit 304 also decodes the codeword read from the semiconductor device 10.

[0021] The RAM 301 temporarily stores user data received from the host before storing it in the semiconductor device 10, and temporarily stores data read from the semiconductor device 10 before transmitting it to the host. The RAM 301 is, for example, a general-purpose memory such as an SRAM or a DRAM.

[0022] 1 shows a configuration example in which the memory controller 1 includes an ECC circuit 304 and a memory interface 305. However, the ECC circuit 304 may be built into the memory interface 305. The ECC circuit 304 may also be built into the semiconductor device 10. The specific configuration and arrangement of each element shown in FIG. 1 are not particularly limited.

[0023] 1 operates as follows when a write request is received from the host. The processor 302 temporarily stores data to be written in the RAM 301. The processor 302 reads the data stored in the RAM 301 and inputs the data to the ECC circuit 304. The ECC circuit 304 encodes the input data and inputs the codeword to the memory interface 305. The memory interface 305 writes the input codeword to the semiconductor device 10.

[0024] 1 operates as follows when a read request is received from the host. The memory interface 305 inputs a codeword read from the semiconductor device 10 to the ECC circuit 304. The ECC circuit 304 decodes the input codeword and stores the decoded data in the RAM 301. The processor 302 transmits the data stored in the RAM 301 to the host via the host interface 303.

[0025] 2, the semiconductor device 10 includes a memory cell array 430, a sense amplifier 440, a row decoder 450, an input / output circuit 401, a logic control circuit 402, a sequencer 421, a register 422, a voltage generating circuit 423, an input / output pad group 411, a logic control pad group 412, and a power supply input terminal group 413.

[0026] The memory cell array 430 is a portion for storing data. The memory cell array 430 has a plurality of memory cell transistors MT associated with a plurality of bit lines BL and a plurality of word lines WL. A specific configuration of the memory cell array 430 will be described later with reference to FIGS. 3 to 6.

[0027] The sense amplifier 440 is a circuit for adjusting the voltage applied to the bit line BL and for reading the voltage of the bit line BL and converting it into data. When reading data, the sense amplifier 440 acquires read data read from the memory cell transistor MT to the bit line BL and transfers the acquired read data to the input / output circuit 401. When writing data, the sense amplifier 440 transfers write data to be written via the bit line BL to the memory cell transistor MT. The operation of the sense amplifier 440 is controlled by the sequencer 421.

[0028] The row decoder 450 is a circuit configured as a group of switches (not shown) for applying a voltage to each of the word lines WL. The row decoder 450 receives a block address and a row address from the register 422, selects a corresponding block based on the block address, and selects a corresponding word line WL based on the row address. The row decoder 450 switches the above-mentioned group of switches between open and closed states so that a voltage from the voltage generating circuit 423 is applied to the selected word line WL. The operation of the row decoder 450 is controlled by the sequencer 421.

[0029] The input / output circuit 401 transmits and receives the signal DQ<7:0> and the data strobe signals DQS and / DQS to and from the memory controller 1. The input / output circuit 401 transfers the command and address in the signal DQ<7:0> to the register 422. The input / output circuit 401 also transmits and receives write data and read data to and from the sense amplifier 440.

[0030] The logic control circuit 402 receives a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals RE, / RE, and a write protect signal / WP from the memory controller 1. In addition, the logic control circuit 402 transfers a ready / busy signal / RB to the memory controller 1 to notify the outside of the state of the semiconductor device 10.

[0031] The sequencer 421 controls the operation of each unit including the memory cell array 430 based on a control signal input from the memory controller 1 to the input / output circuit 401 and the logic control circuit 402 .

[0032] The register 422 is a part that temporarily holds commands and addresses. The register 422 holds commands that instruct a write operation, a read operation, an erase operation, etc. The command is input from the memory controller 1 to the input / output circuit 401, and then transferred from the input / output circuit 401 to the register 422 and held therein.

[0033] An address corresponding to the above command is also held in the register 422. The address is input from the memory controller 1 to the input / output circuit 401, and then transferred from the input / output circuit 401 to the register 422 and held therein.

[0034] Furthermore, the register 422 also holds status information indicating the operation state of the semiconductor device 10. The status information is updated by the sequencer 421 each time according to the operation state of the memory cell array 430, etc. In response to a request from the memory controller 1, the status information is output as a status signal from the input / output circuit 401 to the memory controller 1.

[0035] The voltage generation circuit 423 is a part that generates voltages required for each of the data write operation, read operation, and erase operation in the memory cell array 430. Such voltages include, for example, voltages applied to each word line WL, voltages applied to each bit line BL, etc. The operation of the voltage generation circuit 423 is controlled by the sequencer 421.

[0036] The input / output pad group 411 is a portion provided with a plurality of terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the input / output circuit 401. Each terminal is provided individually corresponding to the signal DQ<7:0> and the data strobe signals DQS and / DQS.

[0037] The logic control pad group 412 is a portion provided with a plurality of terminals (pads) for transmitting and receiving each signal between the memory controller 1 and the logic control circuit 402. The terminals are provided individually corresponding to the chip enable signal / CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal / WE, the read enable signals RE, / RE, the write protect signal / WP, and the ready / busy signal / RB.

[0038] The power input terminal group 413 is a portion provided with a plurality of terminals for receiving the voltages necessary for the operation of the semiconductor device 10. The voltages applied to the respective terminals include power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss.

[0039] The power supply voltage Vcc is a circuit power supply voltage provided from the outside as an operating power supply, and is, for example, a voltage of about 3.3 V. The power supply voltage VccQ is, for example, a voltage of 1.2 V. The power supply voltage VccQ is a voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor device 10. The power supply voltage Vpp is a power supply voltage that is higher than the power supply voltage Vcc, and is, for example, a voltage of 12 V.

[0040] A specific configuration of the memory cell array 430 will be described. In FIG. 3, the configuration of the memory cell array 430 is shown as an equivalent circuit diagram. As shown in the figure, the memory cell array 430 includes a plurality of string units SU0 to SU3. Each of the string units SU0 to SU3 includes a plurality of NAND strings SR. Furthermore, each of the NAND strings SR includes, for example, eight memory cell transistors MT0 to MT7 and two select transistors STD and STS. The number of memory cell transistors and select transistors included in the NAND string SR may be different from that in the example of FIG. 3.

[0041] The multiple string units SU0 to SU3 together form one block, and multiple such blocks are provided in the memory cell array 430. In FIG. 3, only a single block is illustrated, and the other blocks are omitted from the illustration.

[0042] In the following description, the string units SU0 to SU3 may be referred to as "string units SU" without distinction. Similarly, the memory cell transistors MT0 to MT7 may be referred to as "memory cell transistors MT" without distinction.

[0043] Each string unit SU includes NAND strings SR in the same number as the N bit lines BL0 to BL(N-1). N is a positive integer. The memory cell transistors MT0 to MT7 included in the NAND string SR are arranged in series between the source of the select transistor STD and the drain of the select transistor STS. The drain of the select transistor STD is connected to one of the bit lines BL0, etc. The source of the select transistor STS is connected to a source line SL. In the following description, the bit lines BL1 to BL(N-1) may be referred to as "bit lines BL" without distinction between them.

[0044] As will be described later, each memory cell transistor MT is configured as a transistor having a charge storage layer in a gate portion. The amount of charge stored in the charge storage layer corresponds to the data held in the memory cell transistor MT. The memory cell transistor MT may be of a charge trap type using, for example, a silicon nitride film as a charge storage layer, or may be of a floating gate type using, for example, a silicon film as a charge storage layer.

[0045] The gates of the select transistors STD included in the string unit SU0 are all connected to a select gate line SGD0. The select gate line SGD0 is a line to which a voltage is applied for switching the open / close of each select transistor STD. Similarly, for the string units SU1 to SU3, select gate lines SGD1 to SGD3 for applying voltages to the select transistors STD are provided in correspondence with each string unit SU.

[0046] The gates of the select transistors STS included in the string unit SU0 are all connected to a select gate line SGS0. The select gate line SGS0 is a line to which a voltage is applied for switching the open / close of each select transistor STS. Similarly, for the string units SU1 to SU3, select gate lines SGS1 to SGS3 for applying a voltage to the select transistors STS are provided in correspondence with each string unit SU. Note that the select gate line SGS may be shared between the string units SU0 to SU3 constituting one block, and the gates of all the select transistors ST2 included in the string units SU0 to SU3 may be connected to a common select gate line SGS.

[0047] The gates of the memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The word lines WL0 to WL7 are lines to which voltages are applied for the purposes of switching the memory cell transistors MT0 to MT7 between open and closed states, changing the amount of charge stored in each charge storage layer of the memory cell transistors MT0 to MT7, etc.

[0048] Data writing and reading in the semiconductor device 10 is performed collectively for a plurality of memory cell transistors MT connected to any word line WL in any string unit SU, for each unit called a "page." On the other hand, data erasure in the semiconductor device 10 is performed collectively for all memory cell transistors MT included in a block. As a specific method for writing, reading, and erasing such data, various well-known methods can be adopted, and detailed explanations thereof will be omitted.

[0049] 4 is a schematic perspective view showing the configuration of a memory cell array 430 and its neighboring portions of the semiconductor device 10. As shown in the figure, the semiconductor device 10 includes a substrate 20, an insulating layer 21, a semiconductor layer 22, and a plurality of insulating layers 30 and conductive layers 40.

[0050] The substrate 20 is a plate-like member having a flat surface on the z-direction side in Fig. 4, and is, for example, a silicon wafer. The insulating layer 21, the semiconductor layer 22, the insulator layer 30, the conductor layer 40, and the like described below are multi-layer films formed on the upper surface side of the substrate 20 by, for example, CVD film formation.

[0051] The insulating layer 21 is a layer made of an insulating material such as silicon oxide, and is formed so as to cover the surface of the substrate 20. Peripheral circuits including, for example, transistors Tr and wiring 220 are formed inside the insulating layer 21. These peripheral circuits constitute the sense amplifier 440 and row decoder 450 shown in Fig. 2. The insulating layer 21 covers the entire peripheral circuits.

[0052] The semiconductor layer 22 is a layer that functions as the source line SL in Fig. 3. The semiconductor layer 22 is formed of a material containing silicon, such as polycrystalline silicon doped with impurities. The semiconductor layer 22 is embedded in the insulating layer 21 in a portion below the memory cell array 430.

[0053] The semiconductor layer 22 may be entirely made of a semiconductor material such as silicon, but may have a two-layer structure consisting of a semiconductor layer 22a and a conductive layer 22b as shown in the example of Fig. 4. The semiconductor layer 22a is a layer made of a semiconductor material such as silicon, and the conductive layer 22b is a layer made of a metal material such as tungsten.

[0054] A plurality of insulating layers 30 and a plurality of conductive layers 40 are formed above the semiconductor layer 22, and are arranged alternately along the z direction in FIG.

[0055] The conductor layer 40 is a conductive layer formed of a material containing tungsten, for example. Each conductor layer 40 is used as the word lines WL0 to WL7 and the select gate lines SGS0, SGD0, etc. in FIG. 3. The insulator layer 30 is disposed between adjacent conductor layers 40, and electrically insulates them from each other. The insulator layer 30 is formed of a material containing silicon oxide, for example.

[0056] In a region where a plurality of insulating layers 30 and conductive layers 40 are stacked along the z direction, a plurality of memory holes MH are formed so as to penetrate them along the z direction, and memory pillars 50 are formed inside the memory holes MH. Each memory pillar 50 is formed in a range from the insulating layer 30 closest to the z direction side to the semiconductor layer 22. Each memory pillar 50 corresponds to a NAND string SR shown in FIG. 3.

[0057] Fig. 5 shows a cross section of the memory pillar 50 taken along a plane (yz plane) passing through the central axis along the longitudinal direction of the memory pillar 50. Fig. 6 shows a cross section of the memory pillar 50 taken along a plane (xy plane) perpendicular to the central axis and passing through the conductive layer 40.

[0058] 6, the memory pillar 50 has a circular or elliptical cross-sectional shape. The memory pillar 50 has a body 51 and a stacked film 52.

[0059] The body 51 has a core portion 51a and a semiconductor portion 51b. The semiconductor portion 51b is formed of a material such as amorphous silicon, and is a portion in which channels of the memory cell transistors MT and the like are formed. The core portion 51a is formed of an insulating material such as silicon oxide, and is provided inside the semiconductor portion 51b. Note that the entire body 51 may be the semiconductor portion 51b, and the inner core portion 51a may not be provided.

[0060] The laminated film 52 is a multi-layer film formed to cover the outer periphery of the body 51. The laminated film 52 has, for example, a tunnel insulating film 52a and a charge trapping film 52b. The tunnel insulating film 52a is a film formed on the innermost side. The tunnel insulating film 52a includes, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 52a is a potential barrier between the body 51 and the charge trapping film 52b. For example, when electrons are injected from the body 51 to the charge trapping film 52b (write operation), and when holes are injected from the body 51 to the charge trapping film 52b (erase operation), the electrons and holes each pass (tunnel) through the potential barrier of the tunnel insulating film 52a.

[0061] The charge trapping film 52b is a film formed to cover the outside of the tunnel insulating film 52a. The charge trapping film 52b contains, for example, silicon nitride, and has trap sites in the film that trap charges. The portion of the charge trapping film 52b sandwiched between the conductive layer 40, which is the word line WL, and the body 51 constitutes the storage region of the memory cell transistor MT as the charge storage layer described above. The threshold voltage of the memory cell transistor MT changes depending on the presence or absence of charges in the charge trapping film 52b, or the amount of the charges. This allows the memory cell transistor MT to hold information.

[0062] 5, the outer peripheral surface of the conductive layer 40, which is the word line WL, is covered with a barrier film 45 and a block insulating film 46. The barrier film 45 is a film for improving adhesion between the conductive layer 40 and the block insulating film 46. For example, when the conductive layer 40 is made of tungsten, the barrier film 45 is a laminated film of titanium nitride and titanium.

[0063] The block insulating film 46 prevents back tunneling of charges from the conductive layer 40 to the laminated film 52 side. The block insulating film 46 is a film for suppressing the above-mentioned. The block insulating film 46 is, for example, a silicon oxide film or a metal oxide film. One example of a metal oxide is aluminum oxide.

[0064] A cover insulating film 31 is provided between the insulator layer 30 and the charge trapping film 52b. The cover insulating film 31 contains, for example, silicon oxide. The cover insulating film 31 is a film for protecting the charge trapping film 52b from being etched in a replacement process in which the sacrificial layer is replaced with the conductor layer 40. If a replacement process is not used to form the conductor layer 40, the cover insulating film 31 may not be provided.

[0065] As described above, the inside of the memory pillar 50 where the conductive layers 40 are connected functions as a transistor. That is, in each memory pillar 50, a plurality of transistors are connected in series along the longitudinal direction. Each conductive layer 40 is connected to the gate of each transistor via the stacked film 52. The semiconductor portion 51b on the inside of the transistor functions as the channel of the transistor.

[0066] Some of the transistors arranged in series along the longitudinal direction of the memory pillar 50 as described above function as the memory cell transistors MT in Fig. 3. In addition, the transistors formed on both sides of the memory cell transistors MT arranged in series function as the select transistors STD, STS in Fig. 3.

[0067] Returning to FIG. 4, the explanation will be continued. As shown in the figure, a plurality of bit lines BL are provided on the upper side of each memory pillar 50. Each bit line BL is formed as a linear wiring extending along the x direction in FIG. 4, and is arranged so as to be aligned along the y direction in the figure. The upper end of the memory pillar 50 is connected to one of the bit lines BL via a contact Cb. As a result, the semiconductor portion 51b of each memory pillar 50 is electrically connected to the bit line BL.

[0068] The laminated conductive layer 40 and insulating layer 30 are divided into multiple pieces by slits ST. The slits ST are linear grooves formed to extend along the y direction in FIG. 4, and are formed to a depth reaching, for example, the semiconductor layer 22.

[0069] Moreover, the upper side portions of the laminated conductive layer 40 and insulating layer 30 are divided by a slit SHE. The slit SHE is a shallow groove formed to extend along the y direction in Fig. 4. The slit SHT is formed to a depth that divides only those of the multiple conductive layers 40 that are provided as the select gate lines SGD.

[0070] At the lower end of the memory pillar 50, the stacked film 52 is removed, and the semiconductor portion 51b is connected to the semiconductor layer 22. This electrically connects the semiconductor layer 22, which functions as the source line SL, to the channel of each transistor.

[0071] The peripheral circuit disposed inside the insulating layer 21 includes a capacitance element 100 in addition to the transistor Tr etc. shown in Fig. 4. The capacitance element 100 functions as, for example, a capacitor for adjusting the time constant of a potential change at a specific node.

[0072] Hereinafter, the configuration of each part will be described using the x-direction, y-direction, and z-direction shown in Fig. 4. The z-direction is a direction from bottom to top, in which multiple conductor layers 40 are stacked. The x-direction is a direction intersecting the z-direction, in which each bit line BL extends. The y-direction is a direction intersecting both the z-direction and the x-direction, in which multiple bit lines BL are lined up.

[0073] The configuration of the capacitive element 100 will be described with reference to Figs. 7 and 8. Fig. 7 shows a cross section of the capacitive element 100 and its surroundings taken along an xy plane parallel to the surface of the substrate 20. Fig. 8 shows a cross section taken along line VIII-VIII of Fig. 7. The capacitive element 100 includes a pair of conductors 110, 120 and an insulating film 130. In addition, a linear conductor 210 extending in the y direction is provided near the capacitive element 100. The conductor 210 is a conductor provided as a wiring layer constituting a part of the peripheral circuit.

[0074] Both the conductors 110 and 120 are formed of a material having electrical conductivity. For example, a metal material such as tungsten can be used as the material. The material of the conductor 110 and the material of the conductor 120 may be the same material or different materials.

[0075] 7, the conductor 110 has a plurality of straight portions 111 extending linearly toward the y direction, and these straight portions 111 are arranged in a row in the x direction. The conductor 120 has a plurality of straight portions 121 extending linearly toward the -y direction, and these straight portions 121 are arranged in a row in the x direction. The straight portions 111 of the conductor 110 and the straight portions 121 of the conductor 120 face each other along the x direction, and are arranged alternately along the same direction.

[0076] The conductor 110, including the straight portion 111, is disposed in a position where the entire conductor 110 is inside the conductor 120 in a top view. The insulating film 130 is formed so as to fill the gap between the conductors 110 and 120 adjacent to each other. The insulating film 130 is a film formed of an insulating material. The insulating film 130 may be made of a material having a relatively high relative dielectric constant, such as hafnium oxide, tantalum oxide, or silicon nitride. With this configuration, the capacitive element 100 functions as a capacitor.

[0077] The insulating film 130 is preferably made of a material having a higher dielectric constant than that of the insulating layer 21. However, if the capacitance of the capacitive element 100 can be sufficiently ensured, the insulating film 130 may be made of the same material as that of the insulating layer 21 (e.g., silicon oxide).

[0078] In this embodiment, due to a manufacturing method described later, the insulating film 130 is formed not only between the conductor 110 and the conductor 120, but also on the outer periphery of the conductor 120. The insulating film 130 corresponds to the "first insulating film" in this embodiment.

[0079] A part of the outer peripheral surface of the conductor 110 and a part of the outer peripheral surface of the conductor 120 are covered with a barrier metal BM. In Figures 7 and 8, the cross section of the part covered with the barrier metal BM is shown by a thick line. The barrier metal BM is a conductive thin film formed to prevent the material of the conductors 110 and 120 from reacting with surrounding members or diffusing into the surroundings. For example, titanium or titanium nitride can be used as the material of the barrier metal BM.

[0080] The conductor 110, including the barrier metal BM that covers part of its outer circumferential surface, corresponds to the "first conductor" in this embodiment. The conductor 120, including the barrier metal BM that covers part of its outer circumferential surface, corresponds to the "second conductor" in this embodiment.

[0081] The portions of the conductor 110 (first conductor) and the conductor 120 (second conductor) shown in Fig. 8 all extend along the y direction. The y direction corresponds to the "second direction" in this embodiment.

[0082] As shown in FIG. 8, one end of a contact 150 extending from the lower side is connected to the conductor 110. The other end of the contact 150 is connected to a wiring 220 constituting a peripheral circuit. One end of a contact 230 extending from the upper side is connected to the conductor 120. The other end of the contact 230 is connected to a wiring (not shown) constituting a peripheral circuit. Both of the contacts 150 and 230 are provided as vias for electrically connecting the capacitance element 100 to the peripheral wiring, and extend in the depth direction (i.e., z direction) of the substrate 20. In the example of FIG. 8, two wirings 220 are formed on the lower side of the capacitance element 100. One of them is connected to the conductor 110 via the contact 150 as described above, and the other is connected to the substrate 20 via the contact 240.

[0083] The contact 150 is formed integrally with the conductor 110 by, for example, a dual damascene method. Similarly, the contact 230 is formed integrally with an upper wiring (not shown). The outer peripheral surfaces of the contacts 150 and 230 are covered with a barrier metal BM. The contacts 150 and the like may be formed by other methods, such as a single damascene method.

[0084] As described above, the semiconductor device 10 according to this embodiment includes the insulating layer 21 covering the surface of the substrate 20, the conductor 110 (first conductor) provided in the insulating layer 21, the conductor 120 (second conductor) provided in the insulating layer 21 at a position facing the conductor 110 along a direction parallel to the surface of the substrate 20 (for example, the x direction in FIG. 8), and the insulating film 130 (first insulating film) provided between the conductor 110 and the conductor 120. The conductor 110, the conductor 120, and the insulating film 130 form a capacitance element 100. The x direction in which the insulating layer 21 and the conductor 120 face each other corresponds to the "first direction" in this embodiment. The insulating layer 21 may directly cover the surface of the substrate 20 as in this embodiment, but may indirectly cover the surface of the substrate 20 via, for example, another film.

[0085] The insulating film 130 is a very thin film formed on the side surface of the conductor 110 by a method described later. For this reason, as shown in Fig. 8, the thickness of the insulating film 130 along the direction in which the conductor 110, the insulating film 130, and the conductor 120 are arranged (x direction in Fig. 8) is smaller than both the thickness of the conductor 110 along that direction and the thickness of the conductor 120 along that direction.

[0086] The capacitance C of the capacitive element 100 can be calculated by the following formula (1). C=ε r ε0×S / d=ε r ε0×(L×H) / d (1)

[0087] In equation (1), ε r is the relative dielectric constant of the insulating film 130, and ε0 is the dielectric constant of a vacuum. S is the surface area of ​​the entire portion of the conductor 110 that faces the conductor 120. d is the thickness of the insulating film 130. L is the length of the entire portion of the conductor 110 that faces the conductor 120 in a top view such as in FIG. 7. H is the height of the portion of the conductor 110 that faces the conductor 120 (i.e., the dimension along the z direction).

[0088] In order to reduce the overall dimensions of the semiconductor device 10, it is preferable to increase the capacitance of the capacitive element 100 per unit area as much as possible by increasing the value of capacitance C shown in formula (1). In this embodiment, the insulating film 130 is formed as a thin film arranged perpendicularly to the surface of the substrate 20, thereby making the value of d in formula (1) smaller than in the past. This makes it possible to increase the capacitance of the capacitive element 100 per unit area and reduce the size of the semiconductor device 10 including the capacitive element 100.

[0089] In this embodiment, the value of L in formula (1) is increased by forming a shape in which a plurality of straight portions 111 and straight portions 121 are alternately arranged as shown in Fig. 7. For example, from the configuration of Fig. 7, if the arrangement pitch of straight portions 111 and straight portions 121 is further reduced, the value of L becomes further increased, and the value of capacitance C becomes further increased. In this way, by adjusting the shapes of conductor 110 and conductor 120, it is possible to further miniaturize semiconductor device 10.

[0090] Furthermore, in this embodiment, the insulating film 130 is made of a material having a higher dielectric constant than the insulating layer 21, so that ε r This makes it possible to further reduce the size of the semiconductor device 10.

[0091] ε in Equation (1) r , d, L, and H are parameters for adjusting the capacitance C of the capacitive element 100. These can be adjusted individually as independent parameters, and therefore may be set appropriately according to the capacitance value required for the capacitive element 100.

[0092] FIG. 25 shows a schematic configuration of a capacitive element 100A according to a comparative example. The conductors 110A, 110B, 110C, and 110D shown in the figure are all formed inside the insulating layer 21 as wiring in the peripheral circuit, and are formed to extend along the y direction in FIG. 25. In this comparative example, a part of the conductor 110A and the like routed as wiring is also used as the capacitive element 100A. In the example of FIG. 25, the contact 150A is connected to the conductor 110A from above, but the position at which the contact 150A is provided may be different from the position shown in FIG. 25.

[0093] In such a configuration, the capacitance element 100A can be, for example, a capacitance component between the conductors 110A and 110C facing each other along the vertical direction. In this case, in order to increase the capacitance per unit area, it is necessary to reduce the distance between the conductors 110A and 110C. However, since these are also used as wiring, if the distance between them is made too small, the capacitance between the conductors that are close to each other but cross each other in a portion other than the range shown in FIG. 25 becomes too large to be ignored, and the peripheral circuit may not operate as designed. In addition, since the conductor 110A, which is the upper layer wiring, and the conductor 110C, which is the lower layer wiring, are formed by lithography at different times, a positional deviation may occur between them, for example, along the x direction. As a result, there is a concern that the capacitance of the capacitance element 100A may deviate from the design value.

[0094] In contrast, in this embodiment, the capacitive element 100 is provided as an independent component separate from the wiring of the peripheral circuit, so that even if the distance between the conductor 110 and the conductor 120 is shortened, the capacitance between the conductors in other parts does not increase. In addition, by forming the insulating film 130 and the conductor 120 by a method described later, it is possible to suppress a change in capacitance caused by misalignment during formation.

[0095] As in the comparative example, a configuration in which a pair of conductors that constitute the capacitance element 100A are arranged in a vertical direction may be considered, for example, a configuration in which plate-shaped conductors (electrodes) parallel to the surface of the substrate 20 are arranged facing each other in the vertical direction, such as a MOS capacitor. However, in this case, the area of ​​the opposing parts of the conductors arranged vertically becomes the area of ​​the capacitance element 100A as viewed from above. As a result, the area of ​​the capacitance element 100A as viewed from above becomes very large, and the capacitance per unit area becomes small. In contrast, in this embodiment, the insulating film 130 is formed as a thin film arranged on a surface perpendicular to the surface of the substrate 20, so that even if the areas of the opposing parts of the conductors 110 and 120 become large, the area of ​​the capacitance element 100A as viewed from above does not become large.

[0096] For example, the capacitance component between conductors 110A and 110B facing each other in the left-right direction can be used as the capacitive element 100A in Fig. 25. In this case, too, in order to increase the capacitance per unit area, it is necessary to reduce the distance between the conductors 110A and 110B. However, since the distance between the two depends on the pattern accuracy of lithography, it is difficult to reduce it as much as the insulating film 130 of this embodiment, and the distance ends up being approximately the same as the width of the conductors 110A, etc. (the dimension along the x direction in Fig. 25).

[0097] In contrast, in this embodiment, the insulating film 130 can be formed as a very thin film by forming the insulating film 130 by a method described later. As a result, as described above, the thickness of the insulating film 130 along the direction in which the conductors 110, the insulating film 130, and the conductors 120 are arranged can be made smaller than both the thickness of the conductors 110 along that direction and the thickness of the conductors 120 along that direction.

[0098] In the cross section of Fig. 8, conductors 120 are provided on both sides of conductor 110 in the x direction, with insulating films 130 interposed between them. The conductors 120 arranged on both sides of conductor 110 correspond to the "second conductor" and the "fourth conductor" in this embodiment, respectively. As is clear from Fig. 7, the second conductor and the fourth conductor are electrically connected to each other.

[0099] In the following, a method for manufacturing the semiconductor device 10 will be described, particularly a method for forming the capacitive element 100 and its peripheral portion.

[0100] <Insulating Layer Forming Process> In the insulating layer forming process, which is the first process, first, circuit elements that become part of the peripheral circuit, such as the transistor Tr shown in FIG. 4, are formed on the surface of the substrate 20, which is a silicon wafer. Then, the insulating layer 21 that covers the surface of the substrate 20, and the wiring 220 and contacts 240 embedded therein are formed through processes such as CVD film formation and lithography. FIG. 9 shows a state in which the insulating layer forming process is completed. In FIG. 9, the circuit elements such as the transistor Tr formed on the surface of the substrate 20 are not shown. In addition, in the insulating layer forming process, the final insulating layer 21 shown in FIG. 4 is not formed in its entirety, but only a part excluding its upper side portion is formed.

[0101] As described above, the insulating layer forming step is a step of forming the insulating layer 21 that covers the surface of the substrate 20.

[0102] <Recess Forming Process> In the recess forming process following the insulating layer forming process, a contact hole 152 is formed in the insulating layer 21, for example, by RIE (Reactive Ion Etching). As shown in Fig. 10, the contact hole 152 is a hole that extends along the z direction and is formed to reach one of the wirings 220. The contact hole 152 is a hole for forming a contact 150 (see Fig. 8) therein in a later process.

[0103] After the contact holes 152 are formed, the recesses 112 and the recesses 212 are formed on the upper surface of the insulating layer 21 by further RIE. FIG. 11 shows a state in which the recess forming step is completed. The area in which the recesses 112 are formed is the area in which the conductors 110 in FIG. 7 are formed, as viewed from above. Each of the recesses 112 shown in the cross section of FIG. 11 corresponds to the portion in FIG. 8 in which each of the linear portions 111 is formed. As shown in FIG. 11, when the recess forming step is completed, the recesses 112 are connected to the previously formed contact holes 152.

[0104] The range in which the recess 212 is formed is the range in which the conductor 210 in Fig. 7 is formed when viewed from above. In this embodiment, as described above, the recess 112 corresponding to the conductor 110 in Fig. 7 and the recess 212 corresponding to the conductor 210 in Fig. 7 are simultaneously formed by, for example, RIE. Therefore, the recess 112 and the recess 212 are formed at the same height.

[0105] <First Conductor Forming Process> In the first conductor forming process following the recess forming process, a layer of a barrier metal BM is first formed so as to cover the entire surface of the insulating layer 21 including the recesses 112 and 212. After that, a layer of the conductor 110 is formed so as to cover the entire barrier metal BM. The barrier metal BM and the conductor 110 are formed by, for example, CVD. FIG. 12 shows a state in which the first conductor forming process is completed. As shown in the figure, when the first conductor forming process is completed, the entire inside of the contact hole 152, the recess 112, and the recess 212 are filled with the conductor 110 via the barrier metal BM. The conductor 110 filling the inside of the recess 112 will ultimately remain as the conductor 110 shown in FIG. 7 and the like. Moreover, the conductor 110 filling the inside of the recess 212 will ultimately remain as the conductor 210 shown in FIG. 7 and the like. Furthermore, the conductor 110 filling the inside of the contact hole 152 will ultimately become the contact 150. The first conductor formation step, as described above, is a step in which the conductor 110 and the underlying contact 150 are simultaneously formed, and is performed using a conventional dual damascene process.

[0106] As described above, the first conductor forming step is a step of forming the conductor 110 (first conductor) inside the insulating layer 21.

[0107] <Mask Forming Process> In the mask forming process following the first conductor forming process, an etching mask 90 is formed so as to cover the surface of the insulating layer 110. Then, an opening 91 is formed in a part of the etching mask 90. ​​FIG. 13 shows the state after the mask forming process is completed. As shown in the figure, the opening 91 is formed in an area directly above the portion in which the capacitive element 100 is formed in FIG. 8. The portion directly above the recess 212 is covered with the etching mask 90.

[0108] <Exposure Step> In the exposure step following the mask formation step, a part of the conductor 110 exposed in the opening 91 is removed by anisotropic etching via the etching mask 90. ​​As shown in Fig. 14, this etching is performed until the surface of the insulating layer 21 is exposed. The insides of the recesses 112 and the recesses 212 remain filled with the conductor 110.

[0109] Thereafter, a part of the insulating layer 21 directly below the opening 91 is removed by anisotropic etching using a gas having selectivity for removing the insulating layer 21 but not removing the conductor 110. As shown in FIG. 15, the etching is performed until the entire side surface 110S of the conductor 110 filling the inside of the recess 112 is exposed. The bottom surface of the recess formed in the insulating layer 21 by the etching is labeled with the symbol "21B" in FIG. 15. The bottom surface is also referred to as the "bottom surface 21B" below. In this embodiment, the above etching is performed so that the height position of the bottom surface 21B is the same as the height position of the lower end of the conductor 110.

[0110] As described above, the exposing step is a step of exposing the side surface 110S of the conductor 110 (first conductor) by removing a part of the insulating layer 21. When the exposing step is completed, the etching mask 90 is removed from the surface of the insulating layer 21.

[0111] <Insulating Film Forming Process> In the insulating film forming process following the exposing process, an insulating film 130 is formed by, for example, CVD so as to cover the entire surface of the insulating layer 21 including the conductor 110. Fig. 16 shows a state in which the formation of the insulating film 130 has been completed. In the state of Fig. 16, the entire surface of the conductor 110, i.e., the surface including the side surface 110S exposed in the exposing process, is covered with the insulating film 130.

[0112] Thereafter, the portions of the insulating film 130 covering the bottom surface 21B and the portions covering the upper surfaces of the conductors 110 are removed, for example, by RIE. Fig. 17 shows a state in which parts of the insulating film have been removed in this manner. As shown in the figure, only the portions of the insulating film 130 covering the side surfaces of each part (i.e., the surfaces perpendicular to the surface of the substrate 20) remain.

[0113] As described above, the insulating film forming step is a step of forming the insulating film 130S on the side surface 110S of the exposed conductor 11 (first conductor).

[0114] <Second Conductor Forming Process> In the second conductor forming process following the insulating film forming process, a layer of a barrier metal BM is first formed so as to cover the entire surface of the insulating layer 21 including the conductor 110, the insulating film 130, etc. Then, a layer of the conductor 120 is formed so as to cover the entire barrier metal BM. The barrier metal BM and the conductor 120 are formed by, for example, CVD. FIG. 18 shows a state in which the second conductor forming process is completed. As shown in the figure, when the second conductor forming process is completed, the entire periphery of the conductor 110 having the insulating film 130 formed on the side surface 110S is filled with the conductor 120 via the barrier metal BM. A part of the conductor 120 is formed at a position facing the conductor 110 with the insulating film 130 sandwiched therebetween. The conductor 120 formed at that position will ultimately remain as the conductor 120 shown in FIG. 7 and the like.

[0115] As described above, the second conductor forming step is a step of forming the conductor 120 (second conductor) at a position facing the conductor 110 (first conductor) with the insulating film 130 sandwiched therebetween.

[0116] <Polishing Step> In the polishing step following the second conductor forming step, a portion of the conductor 110 and the conductor 120 formed above the insulating layer 21 are polished and removed, for example, by CMP (Chemical Mechanical Polishing). The polishing is performed until the upper surface of the insulating layer 21 is exposed. FIG. 19 shows a state where the polishing step is completed. After the polishing step is performed, the entire conductor 120 faces the conductor 110 with the insulating film 130 interposed therebetween.

[0117] <Upper Layer Forming Step> In the upper layer forming step following the polishing step, an insulating layer 21 is additionally formed so as to cover from above the entire surface polished in the polishing step. The added insulating layer 21 corresponds to the upper layer side portion of the insulating layer 21 shown in FIG. 4. FIG. 20 shows a state in which the upper layer forming step is completed. When the upper layer forming step is completed, the conductors 110 and 120 constituting the capacitive element 100 are entirely embedded inside the insulating layer 21.

[0118] <Contact Formation Process> In the contact formation process following the upper layer formation process, a contact hole is formed in the insulating layer 21 in a portion directly above the conductor 120, and a contact 230 is formed inside the contact hole via a barrier metal BM. The barrier metal BM and the contact 230 are formed by, for example, CVD. This completes the capacitive element 100 shown in FIG. 8 and the like.

[0119] As described above, the method for manufacturing the semiconductor device 10 includes the steps of forming the insulating layer 21 covering the surface of the substrate 20, forming the conductor 110 inside the insulating layer 21, removing a part of the insulating layer 21 to expose the side of the conductor 110 (specifically, the side of the first conductor including the barrier metal BM), forming the insulating film 130 on the side of the exposed conductor 110, and forming the conductor 120 at a position facing the conductor 110 with the insulating film 130 sandwiched therebetween. According to this method, the insulating film 130 is formed on the side of the conductor 110 by CVD film formation, and therefore can be formed as a film that is very thin compared to the thicknesses of the conductors 110 and 120. As a result, d in formula (1) becomes smaller, and the capacitance of the capacitive element 100 per unit area can be made larger than that of the conventional capacitance element.

[0120] In addition, the material of the insulating film 130 can be freely changed depending on the type of gas used in CVD, and can be appropriately selected according to the required capacitance value. In other words, unlike the comparative example described with reference to Fig. 25, it is not necessary to use the insulating layer 21 as an insulating film between the electrodes, and a material having a higher relative dielectric constant than the insulating layer 21 can be freely selected.

[0121] 13, the position where the opening 91 in the etching mask 90 is formed may be shifted from the target position in the x-direction or y-direction. However, even if such a positional shift occurs, the area of ​​the portion where the conductor 110 and the conductor 120 face each other does not change, and the thickness of the insulating film 130 does not change. In other words, in the manufacturing method described above, even if the positional shift of the opening 91 occurs, self-alignment is performed, and the capacitance of the capacitive element 100 is ensured with high accuracy according to the initial design value.

[0122] 12, when the conductor 110 is formed inside the recess 112, the conductor 110 is also formed inside the recess 212 located at the same height. The conductor 110 formed inside the recess 212 ultimately becomes the conductor 210, which is a wiring layer. The conductor 210, including the barrier metal BM covering part of its outer circumferential surface, corresponds to the "third conductor" in this embodiment.

[0123] Thus, in the first conductor formation step, the conductor 210 (third conductor) is formed at a position inside the insulating layer 21 at the same height as the conductor 110 (first conductor) of the capacitance element 100. The "position at the same height" in the above means a position where the conductor 110 and the conductor 210 of the capacitance element 100 at least partially overlap each other when viewed along a direction parallel to the surface of the substrate 20. For example, the lower end of the conductor 110 and the lower end of the conductor 210 may be at the same height position as in this embodiment, or may be at different height positions.

[0124] As a result, the semiconductor device 10 according to this embodiment has a configuration in which the capacitive element 100 is disposed in an empty space where no wiring (conductor 210) is formed at a specific height position inside the insulating layer 21. By miniaturizing the capacitive element 100 and disposing it in the empty space, the semiconductor device 10 can be further miniaturized.

[0125] Moreover, the capacitance element 100 is formed at the same height as the conductor 210, which is a wiring, and at a position separated from the conductor 210 in the x direction. Therefore, the capacitance component generated between the conductor 210 and the capacitance element 100 can be kept sufficiently small. In such a configuration, the capacitance component generated with the conductor 210 does not interfere with the configuration or arrangement of the capacitance element 100.

[0126] A second embodiment will be described below. In the following, differences from the first embodiment will be mainly described, and descriptions of commonalities with the first embodiment will be omitted as appropriate.

[0127] Fig. 21 shows the configuration of the capacitive element 100 in this embodiment from the same perspective and in the same manner as Fig. 8. As shown in Fig. 21, in this embodiment, the conductor 120 (second conductor) extends to a deeper position toward the substrate 20 side than the conductor 110 (first conductor).

[0128] Fig. 22 shows a state after an exposure step has been performed among the manufacturing steps for forming the capacitive element 100 of this embodiment. As is clear from comparing Fig. 22 with Fig. 15 (first embodiment), in the exposure step of this embodiment, the insulating layer 21 is etched until the height position of the bottom surface 21B is further below the height position of the lower end of the conductor 110. In other words, the insulating layer 21 is removed to a position deeper toward the substrate 20 than the conductor 110 (first conductor). The steps performed thereafter are the same as those in the first embodiment.

[0129] In the exposure step (FIG. 15) of the first embodiment, if the etching of the insulating layer 21 is not performed accurately and the height position of the bottom surface 21B is higher than the height position of the lower end of the conductor 110, the area of ​​the portion where the conductors 110 and 120 face each other will be reduced. As a result, the capacitance of the capacitance element 100 will be smaller than the initial design value. Thus, in the configuration of the first embodiment, there is a possibility that the capacitance of the capacitance element 100 will vary depending on the etching accuracy of the insulating layer 21.

[0130] In contrast, in the exposure step (FIG. 22) of this embodiment, as described above, the insulating layer 21 is etched until the height position of the bottom surface 21B is further below the height position of the lower end of the conductor 110. Even if the etching of the insulating layer 21 is not performed with precision and the height position of the bottom surface 21B fluctuates up or down from the position in FIG. 22, the area of ​​the portion where the conductors 110 and 120 face each other does not change. In this way, with the configuration of this embodiment, the variation in capacitance caused by the etching precision of the insulating layer 21 can be suppressed, and therefore the capacitance of the capacitive element 100 can be accurately ensured to be the same as the initial design value.

[0131] A third embodiment will be described below. In the following, differences from the first embodiment will be mainly described, and descriptions of commonalities with the first embodiment will be omitted as appropriate.

[0132] Fig. 23 shows the configuration of the capacitive element 100 of this embodiment from the same viewpoint and in the same manner as in Fig. 7. As shown in Fig. 23, in the capacitive element 100 of this embodiment, the conductor 120 is divided into a plurality of parts, and each conductor 120 is disposed at a position inside the conductor 110. In other words, the conductor 110 is disposed so as to surround each of the plurality of conductors 120. A plurality of contacts 230 are provided corresponding to each of the conductors 120. Even with such a configuration, it is possible to achieve the same effects as those described in the first embodiment.

[0133] In this embodiment, similarly to the second embodiment, the conductor 120 (second conductor) may extend to a deeper position toward the substrate 20 side than the conductor 110 (first conductor).

[0134] A fourth embodiment will be described below. In the following, differences from the first embodiment will be mainly described, and descriptions of commonalities with the first embodiment will be omitted as appropriate.

[0135] 24 shows the configuration of the capacitance element 100 in this embodiment from the same viewpoint and in the same manner as in FIG. 7. As shown in FIG. 24, in the capacitance element 100 of this embodiment, the conductor 110 is divided into a plurality of parts, and each conductor 110 is disposed inside the conductor 120. In other words, contrary to the third embodiment, the conductor 120 is disposed so as to surround each of the plurality of conductors 110. A plurality of contacts 150 are provided corresponding to each of the conductors 110. Even with such a configuration, it is possible to achieve the same effects as those described in the first embodiment.

[0136] In this embodiment, similarly to the second embodiment, the conductor 120 (second conductor) may extend to a deeper position toward the substrate 20 side than the conductor 110 (first conductor).

[0137] In the above, an example has been described in which the semiconductor device 10 is a non-volatile semiconductor memory device configured as a NAND type flash memory. However, the configuration described above is not limited to semiconductor memory devices and can be applied to other types of devices.

[0138] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Any design modifications made by a person skilled in the art to these specific examples are also included within the scope of the present disclosure as long as they have the features of the present disclosure. The elements of each of the above-mentioned specific examples and their arrangements, conditions, shapes, etc. are not limited to those exemplified and can be changed as appropriate. The combination of each of the elements of each of the above-mentioned specific examples can be changed as appropriate as long as no technical contradiction occurs. [Explanation of symbols]

[0139] 10: semiconductor device, 20: substrate, 21: insulating layer, 110, 120, 210: conductors, 130: insulating film.

Claims

1. an insulating layer covering a surface of the substrate; A first conductor provided on the insulating layer; a second conductor provided in the insulating layer at a position facing the first conductor along a first direction parallel to a surface of the substrate; a first contact extending in a depth direction of the substrate, connected to the first conductor, and disposed between the substrate and the first conductor; a first insulating film provided between the first conductor and the second conductor; a thickness of the first insulating film along the first direction is smaller than a thickness of the first conductor along the first direction and a thickness of the second conductor along the first direction; The second conductor extends to a deeper position toward the substrate than the first conductor.

2. The semiconductor device according to claim 1 , wherein the first insulating film has a higher dielectric constant than the insulating layer.

3. 2. The semiconductor device according to claim 1, further comprising a third conductor provided in said insulating layer, a portion of said first conductor being at the same position as a portion of said third conductor in a depth direction of said substrate.

4. The semiconductor device according to claim 1 , wherein the first conductor extends in a second direction that intersects the first direction and is parallel to the substrate, and the second conductor extends in the second direction.

5. a fourth conductor adjacent to the first conductor in the first direction and extending in the second direction; a second insulating film provided between the first conductor and the fourth conductor and having a thickness smaller than a thickness of the fourth conductor in the first direction; The semiconductor device according to claim 4 , wherein the second conductor and the fourth conductor are electrically connected to each other.

6. The semiconductor device according to claim 5 , wherein the first conductor is provided between the second conductor and the fourth conductor in the first direction.

7. forming an insulating layer covering a surface of the substrate; forming a first conductor within the insulating layer and a first contact extending in a depth direction of the substrate, connected to the first conductor, and disposed between the substrate and the first conductor; removing a portion of the insulating layer to expose a side surface of the first conductor; forming an insulating film on the exposed side surface of the first conductor; and forming a second conductor at a position facing the first conductor with the insulating film therebetween.

8. In the step of removing a portion of the insulating layer to expose a side surface of the first conductor, The method for manufacturing a semiconductor device according to claim 7 , wherein the insulating layer is removed to a position deeper toward the substrate than the first conductor.

9. In the step of forming a first conductor inside the insulating layer, 9. The method for manufacturing a semiconductor device according to claim 7, further comprising forming a third conductor at a position inside the insulating layer at the same height as the first conductor.

10. The semiconductor device according to claim 1 , wherein said first conductor is integral with said first contact.

11. 2 . The semiconductor device according to claim 1 , wherein a position of said first contact closest to said substrate in said depth direction is closer to said substrate than a position of said second conductor closest to said substrate.

12. 2. The semiconductor device according to claim 1, further comprising a second contact connected to said second conductor and disposed above said first contact.

13. 2. The semiconductor device according to claim 1, further comprising a wiring electrically connected to said first contact, said first contact being provided between said first conductor and said wiring.

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