Three-dimensional memory device having pocket structure in memory string and method thereof

Abstract

[0003] Embodiments of a 3D memory device having a pocket structure in a memory string and a method for forming the 3D memory device are disclosed. In an example, the 3D memory device includes a substrate, a selective epitaxial layer on the substrate, a memory stack including alternating conductive and dielectric layers on the selective epitaxial layer, a channel structure extending vertically within the memory stack, and a memory string including a pocket structure extending vertically within the selective epitaxial layer. The memory string includes a semiconductor channel extending vertically within the channel structure and extending vertically and laterally in the pocket structure and in contact with the selective epitaxial layer.

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for fabricating same. [Background technology]

[0002] Planar memory cells are being scaled to smaller dimensions through improvements in process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar process and fabrication techniques become difficult and costly. As a result, storage densities for planar memory cells are approaching upper limits.

[0003] 3D memory architectures can address the density limitations of planar memory cells and include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention [Problem to be solved by the invention]

[0004] Disclosed herein are embodiments of a 3D memory device having pocket structures in the memory strings, and methods for forming the 3D memory device. [Means for solving the problem]

[0005] In one example, a 3D memory device comprises a substrate, a selective epitaxial layer on the substrate, a memory stack comprising alternating conductive and dielectric layers on the selective epitaxial layer, a channel structure extending vertically within the memory stack, and a memory string comprising a pocket structure extending vertically within the selective epitaxial layer, the memory string comprising a semiconductor channel extending vertically within the channel structure and vertically and laterally within the pocket structure in contact with the selective epitaxial layer.

[0006] In another example, a 3D memory device comprises a substrate, a selective epitaxial layer on the substrate, a memory stack comprising alternating conductive and dielectric layers on the selective epitaxial layer, and a memory string comprising a channel structure extending vertically within the memory stack and a pocket structure extending vertically within the selective epitaxial layer, the lateral dimension of the channel structure being less than or equal to the lateral dimension of the pocket structure.

[0007] In yet another example, a method for forming a 3D memory device is disclosed. A selective epitaxial sacrificial layer is formed above a substrate, and a dielectric stack is formed above the selective epitaxial sacrificial layer. A first opening is formed vertically through the dielectric stack and the selective epitaxial sacrificial layer. A portion of the first opening is enlarged. A memory film and a semiconductor channel are then formed in that order along sidewalls and a bottom surface of the first opening. The selective epitaxial sacrificial layer is removed to form a cavity exposing a portion of the memory film. The portion of the memory film exposed in the cavity is removed to expose a portion of the semiconductor channel. A selective epitaxial layer is epitaxially grown from the substrate to fill the cavity and contact a portion of the semiconductor channel.

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0009] [Figure 1A] 1A-1D are diagrams of an example fabrication process for forming a 3D memory device. [Figure 1B] 1A-1D are diagrams of an example fabrication process for forming a 3D memory device. [Figure 1C] 1A-1D are diagrams of an example fabrication process for forming a 3D memory device. [Diagram 2] 1 illustrates a cross-sectional view of an example 3D memory device having pocket structures in memory strings, according to some embodiments of the present disclosure. [Figure 3A] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3B] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3C] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3D] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3E] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3F] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3G] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3H] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3I] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3J]1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3K] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 3L] 1A-1C illustrate an example fabrication process for forming a 3D memory device having pocket structures in the memory strings, according to some embodiments of the present disclosure. [Figure 4A] 1 is a flow diagram of an example method for forming a 3D memory device having pocket structures in memory strings, according to some embodiments of the present disclosure. [Figure 4B] 1 is a flow diagram of an example method for forming a 3D memory device having pocket structures in memory strings, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0011] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be employed in a variety of other applications.

[0012] It is noted that references herein to "one embodiment," "embodiment," "example embodiment," "some embodiments," and the like, mean that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in the context of an embodiment, it is within the knowledge of one of ordinary skill in the art to bring about such feature, structure, or characteristic in the context of other embodiments, whether or not expressly described.

[0013] Generally, terminology may be understood, at least in part, from usage in context. For example, the term "one or more" as used herein may be used in the singular sense to describe any feature, structure, or characteristic, or in the plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, terms such as "a" or "the" may be understood to convey either the singular use or the plural use, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive collection of factors, but may instead permit the presence of additional factors not necessarily explicitly recited, again depending at least in part on the context.

[0014] It should be readily understood that the meanings of "on", "above", and "across" in this disclosure should be interpreted in the broadest manner such that "on" does not only mean "directly" something, but also includes the meaning of being "at" something with an intermediate feature or layer between them, and that "above" or "across" may not only mean "above" or "across" something, but also include the meaning of "above" or "across" something without an intermediate feature or layer between them (i.e., directly on top of something).

[0015] Additionally, spatially relative terms such as "below," "below," "lower," "above," "above" and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be similarly interpreted accordingly.

[0016] As used herein, the term "substrate" refers to a material onto which a subsequent layer of material is added. The substrate itself may be patterned. Materials added onto the substrate may be patterned or left unpatterned. Additionally, substrates may include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be formed from non-conductive materials such as glass, plastic, or sapphire wafers.

[0017] As used herein, the term "layer" refers to a material portion that includes a region of thickness. A layer may extend throughout an underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. Furthermore, a layer may be a homogeneous or non-homogeneous region of a continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal surfaces between or at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers, and / or may have one or more layers above, above, and / or below. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor layers and contact layers (in which interconnect lines and / or VIA contacts are formed), and one or more dielectric layers.

[0018] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter for a component or process operation that is set during the design phase of a product or during a process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" refers to a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, the term "3D memory device" refers to a semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) in a substrate that is oriented on its side such that the memory strings extend perpendicular to the substrate. As used herein, the term "vertical" refers to a nominal right angle to the lateral plane of the substrate.

[0020] In some 3D NAND memory devices, the semiconductor plug is selectively grown to surround the sidewall of the NAND memory string. Compared with another type of semiconductor plug formed at the bottom of the NAND memory string, the formation of the sidewall semiconductor plug avoids etching the memory film and the semiconductor channel at the bottom of the channel hole, thereby increasing the process window, especially when fabricating 3D NAND memory devices with advanced technologies such as 96 or more levels with multiple deck architecture. However, since some processes for forming the sidewall semiconductor plug require etching the bottom sacrificial layer and the memory film to expose the semiconductor channel that contacts the sidewall semiconductor plug, the removal of the sacrificial layer and the memory film under the dielectric stack with an increased number of levels weakens the bottom structure of the NAND memory string, which may cause peeling problems or even destruction.

[0021] For example, Figures 1A-1C show an exemplary fabrication process for forming a 3D memory device. As shown in Figure 1A, a dielectric stack 104 includes alternating gate sacrificial layers 106 and dielectric layers 108 formed above a substrate 102. After all fabrication processes are completed, the dielectric stack 104 is replaced with a memory stack by a gate exchange process, which replaces each gate sacrificial layer 106 with a conductive layer. A selective epitaxial sacrificial layer 110 and a pad oxide layer 112 are vertically formed between the dielectric stack 104 and the substrate 102. A NAND memory string 114 extends vertically in the dielectric stack 104 through the selective epitaxial sacrificial layer 110 and the pad oxide layer 112 into the substrate 102. The NAND memory string 114 includes a memory film 116 including a block layer 118, a storage layer 120, and a tunnel layer 122 along the sidewall of the NAND memory string 114. The NAND memory string 114 further comprises a semiconductor channel 124 and a cap layer 126 surrounded by the memory membrane 116 .

[0022] As shown in FIG. 1A, a slit 128 is formed vertically through the dielectric stack 104 into the selective epitaxial sacrificial layer 110. A protective layer 130 is formed to cover the sidewalls of the slit 128. The bottom surface of the protective layer 130 is removed to expose a portion of the selective epitaxial sacrificial layer 110. As shown in FIG. 1B, the fabrication process proceeds such that the selective epitaxial sacrificial layer 110 (as shown in FIG. 1A) is removed through the slit 128 to form a cavity 132 that exposes a portion of the memory film 116. As shown in FIG. 1C, the fabrication process proceeds such that the portion of the memory film 116 exposed in the cavity 132 is removed to expose a portion of the semiconductor channel 124 (as circled at 134). Before cavity 132 is filled with a selective epitaxial layer (not shown) in a subsequent process, portion 134 is required to support the entire upper structure, such as dielectric stack 104, and therefore becomes a weak point (hereinafter "weak point 134") that can cause peeling problems or even breakage, reducing yield.

[0023] Various embodiments according to the present disclosure provide an improved structure and a method of fabricating the structure with greater mechanical strength to support the structure above during the fabrication process between the removal of the selective epitaxial sacrificial layer and the formation of the selective epitaxial layer. In some embodiments, a pocket structure of a 3D type NAND memory string extending in the selective epitaxial sacrificial layer is formed by etching back the selective epitaxial sacrificial layer. The semiconductor channel and cap layer in the pocket structure can have larger dimensions compared to their counterparts at the weak point 134 in FIG. 1C to provide stronger mechanical support, thereby reducing the risk of fracture and increasing the yield. Furthermore, no additional fabrication process is required other than the etch-back process, which increases the fabrication cost and complexity.

[0024] FIG. 2 illustrates a cross-sectional view of an example 3D memory device 200 having a pocket structure in a memory string, according to some embodiments of the present disclosure. The 3D memory device 200 may include a substrate 202, which may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, the substrate 202 is a thinned substrate (e.g., a semiconductor layer) that has been thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. It is noted that x- and y-axes are included in FIG. 2 to further illustrate the spatial relationship between components in the 3D memory device 200. The substrate 202 of the 3D memory device 200 includes two lateral surfaces (e.g., a top surface and a bottom surface) that extend laterally in the x-direction (i.e., the lateral direction). As used herein, whether a component (e.g., layer or device) of a 3D memory device (e.g., 3D memory device 200) is "on," "above," or "below" another component (e.g., layer or device) is determined relative to the substrate (e.g., substrate 202) of the 3D memory device in the y-direction (i.e., vertical direction) when the substrate is positioned at the bottom-most plane of the 3D memory device in the y-direction. The same concepts for describing spatial relationships apply throughout this disclosure.

[0025] The 3D memory device 200 may be part of an integral 3D memory device. The term "integral" means that the components of the 3D memory device (e.g., peripheral devices and memory array devices) are formed on a single substrate. For an integral 3D memory device, fabrication faces additional constraints due to the convolution of peripheral device processing and memory array device processing. For example, fabrication of memory array devices (e.g., NAND memory strings) is constrained by thermal budgets associated with peripheral devices formed or formed on the same substrate.

[0026] Alternatively, the 3D memory device 200 may be part of a non-integral 3D memory device in which components (e.g., peripheral devices and memory array devices) may be formed separately in different substrates and then bonded, such as in a face-to-face manner. In some embodiments, the memory array device substrate (e.g., substrate 202) remains as the substrate of the bonded non-integral 3D memory device, and the peripheral devices (e.g., including any suitable digital, analog, and / or mixed signal peripheral circuitry used to facilitate operation of the 3D memory device 200, such as page buffers, decoders, and latches, not shown) are flipped for hybrid bonding to face down toward the memory array devices (e.g., NAND memory strings). In some embodiments, the memory array device substrate (e.g., substrate 202) is flipped for hybrid bonding to face down toward the peripheral devices (not shown), such that it is understood that in the bonded non-integral 3D memory device, the memory array devices are above the peripheral devices. The memory array device substrate (e.g., substrate 202) can be a thinned substrate (not a substrate of a bonded non-integral 3D memory device) and back-end-of-line (BEOL) interconnects of the non-integral 3D memory device can be formed on the back side of the thinned memory array device substrate.

[0027] As shown in FIG. 2, the 3D memory device 200 also includes a selective epitaxial layer 210 in the substrate 202. The selective epitaxial layer 210 may be an example of a "sidewall semiconductor plug" as previously described. The selective epitaxial layer 210 may include a semiconductor material, such as silicon, that is epitaxially grown upward from the substrate 202. In some embodiments, the substrate 202 is a silicon substrate, and the selective epitaxial layer 210 includes single crystal silicon of the same material as the substrate 202. Stated differently, the selective epitaxial layer 210 may include an epitaxially grown semiconductor layer that is the same material as that of the substrate 202. In some embodiments, the selective epitaxial layer 210 serves as at least a portion of an array common source (ACS) for the array of NAND memory strings 212.

[0028] In some embodiments, the 3D memory device 200 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings 212 that extend vertically above the substrate 202. The memory array device may include NAND memory strings 212 that extend through a plurality of pairs (referred to herein as "conductive / dielectric layer pairs") that include a conductive layer 206 and a dielectric layer 208. The stacked conductive / dielectric layer pairs are also referred to herein as a "memory stack" 204. The number of conductive / dielectric layer pairs in the memory stack 204 (e.g., 32, 64, 96, 128, 160, 192, 256, etc.) determines the number of memory cells in the 3D memory device 200. The memory stack 204 may include a plurality of alternating conductive and dielectric layers 206 and 208 on top of the selective epitaxial layer 210. The conductive and dielectric layers 206 and 208 in the memory stack 204 may alternate in the vertical direction. The conductive layer 206 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The dielectric layer 208 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Although not shown in FIG. 2, it is understood that in some embodiments, the memory stack 204 may have a multiple deck architecture, such as a dual deck architecture with a lower memory deck and an upper memory deck above the lower memory deck.

[0029] As shown in FIG. 2, the NAND memory string 212 may include a channel structure 213 extending vertically in the memory stack 204 and a pocket structure 226 extending below the channel structure 213 in the selective epitaxial layer 210. The NAND memory string 212 may include a channel hole filled with a semiconductor material (e.g., as the semiconductor channel 222) and a dielectric material (e.g., as the memory film 214). In some embodiments, the semiconductor channel 222 includes silicon, such as amorphous silicon, polysilicon, or single crystal silicon. In one example, the semiconductor channel 222 includes polysilicon. In some embodiments, the memory film 214 is a composite layer including a tunnel layer 220, a storage layer 218 (also known as a "charge trapping layer"), and a block layer 216. The remaining space of the channel hole may be partially or completely filled with a cap layer 224 including a dielectric material such as silicon oxide. The channel structure 213 may have a cylindrical shape (e.g., a pillar shape). The cap layer 224, the semiconductor channel 222, the tunnel layer 220, the storage layer 218, and the block layer 216 are arranged in this order radially from the center of the pillar to the outer surface, according to some embodiments. The tunnel layer 220 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 218 may include silicon nitride, silicon oxynitride, or any combination thereof. The block layer 216 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 214 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0030] In some embodiments, the conductive layers 206 (each part of a word line) in the memory stack 204 function as gate conductors for memory cells in the NAND memory string 212. The conductive layers 206 may comprise multiple control gates for multiple NAND memory cells and may run laterally as word lines that terminate at the edges of the memory stack 204 (e.g., in a staircase structure of the memory stack 204). In some embodiments, the memory cell transistors in the NAND memory string 212 comprise a gate conductor (i.e., the portion of the conductive layer 206 that abuts the channel structure 213) made from W, an adhesion layer (not shown) comprising titanium / titanium nitride (Ti / TiN) or tantalum / tantalum nitride (Ta / TaN), a gate dielectric layer (not shown) made from a high-k dielectric material, and the channel structure 213 described in detail above.

[0031] In some embodiments, the NAND memory string 212 further comprises a channel plug 225 at an upper portion (e.g., top end) of the NAND memory string 212. As used herein, the "top end" of a component (e.g., NAND memory string 212) is the end further from the substrate 202 in the y-direction, and the "bottom end" of a component (e.g., NAND memory string 212) is the end closer to the substrate 202 in the y-direction when the substrate 202 is positioned at the bottommost plane of the 3D memory device 200. The channel plug 225 may be the top end of the semiconductor channel 222 or another structure in contact with the top end of the semiconductor channel 222. The channel plug 225 may include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 225 functions as a drain of the NAND memory string 212.

[0032] 1C in which the NAND memory string 114 has a weak point 134 extending in the cavity 132 in which the selective epitaxial layer is formed, the NAND memory string 114 may include a pocket structure 226 extending in the selective epitaxial layer 210 to provide stronger mechanical support to the structures above, such as the memory stack 204, during the fabrication process. Unlike FIG. 1C in which the NAND memory string 114 includes only a portion of the semiconductor channel 124 that extends vertically at the weak point 134 (without the memory film 116), the NAND memory string 114 may include a portion of the semiconductor channel 124 that extends vertically and laterally at the pocket structure 226. As a result, unlike FIG. 1C where the lateral dimension (e.g., width in the x-direction) of the NAND memory string 114 at the weak spot 134 is smaller than the lateral dimension of the NAND memory string 114 above, the lateral dimension W1 (e.g., width in the x-direction) of the channel structure 213 in FIG. 2 is less than or equal to the lateral dimension W2 (e.g., width in the x-direction) of the pocket structure 226 according to some embodiments. In some embodiments, the lateral dimension W1 of the channel structure 213 in FIG. 2 is nominally the same as the lateral dimension W2 of the pocket structure 226. That is, the NAND memory string 212 may have the same diameter in the vertical direction in both the channel structure 213 and the pocket structure 226.

[0033] As shown in FIG. 2, the semiconductor channel 222 in the 3D memory device 200 may extend vertically in the channel structure 213 and vertically and laterally in the pocket structure 226 to contact the selective epitaxial layer 210. In some embodiments, the selective epitaxial layer 210 includes single crystal silicon and the semiconductor channel 222 includes polysilicon. A portion of the semiconductor channel 222 in the pocket structure 226 may contact the selective epitaxial layer 210 to form an electrical coupling between the NAND memory string 212 and the selective epitaxial layer 210. In some embodiments, the semiconductor channel 222 extends laterally in the pocket structure 226 over a distance that is nominally the same as the thickness of the memory film 214 (i.e., the total thickness of the block layer 216, the storage layer 218, and the tunnel layer 220). For example, the semiconductor channel 222 may extend laterally in the pocket structure 226 over about 20 nm, such as 20 nm. As a result, according to some embodiments, the distance between the semiconductor channels 222 formed on opposing sidewalls in the pocket structure 226 is greater than the distance between the semiconductor channels 222 formed on opposing sidewalls in the channel structure 213. In some embodiments, the semiconductor channels 222 are flat at the bottom ends of the NAND memory strings 212 due to the use of the selective epitaxial layer 210 as a sidewall semiconductor plug instead of a lower semiconductor plug that would require removal of at least a portion of the semiconductor channel 222 at the bottom ends of the NAND memory strings.

[0034] 2, according to some embodiments, the cap layer 224 of the 3D memory device 200, which is surrounded by the semiconductor channel 222, has a lateral dimension at the pocket structure 226 that is larger than its lateral dimension at the channel structure 213. Unlike FIG. 1C, where the cap layer 126 has the same lateral dimension in the vertical dimension, the cap layer 224 of the 3D memory device 200 can be thicker at the pocket structure 226 to provide increased mechanical strength together with the expanding semiconductor channel 222 to support the structures above, such as the memory stack 204.

[0035] In some embodiments, the memory film 214 in the 3D memory device 200 is laterally between the memory stack 204 and the semiconducting channel 222 in the channel structure 213. As shown in Figure 2, the memory film 214 can extend vertically in the channel structure 213 and laterally in the pocket structure 226. Unlike Figure 1C where the memory film 116 is removed at the weak points 134, at least a portion of the laterally extending memory film 214 can remain in the pocket structure 226 to provide additional support to the structures above, such as the memory stack 204.

[0036] In some embodiments, the 3D memory device 200 further comprises a source contact structure 228. The source contact structure 228 may extend vertically through the conductive / dielectric layer pairs in the memory stack 204 and contact the selective epitaxial layer 210. The source contact structure 228 may also extend laterally (e.g., perpendicular to the x- and y-directions) to separate the memory stack 204 into multiple blocks. The source contact structure 228 may include an opening (e.g., a slit) that is filled with a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof, to form a source conductor 232. The source contact structure 228 may further comprise a spacer 230 having a dielectric material, such as silicon oxide, laterally between the source conductor 232 and the memory stack 204 to electrically insulate the source conductor 232 from the surrounding conductive layer 206 in the memory stack 204. As a result, the multiple source contact structures 228 can divide the 3D memory device 200 into multiple memory blocks and / or memory fingers. In some embodiments, the source conductor 232 comprises polysilicon at its lower portion in contact with the selective epitaxial layer 210, which may comprise, for example, single crystal silicon, and a metal (e.g., W) at its upper portion in contact with a metal interconnect (not shown) to form an electrical connection between the selective epitaxial layer 210 (e.g., as a source of the NAND memory string 212) and the metal interconnect.

[0037] 3A-3L illustrate an example fabrication process for forming a 3D memory device having a pocket structure in a memory string according to some embodiments of the present disclosure. FIG. 4A-4B illustrates a flow diagram of an example method 400 for forming a 3D memory device having a pocket structure in a memory string according to some embodiments of the present disclosure. An example of a 3D memory device depicted in FIG. 3A-3L and FIG. 4A-4B is the 3D memory device 200 depicted in FIG. 2. FIG. 3A-3L and FIG. 4A-4B are described together. It is understood that the operations illustrated in the method 400 are not exhaustive and that other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 4A-4B.

[0038] 4A, the method 400 begins at operation 402, where a selective epitaxial sacrificial layer is formed over a substrate and a dielectric stack is formed over the selective epitaxial sacrificial layer. The substrate may be a silicon substrate. The selective epitaxial sacrificial layer may be a polysilicon substrate. The dielectric stack may comprise a plurality of alternating sacrificial and dielectric layers.

[0039] As shown in FIG. 3A, a selective epitaxial sacrificial layer 306 is formed above a silicon substrate 302. The selective epitaxial sacrificial layer 306 may be formed by depositing polysilicon or any other suitable sacrificial material (e.g., carbon) that can be subsequently selectively removed using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, an oxide pad layer 304 is formed between the selective epitaxial sacrificial layer 306 and the silicon substrate 302 by depositing a dielectric material, such as silicon oxide, on the silicon substrate 302 prior to the formation of the selective epitaxial sacrificial layer 306 or by thermal oxidation. A dielectric stack 312 including multiple pairs of a first dielectric layer (also known as a "gate sacrificial layer 308") and a second dielectric layer 310 (together referred to herein as a "dielectric layer pair") is formed on the selective epitaxial sacrificial layer 306. According to some embodiments, the dielectric stack 312 includes alternating gate sacrificial layers 308 and dielectric layers 310. The dielectric layers 310 and the gate sacrificial layers 308 may be alternately deposited on the selective epitaxial sacrificial layer 306 above the silicon substrate 302 to form the dielectric stack 312. In some embodiments, each dielectric layer 310 includes a layer of silicon oxide and each gate sacrificial layer 308 includes a layer of silicon nitride. The dielectric stack 312 may be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0040] The method 400 proceeds to operation 404 as shown in FIG. 4A, where a first opening is formed extending vertically through the dielectric stack and the selective epitaxial sacrificial layer. As shown in FIG. 3A, a channel hole 314 is an opening formed extending vertically through the dielectric stack 312 and the selective epitaxial sacrificial layer 306. In some embodiments, multiple openings are formed through the dielectric stack 312 and the selective epitaxial sacrificial layer 306, such that each opening is a location for growing an individual NAND memory string in a later process. In some embodiments, the fabrication process for forming the channel hole 314 includes wet etching, such as deep reactive ion etching (DRIE), and / or dry etching. In some embodiments, the channel hole 314 extends further into an upper portion of the silicon substrate 302 through the pad oxide layer 304. The etching process through the dielectric stack 312, the selective epitaxial sacrificial layer 306, and the pad oxide layer 304 may not stop at the top surface of the silicon substrate 302, and may continue to etch away portions of the silicon substrate 302. In some embodiments, after etching through the dielectric stack 312, the selective epitaxial sacrificial layer 306, and the pad oxide layer 304, another etching process is used to etch away portions of the silicon substrate 302.

[0041] The method 400 proceeds to operation 406 as shown in FIG. 4A where a portion of the first opening extending vertically through the selective epitaxial sacrificial layer is enlarged. In some embodiments, the selective epitaxial sacrificial layer is etched back through the first opening to enlarge the portion of the first opening. As shown in FIG. 3B , a portion 316 of the channel hole 314 extending vertically through the selective epitaxial sacrificial layer 306 is enlarged. For example, the diameter of the portion of the channel hole 314 that passes through the selective epitaxial sacrificial layer 306 can be increased by etching back the portion of the selective epitaxial sacrificial layer 306 surrounding the channel hole 314. The etch back can be performed by wet etching and / or dry etching, such as by applying a wet etching etchant through the channel hole 314. In one example, tetramethylammonium hydroxide (TMAH) can be applied through the channel holes 314 to etch the polysilicon-containing selective epitaxial sacrificial layer 306. The degree of enlargement, i.e., the amount of selective epitaxial sacrificial layer 306 that is etched, can be controlled by controlling the etching conditions, such as, for example, etchant concentration, temperature, duration, etc.

[0042] The method 400 proceeds to operation 408 as shown in FIG. 4A where a memory film and a semiconductor channel are then formed, in that order, along the sidewalls and bottom surface of the first opening. In some embodiments, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are then deposited, in that order, on the sidewalls and bottom surface of the first opening to form the memory film. In some embodiments, a polysilicon layer is deposited over the second silicon oxide layer to form the semiconductor channel. According to some embodiments, the first silicon oxide layer, the silicon nitride layer, the second silicon oxide layer, and the polysilicon layer extend laterally within the enlarged portion of the first opening.

[0043] As shown in FIG. 3C, the memory film 318 (including the block layer 320, the storage layer 322, and the tunnel layer 324) and the semiconductor channel 326 are then formed in this order along the sidewall and bottom surface of the channel hole 314 (as shown in FIG. 3B). In some embodiments, the memory film 318 is first deposited along the sidewall and bottom surface of the channel hole 314, and then the semiconductor channel 326 is deposited over the memory film 318. The block layer 320, the storage layer 322, and the tunnel layer 324 can then be deposited in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form the memory film 318. The semiconductor channel 326 can be formed by depositing a semiconductor material, such as polysilicon, on the tunnel layer 324 of the memory film 318 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are then deposited to form the memory membrane 318 and the semiconductor channel 326.

[0044] As shown in FIG. 3C, a cap layer 328 is formed over the semiconductor channel 326 in the channel hole 314 (shown in FIG. 3B) to completely or partially (e.g., without or with voids) fill the channel hole 314. The cap layer 328 may be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Thereby, a NAND memory string 330 is formed, including a vertically extending channel structure 331 in the dielectric stack 312 (later replaced by a memory stack) and a vertically extending pocket structure 332 in the selective epitaxial sacrificial layer 306 (later replaced by a selective epitaxial layer).

[0045] As shown in FIG. 3C, the memory film 318, the semiconductor channel 326, and the cap layer 328 may be further deposited along the sidewalls of the widened portion 316 of the channel hole 314 (as shown in FIG. 3B) to form a pocket structure 332. In some embodiments, each of the block layer 320, the storage layer 322, the tunnel layer 324, the semiconductor channel 326, and the cap layer 328 is deposited using ALD to control the thickness of each layer such that each layer follows the contour of the sidewalls of the channel hole 314, including the widened portion 316. As a result, the block layer 320 (e.g., including a first silicon oxide layer), the storage layer 322 (e.g., including a silicon nitride layer), the tunnel layer 324 (e.g., including a second silicon oxide layer), and the semiconductor channel 326 (e.g., including a polysilicon layer) extend laterally within the widened portion 316 of the channel hole 314, according to some embodiments. In some embodiments, the channel hole 314 is etched back in FIG. 3B over a distance that is nominally the same as the thickness of the memory film 318 (i.e., the total thickness of the block layer 320, the storage layer 322, and the tunnel layer 324). For example, the thickness of each of the memory films 318 and the etch-back distance of the extension portion 316 is about 20 nm.

[0046] The method 400 proceeds to operation 410 as shown in FIG. 4A where a second opening is formed extending vertically through the dielectric stack to expose a portion of the selective epitaxial sacrificial layer. As shown in FIG. 3D, a slit 334 is an opening formed extending vertically through the dielectric stack 312 to expose a portion of the selective epitaxial sacrificial layer 306. In some embodiments, the fabrication process for forming the slit 334 includes wet etching, such as DRIE, and / or dry etching. In some embodiments, the slit 334 extends further into an upper portion of the selective epitaxial sacrificial layer 306. The etching process through the dielectric stack 312 may not stop at the top surface of the selective epitaxial sacrificial layer 306 and may continue to etch a portion of the selective epitaxial sacrificial layer 306. In some embodiments, after etching through the dielectric stack 312, another etching process is used to etch a portion of the selective epitaxial sacrificial layer 306.

[0047] 4A, the method 400 proceeds to operation 412, where a protective layer is formed covering the sidewalls of the second opening. In some embodiments, to form the protective layer, a high-k dielectric layer is formed on the sidewalls and bottom surface of the second opening, and a portion of the high-k dielectric layer at the bottom surface of the second opening is etched to expose a portion of the selective epitaxial sacrificial layer.

[0048] As shown in FIG. 3E, a protective layer 336 is formed along the sidewalls and bottom surface of the slit 334. In some embodiments, the protective layer 336 is also formed on the dielectric stack 312. The protective layer 336 may be formed by depositing a high-k dielectric layer (e.g., aluminum oxide) or any other sacrificial material, which is subsequently removed, on the sidewalls and bottom surface of the slit 334 using one or more thin film deposition processes, such as PVD, CVD, ALD, or any combination thereof. In one example, the protective layer 336 may be deposited using ALD. The material of the protective layer 336 may be any suitable sacrificial material different from the material of the selective epitaxial sacrificial layer 306 (e.g., polysilicon) and the material of the memory film 318 (e.g., silicon oxide and silicon nitride) such that the protective layer 336 can withstand during the removal of the selective epitaxial sacrificial layer 306 and the removal of the portion of the memory film 318 in the pocket structure 332 to protect the dielectric stack 312.

[0049] 3F, a portion of the protective layer 336 at the bottom of the slit 334 is removed using dry and / or wet etching to expose a portion of the selective epitaxial sacrificial layer 306. As a result, according to some embodiments, the protective layer 336 covers the sidewalls of the slit 334 but does not cover the entire bottom surface of the slit 334 for later processes.

[0050] The method 400 proceeds to operation 414 as shown in FIG. 4B where the selective epitaxial sacrificial layer is removed to form a cavity exposing a portion of the memory film. In some embodiments, the selective epitaxial sacrificial layer is etched through the second opening to remove the selective epitaxial sacrificial layer. As shown in FIG. 3G, the selective epitaxial sacrificial layer 306 (shown in FIG. 3F) is removed by wet etching and / or dry etching to form a cavity 338. In some embodiments, the selective epitaxial sacrificial layer 306 comprises polysilicon and the protective layer 336 comprises a high-k dielectric material and the selective epitaxial sacrificial layer 306 is etched by applying a TMAH etchant through the slits 334, which may be stopped by the high-k dielectric material of the protective layer 336 and the dielectric material of the memory film 318 at the pocket structure 332. That is, according to some embodiments, removal of the selective epitaxial sacrificial layer 306 does not remove the dielectric stack 312 and pocket structure 332 of the NAND memory string 330. As shown in FIG. 3G, the pocket structure 332 can provide enhanced mechanical support to the upper structure, even after removal of the selective epitaxial sacrificial layer 306, due to the enlarged dimensions and characteristic shapes of the memory film 318, the semiconductor channel 326, and the cap layer 328 therein.

[0051] The method 400 proceeds to operation 416 as shown in FIG. 4B, where a portion of the memory film exposed in the cavity is removed to expose a portion of the semiconductor channel. In some embodiments, to remove the portion of the memory film exposed in the cavity, the portion of the memory film is etched until stopped by a portion of the semiconductor channel. As shown in FIG. 3H, a portion of the memory film 318 exposed in the cavity 338 (as shown in FIG. 3G) is removed to expose a portion of the semiconductor channel 326 in the pocket structure 340. In some embodiments, the block layer 320 (e.g., including silicon oxide), the storage layer 322 (e.g., including silicon nitride), and a portion of the tunnel layer (e.g., including silicon oxide) are etched by applying an etchant, such as phosphoric acid to etch silicon nitride and hydrofluoric acid to etch silicon oxide, through the slit 334 and the cavity 338. The etching may be stopped by the protective layer 336 and the semiconductor channel 326. That is, according to some embodiments, removal of the portion of the memory film 318 exposed in the cavity 338 does not remove the dielectric stack 312 (protected by the protective layer 336) and the pocket structure 340 (e.g., the polysilicon-containing semiconductor channel 326 and the cap layer 328 surrounded by the semiconductor channel 326) of the NAND memory string 330. As shown in FIG. 3H, the pocket structure 340 can provide enhanced mechanical support to the upper structure even after removal of the portion of the memory film 318 due to the enlarged dimensions and characteristic shapes of the memory film 318, the semiconductor channel 326, and the cap layer 328 therein.

[0052] The method 400 proceeds to operation 418 as shown in FIG. 4B, where a selective epitaxial layer is epitaxially grown from the substrate to fill the cavity and contact a portion of the semiconductor channel. As shown in FIG. 3I, a selective epitaxial layer 342 is formed by selectively filling the cavity 338 (as shown in FIG. 3H) with single crystal silicon epitaxially grown upward from the silicon substrate 302. The fabrication process for epitaxially growing selective epitaxial layer 342 may include pre-cleaning the cavity 338, followed by, for example, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. The selective epitaxial layer 342 may contact a sidewall of a portion of the semiconductor channel 326 in the pocket structure 340 of the NAND memory string 330.

[0053] The method 400 proceeds to operation 420, as shown in Figure 4B, where the protective layer is removed. As shown in Figure 3J, the protective layer 336 (as shown in Figure 3I) covering the sidewalls of the slit 334 is removed using wet and / or dry etching to expose the gate sacrificial layer 308 (as shown in Figure 3I) of the dielectric stack 312 from the slit 334 for later processing.

[0054] The method 400 proceeds to operation 422 as shown in FIG. 4B, where a memory stack is formed to replace the dielectric stack through the second opening. As shown in FIG. 3J and FIG. 3K, after removal of the protective layer 336, a memory stack 346 may be formed by a gate replacement process, i.e., by replacing the gate sacrificial layer 308 (as shown in FIG. 3I) with a conductive layer 344. Thus, the memory stack 346 may comprise alternating conductive layers 344 and dielectric layers 310 on the selective epitaxial layer 342 above the silicon substrate 302. As shown in FIG. 3J, to form the memory stack 346, the gate sacrificial layer 308 (as shown in FIG. 3I) is removed by applying an etchant through the slits 334 to form a plurality of lateral recesses 341. As shown in FIG. 3K, the conductive layer 344 may be deposited in the lateral recesses 341 using one or more thin film deposition processes, such as PVD, CVD, ALD, or any combination thereof.

[0055] The method 400 continues to operation 424 as shown in FIG. 4B, where selective epitaxy is performed. Layer A source contact structure is formed in the second opening and extends vertically through the memory stack to contact the selective epitaxial layer 342. As shown in FIG. 3K, a source contact structure 352 including a source conductor 350 and a spacer 348 surrounding the source conductor 350 is formed in the slit 334 (as shown in FIG. 3K). In some embodiments, the spacer 348 including a dielectric material such as silicon oxide and the source conductor 350 including one or more conductive materials such as polysilicon and tungsten are then deposited in this order in the slit 334 using one or more thin film deposition processes such as PVD, CVD, ALD, electroplating, chemical plating, or any combination thereof to fill the slit 334. The source contact structure 352 can contact the selective epitaxial layer 342 as shown in FIG. 3L.

[0056] According to one aspect of the disclosure, a 3D memory device comprises a substrate, a selective epitaxial layer on the substrate, a memory stack comprising alternating conductive and dielectric layers on the selective epitaxial layer, a channel structure extending vertically within the memory stack, and a memory string comprising a pocket structure extending vertically within the selective epitaxial layer, the memory string comprising a semiconductor channel extending vertically within the channel structure and vertically and laterally within the pocket structure in contact with the selective epitaxial layer.

[0057] In some embodiments, the lateral dimension of the channel structure is less than or equal to the lateral dimension of the pocket structure, hi some embodiments, the lateral dimension of the channel structure is the same as the lateral dimension of the pocket structure.

[0058] In some embodiments, the memory string comprises a memory film laterally between the memory stack and the semiconductor channel in the channel structure, the memory film extending vertically in the channel structure and laterally in the pocket structure, hi some embodiments, the memory film comprises a blocking layer, a storage layer, and a tunnel layer.

[0059] In some embodiments, the memory string comprises a cap layer surrounded by the semiconductor channel, the lateral dimensions of the cap layer in the pocket structure being greater than the lateral dimensions of the cap layer in the channel structure.

[0060] In some embodiments, the selective epitaxial layer comprises single crystal silicon and the semiconductor channel comprises polysilicon.

[0061] In some embodiments, the semiconducting channel extends laterally within the pocket structure over about 20 nm.

[0062] In some embodiments, the semiconductor channel is flat at the bottom end of the memory string.

[0063] In some embodiments, the 3D memory device further comprises a source contact structure extending vertically through the memory stack and in contact with the selective epitaxial layer.

[0064] According to another aspect of the disclosure, a 3D memory device comprises a substrate, a selective epitaxial layer on the substrate, a memory stack comprising alternating conductive and dielectric layers on the selective epitaxial layer, and a memory string comprising a channel structure extending vertically within the memory stack and a pocket structure extending vertically within the selective epitaxial layer, the lateral dimensions of the channel structure being less than or equal to the lateral dimensions of the pocket structure.

[0065] In some embodiments, the lateral dimension of the channel structure is the same as the lateral dimension of the pocket structure.

[0066] In some embodiments, the memory string comprises a semiconductor channel that extends vertically within the channel structure, extends vertically and laterally within the pocket structure, and is in contact with the selective epitaxial layer.

[0067] In some embodiments, the semiconducting channel extends laterally within the pocket structure over about 20 nm.

[0068] In some embodiments, the memory string comprises a memory film laterally between the memory stack and the semiconductor channel in the channel structure, the memory film extending vertically in the channel structure and laterally in the pocket structure, hi some embodiments, the memory film comprises a blocking layer, a storage layer, and a tunnel layer.

[0069] In some embodiments, the memory string comprises a cap layer surrounded by the semiconductor channel, the lateral dimensions of the cap layer in the pocket structure being greater than the lateral dimensions of the cap layer in the channel structure.

[0070] In some embodiments, the selective epitaxial layer comprises single crystal silicon and the semiconductor channel comprises polysilicon.

[0071] In some embodiments, the semiconductor channel is flat at the bottom end of the memory string.

[0072] In some embodiments, the 3D memory device further comprises a source contact structure extending vertically through the memory stack and in contact with the selective epitaxial layer.

[0073] According to yet another aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A selective epitaxial sacrificial layer is formed above a substrate, and a dielectric stack is formed above the selective epitaxial sacrificial layer. A first opening extending vertically through the dielectric stack and the selective epitaxial sacrificial layer is formed. A portion of the first opening extending vertically through the selective epitaxial sacrificial layer is enlarged. A memory film and a semiconductor channel are then formed in this order along the sidewalls and bottom surface of the first opening. The selective epitaxial sacrificial layer is removed to form a cavity exposing a portion of the memory film. The portion of the memory film exposed in the cavity is removed to expose a portion of the semiconductor channel. A selective epitaxial layer is epitaxially grown from the substrate to fill the cavity and contact a portion of the semiconductor channel.

[0074] In some embodiments, the selective epitaxial sacrificial layer is etched back through the first opening to enlarge a portion of the first opening.

[0075] In some embodiments, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are then deposited, in that order, on the sidewalls and bottom surface of the first opening to form a memory membrane, and a polysilicon layer is deposited over the second silicon oxide layer to form a semiconductor channel.

[0076] In some embodiments, the first silicon oxide layer, the silicon nitride layer, the second silicon oxide layer, and the polysilicon layer extend laterally within the enlarged portion of the first opening.

[0077] In some embodiments, after forming the memory film and the semiconductor channel, a second opening is formed that extends vertically through the dielectric stack to expose a portion of the selective epitaxial sacrificial layer, and a protective layer is formed covering the sidewalls of the second opening.

[0078] In some embodiments, a high-k dielectric layer is formed on the sidewalls and bottom surface of the second opening to form a protective layer, and a portion of the high-k dielectric layer at the bottom surface of the second opening is etched to expose a portion of the selective epitaxial sacrificial layer.

[0079] In some embodiments, the selective epitaxial sacrificial layer is etched through the second opening to remove the selective epitaxial sacrificial layer, and the portion of the memory film is etched until stopped by a portion of the semiconductor channel to remove the portion of the memory film exposed in the cavity.

[0080] In some embodiments, after epitaxially growing the selective epitaxial layer, the protective layer is removed and a memory stack is formed to replace the dielectric stack through the second opening.

[0081] In some embodiments, a source contact structure is formed in the second opening and extends vertically through the memory stack so as to contact the selective epitaxial sacrificial layer.

[0082] In some embodiments, the substrate is a silicon substrate and the selective epitaxial layer comprises single crystal silicon.

[0083] The above description of specific embodiments reveals the general nature of the disclosure so that others may, by applying the knowledge of those skilled in the art, easily modify and / or adapt such specific embodiments for various applications without undue experimentation and without departing from the broad concept of the disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments based on the teachings and guidance provided herein. It is understood that the expressions and terms in the specification are for the purpose of description and not of limitation, as the terms and terms in the specification are interpreted by those skilled in the art in light of the teachings and guidance.

[0084] The embodiments of the present disclosure have been described above with the aid of functional components illustrating the implementation of specified functions and their relationships. The boundaries of these functional components have been arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the specified functions and their relationships are appropriately implemented.

[0085] The Summary and Abstract sections may describe one or more exemplary embodiments of the disclosure, but may not describe every exemplary embodiment of the disclosure contemplated by the inventors, and thus are not intended to limit the scope of the disclosure and the appended claims in any way.

[0086] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0087] 102 Substrate 104 Dielectric Stack 106 Gate sacrificial layer 108 Dielectric layer 110 Selective epitaxial sacrificial layer 112 Oxidized pad layer 114 NAND memory strings 116 Memory Film 118 Block Layer 120 Storage layer 122 Tunnel Layer 124 Semiconductor Channels 126 Cap Layer 128 Slit 130 Protective layer 132 Cavity 134 Part of semiconductor channel 124, weak point 200 3D memory devices 202 Substrate 204 Memory Stack 206 Conductive Layer 208 Dielectric layer 210 Selective epitaxial layer 212 NAND memory strings 213 Channel Structure 214 Memory Film 216 Block Layer 218 Memory layer, charge trapping layer 220 Tunnel Layer 222 Semiconductor Channel 224 Cap Layer 225 Channel Plug 226 Pocket structure 228 Source Contact Structure 230 Spacer 232 Source Conductor 302 Silicon substrate 304 Oxidized pad layer 306 Selective epitaxial sacrificial layer 308 First dielectric layer, gate sacrificial layer 310 Second Dielectric Layer 312 Dielectric Stack 314 Channel Hall 316 Enlarged section 318 Memory Film 320 Block Layer 322 Memory layer 324 Tunnel Layer 326 Semiconductor Channels 328 Cap Layer 330 NAND memory strings 331 Channel Structure 332 Pocket structure 334 Slit 336 Protective layer 338 Cavity 340 Pocket structure 341 Horizontal recess 342 Selective Epitaxial Layer 344 Conductive Layer 346 Memory Stack 348 Spacer 350 Source Conductor 352 Source Contact Structure W1 lateral dimension of channel structure 213 W2 Pocket structure 226 horizontal dimension

Claims

1. A substrate; a selective epitaxial layer on the substrate; a memory stack comprising alternating conductive and dielectric layers over the selective epitaxial layer; a memory string including a cylindrical channel structure extending vertically within the memory stack and a pocket structure extending vertically within the selective epitaxial layer; Equipped with a lateral dimension of the channel structure in the memory stack is less than or equal to a lateral dimension of the pocket structure; the memory string comprises a semiconductor channel extending vertically within the channel structure, extending vertically and laterally within the pocket structure, and in contact with the selective epitaxial layer; the memory string comprises a memory film in the channel structure between the memory stack and the semiconductor channel, the memory film extending vertically in the channel structure, extending in the pocket structure, and extending vertically and laterally in the substrate; a source contact structure extending vertically through the memory stack and contacting the selective epitaxial layer; the source contact structure comprises a source conductor comprising a conductive material and a spacer surrounding the source conductor and comprising a dielectric material; A three-dimensional (3D) memory device, wherein the semiconductor channel extends laterally within the pocket structure over approximately 20 nm.

2. 10. The 3D memory device of claim 1, wherein the lateral dimensions of the channel structure are the same as the lateral dimensions of the pocket structure.

3. 10. The 3D memory device of claim 1, wherein the memory string comprises a cap layer surrounded by the semiconductor channel, the cap layer having a lateral dimension in the pocket structure greater than a lateral dimension in the channel structure.

4. 10. The 3D memory device of claim 1, wherein the selective epitaxial layer comprises single crystal silicon and the semiconductor channel comprises polysilicon.

5. 10. The 3D memory device of claim 1, wherein the semiconductor channel is flat at a bottom end of the memory string.

6. 1. A method for forming a three-dimensional (3D) memory device, comprising: forming a first sacrificial layer for forming a cavity for growing a selective epitaxial layer above a substrate and a dielectric stack above said first sacrificial layer; forming a first opening extending vertically through the dielectric stack and the first sacrificial layer into the substrate; etching back the first sacrificial layer through the first opening; Next, forming a memory film and a semiconductor channel in this order along the sidewall and bottom surface of the first opening; forming a second opening extending vertically through the dielectric stack to expose a portion of the first sacrificial layer; forming a protective layer covering a sidewall of the second opening; removing the first sacrificial layer to form a cavity exposing a portion of the memory film; removing the portion of the memory film exposed at the cavity to expose a portion of the semiconductor channel; epitaxially growing a selective epitaxial layer from the substrate so as to fill the cavity and contact the portion of the semiconductor channel; removing the protective layer; forming a memory stack by replacing the gate sacrificial layers with conductive layers among the alternating gate sacrificial layers and dielectric layers provided in the dielectric stack through the second opening; forming a source contact structure in the second opening and extending vertically through the memory stack so as to contact the selective epitaxial layer; Including, The method of claim 1, wherein the source contact structure comprises a source conductor comprising a conductive material and a spacer surrounding the source conductor and comprising a dielectric material.

7. forming the memory film includes depositing a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer in this order on the sidewall and the bottom surface of the first opening; 7. The method of claim 6, wherein forming the semiconductor channel comprises depositing a polysilicon layer over the second silicon oxide layer.

8. The step of forming the protective layer includes: depositing a high dielectric constant (high-k) dielectric layer on the sidewalls and bottom surface of the second opening; etching a portion of the high-k dielectric layer at the bottom of the second opening to expose the portion of the first sacrificial layer; The method of claim 6, comprising:

9. removing the first sacrificial layer includes etching the first sacrificial layer through the second opening; 7. The method of claim 6, wherein removing the portion of the memory film exposed at the cavity comprises etching the portion of the memory film until stopped by the portion of the semiconductor channel.

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