Display device

Abstract

To provide good interface characteristics in a thin film transistor with an oxide semiconductor layer without introducing an impurity such as moisture, and propose a semiconductor device having a thin film transistor with high electrical characteristics and reliability, and a method for mass-producing the semiconductor device with high efficiency.SOLUTION: Oxygen radical treatment is performed on the surface of a gate insulating layer. Therefore, the oxygen concentration has a peak at the interface between a gate insulating layer and a semiconductor layer, and the oxygen concentration in the gate insulating layer has a concentration gradient, and the oxygen concentration increases as it approaches the interface between the gate insulating layer and the semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a thin film transistor (hereinafter referred to as TFT) using an oxide semiconductor film in a channel formation region. The present invention relates to a semiconductor device having a circuit formed of a liquid crystal display (hereinafter referred to as a liquid crystal display), and a manufacturing method thereof. The components include electro-optical devices such as display panels and light-emitting display devices with organic light-emitting elements. Regarding the electronic devices installed.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, a switching element made of a TFT has been installed for each display pixel arranged in a matrix. Active matrix display devices (liquid crystal display devices, light-emitting display devices, and electrophoretic display devices) Active matrix display devices are made up of pixels (or one dot). ) has a switching element, which increases pixel density compared to the simple matrix method. This is advantageous because it can be driven at a low voltage when the

[0004] In addition, thin film transistors (TFTs) and the like are fabricated using oxide semiconductor films in the channel formation region. The technology of fabricating oxide semiconductors and applying them to electronic and optical devices is attracting attention. TFTs that use zinc oxide (ZnO) as the thin film, and InGaO3 (ZnO) m Using T TFTs using these oxide semiconductor films are formed on a light-transmitting substrate. The technology for forming the semiconductor device and using it as a switching element for an image display device is described in Patent Documents 1 and 2. This is disclosed in. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] Thin film transistors using oxide semiconductor films in the channel formation region, such as instability of the oxide semiconductor film interface, However, thin-film transistors using IGZO have been The interface characteristics of transistors have not been discussed at all. In addition, there is uncertainty about reliability. The cause of this was unknown.

[0007] Therefore, one aspect of the present invention is to provide a method for manufacturing a semiconductor device using indium (In), gallium (Ga), and zinc (Zn) In a thin film transistor using an oxide semiconductor film containing One of the objectives of the present invention is to provide good interface characteristics without any problem.

[0008] In addition, when hydrogen is contained in the gate insulating layer in contact with the oxide semiconductor film, There is a risk that the hydrogen diffuses and reacts with oxygen in the oxide semiconductor film to become an H2O component.

[0009] In addition, when the oxygen concentration in the gate insulating layer is low, the oxygen concentration in the oxide semiconductor film may be reduced. There is.

[0010] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device using indium (In), gallium (Ga), and zinc (Zn). In a thin film transistor using an oxide semiconductor film containing One of the objectives is to provide a structure that can include the above.

[0011] In addition, a thin film transistor using an oxide semiconductor film for a channel formation region has a high operating speed. The manufacturing process must be relatively simple and the reliability must be sufficient.

[0012] In forming a thin film transistor, the source electrode and the drain electrode are made of a low-resistance metal material. In particular, when manufacturing a display device that displays a large area, the resistance of the wiring can cause the signal Therefore, gold, which has a low electrical resistance, is used as the material for wiring and electrodes. It is preferable to use a metal material for the source and drain electrodes. When a thin film transistor structure is used in which the doped electrode and the oxide semiconductor film are in direct contact with each other, The contact resistance may become high. The cause of the high contact resistance is the One of the reasons is that a Schottky junction is formed at the contact surface between the electrode and the oxide semiconductor film. It is possible.

[0013] In addition, a capacitance is generated at the portion where the source electrode and the drain electrode are in direct contact with the oxide semiconductor film. This results in a lower frequency characteristic (called the f characteristic), enabling high-speed operation of thin-film transistors. There is a risk of hindering it.

[0014] One aspect of the present invention is an oxide containing indium (In), gallium (Ga), and zinc (Zn). In a thin film transistor using a nitride semiconductor film, An object of the present invention is to provide a thin film transistor having reduced tact resistance and a method for manufacturing the same. do.

[0015] In addition, the operating characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn One of the challenges is to improve the reliability of the system.

[0016] In addition, the electrical characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn In particular, in liquid crystal display devices, it is necessary to reduce the variation in individual If there is a large variation between elements, the display will be uneven due to the variation in the TFT characteristics. There is a risk that this may happen.

[0017] In addition, in a display device having a light-emitting element, the pixel electrodes are arranged so that a constant current flows through them. The on-chip TFT (which supplies current to the driver circuit or the light-emitting element arranged in the pixel) Current (I on If the variation in the brightness of the display screen is large, the brightness of the display screen may vary. There is a problem.

[0018] An object of one embodiment of the present invention is to solve at least one of the above problems. [Means for solving the problem]

[0019] One embodiment of the present invention is to perform oxygen radical treatment on a surface of a gate insulating layer. The gate insulating layer has an oxygen concentration peak at the interface between the gate insulating layer and the semiconductor layer, and the oxygen concentration of the gate insulating layer is The concentration has a concentration gradient, and the oxygen concentration decreases as it approaches the interface between the gate insulating layer and the semiconductor layer. increases.

[0020] In addition, an oxygen-excess oxide semiconductor film is used as a semiconductor layer, and the semiconductor layer and the source electrode layer and the drain electrode layer are A source region and a drain region using an oxygen-deficient oxide semiconductor film are provided between the semiconductor layer and the gate electrode layer. The thin film transistor includes an inverted staggered type (bottom gate structure) thin film transistor.

[0021] The semiconductor layer, source region, and drain region are made of an oxide semiconductor containing In, Ga, and Zn. In addition, any one of In, Ga, and Zn can be used in combination with tungsten, molybdenum, or It may be replaced by lithium, titanium, nickel, or aluminum.

[0022] In this specification, a semiconductor formed using an oxide semiconductor film containing In, Ga, and Zn is The semiconductor layer is also referred to as the "IGZO semiconductor layer."

[0023] By performing oxygen radical treatment on the gate insulating layer, oxygen radicals are bombarded into the gate insulating layer. The gate insulating layer near the interface with the oxygen-excess oxide semiconductor layer is thicker than the bulk GI. Contains excess oxygen.

[0024] By performing oxygen radical treatment, the gate insulating layer and the vicinity of the interface with the oxide semiconductor layer are also improved. In this case, the gate insulating layer may have an oxygen excess region.

[0025] The gate insulating layer having an oxygen-excess region and the oxygen-excess oxide semiconductor layer are compatible with each other and have a good interface. characteristics can be obtained.

[0026] In addition, in order to stack a gate insulating layer having an oxygen excess region and an oxygen excess oxide semiconductor layer, In this case, it is preferable to carry out continuous film formation.

[0027] The oxygen radicals may be supplied by a plasma generator using a gas containing oxygen; Alternatively, the oxygen may be supplied by an ozone generator. The surface of the thin film can be modified by irradiating the thin film with oxygen or water.

[0028] Furthermore, the radical treatment is not limited to oxygen radical treatment, and radical treatment using argon and oxygen may be performed. The argon and oxygen radical treatment involves introducing argon gas and oxygen gas to generate plasma. The purpose of this method is to modify the thin film surface by applying heat to the thin film.

[0029] Argon atoms (Ar) in the reaction space where an electric field is applied and discharge plasma is generated are The electrons (e) in the plasma excite or ionize the argon radicals (Ar * ) and Argon On (Ar + ) and electrons (e). Argon radicals (Ar * ) is a high energy equivalent It is in a stable state and reacts with the same or different atoms in the vicinity, exciting or ionizing those atoms. When the oxygen is in the vicinity, the reaction occurs like an avalanche. When the oxygen atom (O) is excited or ionized, it becomes an oxygen radical (O * ) and oxygen ions (O + ) and oxygen (O). The oxygen radical (O * ) reacts with the material on the surface of the thin film that is the object to be treated. Plasma treatment is used to modify the surface or to react with organic matter on the surface to remove it. The radicals of the inert gas are in a metastable state compared to the radicals of the reactive gas. This is because the plasma is generated using an inert gas. It is common for

[0030] The gate insulating layer is formed using a silicon target and by introducing Ar gas and oxygen gas. It is most preferable to form the insulating layer by sputtering and have a high oxygen content. When forming a gate insulating layer by plasma CVD (PCVD) using gas, etc., When hydrogen contained in the insulating layer reacts with oxygen in the oxide semiconductor layer, it easily produces HO and OH. It may become a carrier killer and cause a deterioration in reliability. When an insulating film containing hydrogen is used as a gate insulating layer in the D method, the hydrogen in the gate insulating layer is converted into oxygen. The excess may react with oxygen in the oxide semiconductor layer, which is not preferable. The hydrogen concentration in the insulating layer was obtained by analysis using a secondary ion mass spectrometer (SIMS). The concentration peak is 2×10 19 cm -3 It is preferable that the oxygen concentration is less than 100%. A comparative example is shown in which oxygen radical treatment is performed on a gate insulating layer having a low resistance. This is not preferable because there is a risk of absorbing oxygen from the oxygen-rich oxide semiconductor layer.

[0031] As a result, as shown in the oxygen concentration distribution in FIG. 1(A), oxygen radicals are present at the interface on the gate insulating layer side. After that, the IGZO film is formed and then heat treated (200℃~6 1A shows the oxygen concentration near the interface between the gate insulating layer and the semiconductor layer before the heat treatment. FIG. 1(B) shows the vicinity of the interface between the gate insulating layer and the semiconductor layer after heat treatment. FIG.

[0032] By carrying out heat treatment from the state shown in FIG. 1(A) to the state shown in FIG. 1(B), Excess oxygen in the insulating layer is drifted to the IGZO film side, and oxygen in the IGZO film is drifted to the GI film side. The effect of preventing the drift of the interface caused by oxygen radicals on the surface of the gate insulating layer is One of the causes of instability in reliability is the interface between the gate insulating layer and the IGZO film. It was revealed that the gate insulating layer, not the IGZO film, was modified, and the subsequent heat treatment This technology stabilizes reliability.

[0033] In addition, the surface of the gate insulating layer is subjected to plasma treatment to form SiN, and then oxygen radical treatment is performed. The surface may be treated to reduce the diffusion of hydrogen in the gate insulating layer into the IGZO film. The plasma process for converting SiN uses microwaves to excite the plasma, A method of nitriding the surface of the gate insulating layer by using radicals (which may contain NH radicals). Alternatively, a method of performing reverse sputtering in a nitrogen atmosphere may be used. After conversion to iN, oxygen radical treatment was performed on the gate insulating layer and the semiconductor layer. FIG.

[0034] 1, 2, and 3 are schematic diagrams for simply explaining the concept of one embodiment of the present invention. It goes without saying that there is no particular limitation.

[0035] In addition, an ohmic contact is required between the source electrode layer and the IGZO semiconductor layer. In addition, it is desirable to reduce the contact resistance as much as possible. An ohmic contact is required with the GZO semiconductor layer, and the contact resistance is It is desirable to reduce the resistance as much as possible.

[0036] Therefore, an IGZO semiconductor is provided between the source electrode layer, the drain electrode layer and the IGZO semiconductor layer. By intentionally providing a source region and a drain region having a higher carrier concentration than the layer, An ohmic contact is formed.

[0037] An oxygen-excess oxide semiconductor layer is used as a semiconductor layer, and an oxygen-excess oxide semiconductor layer is used as a source region and a drain region. The oxygen-deficient oxide semiconductor layer in the source and drain regions is It has crystal grains.

[0038] The oxygen-deficient oxide semiconductor layer having crystal grains is actively used as a source region or a drain region. By providing the metal layer, the source electrode layer or the drain electrode layer and the IGZO film This provides a good junction between the layers, and provides thermally stable operation compared to a Schottky junction. Supplying the channel carriers (source side) or stably absorbing the channel carriers (drain side), or the resistance component is at the interface with the source electrode layer (or drain electrode layer) In order to prevent this, it is necessary to provide a source region or drain region having crystal grains. It is important to reduce the resistance in order to maintain good mobility even at high drain voltages. be.

[0039] A 400 nm IGZO film was formed on a glass substrate by DC sputtering, and XRD (X-ray The deposition conditions were a pressure of 0.4 Pa, a power of 500 W, and a deposition temperature of 1000 s. The temperature was set to room temperature, the argon gas flow rate was set to 10 sccm, the oxygen flow rate was set to 5 sccm, and the turbine The target used was In2O3:Ga2O3:ZnO=1:1:1. In order to obtain an amorphous IGZO film, a target with this ratio was intentionally used. There are.

[0040] Figure 37 shows the XRD measurement chart. The chart immediately after the film formation is shown in as-de in Figure 37. In addition, FIG. 37 shows the results of the film deposition in a nitrogen atmosphere at 350° C. for 1 hour. The chart after the heat treatment and the chart after the heat treatment at 500℃ in nitrogen atmosphere for 1 hour after the film formation are shown. After deposition, the chart shows the results after heat treatment in a nitrogen atmosphere at 600°C for 1 hour, and after deposition, the chart shows the results after heat treatment in a nitrogen atmosphere at 700°C for 1 hour. For convenience, the charts are shown side by side for comparison with the chart after heat treatment at 00°C for 1 hour. .

[0041] In the sample after heat treatment at 700°C, the peaks clearly indicating crystallinity were in the range of 30 to 35° and 55 In addition, a 400 nm IGZO film was formed and then cooled in a nitrogen atmosphere for 7 After heat treatment at 00℃ for 1 hour, the sample was analyzed by FIB (Focused Ion Beam). The end surface was cut out and observed under a high-resolution transmission electron microscope (Hitachi "H9000-NAR":TE The cross-section was observed at 500,000 magnification using a microscope (M) with an accelerating voltage of 300 kV. The crystal grains can be confirmed. The cross-section was observed at 6 million magnifications using a STEM with an accelerating voltage of 200 kV. The photograph is shown in Figure 49. A clear lattice image can be seen in Figure 49, and XRD measurements show peaks indicating crystals. This corresponds to the fact that the

[0042] In addition, to investigate the presence or absence of crystal grains, their size, and the distribution of crystal grains, a glass substrate was used. A 50 nm IGZO film was formed on the substrate by DC sputtering, and the end surface was cut out by FIB. , a high-resolution transmission electron microscope (Hitachi "H9000-NAR": TEM) was used with an accelerating voltage The voltage was set to 300 kV and the cross section was observed.

[0043] The target was In2O3:Ga2O3:ZnO=1:1:1, and the film formation conditions were pressure, The pressure was 0.4 Pa, the power was 500 W, the deposition temperature was room temperature, and the argon gas flow rate was 5 s. Sample 1 was sputtered under oxygen excess conditions with an oxygen flow rate of 45 sccm and an oxygen flow rate of 45 sccm. No oxygen gas was introduced, and only argon gas was used at a flow rate of 40 sccm, with other conditions remaining the same. Sample 1 and sample 2 were prepared by sputtering under oxygen-deficient conditions, and their cross sections were observed.

[0044] The result of observing sample 1 at 500,000 times magnification is shown in Figure 38, and the result of observing sample 2 at 500,000 times magnification is shown in Figure 39. In sample 1, no crystal grains were observed in the IGZO film, but in sample 2, The IGZO film has scattered crystal grains with diameters of 1 nm to 10 nm, typically 2 nm to 4 nm. The grains of sample 2 were observed in the cross section of the sample that had been heat-treated at 700°C. The crystal grain size is smaller than that of the observation photograph in Figure 48. To obtain a glass-like IGZO film, a tube with a composition of In2O3:Ga2O3:ZnO=1:1:1 was used. Although a target was intentionally used, an IGZO film containing crystal grains was obtained immediately after deposition. It can be said that this is the case.

[0045] In addition, after the deposition conditions of Sample 1, a sample was further heat-treated in a nitrogen atmosphere at 350°C for 1 hour. 3 and sample 2, which were then heat-treated in a nitrogen atmosphere at 350°C for 1 hour after the deposition conditions. 4 and 5 were prepared and their cross sections were observed.

[0046] The result of observing sample 3 at 500,000 times magnification is shown in Figure 40, and the result of observing sample 4 at 500,000 times magnification is shown in Figure 41. In addition, no crystal grains were observed in the IGZO film in sample 3, but the crystal grains were observed in the IGZO film in sample 4. In the IGZO film, crystals with a diameter of about 1 nm to 10 nm, typically 2 nm to 4 nm, are formed. It can be seen that crystal grains are scattered.

[0047] In addition, when samples 1 to 4 were subjected to XRD measurement, the as-depo The sample shown in Fig. 1 was heat-treated in a nitrogen atmosphere at 350°C for 1 hour, and the sample was similarly The results showed that no peaks clearly indicating crystals were observed.

[0048] Thus, in sample 1, in which the sputtering conditions were oxygen-rich, crystal grains were clearly visible in the TEM photograph. The reasons why crystal grains were observed in the TEM photograph of sample 2, which was prepared under oxygen-deficient conditions, are as follows: show.

[0049] In sample 2, which was made under oxygen-deficient conditions, the sputtering target was struck with Ar, and the The plasma energy of Ar ions is given to the stoichiometric particles, and during flight (from the target) Crystallization or grain growth occurs from the film surface to the substrate. The corners are also observed. In addition, when heat-treated at 350°C, the amorphous components around the crystal grains As a result of reaction with oxygen, the grain boundaries of the crystal grains become blurred, i.e., unclear, as shown in Figure 41, compared to Figure 39. It has been observed that the order of the crystals in the amorphous component tends to be more peripheral than the crystal grains. It is believed to be continuing to develop and grow.

[0050] Therefore, an IGZO film with a lower oxygen concentration is formed under oxygen-deficient conditions, and the N+ type is more highly It is thought to be composed of a concentrated carrier region.

[0051] From the grain formation process, the target component ratio, deposition pressure (0.1 Pa to 2.0 Pa) , power (250W~3000W: 8 inch diameter), temperature (room temperature~100℃), reactive spat By appropriately adjusting the deposition conditions of the crystal grains, the grain density and diameter size can be adjusted to 1 nm to 10 nm. It can be said that the distance can be adjusted within a range of m.

[0052] On the other hand, in sample 1, which was made under oxygen-rich conditions, the sputtering target was struck and plasma energy was generated during flight. Even if we want to use energy to grow crystals, there is an excess of oxygen at the same time, so each element cannot react with oxygen. It is strong and cannot accompany the crystal growth mechanism of IGZO, and it becomes glassy (amorphous). All components are deposited on the substrate in a single layer.

[0053] Of course, the intermediate conditions between oxygen deficiency and oxygen excess conditions are the degree of oxygen contamination in sputtering deposition. The process is regulated by degree.

[0054] In addition, the sputtering method uses Ar ions to apply high energy to the target, It is believed that a strong strain energy exists in the formed IGZO film. To release the ghee, heat treatment is performed at 200℃ to 600℃, typically 300℃ to 500℃. This heat treatment causes rearrangements at the atomic level. This heat treatment allows the movement of carriers. The deposition and heat treatment (including photo-annealing) are important because they release the inhibiting strain. Heat treatment at 200℃ to 600℃ does not involve large atomic movements like heat treatment at temperatures above 700℃. However, it has not yet reached the stage of single crystal growth by this method.

[0055] At heating temperatures above 700°C, clear crystal growth was observed, and as shown in Figure 37, XRD also showed Crystal peaks are observed. On the other hand, under both oxygen-deficient and oxygen-rich conditions, As shown above, the XRD measurement showed that the crystal grain size was not significant due to the low crystalline content or the low degree of crystallinity. It is unclear whether this is due to the small size of the ion beam or some other factor, but it is not observed.

[0056] The crystal grains observed in Figs. 39 and 41 are shown in further enlargement in Figs. 42 and 43. Figure 42 is a cross-sectional TEM photograph (8 million times magnification) of sample 2 under oxygen-deficient conditions. This is a cross-sectional TEM photograph (8 million times magnification) of sample 4 that was subjected to oxygen-deficient conditions and further heat treatment. In both Figures 42 and 43, clear lattice images of the crystal grains are observed, and a single crystal with a three-layer structure is observed. is clearly observed.

[0057] 38 and 40 are enlarged in Figs. 44, 45, 46, and 47. Figure 44 shows a cross-sectional TEM image (2 million times magnification) of sample 1 under oxygen excess conditions. Figure 46 shows a 100,000x magnification photograph. Figure 45 shows sample 3, which was subjected to an oxygen excess condition and further heat treatment. The cross-sectional TEM photographs (2 million magnifications) are shown in Fig. 44 and Fig. 47, which are shown at 8 million magnifications. No crystal grains can be seen in Figures 45, 46, and 47.

[0058] One embodiment of a semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer over the gate electrode layer, and a gate insulating layer over the gate electrode layer. an oxide semiconductor layer on the gate insulating layer; and a source region and a drain region on the oxide semiconductor layer; A thin-film transistor including a source electrode layer and a drain electrode layer on the source region and the drain region. a peak of oxygen concentration is present at an interface between a gate insulating layer and an oxide semiconductor layer; The oxygen concentration in the gate insulating layer has a concentration gradient, and the oxygen concentration is It increases as it approaches the interface with

[0059] One embodiment of a semiconductor device of the present invention includes a gate electrode layer, a gate insulating layer over the gate electrode layer, and a gate insulating layer over the gate electrode layer. an oxide semiconductor layer on the gate insulating layer; and a source region and a drain region on the oxide semiconductor layer; A thin-film transistor including a source electrode layer and a drain electrode layer on the source region and the drain region. a peak of oxygen concentration is present at an interface between a gate insulating layer and an oxide semiconductor layer; The oxygen concentration in the gate insulating layer and the oxide semiconductor layer has a concentration gradient. The concentration of the impurity increases toward the interface between the oxide semiconductor layer and the oxide semiconductor layer.

[0060] In the above structure, the oxygen concentration in the oxide semiconductor layer is The oxide semiconductor layer is an oxygen-excess oxide semiconductor layer, and the source and drain regions are an oxygen-excess oxide semiconductor layer. When the silicon-deficient oxide semiconductor layer is used, the carrier concentration of the source region and the drain region is increased by the oxide semiconductor. It can be made higher than the conductor layer.

[0061] In addition, it is preferable to use a titanium film for the source electrode layer and the drain electrode layer. The laminated layer of the tantalum film, the aluminum film, and the titanium film has low resistance, and the aluminum film Hillocks are less likely to occur.

[0062] According to one embodiment of a method for manufacturing a semiconductor device of the present invention, a gate electrode layer is formed over a substrate, A gate insulating layer is formed on the layer, and the gate insulating layer is modified by exposing it to oxygen radicals. An oxide semiconductor layer is formed over the gate insulating layer, and a source region and a drain region are formed over the oxide semiconductor layer. forming a source electrode layer and a drain electrode layer on the source region and the drain region; The gate insulating layer and the oxide semiconductor layer are formed in succession without exposure to air.

[0063] Gate insulating layer, semiconductor layer, source region and drain region, source electrode layer and drain electrode The layers can be formed successively without exposure to the atmosphere. This can reduce defects caused by impurities in the air getting into the interface.

[0064] Gate insulating layer, semiconductor layer, source region and drain region, source electrode layer and drain electrode The layer may be formed by a sputtering method.

[0065] By using the sputtering method to continuously form films in this way, productivity is high and the reliability of the thin film interface is high. In addition, the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere, so that they contain a lot of oxygen. This can lead to a decrease in reliability due to degradation and a shift in thin-film transistor characteristics to the normally-on side. This can reduce the shift in the load.

[0066] According to one embodiment of a method for manufacturing a semiconductor device of the present invention, a gate electrode layer is formed over a substrate, A gate insulating layer is formed on the layer, and the gate insulating layer is modified by exposing it to oxygen radicals. An oxide semiconductor layer is formed over the gate insulating layer, and a source region and a drain region are formed over the oxide semiconductor layer. The oxide semiconductor layer, the source region, and the drain region are heated at a temperature of 200° C. or higher and 600° C. or higher. The source electrode layer and the drain electrode layer are formed on the source region and the drain region by heating at a temperature of 1000.degree. The gate insulating layer and the oxide semiconductor layer are formed in succession without exposure to air. Effect of the Invention

[0067] According to one aspect of the present invention, a thin film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio can be obtained. It is possible to obtain a thin film transistor having good dynamic characteristics. Thus, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided. can be done. [Brief description of the drawings]

[0068] [Figure 1] Schematic diagram of the oxygen concentration near the interface between the gate insulating layer and the semiconductor layer before and after heat treatment. [Diagram 2] FIG. 1 is a schematic diagram of the oxygen concentration in the vicinity of the interface between a nitrided gate insulating layer and a semiconductor layer. [Diagram 3] FIG. 4 is a schematic diagram of the oxygen concentration in the vicinity of the interface between a gate insulating layer and a semiconductor layer (Comparative Example). [Figure 4] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 5] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 6] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 12] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 13] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 14] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 15] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 16] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 17] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 18] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 19] 4 is a timing chart illustrating the operation of the signal line driver circuit. [Figure 20] FIG. 2 is a diagram illustrating a configuration of a shift register. [Figure 21] 21 is a diagram for explaining a connection configuration of the flip-flop shown in FIG. 20. [Figure 22] Schematic top view of a multi-chamber manufacturing device. [Figure 23] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 24] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 28] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 29] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 30] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 31] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Diagram 32] FIG. 1 is an external view showing an example of an electronic book. [Diagram 33] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Diagram 34] FIG. 1 is an external view showing an example of a gaming machine. [Diagram 35] FIG. 1 is an external view showing an example of a mobile phone. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 37] FIG. 1 shows the results of XRD measurement. [Figure 38] Cross-sectional TEM photograph (500,000x) of sample 1 under oxygen-rich conditions. [Figure 39] Cross-sectional TEM photograph (500,000x) of sample 2 under oxygen-deficient conditions. [Diagram 40] Cross-sectional TEM photograph (500,000x) of sample 3 that was subjected to excess oxygen conditions and then heat treatment. [Diagram 41] Cross-sectional TEM photograph (500,000x) of sample 4 that was subjected to oxygen-deficient conditions and then heat-treated. [Diagram 42] Cross-sectional TEM photograph (8 million times magnification) of sample 2 under oxygen-deficient conditions. [Diagram 43] Cross-sectional TEM photograph (8 million times magnification) of sample 4 under oxygen-deficient conditions. [Diagram 44] Cross-sectional TEM photograph (8 million times magnification) of Sample 1 under oxygen-rich conditions. [Diagram 45] Cross-sectional TEM photograph (2 million times magnification) of sample 3 under oxygen-rich conditions. [Figure 46]Cross-sectional TEM photograph (2 million times magnification) of sample 3 that was subjected to excess oxygen conditions and then heat treatment. [Figure 47] Cross-sectional TEM photograph (8 million times magnification) of sample 3 that was subjected to excess oxygen conditions and then heat treatment. [Figure 48] Cross-sectional TEM photograph (500,000x) of a sample that was heat treated at 700℃. [Figure 49] STEM image (6 million times magnification) of a sample that was heat treated at 700℃. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0069] The present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in the following manner. The present invention is not limited to the above-described embodiment. In the structure, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. and the repeated explanation will be omitted.

[0070] (Embodiment 1) In this embodiment mode, a thin film transistor and a manufacturing process thereof will be described with reference to FIGS. explain.

[0071] FIG. 1 shows thin film transistors 170a, 170b, and 170c having a bottom gate structure according to the present embodiment. 5 and 6. FIG. 5(A1) is a plan view, and FIG. 5(A2) is a schematic view of FIG. 5(A1). FIG. 5(B1) is a plan view, and FIG. 5(B2) is a cross-sectional view taken along line A1-A2. 6(A1) is a cross-sectional view taken along line B1-B2 in FIG. 6(A2). 7 is a cross-sectional view taken along line C1-C2 in FIG. 6(A1).

[0072] In FIG. 5, a gate electrode layer 101, a gate insulating layer 102, a semiconductor layer 1 03, source region or drain region 104a, 104b, source electrode layer or drain electrode A thin film transistor 170a is provided on the layers 105a and 105b.

[0073] The surface of the gate insulating layer 102 is subjected to oxygen radical treatment. The oxygen concentration of the gate insulating layer 102 is a peak at the interface with the layer 103. The oxygen concentration has a gradient as it approaches the interface between the gate insulating layer 102 and the semiconductor layer 103. The number of people increases.

[0074] In addition, an oxygen-excess oxide semiconductor film containing In, Ga, and Zn is used as the semiconductor layer 103. , source electrode layer or drain electrode layer 105a, 105b and a semiconductor layer which is an IGZO semiconductor layer A source or drain region 104 made of an oxygen-deficient oxide semiconductor layer is formed between the layer 103 and the a, 104b are intentionally provided to form an ohmic contact. The semiconductor layer 103 and the source and drain regions 104a and 104b are made of In, Ga , and Zn, with tungsten, molybdenum, titanium, nickel, aluminum may be substituted.

[0075] The source and drain regions 104a and 104b include In, Ga, and Zn. An oxygen-deficient oxide semiconductor film having crystal grains is used.

[0076] The IGZO for the channel is a capacitor that is not normally on as a thin-film transistor. Therefore, the IGZO film having the carrier concentration in the range of the present invention is used as the channel of the semiconductor layer. By using it as a thin film transistor, a highly reliable thin film transistor can be obtained.

[0077] The source region or the drain region may have a laminated structure. When stacking layers, the carrier concentration increases toward the source electrode layer and drain electrode layer side. The concentration range should be set so that the source and drain regions contain impurity elements. High carrier concentration source and drain regions can be formed.

[0078] The thin film transistor 170a in FIG. 5(A1) and FIG. 5(A2) has a source region or a drain region 10 4a and 104b and the source or drain electrode layers 105a and 105b are formed using a different mask. This is an example of etching using a source region or drain region 104a, 104b. The source and drain electrode layers 105a and 105b have different shapes.

[0079] The thin film transistor 170b in FIG. 5(B1) and (B2) has a source region or a drain region 10 4a, 104b and the source or drain electrode layers 105a, 105b are formed using the same mask. This is an example of etching using a source region or drain region 104a, 104b. The source and drain electrode layers 105a and 105b have a similar shape.

[0080] In addition, the thin film transistors 170a and 170b in FIGS. On the semiconductor layer 103, the ends of the source and drain electrode layers 105a and 105b are The end of the source region or drain region 104a, 104b does not match the end of the source region or drain region 104a, 104b. In this example, the drain regions 104a and 104b are partially exposed.

[0081] On the other hand, the thin film transistor 170c in FIG. 6(A1) and (A2) has a semiconductor layer 103 and a source region. In this example, the gate region 104a and drain region 104b are etched using the same mask. The ends of the semiconductor layer 103 and the source and drain regions 104a and 104b are aligned. In addition, the thin film transistor 170c in FIG. 6(A1) and (A2) has a semiconductor layer 103. In the above, the ends of the source and drain electrode layers 105a and 105b are In this example, the ends of the rain regions 104a and 104b also coincide.

[0082] Furthermore, a thin film transistor 171d in which the source electrode layer or the drain electrode layer has a stacked structure is FIG. 15 shows the thin film transistor 171d. , 105a2, 105a3, and the source or drain electrode layers 105b1, 105 For example, the source or drain electrode layer 105 a1, 105b1 as titanium film, 105a2, 105b2 as aluminum film, 10 A titanium film can be used as 5a3 and 105b3.

[0083] In the thin film transistor 171d, the source and drain electrode layers 105a1 and 105b 1 as an etching stopper, the source or drain electrode layer 105a2, 105a3, 105b2, and 105b3 are formed by wet etching. The source electrode layer or the drain electrode layer is then etched using the same mask as that used in the wet etching. 105a1, 105b1, source region or drain region 104a, 104b, semiconductor layer 1 03 is formed by dry etching.

[0084] Therefore, the source or drain electrode layer 105a1 is a source or drain region 10 The end of 4a and the source or drain electrode layer 105b1 are The source electrode layer or drain electrode layer 105a2 , 105a3, and the source or drain electrode layers 105b2, 105b3 are source electrodes The ends of the drain electrode layers 105a1 and 105b1 are recessed.

[0085] In this way, the conductive film used for the source electrode layer and the drain electrode layer and the source region or the drain region When the selectivity between the semiconductor layer and the gate region is low in the etching process, an etching stopper is used. By stacking conductive films that function as a barrier, etching processes can be performed multiple times under different etching conditions. Good.

[0086] In FIG. 4(A) and (B), a gate electrode layer 101 is provided on a semiconductor layer 103, a source region or a drain region. The regions 104a, 104b are larger than the source electrode layer or drain electrode layer 105a, 105b. On the gate electrode layer 101, a semiconductor layer 103, a source region or a drain region 104a, 4b, a thin film transistor on which the source electrode layer or drain electrode layer 105a, 105b is formed In addition, the thin film transistors 170d and 170e have Insulating films 107a and 107b are formed as protective films.

[0087] The method for fabricating the thin film transistor 170a shown in FIG. 5(A1) and (A2) will be described with reference to FIGS. I will use this to explain.

[0088] A gate electrode layer 101, a gate insulating layer 102, and a semiconductor film 111 are formed on a substrate 100 ( See FIG. 7(A). The substrate 100 is made of barium borosilicate glass, aluminoborosilicate glass, etc. Glass or aluminosilicate glass, made by the fusion or float process. In addition to alkali-free glass and ceramic substrates, we also offer heat-resistant substrates that can withstand the processing temperatures of this manufacturing process. A plastic substrate having a metal substrate such as a stainless steel alloy may be used. A substrate having an insulating film on its surface may be used. The size of the substrate 50 is 320 mm x 4 00mm, 370mm×470mm, 550mm×650mm, 600mm×720mm , 680mm×880mm, 730mm×920mm, 1000mm×1200mm, 1 100mm×1250mm, 1150mm×1300mm, 1500mm×1800mm , 1900mm×2200mm, 2160mm×2460mm, 2400mm×2800 mm, or 2850mm x 3050mm, etc. can be used.

[0089] An insulating film may be formed as a base film on the substrate 100. The base film may be formed by a sputtering method. A single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film, Alternatively, it may be formed by laminating layers.

[0090] The gate electrode layer 101 may be made of titanium, molybdenum, chromium, tantalum, tungsten, or aluminum. The gate electrode layer 101 is formed using a metal material such as sulphur dioxide or an alloy material thereof. A conductive film is formed on the substrate 100 by a sputtering method or a vacuum deposition method, and then photolithography is performed on the conductive film. A mask is formed by a printing technique or an inkjet method, and a conductive film is etched using the mask. It can be formed by etching. It can also be formed by etching conductive nanoparticles such as silver, gold, and copper. The gate electrode layer 101 is formed by discharging the conductive paste by an ink-jet method and baking the same. In addition, the adhesion of the gate electrode layer 101 can be improved and a barrier layer can be formed to prevent diffusion into the substrate or the underlayer. As the metal, a nitride film of the above metal material is provided between the substrate 100 and the gate electrode layer 101. The gate electrode layer 101 may have a single layer structure or a stacked layer structure. For example, a molybdenum film and an aluminum film are laminated from the substrate 100 side, Lamination of titanium and neodymium alloy films, lamination of titanium and aluminum films, titanium film, aluminum A laminate of a aluminum film and a titanium film can be used.

[0091] Since a semiconductor film and wiring are formed on the gate electrode layer 101, the edge of the gate electrode layer 101 is cut to prevent a step. It is preferable to process it so that it has a tapered shape.

[0092] The gate insulating layer 102 and the semiconductor film 111 can be formed in succession without exposure to the air. When films are formed continuously, they can be contaminated by atmospheric components and impurity elements suspended in the air. Each lamination interface can be formed without any problem.

[0093] In active matrix display devices, the electrical properties of thin film transistors that make up the circuits are The characteristics are important, and these electrical characteristics determine the performance of the display device. Among the electrical characteristics of , the threshold voltage (Vth) is important. If the threshold voltage is high or negative, the circuit cannot control it. It is difficult to achieve this. In the case of a thin-film transistor, when the driving voltage is low, it does not function as a switching element. If the threshold voltage is negative, Even if the gate voltage is 0V, current flows between the source and drain electrodes. This is called normally-on. This is likely to happen.

[0094] In the case of an n-channel thin-film transistor, the channel is turned on only when a positive voltage is applied to the gate. A transistor in which a channel is formed and a drain current flows out is desirable. There are transistors in which a channel does not form unless a negative voltage is applied, and transistors in which a channel forms even under negative voltage conditions. Transistors that allow drain current to flow are not suitable for use as thin-film transistors in circuits. be.

[0095] Therefore, the gate of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn is It is desirable to form a channel with a positive threshold voltage as close to 0V as possible.

[0096] The threshold voltage of a thin film transistor is determined by the interface between the oxide semiconductor layer, that is, the interface between the oxide semiconductor layer and the gate electrode. This is thought to have a significant effect on the interface of the gate insulating layer.

[0097] Therefore, by forming these interfaces in a clean state, the electrical characteristics of the thin film transistors can be improved. This improves the manufacturing process and prevents the manufacturing process from becoming complicated, achieving both mass production and high performance. A thin film transistor having the above structure is realized.

[0098] In particular, when moisture in the air is present at the interface between the oxide semiconductor layer and the gate insulating layer, the thin film transistor The electrical characteristics of the transistors deteriorate, the threshold voltage varies, and the transistors tend to be normally on. By successively forming the oxide semiconductor layer and the gate insulating layer, such hydrogen The compound can be eliminated.

[0099] In addition, the surface of the gate insulating layer 102 is subjected to oxygen radical treatment to convert the surface of the gate insulating layer 102 into an oxygen-containing gas. The region is modified to an excess of oxygen.

[0100] The oxygen radical treatment on the surface of the gate insulating layer 102 is performed by plasma treatment such as reverse sputtering. Reverse sputtering is a method of sputtering oxygen or oxygen and arsenic without applying a voltage to the target side. A method of modifying the surface by applying a voltage to the substrate side in an argon atmosphere to generate plasma on the substrate. The gate insulating layer may be subjected to a nitriding treatment, for example, by reverse sputtering under a nitrogen atmosphere. The plasma treatment may be performed as described above.

[0101] Therefore, the surface of the gate insulating layer 102 is modified by oxygen radicals, and the gate is formed without being exposed to the air. The insulating layer 102 and the semiconductor film 111 are successively formed under reduced pressure by sputtering. This has resulted in a thin-film transistor with a good interface, low leakage current, and high current driving capability. It is possible.

[0102] The gate insulating layer 102 and the semiconductor layer 103 are oxide semiconductor films containing In, Ga, and Zn. The film 111 is heated under an oxygen atmosphere (or oxygen 90% or more, rare gas (argon, helium, etc.) It is preferable to form the film at a concentration of 10% or less.

[0103] By using the sputtering method to continuously form films in this way, productivity is high and the reliability of the thin film interface is high. In addition, the gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere, so that they contain a lot of oxygen. Doing so may result in a decrease in reliability due to degradation, or the thin-film transistor becoming normally on. and can be reduced.

[0104] The gate insulating layer 102 is formed by sputtering a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. Alternatively, the thin film transistor shown in FIG. 6(A1) and (A2) can be formed of a silicon nitride oxide film. The transistor 170c is an example in which the gate insulating layer 102 is laminated.

[0105] The gate insulating layer 102 is made of a silicon nitride film or a silicon nitride oxide film, and a silicon oxide film or an oxide The gate insulating layer can be formed by stacking a silicon nitride film and a silicon nitride film in that order. From the substrate side, a silicon nitride film or a silicon nitride oxide film, a silicon oxide film or a silicon oxynitride film, and a nitride The gate insulating film can be formed by laminating three layers in this order: a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating layer is a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. It can be formed.

[0106] In addition, a silicon nitride film is formed as a gate insulating layer 102 on the gate electrode layer 101 by a sputtering method. A silicon oxide film may be laminated on the silicon nitride film by sputtering.

[0107] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. In addition, a silicon nitride oxide film is a film whose composition contains more nitrogen than oxygen. This refers to.

[0108] The gate insulating layer 102 may be formed of an oxide of aluminum, yttrium, or hafnium. At least two of the following compounds are used: Compounds including those mentioned above can also be used.

[0109] The gate insulating layer 102 may contain halogen elements such as chlorine and fluorine. The concentration of halogen elements in the insulating layer 102 is 1×10 15 atoms / cm 3 More than 1×10 20 atoms / cm 3 The following would suffice.

[0110] In this embodiment, in order to reduce hydrogen in the gate insulating layer 102, 02 is sputtered using a silicon single crystal target and argon and oxygen gases. The hydrogen in the gate insulating layer 102 diffuses and reacts with the excess oxygen in the semiconductor film 111. It is extremely important to prevent the channel from becoming an I-type by forming the H2O component in succession. It is also important to prevent moisture from adhering to the interface between the gate insulating layer 102 and the semiconductor film 111. Therefore, the chamber is evacuated with a cryopump or other device to achieve a minimum pressure of 1×10 -7 ~1×10 -10 Torr (approx. 1×10 -5 Pa or more 1×10 -8 Ultra-high vacuum (Pa) It is preferable to perform sputtering in a so-called UHV region. When the gate insulating layer and the semiconductor film 111 are successively laminated so as not to expose the interface therebetween to the air, The surface of 102 is treated with oxygen radicals to make the surface an oxygen-excess region. In the heat treatment for improving the reliability in the process, oxygen is supplied to modify the semiconductor film 111 interface. It is effective in creating a supply source.

[0111] In addition, an oxygen excess region is formed by performing oxygen radical treatment on the gate insulating layer 102. The oxygen concentration at the surface of the semiconductor film 111 is lower than that in the inside of the gate insulating layer 102. In addition, the concentration of oxygen radicals is higher than that of oxygen radicals. In this case, the oxygen concentration at the interface between the gate insulating layer 102 and the semiconductor film 111 becomes high.

[0112] The gate insulating layer 102 is subjected to oxygen radical treatment, a semiconductor film 111 is laminated thereon, and then a heat treatment is performed. For example, the oxygen concentration on the gate insulating layer 102 side of the semiconductor film 111 also becomes high.

[0113] As the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn is formed. For example, the semiconductor film 111 may be formed by sputtering an oxide semiconductor containing In, Ga, and Zn. The conductive film may be formed to a thickness of 50 nm. Using an oxide semiconductor target containing Ga and Zn, the distance between the substrate and the target was Distance 170 mm, pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, argon or oxygen atmosphere In addition, the use of a pulsed direct current (DC) power supply reduces dust. This is preferable because the film thickness distribution becomes uniform.

[0114] Using an oxide semiconductor target containing In, Ga, and Zn, The film can be formed in an oxygen atmosphere. Here, the IGZO film contains as much oxygen as possible. In order to achieve this, an oxide semiconductor containing In, Ga, and Zn was used as a target, and the amount of oxygen Pulse D under an atmosphere of 90% or more oxygen and 10% or less Ar The sputtering method is performed using the C sputtering method to form an oxygen-excess IGZO film.

[0115] In this manner, the gate insulating layer 102 containing excess oxygen and the semiconductor By continuously depositing the film 111, the interface between the films is stabilized due to the excess oxygen. This improves the reliability of FT. If the substrate is exposed to the air before the IGZO film is deposited, Moisture and other substances may adhere to the interface, adversely affecting the interface condition, causing variations in threshold voltage and degradation of electrical characteristics. Moisture can cause problems such as a normally-on TFT. By continuously depositing the film without exposure to the air, hydrogen compounds are formed at the interface. Therefore, by successively depositing the films, the threshold voltage is reduced. Reduction of ragging, prevention of deterioration of electrical characteristics, and shift of TFT to the normally-on side. The shift can be reduced, and preferably eliminated.

[0116] Next, the semiconductor film 111 is processed by etching using a mask 113, and the semiconductor layer 112 is The semiconductor layer 112 is formed by photolithography or droplet deposition. A mask 113 is formed by a discharge method, and the semiconductor film 111 is etched using the mask 113. It can be formed by applying

[0117] The end of the semiconductor layer 112 is etched into a tapered shape, so that the step shape This can prevent wiring from being disconnected.

[0118] Next, an oxygen-deficient oxide containing In, Ga, and Zn is deposited on the gate insulating layer 102 and the semiconductor layer 112. A semiconductor film 114, which is a nitride semiconductor film, is formed (see FIG. 7(C)). The mask 116 is formed by photolithography or inkjet printing. The semiconductor film 114 is processed by etching using a mask 116. Then, a semiconductor film 115 is formed (see FIG. 7(D)). The semiconductor film 115 has a thickness of 2 to 100 nm. The semiconductor film 114 is formed of a rare gas (preferably, arsenic). The film is formed in a nitrogen atmosphere.

[0119] In addition, the etching of the IGZO semiconductor film such as the semiconductor film 111 and the semiconductor film 115 is performed using a quenching gas. Organic acids such as phosphoric acid and oxalic acid can be used as etchants. The semiconductor film 111 can be etched in 150 seconds using ITO07N (manufactured by Kanto Chemical Co., Ltd.). .

[0120] A conductive film 117 is formed over the semiconductor film 115 (see FIG. 7E).

[0121] The conductive film 117 is made of aluminum, copper, silicon, titanium, neodymium, scandium, or the like. Aluminum to which elements for improving heat resistance or elements for preventing hillocks, such as aluminum or molybdenum, have been added. It is preferable to form the semiconductor layer by a single layer or a multilayer of a silicon alloy. The film on the side in contact with the film is made of titanium, tantalum, molybdenum, tungsten, or any of these elements. A laminated structure formed of a nitride of the base material and then forming aluminum or an aluminum alloy on top of it. Furthermore, the upper and lower surfaces of the aluminum or aluminum alloy may be coated with titanium. , tantalum, molybdenum, tungsten, or nitrides of these elements. Here, the conductive film 117 may be formed using a titanium film, an aluminum film, or a titanium A laminated conductive film of the film is used.

[0122] A laminate of a titanium film, an aluminum film, and a titanium film provides low resistance and also provides a high resistance to aluminum. Hillocks are unlikely to occur on the film.

[0123] The conductive film 117 is formed by a sputtering method or a vacuum deposition method. Conductive nano paste such as copper is used to print the film using screen printing, inkjet printing, etc. It may be formed by baking.

[0124] Next, a mask 118 is formed over the conductive film 117. The source and drain electrode layers 105a and 105b are formed by etching and separating the layers. (See FIG. 7(F)). As shown in FIG. 7 of this embodiment, the conductive film 117 is wet-etched. Then, the conductive film 117 is isotropically etched, so that the end of the mask 118 and the source The edges of the drain electrode layers 105a, 105b are less coincident and more recessed. Next, the semiconductor film 115 having n-type conductivity is etched using the mask 118 to form a semiconductor layer. Then, source and drain regions 104a and 104b are formed (see FIG. 7(G)). Depending on the etching conditions, in the etching process of the semiconductor film 115, The exposed region is also partially etched to become the semiconductor layer 103. The channel region of the semiconductor layer 103 between the regions 104a and 104b is as shown in FIG. In the semiconductor layer 103, which is an IGZO semiconductor layer, the thin film thickness region The region is from 2 nm to 200 nm, preferably from 20 nm to 150 nm.

[0125] Furthermore, the semiconductor layer 103 may be subjected to oxygen radical treatment in the same manner as the gate insulating layer 102. By subjecting the exposed channel formation region of the semiconductor layer 103 to oxygen radical treatment, This allows the surface of the semiconductor layer to become an oxygen excess region.

[0126] FIG. 4B shows a thin-film transistor in which the channel formation region of the semiconductor layer 103 has been subjected to oxygen radical treatment. In the thin film transistor 170e, a semiconductor The exposed area of ​​the conductor layer 103 is modified to an oxygen excess area by oxygen radical treatment.

[0127] By making the surface of the semiconductor layer an oxygen-excess region, hydrogen is prevented from being mixed into the semiconductor layer. The back channel becomes an oxygen-deficient region, preventing conduction between the source and drain, and thus reducing the off-state current. In this way, the semiconductor layer in the back channel portion is also made into an oxygen excess region. Therefore, the back channel semiconductor can be treated with oxygen radicals in the same way as the gate insulating layer. It is effective to subject the conductor layer to oxygen radical treatment.

[0128] The ends of the source and drain electrode layers 105a and 105b and the source and drain regions The ends of the regions 104a and 104b are not aligned but offset from each other, and the source electrode layer or the drain electrode layer The source or drain regions 104a and 104b are provided on the outside of the ends of the first and second electrodes 105a and 105b. The ends are formed.

[0129] After this, the mask 118 is removed. Through the above steps, a thin film transistor 170a is formed. It is possible.

[0130] Next, a manufacturing process of the thin film transistor 170b shown in FIG. 5(B1)(B2) is shown in FIG.

[0131] FIG. 8A shows a state in which the mask 113 has been removed in the process of FIG. A semiconductor film 114 and a conductive film 121 are laminated in this order on the substrate 12 (see FIG. 8(B)). The composite semiconductor film 114 and the conductive film 121 are successively formed by sputtering without being exposed to the atmosphere. This can be done.

[0132] A mask 122 is formed over the semiconductor film 114 and the conductive film 121, and the conductive film 121 is 121 is wet-etched to form source and drain electrode layers 105a and 105 b is formed (see FIG. 8(C)).

[0133] Next, the semiconductor film 114 is dry-etched to form the source or drain region 104a. In the same process, a part of the semiconductor layer 112 is also etched. As shown in FIG. 8, the source or drain region 104a, Etching to form 104b and source and drain electrode layers 105a and 105b. If the same mask is used for both, the number of masks can be reduced, simplifying the process and reducing costs. can be measured.

[0134] Thin film transistors 170a, 170b, and 170c are also provided on the thin film transistors 170d, As with 70e, an insulating film may be formed as a protective film. The protective film can be formed in the same manner as above. The purpose of this is to prevent the intrusion of contaminating impurities such as fluorine, and a dense film is preferable. An oxide film is formed on the transistors 170a, 170b, 170c, 170d, and 170e as a protective film. (Silicon oxide film, silicon oxynitride film, aluminum oxide film, aluminum oxynitride film) and nitride Films (silicon nitride film, silicon oxynitride film, aluminum nitride film, aluminum oxynitride film) The silicon oxide film is formed by deposition in a nitrogen and argon atmosphere using a silicon target. The aluminum nitride film and aluminum oxynitride film can be formed by DC sputtering in air. The aluminum film can be formed by RF sputtering using an aluminum nitride target. The aluminum oxide film was formed by RF sputtering using an aluminum oxide target. Furthermore, vacuum baking may be performed before forming the protective film.

[0135] In addition, the semiconductor layer 103 and the source and drain regions 104a, 104b, etc. are oxidized. It is preferable to perform a heat treatment on the semiconductor film after the film formation. However, it may be performed immediately after the film formation, after the formation of the conductive film 117, after the formation of the protective film, etc. It can be performed in combination with other heat treatments. The heating temperature is 200°C or higher and 60°C or lower. The temperature may be set to 0° C. or lower, and preferably 300° C. to 500° C. As shown in FIG. When the source region or drain region 104a, 104b is successively formed, the stacked layers are Heat treatment may be performed after the semiconductor layer 103 and the source or drain region. The steps 104a and 104b may be carried out multiple times in separate steps.

[0136] The ends of the source and drain electrode layers 105a and 105b and the source and drain regions The ends of the regions 104a and 104b are not aligned but are offset from each other, so that the source electrode layer or the drain electrode layer is not aligned. Since the distance between the ends of the drain electrode layers 105a and 105b is large, This makes it possible to prevent leakage current and short circuits between the electrode layers 105a and 105b. Thus, a thin film transistor having high reliability and high withstand voltage can be manufactured.

[0137] Also, as in the thin film transistor 170c of FIG. 6(A1)(A2), The ends of the drain regions 104a and 104b are aligned with the ends of the source and drain electrodes. The source and drain electrode layers 105a and 105b may be formed by etching. 10. A gate and an etch to form source or drain regions 104a, 104b. By dry etching, a thin film transistor such as the thin film transistor 170c shown in FIG. The semiconductor film 115 having n-type conductivity can be formed into a source electrode and a The drain electrode is used as a mask to etch the source or drain regions 104a, 10 Even if the thin film transistor 4b is formed, the shape is the same as that of the thin film transistor 170c shown in FIG. .

[0138] A source region or a drain region (oxygen-deficient oxide semiconductor layer containing In, Ga, and Zn) The gate electrode layer, the gate insulating layer, the semiconductor layer (oxygen peroxide containing In, Ga, and Zn) are not provided. In the case of a stacked structure of a gate electrode layer, a gate oxide semiconductor layer, a source electrode layer, and a drain electrode layer, The distance between the electrode layer and the source electrode layer or the drain electrode layer becomes short, and the parasitic capacitance between them increases. Furthermore, this increase in parasitic capacitance becomes more pronounced as the semiconductor layer becomes thinner. In this embodiment mode, a gate electrode layer, a gate insulating layer, and a gate insulating film are provided. The insulating layer, the semiconductor layer, the source region or drain region, the source electrode layer, and the drain electrode layer are Since the thin-film transistor has a laminated structure, the semiconductor layer can be thin without any loss of sensitivity. The raw volume can be reduced.

[0139] According to the present embodiment, a thin-film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio is obtained. Thus, a thin film transistor having good dynamic characteristics can be obtained. As a result, it is possible to provide a semiconductor device having a thin film transistor with excellent electrical characteristics and high reliability. can.

[0140] (Embodiment 2) This embodiment is an example of a thin film transistor having a multi-gate structure according to one embodiment of the present invention. Therefore, the other steps can be performed in the same manner as in the first embodiment, and the same parts or functions as those in the first embodiment can be used. Descriptions of functional parts and repetitive steps will be omitted.

[0141] In this embodiment, a thin film transistor used in a semiconductor device will be described with reference to FIG. 11(A) and (B) will be used to explain the above.

[0142] FIG. 9A is a plan view showing a thin film transistor, and FIG. 9B is a plan view showing the thin film transistor in FIG. 1 corresponds to a cross-sectional view showing the thin film transistor 170a along line E1-E2.

[0143] As shown in FIG. 9(A) and (B), gate electrode layers 151a and 151b, A gate insulating layer 152, semiconductor layers 153a and 153b, and a source or drain region 154a , 154b, 154c, and the multi-layer structure including the source electrode layer or the drain electrode layer 155a, 155b. A thin film transistor 171a having a double-gate structure is provided.

[0144] The semiconductor layers 153a and 153b are oxygen-excess oxide semiconductor layers containing In, Ga, and Zn. and the source or drain regions 154a, 154b, 154c are made of In, Ga, and Z. The source and drain regions 154a and 154b are oxygen-deficient oxide semiconductor layers containing n. The semiconductor layers 154b and 154c have higher carrier concentrations than the semiconductor layers 153a and 153b.

[0145] A gate insulating layer 152 having an oxygen excess region and a semiconductor layer 15 which is an oxygen excess oxide semiconductor layer 3a and 153b are compatible with each other, and good interface characteristics can be obtained.

[0146] After the gate insulating layer 152 is formed, the surface of the gate insulating layer 152 is subjected to oxygen radical treatment to form an oxygen permeation. The gate insulating layer 152 and the semiconductor layers 153a and 153b are successively formed. do.

[0147] The oxygen-deficient oxide semiconductor layers of the source and drain regions 154a, 154b, and 154c are The semiconductor layers 153a and 153b have crystal grains with a size of 1 nm or more and 10 nm or less. The carrier concentration is high.

[0148] The semiconductor layer 153a and the semiconductor layer 153b are each formed as a source region or a drain region 154c. On the other hand, the semiconductor layer 153a is electrically connected to the source region or the drain region through the A source or drain electrode layer 155a and a semiconductor layer 153 are connected to each other through an in-region 154a. b is a source electrode layer or a drain electrode layer 15 through a source region or a drain region 154b. It is electrically connected to 5b.

[0149] FIG. 10 shows a thin film transistor 171b having a multi-gate structure having another configuration. FIG. 10(B) is a plan view showing the thin film transistor 171b, and FIG. 10(A) is a plan view showing the thin film transistor 171b. 10 corresponds to a cross-sectional view showing the thin film transistor 171b taken along line F1-F2 in FIG. In the transistor 171b, a source electrode layer or A wiring layer 156 is provided, which is formed in the same process as the drain electrode layers 155a and 155b. The conductor layer 153a and the semiconductor layer 153b are connected to the source or drain region 154c and the wiring layer 1 56 are electrically connected.

[0150] FIG. 11 shows a thin film transistor 171c having a multi-gate structure having another configuration. FIG. 11(B) is a plan view showing the thin film transistor 171c, and FIG. 11(A) is a plan view showing the thin film transistor 171c. 11 corresponds to a cross-sectional view showing the thin film transistor 171c taken along line G1-G2 in FIG. In the transistor 171c, the semiconductor layer 153a and the semiconductor layer 153b are formed into a single continuous layer. In this example, the semiconductor layer 153 is formed as the gate insulating layer 152. The gate electrode layer 151a and the gate electrode layer 151b are provided across each other with the gate electrode layer 151a and the gate electrode layer 151b interposed therebetween.

[0151] In this way, in a thin film transistor having a multi-gate structure according to one embodiment of the present invention, each gate The semiconductor layer formed on the electrode layer may be provided continuously or as a source region or a drain region. A plurality of semiconductor layers may be provided and electrically connected via a gate region, a wiring layer, and the like.

[0152] The thin film transistor having a multi-gate structure according to one embodiment of the present invention has a small off-current. A semiconductor device including such a thin film transistor can have high electrical characteristics and high reliability. do.

[0153] In this embodiment, a double-gate structure having two gate electrode layers is used as an example of the multi-gate structure. However, one embodiment of the present invention is directed to a triple gate structure having more gate electrode layers. can also be applied.

[0154] In this embodiment, a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), , source region and drain region (oxygen-deficient oxide semiconductor layer), source electrode layer and drain A thin-film transistor having a laminated structure of an electrode layer and a crystal grain in an oxygen-deficient oxide semiconductor layer is formed. By using high carrier concentration source and drain regions having It is possible to suppress parasitic capacitance while keeping the film thickness of the layer thin. Since the ratio of the insulating layer to the insulating film is sufficient, the parasitic capacitance is sufficiently suppressed.

[0155] According to the present embodiment, a thin-film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio is obtained. Thus, a thin film transistor having good dynamic characteristics can be obtained. As a result, it is possible to provide a semiconductor device having a thin film transistor with excellent electrical characteristics and high reliability. can.

[0156] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0157] (Embodiment 3) In this embodiment, a source region and a drain region in a thin film transistor according to one embodiment of the present invention are Therefore, the other steps can be performed in the same manner as in the first or second embodiment. The present invention is also applicable to the same parts and steps as those in the first and second embodiments, or parts and steps having similar functions. The repeated explanation will be omitted.

[0158] In this embodiment, a thin film transistor 173 used in a semiconductor device will be described with reference to FIG. I will use this to explain.

[0159] As shown in FIG. 12, a gate electrode layer 101, a semiconductor layer 103, a second semiconductor layer 104, and a The first source or drain regions 106a, 106b are Source or drain regions 104a, 104b, A thin film transistor 173 including source and drain electrode layers 105a and 105b is provided. It is being done.

[0160] The thin film transistor 173 of this embodiment has a source region or drain region 104a, 4b and the source or drain electrode layer 105a, 105b. The source and drain regions 106a and 106b are provided as the source and drain regions. It is being done.

[0161] The semiconductor layer 103 is an oxygen-excess oxide semiconductor layer containing In, Ga, and Zn. The drain regions 104a, 104b, 106a, 106b are made of In, Ga, and Zn. The oxygen-deficient oxide semiconductor layer includes:

[0162] The source or drain regions 104a and 104b and the source or drain electrode layer 10 The source region or drain region 106a, 106b provided between the first and second gate electrodes 5a, 105b is Contains impurity elements.

[0163] The impurity elements contained in the source and drain regions 106a and 106b are, for example, Indium, gallium, zinc, magnesium, aluminum, titanium, iron, tin, calcium Zn, Scandium, Yttrium, Zirconium, Hafnium, Boron, Thallium, Gel These impurity elements (e.g., magnesium, lead, etc.) can be used. When the source or drain region contains a metal such as aluminum or titanium, it acts as a blocker of oxygen. The oxygen concentration in the semiconductor layer can be adjusted to an optimal range by heat treatment after film formation. In this embodiment, the source region or drain region 106a, 106b can be held in the An oxygen-deficient oxide semiconductor layer containing In, Ga, and Zn, which contains titanium, is used.

[0164] The source and drain regions 106a and 106b are made of oxygen-deficient oxide semiconductors containing titanium. When the semiconductor layer is provided, the source region or drain region 1 is formed as the source electrode layer and the drain electrode layer. An aluminum film is formed directly on 06a and 106b, and a titanium film is formed on the aluminum film. It is possible.

[0165] A thin film transistor having a multi-layer source or drain region according to one embodiment of the present invention is more High-speed operation is possible, and a semiconductor device including such a thin film transistor has excellent electrical characteristics and It is possible to provide high reliability.

[0166] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0167] (Embodiment 4) In this embodiment, the shape and manufacturing method of the thin film transistor are partially different from those in the first embodiment. Therefore, the rest can be performed in the same manner as in the first embodiment, and the same Descriptions of parts or parts having similar functions and repetitive steps will be omitted.

[0168] In this embodiment mode, a thin film transistor 174 used in a display device and a manufacturing process thereof will be described. FIG. 13(A1) shows a thin film transistor 174. 13(A2) and 14 are plan views of the thin film transistor along the line D1-D2 in FIG. 13(A1). 1A and 1B are cross-sectional views showing a transistor and a manufacturing process thereof.

[0169] As shown in FIGS. 13A and 13B, a gate electrode layer 101 and a semiconductor layer 10 are formed on a substrate 100. 3. Source or drain region 104a, 104b, source or drain electrode layer A thin film transistor 174 is provided, which includes 105a and 105b.

[0170] The semiconductor layer 103 is an oxygen-excess oxide semiconductor layer containing In, Ga, and Zn. The drain regions 104a, 104b are made of oxygen-deficient oxide containing In, Ga, and Zn. The source region or drain region 104a, 104b is a semiconductor layer. The carrier concentration is higher.

[0171] After the gate insulating layer 102 is formed, the surface of the gate insulating layer 102 is subjected to oxygen radical treatment to form an oxygen permeation. The gate insulating layer 102 and the semiconductor layer 103 are formed in succession.

[0172] A gate insulating layer 102 having an oxygen excess region and a semiconductor layer 10 which is an oxygen excess oxide semiconductor layer 3 has good compatibility and can provide good interface properties.

[0173] The oxygen-deficient oxide semiconductor layers of the source and drain regions 104a and 104b are 1 nm or thicker than the It has crystal grains with a size of 10 nm or less and has a higher carrier concentration than the semiconductor layer 103.

[0174] The semiconductor layer 103 is connected to a source electrode layer or a drain electrode layer via a source region or a drain region 104a. A source electrode layer 105a and a source electrode layer or a drain electrode layer 104b are formed through the source electrode layer 105a and the source electrode layer or the drain electrode layer 104b. It is electrically connected to the rain electrode layer 105b.

[0175] A manufacturing process of the thin film transistor 174 will be described with reference to FIG. Next, a gate insulating layer 102 is formed on the gate electrode layer 101. After performing oxygen radical treatment on the surface of the gate insulating layer 102, an acid containing In, Ga, and Zn was added. The semiconductor film 131 is an oxygen-rich oxide semiconductor film, and the semiconductor film 132 is an oxygen-deficient oxide semiconductor film containing In, Ga, and Zn. A semiconductor film 132, which is a compound semiconductor film, and a conductive film 133 are formed in this order (see FIG. 14(A)). .

[0176] The gate insulating layer 102 is a semiconductor film made of an oxygen-excess oxide semiconductor containing In, Ga, and Zn. The semiconductor film 131 is an oxygen-deficient oxide semiconductor film containing In, Ga, and Zn. The conductive film 132 and the conductive film 133 can be formed successively without being exposed to the air. By continuously forming the film without exposing it to the air, atmospheric components and airborne contaminants are eliminated. Since each layer interface can be formed without being contaminated by chemical elements, thin film transistors The variation in characteristics can be reduced.

[0177] In this embodiment, an example is given in which exposure is performed using a high-resolution mask to form the mask 135. A resist is formed to form a mask 135. The resist may be a positive resist or A positive resist is used here.

[0178] Next, a multi-tone mask is used as a photomask to irradiate the resist with light. Expose.

[0179] A multi-tone mask has three exposure levels for the exposed, intermediate and unexposed parts. This is a mask that can produce multiple (typically two types) It is possible to form a resist mask having a region of thickness of 100 nm or more. By using this mask, it is possible to reduce the number of photomasks.

[0180] Typical examples of multi-tone masks include gray-tone masks and half-tone masks.

[0181] The gray-tone mask is a mask that includes a light-transmitting substrate and a light-shielding portion and a diffraction grating formed thereon. The light transmittance in the light-shielding area is 0%. The spacing between light-transmitting parts such as dots, meshes, etc. is set to be equal to or less than the resolution limit of the light used for exposure. By doing so, it is possible to control the light transmittance. Use either slits, dots, meshes, or non-periodic slits, dots, meshes It is possible.

[0182] The light-transmitting substrate may be a light-transmitting substrate such as quartz. The diffraction grating can be made of light-absorbing, light-shielding materials such as chromium or chromium oxide. do.

[0183] When the gray-tone mask is irradiated with exposure light, the light transmittance in the light-shielding area is 0%. In other words, the light transmittance is 100% in the area where the light shielding portion and the diffraction grating are not provided. In the case of a diffraction grating, the light transmittance can be adjusted in the range of 10 to 70%. The transmittance can be adjusted by adjusting the spacing and pitch of the slits, dots, or meshes of the diffraction grating. It is more possible.

[0184] The halftone mask is a mask that includes a light-transmitting substrate and a semi-transmitting portion and a light-shielding portion formed thereon. The semi-transparent part is made up of MoSiN, MoSi, MoSiO, MoSiON, and Cr The light-shielding part is made of a light-shielding material that absorbs light, such as chromium or chromium oxide. It can be formed using materials.

[0185] When exposure light is irradiated onto a half-tone mask, the light transmittance in the light-shielding area is 0%. In other words, the light transmittance is 100% in the area where the light-shielding portion and the semi-transmitting portion are not provided. In the semi-transmitting portion, the light transmittance can be adjusted in the range of 10 to 70%. The transmittance can be adjusted by adjusting the material of the semi-transmissive portion.

[0186] After exposure using a multi-tone mask, the film is developed to have a thickness of 100 μm, as shown in FIG. A mask 135 having different regions can be formed.

[0187] Next, the semiconductor film 131, the semiconductor film 132 having n-type conductivity, and the conductive film 133 are removed by a mask 135. The conductive film 133 is etched and separated. As a result, the semiconductor film 136 has an n-type conductivity. A semiconductor film 137 and a conductive film 138 can be formed (see FIG. 14B).

[0188] Next, the mask 135 is ashed. As a result, the area of ​​the mask is reduced and the thickness is reduced. At this time, the resist of the mask in the thin region (which overlaps a part of the gate electrode layer 101) is The regions (which are to be removed) can be removed to form the isolated mask 139 (see FIG. 14(C)). Light. ).

[0189] The conductive film 138 is etched using the mask 139, and the source or drain electrode layer 1 As in the present embodiment, the conductive film 138 is formed by wet etching. Then, the conductive film 138 is isotropically etched, so that the end of the mask 139 and the source The ends of the drain electrode layers 105a and 105b are not aligned but are recessed. The semiconductor film 137 having n-type conductivity is provided on the outside of the drain electrode layers 105a and 105b. Then, a mask 139 is used to form an n-type conductive film. The semiconductor film 137 and the semiconductor film 136 are etched to form a source region or a drain region. The regions 104a and 104b are then formed into the semiconductor layer 103 (see FIG. 14(D)). The semiconductor layer 103 is only partially etched, forming a semiconductor layer having a groove.

[0190] A process for forming source and drain regions 104a and 104b, and a process for forming a groove in the semiconductor layer 103 Similarly, the end of the semiconductor layer 103 is partially etched. After that, the mask 139 is removed.

[0191] Through the above steps, a thin film transistor 174 shown in FIGS. 13(A) and 13(B) can be manufactured. do.

[0192] As in the present embodiment, a multi-tone mask is used to form a multi-layer mask having a plurality of thicknesses (typically, two types). By using a resist mask having regions, the number of resist masks can be reduced. This simplifies the process and reduces costs.

[0193] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0194] (Embodiment 5) In this embodiment mode, in a display device which is an example of a semiconductor device of the present invention, The following is an example of manufacturing a thin film transistor arranged in at least a part of a driver circuit and a pixel portion. Explained below.

[0195] The thin film transistor disposed in the pixel portion is according to any one of the first to fourth embodiments. In addition, the thin film transistor shown in any one of the first to fourth embodiments is formed as follows. Since the photodiode is an n-channel TFT, the driver circuit is composed of n-channel TFTs. A part of the driver circuit capable of performing this is formed on the same substrate as the thin film transistor of the pixel portion.

[0196] FIG. 1 is a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device of the present invention. An example is shown in FIG. 16A. The display device shown in FIG. A pixel portion 5301 having a plurality of pixels, and a scanning line driver circuit 5302 for selecting each pixel. and a signal line driver circuit 5303 for controlling input of a video signal to a selected pixel.

[0197] The pixel portion 5301 includes a signal line driver circuit 5303 and a plurality of signal lines arranged in a column direction. The signal line driver circuit 5303 is connected to the signal line driver circuit 5303 by lines S1 to Sm (not shown). A plurality of scanning lines G1 to Gn (not shown) are arranged extending from 5302 in the row direction. The scanning line driver circuit 5302 is connected to the signal lines S1 to Sm and the scanning lines G1 to Gn. The image sensor has a plurality of pixels (not shown) arranged in a matrix. Signal line Sj (any one of signal lines S1 to Sm), scanning line Gi (any one of scanning lines G1 to Gn) Either one of them is connected.

[0198] In addition, the thin film transistor shown in any one of the first to fourth embodiments is an n-channel The signal line driver circuit is configured with n-channel TFTs. He explains.

[0199] The signal line driver circuit shown in FIG. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes A first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor It has a transistor 5603c.

[0200] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, and a third wiring 5613. and are connected to the wirings 5621_1 to 5621_M. 5602_M are a first wiring 5611, a second wiring 5612, a third wiring 561 3 and wiring 5621_1 to 5621_5 corresponding to the switch groups 5602_1 to 5602_M, respectively. Each of the wirings 5621_1 to 5621_M is connected to the first A thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor For example, the wiring 5621 in the Jth column is connected to three signal lines via a resistor 5603c. _J (any one of the wirings 5621_1 to 5621_M) is a switch group 5602 The first thin film transistor 5603a, the second thin film transistor 5603b, and and the third thin film transistor 5603c, the signal line Sj-1, the signal line Sj, the signal line S j+1 is connected to

[0201] The first wiring 5611, the second wiring 5612, and the third wiring 5613 are each connected to a signal line. The number is entered.

[0202] It is preferable that the driver IC 5601 is formed on a single crystal substrate. The switch group 5602_1 to 5602_M is formed on the same substrate as the pixel section. Therefore, the driver IC 5601 and the switch group 5602_1 to 5602_ It is recommended to connect to M via an FPC or similar.

[0203] Next, the operation of the signal line driver circuit shown in FIG. 17 will be described with reference to the timing chart of FIG. The timing chart in FIG. 18 is explained with reference to the timing chart in FIG. Further, during the selection period of the i-th scanning line Gi, is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, when a scanning line of another row is selected, the signal line driver circuit of FIG. In this case, the same operation as in FIG. 18 is performed.

[0204] In the timing chart of FIG. 18, the wiring 5621_J in the Jth column is connected to the first thin-film transistor. a second thin film transistor 5603b, and a third thin film transistor 560 When connected to signal line Sj-1, signal line Sj, and signal line Sj+1 via 3c It shows.

[0205] In the timing chart of FIG. 18, the timing when the i-th scanning line Gi is selected, The on / off timing 5703a of the first thin film transistor 5603a, The on / off timing 5703b of the third thin film transistor 56 The on / off timing of 03c is input to 5703c and the wiring 5621_J of the Jth row. 5 shows signal 5721_J.

[0206] The wirings 5621_1 to 5621_M are connected to the first sub-selection period T1 and the second sub-selection period T2. In the first sub-selection period T2 and the third sub-selection period T3, different video signals are input. For example, the video signal input to the wiring 5621_J in the first sub-selection period T1 is The signal is input to the signal line Sj-1 and is input to the wiring 5621_J in the second sub-selection period T2. The video signal to be output is input to the signal line Sj, and the line 5621 is connected to the line Sj during the third sub-selection period T3. The video signal input to the first sub-selection period is input to the signal line Sj+1. In the period T1, the second sub-selection period T2, and the third sub-selection period T3, the wiring 5621_ The video signals input to J are Data_j-1, Data_j, and Data_j+ Let's say it's 1.

[0207] As shown in FIG. 18, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c At this time, Data_j-1 input to the wiring 5621_J is turned off. The signal is input to the signal line Sj-1 via the transistor 5603a. Second sub-selection period T2 In this case, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a is turned on. and the third thin film transistor 5603c are turned off. At this time, the input The Data_j to be output is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first The first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the third thin film transistor 56 03c and input to the signal line Sj+1.

[0208] From the above, the signal line driver circuit in FIG. 17 divides one gate selection period into three. During one gate selection period, a video signal is input from one wiring 5621 to three signal lines. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the pixel area is formed and the substrate on which the pixel area is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0209] As shown in FIG. 17, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0210] For example, three or more signal lines are connected to one wiring during each of three or more sub-selection periods. When a video signal is input to each of them, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two or It is preferably divided into three sub-selection periods.

[0211] As another example, as shown in the timing chart of FIG. 19, one selection period is precharged. The first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 are Furthermore, in the timing chart of FIG. 19, the i-th scanning line Gi is selected. the timing of turning on and off the first thin film transistor 5603a; a, the on-off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the membrane transistor 5603c and the wiring 562 of the Jth column 19 shows a signal 5821_J input to the precharge In the period Tp, the first thin film transistor 5603a and the second thin film transistor 5603 At this time, the input to the wiring 5621_J is turned on. The input precharge voltage Vp is applied to the first thin film transistor 5603a, the second thin film transistor 5603b, and the and a third thin film transistor 5603c are connected to the signal line Sj- 1, signal line Sj, and signal line Sj+1. The thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor At this time, the signal Dat input to the wiring 5621_J is turned off. a_j-1 is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor The third thin film transistor 5603a and the third thin film transistor 5603c are turned off. Data_j input to the wiring 5621_J is input to the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor The first thin film transistor 5603a and the second thin film transistor 5603c are turned on. At this time, Data_j+1 input to the wiring 5621_J is The signal is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0212] From the above, the signal line driver circuit of FIG. 17 to which the timing chart of FIG. 19 is applied By providing a precharge selection period before the sub selection period, the signal lines can be precharged. This allows high-speed writing of video signals to the pixels. In this embodiment, the same reference numerals are used for the same parts as those in FIG. 18, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0213] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit includes a shift register, a buffer, and a In some cases, a level shifter may be included. In the circuit, a clock signal (CLK) and a start pulse signal (SP ) is input, the selection signal is generated. The generated selection signal is buffered The signal is buffered and amplified in the 10-bit signal line and then fed to the corresponding scan line. The gate electrodes of the transistors are connected. Since they must all be turned on at the same time, the buffer must be capable of passing a large current. Used.

[0214] One form of a shift register used as a part of a scanning line driving circuit will be described with reference to FIGS. 20 and 21. He explains.

[0215] The circuit configuration of the shift register is shown in Figure 20. The shift register shown in Figure 20 has multiple free Flip-flop 5701_i (any of flip-flops 5701_1 to 5701_n) Also, the first clock signal, the second clock signal, the start pulse It operates when a signal and a reset signal are input.

[0216] The connection relationship of the shift register in Fig. 20 will be described. The shift register in Fig. 20 has i-stage The first flip-flop 5701_i (flip-flops 5701_1 to 5701_n In either one of them, the first wiring 5501 shown in FIG. 21 is connected to the seventh wiring 5717_i-1. 21 is connected to the seventh wiring 5717_i+1. 21 is connected to the seventh wiring 5717_i, The sixth wiring 5506 is connected to the fifth wiring 5715 .

[0217] In addition, the fourth wiring 5504 shown in FIG. 21 corresponds to the second wiring in the odd-numbered flip-flops. 5712, and in the even-numbered flip-flops, it is connected to the third wiring 5713. The fifth wiring 5505 shown in FIG.

[0218] However, the first wiring 5501 shown in FIG. 21 of the first-stage flip-flop 5701_1 is 21 of the n-th flip-flop 5701_n in the n-th stage. The second wiring 5502 is connected to the sixth wiring 5716 .

[0219] The first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 can be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 are respectively connected to the first power supply line and the third power supply line. This may also be called the power line 2.

[0220] Next, the details of the flip-flop shown in FIG. 20 are shown in FIG. The flip-flop includes a first thin film transistor 5571, a second thin film transistor 5572, A third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor a sixth thin film transistor 5575, a seventh thin film transistor 5576, and and an eighth thin film transistor 5578. A second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor a fifth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, The seventh thin film transistor 5577 and the eighth thin film transistor 5578 are n-channel A transistor in which the gate-source voltage (Vgs) exceeds the threshold voltage (Vth). When this occurs, the device is in a conductive state.

[0221] Next, the connection configuration of the flip-flop shown in FIG. 20 will be described below.

[0222] A first electrode (either a source electrode or a drain electrode) of the first thin film transistor 5571 is connected to a fifth wiring 5504, and a second electrode (source) of a first thin film transistor 5571 is connected to The other of the source electrode and the drain electrode is connected to a third wiring 5503 .

[0223] A first electrode of the second thin film transistor 5572 is connected to the fourth wiring 5506. A second electrode of the second thin film transistor 5572 is connected to a third wiring 5503 .

[0224] A first electrode of the third thin film transistor 5573 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5573 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. will be done.

[0225] A first electrode of the fourth thin film transistor 5574 is connected to a sixth wiring 5506. The second electrode of the thin film transistor 5574 is the gate electrode of the second thin film transistor 5572. , and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5 It is connected to the gate electrode of 571.

[0226] A first electrode of the fifth thin film transistor 5575 is connected to a fifth wiring 5505. The second electrode of the thin film transistor 5575 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. will be done.

[0227] A first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5576 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5 It is connected to the gate electrode of 572.

[0228] A first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506. The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0229] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5543, a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0230] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 may be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 is a first power supply line, and the sixth wiring 5506 is a second power supply line. It may also be called.

[0231] In addition, the signal line driver circuit and the scanning line driver circuit may be any one of the first to fourth embodiments. It is also possible to manufacture the device using only the n-channel TFT shown in the embodiment 1 to the embodiment 2. The n-channel TFT shown in any one of the four modes has a high transistor mobility, so it is easy to drive It is possible to increase the driving frequency of the circuit. The n-channel TFT shown in any one of the above is an oxygen-deficient TFT containing indium, gallium, and zinc. The parasitic capacitance is reduced by the source region or drain region which is an oxide semiconductor layer. For example, in any of the first to fourth embodiments, The scanning line driver circuit using the n-channel TFT shown in FIG. 1 can be operated at high speed. In order to achieve this, it is possible to increase the frame frequency or insert a black screen. It is possible to do so.

[0232] Furthermore, the channel width of the transistor of the scanning line driving circuit is increased, and multiple scanning lines By arranging the drive circuit, it is possible to achieve even higher frame frequencies. When multiple scanning line driving circuits are arranged, a scanning line driving circuit for driving the even-numbered scanning lines is provided. The circuit is placed on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is placed on the opposite side. By placing the pixel clock in the pixel clockwise direction, it is possible to realize a high frame frequency.

[0233] In addition, an active matrix type light emitting display device, which is an example of the semiconductor device of the present invention, is manufactured. In this case, since a plurality of thin film transistors are arranged in at least one pixel, the scanning line driving circuit It is preferable to arrange a plurality of the active matrix type light emitting display device. An example is shown in FIG.

[0234] The light-emitting display device shown in FIG. 16B has a plurality of pixels each having a display element over a substrate 5400. A pixel portion 5401 for selecting each pixel, a first scanning line driver circuit 5402 for selecting each pixel, and a second scanning line driver circuit 5403 for selecting each pixel. A driver circuit 5404 and a signal line driver circuit 5405 for controlling the input of a video signal to a selected pixel 403.

[0235] In the case where a video signal input to a pixel of the light-emitting display device shown in FIG. 16B is in a digital format, When a pixel is turned on, the transistor is switched on and off to make it either emitting light or not. Therefore, gray scale display can be performed using area gray scale or time gray scale. The stacked gray scale method divides one pixel into multiple sub-pixels, and each sub-pixel is independently driven based on a video signal. The time gray scale method is a driving method that displays gray scales by changing the time when the pixel emits light. This is a driving method that displays gradations by controlling the period during which the liquid crystal display is turned on.

[0236] Light-emitting elements have a higher response speed than liquid crystal elements, so they are more suitable for time gray scale modulation than liquid crystal elements. Specifically, when displaying using the time gray scale method, one frame period is divided into multiple subframes. Then, the light emitting element of the pixel is divided into sub-frame periods according to the video signal. By dividing the period into multiple subframes, The total length of time that pixels actually emit light during one frame is controlled by the video signal. It is possible to control the brightness and display gradation.

[0237] In the light-emitting display device shown in FIG. 16B, a switching TFT and a When two TFTs are arranged, the first TFT, which is the gate wiring of the switching TFT, The signal input to the scanning line is generated by the first scanning line driver circuit 5402, and the current control TFT A signal input to the second scanning line, which is a gate wiring, is generated by a second scanning line driver circuit 5404. In this example, the signal input to the first scanning line and the signal input to the second scanning line are The signals for the scanning lines may be generated by a single scanning line driving circuit. The operation of the switching element is controlled by the number of transistors that the switching element has. A plurality of first scan lines may be provided for each pixel. All the signals input to the multiple first scanning lines may be generated by one scanning line driver circuit. , may be generated by a plurality of scanning line driving circuits.

[0238] In addition, in the light-emitting display device, the driver circuit may be configured with n-channel TFTs. A part of the driver circuit can be formed on the same substrate as the thin film transistor of the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those in any one of the first to fourth embodiments. It is also possible to fabricate the device using only the n-channel TFT shown in FIG.

[0239] The above-mentioned driving circuit is not limited to liquid crystal display devices and light-emitting display devices, but may also be used in devices with switching elements and It may also be used in electronic paper, where electrically connected elements are used to drive electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. The advantages are ease of reading, lower power consumption compared to other display devices, and the possibility of making them thin and lightweight. It has points.

[0240] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0241] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Electrophoretic displays do not require polarizing plates or opposing substrates, which are necessary for display devices, and are half the thickness and weight. Reduce.

[0242] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. A color display is also possible by using a color filter or particles having a pigment.

[0243] In addition, the above microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. 4. An active matrix substrate obtained by using any one of the thin film transistors It is possible.

[0244] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic material, magnetophoretic material, and a composite material thereof. Just use it.

[0245] Through the above steps, a display device with high reliability as a semiconductor device can be manufactured.

[0246] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0247] (Embodiment 6) Here, at least the gate insulating layer and the oxygen-excess oxide semiconductor layer are stacked and exposed to the air. An example of fabricating an inverted staggered thin film transistor by successive film formation without using a single layer is shown below. The process up to the process of performing continuous film formation is shown, and the subsequent processes are the same as those in the first to fourth embodiments. A thin film transistor may be manufactured according to any one of the above.

[0248] In this specification, continuous film formation refers to a process from a first film formation process performed by sputtering to a second film formation process performed by sputtering. During the series of processes up to the film formation step, the atmosphere in which the substrate is placed is a polluted atmosphere such as air. Always keep the device in a vacuum or inert gas atmosphere (nitrogen or rare gas atmosphere) without exposing it to air. By performing continuous film formation, the substrate to be treated is cleaned. This allows film formation while avoiding re-adhesion of moisture and the like to the plate.

[0249] A series of processes from the first film formation process to the second film formation process are carried out in the same chamber. is within the scope of continuous film formation in this specification.

[0250] In addition, a series of processes from the first film formation process to the second film formation process are performed in different chambers. In this case, after the first film formation process is completed, the substrate is transported between chambers without being exposed to the atmosphere. The application of a second film is also considered to be within the scope of successive film formation in this specification.

[0251] Between the first and second film formation processes, a substrate transfer process, an alignment process, and a slow cooling process are performed. or a step of heating or cooling the substrate to a temperature required for the second step. However, such a method is considered to be within the scope of continuous film formation in this specification.

[0252] However, the first step involves processes that use liquids, such as cleaning, wet etching, and resist formation. If the film formation step is between the first film formation step and the second film formation step, it does not fall within the scope of continuous film formation as used in this specification. Let's say that's not the case.

[0253] When performing continuous film formation without exposure to the atmosphere, a multi-chamber production system as shown in Figure 22 is used. It is preferable to use a manufacturing device.

[0254] The manufacturing apparatus is provided at its center with a transport mechanism (typically a transport robot 81) for transporting substrates. The transfer chamber 80 is provided with a transfer chamber 81 for transferring a plurality of substrates to and from the transfer chamber. A cassette chamber 82 for setting a cassette case to be stored is connected.

[0255] In addition, a plurality of processing chambers are connected to the transfer chamber via gate valves 83 to 88. Here, an example is shown in which five processing chambers are connected to a transfer chamber 80 having a hexagonal top surface shape. By changing the shape of the top surface of the transfer chamber, the number of process chambers that can be connected can be changed. For example, If it is shaped like a rectangle, three treatment chambers can be connected, and if it is shaped like an octagon, seven treatment chambers can be connected.

[0256] At least one of the five processing chambers is a sputtering chamber for sputtering. The sputtering chamber is provided with at least a sputtering target, The device includes a power application mechanism for sputtering the target, a gas introduction means, and a means for holding the substrate in a predetermined position. The sputtering chamber is also equipped with a substrate holder. The sputtering chamber is provided with a pressure control means for controlling the pressure within the chamber.

[0257] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used for depositing insulating films, while the DC sputtering method is mainly used for depositing metal films. It is used in.

[0258] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0259] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0260] The sputtering chamber is suitably used for the various sputtering methods described above.

[0261] In addition, the film formation method involves chemically reacting the target material with the sputtering gas components during film formation. The reactive sputtering method for forming these compound thin films and the application of voltage to the substrate during film formation are also used. There is also a bias sputtering method.

[0262] In addition, one of the five processing chambers is used for preheating the substrate before sputtering. a heating chamber for performing sputtering, a cooling chamber for cooling the substrate after sputtering, or This chamber performs plasma processing.

[0263] Next, an example of the operation of the manufacturing apparatus will be described.

[0264] A substrate cassette containing substrates 94 with the film-forming surface facing downward is set in the cassette chamber 82. The cassette chamber 82 is then placed in a decompressed state by a vacuum exhaust means provided in the cassette chamber 82. The inside of each processing chamber and the transfer chamber 80 is previously depressurized by a vacuum exhaust means provided therein. This prevents the substrate from coming into contact with the atmosphere while being transported between the processing chambers. It is possible to maintain a clean state without

[0265] The substrate 94 with the film-forming surface facing downward is provided with at least a gate electrode. A base insulating film may be provided between the gate electrode and the substrate. Although not limited thereto, a silicon nitride film, a silicon oxynitride film, etc. obtained by a sputtering method are used. When a glass substrate containing an alkali metal is used as the substrate 94, the base insulating film is Mobile ions such as sodium ions penetrate from the substrate into the semiconductor region above it, causing the electrical conductivity of the TFT to decrease. It has the effect of suppressing changes in characteristics.

[0266] Here, a silicon nitride film that covers the gate electrode is formed by plasma CVD, and the first gate layer is The silicon nitride film formed by the plasma CVD method is dense. By using it as the first gate insulating layer, it is possible to prevent pinholes from occurring. In this example, the gate insulating layer is a laminated layer, but is not limited thereto. The above laminated layers may be used.

[0267] Next, the gate valve 83 is opened and the first substrate 94 is loaded into the cassette by the transfer robot 81. Then, the gate valve 84 is opened and the wafer is transferred into the first processing chamber 89. In the first processing chamber 89, the substrate is heated by a heater or a lamp heater. In particular, if moisture is present in the gate insulating layer, it can damage the TFT. Heating before sputtering is effective because the thermal properties may change. If the moisture is sufficiently removed at the stage when the substrate is set in the chamber 82, this heat treatment can be performed without It is not necessary.

[0268] In addition, a plasma processing means is provided in the first processing chamber 89, and a plasma is applied to the surface of the first gate insulating layer. In addition, a heating means may be provided in the cassette chamber 82 to heat the cassette chamber 82. Heating may be performed to remove the residue.

[0269] Next, the gate valve 84 is opened and the substrate is transported to the transport chamber 80 by the transport robot 81. The gate valve 85 is opened, the substrate is transferred into the second processing chamber 90, and the gate valve 85 is closed.

[0270] Here, the second processing chamber 90 is a sputtering chamber using an RF magnetron sputtering method. -Let's say.

[0271] In the second processing chamber 90, a silicon nitride film (SiNx film) is formed as a first gate insulating layer. Perform the membrane.

[0272] After the SiNx film is formed, the gate valve 85 is opened and the transfer robot 8 is 1 to the transfer chamber 80, and then the gate valve 86 is opened to transfer the substrate into the third processing chamber 91. Then, the gate valve 86 is closed.

[0273] Here, the third processing chamber 91 is a sputtering chamber using an RF magnetron sputtering method. -Let's say.

[0274] In the third processing chamber 91, a silicon oxide film (SiOx film) is formed as a second gate insulating layer. In addition to the silicon oxide film, an aluminum oxide film (AlO 3 film), magnesium oxide film (MgOx film), aluminum nitride film (AlNx film), oxide An yttrium film (YOx film) or the like can be used.

[0275] In order to reduce hydrogen in the gate insulating layer, the gate insulating layer was grown using a single crystal Si target. The hydrogen in the gate insulating layer is deposited by sputtering using argon gas and oxygen gas. The diffusion of oxygen into the IGZO film and reaction with the excess oxygen in the film to form the H2O component results in the I-type channel. This is extremely important in preventing water from entering the interface between the gate insulating layer and the IGZO film by successive deposition. It is also important to prevent the deposition of chemicals. Therefore, the inside of the chamber is evacuated with a cryopump or the like. Exhaust and reach a minimum pressure of 1 x 10 -7 ~1×10 -10 Torr (approx. 1×10 -5 Pa Top 1×10 -8 It is preferable to perform sputtering in an ultra-high vacuum region (up to 100 Pa), i.e., in the so-called UHV region. In addition, the gate insulating layer and the IGZO film are stacked continuously to prevent the interface from being exposed to the air. When this is done, the surface of the gate insulating layer is subjected to oxygen radical treatment to make the surface an oxygen excess region. In the subsequent heat treatment to improve reliability, the oxygen in the IGZO film interface is modified. It is effective in creating a source of supply for

[0276] In addition, by providing an oxygen excess region by performing oxygen radical treatment on the gate insulating layer, The oxygen concentration on the surface of the IGZO side is higher than the oxygen concentration inside the gate insulating layer. In addition, the oxygen radical treatment was performed more efficiently than the non-treatment. The oxygen concentration at the interface between the insulating layer and the IGZO film increases.

[0277] By performing oxygen radical treatment on the gate insulating layer, laminating the IGZO film, and then performing heat treatment, the IGZO The oxygen concentration on the gate insulating layer side of the O film is also high.

[0278] In addition, a small amount of halogen elements, such as fluorine or chlorine, is added to the gate insulating layer to form a naphthalene film. The mobile ions such as sodium may be immobilized in the chamber. Sputtering is performed by introducing a gas containing a halogen element. When introducing the gas, it is necessary to provide a detoxification device in the exhaust means of the chamber. The concentration of halogen elements contained in the was determined by analysis using a SIMS (secondary ion mass spectrometer). The concentration peak obtained is 1×10 15 cm -3 More than 1×10 20 cm -3 Within the following range It is preferable to do so.

[0279] After the SiOx film is formed, the gate valve 86 is opened without exposing the substrate to the air, and the transfer robot 8 1 to the transfer chamber 80, and then the gate valve 87 is opened to transfer the substrate into the fourth processing chamber 92. Then, the gate valve 87 is closed.

[0280] Here, the fourth processing chamber 92 is a sputtering chamber using a DC magnetron sputtering method. In the fourth treatment chamber 92, oxygen radical treatment is performed on the surface of the gate insulating layer, and As the source region and the drain region, an oxygen-excess oxide semiconductor layer (IGZO film) and An oxygen-deficient oxide semiconductor layer is formed as the oxygen-deficient region.

[0281] For oxygen radical treatment of the gate insulating layer surface, plasma treatment such as reverse sputtering can be performed. Reverse sputtering is a method of sputtering oxygen or oxygen and argon without applying a voltage to the target side. This method involves applying a voltage to the substrate in an atmosphere to form plasma on the substrate surface, thereby modifying the surface. The gate insulating layer may be subjected to a nitriding treatment, and may be subjected to a reverse sputtering treatment under a nitrogen atmosphere. This can be achieved by performing plasma treatment.

[0282] Using an oxide semiconductor target containing In, Ga, and Zn, The film can be formed in an oxygen atmosphere. Here, the IGZO film contains as much oxygen as possible. In order to achieve this, an oxide semiconductor containing In, Ga, and Zn was used as a target, and the amount of oxygen Pulse D under an atmosphere of 90% or more oxygen and 10% or less Ar The sputtering method is performed using the C sputtering method to form an oxygen-excess IGZO film.

[0283] In this way, the oxygen-rich SiOx film and the oxygen-rich IGZO film are formed without being exposed to the air. By forming the films successively, the interface between the films containing excess oxygen is stabilized, improving the reliability of the TFT. If the substrate is exposed to the air before the IGZO film is formed, moisture, etc. Adhesion can adversely affect the interface state, resulting in variations in threshold voltage, deterioration of electrical characteristics, and This can cause problems such as the TFT turning on. By continuously depositing the film without exposure to the air, hydrogen compounds exist at the interface. Therefore, by forming the films continuously, the variation in the threshold voltage can be reduced. In addition, it is possible to prevent deterioration of electrical characteristics, reduce the shift of the TFT to the normally-on side, and Or shifting can be eliminated.

[0284] The sputtering chamber of the third processing chamber 91 was equipped with an artificial quartz target and In, Ga, and Zn-containing oxide semiconductor targets were placed, and stacked in sequence using a shutter. It is also possible to perform lamination in the same chamber by successively depositing films using the shutter. The shutter is placed between the target and the substrate, and the target that is to be deposited is opened and the deposition is performed. The advantage of stacking in the same chamber is that This reduces the number of chambers used and reduces the amount of paper required to transport substrates between different chambers. The advantage is that it is possible to prevent tickles and the like from adhering to the substrate.

[0285] If the process does not use a gray-tone mask, the mask is transferred from the manufacturing equipment to the cassette room at this stage. The substrate is then removed and the IGZO film is etched using photolithography. However, if a gray-tone mask is used, the following continuous film formation is performed. conduct.

[0286] Subsequently, in the fourth processing chamber 92, the sputtering process is performed by pulse DC sputtering in an atmosphere of only rare gas. Then, a thin film of oxygen-deficient IGZO is formed on the thin film of oxygen-excess. The oxygen-deficient IGZO film has a lower oxygen concentration than the oxygen-rich IGZO film. The oxygen-deficient IGZO film functions as a source region or a drain region.

[0287] Next, the gate valve 87 is opened and the substrate is transferred into the fourth processing chamber 92 without being exposed to the atmosphere. , and close gate valve 87.

[0288] Next, the gate valve 87 is opened and the substrate is transferred by the transfer robot 81 without being exposed to the atmosphere. The wafer is transferred to the transfer chamber 80, the gate valve 88 is opened, the wafer is transferred to the fifth processing chamber 93, and the gate Close valve 88.

[0289] Here, the fifth processing chamber 93 is a sputtering chamber using a DC magnetron sputtering method. In the fifth treatment chamber 93, a metal multilayer film that will become a source electrode layer or a drain electrode layer is formed. A titanium target is placed in the sputtering chamber of the fifth processing chamber 93. Both the aluminum target and the aluminum target are installed, and the shutter is used to stack them one after another. In this example, aluminum is deposited on a titanium film. A titanium film is then laminated on the aluminum film.

[0290] In this way, when using a gray-tone mask, oxygen-rich Si By successively depositing an Ox film, an oxygen-rich IGZO film, an oxygen-deficient IGZO film, and a metal multilayer film, In particular, the interface state of the oxygen-rich IGZO film becomes more stable, improving the reliability of the TFT. If the substrate is exposed to the air before or after the IGZO film is formed, moisture may be present. This can adversely affect the interface condition, resulting in variations in threshold voltage, deterioration of electrical characteristics, and normal operation. This can cause problems such as the TFT becoming damaged. By continuously depositing the film without exposure to the air, hydrogen compounds are prevented from existing at the interface of the IGZO film. Therefore, by successively depositing four layers, the threshold The reduction of variation in the TFT, the prevention of deterioration of electrical characteristics, and the shift of the TFT to the normally-on side are achieved. The shift can be reduced, and preferably eliminated.

[0291] In addition, the oxygen-deficient IGZO film and the source and drain electrode layers are not exposed to the air. By continuously depositing the metal multilayer film, the oxygen-deficient IGZO film and the metal multilayer film are formed. A good interface state can be achieved with the film, and contact resistance can be reduced.

[0292] The sputtering chamber of the third processing chamber 91 was equipped with an artificial quartz target and In, Ga, and Zn-containing oxide semiconductor targets were installed and introduced sequentially using a shutter. By switching the gas used to deposit three layers in succession, the layers can be stacked in the same chamber. The advantage of stacking in the same chamber is that it reduces the number of chambers used. In addition, particles may adhere to the substrate while it is being transported between different chambers. The point is that this can be prevented.

[0293] The above steps are repeated to perform film formation on the substrates in the cassette case, and multiple substrates are processed. After completion, the vacuum in the cassette chamber is released to the atmosphere, and the substrates and cassette are removed.

[0294] In addition, in the first processing chamber 89, after the formation of the oxygen-excessive IGZO film and the oxygen-deficient IGZO film, Heat treatment, specifically, heat treatment at 200°C to 600°C, preferably 300°C to 500°C By carrying out this heat treatment, an inverted staggered thin-film transistor can be formed. This heat treatment improves the electrical properties of the IGZO film and There are no particular limitations as long as it is after the formation of an oxygen-deficient IGZO film. For example, This can be done immediately after the deposition of an oxygen-deficient IGZO film or immediately after the deposition of a metal multilayer film.

[0295] Next, each laminated film is etched using a gray-tone mask. Alternatively, the insulating layer may be formed by etching in multiple steps. Selective etching may also be performed.

[0296] The semiconductor layer, the source region, the drain region, the source electrode layer, and the drain electrode layer are etched. After the formation of the insulating film, vacuum baking may be performed before forming the protective film.

[0297] In addition, the semiconductor layer, the source region, the drain region, the source electrode layer, and the drain electrode layer are etched. After the formation of the protective film by the exposure process, oxygen radical treatment may be performed before the formation of the protective film. By performing oxygen radical treatment on the channel formation region of the semiconductor layer, The layer surface can be the oxygen excess region.

[0298] By making the surface of the semiconductor layer an oxygen-excess region, hydrogen is prevented from being mixed into the semiconductor layer. The back channel becomes an oxygen-deficient region, preventing conduction between the source and drain, and thus reducing the off-state current. In this way, the semiconductor layer in the back channel portion is also made into an oxygen excess region. Therefore, the back channel semiconductor can be treated with oxygen radicals in the same way as the gate insulating layer. It is effective to subject the conductor layer to oxygen radical treatment.

[0299] The subsequent steps are the same as those of the first to fourth embodiments described above. This makes it possible to fabricate thin film transistors of this type.

[0300] Here, we have taken the example of a multi-chamber manufacturing device, but if the sputtering chamber is Using in-line manufacturing equipment connected in series, continuous film formation is performed without exposure to the atmosphere. This is also fine.

[0301] The apparatus shown in FIG. 22 is a so-called face-down type in which the substrate is set with the surface on which the film is to be formed facing downward. However, the substrate may be placed vertically in the processing chamber. The advantage of this treatment chamber is that it has a smaller footprint than a face-down treatment chamber. Furthermore, this is effective when using a large-area substrate that may bend due to its own weight.

[0302] (Embodiment 7) The thin film transistor of the present invention is manufactured, and the thin film transistor is installed in a pixel portion and further in a driving circuit. A semiconductor device having a display function (also called a display device) can be manufactured using the above-mentioned organic EL display device. The thin film transistor of the present invention is integrated with a part or the whole of a driver circuit on the same substrate as a pixel portion. A system on panel can be formed.

[0303] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0304] The display device includes a panel in which a display element is sealed, and a controller for the panel. The display device according to the present invention further includes a module in which an IC or the like including the display device is mounted. In the manufacturing process, a display element substrate corresponds to a form before the display element is completed. The child substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, only the pixel electrodes of the display element may be formed, or the pixel electrodes may be formed. Even if the conductive film is formed after etching and before forming the pixel electrode, Good, and all forms apply.

[0305] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0306] In this embodiment, a liquid crystal display device is shown as an example of a semiconductor device according to one embodiment of the present invention.

[0307] 23(A) and (B) show an active matrix type liquid crystal display device to which the present invention is applied. FIG. 23A is a plan view of a liquid crystal display device, and FIG. 23B is a diagram showing the line in FIG. 1 is a cross-sectional view of a thin film transistor 201 used in the semiconductor device. The thin film transistor shown in FIG. 2 can be fabricated in the same manner as in FIG. 1, and the gate insulating film is treated with oxygen radicals. A highly reliable thin film transistor including an oxygen-rich oxide semiconductor layer and an oxygen-deficient oxide semiconductor layer on an insulating layer. Also, the thin film transistor shown in the first, third or fourth embodiment A transistor can also be applied as the thin film transistor 201 of this embodiment.

[0308] The liquid crystal display device of this embodiment shown in FIG. 23(A) includes a source wiring layer 202 and a multi-gate structure. The thin film transistor 201 includes a reverse staggered type, a gate wiring layer 203, and a capacitance wiring layer 204. .

[0309] In addition, in FIG. 23B, the liquid crystal display device of the present embodiment has a multi-gate structure. A transistor 201, an insulating layer 211, an insulating layer 212, an insulating layer 213, and a display element The substrate 2 is provided with an electrode layer 255, an insulating layer 261 that functions as an alignment film, and a polarizing plate 268. 00, an insulating layer 263 that functions as an alignment film, an electrode layer 265 used for a display element, A colored layer 264 functioning as a filter, a substrate 266 provided with a polarizing plate 267, and a liquid crystal layer 268 are arranged in the liquid crystal layer 268. 62 and has a liquid crystal display element 260.

[0310] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 262. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to 1 It is optically isotropic, so alignment processing is unnecessary and viewing angle dependency is small. .

[0311] Although FIG. 23 shows an example of a transmissive liquid crystal display device, one embodiment of the present invention is a reflective liquid crystal display device. The present invention can also be applied to semi-transmissive liquid crystal display devices.

[0312] In the liquid crystal display device of FIG. 23, a polarizing plate 267 is provided on the outer side (the viewing side) of the substrate 266. In the example shown, a colored layer 264 and an electrode layer 265 used for a display element are provided in this order on the inside. The plate 267 may be provided on the inside of the substrate 266. Also, the laminated structure of the polarizing plate and the colored layer may be the same as that shown in FIG. However, the present invention is not limited to these values, and may be appropriately set depending on the materials of the polarizing plate and the coloring layer and the manufacturing process conditions. In addition, a light-shielding film that functions as a black matrix may be provided.

[0313] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, In order to improve the reliability of the transistor, the thin film transistor obtained in the first embodiment is provided with a protective film or The insulating layer 211, the insulating layer 212, and the insulating layer 213 function as a planarizing insulating film. The protective film is made of a material that can withstand organic matter, metals, water vapor, and other substances suspended in the air. The purpose of the protective film is to prevent the intrusion of contaminating impurities, and a dense film is preferable. Using the above, silicon oxide film, silicon nitride film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, Aluminum nitride film, aluminum oxynitride film, or aluminum oxynitride film. In this embodiment mode, the protective film is formed by a sputtering method. However, there is no particular limitation and various methods may be used for forming the insulating layer.

[0314] An insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is a hiroma of an aluminum film. In this embodiment, the insulating layer 211 is a silicon oxide film formed by sputtering. Form.

[0315] In addition, an insulating layer 212 is formed as the second layer of the protective film. A silicon nitride film is formed by sputtering. When a silicon nitride film is used as one layer of the protective film, Mobile ions such as sodium can penetrate into the semiconductor region and change the electrical properties of the TFT. It is possible to suppress the above.

[0316] After forming the protective film, the IGZO semiconductor layer is annealed (300°C to 400°C). This is also possible.

[0317] In addition, an insulating layer 213 is formed as a planarizing insulating film. The insulating layer 213 is made of acrylic, Heat-resistant organic materials such as polyimide, benzocyclobutene, polyamide, and epoxy In addition to the above organic materials, low-k materials, silicon materials, etc. can be used. Use oxyxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. Siloxane resins can have hydrogen, fluorine, alkyl groups, or aryl groups as substituents. The insulating film formed of these materials may have at least one of the following groups: The insulating layer 213 may be formed by stacking a plurality of layers.

[0318] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. Siloxane-based resins contain hydrogen, fluorine, alkyl, and aryl groups as substituents. The alkyl group may have at least one of a cyclic group, a cyclic group, or an aromatic hydrocarbon.

[0319] The method for forming the insulating layer 213 is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. Spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 213 is formed using a material liquid, a baking In the process of forming the IGZO semiconductor layer, annealing (at 300° C. to 400° C.) may be performed at the same time. The annealing process for the IGZO semiconductor layer is also performed during the baking process for the insulating layer 213, so that the semiconductor It becomes possible to fabricate the device.

[0320] The electrode layers 255 and 265 functioning as pixel electrode layers are made of indium tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive material having such a property can be used.

[0321] The electrode layers 255 and 265 are made of a conductive material including a conductive polymer. The pixel electrode formed by using the conductive composition can be formed by the following steps: Sheet resistance is 10,000 Ω / □ or less, and light transmittance at a wavelength of 550 nm is 70% or more. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm. It is preferable that:

[0322] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0323] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0324] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0325] (Embodiment 8) In this embodiment mode, an example of electronic paper will be shown as a semiconductor device of the present invention.

[0326] FIG. 30 shows an active matrix type electronic paper as an example of a semiconductor device to which the present invention is applied. As a thin film transistor 581 used in the semiconductor device, The gate insulating layer is treated with oxygen radicals, and the oxygen radicals are deposited on the gate insulating layer. An excess oxide semiconductor layer, and an oxygen-deficient oxide semiconductor layer as a source region and a drain region The present invention is also directed to a highly reliable thin film transistor including the above-mentioned. The thin film transistor shown in the fourth embodiment is also applicable to the thin film transistor 581 of this embodiment. It is also possible.

[0327] The electronic paper in FIG. 30 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0328] The thin film transistor 581 is an inverted staggered type thin film transistor having a multi-gate structure. The first electrode layer 587 and the insulating layer 585 are formed as a source electrode layer or a drain electrode layer. The first electrode layer 587 and the second electrode layer 588 are in contact with each other at the opening and are electrically connected. The liquid-filled container has a black area 590a and a white area 590b in between. A spherical particle 589 including a bit 594 is provided, and the spherical particle 589 is surrounded by a resin or the like. It is filled with a filler material 595 (see FIG. 30).

[0329] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is the electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display, the image that was displayed can be retained. Therefore, a semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0330] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0331] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0332] (Embodiment 9) In this embodiment mode, an example of a light-emitting display device will be described as a semiconductor device of the present invention. As the display element, a light-emitting element utilizing electroluminescence is used here. Light-emitting elements that utilize electroluminescence are either made of organic compounds or Generally, the former are organic EL elements and the latter are inorganic EL elements. It is called an element.

[0333] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0334] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0335] 26(A) and 26(B) show an active matrix type semiconductor device as an example of the semiconductor device to which the present invention is applied. FIG. 26(A) is a plan view of the light-emitting display device, and FIG. 26(B) is a schematic view of the light-emitting display device. FIG. 27 is a cross-sectional view of the light-emitting display device shown in FIG. The equivalent circuit of the device is shown.

[0336] The thin film transistors 301 and 302 used in the semiconductor device are the same as those in the first embodiment and the second embodiment. The thin film transistor can be manufactured in the same manner as in the second embodiment, and the gate electrode is treated with oxygen radicals. An oxygen-excessive oxide semiconductor layer is formed on an insulating layer, and an oxygen-deficient oxide semiconductor layer is formed as a source region and a drain region. The thin film transistor includes an oxide semiconductor layer. The thin film transistors shown in the fourth embodiment are also used as the thin film transistors 301 and 302 of this embodiment. It can also be applied.

[0337] The light-emitting display device of this embodiment shown in FIG. 26(A) and FIG. 26(B) has a multi-gate structure. A thin film transistor 301, a light emitting element 303, a capacitor element 304, a source wiring layer 305, The thin film transistors 301 and 302 are n-channel It is a type thin film transistor.

[0338] In addition, in FIG. 26B, the light-emitting display device of this embodiment mode has a thin film transistor 302 , the insulating layer 311, the insulating layer 312, the insulating layer 313, the partition wall 321, and the light-emitting element 303. The light-emitting device has a first electrode layer 320 , an electroluminescent layer 322 , and a second electrode layer 323 .

[0339] The insulating layer 313 is made of an organic resin such as acrylic, polyimide, or polyamide, or siloxane. It is preferable to form the insulating film using the above method.

[0340] In this embodiment, since the thin film transistor 302 of the pixel is an n-type transistor, the first It is preferable to use a cathode as the first electrode layer 320. Materials with small functions, such as Ca, Al, MgAg, and AlLi, can be used.

[0341] The partition wall 321 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. A photosensitive material is used to form an opening on the first electrode layer 320, and the sidewall of the opening is continuous. It is preferable to form the inclined surface so as to have a continuous curvature.

[0342] The electroluminescent layer 322 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it's

[0343] A second electrode layer 323 using an anode is formed so as to cover the electroluminescent layer 322. The electrode layer 323 is made of a conductive material having light transmission properties as listed in the seventh embodiment for the pixel electrode layer. In addition to the above-mentioned transparent conductive film, a titanium nitride film or A titanium film may be used for the first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 32 3 are overlapped to form the light emitting element 303. The second electrode layer 323 and the partition wall 32 are provided to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the A protective film may be formed on the substrate 1. Examples of the protective film include a silicon nitride film, a silicon oxynitride film, and a DLC film. A film or the like can be formed.

[0344] Furthermore, in practice, once the process is completed up to Figure 26(B), the structure is made airtight to prevent it from being exposed to the outside air. Protective films with high heat resistance and low degassing (laminated films, UV curable resin films, etc.) It is preferable to package (enclose) the container in a container-type container or a cover material.

[0345] Next, the configuration of the light-emitting element will be described with reference to FIG. 28. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figures 28(A), (B), and (C). The driving TFTs used in the semiconductor device, TFTs 7001, 7011, and 7021, are The thin film transistor can be manufactured in the same manner as in the first embodiment, and the gate electrode is subjected to oxygen radical treatment. An oxygen-excessive oxide semiconductor layer is formed on an insulating layer, and an oxygen-deficient oxide semiconductor layer is formed as a source region and a drain region. The thin film transistor includes an oxide semiconductor layer and is highly reliable. The thin film transistors shown in the third embodiment or the fourth embodiment are TFTs 7001, 7011, and 70 It can also be applied as 21.

[0346] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There is a light-emitting element having a dual-side emission structure in which light is emitted from the side of the substrate. The present invention can be applied to any light emitting element with any emission structure.

[0347] A light emitting element having a top emission structure will be described with reference to FIG.

[0348] In FIG. 28A, a TFT 7001 which is a driving TFT is an n-type TFT, and a light emitting element 7002 emits light. FIG. 28(A) shows a cross-sectional view of a pixel when the light incident thereon exits to the anode 7005 side. A cathode 7003 of a light emitting element 7002 and a TFT 7001 which is a driving TFT are electrically connected. A light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. 7003 uses various materials as long as they have a small work function and are conductive films that reflect light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers may be laminated. When the cathode 7003 is composed of multiple layers, the electron injection layer 7004 is disposed on the cathode 7003. The layers are laminated in this order: electron transport layer, light emitting layer, hole transport layer, and hole injection layer. It is not necessary to provide all of the anodes. The anode 7005 is made of a conductive material that transmits light. For example, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, oxide A light-transmitting conductive film such as indium tin oxide doped with indium may be used.

[0349] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 28(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0350] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. When 011 is an n-type light emitting element and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, FIG. 28B shows a cross-sectional view of a pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. When the anode 15 has a light-transmitting property, a shielding layer for reflecting or blocking light is provided so as to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 014, like FIG. 28(A), may be composed of a single layer, but may also be composed of multiple layers stacked together. The anode 7015 does not need to transmit light, but as shown in FIG. As with 28(A), it can be formed using a conductive material having light-transmitting properties. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0351] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 28B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0352] Next, a light emitting element having a dual emission structure will be described with reference to FIG. In this example, a conductive film 7027 having a light-transmitting property and electrically connected to the driving TFT 7021 is formed on the substrate 7022. A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be configured as a single layer or as a laminate of multiple layers. 25 is formed using a conductive material having a light transmitting property, similar to FIG. It is possible.

[0353] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 28C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0354] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0355] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light-emitting element is electrically connected has been shown, the current between the driving TFT and the light-emitting element is A control TFT may be connected.

[0356] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0357] Through the above steps, a light-emitting display device having high reliability as a semiconductor device can be manufactured. .

[0358] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0359] (Embodiment 10) Next, a structure of a display panel, which is one embodiment of a semiconductor device of the present invention, will be described below. In the embodiment, a liquid crystal display panel, which is one type of liquid crystal display device having a liquid crystal element as a display element, is used. A liquid crystal panel is one form of a semiconductor device having a light-emitting element as a display element. A light-emitting display panel (also called a light-emitting panel) will be described below.

[0360] Next, the appearance and cross section of a light-emitting display panel, which is one embodiment of a semiconductor device of the present invention, will be described. The following description will be given with reference to FIG. 29. FIG. 29 shows a structure of a semiconductor device that has been subjected to oxygen radical processing on a first substrate. An oxygen-excess oxide semiconductor layer and a source region and a drain region are formed on the gate insulating layer. A highly reliable thin film transistor and a light emitting element including an oxygen-deficient oxide semiconductor layer are formed on a second substrate. FIG. 29(B) is a top view of the panel sealed with a sealant between the panel and the plate. This corresponds to the cross-sectional view taken along line HI in (A).

[0361] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed so as to surround the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. 4507. It is sealed together with the filler material 4507 by

[0362] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 29B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0363] The thin film transistors 4509 and 4510 are formed by forming an oxide film on a gate insulating layer that has been subjected to oxygen radical treatment. An oxygen-rich oxide semiconductor layer and an oxygen-deficient oxide semiconductor as a source region and a drain region. The present invention corresponds to a highly reliable thin film transistor including a layer, and is The thin film transistor described in Embodiment 3 or 4 can be used. In this embodiment, the thin film transistors 4509 and 4510 are n-channel thin film transistors. do.

[0364] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is not limited to that shown in this embodiment mode. The structure of the light emitting element 4511 is adjusted according to the direction of the light to be extracted from the light emitting element 4511. The composition can be changed as appropriate.

[0365] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0366] In this embodiment mode, the connection terminal 4515 is formed from the same conductive film as the second electrode layer 4512. The wiring 4516 is made of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. has been formed.

[0367] The connection terminal 4515 is connected to a terminal of the FPC 4518a via an anisotropic conductive film 4519. are electrically connected.

[0368] The second substrate is not transparent to light, and is located in the direction of light extraction from the light emitting element 4511. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0369] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler. The substance was used.

[0370] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0371] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0372] Next, the appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device of the present invention, will be described. The following description will be given with reference to FIG. 24. FIG. 24 shows an oxygen radical processing An oxygen-excess oxide semiconductor layer, a source region, and a drain region are formed on the gate insulating layer. Highly reliable thin film transistors 4010 and 401 each including an oxygen-deficient oxide semiconductor layer as a region The liquid crystal element 4013 is sealed between the first substrate 4006 and the second substrate 4006 by a sealant 4005. FIG. 24(B) is a top view of the panel in MN of FIG. 24(A1)(A2). This corresponds to a cross-sectional view in

[0373] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0374] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 24(A2) shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0375] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 24B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The following are given as examples:

[0376] The thin film transistors 4010 and 4011 are formed by forming an oxide film on the gate insulating layer that has been subjected to oxygen radical treatment. An oxygen-rich oxide semiconductor layer and an oxygen-deficient oxide semiconductor as a source region and a drain region. The present invention corresponds to a highly reliable thin film transistor including a layer, and is The thin film transistor described in Embodiment 3 or 4 can be used. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. do.

[0377] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0378] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, polyester film Alternatively, acrylic resin film can be used. Aluminum foil can also be used as a PVF film. A sheet having a structure sandwiched between films or polyester films can also be used.

[0379] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may also be used.

[0380] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0381] In this embodiment, the connection terminal 4015 is connected to the pixel electrode layer 4030 of the liquid crystal element 4013. The wiring 4016 is formed from the same conductive film as the thin film transistors 4010 and 4011. The gate electrode layer is formed from the same conductive film.

[0382] The connection terminal 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0383] In FIG. 24, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0384] FIG. 25 shows a liquid crystal display device as a semiconductor device using a TFT substrate 2600 produced by applying the present invention. 1 shows an example of a liquid crystal display module.

[0385] FIG. 25 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604, a colored layer 2605, and a polarizing plate 2606 are provided to form a display area. The color layer 2605 is necessary for color display. In the case of the RGB method, it is red, green, A colored layer corresponding to each color of blue and blue is provided for each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed on the outer side of the optical substrate 2601. The light source is composed of a cold cathode fluorescent lamp 2610 and a reflector 2611. The circuit board 2612 is , and is connected to a wiring circuit section 2608 of the TFT substrate 2600 via a flexible wiring substrate 2609. It also includes external circuits such as a control circuit and a power supply circuit. The liquid crystal layer may be laminated with a retardation plate interposed therebetween.

[0386] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment), ASM(Axially Symmetric aligned Mic) ro-cell) mode, OCB(Optical Compensated Bire) fringence mode, FLC (Ferroelectric Liquid C rystal) mode, AFLC (AntiFerroelectric Liquid Crystal) can be used.

[0387] Through the above steps, a highly reliable display panel can be manufactured as a semiconductor device.

[0388] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0389] (Embodiment 11) The semiconductor device of the present invention can be used as electronic paper. It can be used in any electronic device that displays information. For example, Electronic paper is used for electronic books, posters, and advertisements inside trains and other vehicles. The present invention can be applied to advertisements, displays on various cards such as credit cards, etc. An example is shown in FIG. 31 and FIG.

[0390] FIG. 31(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the advertisements are exchanged manually, but in the case of electronic matter to which the present invention is applied, By using paper, you can change the display of your advertisement in a short time. Also, the display will not collapse. The poster can also be used to transmit and receive information wirelessly. good.

[0391] FIG. 31(B) shows an advertisement 2632 on a train or other vehicle. In the case of paper printouts, the advertisements are exchanged manually, but in the case of electronic By using child paper, it is possible to change the display of advertisements in a short time without a lot of manpower. The display is stable and does not collapse. The poster transmits information wirelessly. It may be configured to be capable of transmitting and receiving.

[0392] FIG. 32 shows an example of an electronic book 2700. For example, the electronic book 2700 is The device is made up of two housings, a housing 2701 and a housing 2703. The body 2703 is integrated with a shaft portion 2711, and the opening and closing movement is performed around the shaft portion 2711. This configuration allows the device to operate like a paper book. It becomes.

[0393] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 32) and An image can be displayed on the display unit 2707 in FIG.

[0394] FIG. 32 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0395] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0396] (Embodiment 12) The semiconductor device according to the present invention can be applied to various electronic devices (including gaming machines). The electronic device may be, for example, a television device (television or television receiver) (also called "computer monitors"), digital cameras, digital video cameras, digital digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable games Examples of such devices include machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines.

[0397] FIG. 33(A) shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. This shows a configuration in which the above is supported.

[0398] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0399] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and also has wired or over-the-air reception via a modem. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0400] FIG. 33B shows an example of a digital photo frame 9700. The photo frame 9700 includes a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0401] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0402] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0403] FIG. 34(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 34(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least the present invention is It is sufficient that the device is provided with the semiconductor device, and other auxiliary equipment is provided as appropriate. The portable game machine shown in FIG. 34(A) can be used to play a game using a program recorded on a recording medium. It has the function of reading the program or data and displaying it on the display unit, and wirelessly communicating with other portable gaming machines. The portable gaming machine shown in FIG. 34(A) has the following functions: The function is not limited to this and may have various functions.

[0404] FIG. 34(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. The Machine 9900 also includes other operating means such as a start lever and stop switch, coin The slot machine 9900 is equipped with a slot slot, a speaker, etc. However, the present invention is not limited to the above, and may be configured to include at least the semiconductor device according to the present invention. Other auxiliary equipment may be provided as appropriate.

[0405] FIG. 35 shows an example of a mobile phone 1000. The mobile phone 1000 has a housing 100 In addition to the display unit 1002 incorporated in the device 1, the device 1002 also includes an operation button 1003, an external connection port 1004, It is equipped with a speaker 1005, a microphone 1006, etc.

[0406] The mobile phone 1000 shown in FIG. 35 allows users to input information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or typing an e-mail can be performed by the display unit 100. This can be done by touching 2 with a finger or other object.

[0407] The screen of the display unit 1002 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0408] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0409] In addition, a sensor for detecting tilt, such as a gyro or an acceleration sensor, is installed inside the mobile phone 1000. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0410] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0411] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0412] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0413] (Embodiment 13) In this embodiment, a channel protection type thin film transistor is used in the thin film transistor of the present invention. Therefore, the other steps can be performed in the same manner as in the first or second embodiment. The same parts as those in the first or second embodiment or parts having similar functions and steps The explanation will be omitted.

[0414] In this embodiment, a thin film transistor 175 used in a semiconductor device will be described with reference to FIG. I will use this to explain.

[0415] As shown in FIG. 36, a gate electrode layer 101, a gate insulating layer 102, a semiconductor a dielectric layer 103, a channel protection layer 108, a source region or a drain region 104a, 104b, A thin film transistor 175 including source and drain electrode layers 105a and 105b is provided. It is being done.

[0416] The thin film transistor 175 of this embodiment has a channel region on the channel formation region of the semiconductor layer 103. A protective layer 108 is provided. The semiconductor layer 103 is formed by the channel protective layer 108. The channel protection layer 108 is also not etched because it functions as a gate insulating layer 104. The insulating layer 102 and the semiconductor layer 103 may be successively formed without being exposed to the air. Productivity is improved if the thin films to be laminated are formed successively without exposure to the atmosphere.

[0417] The channel protection layer 108 is made of an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, silicon nitride, etc.). Silicon dioxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide The deposition method can be a sputtering method. .

[0418] The semiconductor layer 103 is an oxygen-excess oxide semiconductor layer containing In, Ga, and Zn. The drain regions 104a, 104b are made of oxygen-deficient oxide containing In, Ga, and Zn. It is a semiconductor layer.

[0419] The gate insulating layer having an oxygen-excess region and the oxygen-excess oxide semiconductor layer are compatible with each other and have a good interface. characteristics can be obtained.

[0420] After the gate insulating layer 102 is formed, the surface of the gate insulating layer is subjected to oxygen radical treatment to form an oxygen excess region. The gate insulating layer 102 and the semiconductor layer 103 are formed in succession.

[0421] The oxygen-deficient oxide semiconductor layers of the source and drain regions 104a and 104b are 1 nm or thicker than the It has crystal grains with a size of 10 nm or less and has a higher carrier concentration than the semiconductor layer 103.

[0422] In this embodiment, a gate electrode layer, a gate insulating layer, a semiconductor layer (oxygen-excess oxide semiconductor layer), , source region and drain region (oxygen-deficient oxide semiconductor layer), source electrode layer and drain A thin-film transistor having a laminated structure of an electrode layer and a crystal grain in an oxygen-deficient oxide semiconductor layer is formed. By using high carrier concentration source and drain regions having It is possible to suppress parasitic capacitance while keeping the film thickness of the layer thin. Since the ratio of the insulating layer to the insulating film is sufficient, the parasitic capacitance is sufficiently suppressed.

[0423] According to the present embodiment, a thin-film transistor having a small photocurrent, a small parasitic capacitance, and a high on-off ratio is obtained. Thus, a thin film transistor having good dynamic characteristics can be obtained. As a result, it is possible to provide a semiconductor device having a thin film transistor with excellent electrical characteristics and high reliability. can.

[0424] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

Claims

1. a circuit having first to sixth transistors; A pixel electrode; a seventh transistor electrically connected to the pixel electrode; one of a source and a drain of each of the first to fifth transistors is electrically connected to a first wiring; a gate of the first transistor is electrically connected to the other of the source and the drain of the fourth transistor and the other of the source and the drain of the fifth transistor; the other of the source and the drain of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor; a gate of the fifth transistor is electrically connected to a gate of the third transistor; a gate of the second transistor and a gate of the sixth transistor are electrically connected to a second wiring; At least one of the first to sixth transistors and each of the seventh transistor are A gate electrode; a gate insulating film on the gate electrode; an oxide layer containing In, Ga, and Zn provided on the gate insulating film; a conductive layer provided over the oxide layer and functioning as one of a source electrode and a drain electrode; the oxide layer has a laminated structure including a first oxide layer on the gate insulating film and a second oxide layer on the first oxide layer; the conductive layer has a laminated structure including a first conductive layer on the second oxide layer, a second conductive layer on the first conductive layer, and a third conductive layer on the second conductive layer; the oxide layer has a first region in contact with the first conductive layer and a second region in contact with a first insulating layer; When viewed in a cross section in a channel length direction, the first conductive layer has a third region that does not overlap with the second conductive layer and the third conductive layer and is in contact with the first insulating layer, a fourth region that does not overlap with the third conductive layer and is in contact with the second conductive layer, a fifth region that overlaps with the third conductive layer and is in contact with the second conductive layer, a sixth region that does not overlap with the third conductive layer and is in contact with the second conductive layer, and a seventh region that does not overlap with the second conductive layer and the third conductive layer and is in contact with the first insulating layer, In the cross-sectional view, both ends of each of the second oxide layer and the conductive layer overlap an upper surface of the gate electrode; In the cross-sectional view, the oxide layer does not have a region in contact with the second conductive layer, a second insulating layer having an organic material on the first insulating layer; the pixel electrode is provided on the second insulating layer and is electrically connected to the conductive layer of the seventh transistor.

2. In claim 1, The oxide layer has crystal grains with a size of 1 nm or more and 10 nm or less.

3. In claim 1 or 2, A display device, wherein a thickness of the oxide layer in the second region is smaller than a thickness of the oxide layer in the first region.

Images