Silicon carbide semiconductor device and manufacturing method thereof

Abstract

To provide a silicon carbide semiconductor device and a manufacturing method thereof, capable of suppressing the progress of chipping and the occurrence of cracks originating from chipping.SOLUTION: A trench 12 is formed in a dicing area, and a chipping suppression layer is formed so as to embed the trench 12, the chipping suppression layer comprising a Poly-Si film 13 serving as a dissimilar material to SiC. Thus, even if chipping is formed when dicing is performed along a dicing line with a dicing blade 20, the formation of chipping is allowed only in the chipping suppression layer. Accordingly, even if chipping occurs, the progress of the chipping stops at an interface between the pitching suppression layer and SiC, so that chipping cannot progress into SiC.SELECTED DRAWING: Figure 2E

Description

[Technical field]

[0001] The present invention relates to a silicon carbide (hereinafter referred to as SiC) semiconductor device that is divided into chip units by dicing, and to a method for manufacturing the same. [Background technology]

[0002] In a dicing device, a semiconductor wafer on which devices have been formed is attached onto a dicing tape, and then the wafer is physically cut into chips by dicing using a circular dicing blade made of diamond.

[0003] At this time, the physical cutting by the dicing blade causes random chipping at the cutting points, so it is necessary to secure a dicing area taking into account the chipping distance.As a result, the chip size increases and the number of chips that can be taken out of the semiconductor wafer ultimately decreases.

[0004] Furthermore, when the semiconductor chip is used, in other words when it is subjected to an environmental load due to thermal cycles, cracks may occur starting from chipping that occurs during dicing, leading to destruction of the semiconductor chip.

[0005] Therefore, a semiconductor device capable of suppressing the progress of chipping during dicing has been proposed in Patent Document 1. In this semiconductor device, a modified layer with a collapsed crystal structure is formed by performing plasma irradiation, ion implantation, or laser irradiation in an area near a semiconductor element, and the modified layer suppresses the progress of chipping. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2008-147412 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, in order to form the modified layer, plasma irradiation, ion implantation or laser irradiation is required, and when SiC is used as the semiconductor material, it is difficult to form the modified layer by these methods.

[0008] In view of the above, an object of the present invention is to provide a SiC semiconductor device capable of suppressing the progression of chipping and the occurrence of cracks originating from chipping, and a manufacturing method thereof. [Means for solving the problem]

[0009] In order to achieve the above object, the present invention provides a SiC semiconductor device having a semiconductor element formed thereon and formed into a chip, the SiC semiconductor device comprising: Do The chip is surrounded by a trench (12) formed in the corner of the chip end surface, and a chipping suppression layer (13) made of SiC and a different material is provided. The dot line pattern is a staggered pattern in which a plurality of dot lines are arranged side by side. .

[0010] With this structure, even if chipping occurs during dicing into chips, its progression is stopped and suppressed at the interface between the chipping suppression layer and SiC. This makes it possible to suppress the progression of chipping. Furthermore, even when the chip is used, in other words when it is subjected to environmental loads due to thermal cycles, it is possible to suppress the occurrence of cracks originating from chipping.

[0011] The invention described in claim 3 is a method for manufacturing a SiC semiconductor device in which a semiconductor wafer (10) on which semiconductor elements are formed is diced into chips in a dicing region with a dicing blade (20), the method including the steps of: preparing a semiconductor wafer; arranging a resist (11) on a surface of the semiconductor wafer; patterning the resist to form a photopattern with openings at predetermined positions; and forming a trench (12) in the dicing region, the width of which is a dimension perpendicular to the dicing line, in the dicing region by performing dry etching on the photopattern, the width of the dicing blade being equal to or greater than the sum of the finishing accuracy of the dicing blade and the dicing position accuracy when dicing is performed; filling the trench with a chipping suppression layer (13) made of SiC and a different material; and dividing the semiconductor wafer into chip units by cutting the semiconductor wafer from the chipping suppression layer side using the dicing blade. In the method of forming the trench and the chipping suppression layer, the trench and the chipping suppression layer are arranged in a staggered pattern. .

[0012] According to this manufacturing method, even if chipping occurs during dicing into chips, its progress is stopped and suppressed at the interface between the chipping suppression layer and SiC. Therefore, it is possible to suppress the progress of chipping. Furthermore, even when the chip is used, in other words, when an environmental load is applied due to a thermal cycle, it is possible to suppress the occurrence of cracks originating from chipping.

[0013] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0014] [Figure 1] 4 is a flowchart showing steps relating to dicing in the method for manufacturing a SiC semiconductor device according to the first embodiment of the present invention. [Figure 2A] 1A to 1C are cross-sectional views showing a state of a SiC semiconductor device during a manufacturing process. [Figure 2B] 2B is a cross-sectional view showing a state of the SiC semiconductor device during the manufacturing process subsequent to FIG. 2A. [Figure 2C] 2C is a cross-sectional view showing a state of the SiC semiconductor device during the manufacturing process subsequent to FIG. 2B. [Figure 2D] 2D is a cross-sectional view showing a state of the SiC semiconductor device during the manufacturing process subsequent to FIG. 2C. [Figure 2E] 2D; FIG. 3 is a cross-sectional view showing a state of the SiC semiconductor device during the manufacturing process, subsequent to FIG. 2D; [Figure 3A] FIG. 13 is a diagram showing the relationship between the width of a dicing blade and the width of a trench in a dicing region. [Figure 3B] FIG. 13 is a diagram illustrating the depth of a trench in a dicing region. [Figure 4] FIG. 13 is a diagram showing an image obtained when the depth of chipping was actually measured. [Figure 5A] 13 is a diagram showing an example of a layout of a trench and a chipping suppression layer described in another embodiment. FIG. [Figure 5B] 13 is a diagram showing an example of a layout of a trench and a chipping suppression layer described in another embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) A SiC semiconductor device and its manufacturing method according to the first embodiment will be described. When manufacturing a SiC semiconductor device, a semiconductor wafer made of SiC is subjected to a device manufacturing process, and then the wafer is divided into chips using a dicing blade. However, the part of the device manufacturing process related to the formation of semiconductor elements is the same as the conventional process, so the description of the part of the device manufacturing process that is the same as the conventional process will be omitted, and the part related to dicing will be mainly described.

[0017] First, a semiconductor wafer using SiC as a semiconductor material is prepared, and then various device manufacturing processes are performed on the semiconductor wafer. Then, as one step of the device manufacturing process, preferably as a common step with the steps originally performed as the device manufacturing process, a step related to dicing is performed.

[0018] Specifically, as steps relating to dicing, each step is carried out according to the flowchart shown in Fig. 1. Figs. 2A to 2D are cross-sectional views corresponding to each step according to the flowchart shown in Fig. 1.

[0019] First, a trench photo process, a trench dry etching process, and a resist removal process are performed. FIG. 2A shows the state in which these processes are performed. In the trench photo process, a resist 11 is placed on the surface of a semiconductor wafer 10. Then, the resist 11 is patterned by performing exposure and development, etc., to form a photo pattern with an opening at a desired position. In the trench dry etching process, a trench 12 is formed in the semiconductor wafer 10 by performing dry etching from above the photo pattern made of the resist 11. At this time, the trench 12 is formed in the dicing region, and is formed in a frame shape along the dicing line. Then, as shown in FIG. 3A, the width of the trench 12, which is the dimension in the vertical direction to the dicing line, is set to the width of the dicing blade + 15.0 μm or more, and as shown in FIG. 3B, the depth of the trench 12 is set to 5.0 μm or less. The reason for setting such dimensions will be described later.

[0020] Next, after removing the resist 11, a Poly-Si (polysilicon) film formation process is performed. Fig. 2B shows the state after this process is performed. By performing this process, the inside of the trench 12 is filled with a Poly-Si film 13.

[0021] Furthermore, a Poly-Si etch-back process is performed. FIG. 2C shows the state after this process is performed. By the etch-back, the Poly-Si film 13 is left only in the trench 12. The portion of the Poly-Si film 13 formed outside the trench 12 is removed, and the surface of the semiconductor wafer 10 is exposed outside the trench 12. In this way, a structure is formed in which the Poly-Si film 13 is formed along the dicing line. The Poly-Si film 13 formed inside the trench 12 becomes a chipping suppression layer formed as a different material to the SiC.

[0022] The above steps are performed as a chipping suppression layer forming step among the steps related to dicing. These steps may be performed as one of the steps of forming various semiconductor elements on the semiconductor wafer 10 in the device manufacturing process, or may be performed as a separate step from the step of forming the semiconductor elements.

[0023] For example, when forming a MOSFET or IGBT with a trench gate structure as a semiconductor element, there are a gate trench forming process and a poly-Si gate forming process when forming the trench gate structure. Therefore, if the steps shown in Figures 2A to 2C are performed as common steps with the gate trench forming process and the poly-Si gate forming process of the MOSFET or IGBT, the chipping suppression layer forming process can be performed without increasing the number of manufacturing steps.

[0024] In addition, the poly-Si film is not limited to that included in a semiconductor element such as a MOSFET or an IGBT that is fabricated in the semiconductor wafer 10, but may also be formed on the surface of the semiconductor wafer 10 via an insulating film or the like. For example, a PN diode formed as a temperature sensor and a bidirectional Zener diode formed as a protection element for a peripheral breakdown voltage structure may be mentioned. In these cases, a diode structure is formed by ion-implanting p-type impurities or n-type impurities after forming a poly-Si film. Therefore, if the poly-Si film formation process shown in FIG. 2B is performed as a common process with the poly-Si film formation process for forming the diode structure, the chipping suppression layer formation process can be performed while suppressing an increase in the number of manufacturing processes.

[0025] In addition, there is a case where a mesa structure is formed in which a cell region in which the semiconductor element is formed is protruded from the peripheral region by forming a trench in the semiconductor wafer 10. Since the trench forming step is also performed in this case, if the trench 12 forming step shown in Fig. 2A described above is performed as a common step with the trench forming step for forming the mesa structure, the chipping suppression layer forming step can be performed while suppressing an increase in the number of manufacturing steps.

[0026] Furthermore, when forming a semiconductor element, a trench for alignment may be formed and alignment may be performed based on the position where the trench is formed. Since a trench forming process is also performed in this case, if the trench 12 forming process shown in FIG. 2A is performed as a common process with the alignment trench forming process, the chipping suppression layer forming process can be performed while suppressing an increase in the manufacturing process. However, if the alignment trench forming process is performed as an early stage process in the device manufacturing process, the trench will be filled with other films in the subsequent epitaxial growth process. Therefore, when forming the trench 12, the forming dimensions of the trench 12 are determined taking into account the reduction in width and depth due to filling with other films, and the chipping suppression layer is finally filled with the above-mentioned dimensions.

[0027] It is also possible to combine forming the trench 12 in the trench formation process for forming the mesa structure with forming the Poly-Si film 13 in the PN diode formation process using the Poly-Si film. It is also possible to combine forming the trench 12 in the alignment trench formation process with forming the Poly-Si film 13 in the PN diode formation process using the Poly-Si film. In this way, it is possible to perform the chipping suppression layer formation process while further suppressing an increase in the manufacturing process.

[0028] In this manner, various semiconductor element forming processes, including the chipping suppression layer forming process, are performed on the semiconductor wafer 10 as part of the device manufacturing process. After these processes are performed, various processes for forming structures above the surface of the semiconductor wafer 10, such as a wiring forming process and a protective film forming process, are then performed. Fig. 2D shows the state after these processes have been performed, and shows the surface electrode 14, EQR (Equivalent Potential Ring) structure 15, and protective film 16 as examples of structures formed through the wiring forming process and protective film forming process.

[0029] The surface electrode 14 is an electrode electrically connected to the semiconductor element formed on the semiconductor wafer 10, and is configured with a laminated structure of an aluminum (Al) layer 14a and a nickel (Ni) layer 14b. For example, when a MOSFET is formed as the semiconductor element, the source electrode becomes the surface electrode 14. The EQR structure 15 is configured as a part of the peripheral breakdown voltage structure, and is formed, for example, at a position corresponding to the outermost periphery of a guard ring formed in the semiconductor wafer, and is configured with an Al layer or the like. The protective film 16 is formed to cover the EQR structure 15 and to cover the semiconductor element other than the surface electrode 14 and other pad parts, and is configured with, for example, a polyimide film. By performing such wiring formation process and protective film formation process, the device manufacturing process is completed.

[0030] After that, in the dicing process, as shown in Fig. 2E, the semiconductor wafer 10 on which the semiconductor elements are formed is diced and divided into chip units using a dicing blade 20. Specifically, the semiconductor wafer 10 is cut from the side of the Poly-Si film 13 that serves as a chipping suppression layer using the dicing blade 20. This completes the production of chipped SiC semiconductor devices.

[0031] At this time, since a chipping suppression layer formed by embedding the Poly-Si film 13 in the trench 12 along the dicing line is provided, even if chipping 21 occurs, it can be prevented from progressing within the chipping suppression layer. More specifically, since the chipping suppression layer is formed of a material different from SiC, even if chipping 21 occurs, its progress can be stopped at the interface between the chipping suppression layer and SiC, and it can be prevented from progressing into the SiC.

[0032] Furthermore, in the chipped SiC semiconductor device, a chipping suppression layer made of the Poly-Si film 13 remains at the corners of the chip end face so as to surround the outer edge of the chip in a line. Also, chipping 21 may remain inside the chipping suppression layer. However, even if chipping 21 exists, it is inside the chipping suppression layer, so that it is possible to suppress the occurrence of cracks originating from chipping 21 when the chip is used, in other words, when an environmental load is applied due to a thermal cycle.

[0033] Here, the reason why the dimensions of the width and depth of the trench 12 are as described above will be explained. As described above, the width of the trench 12 is set to +15.0 μm or more with respect to the width of the dicing blade 20. The dicing blade 20 is manufactured with a target width of a predetermined width, for example, 60 μm, but the finishing accuracy is within a range of ±10 μm with respect to the target width, and even if it is manufactured with a target width of 60 μm, the actual width varies from 50 to 70 μm. In addition, the dicing position accuracy, that is, the deviation of the formation position of the trench 12 caused by the alignment deviation of the photomask and the deviation based on the mechanical position accuracy when dicing by the dicing blade 20 is up to 5.0 μm. In consideration of these, the finishing accuracy and dicing position accuracy of the dicing blade 20 are added to the width of the dicing blade 20, and the width of the trench 12 is set to +15.0 μm or more. In this way, dicing by the dicing blade 20 can be performed accurately within the formation range of the Poly-Si film 13.

[0034] In addition, the depth of the trench 12 is set to 5.0 μm or less. When the semiconductor wafer 10 on which chipping occurred was examined, the depth of the chipping was 5.0 μm or less, as shown in FIG. 4. Therefore, if the trench 12 has a maximum depth of 5.0 μm, the chipping can be kept inside. Therefore, by setting the depth of the trench 12 according to the chipping, the chipping can be prevented from protruding outside the trench 12. As for the depth of the trench 12, there is no problem if it is equal to or greater than the depth of the chipping, but if it is too deep, it takes time to form the trench 12, so it is preferable that the depth is the minimum required. Therefore, the trench 12 is formed to a depth that is deeper than the maximum depth of chipping that can occur and is equal to or less than 5.0 μm.

[0035] As described above, in this embodiment, the trench 12 is formed in the dicing region, and the chipping suppression layer made of the Poly-Si film 13, which is a different material from SiC, is formed by filling the trench 12. Therefore, even if chipping occurs when dicing is performed along the dicing line with the dicing blade 20, the chipping can be formed in the chipping suppression layer. Therefore, even if chipping occurs, its progress stops at the interface between the chipping suppression layer and SiC, and it can be prevented from progressing into the SiC.

[0036] Furthermore, even if the depth of the trench 12 is 5.0 μm or less, chipping can be prevented from occurring within the chipping suppression layer. Therefore, if the depth of the trench 12 is 5.0 μm, it is not necessary to form the trench 12 deeper than necessary.

[0037] Since chipping can be suppressed in this way, it becomes unnecessary to secure an excessive dicing area, and it is possible to suppress the increase in chip size. Furthermore, even when the chip is used, in other words when it is subjected to an environmental load due to a thermal cycle, it is possible to suppress the occurrence of cracks originating from chipping.

[0038] Furthermore, if the process of forming the trench 12 for forming the chipping suppression layer and the process of forming the Poly-Si film 13 are performed as common processes with the processes originally performed as the device manufacturing process, it is possible to suppress an increase in the number of manufacturing processes. For example, a semiconductor element having a trench gate structure is formed, and the process of forming the trench 12 and the process of forming the gate trench when constructing the trench gate structure are formed as a common process. Also, the process of forming the chipping suppression layer and the process of forming the Poly-Si gate are formed as a common process. In this way, an increase in the number of manufacturing processes can be suppressed.

[0039] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0040] For example, in the above embodiment, the chipping suppression layer is formed of the Poly-Si film 13, but the chipping suppression layer may be formed of other materials as long as they are different materials from SiC. For example, the chipping suppression layer may be formed of a silicon oxide (SiO2) film, a silicon nitride (SiN) film, a metal film, a metal silicide film, or the like.

[0041] In the case of a silicon oxide film, the chipping suppression layer can be formed using an interlayer insulating film formed on the surface of the semiconductor wafer 10 after the semiconductor element is formed. In the case of a silicon nitride film or a metal film, these films can be formed after the trench 12 is formed, and then etched back to leave the chipping suppression layer. In a SiC semiconductor device, an Al film or the like that constitutes the surface electrode is formed, so that it is possible to standardize the manufacturing process by using it as a metal film, and it is possible to suppress an increase in the manufacturing process. In addition, in a SiC semiconductor device, a metal silicide film such as a Ni silicide film is formed so that the surface electrode and SiC can be in ohmic contact. This metal silicide film can also be used as a chipping suppression layer. For example, in the case of a Ni silicide film, a Ni layer can be formed on the SiC surface including the inside of the trench 12, and then patterned to leave the Ni layer in the trench 12 or at a desired position, and then annealed to cause a silicidation reaction.

[0042] Furthermore, if the process of forming the trench 12 and the process of forming the chipping suppression layer are made common to one of the steps in the existing device manufacturing process, the increase in the number of manufacturing steps can be suppressed, but it is not necessary to make them common, and they may be performed as independent steps.

[0043] In the above embodiment, the trench 12 and the chipping suppression layer are formed over the entire dicing region, but may have other shapes. For example, the trench 12 and the chipping suppression layer may be formed in a stripe shape consisting of a plurality of lines extending along the dicing line as shown in FIG. 5A. The trench 12 and the chipping suppression layer may be formed in a staggered shape by arranging a plurality of dot lines as shown in FIG. 5B. That is, even if chipping occurs, it is sufficient that it remains within the dicing region, so the trench 12 and the chipping suppression layer may be formed in a plurality of stripes or a staggered shape. If the trench 12 and the chipping suppression layer are formed in a stripe shape, even if chipping occurs in the chipping suppression layer, the progress of chipping can be stopped by a line somewhere. If the trench 12 and the chipping suppression layer are formed in a staggered shape, the portions that are not the chipping suppression layer are not connected in a straight line, so the progress of chipping can be stopped by a dot somewhere.

[0044] In the case of these multiple line or staggered check patterns, the width of the chipping suppression layer, i.e., the distance between the outermost lines, may be at least ±15 μm as the width of dicing blade 20, and the depth may be 5.0 μm or less. Also, the chipped SiC semiconductor device has a structure in which the chipping suppression layer made of Poly-Si film 13 remains in trench 12 at the corners of the chip end face so as to surround the outer edge of the chip in lines or dotted lines. [Explanation of symbols]

[0045] 10. Semiconductor Wafers 11 Resist 12. Trench 13 Poly-Si membrane 14 Surface electrode 15 EQR structure 16 Protective film 20 Dicing Blade 21 Chipping

Claims

1. A silicon carbide semiconductor device in which a semiconductor element is formed and made into a chip, The chip includes a chipping suppression layer (13) made of silicon carbide and a different material, the chip being arranged in a trench (12) that surrounds the outer edge of the chip in a dotted line shape and is formed at the corner of the chip end face; In the silicon carbide semiconductor device, the dot line pattern is a staggered pattern formed by arranging a plurality of dot lines side by side.

2. The silicon carbide semiconductor device according to claim 1 , wherein the trench has a depth of not more than 5.0 μm.

3. A method for manufacturing a silicon carbide semiconductor device, comprising: dicing a semiconductor wafer (10) on which semiconductor elements are formed into chips in a dicing region with a dicing blade (20), providing the semiconductor wafer and disposing a resist (11) on a surface of the semiconductor wafer; patterning the resist to form a photopattern having openings at predetermined positions; By performing dry etching from above the photopattern, a trench (12) is formed in the dicing region, the width of which is a dimension perpendicular to the dicing line is equal to or greater than the width of the dicing blade plus the finishing accuracy of the dicing blade and the dicing position accuracy when performing the dicing; Filling the trench with a chipping suppression layer (13) made of silicon carbide and a different material; and dividing the semiconductor wafer into chip units by cutting the semiconductor wafer from the chipping suppression layer side using the dicing blade. The method for manufacturing a silicon carbide semiconductor device, wherein forming the trench and forming the chipping suppression layer causes the trench and the chipping suppression layer to have a staggered pattern.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 3 , wherein said trench is formed to a depth of said trench of 5.0 μm or less.

5. forming the trench in common with forming a trench in a device manufacturing process for forming the semiconductor element; 5. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the chipping suppression layer is formed by depositing the different material in the device manufacturing process, the different material being also deposited in the trench in which the chipping suppression layer is embedded.

6. The semiconductor device has a trench gate structure, The formation of the trench is performed simultaneously with the formation of a gate trench when constructing the trench gate structure; 5. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the chipping suppression layer is formed by performing formation of the chipping suppression layer in common with formation of a polysilicon gate formed in the gate trench, so that the chipping suppression layer is constituted by a polysilicon film.

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