Integrated circuit device, device and manufacturing method

Abstract

To provide an integrated circuit device that can achieve appropriate lead-out wiring electrically connecting a pad and a circuit to each other, while arranging the circuit to be overlapped on the pad to achieve a reduction in the area.SOLUTION: An integrated circuit device 20 includes a pad 2 that has a shape having a longitudinal direction and short direction; a circuit 8 that overlaps the pad 2 in plan view and is electrically connected with the pad 2; lead-out wiring 5 that is led out from a longitudinal outer edge EDL of the pad 2 along the short direction DS of the pad 2; and a via group 6 that electrically connect the lead-out wiring 5 and wiring 7 of the circuit 8 to each other and do not overlap the pad 2 in plan view.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an integrated circuit apparatus, a device, a manufacturing method, and the like. [Background technology]

[0002] Pads for external connection are provided in integrated circuit devices. For example, Patent Document 1 discloses a method of forming pads provided along the side edges of an integrated circuit device into a rectangular shape with long sides aligned with the vibration direction of ultrasonic waves during wire bonding. Patent Document 1 provides a pad shape that corresponds to the connection part of wire bonding, which has a substantially elliptical shape that is long in the vibration direction of ultrasonic waves in a plan view, thereby realizing a miniaturization of the integrated circuit device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 6-333974 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a configuration such as that of Patent Document 1, when a circuit is arranged so as to overlap a pad in a plan view, a method for appropriately drawing out wiring to the circuit has not been proposed. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to an integrated circuit device that includes a pad having a shape having a longitudinal direction and a lateral direction, a circuit that overlaps the pad in a planar view and is electrically connected to the pad, lead-out wiring that is drawn out from the outer edge of the longitudinal side of the pad along the lateral direction of the pad, and a group of vias that electrically connect the lead-out wiring to the wiring of the circuit and do not overlap the pad in the planar view.

[0006] Another aspect of the present disclosure relates to a manufacturing method for a device including an integrated circuit device and a package in which the integrated circuit device is housed, the method including: a manufacturing process for the integrated circuit device; and an assembly process for mounting the integrated circuit device in the package, the manufacturing process forming, on an active surface of the integrated circuit device: a pad having a shape having a longitudinal direction and a lateral direction; a circuit that overlaps the pad in a planar view and is electrically connected to the pad; lead-out wiring that is drawn out from an outer edge of the longitudinal side of the pad along the lateral direction of the pad; and a group of vias that electrically connect the lead-out wiring and the wiring of the circuit and do not overlap the pad in the planar view; and the assembly process forming bumps on the pads of the integrated circuit device, positioning the integrated circuit device such that the active surface faces a surface of the package, and connecting a terminal provided on a surface of the package to the bumps formed on the pads by ultrasonic bonding with the longitudinal direction of the pad as a vibration direction. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a cross-sectional view of a pad region of the integrated circuit device according to the embodiment. [Diagram 2] FIG. 2 is a plan view of a pad region of the integrated circuit device according to the embodiment. [Diagram 3] An example of input pad layout. [Figure 4] An example of output pad layout. [Diagram 5] An example of ground pad layout. [Figure 6] An example of layout arrangement when routing multiple lead wires from a pad. [Figure 7] FIG. 4 is an explanatory diagram of a bump formed on a pad. [Figure 8] FIG. 1 is an explanatory diagram of problems that may occur in ultrasonic bonding. [Figure 9] 4A to 4C are diagrams showing examples of pad structures. [Figure 10] 2 shows an example of the configuration of an integrated circuit device according to the present embodiment. [Figure 11] 2 shows an example of the configuration of a reference voltage generation circuit. [Figure 12] 13 shows another example of the configuration of the reference voltage generating circuit. [Figure 13] 1 shows an example of a layout arrangement of an integrated circuit device. [Figure 14] 3 shows an example of the structure of an oscillator which is a device according to the present embodiment. [Figure 15] 3A to 3C are manufacturing process diagrams of the manufacturing method of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present embodiment will be described below. Note that the present embodiment described below does not unduly limit the contents of the claims. Furthermore, not all of the configurations described in the present embodiment are necessarily essential configurations.

[0009] 1. Pad lead wiring FIG. 1 shows a cross-sectional view of the pad region of the integrated circuit device 20 of this embodiment, and FIG. 2 shows a plan view of the pad region. The integrated circuit device 20 of this embodiment includes a pad 2, an extraction wiring 5, and a via group 6. As shown in FIG. 2, the pad 2 is a pad having a shape having a long side and a short side. For example, when the pad 2 is a quadrilateral, the pad 2 is a rectangular shape having a long side and a short side. The shape of the pad 2 is not limited to a rectangle, and may be, for example, a shape that includes an ellipse or an oval, and may be, for example, a polygon having five or more sides such as a hexagon or an octagon, or a shape that is approximately an ellipse. For example, the corners of the pad 2 may be chamfered, which can reduce stress concentration on the corners. The area of ​​the pad 2 is a region of the metal layer constituting the pad 2 that is exposed on the active surface of the integrated circuit device 20. For example, in FIG. 1, the pad 2 is composed of a metal layer ALE such as aluminum, which is the top layer. Of the metal layer ALE, the region of the opening exposed from the passivation film 3, which is an oxide film formed so as to cover the metal layer ALE, becomes the region of the pad 2.

[0010] 1 and 2, a circuit 8 is provided that overlaps with the pad 2 in a plan view and is electrically connected to the pad 2. The circuit 8 is, for example, a functional circuit having a predetermined function. The circuit is, for example, composed of a plurality of circuit elements. The circuit elements are active elements such as transistors, and passive elements such as resistors and capacitors. For example, in FIG. 1, the circuit 8 includes an N-type transistor formed in a P-type well PWL, and a P-type transistor formed in an N-type well NWL. Note that FIG. 1 is a schematic diagram showing the layout relationship between the pad 2 and the circuit 8, and in reality, the layout area of ​​the transistors and the like of the circuit 8 relative to the layout area of ​​the pad 2 is sufficiently small, and a necessary number of circuit elements such as transistors that constitute the circuit 8 are arranged below the pad 2.

[0011] 1, for example, from a direction perpendicular to the semiconductor substrate constituting the integrated circuit device 20. As shown in FIG. 2, the circuit 8 is arranged so as to overlap the pad 2 in the plan view. For example, when the direction DR toward the semiconductor substrate is a downward direction, the circuit 8 is arranged below the pad 2. The pad 2 and the circuit 8 are electrically connected via the lead-out wiring 5, the via group 6, etc. By arranging the circuit 8 so as to overlap the pad 2 in the plan view in this way, it is possible to reduce the layout area of ​​the integrated circuit device 20.

[0012] As shown in FIG. 2, the lead-out wiring 5 is a wiring drawn from the outer edge EDL on the long side of the pad 2 along the short-side direction DS of the pad 2. For example, in FIG. 2, the outer edge EDL is an outer edge along the long-side direction DL of the pad 2, and the outer edge EDS is an outer edge along the short-side direction DS of the pad 2. When the pad 2 has a rectangular shape, the outer edge EDL on the long side is the long side of the pad 2, and the long-side direction DL is the direction along the long side. Also, the outer edge EDS on the short side is the short side of the pad 2, and the short-side direction DS is the direction along the short side. As shown in FIG. 1, the lead-out wiring 5 is made of the metal layer ALE of the same layer as the pad 2. For example, the lead-out wiring 5 is a wiring drawn by extending the metal layer ALE of the pad 2 along the short-side direction DS of the pad 2.

[0013] The via group 6 electrically connects the lead-out wiring 5 and the wiring 7 of the circuit 8. The via group 6 is arranged so as not to overlap the pad 2 in a plan view. For example, the via group 6 electrically connecting the lead-out wiring 5 and the wiring 7 is not arranged below the pad 2, but is arranged below the lead-out wiring 5 drawn from the outer edge EDL of the pad 2 in the short direction DS. For example, in FIG. 1 and FIG. 2, the integrated circuit device 20 has five metal layers ALA to ALE. The metal layers ALA to ALE are, for example, metal layers of aluminum or aluminum alloy. The number of metal layers is not limited to five, and may be four or less, or six or more. The via group 6 includes a plurality of vias connecting between these metal layers. The vias are also called via wiring, for example, and are composed of via holes and metal plugs. For example, the via group 6 includes vias connecting the metal layer ALE and the metal layer ALD, vias connecting the metal layer ALD and the metal layer ALC, vias connecting the metal layer ALC and the metal layer ALB, and the like. These multiple vias are arranged side by side, for example, along the direction DR, below the lead-out wiring 5. The via group 6 including these multiple vias electrically connects the metal layer ALE constituting the lead-out wiring 5 and the metal layer ALB constituting the wiring 7. One end of the wiring 7 is connected to a via in the via group 6, and the other end is electrically connected to the circuit 8. For example, the other end of the wiring 7 is connected to a circuit element constituting the circuit 8. For example, the wiring 7 is electrically connected to the drain, source, or gate of a transistor, which is a circuit element, or one end of a resistor or capacitor, which is a passive element. Note that while FIG. 1 shows the wiring 7 formed of the metal layer ALB, the wiring electrically connecting the via group 6 and the circuit 8 may be formed of another metal layer, such as the metal layers ALA and ALC.

[0014] As described above, in this embodiment, the circuit 8 is arranged so as to overlap the pad 2 in a plan view. This allows the circuit 8 to be arranged by effectively utilizing the area of ​​the pad 2, thereby realizing a reduction in the area of ​​the integrated circuit device 20. That is, by arranging the circuit 8 in the area of ​​the pad 2, the area of ​​the integrated circuit device 20 can be reduced by the area of ​​the circuit 8 compared to the case where the circuit 8 is arranged outside the area of ​​the pad 2. Furthermore, since the pad 2 has a shape having a longitudinal direction and a lateral direction, even if a force along the longitudinal direction of the pad 2 is applied when the integrated circuit device 20 is mounted, it is possible to suppress the occurrence of defects such as short circuits and disconnections in the wiring. For example, when ultrasonic bonding is performed during mounting as described later, by setting the vibration direction of the ultrasonic waves to the longitudinal direction of the pad 2, it is possible to suppress the occurrence of short circuits in the wiring caused by the vibration of the ultrasonic waves. Furthermore, in this embodiment, the lead-out wiring 5 is led out along the lateral direction DS of the pad 2 from the outer edge EDL on the longitudinal side of the pad 2, and the lead-out wiring 5 and the wiring 7 of the circuit 8 are electrically connected by the via group 6. In this way, even if a force acts along the longitudinal direction of the pad 2 when mounting the integrated circuit device 20, the risk of damage being applied to the lead-out wiring 5 and the via group 6, causing a short circuit or disconnection, can be suppressed. Therefore, it is possible to provide an integrated circuit device 20 that can suppress damage to the lead-out wiring 5 and the via group 6 for electrically connecting the pad 2 to the circuit 8 arranged so as to overlap the pad 2. That is, it is possible to realize an appropriate lead-out wiring 5 that electrically connects the pad 2 to the circuit 8 while realizing a small area of ​​the integrated circuit device 20 by arranging the circuit 8 so as to overlap the pad 2. As a method of a comparative example of this embodiment, a method of providing a via directly under the pad 2 and connecting the pad 2 and the circuit 8 through this via is also considered. However, if a via is arranged directly under the pad 2, problems such as peeling off of the metal layer ALE of the pad 2 or damage to the via may occur. In this regard, in this embodiment, the via group 6 is provided in a place that does not overlap the pad 2 in a plan view, so that such problems can be prevented from occurring.

[0015] 1, the wiring 7 is a wiring of the metal layer ALB below the metal layer ALE of the pad 2, and a part of the wiring 7 overlaps with the pad 2 in a plan view. By providing such wiring 7, the lead-out wiring 5 from the pad 2 is connected to one end of the wiring 7 through the via group 6, and the other end of the wiring 7 is connected to the circuit 8, so that the pad 2 can be electrically connected to the circuit element of the circuit 8 arranged so as to overlap with the pad 2. Therefore, the circuit 8 electrically connected to the pad 2 can be arranged so as to overlap with the pad 2 in a plan view, and the area of ​​the integrated circuit device 20 can be reduced.

[0016] Also, in FIG. 1, the wiring 7 is made of the metal layer ALB arranged at a distance of one layer from the metal layer ALE of the pad 2. For example, the wiring 7 of the circuit 8 is made of the metal layer ALB arranged at a distance of one layer from the metal layer ALE of the pad 2, instead of the metal layer ALD directly below the metal layer ALE of the pad 2. Note that, although the wiring 7 is made of the metal layer ALB in FIG. 1, the wiring 7 may be made of the metal layer ALC or the metal layer ALA arranged at a distance of one layer from the metal layer ALE of the pad 2. For example, if the wiring 7 of the circuit 8 is made of the metal layer ALD directly below the metal layer ALE of the pad 2, the wiring 7 may be damaged and defects such as disconnection may occur when weight is applied to the pad 2 during mounting, etc. In this regard, if the wiring 7 of the circuit 8 is made of the metal layer ALB, metal layer ALC, or metal layer ALA arranged at a distance of one layer from the metal layer ALE of the pad 2, the wiring 7 may be prevented from being damaged and defects may occur, and reliability, etc. may be improved. For example, in this embodiment, the lead-out wiring 5 from the pad 2 and the wiring 7 are electrically connected by multiple vias in the via group 6, so that the wiring 7 of the circuit 8 can be constructed using metal layer ALB, metal layer ALC or metal layer ALA that is arranged at a distance of at least one layer from the metal layer ALE of the pad 2.

[0017] As shown in FIG. 2, the lead-out wiring 5 has a shape in which the longitudinal direction DL of the pad 2 is the longitudinal direction. For example, the lead-out wiring 5 has a shape in which the longitudinal direction DL of the pad 2 is the longitudinal direction and the short-side direction DS of the pad 2 is the short-side direction. For example, in FIG. 2, the longitudinal direction DL of the pad 2 is the vertical direction on the paper, and the short-side direction DS of the pad 2 is the horizontal direction on the paper, and the pad 2 has a shape in which the vertical length is longer than the horizontal length. Similarly, the lead-out wiring 5 has a shape in which the vertical length is longer than the horizontal length. In this way, the lead-out wiring 5 with a short length in the horizontal direction can be led out from the outer edge EDL on the longitudinal side of the pad 2, and the lead-out wiring 5 can be connected to the wiring 7 of the circuit 8 through the via group 6. By increasing the vertical length of the lead-out wiring 5, it is possible to increase the number of vias provided in the area of ​​the lead-out wiring 5, thereby improving resistance to static electricity and reducing the impedance of the wiring.

[0018] As shown in FIG. 2, the vias in the via group 6 are arranged in a line along the longitudinal direction of the draw-out wiring 5. For example, in FIG. 2, a plurality of rows of via groups are arranged in a line along the longitudinal direction of the draw-out wiring 5, and specifically, three rows of via groups are arranged. The number of rows of the via group is not limited to three, and may be one row or four or more rows. In this way, by arranging the vias in the via group 6 in a line along the longitudinal direction of the draw-out wiring 5, it is possible to increase the number of via groups 6 for electrically connecting the draw-out wiring 5 and the wiring 7 of the circuit 8. This makes it possible to improve resistance to static electricity and reduce the impedance of the wiring, thereby improving the reliability of the integrated circuit device 20.

[0019] 2, the draw-out wiring 5 has a shape in which the corners are chamfered in a plan view. For example, the draw-out wiring 5 has a substantially rectangular shape with the long side in the vertical direction and the short side in the horizontal direction on the paper surface of FIG. 2 by chamfering the corners as shown in A1 and A2. In FIG. 2, the upper right corner shown in A1 and the lower right corner shown in A2 are chamfered. By chamfering the corners of the draw-out wiring 5 in this way, for example, when static electricity is applied to the pad 2, it is possible to suppress the concentration of electric charge at the corners and the occurrence of destruction due to heat generation, etc. This improves the reliability of the integrated circuit device 20.

[0020] In addition, the pad 2 in this embodiment is an input pad PI to which an input signal is input, as shown in FIG. 3, for example. The circuit 8 arranged to overlap the input pad PI in a plan view is an I / O circuit 22 to which an input signal is input from the input pad PI. The I / O circuit 22 includes an input buffer circuit that receives and buffers the input signal, and outputs the buffered input signal to a circuit inside the integrated circuit device 20. In this way, the input signal to the input pad PI can be input to the I / O circuit 22 via the lead-out wiring 5, the via group 6, and the wiring 7. The input pad PI has a shape having a longitudinal direction and a lateral direction, and the lead-out wiring 5 is led out from the outer edge EDL on the longitudinal side of the input pad PI. Therefore, even if a force acts along the longitudinal direction of the input pad PI during mounting of the integrated circuit device 20, it is possible to suppress the occurrence of defects such as a short circuit and the damage to the lead-out wiring 5 and the via group 6. Furthermore, since the I / O circuit 22 can be arranged by effectively utilizing the area of ​​the input pad PI, the area of ​​the integrated circuit device 20 can be reduced in comparison with the case where the I / O circuit 22 is arranged outside the area of ​​the input pad PI. In Fig. 3, the electrostatic protection circuit 21, power supply stabilization capacitor, etc. are also arranged so as to overlap with the input pad PI in a plan view. This makes it possible to further reduce the area of ​​the integrated circuit device 20 by effectively utilizing the area of ​​the input pad PI.

[0021] In addition, the pad 2 in this embodiment is an output pad PQ that outputs an output signal, as shown in FIG. 4, for example. The circuit 8 arranged so as to overlap the output pad PQ in a plan view is an output buffer circuit 52 that outputs an output signal to the output pad PQ. The output buffer circuit 52 buffers an output signal from a circuit inside the integrated circuit device 20, for example, and outputs it to the output pad PQ. In this way, the output signal from the output buffer circuit 52 can be output from the output pad PQ via the wiring 7, the via group 6, and the draw-out wiring 5. The output pad PQ has a shape having a longitudinal direction and a lateral direction, and the draw-out wiring 5 is drawn out from the outer edge EDL on the longitudinal side of the output pad PQ. Therefore, even if a force acts along the longitudinal direction of the output pad PQ when the integrated circuit device 20 is mounted, it is possible to suppress the occurrence of defects such as a short circuit and damage to the draw-out wiring 5 and the via group 6. In addition, since the output buffer circuit 52 can be arranged by effectively utilizing the area of ​​the output pad PQ, the integrated circuit device 20 can be reduced in area. Furthermore, when the output buffer circuit 52 outputs an output signal such as a high-frequency clock signal, the output buffer circuit 52 becomes a noise source. In this regard, in Fig. 4, the output pad PQ is disposed so as to cover the output buffer circuit 52, which is a noise source, and the metal layer of the output pad PQ acts as a shielding layer, preventing the noise source from affecting other circuits in the integrated circuit device 20. This makes it possible to prevent a decrease in performance of the integrated circuit device 20 caused by noise from the output buffer circuit 52.

[0022] In addition, the pad 2 in this embodiment is a ground pad PGND to which a ground is supplied, as shown in FIG. 5, for example. The circuit 8 arranged to overlap the ground pad PGND in a plan view is a reference voltage generating circuit 62 that generates a reference voltage. The reference voltage generating circuit 62 generates a reference voltage that is constant even if the power supply voltage or temperature changes. For example, the reference voltage generating circuit 62 generates a reference voltage for generating at least one of a bias current, a bias voltage, or a regulated power supply voltage. For example, the integrated circuit device 20 has an analog circuit, and the reference voltage generating circuit 62 generates a reference voltage for generating a bias current or a bias voltage for this analog circuit. The integrated circuit device 20 also has a regulator, and the regulator generates a regulated power supply voltage that is a constant voltage obtained by stepping down the power supply voltage based on the reference voltage generated by the reference voltage generating circuit 62, and supplies the generated regulated power supply voltage to each circuit block of the integrated circuit device 20. If the layout arrangement is as shown in FIG. 5, the ground voltage supplied to the ground pad PGND can be supplied to the reference voltage generating circuit 62 via the lead wiring 5, the via group 6, and the wiring 7. The ground pad PGND has a shape having a longitudinal direction and a lateral direction, and the lead-out wiring 5 is led out from the outer edge EDL on the longitudinal side of the ground pad PGND, so that even if a force along the longitudinal direction of the ground pad PGND acts, it is possible to suppress the occurrence of defects such as a short circuit of the wiring or damage to the lead-out wiring 5. In addition, the reference voltage generating circuit 62 can be arranged by effectively utilizing the area of ​​the ground pad PGND, so that the area of ​​the integrated circuit device 20 can be reduced. In addition, in FIG. 5, the ground pad PGND is arranged so as to cover the reference voltage generating circuit 62, so that the metal layer of the ground pad PGND becomes a shielding layer, and it is possible to suppress the noise from other circuits of the integrated circuit device 20 from being transmitted and being superimposed on the reference voltage generated by the reference voltage generating circuit 62. Therefore, the reference voltage generating circuit 62 can generate a low-noise reference voltage, and it is also possible to suppress the performance degradation of the integrated circuit device 20 caused by the noise superimposed on the reference voltage.

[0023] 6, the integrated circuit device 20 includes a second lead-out wiring 9 led from the outer edge EDS of the short side of the pad 2 along the longitudinal direction DL of the pad 2 in addition to the lead-out wiring 5 led from the outer edge EDL of the long side of the pad 2 along the transverse direction DS of the pad 2. The second lead-out wiring 9 is made of the same metal layer ALE as the pad 2. For example, in a power supply pad to which a power supply voltage is supplied, the power supply voltage supplied to the power supply pad may be supplied to each circuit of the integrated circuit device 20 through a plurality of lead-out wirings. In such a power supply pad, as shown in FIG. 6, a second lead-out wiring 9 led from the outer edge EDS of the short side of the pad 2 may be provided. In this case, the lead-out wiring 5 and the second lead-out wiring 9 supply the same potential of the power supply voltage to each circuit of the integrated circuit device 20, so that it is considered that there is little risk of malfunction even if a force along the longitudinal direction of the pad is applied.

[0024] Next, a defect caused by ultrasonic bonding during mounting of the integrated circuit device 20 will be described. In FIG. 7, a bump BMP is formed on the pad 2 of the integrated circuit device 20. This bump BMP is, for example, called a stud bump, and is used, for example, in flip-chip mounting of the integrated circuit device 20. In the stud bump, a ball is formed at the tip of a wire such as a gold wire, and the ball is pressure-bonded to the upper surface of the pad 2 using heat, ultrasonic vibration, or the like, and then the wire is cut. As a result, a bump BMP such as a gold bump can be formed near the center of the pad 2 as shown in FIG. 7. Then, the integrated circuit device 20 having the bump BMP formed on the pad 2 in this way is flip-mounted on the surface SF, which is the mounting surface of the package 15, as shown in FIG. 14 described later. Specifically, the integrated circuit device 20 is arranged so that the other end of the bump BMP comes into contact with a terminal TM formed on the surface SF of the package 15, and the other end of the bump BMP is bonded to the terminal TM formed of gold or the like by ultrasonic vibration.

[0025] However, when ultrasonic bonding is performed using such ultrasonic vibration, the bump BMP formed on the pad 2 may spread in the direction of ultrasonic vibration and may protrude from the area of ​​the pad 2 as shown in FIG. 8. When such a situation occurs, the protruding bump BMP contacts the passivation film 3 in FIG. 1 at B1 in FIG. 8, causing a crack. In the pad 2 made of a metal softer than the passivation film 3, the force of ultrasonic vibration does not cause much of a problem, but when the force of ultrasonic vibration is applied to the hard passivation film 3, a crack occurs. Then, the metal of the pad 2 passes through the crack and contacts other wiring, causing a defect such as a short circuit. In order to prevent such a defect from occurring, in this embodiment, the pad 2 is shaped so that the direction of ultrasonic vibration is the longitudinal direction, as shown in B2 in FIG. 8. Specifically, the pad 2 is shaped, for example, as a rectangle with the direction of ultrasonic vibration being the long side direction. In this way, even if the ultrasonic vibration causes the shape of the bump BMP in a planar view to become elliptical, it is possible to prevent the bump BMP from protruding from the pad 2, and it is possible to prevent defects such as wiring shorts caused by the occurrence of cracks as described above.

[0026] On the other hand, in the method of arranging the circuit 8 so as to overlap the pad 2, the lead-out wiring 5 and the via group 6 are required to electrically connect the pad 2 and the circuit 8. However, if the lead-out wiring 5 from the pad 2 is led out from the outer edge EDS on the short side of the pad 2, ultrasonic vibration may cause stress on the lead-out wiring 5 and the via group 6, which may cause defects such as short circuits and disconnections. Therefore, in this embodiment, the pad 2 is formed in a shape having a longitudinal direction and a lateral direction, the lead-out wiring 5 is led out from the outer edge EDL on the long side of the pad 2, and the lead-out wiring 5 and the wiring 7 of the circuit 8 are electrically connected by the via group 6. In this way, even if the longitudinal direction of the pad 2 is the vibration direction of the ultrasonic vibration, it is possible to prevent defects such as short circuits and disconnections caused by stress on the lead-out wiring 5 and the via group 6 due to the stress caused by the ultrasonic vibration.

[0027] As described above, in Figs. 7 and 8, the pad 2 is a pad electrically connected to an external terminal by the bump BMP. The bump BMP is ultrasonically bonded to the terminal. The longitudinal direction DL of the pad 2 is the direction of ultrasonic vibration for ultrasonic bonding. In other words, the longitudinal direction DL of the pad 2 is the longitudinal direction of the bump BMP. In this way, it is possible to prevent the bump BMP from protruding from the area of ​​the pad 2 as shown in Fig. 8, which may cause defects such as a short circuit. In addition, the drawing wiring 5 is drawn out from the outer edge EDL on the longitudinal side of the pad 2, which prevents the stress caused by the ultrasonic vibration for ultrasonic bonding from being applied to the drawing wiring 5 and the via group 6, which may prevent defects such as a short circuit and a break in wiring.

[0028] In the above, a case where a defect such as a short circuit occurs due to ultrasonic vibration in a stud bump has been described, but this embodiment is not limited to this. For example, ultrasonic vibration may also be used in wire bonding, and in this case, the method of making the longitudinal direction DL of the pad 2 the direction of ultrasonic vibration and drawing out the lead wire 5 from the outer edge EDL of the longitudinal side of the pad 2 is effective. The bump BMP may be a bump other than a stud bump, and even when stress is applied in a predetermined direction by some method other than ultrasonic bonding, the method of making the longitudinal direction of the pad 2 the predetermined direction and drawing out the lead wire 5 from the outer edge EDL of the longitudinal side of the pad 2 is effective. The phenomenon in which the bump BMP protrudes from the area of ​​the pad 2 may also occur when the bump BMP is formed on the pad 2 by ultrasonic bonding.

[0029] The structure of the pad 2 is not limited to the structure shown in FIG. 1, and various structures can be adopted. FIG. 9 is a cross-sectional view showing another example of the structure of the pad 2. In FIG. 9, conductive layers 92, 93, and 94 are formed on a pad metal 91 by plating or the like. The conductive layer 92 is formed of a material that has good bonding properties with the pad metal 91 formed of aluminum or an aluminum alloy, for example, nickel or a nickel alloy. The conductive layer 92 has a thickness of, for example, 2 μm to 10 μm. By increasing the thickness of the conductive layer 92 in this way, even if a large load is applied when a bump or a bonding wire is bonded to the pad 2, this load is unlikely to be transmitted below the pad 2. Therefore, it is possible to prevent a situation in which a malfunction occurs in the circuit 8 provided below the pad 2 due to the load when bonding the bump or the bonding wire. The conductive layer 93 is interposed between the conductive layer 92 and the conductive layer 94, and functions as a barrier layer that increases the adhesion between the conductive layers 92 and 94 and prevents the conductive layer 92 from diffusing into the conductive layer 94. The conductive layer 93 is formed of a material having good adhesion to both the conductive layer 92 and the conductive layer 94, for example, palladium or a palladium alloy. The conductive layer 93 may be provided as necessary, and may be omitted, for example, when the adhesion between the conductive layer 92 and the conductive layer 94 is good. The conductive layer 94 functions as a connection layer with the bump or bonding wire. The conductive layer 94 is formed of a material having low contact resistance with the bump or bonding wire, for example, gold or a gold alloy. By using the pad 2 having the structure shown in FIG. 9, the circuit 8 under the pad can be protected against the load applied during mounting when the bump or bonding wire is bonded to the pad 2, and the bump or bonding wire can be bonded with low contact resistance, which makes it possible to facilitate mounting and improve reliability.

[0030] 2. Integrated Circuit Device Next, a specific example of the integrated circuit device 20 of this embodiment will be described. Fig. 10 is a diagram showing a configuration example of the integrated circuit device 20 of this embodiment. The integrated circuit device 20 is not limited to the configuration of Fig. 10, and various modifications are possible, such as omitting some of its components or adding other components. In the following, a case will be mainly described as an example in which the device of this embodiment in which the integrated circuit device 20 is incorporated is an oscillator 4, but the device of this embodiment is not limited to the oscillator 4.

[0031] The integrated circuit device 20 in FIG. 10 includes an oscillator circuit 30. The integrated circuit device 20 can also include an output circuit 50, a power supply circuit 60, a logic circuit 70, a temperature compensation circuit 80, a temperature sensor circuit 90, a power supply pad PVDD, a ground pad PGND, a clock pad PCK, an output enable pad POE, and pads PX1 and PX2 for connecting an oscillator. The oscillator 4, which is an example of a device of this embodiment, includes an oscillator 10 and an integrated circuit device 20. The oscillator 10 is electrically connected to the integrated circuit device 20. For example, the oscillator 10 and the integrated circuit device 20 are electrically connected to each other using internal wiring, bonding wires, metal bumps, or the like of a package that houses the oscillator 10 and the integrated circuit device 20.

[0032] The vibrator 10 is an element that generates mechanical vibration by an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 can be realized by a quartz crystal vibrating piece that vibrates in a thickness shear manner such as an AT cut or SC cut cut angle, a tuning fork type quartz crystal vibrating piece, or a double tuning fork type quartz crystal vibrating piece. For example, the vibrator 10 may be a vibrator built in a temperature compensated crystal oscillator (TCXO) that does not have a thermostatic oven, or a vibrator built in an oven-controlled crystal oscillator (OCXO) that has a thermostatic oven. Alternatively, the vibrator 10 may be a vibrator built in an oscillator of an SPXO (Simple Packaged Crystal Oscillator). Note that the vibrator 10 of this embodiment can also be realized by various vibrating pieces such as a vibrating piece other than a thickness shear vibration type, a tuning fork type, or a double tuning fork type, or a piezoelectric vibrating piece formed of a material other than quartz. For example, the vibrator 10 may be a surface acoustic wave (SAW) resonator or a micro electro mechanical systems (MEMS) vibrator as a silicon vibrator formed using a silicon substrate.

[0033] The integrated circuit device 20 is, for example, an IC (Integrated Circuit) manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate.

[0034] The oscillator circuit 30 is a circuit that oscillates the vibrator 10. For example, the oscillator circuit 30 is electrically connected to the pads PX1 and PX2, and generates an oscillation signal OSC by oscillating the vibrator 10. The pad PX1 is a pad for connecting a first vibrator, and the pad PX2 is a pad for connecting a second vibrator. For example, the oscillator circuit 30 can be realized by a driving circuit for oscillation provided between the pads PX1 and PX2, and active elements such as a capacitor and a resistor. The driving circuit can be realized by, for example, a CMOS inverter circuit or a bipolar transistor. The driving circuit is a core circuit of the oscillator circuit 30, and the driving circuit drives the vibrator 10 with a voltage or current to oscillate the vibrator 10. As the oscillator circuit 30, various types of oscillator circuits such as an inverter type, a Pierce type, a Colpitts type, or a Hartley type can be used. In addition, a variable capacitance circuit is provided in the oscillator circuit 30, and the oscillation frequency can be adjusted by adjusting the capacitance of this variable capacitance circuit. The variable capacitance circuit can be realized by a variable capacitance element such as a varactor. For example, the variable capacitance circuit can be realized by a variable capacitance element whose capacitance is controlled based on a temperature compensation voltage. Alternatively, the variable capacitance circuit may be realized by a capacitor array and a switch array connected to the capacitor array. The connection in this embodiment is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be a connection via a passive element or the like.

[0035] The output circuit 50 outputs a clock signal CKQ based on the oscillation signal OSC. The output circuit 50 includes an output buffer circuit 52. The output buffer circuit 52 outputs a signal obtained by buffering the oscillation signal OSC as a clock signal CKQ to the clock pad PCK. Then, this clock signal CKQ is output to the outside via the external terminal TCK of the oscillator 4. For example, the output circuit 50 outputs the clock signal CKQ in a single-ended CMOS signal format. Note that the output circuit 50 may be configured to output the clock signal CKQ in a signal format other than CMOS. For example, the output circuit 50 may output a differential clock signal to the outside in a signal format such as LVDS (Low Voltage Differential Signaling), PECL (Positive Emitter Coupled Logic), HCSL (High Speed ​​Current Steering Logic), or differential CMOS (Complementary MOS).

[0036] The power supply circuit 60 receives the power supply voltage VDD from the power supply pad PVDD and the ground voltage from the ground pad PGND, and supplies various power supply voltages for the internal circuits of the integrated circuit device 20 to the internal circuits. For example, the power supply circuit 60 supplies a regulated power supply voltage based on the power supply voltage VDD to the oscillator circuit 30 and the like. The power supply circuit 60 includes a reference voltage generating circuit 62 and a regulator 64. The reference voltage generating circuit 62 generates and outputs a reference voltage. The reference voltage generating circuit 62 can be realized by, for example, a band gap reference circuit, a circuit using a gate work function difference, or a circuit using a threshold voltage difference caused by changing the channel impurity concentration. The regulator 64 receives the power supply voltage VDD and generates various regulated power supply voltages. For example, the regulator 64 generates a constant regulated power supply voltage by stepping down the power supply voltage VDD based on the reference voltage generated by the reference voltage generating circuit 62, and supplies the generated regulated power supply voltage to each circuit block of the integrated circuit device 20.

[0037] The logic circuit 70 is a control circuit that performs various control processes. For example, the logic circuit 70 controls the entire integrated circuit device 20 and controls the operation sequence of the integrated circuit device 20. For example, the logic circuit 70 controls each circuit block of the integrated circuit device 20, such as the oscillation circuit 30, the output circuit 50, the power supply circuit 60, or the temperature compensation circuit 80. The logic circuit 70 can be realized by an ASIC (Application Specific Integrated Circuit) circuit that is automatically placed and wired, such as a gate array.

[0038] The temperature compensation circuit 80 performs temperature compensation of the oscillation signal OSC of the oscillation circuit 30. The temperature compensation of the oscillation signal OSC is temperature compensation of the oscillation frequency of the oscillation circuit 30. Specifically, the temperature compensation circuit 80 performs temperature compensation based on temperature detection information from the temperature sensor circuit 90. For example, the temperature compensation circuit 80 generates a temperature compensation voltage VCP based on a temperature detection voltage VT from the temperature sensor circuit 90, and outputs the generated temperature compensation voltage VCP to the oscillation circuit 30, thereby performing temperature compensation of the oscillation signal OSC of the oscillation circuit 30. For example, the temperature compensation circuit 80 performs temperature compensation by outputting a temperature compensation voltage VCP, which is a capacitance control voltage of the variable capacitance circuit, to a variable capacitance circuit included in the oscillation circuit 30. In this case, the variable capacitance circuit of the oscillation circuit 30 is realized by a variable capacitance element such as a varactor. The temperature compensation is a process of suppressing and compensating for fluctuations in the oscillation frequency due to temperature fluctuations. For example, the temperature compensation circuit 80 performs analog temperature compensation by polynomial approximation. For example, when the temperature compensation voltage for compensating for the frequency-temperature characteristic of the vibrator 10 is approximated by a polynomial, the temperature compensation circuit 80 performs analog temperature compensation based on coefficient information of the polynomial. The temperature compensation circuit 80 may also perform digital temperature compensation.

[0039] The temperature sensor circuit 90 is a sensor circuit that detects temperature. Specifically, the temperature sensor circuit 90 outputs a temperature-dependent voltage that changes according to the temperature of the environment as a temperature detection voltage VT. For example, the temperature sensor circuit 90 generates the temperature detection voltage VT by using a circuit element having temperature dependency. Specifically, the temperature sensor circuit 90 outputs a temperature detection voltage VT whose voltage value changes depending on temperature by using the temperature dependency of the forward voltage of a PN junction. For example, the base-emitter voltage of a bipolar transistor can be used as the forward voltage of the PN junction. Note that when performing digital temperature compensation processing, the temperature sensor circuit 90 measures temperatures such as the environmental temperature and outputs the result as temperature detection data.

[0040] The integrated circuit device 20 also includes a power supply pad PVDD, a ground pad PGND, a clock pad PCK, an output enable pad POE, and pads PX1 and PX2 for connecting oscillators. These pads are terminals of the integrated circuit device 20, which is, for example, a semiconductor chip.

[0041] The power supply pad PVDD is a pad to which a power supply voltage VDD is supplied. For example, the power supply voltage VDD from an external power supply device is supplied to the power supply pad PVDD. The ground pad PGND is a terminal to which a ground voltage GND is supplied. GND can also be called VSS, and the ground voltage is, for example, a ground potential. In this embodiment, the ground is described as GND as appropriate. The clock pad PCK is a pad to which a clock signal CKQ is output. For example, a clock signal CKQ based on an oscillation signal OSC in the oscillation circuit 30 is output to the outside from the clock pad PCK. The output enable pad POE is a pad for controlling the output enable of the clock signal CKQ. Specifically, the output enable control of the clock signal CKQ is performed based on an output enable signal OE input via the output enable pad POE. For example, the logic circuit 70 receives the output enable signal OE from the output enable pad POE and performs the output enable control of the clock signal CKQ in the output circuit 50.

[0042] The power supply pad PVDD, the ground pad PGND, the clock pad PCK, and the output enable pad POE are electrically connected to the external terminals TVDD, TGND, TCK, and TOE for external connection of the oscillator 4, respectively. For example, they are electrically connected using internal wiring of the package, bonding wires, metal bumps, or the like. The external terminals TVDD, TGND, TCK, and TOE of the oscillator 4 are electrically connected to an external device. The pads PX1 and PX2 are pads for connecting the resonator 10. For example, the pad PX1 is electrically connected to one end of the resonator 10, and the pad PX2 is electrically connected to the other end of the resonator 10. For example, the resonator 10 and the pads PX1 and PX2 of the integrated circuit device 20 are electrically connected to each other using internal wiring, bonding wires, metal bumps, or the like of a package that houses the resonator 10 and the integrated circuit device 20.

[0043] FIG. 11 shows a configuration example of the reference voltage generating circuit 62. The reference voltage generating circuit 62 in FIG. 11 includes an N-type transistor TD1, resistors RD1, RD2, RD3, and bipolar transistors BP1 and BP2 that are provided between the VDD node and the GND node. The reference voltage generating circuit 62 also includes P-type transistors TD2 and TD3 to whose gates a bias voltage VB is input, and a bipolar transistor BP3 that is provided between the drain node of the transistor TD2 and the GND node. The reference voltage generating circuit 62 is a bandgap reference circuit that generates and outputs a reference voltage VREF based on a bandgap voltage. For example, the base-emitter voltages of the PNP bipolar transistors BP1 and BP2 are VBE1 and VBE2, respectively, and ΔVBE=VBE1-VBE2. The reference voltage generating circuit 62 outputs a reference voltage VREF that satisfies, for example, VREF=K×ΔVBE+VBE2. K is set by the resistance values ​​of the resistors RD1 and RD2. For example, since VBE2 has a negative temperature characteristic and ΔVBE has a positive temperature characteristic, it is possible to generate a constant reference voltage VREF that is not temperature dependent by adjusting the resistance values ​​of resistors RD1 and RD2. The generated reference voltage VREF is a constant voltage based on the ground voltage.

[0044] FIG. 12 shows another example of the configuration of the reference voltage generating circuit 62. The reference voltage generating circuit 62 in FIG. 12 is also a bandgap reference circuit, and includes N-type transistors TE1 and TE2, P-type transistors TE3, TE4, and TE5, resistors RE1 and RE2, and diodes DI1, DI2, and DI3 having PN junctions. The N-type transistors TE1 and TE2 form a current mirror circuit, and the P-type transistors TE3, TE4, and TE5 also form a current mirror circuit, so that the currents flowing through these transistors are almost equal. The source voltages of the N-type transistors TE1 and TE2 are also almost equal. The number of parallel connections of the PN junctions in the diode DI2 is formed to be M times the number of parallel connections of the PN junctions in the diode DI1. Therefore, when the saturation current of the diode DI1 is Is, the saturation current of the diode DI2 is M×Is. Here, if the current flowing through transistors TE3, TE4, and TE5 is I, the voltages across diodes DI1, DI2, and DI3 are Vd1, Vd2, and Vd3, respectively, and the resistances of resistors RE1 and RE2 are R1 and R2, then the reference voltage VREF generated by the reference voltage generating circuit 62 is expressed by the following equation (1).

[0045] VREF = I R2 + Vd3 =(R2 / R1)·(kT / q)·In(M)+Vd3 (1)

[0046] Here, k is the Boltzmann constant, T is the absolute temperature, and q is the charge of an electron. Differentiating the above equation (1) with respect to the absolute temperature T gives the following equation (2).

[0047] dVREF / dT=(R2 / R1)·(k / q)·In(M)+Vd3 / dT (2)

[0048] In the above formula (2), the term Vd3 / dT has negative temperature characteristics, and by adjusting the value of (R2 / R1)·(k / q)·In(M) to a positive value correspondingly, the value of the above formula (2) can be made zero, making it possible to generate a reference voltage VREF with canceled temperature dependency. Note that the reference voltage generating circuit 62 is not limited to the configurations in Figures 11 and 12, and circuits of various configurations can be used, such as a circuit that generates the reference voltage VREF using the work function difference voltage of a transistor.

[0049] In the above, the device of the present embodiment is the oscillator 4, and an example of the configuration of the integrated circuit device 20 incorporated in the oscillator 4 has been described, but the present embodiment is not limited to this. For example, the device of the present embodiment may be a sensor device such as a gyro sensor or an acceleration sensor, a display device that displays an image on a display panel, a communication device that communicates according to a predetermined communication standard, a drive device that drives a predetermined mechanism of a printer, or a power supply device that supplies and controls power. The integrated circuit device 20 of the present embodiment is also not limited to being incorporated in the oscillator 4, and may be an IC (Integrated Circuit) incorporated in the above-mentioned sensor device, display device, communication device, or power supply device. For example, when the device is a gyro sensor, the integrated circuit device 20 may include a drive circuit that drives the vibrator of the gyro sensor, a detection circuit that detects a sensor signal from the vibrator, and the like. When the device is an acceleration sensor, the integrated circuit device 20 may include a drive circuit and a detection circuit of an acceleration sensor element realized by (MEMS Micro Electro Mechanical Systems) and the like. When the sensor is a display device, the integrated circuit device 20 may include a drive circuit of the display panel, a logic circuit that processes display data, and the like. In the case where the sensor is a communication device, the integrated circuit device 20 may include a communication physical layer circuit, a link layer circuit, and a logic circuit. In this manner, circuits of various configurations can be adopted as the integrated circuit device 20.

[0050] 3.Layout arrangement FIG. 13 shows an example of the layout arrangement of the integrated circuit device 20 of FIG. 10. The external shape of the integrated circuit device 20 includes a side SD1 and a side SD2 opposite to the side SD1. The side SD1 is the first side, the side SD2 is the second side, and the side SD2 is the opposite side to the side SD1. The external shape of the integrated circuit device 20 also includes sides SD3 and SD4 intersecting the sides SD1 and SD2. The side SD3 is the third side, the side SD4 is the fourth side, and the side SD4 is the opposite side to the side SD3. The external shape of the integrated circuit device 20 is the external shape of, for example, a rectangular semiconductor chip which is the integrated circuit device 20. For example, the sides SD1, SD2, SD3, and SD4 are the sides of the substrate of the semiconductor chip. The semiconductor chip is also called a silicon die. Here, the direction from the side SD1 toward the side SD2 is defined as DR1, and the direction from the side SD3 toward the side SD4 is defined as DR2. The opposite direction to the direction DR1 is defined as direction DR3, and the opposite direction to the direction DR2 is defined as direction DR4. The directions DR1, DR2, DR3, and DR4 are the first direction, the second direction, the third direction, and the fourth direction, respectively.

[0051] 13, the integrated circuit device 20 is provided with a ground pad PGND, a power pad PVDD, a clock pad PCK, and an output enable pad POE. The power pad PVDD and the clock pad PCK are arranged along a side SD1. The clock pad PCK is arranged, for example, at a first corner where the sides SD1 and SD4 intersect. The output enable pad POE and the ground pad PGND are arranged along a side SD2. The ground pad PGND is arranged, for example, at a second corner where the sides SD2 and SD4 intersect. The temperature sensor circuit 90 is arranged, for example, at a third corner where the sides SD2 and SD3 intersect. The temperature sensor circuit 90 may be arranged so as to overlap the output enable pad POE in a plan view.

[0052] Here, the output enable pad POE corresponds to the input pad PI in FIG. 3, and the clock pad PCK corresponds to the output pad PQ in FIG. 4. The ground pad PGND is the ground pad PGND in FIG. 5. The output enable pad POE, the clock pad PCK, the ground pad PGND, and the power supply pad PVDD arranged in the integrated circuit device 20 are pads having a shape having a longitudinal direction and a lateral direction as described in FIG. 1 and the like, and are specifically rectangular pads. For example, these pads are pads having a longitudinal direction in a direction DR1 and a lateral direction in a direction DR2. That is, the integrated circuit device 20 includes a plurality of pads having a longitudinal direction in a direction DR1 and a lateral direction in a direction DR2. The direction DR1 is, for example, the vibration direction of the ultrasonic waves described in FIG. 8. In other words, the integrated circuit device 20 includes a pad and a second pad as a plurality of pads, and the pad and the second pad are shaped to have a longitudinal direction and a lateral direction, respectively. The longitudinal direction of the pad and the longitudinal direction of the second pad are the same direction DR1, and the direction DR1 is the vibration direction of the ultrasonic waves.

[0053] The integrated circuit device 20 is also provided with pads PX1 and PX2 for connecting a resonator. The pads PX1 and PX2 for connecting a resonator are arranged along the side SD3. For example, the oscillation circuit 30 is arranged along the side SD3, and the pads PX1 and PX2 for connecting a resonator are arranged in the area of ​​the oscillation circuit 30. The output circuit 50 is arranged along the side SD1, and the power supply circuit 60 is arranged along the side SD4. The logic circuit 70 is arranged between the oscillation circuit 30 and the power supply circuit 60. The temperature compensation circuit 80 is arranged between the oscillation circuit 30 and the output circuit 50, and the logic circuit 70 is arranged between the temperature compensation circuit 80 and the side SD2.

[0054] 13, the reference voltage generating circuit 62 is arranged so as to overlap the ground pad PGND in a plan view. That is, as explained in FIG. 5, the reference voltage generating circuit 62 is arranged below the ground pad PGND. In this way, the shielding effect of the ground pad PGND suppresses the transmission of high-frequency noise to the reference voltage generating circuit 62, and it is possible to prevent the occurrence of potential fluctuations in the reference voltage generated by the reference voltage generating circuit 62, which in turn prevents the accuracy of the clock frequency from decreasing. In addition, the reference voltage generating circuit 62 can be arranged by effectively utilizing the arrangement area of ​​the ground pad PGND, thereby realizing a reduction in the area of ​​the integrated circuit device 20. Note that the circuits of the power supply circuit 60 other than the reference voltage generating circuit 62 are arranged, for example, along the side SD4 without overlapping the ground pad PGND in a plan view.

[0055] 13, the output buffer circuit 52 is arranged so as to overlap the clock pad PCK in a plan view. That is, as described in FIG 4, the output buffer circuit 52 is arranged below the clock pad PCK. Note that, among the output circuit 50, the circuits other than the output buffer circuit 52 are arranged, for example, along the side SD1 without overlapping the clock pad PCK in a plan view.

[0056] By arranging the clock pad PCK and the output buffer circuit 52 so as to overlap each other in a plan view, the clock signal CKQ from the output buffer circuit 52 can be output to the clock pad PCK through a short-path clock wiring route from the output buffer circuit 52 to the clock pad PCK arranged directly above it. This makes it possible to minimize the impedance of the clock wiring, and suppress potential fluctuations caused by the impedance. The output buffer circuit 52 has high driving capability because it needs to drive a large external load. Therefore, if the impedance of the clock wiring is high, the potential fluctuations also become large, and the signal quality of the clock signal CKQ deteriorates. In this regard, by arranging the clock pad PCK and the output buffer circuit 52 so as to overlap each other in a plan view, the route of the clock wiring connecting the output buffer circuit 52 and the clock pad PCK can be a short-path route, and the impedance of the clock wiring can be minimized, making it possible to suppress deterioration of the signal quality of the clock signal CKQ. In addition, since the output buffer circuit 52 has a high driving capability so that it can drive an external load, it generates a large amount of high-frequency noise, and the output buffer circuit 52 and the clock pad PCK from which the clock signal CKQ is output become sources of high-frequency noise. In this regard, if the clock pad PCK and the output buffer circuit 52 are arranged so as to overlap in a plan view, such high-frequency noise sources can be arranged together in one place. This makes it possible to easily implement measures such as layout arrangement for reducing the adverse effects of noise from these high-frequency noise sources.

[0057] 13, the external shape of the integrated circuit device 20 includes a side SD1 and a side SD2 opposite to the side SD1, and the output buffer circuit 52 and the clock pad PCK are arranged on the side SD1, and the reference voltage generating circuit 62 and the ground pad PGND are arranged on the side SD2. The side SD1 is the first side, and the side SD2 is the second side. For example, the output buffer circuit 52 and the clock pad PCK are arranged in a location closer to the side SD1 than the side SD2. The reference voltage generating circuit 62 and the ground pad PGND are arranged in a location closer to the side SD2 than the side SD1. For example, the output buffer circuit 52 and the clock pad PCK are arranged in a first region between the side SD1 and the center lines of the sides SD1 and SD2, and the reference voltage generating circuit 62 and the ground pad PGND are arranged in a second region between the side SD2 and the center lines of the sides SD1 and SD2. In this way, the output buffer circuit 52 and the clock pad PCK, which are sources of high-frequency noise, are arranged on the side SD1, while the reference voltage generating circuit 62 and the ground pad PGND, which need to be protected from high-frequency noise, are arranged on the side SD2. This makes it possible to separate the output buffer circuit 52 and the clock pad PCK, which are sources of high-frequency noise, from the reference voltage generating circuit 62 and the ground pad PGND. This makes it possible to prevent high-frequency noise from the output buffer circuit 52 and the clock pad PCK from being transmitted to the reference voltage generating circuit 62 and the ground pad PGND, and to prevent deterioration of the accuracy of the clock frequency caused by high-frequency noise.

[0058] The external shape of the integrated circuit device 20 also includes a side SD3, which is a third side intersecting the sides SD1 and SD2, and the oscillator circuit 30 is provided on the side SD3. For example, the oscillator circuit 30 is provided along the side SD3. Specifically, the oscillator circuit 30 is arranged so that, for example, the long side of the oscillator circuit 30 is along the side SD3. By arranging the oscillator circuit 30 on the side SD3 in this manner, the distance between the output buffer circuit 52 and the oscillator circuit 30 arranged on the side SD1 side can be increased, and it becomes possible to prevent a situation in which high-frequency noise of the output buffer circuit 52 is superimposed on the oscillation signal OSC and the oscillation characteristics are deteriorated. Furthermore, by arranging the oscillator circuit 30 on the side SD3, the distance between the reference voltage generating circuit 62 and the oscillator circuit 30 arranged on the side SD2 side can be increased, and it becomes possible to prevent a situation in which the oscillation noise from the oscillator circuit 30 is superimposed on the reference voltage of the reference voltage generating circuit 62 and the accuracy of the clock frequency is reduced.

[0059] The integrated circuit device 20 also includes a temperature compensation circuit 80 that performs temperature compensation of the oscillation frequency of the oscillation signal OSC. As shown in FIG. 13, the temperature compensation circuit 80 is provided between the oscillation circuit 30 and the clock pad PCK. For example, the temperature compensation circuit 80 is provided on the DR2 side of the oscillation circuit 30, and the clock pad PCK is provided on the DR2 side of the temperature compensation circuit 80. By providing the temperature compensation circuit 80 between the oscillation circuit 30 and the clock pad PCK in this way, the area between the oscillation circuit 30 and the clock pad PCK can be effectively used to arrange the temperature compensation circuit 80, and an efficient layout arrangement can be achieved. In addition, the distance between the clock pad PCK, which is a noise source, and the oscillation circuit 30 can be increased, and the transmission of noise from the clock pad PCK to the oscillation circuit 30 can be suppressed. In addition, the temperature compensation circuit 80 can be arranged near the oscillation circuit 30, and the temperature compensation voltage VCP from the temperature compensation circuit 80 can be input to the oscillation circuit 30 through a short-path signal path, thereby realizing temperature compensation of the oscillation frequency.

[0060] 4. Oscillator 14 shows an example of the structure of an oscillator 4, which is an example of a device according to this embodiment. The oscillator 4 has a resonator 10, an integrated circuit device 20, and a package 15 that houses the resonator 10 and the integrated circuit device 20. The package 15 is made of, for example, ceramics, and has an accommodation space inside, in which the resonator 10 and the integrated circuit device 20 are accommodated. The accommodation space is hermetically sealed, and is preferably in a reduced pressure state that is close to a vacuum. The package 15 can suitably protect the resonator 10 and the integrated circuit device 20 from impact, dust, heat, moisture, and the like.

[0061] The package 15 has a base 16 and a lid 17. Specifically, the package 15 is composed of the base 16 that supports the vibrator 10 and the integrated circuit device 20, and the lid 17 that is joined to the upper surface of the base 16 so as to form a storage space between the base 16 and the lid 17. The vibrator 10 is supported via a terminal electrode on a step portion provided on the inside of the base 16. The integrated circuit device 20 is disposed on a surface SF that is the inner bottom surface of the base 16. Specifically, the integrated circuit device 20 is disposed so that the active surface faces the inner bottom surface of the base 16. The active surface is a surface on which the circuit elements of the integrated circuit device 20 are formed. Furthermore, bumps BMP are formed on pads 2 that are terminals of the integrated circuit device 20. The integrated circuit device 20 is supported on the surface SF of the base 16 via the conductive bumps BMP. The conductive bumps BMP are metal bumps such as gold bumps. One end of the bump BMP is connected to the pad 2 of the integrated circuit device 20, and the other end of the bump BMP is connected to the terminal TM provided on the surface SF, which is the mounting surface of the integrated circuit device 20. As a result, the pad 2 of the integrated circuit device 20 is electrically connected to the external terminals 18 and 19, which are the external connection terminals of the oscillator 4, and the resonator 10 via the bump BMP, the terminal TM, and the internal wiring. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to an external device via the external wiring. The external wiring is, for example, wiring formed on a circuit board on which the external device is mounted. This allows the integrated circuit device 20 to output a clock signal, etc. to the external device.

[0062] In FIG. 14, when the integrated circuit device 20 is flip-mounted on the surface SF of the package 15, the ultrasonic bonding described in FIG. 8 is used. Specifically, when the other end of the bump BMP, one end of which is connected to the pad 2 of the integrated circuit device 20, is connected to the terminal TM on the surface SF of the package 15, ultrasonic bonding is used. In this case, in this embodiment, the pad 2 in which the direction of ultrasonic vibration in ultrasonic bonding is the longitudinal direction DL is arranged on the integrated circuit device 20. This makes it possible to suppress the occurrence of defects such as wiring shorts caused by ultrasonic vibration. In addition, the drawing wiring 5 is drawn from the outer edge EDL on the longitudinal side of the pad 2 along the lateral direction DS of the pad 2, and the drawing wiring 5 is electrically connected to the wiring 7 of the circuit 8 below the pad 2 through the via group 6. This makes it possible to suppress the occurrence of defects caused by stress due to ultrasonic vibration or the like being applied to the drawing wiring 5 and the via group 6.

[0063] As described above, a device such as the oscillator 4 of this embodiment includes the integrated circuit device 20, the package 15 in which the integrated circuit device 20 is housed, the terminal TM provided on the surface SF of the package 15, and the bump BMP that electrically connects the terminal TM to the pad 2 of the integrated circuit device 20. In this way, the pad 2 of the integrated circuit device 20 and the terminal TM provided on the surface SF of the package 15 can be electrically connected via the bump BMP, making it possible to output a signal from the integrated circuit device 20 to the terminal TM or input a signal from the terminal TM to the integrated circuit device 20. Even when the integrated circuit device 20 is mounted on the surface SF of the package 15 in this way, the occurrence of the various problems described above can be suppressed by forming the pad 2 into a shape having a longitudinal direction and leading out the lead-out wiring 5 of the pad 2 from the outer edge EDL on the longitudinal side.

[0064] 8, for example, the bump BMP is connected to the terminal TM by ultrasonic bonding, and the longitudinal direction of the pad 2 is the direction of ultrasonic vibration for ultrasonic bonding. In this way, even when stress from ultrasonic vibration in ultrasonic bonding is applied, the pad 2 is shaped to have a longitudinal direction, and the lead-out wiring 5 of the pad 2 is led out from the outer edge EDL on the longitudinal side, thereby making it possible to suppress the occurrence of defects caused by ultrasonic vibration.

[0065] The device of this embodiment includes a resonator 10 accommodated in a package 15 as shown in Fig. 14, and the integrated circuit device 20 includes an oscillation circuit 30 that vibrates the resonator 10 to generate an oscillation signal OSC as shown in Fig. 10. This makes it possible to realize the oscillator 4 as described in Fig. 10 and Fig. 14 as the device of this embodiment. By forming the pad 2 of the integrated circuit device 20 incorporated in the oscillator 4 into a shape having a longitudinal direction and leading out the lead-out wiring 5 of the pad 2 from the outer edge EDL on the longitudinal side, it is possible to realize an oscillator 4 that can suppress the occurrence of the various defects described above, and improve the reliability of the oscillator 4.

[0066] The device of this embodiment is not limited to the oscillator 4 shown in FIG. 14, but may be a sensor device, a display device, a communication device, a power supply device, or the like, as described above.

[0067] 15 is a manufacturing process diagram showing an example of a manufacturing method for the device of this embodiment. The manufacturing method of this embodiment is a manufacturing method for a device including an integrated circuit device 20 and a package 15 in which the integrated circuit device 20 is housed, and includes a manufacturing process S1 for the integrated circuit device 20 and processes S2, S3, and S4 for mounting the integrated circuit device 20 onto the package 15.

[0068] In the manufacturing process S1, the pad 2, the circuit 8 electrically connected to the pad 2, the lead-out wiring 5 of the pad 2, and a via group electrically connecting the lead-out wiring 5 and the wiring 7 of the circuit 8 are formed on the active surface of the integrated circuit device 20. The active surface is a region where circuit elements are formed. As described in FIG. 1, FIG. 2, etc., the pad 2 is a pad having a shape having a longitudinal direction and a lateral direction, and the circuit 8 overlaps the pad 2 in a plan view and is electrically connected to the pad 2. The lead-out wiring 5 is led out from the outer edge EDL of the longitudinal side of the pad 2 along the lateral direction DS of the pad 2. The via group 6 electrically connects the lead-out wiring 5 and the wiring 7 of the circuit 8, and is provided at a position that does not overlap the pad 2 in a plan view. The manufacturing process S1 of the integrated circuit device 20 is realized by a semiconductor process. The semiconductor process includes a film forming process for forming a conductive film, an insulating film, etc., a lithography process for patterning using a resist, etc., an etching process for removing unnecessary oxide films, etc., and an ion implantation process for injecting impurities and activating them by heat treatment, but as these are well known, detailed explanations will be omitted.

[0069] In the mounting process following the manufacturing process S1 of the integrated circuit device, a bump BMP is formed on the pad 2 of the integrated circuit device 20 (process S2). For example, a bump BMP called a stud bump is formed. The bump BMP is not limited to a stud bump. Next, as described in FIG. 14, the integrated circuit device 20 is arranged so that the active surface faces the surface SF of the package 15 (process S3). Then, the terminal TM provided on the surface SF of the package 15 and the bump BMP formed on the pad 2 are connected by ultrasonic bonding with the longitudinal direction of the pad 2 as the vibration direction (process S4). For example, the gold bump BMP and the terminal TM, which is a gold-plated electrode, are rubbed together and bonded using ultrasonic vibration. The amplitude of the ultrasonic waves brings the bonding interfaces closer to each other, causing the metal atoms to diffuse, and the bonding is achieved by this metal diffusion. This allows the bump BMP and the terminal TM to be bonded at low temperatures.

[0070] In this manner, according to the manufacturing method of this embodiment, it becomes possible to use ultrasonic vibration to bond the pad 2 of the integrated circuit device 20 and the terminal TM provided on the surface of the package 15. Also in this case, in this embodiment, the pad 2 of the integrated circuit device 20 is shaped to have a longitudinal direction, and the lead-out wiring 5 of the pad 2 is led out from the outer edge EDL on the longitudinal side, so that it becomes possible to effectively suppress the occurrence of defects caused by stress due to ultrasonic vibration.

[0071] As described above, the integrated circuit device of this embodiment includes a pad having a shape having a longitudinal direction and a lateral direction, a circuit that overlaps the pad in a planar view and is electrically connected to the pad, lead-out wiring that is drawn out from the outer edge of the longitudinal side of the pad along the lateral direction of the pad, and a group of vias that electrically connect the lead-out wiring and the wiring of the circuit and do not overlap the pad in a planar view.

[0072] In this embodiment, the circuit is arranged so as to overlap the pad in a plan view. Therefore, the area of ​​the pad can be effectively utilized to arrange the circuit, and the area of ​​the integrated circuit device can be reduced. In addition, the pad has a shape having a longitudinal direction and a lateral direction, and the wiring of the circuit is electrically connected to the wiring of the circuit, which is drawn from the outer edge of the longitudinal side of the pad along the lateral direction of the pad, by a group of vias, so that the occurrence of defects due to the force acting along the longitudinal direction of the pad can be suppressed. Therefore, it is possible to provide an integrated circuit device or the like that can realize a reduction in the area of ​​the integrated circuit device by arranging the circuit so as to overlap the pad, while realizing an appropriate drawing wiring that electrically connects the pad and the circuit.

[0073] In this embodiment, the wiring is a wiring in a metal layer below the metal layer of the pad, and the wiring may partially overlap the pad in a plan view.

[0074] In this way, the wiring leading from the pad is connected to one end of the wiring through a group of vias, and the other end of the wiring is connected to a circuit element of the circuit, so that the pad can be electrically connected to a circuit element of the circuit that is arranged so as to overlap the pad.

[0075] In this embodiment, the wiring may be a metal layer wiring that is disposed at a distance of at least one layer from the metal layer of the pad.

[0076] In this way, when weight is applied to the pad, it is possible to prevent the wiring from being damaged and causing a malfunction.

[0077] In this embodiment, the lead-out wiring may have a shape whose longitudinal direction coincides with the longitudinal direction of the pad.

[0078] In this way, it becomes possible to draw out a short lead wire in the lateral direction from the outer edge of the longer side of the pad and to electrically connect the lead wire to the circuit wiring through the via group.

[0079] In this embodiment, a plurality of vias in the via group may be arranged side by side along the longitudinal direction of the lead-out wiring.

[0080] In this way, it becomes possible to increase the number of via groups for electrically connecting the lead-out wiring and the circuit wiring.

[0081] In this embodiment, the lead-out wiring may have a shape in which the corners are chamfered in a plan view.

[0082] In this way, when static electricity or the like is applied to the pad, it is possible to prevent the electric charge from concentrating at the corner portion and causing problems.

[0083] In this embodiment, the pad may be an input pad to which an input signal is input, and the circuit may be an I / O circuit to which an input signal is input from the input pad.

[0084] In this way, the input signal to the input pad can be input to the I / O circuit via the lead-out wiring, via group, and wiring, and the area of ​​the input pad can be effectively utilized to reduce the area of ​​the integrated circuit device.

[0085] In this embodiment, the pad may be an output pad that outputs an output signal, and the circuit may be an output buffer circuit that outputs an output signal to the output pad.

[0086] In this way, the output signal from the output buffer circuit can be output from the output pad through the wiring, the via group, and the lead-out wiring, and the performance degradation of the integrated circuit device caused by noise from the output buffer circuit can be suppressed.

[0087] In this embodiment, the pad may be a ground pad to which a ground is supplied, and the circuit may be a reference voltage generating circuit that generates a reference voltage.

[0088] In this way, the ground voltage supplied to the ground pad can be supplied to the reference voltage generating circuit through the lead-out wiring, the via group, and the wiring. In addition, the ground pad acts as a shielding layer, making it possible to suppress the transmission of noise from other circuits in the integrated circuit device and the superposition of the noise on the reference voltage generated by the reference voltage generating circuit.

[0089] Furthermore, in this embodiment, a second lead-out wiring is included that is led out from the outer edge of the short side of the pad along the longitudinal direction of the pad, and the second lead-out wiring may be made of the same metal layer as the pad.

[0090] In this way, depending on the pad, there may be a pad in which the second lead-out wiring is led out from the outer edge on the short side of the pad.

[0091] In this embodiment, the second pad may be included, which has a shape having a longitudinal direction and a lateral direction, and the longitudinal direction of the pad and the longitudinal direction of the second pad may be the same direction.

[0092] In this way, when bonding the integrated circuit device to the package, ultrasonic bonding vibrations can be applied along the longitudinal direction of the pad and the second pad, making it possible to prevent stress caused by ultrasonic vibrations from being applied to the draw-out wiring and via group.

[0093] This embodiment also relates to a device including a package that houses an integrated circuit device, terminals provided on a surface of the package, and bumps that electrically connect the terminals and pads of the integrated circuit device.

[0094] In this way, it is possible to electrically connect the pads of the integrated circuit device to the terminals provided on the surface of the package via the bumps, and it is also possible to prevent problems caused by forces acting along the longitudinal direction of the pads.

[0095] In this embodiment, the bumps are ultrasonically bonded to the terminals, and the longitudinal direction of the pads may be the longitudinal direction of the bumps.

[0096] In this way, it is possible to suppress the occurrence of problems caused by the stress of ultrasonic vibration during ultrasonic bonding.

[0097] In addition, in this embodiment, the integrated circuit device may include a vibrator housed in the package, and may include an oscillation circuit that vibrates the vibrator to generate an oscillation signal.

[0098] In this way, it becomes possible to realize a highly reliable oscillator capable of suppressing the occurrence of various problems.

[0099] The present embodiment is also a method for manufacturing a device including an integrated circuit device and a package in which the integrated circuit device is housed, and includes a manufacturing process for the integrated circuit device and a mounting process for mounting the integrated circuit device in the package. In the manufacturing process, a pad having a shape with a longitudinal direction and a lateral direction, a circuit overlapping the pad in a plan view and electrically connected to the pad, a lead-out wiring drawn out from the outer edge of the longitudinal side of the pad along the lateral direction of the pad, and a via group that electrically connects the lead-out wiring and the wiring of the circuit and does not overlap the pad in a plan view are formed on the active surface of the integrated circuit device. In the mounting process, a bump is formed on the pad of the integrated circuit device, the integrated circuit device is arranged so that the active surface faces the surface of the package, and a terminal provided on the surface of the package is connected to the bump formed on the pad by ultrasonic bonding with the longitudinal direction of the pad as the vibration direction.

[0100] According to this manufacturing method, it is possible to bond the pads of the integrated circuit device to the terminals provided on the surface of the package using ultrasonic vibration. The pads of the integrated circuit device are shaped to have a longitudinal direction, and the lead-out wiring of the pads is led out from the outer edge of the longitudinal side of the pads, thereby making it possible to suppress the occurrence of defects caused by stress due to ultrasonic vibration. Therefore, it is possible to provide a manufacturing method that can realize a circuit overlapping the pad to reduce the area of ​​the integrated circuit device while realizing appropriate lead-out wiring that electrically connects the pads and the circuit.

[0101] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. In addition, all combinations of the present embodiment and modifications are also included in the scope of the present disclosure. In addition, the configuration, operation, and manufacturing method of the integrated circuit device and device are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0102] 2...pad, 3...passivation film, 4...oscillator, 5...drawing wiring, 6...via group, 7...wiring, 8...circuit, 9...second drawing wiring, 10...resonator, 15...package, 16...base, 17...lid, 18...external terminal, 19...external terminal, 20...integrated circuit device, 21...electrostatic protection circuit, 22...I / O circuit, 30...oscillating circuit, 50...output circuit, 52...output buffer circuit, 60...power supply circuit, 62...reference voltage generating circuit, 64...regulator, 70...logic circuit, 80...temperature compensation circuit, 90...temperature sensor circuit, 91...pad metal, 92, 93, 94...conductive layer, ALA~ALE...metal layer, BMP...bump, BP1, BP2, BP3...bipolar transistor, CKQ...clock signal, D I1, DI2, DI3...diode, DL...longitudinal direction, DR, DR1, DR2, DR3, DR4...direction, DS...shortitudinal direction, EDL, EDS...outer edge, OE...output enable signal, OSC...oscillation signal, PCK...clock pad, PGND...ground pad, PI...input pad, POE...output enable pad, PQ...output pad, PVDD...power supply pad, PX1...pad, PX2...pad, RD1~RD3, RE1, RE2...resistor, SD1~SD4...side, SF...face, TD1~TD3, TE1~TE5...transistor, TM...terminal, TCK, TGND, TOE, TVDD...external terminal, VB...bias voltage, VCP...temperature compensation voltage, VDD...power supply voltage, VREF...reference voltage, VT...temperature detection voltage

Claims

1. A pad having a shape having a longitudinal direction and a lateral direction; a circuit overlapping the pad in a plan view and electrically connected to the pad; a lead-out wiring that is led out from an outer edge of a long side of the pad along the short side direction of the pad; a via group that electrically connects the lead-out wiring and the wiring of the circuit and does not overlap the pad in the plan view; the pad is a ground pad to which a ground is supplied, The circuit is a reference voltage generating circuit that generates a reference voltage.

23. An integrated circuit device comprising:

2. 2. The integrated circuit device of claim 1, the wiring is a wiring in a metal layer below a metal layer of the pad, The wiring has a portion overlapping with the pad in the plan view.

3. 3. The integrated circuit device of claim 2, 4. An integrated circuit device, comprising: a first metal layer and a second metal layer, the first metal layer being spaced apart from the first metal layer by at least one layer;

4. 4. The integrated circuit device according to claim 1, The integrated circuit device according to claim 1, wherein the lead-out wiring has a shape whose longitudinal direction coincides with the longitudinal direction of the pad.

5. 5. The integrated circuit device according to claim 4, an integrated circuit device, wherein a plurality of vias in the via group are arranged side by side along the longitudinal direction of the lead-out wiring;

6. 6. The integrated circuit device according to claim 1, The integrated circuit device is characterized in that the lead-out wiring has a shape with chamfered corners in the plan view.

7. 7. The integrated circuit device according to claim 1, a second lead-out wiring led out from an outer edge of a short side of the pad along the longitudinal direction of the pad, The integrated circuit device according to claim 1, wherein the second lead-out wiring is made of the same metal layer as the pad.

8. 8. The integrated circuit device according to claim 1, a second pad having a shape having a longitudinal direction and a lateral direction; an integrated circuit device, wherein the longitudinal direction of the first pad and the longitudinal direction of the second pad are the same direction;

9. An integrated circuit device according to any one of claims 1 to 8; a package in which the integrated circuit device is housed; A terminal provided on a surface of the package; a bump electrically connecting the terminal and the pad of the integrated circuit device; A device comprising:

10. 10. The device of claim 9, the bump is ultrasonically bonded to the terminal; A device, characterized in that the longitudinal direction of the pad is the longitudinal direction of the bump.

11. 11. The device according to claim 9 or 10, a vibrator housed in the package; The device, wherein the integrated circuit device includes an oscillator circuit that vibrates the oscillator to generate an oscillation signal.

12. 1. A method for manufacturing a device including an integrated circuit device and a package in which the integrated circuit device is housed, comprising the steps of: A manufacturing process for the integrated circuit device; a mounting step of mounting the integrated circuit device in the package; Including, In the manufacturing process, a pad having a shape having a longitudinal direction and a lateral direction; a circuit overlapping the pad in a plan view and electrically connected to the pad; a lead-out wiring extending along the lateral direction of the pad and drawn out from an outer edge of the longitudinal side of the pad; and a via group electrically connecting the lead-out wiring and the wiring of the circuit and not overlapping the pad in the plan view; forming a conductive layer on an active surface of the integrated circuit device; the pad is a ground pad to which a ground is supplied, the circuit is a reference voltage generating circuit that generates a reference voltage; In the mounting step, forming bumps on the pads of the integrated circuit device; placing the integrated circuit device with the active surface facing a surface of the package; A manufacturing method comprising connecting a terminal provided on a surface of the package to the bump formed on the pad by ultrasonic bonding in which the longitudinal direction of the pad is the vibration direction.

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