Semiconductor device manufacturing method

Abstract

To provide a semiconductor device and a method for manufacturing the same that can reduce the cost.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: preparing a substrate 20 provided with a first pattern 22a on a first surface 20a, and a semiconductor chip 10 having a second surface 10a, and a third surface 10b opposite to the second surface, and including a second pattern 19 provided on the second surface; recognizing the first pattern from the side of the first surface in the substrate, recognizing the second pattern by transmitting through the semiconductor chip from the side of the third surface in the semiconductor chip; aligning the semiconductor chip 10 with the substrate 20 based on a recognition result of the first pattern and the second pattern; and bonding the semiconductor chip to the substrate so that the second surface faces the first surface.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention Semiconductor device manufacturing method For example, a semiconductor chip is bonded to Semiconductor device manufacturing method Regarding. [Background technology]

[0002] Nitride semiconductor devices such as GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) are used in radio frequency power amplifiers for mobile communication base stations, etc. It is known to mount a semiconductor chip such as a GaN HEMT face-up on a heat dissipating member (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication 2019-176149 Summary of the Invention [Problem to be solved by the invention]

[0004] In face-up mounting, bonding wires are used for electrical connection with the semiconductor chip, which makes it easy for high-frequency characteristics to deteriorate. In order to improve high-frequency characteristics, flip-chip bonding of the semiconductor chip (i.e., face-down mounting) can be considered. When flip-chip bonding a semiconductor chip to a substrate, a flip-chip bonder is used. However, flip-chip bonders have a complex mechanism and the takt time for mounting a semiconductor chip on a substrate is long. For these reasons, it is not suitable for mass production and increases costs.

[0005] The present disclosure has been made in consideration of the above problems, and is directed to a method for reducing costs. Semiconductor device manufacturing method The purpose is to provide. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a method for manufacturing a semiconductor device, including the steps of preparing a first substrate having a first pattern on a first surface and a semiconductor chip having a second surface and a third surface opposite the second surface, the second pattern being provided on the second surface; recognizing the first pattern from the first surface side of the first substrate, recognizing the second pattern from the third surface side of the semiconductor chip through the semiconductor chip, aligning the semiconductor chip and the first substrate based on the recognition results of the first pattern and the second pattern, and bonding the semiconductor chip to the first substrate so that the second surface faces the first surface.

[0007] One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a first surface on which a first pattern is formed; and a semiconductor chip having a second surface and a third surface opposite the second surface, the second surface having a second pattern formed thereon, the third surface having an arithmetic mean roughness of 0.1 μm or less, the semiconductor chip being bonded onto the substrate such that the second surface faces the first surface, the semiconductor chip being transparent to light of at least some of the wavelengths of visible light and infrared light. Effect of the Invention

[0008] According to the present disclosure, it is possible to provide a semiconductor device and a manufacturing method thereof that can reduce costs. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view showing a semiconductor chip in the first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing the semiconductor chip in the first embodiment. [Figure 3A] FIG. 3A is a cross-sectional view showing a method for manufacturing a semiconductor chip in the first embodiment. [Figure 3B] FIG. 3B is a cross-sectional view showing a method for manufacturing the semiconductor chip in the first embodiment. [Figure 3C] FIG. 3C is a cross-sectional view showing a method for manufacturing the semiconductor chip in the first embodiment. [Figure 4A] FIG. 4A is a cross-sectional view showing a method for manufacturing the substrate in the first embodiment. [Figure 4B] FIG. 4B is a cross-sectional view showing a method for manufacturing the substrate in the first embodiment. [Figure 4C] FIG. 4C is a cross-sectional view showing a method for manufacturing the substrate in the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view showing a method for mounting a semiconductor chip on a substrate in the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a method for mounting a semiconductor chip on a substrate in the first embodiment. [Figure 7] FIG. 7 is a plan view of the pattern on the second surface of the semiconductor chip in the first embodiment as viewed from the third surface. [Figure 8] FIG. 8 is a plan view of a pattern on a first surface of a substrate in the first embodiment. [Figure 9] FIG. 9 is a view of the semiconductor chip and the substrate after the semiconductor chip is mounted in the first embodiment, as viewed from the third surface. [Figure 10A] FIG. 10A is a cross-sectional view showing a method for manufacturing the semiconductor device in the first embodiment. [Figure 10B] FIG. 10B is a cross-sectional view showing a method for manufacturing the semiconductor device in the first embodiment. [Figure 10C] FIG. 10C is a cross-sectional view showing a method for manufacturing the semiconductor device in the first embodiment. [Figure 11A] FIG. 11A is a cross-sectional view showing a manufacturing method of the semiconductor device in the first embodiment. [Figure 11B] FIG. 11B is a cross-sectional view showing a method for manufacturing the semiconductor device in the first embodiment. [Figure 11C] FIG. 11C is a cross-sectional view showing a method for manufacturing the semiconductor device in the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view of the semiconductor device in the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view of the semiconductor device according to the first embodiment after mounting. [Figure 14]FIG. 14 is a cross-sectional view showing a method for mounting a semiconductor chip on a substrate in Comparative Example 2. As shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view showing a method for mounting a semiconductor chip on a substrate in Comparative Example 2. As shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a method for manufacturing a semiconductor device, including the steps of: preparing a first substrate having a first pattern on a first surface; and a semiconductor chip having a second surface and a third surface opposite to the second surface, the second surface being provided with a second pattern; recognizing the first pattern from the first surface side of the first substrate, recognizing the second pattern from the third surface side of the semiconductor chip through the semiconductor chip, aligning the semiconductor chip and the first substrate based on the recognition result of the first pattern and the second pattern, and bonding the semiconductor chip to the first substrate so that the second surface faces the first surface. This allows for cost reduction. (2) It is preferable that the bonding step includes the steps of: placing the first substrate on a first stage with the first surface facing up and the semiconductor chip on a second stage with the third surface facing up, recognizing the first pattern from above and recognizing the second pattern through the semiconductor chip; and adsorbing the third surface of the semiconductor chip on the second stage and moving the semiconductor chip onto the first stage to mount the semiconductor chip on the first substrate. (3) It is preferable that the semiconductor chip is transparent to light having at least some of the wavelengths of visible light and infrared light, and the bonding step includes a step of recognizing the second pattern using light having at least some of the wavelengths. (4) It is preferable that the semiconductor chip comprises a second substrate which is a SiC substrate, a sapphire substrate or a GaN substrate and has the third surface, and a nitride semiconductor layer provided on the second substrate and having the second surface. (5) The third surface preferably has an arithmetic mean roughness of 0.1 μm or less. (6) It is preferable that the semiconductor chip processes high frequency signals. (7) It is preferable that the method further includes, after the bonding step, a step of forming a metal layer on the third surface of the semiconductor chip. (8) One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a first surface on which a first pattern is formed; and a semiconductor chip having a second surface and a third surface opposite the second surface, the second surface having a second pattern formed thereon, the third surface having an arithmetic mean roughness of 0.1 μm or less, the semiconductor chip being bonded onto the substrate such that the second surface faces the first surface, the semiconductor chip being transparent to light of at least some of the wavelengths of visible light and infrared light.

[0011] [Details of the embodiment of the present disclosure] Specific examples of semiconductor devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] Example 1 is an example in which a nitride semiconductor chip such as a GaN HEMT is mounted by FO-PLP (Fan-out Panel Level Package) using the RDL (Redistribution Layer) first process method. FO-PLP is a method for manufacturing a package on a rectangular substrate with a width of 500 mm to 700 mm. The RDL first process method is a method for mounting a semiconductor chip on a rectangular substrate after forming a redistribution layer on the rectangular substrate.

[0013] Fig. 1 is a plan view showing a semiconductor chip in Example 1. Fig. 2 is a cross-sectional view showing the semiconductor chip in Example 1. Fig. 2 is a cross-sectional view taken along the line AA in Fig. 1. To As shown in FIG. 1 and FIG. 2, the semiconductor chip 10 has a second surface 10a and a third surface 10b which is the surface opposite to the second surface 10a. The substrate 11 includes a substrate 11a provided on the third surface 10b side and a semiconductor layer 11b provided on the second surface 10a side. When a GaN-HEMT is formed on the semiconductor chip 10, the substrate 11a is, for example, a SiC substrate, a sapphire substrate, or a GaN substrate. The thickness of the substrate 11a is, for example, 10 μm to 500 μm. The semiconductor layer 11b is, for example, a nitride semiconductor layer, such as a GaN layer and an AlGaN (the composition ratio of Al is, for example, 0.3) layer. The substrate 11 is almost transparent to visible light and infrared light.

[0014] A pattern 19 is provided on the second surface 10a of the substrate 11. The pattern 19 includes source fingers 12, drain fingers 14, gate fingers 16, source pads 13, drain pads 15, gate pads 17, and gate wiring 17a. The source fingers 12 and drain fingers 14 are arranged in a staggered manner. A gate finger 16 is provided on the substrate 11 between the source fingers 12 and the drain fingers 14. The gate finger 16 is sandwiched between the source fingers 12 and the drain fingers 14. The source fingers 12 are connected to the source pad 13, and the drain fingers 14 are connected to the drain pad 15. The gate fingers 16 are connected to the gate pad 17 via a gate wiring 17a. The gate wiring 17a crosses the source fingers 12 and the source pad 13 via an insulating layer or air. A protruding metal layer 18 is provided on the source pad 13, the drain pad 15, and the gate pad 17. The protruding metal layer 18 may not be provided.

[0015] The source finger 12 and the drain finger 14 are metal films, for example, a titanium film and an aluminum film from the substrate 11 side. The gate finger 16 is a metal film, for example, a nickel film and a gold film from the substrate 11 side. The source pad 13, the drain pad 15, the gate pad 17 and the gate wiring 17a are metal layers, for example, a gold layer. The protruding metal layer 18 is, for example, a gold bump, a copper bump or a copper pillar. The height of the protruding metal layer 18 is, for example, 5 μm to 50 μm.

[0016] 3A to 3C are cross-sectional views showing a method for manufacturing a semiconductor chip in Example 1. As shown in FIG. 3A, the substrate 11 is a wafer, and is provided with regions 50 that will become a plurality of semiconductor chips. A pattern 19 and a protruding metal layer 18 are formed on the surface 11c of each region 50. The thickness of the substrate 11 is, for example, 500 μm or more. If the substrate 11 transmits infrared rays when the pattern 19 and the like are formed on the surface 11c of the substrate 11, the infrared sensor of the semiconductor manufacturing equipment cannot detect the wafer. For this reason, the back surface 11d of the substrate 11 is a rough surface.

[0017] 3B, rear surface 11d of substrate 11 is ground using grindstone 52 as indicated by arrow 53 to thin substrate 11. The thickness of substrate 11 is, for example, 10 μm to 200 μm. At this time, the grit size of grindstone 52 is, for example, #8000, to make rear surface 11d of substrate 11 a mirror surface. The arithmetic mean roughness Ra of rear surface 11d is, for example, 0.01 μm.

[0018] 3C, the back surface of the thinned substrate 11 is attached to a resin dicing film 54. The thinned substrate 11 is cut using a dicing blade 55. As a result, a plurality of semiconductor chips 10 corresponding to a plurality of regions 50 are formed.

[0019] 4A to 4C are cross-sectional views showing a manufacturing method of the substrate in Example 1. As shown in Fig. 4A, an insulating layer 21 is attached onto a supporting substrate 28. The supporting substrate 28 is an insulating substrate such as a resin substrate, and reinforces the insulating layer 21 in the manufacturing process. The insulating layer 21 is, for example, a resin layer. The upper surface of the insulating layer 21 is the first surface 20a.

[0020] As shown in FIG. 4B, a wiring layer 22 is formed on the first surface 20a of the insulating layer 21 by, for example, plating. The wiring layer 22 is a metal layer such as a copper layer or a gold layer. The wiring layer 22 forms patterns 22a to 22c. This forms the substrate 20. The substrate 20 is a rectangular substrate having a width of, for example, 500 mm to 700 mm, and the cross section of one semiconductor device region is shown. As shown in FIG. 4C, a solder layer 23 is formed on the patterns 22a and 22b by, for example, printing. The solder layer 23 is, for example, tin-silver-copper solder.

[0021] 5 and 6 are cross-sectional views showing a method of mounting a semiconductor chip on a substrate in the first embodiment. As shown in FIG. 5, a general-purpose chip mounter 40 is used as a mounter for mounting a semiconductor chip 10 on a substrate 20. The chip mounter 40 includes cameras 42a and 42b, a collet 41, stages 44 and 45, and a control unit 48. A substrate 20, which is a large rectangular substrate, is mounted on the stage 44. A semiconductor chip 10 is mounted on a position correction stage 45. At this time, the protruding metal layer 18 contacts the upper surface of the stage 45, so that the pattern 19 can be prevented from contacting the upper surface of the stage 45. Therefore, the stage 45 can be prevented from contacting the pattern 19, causing scratches on the pattern 19, and from attaching foreign matter thereto.

[0022] The camera 42a scans the pattern 19 provided on the second surface 10a of the semiconductor chip 10 as indicated by the arrow 43a. No.The camera 42a captures the pattern 19 by transmitting light through the substrate 11 from the third surface 10b side. The camera 42a captures the pattern 19 using light of a wavelength that transmits through the substrate 11. The SiC substrate, sapphire substrate, or GaN substrate used as the substrate 11a is almost transparent to visible light. When a nitride semiconductor layer is used as the semiconductor layer 11b, the GaN layer and the AlGaN layer are almost transparent to visible light. Furthermore, if the third surface 10b of the semiconductor chip 10 is not a mirror surface, light is diffusely reflected on the third surface 10b, and the camera 42a cannot capture the pattern 19. In the first embodiment, the arithmetic mean roughness Ra of the third surface 10b is set to 0.1 μm or less. This makes it possible to suppress the diffuse reflection of light on the third surface 10b.

[0023] When a SiC substrate is used as the substrate 11a, SiC is almost transparent to light with a wavelength of 0.38 μm to 5 μm. If visible light with a wavelength of 0.38 μm to 0.78 μm and infrared light with a wavelength of 0.78 μm to 5 μm are used, the camera 42a can capture an image of the pattern 19 through the substrate 11. For example, the semiconductor chip 10 is illuminated with an LED (Light Emitting Diode) illumination that irradiates light with a wavelength of 0.42 μm to 0.66 μm or a near-infrared illumination that irradiates light with a wavelength of 0.78 μm to 3 μm.

[0024] As indicated by arrow 43b, camera 42b captures an image of pattern 22a provided on first surface 20a of substrate 20. Control unit 48 calculates the relative position between pattern 19 captured by camera 42a and pattern 22a captured by camera 42b.

[0025] 6, collet 41 sucks third surface 10b of semiconductor chip 10. Then, based on the relative positions of patterns 19 and 22a, collet 41 moves semiconductor chip 10 above substrate 20. Collet 41 mounts semiconductor chip 10 on substrate 20.

[0026] Fig. 7 is a plan view of the pattern on the second surface of the semiconductor chip in the first embodiment as viewed from the third surface. As shown in Fig. 7, the pattern 19 on the second surface 10a can be seen from the third surface 10b. The control unit 48 recognizes the pattern of the recognition portion 48a in the pattern 19. To improve the alignment accuracy between the patterns 19 and 22a, it is preferable that the recognition portion 48a is a diagonal pattern in the pattern 19, but the recognition portion 48a may be a pattern other than a diagonal pattern.

[0027] Fig. 8 is a plan view of the pattern on the first surface of the substrate in Example 1. As shown in Fig. 8, pads 31 to 33 are provided as pattern 22a. A source pad 13, a drain pad 15, and a gate pad 17 are bonded to pads 31 to 33, respectively. A control unit 48 recognizes the pattern of a recognition unit 48b in pattern 22a.

[0028] FIG. 9 is a view of the semiconductor chip and the substrate after mounting the semiconductor chip in the first embodiment, seen from the third surface. As shown in FIG. 9, the source pad 13, the drain pad 15, and the gate pad 17 are bonded to the pads 31 to 33, respectively. In FIG. 5, the control unit 48 calculates the relative position between the semiconductor chip 10 and the substrate 20, and in FIG. 6, the control unit 48 mounts the semiconductor chip 10 on the substrate 20 based on the calculated relative position. Therefore, the patterns 19 and 22a are aligned. As shown in FIG. 9, after the semiconductor chip 10 is bonded to the substrate 20, the patterns 19 and 22a can be visually recognized from the third surface 10b side. This allows the bonding state between the pads 31 to 33 and the source pad 13, the drain pad 15, and the gate pad 17 to be inspected using an automated optical inspection (AOI) device.

[0029] 10A to 11C are cross-sectional views showing a method for manufacturing a semiconductor device in Example 1. As shown in FIG. 10A, a semiconductor chip 10 and a chip component 30 are mounted on a substrate 20. The semiconductor chip 10 is mounted on a pattern 22a, and the chip component 30 is mounted on a pattern 22b. The chip component 30 is, for example, a chip resistor, a chip capacitor, or a chip inductor. The general-purpose chip mounter 40 described in FIG. 5 and FIG. 6 is used to mount the semiconductor chip 10 and the chip component 30. By performing reflow (i.e., heat treatment), the solder layer 23 melts and the patterns 22a and 19 are bonded together. As a result, the semiconductor chip 10 is flip-chip bonded to the substrate 20. The bonding state between the patterns 19 and 22a is inspected using an automatic appearance inspection device. In FIG. 10A, the solder layer 23 is bonded to the pattern 19 via the protruding metal layer 18, but the protruding metal layer 18 may not be provided and the solder layer 23 may be directly bonded to the pattern 19.

[0030] As shown in Fig. 10B, a resin layer 24 is formed on the substrate 20 so as to cover the semiconductor chip 10 and the chip components 30. The resin layer 24 is formed by a lamination method in which a resin sheet such as an epoxy resin is attached. The resin layer 24 may also be formed by a molding method. As shown in Fig. 10C, the upper surface of the resin layer 24 is ground or polished to expose the third surface 10b of the semiconductor chip 10.

[0031] As shown in Fig. 11A, through-holes 27 penetrating resin layer 24 are formed by, for example, etching. Pattern 22c is exposed from through-holes 27. As shown in Fig. 11B, through-electrodes 25 are formed in through-holes 27 by, for example, plating. Through-electrodes 25 are metal layers such as copper layers or gold layers.

[0032] As shown in FIG. 11C, a metal layer 26 is formed on the resin layer 24 by, for example, plating. UseThe metal layer 26 is, for example, a copper layer. The metal layer 26 includes patterns 26a and 26b. The pattern 26a is in contact with the third surface 10b of the semiconductor chip 10 and functions as a heat dissipation layer that dissipates heat generated in the semiconductor chip 10. The pattern 26b is electrically connected to the pattern 22c of the wiring layer 22 via the through electrode 25. The pattern 22c is electrically connected to the patterns 22a and 22b. As a result, the pattern 22b functions as an external terminal that electrically connects the semiconductor chip 10 and the chip component 30 to an external device.

[0033] Fig. 12 is a cross-sectional view of the semiconductor device in Example 1. As shown in Fig. 12, the support substrate 28 is removed from the insulating layer 21. After that, the insulating layer 21 and the resin layer 24 are cut into individual pieces. In this way, the semiconductor device 100 is manufactured.

[0034] Fig. 13 is a cross-sectional view of the mounted semiconductor device in Example 1. As shown in Fig. 13, a metal layer 57 is provided on a printed circuit board 56. The metal layer 57 and the metal layer 26 of the semiconductor device 100 are joined via a solder layer 58.

[0035] [Comparative Example] Nitride semiconductor devices such as GaN HEMTs are used in high-frequency power amplifiers for mobile communication base stations. For this reason, semiconductor devices are required to maintain high-frequency characteristics, dissipate heat, and reduce costs. Comparative Example 1, which is mounted face-up in a package, is considered as a mounting method for a semiconductor chip on which a GaN HEMT or the like is formed. A bonding wire is connected to the top surface of the semiconductor chip, and high-frequency signals are input and output to and from the semiconductor chip via the bonding wire. In Comparative Example 1, when mounting the semiconductor chip face-up, expensive nano silver paste is used to ensure heat dissipation, making it difficult to reduce costs. High-frequency signals are input and output to and from the semiconductor chip via the inductance of the bonding wire, which reduces high-frequency characteristics.

[0036] Therefore, mounting using FO-PLP (Fan-out Panel Level Package) is considered as Comparative Example 2. In Comparative Example 2, the semiconductor chip 10 is flip-chip bonded, so that degradation of high frequency characteristics can be suppressed compared to the case of using bonding wires as in Comparative Example 1. Since the metal layer 26 can be directly bonded to the third surface 10b of the semiconductor chip 10, there is no need to use expensive nano silver paste as in Comparative Example 1, and costs can be reduced.

[0037] 14 and 15 are cross-sectional views showing a method of mounting a semiconductor chip on a substrate in Comparative Example 2. As shown in FIG. 14, in Comparative Example 2, a flip chip bonder 40a is used as a mounter for mounting a semiconductor chip 10 on a substrate 20. The flip chip bonder 40a includes a camera 42, a collet 41, a stage 44, and an optical system 46. The optical system 46 has a half mirror surface 46a and a mirror surface 46b, and is disposed between the patterns 22a and 19. The camera 42 can capture an image of the pattern 19 reflected on the half mirror surface 46a as indicated by an arrow 43c. The camera 42 can also capture an image of the pattern 22a that is transmitted through the half mirror surface 46a, reflected on the mirror surface 46b, and reflected on the half mirror surface 46a as indicated by an arrow 43d. The collet 41 moves the semiconductor chip 10 so that the patterns 19 and 22a overlap.

[0038] 15, after the position of the semiconductor chip 10 in the planar direction is determined, the optical system 46 is retracted as indicated by arrow 47a. As indicated by arrow 47b, the collet 41 is moved downward to mount the semiconductor chip 10 on the substrate 20. In Comparative Example 2, the optical system 46 is used to align the patterns 19 and 22a, improving the alignment accuracy. However, since the optical system 46 must be retracted, the takt time is long, making this method unsuitable for mass production. This results in high costs.

[0039] 5, it is also possible to mount the semiconductor chip 10 on the substrate 20 without recognizing the patterns 19 and 22a. However, this reduces the accuracy of aligning the patterns 19 and 22a.

[0040] According to the first embodiment, as shown in Figs. 3A to 3C, a semiconductor chip 10 having a pattern 19 (second pattern) on the second surface 10a is prepared. As shown in Figs. 4A to 4C, a substrate 20 (first substrate) having a pattern 22a (first pattern) on the first surface 20a is prepared. As shown in Figs. 5, 7, and 8, the pattern 19 is recognized through the semiconductor chip 10 from the third surface 10b side of the semiconductor chip 10, and the pattern 22a is recognized from the first surface 20a side of the substrate 20. As shown in Figs. 6 and 9, the semiconductor chip 10 and the substrate 20 are aligned based on the recognition result of the patterns 19 and 22a, and the semiconductor chip 10 is flip-chip bonded to the substrate 20 so that the second surface 10a faces the first surface 20a. This eliminates the need to use a complicated flip-chip bonder 40a as shown in Figs. 14 and 15 of the second comparative example, and the use of a general-purpose chip mounter 40 shortens the tact time, making it possible to mass-produce semiconductor devices. This makes it possible to reduce the cost of the semiconductor device 100. Furthermore, it is possible to prevent the alignment accuracy from decreasing as in the third comparative example.

[0041] As shown in FIG. 5, the substrate 20 is placed on a stage 44 (first stage) with the first surface 20a facing up. On top Then, semiconductor chip 10 is placed on stage 45 (second stage) with third surface 10b facing up. In this state, pattern 22a is recognized from above, and pattern 19 is recognized from above through semiconductor chip 10. As shown in Fig. 6, collet 41 (suction member) sucks third surface 10b of semiconductor chip 10 on stage 45, and semiconductor chip 10 is moved onto stage 44, thereby mounting semiconductor chip 10 on substrate 20. This makes it possible to mass-produce semiconductor devices using general-purpose chip mounter 40.

[0042] The semiconductor chip 10 is transparent to light having at least some of the wavelengths of visible light and infrared light. As shown in FIG. 5, in the process of flip-chip bonding the semiconductor chip 10 to the substrate 20, the semiconductor chip 10 uses transparent light to recognize the pattern 19. This allows the pattern 19 to be recognized by transmitting the light through the semiconductor chip 10 from the third surface 10b side of the semiconductor chip 10. The transmittance of the semiconductor chip 10 for the light used to recognize the pattern 19 is preferably 20% or more, more preferably 50% or more, and even more preferably 80% or more. This allows the pattern 19 to be recognized by transmitting the light through the semiconductor chip 10.

[0043] The substrate 11a (second substrate) is a SiC substrate, a sapphire substrate, or a GaN substrate, and the semiconductor layer 11b is a nitride semiconductor layer. This makes the substrate 11a and the semiconductor layer 11b transparent to at least some of the wavelengths of visible light and infrared light. In addition, the SiC substrate has high thermal conductivity, allowing heat dissipation from the third surface 10b.

[0044] The semiconductor chip 10 is a semiconductor chip that processes (e.g., amplifies) high-frequency signals. In this way, in the semiconductor chip 10 that processes high-frequency signals, the high-frequency characteristics change depending on the alignment position of the patterns 19 and 22a. Therefore, according to the first embodiment, it is possible to improve the alignment accuracy and stabilize the high-frequency characteristics. The high-frequency signal is, for example, a signal of 0.5 GHz to 100 GHz, typically a signal of 0.5 GHz to 10 GHz.

[0045] If the third surface 10b is a rough surface, light is diffusely reflected by the third surface 10b, and therefore the camera 42a cannot recognize the pattern 19. Therefore, the arithmetic mean roughness Ra of the third surface 10b is preferably 0.1 μm or less, more preferably 0.05 μm or less, and even more preferably 0.02 μm or less.

[0046] 11C, after the flip-chip bonding process, a metal layer 26 is formed on the third surface 10b of the semiconductor chip 10. This allows the metal layer 26 and the third surface 10b to be directly bonded, and the metal layer 26 can be used as a heat dissipation layer. If the metal layer 26 is formed using a plating method, it is not necessary to use an expensive nano-silver paste as in Comparative Example 1, and the cost of the semiconductor device 100 can be reduced.

[0047] According to the semiconductor device 100 of the first embodiment, the pattern 22a (first pattern) is provided on the first surface 20a, and the pattern 19 (second pattern) is provided on the second surface 10a. The semiconductor chip 10 is flip-chip bonded onto the substrate 20 so that the second surface 10a faces the first surface 20a. The semiconductor chip 10 is transparent to at least a part of the wavelengths of visible light and infrared light, and the arithmetic mean roughness of the third surface 10b is 0.1 μm or less. In this way, since the third surface 10b is a mirror surface and the semiconductor chip 10 is transparent to at least a part of the wavelengths of visible light and infrared light, the semiconductor chip 10 can be flip-chip bonded onto the substrate 20 using a general-purpose chip mounter as shown in FIG. 5 and FIG. 6. Therefore, the cost of the semiconductor device 100 can be reduced.

[0048] In the first embodiment, the semiconductor chip 10 provided with a single GaN HEMT has been described as an example, but the semiconductor chip 10 may be a MMIC (Monolithic Microwave Integrated Circuit). Although an example using the FO-PLP technique has been described as a semiconductor device, it is sufficient that the semiconductor chip is flip-chip bonded to the substrate.

[0049] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0050] 10. Semiconductor Chips 10a 2nd side 10b Side 3 11, 11a Substrate (second substrate) 11b Semiconductor layer 12 Sauce Finger 13 Sauce Pad 14 Drain Finger 15 Drain Pad 16 Gate Finger 17 Gate Pad 17a Gate wiring 18 protrusion metal layer 19 Patterns (Part 2 pattern) 22a Pattern (Part 1 pattern) 22b, 22c, 26a, 26b patterns 20 Substrate (first substrate) 20a Page 1 21 Insulating layer 22 wiring layer 23, 58 Solder layer 24 Resin layer 25 Through electrode 26, 57 metal layer 27 Through hole 28 Support substrate 30 Chip parts 31~33 Pad 40 Chip mounter 40a flip chip bonder 41 Colette 42, 42a, 42b Camera 43a~43d, 47a, 47b, 53 Arrows Stages 44 and 45 46a Half mirror surface 46b Mirror surface 46 Optical system 48 Control Unit 48a, 48b recognition section 50 areas 52 Grindstone 54 Dicing Film 55 Dicing Blade 56 Printed Circuit Board 100 Semiconductor device

Claims

1. preparing a first substrate having a first surface on which a first pattern is provided, and a semiconductor chip having a second surface and a third surface opposite to the second surface, the second surface being provided with a second pattern; a step of recognizing the first pattern from the first surface side of the first substrate by a first camera and recognizing the second pattern from the third surface side of the semiconductor chip by a second camera through the semiconductor chip in a state in which the first substrate is placed on a first stage with the first surface facing up and the semiconductor chip is placed on a second stage with the third surface facing up; a step of adsorbing the third surface of the semiconductor chip on the second stage, moving the semiconductor chip from the second stage onto the first stage, aligning the semiconductor chip with the first substrate based on a recognition result of the first pattern and the second pattern, and bonding the semiconductor chip to the first substrate such that the second surface faces the first substrate and the first pattern is bonded to the second substrate; A method for manufacturing a semiconductor device comprising the steps of:

2. A method for manufacturing a semiconductor device as described in claim 1, wherein, in the recognition process, the second camera recognizes a pattern of the second pattern of the semiconductor chip that is located diagonally on the second surface.

3. the semiconductor chip is transparent to light having at least a part of the wavelengths of visible light and infrared light; 3. The method of claim 1, wherein the bonding step includes a step of recognizing the second pattern by using light having at least the part of the wavelengths.

4. 4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip comprises: a second substrate which is a SiC substrate, a sapphire substrate, or a GaN substrate and has the third surface; and a nitride semiconductor layer provided on the second substrate and having the second surface.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the third surface has an arithmetic mean roughness of 0.1 μm or less.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor chip processes a high-frequency signal.

7. 7. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a metal layer on the third surface of the semiconductor chip after the bonding step.

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