Semiconductor device and method for manufacturing the same

Abstract

To preferably control a carrier lifetime in a semiconductor device.SOLUTION: A semiconductor device 100 comprises: a semiconductor substrate 10; a hydrogen donor provided inside in a depth direction Z of the semiconductor substrate and having a higher doping concentration than a doping concentration of a dopant of the semiconductor substrate, a peak of a doping concentration distribution at a first position Ps separated at a distance predetermined from one principal surface of the semiconductor substrate in a depth direction of the semiconductor substrate, and a hem of a doping concentration distribution in which the doping concentration is smaller than the peak on one principal surface (upper surface 21) closer than the first position; and a crystal defect region 19-1 having a center peak of a crystal defect density at a shallower position than the first position in a depth direction of the semiconductor substrate.SELECTED DRAWING: Figure 1B

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices such as insulated gate bipolar transistors (IGBTs) are known (see, for example, Patent Document 1). Patent Document 1: U.S. Patent Application Publication No. 2005 / 0116249 Summary of the Invention [Problem to be solved by the invention]

[0003] In a semiconductor device, it is preferable to control the carrier lifetime. [Means for solving the problem]

[0004] In a first aspect of the present invention, there is provided a transistor portion including a semiconductor substrate having a first conductivity type dopant and an emitter region provided on one main surface of the semiconductor substrate; and an active portion including a diode portion having an anode region on the one main surface; and a high concentration region having a doping concentration higher than a dopant concentration of the semiconductor substrate, the high concentration region having a hydrogen concentration peak at a first position in a depth direction of the semiconductor substrate; A crystal defect density peak having the highest density is formed at a second position located closer to the one main surface side of the semiconductor substrate than the high concentration region and closer to the one main surface side than the first position; or The present invention provides a semiconductor device comprising: a first crystal defect region that is provided on the other main surface side of the semiconductor substrate relative to the high concentration region and has a center peak with the highest crystal defect density at a second position that is on the other main surface side of the semiconductor substrate relative to the first position. In the above semiconductor device, the transistor section may have a collector region of a second conductivity type on the other main surface. In any of the above semiconductor devices, the diode section may have a cathode region of a first conductivity type on the other main surface. In any of the above semiconductor devices, the transistor section may have a plurality of gate trench sections or dummy trench sections arranged in an arrangement direction and extending in an extension direction. In any of the above semiconductor devices, the transistor section may have a first mesa section that contacts the gate trench section or the dummy trench section in the arrangement direction. In any of the above semiconductor devices, the diode section may have a plurality of the dummy trench sections in the arrangement direction. In any of the above semiconductor devices, the diode section may have a third mesa section that contacts the dummy trench section in the arrangement direction. In any of the above semiconductor devices, the transistor section may have the first mesa section sandwiched between one or more dummy trench sections in the arrangement direction, closer to the diode section than the gate trench section provided closest to the diode section in the arrangement direction. In any of the above semiconductor devices, an end portion of the first crystal defect region in the arrangement direction may be located in the first mesa portion or the dummy trench portion that is provided on the diode portion side rather than the gate trench portion that is provided closest to the diode portion in the arrangement direction.

[0005] In any of the above semiconductor devices, the first mesa portion may have the emitter region provided on the one main surface. In any of the above semiconductor devices, the transistor portion may have a boundary portion adjacent to the diode portion. The transistor portion may have a boundary portion adjacent to the diode portion. In any of the above semiconductor devices, the boundary portion may have a second mesa portion in which a second conductivity type base region is exposed to the one main surface.

[0006] In any of the semiconductor devices described above, the first crystal defect region may be provided on the one main surface side of the high concentration region, and the second position may be provided on the one main surface side of the first position.

[0007] In any of the above semiconductor devices, the hydrogen concentration distribution in the depth direction of the semiconductor substrate may have a first base which is located closer to the one main surface than the first position and in which the hydrogen concentration decreases from the first position toward the one main surface, and a second base which is located closer to the other main surface of the semiconductor substrate than the first position and in which the hydrogen concentration decreases more steeply from the first position toward the other main surface than the first base.

[0008] In any of the semiconductor devices described above, the first crystal defect region may be provided on the other main surface side of the high concentration region, and the second position may be provided on the other main surface side of the first position.

[0009] In any of the above semiconductor devices, the hydrogen concentration distribution in the depth direction of the semiconductor substrate may have a first base which is located closer to the other main surface than the first position and in which the hydrogen concentration decreases from the first position toward the other main surface, and a second base which is located closer to the one main surface of the semiconductor substrate than the first position and in which the hydrogen concentration decreases more steeply from the first position toward the one main surface than the first base.

[0010] In any of the semiconductor devices described above, the distribution of the doping concentration in the depth direction may have a first donor peak having a lower concentration than a hydrogen concentration at the first position.

[0011] In any of the semiconductor devices described above, the crystal defect density distribution of the first crystal defect region may have a third tail that decreases in the first tail region from the center peak toward the other main surface.

[0012] In any of the semiconductor devices described above, the crystal defect density distribution of the first crystal defect region may have a third tail that decreases in the first tail region from the center peak toward the one main surface.

[0013] In any of the semiconductor devices described above, the transistor portion may have a plurality of the first mesa portions, and at least one of the first mesa portions may be sandwiched between the dummy trench portions in contact with the first mesa portions.

[0014] In any of the above semiconductor devices, the collector region of the transistor portion may extend onto the other main surface of the boundary portion, and the other main surface of one or more third mesa portions in the diode portion closest to the boundary portion may not have the cathode region, but may have the collector region of the boundary portion extending thereto.

[0015] In any of the above semiconductor devices, an end portion of the first crystal defect region in the extension direction may extend outside the active portion further than an end portion of the cathode region.

[0016] In any of the above semiconductor devices, a carrier concentration in the first crystal defect region may be lower than a doping concentration of a dopant in the semiconductor substrate.

[0017] Any of the above semiconductor devices may further include a well region of a second conductivity type that is provided from the one main surface to a depth deeper than the gate trench portion and the dummy trench portion and covers ends of the gate trench portion and the dummy trench portion in the extension direction. In any of the above semiconductor devices, an end of the first crystal defect region in the extension direction may be located inside the well region.

[0018] In any of the above semiconductor devices, the gate trench portion has a gate conductive portion formed of a conductive material and a gate insulating film that insulates the gate conductive portion from the semiconductor substrate, and further includes a gate runner and a gate metal layer provided on the one main surface and connected to the gate conductive portion, and in a top view, at least a portion of the first crystal defect region may overlap with the gate runner or the gate metal layer.

[0019] In a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate including a dopant of a first conductivity type; an active portion including a transistor portion having an emitter region provided on one main surface of the semiconductor substrate or a diode portion having an anode region provided on the one main surface; a high-concentration region having a doping concentration higher than a concentration of the dopant in the semiconductor substrate and having a hydrogen concentration distribution in a depth direction of the semiconductor substrate with a peak at a first position; and a first crystal defect region provided on the other main surface side of the semiconductor substrate than the high-concentration region and having a center peak with the highest crystal defect density at a second position on the other main surface side of the first position. The hydrogen concentration distribution in the depth direction of the semiconductor substrate may have a first foot provided on the other main surface side of the first position and having a hydrogen concentration decreasing from the first position toward the other main surface, and a second foot provided on the one main surface side of the semiconductor substrate than the first position and having a steeper decrease in hydrogen concentration from the first position toward the one main surface than the first foot. The distribution of the doping concentration in the depth direction may have a first donor peak at the first position that is lower than a hydrogen concentration.

[0020] The first position may be located closer to the one main surface than the center in the depth direction of the semiconductor substrate. The first position may be located closer to the other main surface than the center in the depth direction of the semiconductor substrate. The crystal defect density distribution of the first crystal defect region may have a third skirt that decreases in the first skirt region from the center peak toward the one main surface. The semiconductor substrate may include a first conductivity type drift region including the first donor peak, a second conductivity type anode region provided between the one main surface of the semiconductor substrate and the drift region, and a first conductivity type cathode region provided between the other main surface of the semiconductor substrate and the drift region.

[0021] The crystal defect density in the anode region may be the same as the crystal defect density in the drift region. The carrier mobility distribution in the depth direction may have a minimum carrier mobility at the second position. The carrier mobility distribution in the depth direction may have a minimum carrier mobility at the second position. The carrier mobility at the second position may be smaller than the carrier mobility at the first donor peak and smaller than the carrier mobility in the drift region on the one main surface side of the first donor peak.

[0022] The semiconductor substrate may have a first conductive type drift region including the first donor peak. A doping concentration in the drift region on the other main surface side of the high concentration region may be higher than a doping concentration in the drift region on the one main surface side of the high concentration region. In the first crystal defect region, a carrier concentration measured by a spreading resistance measurement method may be lower than the doping concentration. The semiconductor substrate may have a first conductive type buffer region between the drift region and the other main surface of the semiconductor substrate, the buffer region having a doping concentration higher than that of the drift region. The doping concentration distribution in the depth direction of the buffer region may have one or more doping concentration peaks.

[0023] The doping concentration distribution in the depth direction of the buffer region may have a plurality of doping concentration peaks. A second crystal defect region having a center peak of the crystal defect density may be provided between two adjacent doping concentration peaks in the buffer region along the depth direction. The doping concentration distribution in the buffer region may have a plurality of doping concentration peaks. A second crystal defect region having a center peak of the crystal defect density may be provided on the other main surface side of the semiconductor substrate relative to a doping concentration peak located closest to the other main surface side among the plurality of doping concentration peaks in the buffer region. The doping concentration at the first position may be 1×1014 ( / cm3) or more and 1×1015 ( / cm3) or less.

[0024] The semiconductor device may include a transistor section having a collector region of a second conductivity type provided in a region in contact with the other main surface of the semiconductor substrate, and a diode section having a cathode region of a first conductivity type having a doping concentration higher than a dopant concentration of the semiconductor substrate provided in a region in contact with the other main surface of the semiconductor substrate. The diode section may include the first crystal defect region. The transistor section may include the first crystal defect region. The transistor section may include the first crystal defect region in a region in contact with the diode section. The semiconductor device may include an edge termination structure disposed between an outer peripheral edge of the semiconductor substrate. The edge termination structure may include the first crystal defect region. A distance between the peak of the hydrogen concentration distribution and the center peak of the first crystal defect region may be 20 μm or less.

[0025] In a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a semiconductor substrate having a dopant of a first conductivity type, and an active portion including a transistor portion having an emitter region provided on one main surface of the semiconductor substrate, or a diode portion having an anode region provided on the one main surface. The manufacturing method may include a first step of implanting hydrogen ions from the other main surface of the semiconductor substrate in a depth direction of the semiconductor substrate, and a step of annealing the semiconductor substrate at a first temperature to reduce crystal defects generated at a position of a maximum hydrogen concentration of the implantation of the hydrogen ions, and forming a position where the defect density of the crystal defects formed by the implantation of the hydrogen ions is maximum on the other main surface side relative to the position of the maximum hydrogen concentration.

[0026] The manufacturing method may include a second step of implanting hydrogen ions from the other main surface of the semiconductor substrate in a depth direction of the semiconductor substrate before the first step of implanting hydrogen ions from the other main surface of the semiconductor substrate in a depth direction of the semiconductor substrate, and a step of annealing the semiconductor substrate into which the hydrogen ions have been implanted from the other main surface at a second temperature higher than the first temperature. The second step of implanting hydrogen ions from the other main surface of the semiconductor substrate in a depth direction of the semiconductor substrate may include a step of implanting the hydrogen ions multiple times in a depth direction of the semiconductor substrate such that the positions of the peaks of the concentration distribution of the hydrogen ions are different. The manufacturing method may include a step of chipping the semiconductor substrate after the step of annealing at the first temperature, and a soldering step of soldering the chipped semiconductor substrate to a circuit board at a third temperature. The third temperature may be lower than the first temperature.

[0027] In the first step of implanting the hydrogen ions, the hydrogen ions may be implanted with an acceleration energy that provides a range of 8 μm or more from the other main surface of the semiconductor substrate. The acceleration energy in the first step of implanting the hydrogen ions may be 1.0 MeV or more. The acceleration energy may be 1.5 MeV or more.

[0028] The acceleration energy in the first step of implanting the hydrogen ions may be 11.0 MeV or less. The acceleration energy may be 5.0 MeV or less. The acceleration energy may be 2.0 MeV or less. The dose of the hydrogen ions in the first step of implanting the hydrogen ions is 1.0×10 12 / cm 2 The dose of the hydrogen ions in the first step of implanting the hydrogen ions may be 1.0×10 15 / cm 2 It may be the following:

[0029] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0030] [Figure 1A] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 1B] 2 is a diagram showing an example of a partial YZ cross section of the semiconductor device 100. FIG. [Diagram 2] FIG. 2 is a cross-sectional view of a semiconductor device 150 of a comparative example. [Diagram 3] FIG. 1B shows distribution diagrams of the net doping concentration (A), hydrogen concentration and helium concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along line a-a' in the semiconductor device 100 of the embodiment shown in FIG. 1B, and along line z-z' in the semiconductor device 150 of the comparative example. [Figure 4] 2 is a diagram showing another example of a cross section of the semiconductor device 100 according to the present embodiment. FIG. [Diagram 5] 2 is a diagram showing another example of a cross section of the semiconductor device 100 according to the present embodiment. FIG. [Figure 6] 2 is a diagram showing another example of a cross section of the semiconductor device 100 according to the present embodiment. FIG. [Figure 7A]FIG. 5 shows distribution diagrams of the net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along line c-c' in the semiconductor device 100 of the embodiment. [Figure 7B] The diagrams show the distribution of the net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) when the crystal defect region 19-2 on the lower surface 23 side is formed by implanting helium ions. [Figure 7C] Other examples of distribution diagrams of net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) are shown. [Figure 7D] Other examples of distribution diagrams of net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) are shown. [Figure 8A] FIG. 2 is a diagram partially illustrating an example of the upper surface of a semiconductor device 200 according to the present embodiment. [Figure 8B] 13 is a diagram partially illustrating another example of the upper surface of the semiconductor device 200. FIG. [Figure 8C] 13 is a diagram partially illustrating another example of the upper surface of the semiconductor device 200. FIG. [Figure 8D] 13 is a diagram partially illustrating another example of the upper surface of the semiconductor device 200. FIG. [Figure 9A] FIG. 8B is a diagram showing an example of the dd' cross section in FIG. 8A. [Figure 9B] FIG. 8C is a diagram showing an example of the dd' cross section in FIG. 8B. [Figure 9C] FIG. 8D is a diagram showing an example of the dd' cross section in FIG. 8C. [Figure 10A] 1A to 1C are diagrams illustrating an example of an outline of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10B] 11A to 11C are diagrams illustrating another example of the method for manufacturing a semiconductor device. [Figure 11] 1A to 1C are diagrams illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 12 is a diagram showing the distributions of hydrogen concentration (B), crystal defect density (C), and carrier concentration (F) along the line hh' in FIG. 11. FIG. [Figure 13] 10A to 10C are diagrams illustrating another example of the method for manufacturing a semiconductor device according to the embodiment. [Figure 14] 10A to 10C are diagrams illustrating another example of the method for manufacturing a semiconductor device according to the embodiment. [Figure 15] 1A to 1C are diagrams illustrating an example of an outline of a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1 is a diagram illustrating a step of implanting hydrogen ions (protons in this example) from the upper surface 21 side of the semiconductor substrate 10 to form a crystal defect region 19 and a high concentration region 26. FIG. [Figure 17] 1 is a diagram illustrating a step of implanting hydrogen ions (protons in this example) from the lower surface 23 side of the semiconductor substrate 10 to form a crystal defect region 19 and a high concentration region 26. FIG. [Figure 18] FIG. 17 shows distribution diagrams of net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) in the depth direction in the semiconductor device 100. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0032] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0033] In this specification, technical matters may be described using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and a depth direction perpendicular to the top surface of the semiconductor substrate is defined as the Z axis.

[0034] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are reversed. In addition, when P+ type (or N+ type) is described in this specification, it means that the doping concentration is higher than that of P type (or N type), and when P- type (or N- type) is described, it means that the doping concentration is lower than that of P type (or N type).

[0035] In this specification, the doping concentration refers to the concentration of impurities that have become donors or acceptors. In this specification, the difference in concentration between donors and acceptors (i.e., net doping concentration) may be referred to as the doping concentration. Also, the peak value of the doping concentration distribution in a doping region may be referred to as the doping concentration in the doping region.

[0036] FIG. 1A is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, a diamond semiconductor substrate, or an oxide semiconductor substrate such as gallium oxide. The semiconductor substrate 10 in this example is a silicon substrate. In FIG. 1A, the outer peripheral end of the semiconductor substrate 10 is referred to as an outer peripheral end 140.

[0037] The semiconductor device 100 includes an active portion 120 and an edge termination structure 92. The active portion 120 is a region where a main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. That is, the active portion 120 is a region where a current flows in the depth direction inside the semiconductor substrate 10 from the upper surface to the lower surface of the semiconductor substrate 10, or from the lower surface to the upper surface. An interlayer insulating film and an emitter electrode, which will be described later, are provided above the active portion 120, but are omitted in FIG. 1A. The region covered by the emitter electrode may be the active portion 120.

[0038] The active section 120 is provided with at least one of a transistor section 70 and a diode section 80. The transistor section 70 includes a transistor such as an insulated gate bipolar transistor (IGBT). The diode section 80 includes a diode such as a free wheel diode (FWD). In the example of FIG. 1A, the transistor section 70 and the diode section 80 are arranged side by side along a predetermined arrangement direction (Y-axis direction). The transistor section 70 and the diode section 80 may be arranged alternately in contact with each other along the arrangement direction. In the active section 120, the transistor section 70 may be provided at both ends in the Y-axis direction. In another example, the active section 120 may be provided with the diode section 80 and may not be provided with the transistor section 70.

[0039] Each diode portion 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In Fig. 1A, the diode portion 80 indicated by a solid line is a region in which a cathode region 82 is provided on the lower surface 23 of the semiconductor substrate 10. In the semiconductor device 100 of this example, a collector region 22 is provided in the region in contact with the lower surface of the semiconductor substrate 10 other than the cathode region 82.

[0040] The diode section 80 is a region obtained by projecting the cathode region 82 in the Z-axis direction. The transistor section 70 is a region in which the collector region 22 is provided on the lower surface of the semiconductor substrate 10, and unit structures including an emitter region and a gate trench portion, which will be described later, are periodically provided on the upper surface of the semiconductor substrate 10. The diode section 80 may also include an extension region 81 (a portion indicated by a dashed line in FIG. 1A that extends the diode section 80) in the X-axis direction, where the region obtained by projecting the cathode region 82 is extended to the end of the active section 120 or the gate runner 48.

[0041] The semiconductor device 100 of this example further includes a gate metal layer 50 and a gate runner 48. The semiconductor device 100 may also include pads such as a gate pad 116 and an emitter pad 118. The gate pad 116 is electrically connected to the gate metal layer 50 and the gate runner 48. The emitter pad 118 is electrically connected to the emitter electrode 52.

[0042] The gate metal layer 50 may be provided so as to surround the active portion 120 in a top view of the semiconductor substrate 10. The gate pad 116 and the emitter pad 118 may be disposed within a region surrounded by the gate metal layer 50. The gate metal layer 50 may be formed of a metal material such as aluminum or an aluminum-silicon alloy. The gate metal layer 50 is insulated from the semiconductor substrate 10 by an interlayer insulating film. The gate metal layer 50 is provided separately from the emitter electrode. The gate metal layer 50 transmits a gate voltage applied to the gate pad 116 to the transistor portion 70.

[0043] The gate runner 48 connects the gate metal layer 50 and the transistor section 70. The gate runner 48 may be formed of a semiconductor material such as polysilicon doped with impurities. A part of the gate runner 48 may be provided above the active section 120. The gate runner 48 shown in FIG. 1A is provided across the active section 120 in the Y-axis direction. This makes it possible to suppress a drop and delay in the gate voltage even inside the active section 120 away from the gate metal layer 50. A part of the gate runner 48 may be disposed along the gate metal layer 50, surrounding the active section 120. The gate runner 48 may be connected to the transistor section 70 at an end of the active section 120.

[0044] Edge termination structure 92 is provided on the top surface of semiconductor substrate 10, between active portion 120 and outer periphery edge 140 of semiconductor substrate 10. In this example, gate metal layer 50 is disposed between edge termination structure 92 and active portion 120. Edge termination structure 92 may be disposed in an annular shape surrounding active portion 120 on the top surface of semiconductor substrate 10. Edge termination structure 92 in this example is disposed along outer periphery edge 140 of semiconductor substrate 10. Edge termination structure 92 relieves electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 92 has, for example, a guard ring, a field plate, a resurf, or a structure combining these.

[0045] FIG. 1B is a diagram showing an example of a partial YZ cross section of the semiconductor device 100. In this example, a partial YZ cross section of the diode section 80 described in FIG. 1A is shown. As described above, the semiconductor device 100 may be a chip in which the active section 120 is provided with the diode section 80 shown in FIG. 1B and the transistor section 70 is not provided, or may be a chip in which the active section 120 is provided with the diode section 80 and the transistor section 70. In either chip, the diode section 80 may have the same structure as the semiconductor device 100 described in FIG. 1B to FIG. 7D. In addition, the diode section 80 may include a dummy trench section 30, similar to the semiconductor device 100 described in FIG. 9A to FIG. 9C, FIG. 16, and FIG. 17. In FIG. 1B of this example, the dummy trench section 30 is omitted. Note that the diode section 80 may not include the dummy trench section 30. The semiconductor device 100 of this example has a semiconductor substrate 10, an upper surface side electrode 53, and a lower surface side electrode 27. The upper electrode 53 is provided on the upper surface 21 of the semiconductor substrate 10. The lower electrode 27 is provided on the lower surface 23 of the semiconductor substrate 10. The upper electrode 53 and the lower electrode 27 are made of a conductive material such as a metal. The upper surface 21 and the lower surface 23 are the main surfaces of the semiconductor substrate 10.

[0046] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a remaining region in the semiconductor substrate 10 without other doped regions. The dopant in the semiconductor substrate 10 may be an N-type donor such as phosphorus or antimony. As an example, the dopant in the semiconductor substrate 10 is phosphorus. The ratio of the donor concentration to the chemical concentration of the dopant is called the donor conversion rate. The donor conversion rate of the dopant in the semiconductor substrate 10 may be 90% or more and 100% or less of the chemical concentration of the dopant. The donor conversion rate of phosphorus or antimony in this example may be 95% or more and 100% or less.

[0047] The doping concentration of the drift region 18 may match the doping concentration of the semiconductor substrate 10. If the doping concentration of the drift region 18 matches the doping concentration of the semiconductor substrate 10, the dopant of the drift region 18 may match the dopant of the semiconductor substrate 10. Alternatively, the doping concentration of the drift region 18 may be two or more times higher than the doping concentration of the semiconductor substrate 10. In this case, the dopant of the drift region 18 may be different from the dopant of the semiconductor substrate 10. As an example, the dopant of the drift region 18 is hydrogen and the dopant of the semiconductor substrate 10 is phosphorus or antimony.

[0048] The single crystal wafer of the semiconductor substrate 10 may be manufactured from an ingot formed by the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), the float zone method (FZ method), etc. As an example, the single crystal wafer of the semiconductor substrate 10 is a wafer manufactured by the magnetic field applied Czochralski method (MCZ method).

[0049] A first conductive type anode region 14 is provided above the drift region 18. In this example, the anode region 14 is, for example, a P-type. The anode region 14 may be provided between the drift region 18 and the upper surface 21 in the Z-axis direction. In this example, the upper surface of the anode region 14 is provided in contact with the upper surface 21. Also, in this example, the anode region 14 is provided in contact with the drift region 18.

[0050] A cathode region 82 of a first conductivity type having a doping concentration higher than that of the drift region 18 is provided below the drift region 18. In this example, the cathode region 82 is an N+ type, for example. The cathode region 82 is provided in contact with the lower surface 23. In this example, the cathode region 82 and the drift region 18 are provided in contact with each other. The cathode region 82 may be formed by implanting ions such as phosphorus from the lower surface 23 of the semiconductor substrate 10 and annealing the resulting material.

[0051] In the semiconductor device 100 of this example, a high concentration region 26 is provided inside the semiconductor substrate 10. The high concentration region 26 may be formed by implanting hydrogen ions from the top surface 21. The hydrogen ions may be protons, deuthorons, or tritons. In this example, they are protons. The hydrogen concentration distribution in the depth direction of the semiconductor substrate 10 has a peak at a first position Ps that is a predetermined distance Dps away from one main surface (top surface 21 in this example) of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In FIG. 1B, the peak of the hydrogen concentration distribution at the first position Ps is indicated by a symbol (marker) of "x". The first position Ps may be located on the top surface 21 side of ½ of the thickness T of the semiconductor substrate.

[0052] The hydrogen concentration distribution in the depth direction of the semiconductor substrate 10 has a tail, which is lower than the peak, on the upper surface 21 side of the first position Ps. The hydrogen concentration distribution and the tail of the concentration distribution will be described later.

[0053] The high concentration region 26 is provided in a range including the first position Ps. The high concentration region 26 includes a hydrogen donor. The high concentration region 26 may include a VOH complex defect as a hydrogen donor, in which one or more hydrogen (H), oxygen (O), and vacancies (V) are bonded in a cluster shape. The VOH complex defect may be an N-type donor. In this specification, the VOH complex defect may be simply referred to as a hydrogen donor. The chemical concentration of hydrogen may be referred to as a hydrogen concentration. The high concentration region 26 in this example is, as an example, an N+ type.

[0054] The oxygen in the semiconductor substrate 10 may be introduced intentionally or unintentionally. The oxygen in the semiconductor substrate 10 may be introduced from an oxide film formed on the main surface of the semiconductor substrate 10. The oxygen concentration in the semiconductor substrate 10 is 1×10 16 ( / cm 3 ) or more 1×10 18 ( / cm 3 ) or less, and may be 5×10 16 ( / cm 3 ) or more 5×10 17 ( / cm 3 ) or less.

[0055] The hydrogen donor is formed after hydrogen ions are implanted from the main surface (upper surface 21 in this example) of the semiconductor substrate 10. After the hydrogen ion implantation, the semiconductor substrate 10 may be thermally annealed to increase the donor conversion rate of the hydrogen donor. By implanting hydrogen ions, hydrogen donors are formed in the region where hydrogen is present at the maximum concentration (i.e., the region corresponding to the range Rp of the hydrogen ions). Furthermore, by annealing the semiconductor substrate 10, the formation of VOH complex defects is promoted, and the concentration of the hydrogen donor is increased. As a result, a high concentration region 26 having a doping concentration higher than that of the drift region 18 is formed. The high concentration region 26 may be formed so as to be sandwiched between the drift regions 18 in the Z-axis direction (depth direction perpendicular to the main surface of the semiconductor substrate 10). A method for forming the high concentration region 26 will be described later.

[0056] The first position Ps may be a peak position in the Z-axis direction of the doping concentration of the high concentration region 26. In this specification, the peak of the hydrogen donor concentration at the first position Ps may be referred to as a donor peak. The doping concentration at the first position Ps of the high concentration region 26 is 1×10 13 ( / cm 3 ) or more 1×10 17 ( / cm 3 ) or less, and may be 1×10 14 ( / cm 3 ) or more 1×10 16 ( / cm 3 ) or less, and may be 1×10 14 ( / cm 3 ) or more 1×10 15 ( / cm 3 ) or less.

[0057] A crystal defect region 19-1 is provided above the high concentration region 26. The crystal defect region 19-1 may be a region including crystal defects formed by implanting hydrogen ions from the upper surface 21. In FIG. 1B, the range in the Z-axis direction where the crystal defect region 19-1 is provided is indicated by a double-headed arrow.

[0058] The crystal defect region 19-1 has a peak of crystal defect density at a position Ks that is a distance Dks away from the upper surface 21 in the Z-axis direction. The crystal defect region 19-1 may be provided from the position Ks to the upper surface 21. The crystal defects may be defects that serve as carrier recombination centers, and may be mainly vacancies (V) or double vacancies (VV). The crystal defect density may be the density of recombination centers. Generally, dopants such as donors and acceptors are also included in crystal defects, but in this specification, crystal defects are defined as defects that mainly function as recombination centers for carrier recombination.

[0059] In this example, the peak of the crystal defect density in the Z-axis direction in crystal defect region 19-1 is referred to as the center peak. The position of the center peak in the Z-axis direction is position Ks. Position Ks is located at a position shallower than first position Ps, which is the peak position of the doping concentration of high concentration region 26, with respect to upper surface 21. In other words, distance Dks is smaller than distance Dps. In FIG. 1B, the center peak of the crystal defect density at position Ks is indicated by a "+" symbol (marker).

[0060] In the semiconductor device 100 of this embodiment, the carrier lifetime is controlled by crystal defects generated by hydrogen ion implantation. In this embodiment, the region for controlling (reducing) the lifetime is provided in a region that is different in position in the Z-axis direction from the position of the maximum hydrogen concentration (range, Rp) where hydrogen ions stop and hydrogen is most abundant. In this embodiment, the region for reducing the lifetime is a region shallower on the upper surface 21 side than the position of the maximum hydrogen concentration, that is, the hydrogen ion passage region. While the hydrogen ions are passing through the semiconductor substrate 10, they collide with semiconductor atoms (silicon in this embodiment), attenuating their energy and damaging the crystal, forming many crystal defects in a region (passage region) shallower than the range Rp of the hydrogen ions. This forms a crystal defect region in the hydrogen ion passage region to control the lifetime.

[0061] On the other hand, in the vicinity of the position where the hydrogen concentration is maximum, the large amount of hydrogen present causes hydrogen to terminate the dangling bonds in the vacancies and divacancies. As a result, the density of recombination centers in the vicinity of the position where the hydrogen concentration is maximum is extremely lower than in the passage region, and it can be said that the contribution of carrier recombination is almost zero compared to the passage region.

[0062] The center peak of the crystal defect density in the crystal defect region 19-1 may be set as the upper surface side lifetime control region 74. The upper surface side lifetime control region 74 has a higher crystal defect density than other regions of the semiconductor substrate 10. The range in which the lifetime control region is formed in this example will be described later.

[0063] Fig. 2 is a diagram showing a cross section of a semiconductor device 150 of a comparative example. The semiconductor device 150 of the comparative example differs from the semiconductor device 100 shown in Fig. 1B in that an upper surface side lifetime control region 274 is provided instead of the upper surface side lifetime control region 74 in the semiconductor device 100 of the present example shown in Fig. 1B, and in that the high concentration region 26 is not provided. The upper surface side lifetime control region 274 is formed by injecting helium from the upper surface 21.

[0064] In the semiconductor device 150 of the comparative example, the upper surface side lifetime control region 274 is provided at a position Ks' in the Z-axis direction. A distance Dks' in the Z-axis direction from the upper surface 21 to the position Ks' is smaller than the distance Dks in the semiconductor device 100 shown in FIG.

[0065] When helium ions and hydrogen ions are implanted with the same acceleration energy from the upper surface 21 of the semiconductor substrate 10, the hydrogen ions are implanted deeper than the helium ions in the depth direction from the upper surface 21 into the semiconductor substrate 10. For this reason, the distance Dks is greater than the distance Dks'.

[0066] In the semiconductor device 150 of the comparative example, helium injected into the semiconductor substrate 10 hardly becomes a donor, even when annealed, compared with hydrogen. Therefore, the high concentration region 26 is not provided in the semiconductor device 150 of the comparative example. Furthermore, unlike the semiconductor device 100 of the present example, the semiconductor device 150 of the comparative example does not have hydrogen terminating the dangling bonds present in the vacancies and the complex vacancies (or the hydrogen concentration is very low), so that the peak position where the density of crystal defects, which are recombination centers, is maximized overlaps with the peak position of the helium concentration where helium is most abundant in the semiconductor substrate 10. Therefore, the position where carrier recombination occurs most frequently is the peak position of the helium concentration.

[0067] FIG. 3 shows distribution diagrams of the net doping concentration (A), hydrogen concentration and helium concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along line a-a' in the semiconductor device 100 according to the embodiment shown in FIG. 1B, and line z-z' in the semiconductor device 150 according to the comparative example. As described above, in the semiconductor device 100, the upper surface side lifetime control region 74 is formed by implanting hydrogen ions into the semiconductor substrate 10, and in the semiconductor device 150, the upper surface side lifetime control region 274 is formed by implanting helium ions into the semiconductor substrate 10. However, the net doping concentration (A) is shown only as an example for the semiconductor device 100. In FIG. 3, each distribution diagram in the semiconductor device 100 is shown by a solid line, and each distribution diagram in the semiconductor device 150 is shown by a dashed line.

[0068] The vertical axes of distribution diagrams (A), (B), (C), (D), and (F) are displayed in a logarithmic scale, while the vertical axis of distribution diagram (E) is displayed in a linear scale. In the distribution diagrams in Fig. 3 where the vertical axis is displayed in a logarithmic scale, the value of the vertical axis at the point where it intersects with the horizontal axis is not 0 but a predetermined value greater than 0. In each distribution diagram, the horizontal axis is displayed in a linear scale. The horizontal axis of each distribution diagram in Fig. 3 indicates the depth from the upper surface 21 of the semiconductor substrate 10.

[0069] The distribution diagram (A) shows the net doping concentration distribution of electrically activated donors and acceptors (i.e., the distribution of the difference between the donor concentration and the acceptor concentration). As shown in FIG. 1B, the net doping concentration has a peak (donor peak) at the position Ps. In this example, a region that includes the position Ps and has a higher net doping concentration than the drift region 18 is defined as a high concentration region 26. The high concentration region 26 may be a region whose net doping concentration is greater than half the net doping concentration at the position Ps. The peak concentration of the net doping concentration at the position Ps of the high concentration region 26 is referred to as Np.

[0070] In the distribution diagram (A), an N-type region having a doping concentration higher than the doping concentration N0 of the semiconductor substrate 10 is defined as an N+ type. In this example, the doping concentration of the drift region 18 provided at a position deeper than the high concentration region 26 is equal to the doping concentration N0. Hydrogen ions implanted from the upper surface 21 of the semiconductor substrate 10 pass through the drift region 18 provided between the anode region 14 and the high concentration region 26. The doping concentration of the drift region 18 may be higher than the doping concentration N0 of the semiconductor substrate 10 due to the remaining hydrogen donors. The average value of the doping concentration of the drift region 18 may be three times or less the doping concentration N0 of the semiconductor substrate 10.

[0071] In addition, an N-type accumulation region 16 having a higher concentration than the drift region 18 may be provided between the anode region 14 and the drift region 18. The accumulation region 16 is a portion where donor dopants accumulate at a higher concentration than the drift region 18. Two or more accumulation regions 16 may be provided in the depth direction. The two or more accumulation regions 16 may have two or more peaks of doping concentration. The region between two adjacent peaks may be N-type. The two or more accumulation regions 16 may have a kink-like shape.

[0072] The distribution diagram (B) shows the chemical concentration of the implanted hydrogen or helium. In the semiconductor device 100, the hydrogen concentration is shown, and in the semiconductor device 150, the helium concentration is shown. As an example, the chemical concentration of atoms can be measured by secondary ion mass spectrometry (SIMS). The helium and hydrogen concentrations are distributed as implanted helium ions and hydrogen ions are diffused by annealing. The degree of diffusion can be controlled according to the annealing time, annealing temperature, etc. The hydrogen concentration has a peak at the position Ps. The helium concentration has a peak at the position Dks'.

[0073] The hydrogen concentration is the chemical concentration of hydrogen, and the concentration at the position Ps where the hydrogen concentration is the highest peak is called Hp. The peak hydrogen concentration Hp is higher than the peak concentration Np of the net doping concentration at the position Ps. If the donor conversion rate of the hydrogen donor is α, then Np=αHp, where α may be 0.001 to 0.5. That is, the hydrogen concentration may be about one order of magnitude higher than the donor concentration, or may be two or more orders of magnitude higher.

[0074] As described above, the hydrogen concentration distribution has a skirt S from the peak position Ps toward one of the main surfaces (the upper surface 21 in this example). The skirt S refers to the concentration distribution that changes more gradually when comparing the hydrogen concentration distribution in a region shallower than the peak position Ps with the hydrogen concentration distribution in a region deeper than the peak position Ps. In other words, the hydrogen concentration distribution has a skirt S toward the main surface into which the hydrogen ions are implanted. The skirt S may or may not reach the upper surface 21. Also, as shown in the distribution diagram (A), the average doping concentration of the drift region 18 on the shallower side than the high concentration region 26 may be compared with the average doping concentration of the drift region 18 on the deeper side, and it may be determined that the skirt S of the hydrogen concentration distribution exists on the side with the higher average doping concentration.

[0075] The distribution diagram (C) shows the crystal defect density after implanting hydrogen ions or helium ions into the semiconductor substrate 10 and then annealing under predetermined conditions. In the semiconductor device 150 implanted with helium ions, the crystal defect density distribution and the helium concentration distribution have similar shapes. For example, the peak position Dks' of the helium concentration coincides with the peak position Ks' of the crystal defect density.

[0076] Position Z0 is the position where the net doping concentration of the high concentration region 26 is approximately equal to the doping concentration N0 of the semiconductor substrate 10 on the lower surface 23 side of position Ps. On the lower surface 23 side of position Z0, the crystal defect density may be a sufficiently small value Nr0. A sufficiently small crystal defect density Nr0 means that the crystal defect density has a low value to the extent that the carrier lifetime is not shorter than τ0 described below. As an example, the concentration of vacancies or divacancies is Nr0, and Nr0 is 1×10 at a temperature of 300 K. 12 atoms / cm 3 or smaller, 1×10 11 atoms / cm 3 It may be less than 1 x 10 10 atoms / cm 3 At a position J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the crystal defect density may be higher than Nr0.

[0077] The density of crystal defects such as vacancies and complex vacancies caused by implanting helium ions is highest near the position Dks' where the largest number of helium ions are implanted. As described above, in the semiconductor device 150, since there is almost no hydrogen in the substrate, annealing hardly reduces the crystal defects. Therefore, the distribution of the crystal defect density is maintained before and after annealing.

[0078] In contrast, in the semiconductor device 100 into which hydrogen ions are implanted, the crystal defects are terminated by hydrogen, so that the crystal defect density distribution and the hydrogen concentration distribution have different shapes. For example, the hydrogen concentration peak position Ps and the crystal defect density peak position Ks do not coincide. In this example, the crystal defect density peak position Ks is located closer to the upper surface 21 of the semiconductor substrate 10 than the hydrogen concentration peak position Ps. The crystal defect density may monotonically decrease on the upper surface 21 side of the position Ks. The crystal defect density may monotonically decrease more steeply on the lower surface 23 side of the position Ks than on the upper surface 21 side.

[0079] Near the peak position Ps of the hydrogen concentration, a large amount of hydrogen terminates dangling bonds such as vacancies and complex vacancies. Therefore, the crystal defect density near the peak position Ps of the hydrogen concentration is much smaller than the crystal defect density at the peak position Ks of the crystal defect density. In this specification, the width of the distribution showing a concentration greater than 1% of the peak concentration (Hp) is referred to as the 1% full width or FW1%M. The vicinity of the peak position Ps may refer to a region within the 1% full width range centered on the peak position Ps. The position Ks of the peak of the crystal defect density may be located at a position shallower than the 1% full width range centered on the peak position Ps.

[0080] However, the distance D between the peak position Ks of the crystal defect density and the peak position Ps of the hydrogen concentration is determined according to the distance that hydrogen diffuses in the semiconductor substrate 10 by annealing. The distance D may be 40 μm or less, 20 μm or less, or 10 μm or less. The distance D may be 1 μm or more, 3 μm or more, or 5 μm or more. The distance D may be 1% full width or more of the hydrogen concentration. The distance D may be 1% full width or more of the net doping concentration at the position Ps. In this case, the 1% full width of the net doping concentration is the width of the peak at 0.01 Np. The value range of the distance D may be a combination of the upper and lower limits described above. As an example, the crystal defect density distribution can be observed by measuring the density distribution of vacancies and divacancies by positron annihilation.

[0081] The distribution diagram (D) shows the carrier lifetime distribution after implanting hydrogen ions or helium ions into the semiconductor substrate 10 and then annealing under predetermined conditions. In the semiconductor device 150 implanted with helium ions, the carrier lifetime distribution has a shape obtained by inverting the vertical axis of the crystal defect density distribution. For example, the position where the carrier lifetime is at its minimum coincides with the center peak position Ks' of the crystal defect density.

[0082] Similarly, in the semiconductor device 100 implanted with hydrogen ions, the carrier lifetime distribution has a shape obtained by inverting the vertical axis of the crystal defect density distribution. For example, the position where the carrier lifetime is at its minimum coincides with the center peak position Ks of the crystal defect density. In addition, in a region within the range of FW1%M centered on the peak position Ps of the hydrogen concentration, the carrier lifetime of the semiconductor device 100 may be a maximum value τ0. The maximum value τ0 may be the carrier lifetime in the drift region 18 on the lower surface 23 side of the peak position Ps of the hydrogen concentration.

[0083] The carrier lifetime may be a sufficiently large value τ0 on the lower surface 23 side of the position Z0. The carrier lifetime being a sufficiently large value τ0 may be the carrier lifetime in the case where lifetime killers or defects mainly consisting of vacancies or divacancies are not intentionally introduced into the semiconductor substrate 10. At a temperature of 300K, τ0 may be 10 μs or more, and may be 30 μs or more. As an example, τ0 is 10 μs. At a position J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the carrier lifetime may be smaller than τ0.

[0084] The distribution diagram (E) shows the distribution of carrier mobility after implanting hydrogen ions or helium ions into the semiconductor substrate 10 and then annealing under predetermined conditions. On the lower surface 23 side of the position Z0, the carrier mobility may be the mobility μ0 in the case of an ideal crystal structure. As an example, in the case of silicon at a temperature of 300 K, the mobility μ0 is 1360 cm for electrons. 2 / (Vs), hole is 495cm2 At the position J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the carrier mobility may be smaller than μ0.

[0085] The distribution diagram (F) shows the distribution of carrier concentration after annealing under predetermined conditions after implanting hydrogen ions or helium ions into the semiconductor substrate 10. The carrier concentration can be measured by, for example, a spreading resistance measurement method (SR measurement method).

[0086] In the SR measurement method, the spreading resistance is converted to resistivity, and the carrier concentration is calculated from the resistivity. The resistivity is expressed as ρ (Ω cm) and the mobility is expressed as μ (cm 2 / (V s)), the elementary charge q (C), and the carrier concentration N ( / cm 3 ), then N = 1 / (μqρ).

[0087] In the SR measurement method, the value of the carrier mobility when the crystalline state of the semiconductor substrate 10 is ideal is used. However, if damage is left in the semiconductor substrate 10 due to ion implantation, the crystalline state of the semiconductor substrate 10 is broken and becomes disordered, and the mobility is actually reduced. In reality, the reduced mobility should be used as the mobility in the SR measurement, but it is difficult to measure the reduced mobility value. For this reason, the ideal value is used as the mobility in the SR measurement of the example of distribution diagram (F). Therefore, the denominator of the above-mentioned carrier concentration formula becomes large, and the carrier concentration decreases. That is, in the distribution diagram (F), the measured carrier concentration is generally reduced in the region through which the hydrogen ions have passed (the region from the lower end of the anode region 14 of the semiconductor substrate 10 to the high concentration region 26). However, in the high concentration region 26 near the range Rp of the hydrogen ions, the hydrogen concentration is high, so the disordered state is alleviated by the hydrogen termination effect, and the mobility approaches the value of the crystalline state. Furthermore, hydrogen donors are also formed. Therefore, the carrier concentration is higher than the carrier concentration N0 of the semiconductor substrate 10.

[0088] In the semiconductor device 150 implanted with helium ions, the carrier concentration is small in a narrow region near the peak position Ks' of the helium concentration (i.e., near the peak position of the crystal defect density). When helium ions are implanted into the semiconductor substrate 10 to form crystal defects, the peak position of the helium concentration, the position where the carrier concentration shows a minimum, the peak position of the crystal defect density, and the position where the carrier lifetime shows a minimum all coincide with the position Ks'.

[0089] Even when hydrogen ions are implanted into the semiconductor substrate 10 to form crystal defects, the hydrogen concentration peak position Ps and the crystal defect density peak position often coincide before annealing. However, when annealing is performed after hydrogen ion implantation, hydrogen diffuses from the hydrogen concentration peak position toward the upper surface 21 of the semiconductor substrate 10, and hydrogen terminates the dangling bonds contained in the vacancies and divacancies. Therefore, the crystal defect density after annealing decreases around the hydrogen concentration peak position Ps. Therefore, the carrier lifetime in the vicinity of the hydrogen concentration peak position Ps increases and becomes approximately τ0.

[0090] The lifetime control region (upper surface side lifetime control region 74 in this example) may be a region where the carrier concentration is lower than the carrier concentration N0 of the semiconductor substrate 10 as shown in distribution diagram (F) on the main surface side (upper surface 21 side in this example) where the hydrogen concentration shows a base from the peak as shown in distribution diagram (B). Alternatively, the lifetime control region may be a region where the vacancy / divacancy density is higher on the upper surface 21 side of the peak position Ps than on the lower surface 23 side by measuring the density distribution of vacancies / divacancies as shown in distribution diagram (C). Alternatively, the lifetime control region may be a region having a width (FW1%M) between two positions where the vacancy / divacancy density distribution is 1% of the maximum value, sandwiching the maximum value position Ks. Alternatively, the lifetime control region may be simply the position Ks where the crystal defect density peaks as described above.

[0091] 4 is a diagram showing another example of a cross section of the semiconductor device 100 according to this embodiment. The semiconductor device 100 of this embodiment differs from the semiconductor device 100 shown in FIG. 1B in that hydrogen ions are implanted from the lower surface 23 side, the high concentration region 26 is provided on the lower surface 23 side, and the crystal defect region 19-2 is provided on the lower surface 23 side. The lower surface 23 side refers to a region on the lower surface 23 side of the center of the semiconductor substrate 10 in the Z-axis direction.

[0092] In the semiconductor device 100 of this example, the hydrogen concentration distribution in the depth direction of the semiconductor substrate 10 has a peak at a first position Pb that is a predetermined distance Dpb away from one main surface (lower surface 23 in this example) of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In Fig. 4, the peak of the hydrogen concentration distribution at the first position Pb is indicated by an "x" symbol (marker). The first position Pb may be located closer to the lower surface 23 than 1 / 2 of the thickness T of the semiconductor substrate.

[0093] The hydrogen concentration distribution in the depth direction of the semiconductor substrate 10 has a base S (see FIG. 3) of the concentration distribution that is lower than the peak concentration, located closer to the lower surface 23 than the first position Pb. In the Z-axis direction, the first position Pb may be located lower than the first position Ps.

[0094] In the semiconductor device 100 of this example, the semiconductor substrate 10 may have a high concentration region 26 between the drift region 18 and the lower surface 23 of the semiconductor substrate 10, the high concentration region 26 having a doping concentration higher than that of the drift region 18. The high concentration region 26 is provided to include the first position Pb. The high concentration region 26 of this example may be a region formed by annealing the semiconductor substrate 10 into which hydrogen ions have been implanted from the lower surface 23. By annealing the semiconductor substrate 10 after implanting the hydrogen ions, hydrogen becomes donors, and the high concentration region 26 having a doping concentration higher than that of the drift region 18 is formed.

[0095] In the semiconductor device 100 of this example, the high concentration region 26 is provided so as to be sandwiched between the drift regions 18 in the Z-axis direction. Since the high concentration region 26 has a doping concentration higher than that of the drift region 18, the depletion layer spreading from the lower surface side of the anode region 14 can be prevented from reaching the cathode region 82.

[0096] A crystal defect region 19-2 is provided below the high concentration region 26. The crystal defect region 19-2 may be a region including crystal defects formed by implanting hydrogen ions from the lower surface 23. In Fig. 4, the range in the Z-axis direction where the crystal defect region 19-2 is provided is indicated by a double-headed arrow.

[0097] The crystal defect region 19-2 has a center peak of crystal defect density at a position Kb that is a distance Dkb away in the Z-axis direction from the lower surface 23. The crystal defect region 19-2 may be provided from the position Kb to the lower surface 23.

[0098] In this example, the peak of the crystal defect density in the crystal defect region 19-2 in the Z-axis direction is the center peak. The position of the center peak in the Z-axis direction is the position Kb. As described in FIG. 3, when hydrogen ions are implanted to form crystal defects, the peak position of the crystal defect density is located on the main surface (lower surface 23 in this example) side into which the hydrogen ions are implanted, compared to the peak position of the hydrogen concentration. Therefore, position Kb is set at a position shallower than the first position Pb, which is the peak position of the doping concentration of the high concentration region 26, with the lower surface 23 as the reference. In other words, the distance Dkb is smaller than the distance Dpb. In FIG. 4, the center peak of the crystal defect density at position Kb is indicated by a "+" symbol (marker).

[0099] In the semiconductor device 100 of this embodiment, the carrier lifetime is controlled by crystal defects generated by hydrogen ion implantation. In the semiconductor device 100 of this embodiment, the center peak of the crystal defect density in the crystal defect region 19-2 may be set as the lower surface-side lifetime control region 78. The lower surface-side lifetime control region 78 has a higher crystal defect density than other regions of the semiconductor substrate 10.

[0100] FIG. 5 is a diagram showing another example of a cross section of the semiconductor device 100 according to the present embodiment. In the semiconductor device 100 of this embodiment, in addition to the configuration of the semiconductor device 100 shown in FIG. 1B, a buffer region 20 of a first conductivity type having a higher doping concentration than the drift region 18 is provided below the drift region 18. The buffer region 20 of this embodiment is an N+ type, for example. The buffer region 20 may be provided between the drift region 18 and the lower surface 23 in the Z-axis direction. In this embodiment, the buffer region 20 is provided in contact with the drift region 18. The buffer region 20 can function as a field stop region that prevents a depletion layer spreading from the lower surface side of the anode region 14 from reaching the cathode region 82.

[0101] In the semiconductor device 100 of this example, the hydrogen concentration distribution has peaks at multiple positions in the buffer region 20. That is, from the upper surface side to the lower surface side of the buffer region 20, the hydrogen concentration distribution has peaks at four positions, namely, positions Pb4, Pb3, Pb2, and Pb1. In FIG. 5, the hydrogen concentration distribution peaks at multiple positions in the Z-axis direction are indicated by "x" symbols (markers). The buffer region 20 of this example may be a region formed by implanting hydrogen ions into the semiconductor substrate 10 from the lower surface 23 to positions Pb4, Pb3, Pb2, and Pb1, and then annealing the semiconductor substrate 10.

[0102] The semiconductor device 100 of this example is provided with a plurality of crystal defect regions 19. A crystal defect region 19-1 is provided on the upper surface 21 side of the semiconductor substrate 10, and a crystal defect region 19-2 is provided on the lower surface 23 side.

[0103] Crystal defect region 19-1 is a region containing crystal defects formed by implanting hydrogen ions from upper surface 21. Crystal defect region 19-1 is similar to crystal defect region 19-1 shown in FIG. 1B. Crystal defect region 19-2 is a region containing crystal defects formed by implanting hydrogen ions or helium ions from lower surface 23. Crystal defect region 19-2 is not an essential component and may be provided as necessary. Crystal defect region 19-2 may be provided inside buffer region 20. In FIG. 5, the ranges in the Z-axis direction in which crystal defect region 19-1 is provided are indicated by double-headed arrows.

[0104] The crystal defect region 19-2 may have a center peak of crystal defect density between a plurality of peaks of hydrogen concentration in the depth direction of the semiconductor substrate 10. That is, the crystal defect region 19-2 may have a center peak of crystal defect density in any of the following positions Pb1 and Pb2, Pb2 and Pb3, and Pb3 and Pb4 in the Z-axis direction, which are the peak positions of hydrogen concentration in the buffer region 20. The entire crystal defect region 19-2 may be provided between any of the peak positions of hydrogen concentration. The crystal defect region 19-2 of this example shows an example having a center peak of crystal defect density at a position Kb between the positions Pb1 and Pb2. In FIG. 5, the center peak of crystal defect density between the positions Pb1 and Pb2 is indicated by a "+" symbol (marker).

[0105] In the semiconductor device 100 of this embodiment, the carrier lifetime is controlled by crystal defects generated by hydrogen ion implantation. In the semiconductor device 100 of this embodiment, the center peak of the crystal defect density in the crystal defect region 19-2 is set as the lower surface side lifetime control region 78.

[0106] Crystal defect region 19-2 in this example includes crystal defects formed when hydrogen ions or helium ions are implanted at position Pb2 from lower surface 23. As described in FIG. 3, when crystal defects are formed by implanting hydrogen ions, the peak position of the crystal defect density is located on the main surface side into which the hydrogen ions are implanted, compared to the peak position of the hydrogen concentration.

[0107] Fig. 6 is a diagram showing another example of a cross section of the semiconductor device 100 according to the present embodiment. The semiconductor device 100 shown in Fig. 6 differs from the semiconductor device 100 shown in Fig. 5 in that the lower surface-side lifetime control region 78 is provided below the position Pb1 in the Z-axis direction. The crystal defect region 19-2 may be provided up to the lower surface 23 of the semiconductor substrate 10.

[0108] The position in the Z-axis direction of the lower surface-side lifetime control region 78 can be adjusted by adjusting the order of the step (process) of implanting hydrogen ions into a plurality of positions in the Z-axis direction and the step of annealing the hydrogen ion-implanted semiconductor substrate 10. The hydrogen ion implantation step and the annealing step will be described later.

[0109] Fig. 7A shows distribution diagrams of the net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along line c-c' in the semiconductor device 100 according to the embodiment shown in Fig. 5. The vertical and horizontal axes in each distribution diagram are the same as those in the corresponding distribution diagrams shown in Fig. 3.

[0110] The distribution diagram (A) shows the net doping concentration distribution of electrically activated donors and acceptors. As shown in FIG. 5, the buffer region 20 has doping concentration peaks (donor peaks) at multiple positions Pb4, Pb3, Pb2, and Pb1. The high concentration region 26 also has a doping concentration peak (donor peak) at position Ps. The doping concentration between each donor peak may be higher than the doping concentration N0 of the semiconductor substrate 10 or may be the same concentration. In this example, the doping concentration of at least a part of the region between positions Ps and Pb4 is the doping concentration N0. The dopant of the semiconductor substrate 10 may be phosphorus or the like. The doping concentration N0 may be N0 described in the distribution diagram (A) of FIG. 3.

[0111] In the distribution diagram (A), an N-type region having a doping concentration higher than that of the drift region 18 is defined as N+ type. The doping concentration of at least a part of the drift region 18 between the position Ps and the position Pb4 may be lower than the doping concentration of the drift region 18 on the upper surface 21 side of the position Ps. Hydrogen ions implanted from the upper surface 21 of the semiconductor substrate 10 pass through the drift region 18 on the upper surface 21 side. Therefore, the doping concentration of the drift region 18 may be higher than the doping concentration N0 of the semiconductor substrate 10 due to the remaining hydrogen donors. The average doping concentration of the drift region 18 on the upper surface 21 side may be three times or less the doping concentration N0 of the semiconductor substrate 10.

[0112] Hydrogen ions are implanted at positions Pb4, Pb3, Pb2, and Pb1 from the lower surface 23 of the semiconductor substrate 10. Therefore, the doping concentration of the region on the lower surface 23 side from position Pb4 may be higher than the doping concentration N0 of the semiconductor substrate 10 as a whole. That is, the doping concentration (donor concentration in this example) of the drift region 18 in the region sandwiched in the depth direction between two hydrogen donor peaks (hydrogen donor peaks at positions Ps and Pb4 in this example) is the lowest. The doping concentration (donor concentration in this example) of the region sandwiched between these two hydrogen donor peaks is the doping concentration N0 of the semiconductor substrate 10, and the doping concentration distribution may be approximately flat. And, at the two hydrogen donor peaks, the doping concentration from position Ps to the upper surface 21 side and from position Pb4 to the lower surface 23 side may be higher than the doping concentration N0 of the semiconductor substrate 10. The cathode region 82 in this example is formed by implanting and diffusing phosphorus.

[0113] The distribution diagram (B) shows the chemical concentration of the implanted hydrogen. Each peak of the hydrogen concentration has a base on the main surface side where the hydrogen ions are implanted. In this example, the hydrogen concentration peak at position Ps has a base S on the upper surface 21 side. That is, the hydrogen concentration distribution in this example gradually and monotonically decreases on the upper surface 21 side from the first position Ps to the upper surface 21. The base S may be provided across the drift region 18 and the anode region 14.

[0114] The hydrogen concentration distribution in this example has a base where the change in concentration distribution is steeper from the first position Ps to the lower surface 23 side than the base S. That is, the hydrogen distribution is asymmetric on the upper surface 21 side and the lower surface 23 side of the first position Ps.

[0115] Furthermore, each of the hydrogen concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 has a base S' on the lower surface 23 side. Each of the hydrogen concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 has a base on the upper surface 21 side where the change in concentration distribution is steeper than base S'. That is, each of the hydrogen concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 shows an asymmetric distribution on the upper surface 21 side and the lower surface 23 side of the corresponding positions Pb4, Pb3, Pb2, and Pb1.

[0116] The hydrogen concentration may be minimum between the position closest to the lower surface 23 among the positions where hydrogen ions are implanted from the upper surface 21 side (position Ps in this example) and the position closest to the upper surface 21 among the positions where hydrogen ions are implanted from the lower surface 23 side (position Pb4 in this example). The position where the hydrogen concentration is minimum is the position where the sum of the distribution of hydrogen implanted at position Ps and the distribution of hydrogen implanted at position Pb4 is minimum. Alternatively, the position where the hydrogen concentration is minimum may be sandwiched between two hydrogen donor peaks (positions Ps and Pb4 in this example) and in a region of a substantially flat doping concentration distribution where the doping concentration indicates the doping concentration N0 of the semiconductor substrate 10.

[0117] The distribution diagram (C) shows the crystal defect density after hydrogen ions are implanted into the semiconductor substrate 10 and then annealed under predetermined conditions. The distribution of the crystal defect density on the upper surface 21 side of the position Ps is similar to the distribution of the crystal defect density of the semiconductor device 100 shown in the distribution diagram (C) of FIG. 3. The crystal defect density Nr0 may be the Nr0 described in the distribution diagram (C) of FIG. 3. The crystal defect density has a peak at a position Ks on the upper surface 21 side of the position Ps. The crystal defect density may decrease monotonically on the upper surface 21 side of the position Ks. The crystal defect density may decrease monotonically and more steeply on the lower surface 23 side of the position Ks than on the upper surface 21 side.

[0118] The crystal defect density in the vicinity of the peak position Ps of the hydrogen concentration is much smaller than the crystal defect density at the peak position Ks of the crystal defect density. The peak position Ks of the crystal defect density may be located at a position shallower than the range of 1% full width centered on the peak position Ps. The distance D between the peak position Ks of the crystal defect density and the peak position Ps of the hydrogen concentration may be 40 nm or less, or may be 20 nm or less. The distance D may be 5 μm or more and 10 μm or less. The distance D may be 1% full width or more of the hydrogen concentration. The distance D may be 1% full width or more of the net doping concentration at the position Ps. In this case, the 1% full width of the net doping concentration is the width of the peak at 0.01 Np.

[0119] In this example, a peak in crystal defect density is located at position Kb between positions Pb2 and Pb1. The peak in crystal defect density at position Kb mainly includes crystal defects formed when hydrogen ions are implanted from the lower surface 23 to position Pb2. In this example, no peak in crystal defect density is provided on the lower surface 23 side of position Pb4 other than at position Kb.

[0120] For example, hydrogen ions are implanted at positions Pb4, Pb3, and Pb1, and the semiconductor substrate 10 is annealed under a first condition. As a result, peaks of the hydrogen concentration distribution are formed at positions Pb4, Pb3, and Pb1. Thereafter, hydrogen ions are implanted at positions Ps and Pb2, and the semiconductor substrate 10 is annealed under a second condition. The second condition has an annealing temperature lower than that of the first condition. Most of the crystal defects caused by the implantation of hydrogen ions at positions Pb4, Pb3, and Pb1 are terminated by annealing at a relatively high temperature. In contrast, the crystal defects caused by the implantation of hydrogen ions at positions Ps and Pb2 are terminated in the vicinity of positions Ps and Pb2 by annealing at a relatively low temperature. Since a lot of hydrogen is also present in the vicinity of position Pb1, the crystal defects caused by the implantation of hydrogen ions at position Pb2 are also terminated in the vicinity of position Pb1 at a high rate. Therefore, the crystal defect density has a peak between the position Pb2 and the position Pb1.

[0121] In this example, the hydrogen concentration peak at position Ps is not located on the side where the hydrogen ions are implanted (the upper surface 21 side in this example). On the other hand, the hydrogen concentration peak at position Pb2 is located on the side where the hydrogen ions are implanted (the lower surface 23 side in this example) on which another hydrogen concentration peak (position Pb1) is located. The integral value of the crystal defect density on the upper surface 21 side of position Ps may be greater than the integral value of the crystal defect density on the lower surface 23 side of position Pb2.

[0122] The distribution diagram (D) shows the carrier lifetime distribution after implanting hydrogen ions into the semiconductor substrate 10 and annealing it under a predetermined condition. The carrier lifetime distribution has a shape obtained by inverting the vertical axis of the crystal defect density distribution. The carrier lifetime τ0 may be the τ0 described in the distribution diagram (D) of FIG. 3. For example, the position where the carrier lifetime is the minimum value coincides with the center peak position Ks of the crystal defect density. Also, the position where the carrier lifetime is the minimum value coincides with the center peak position Kb of the crystal defect density. As with the distribution diagram (D) of FIG. 3, in the region within the range of FW1%M centered on each peak position Ps, Pb4, Pb3, Pb2, and Pb1 of the hydrogen concentration, the carrier lifetime of the semiconductor device 100 may be the maximum value τ0.

[0123] The distribution diagram (E) shows the distribution of carrier mobility after implanting hydrogen ions into the semiconductor substrate 10 and then annealing under a predetermined condition. The carrier mobility μ0 may be μ0 described in the distribution diagram (E) of FIG. 3. For example, the position where the carrier mobility is at a minimum coincides with the center peak position Ks of the crystal defect density. Also, the position where the carrier mobility is at a minimum coincides with the center peak position Kb of the crystal defect density. As in the distribution diagram (E) of FIG. 3, in the region within the range of FW1%M centered on each of the peak positions Ps, Pb4, Pb3, Pb2, and Pb1 of the hydrogen concentration, the carrier mobility of the semiconductor device 100 may be the maximum value μ0.

[0124] The distribution diagram (F) shows the distribution of carrier concentration after hydrogen ions are implanted into the semiconductor substrate 10 and then annealed under predetermined conditions. As with the distribution diagram (F) in Fig. 3, the measured carrier concentration is generally lower in the region through which the hydrogen ions have passed (the region from the lower end of the anode region 14 of the semiconductor substrate 10 to the vicinity of the position Ps). However, the hydrogen concentration is generally higher in the region on the lower surface 23 side of the position Pb4, and therefore the carrier concentration is higher than the substrate concentration N0.

[0125] In the semiconductor device 100 of this example, the crystal defect density after annealing decreases around the hydrogen concentration peak position Ps. Therefore, the carrier lifetime in the vicinity of the hydrogen concentration peak position Ps increases and becomes approximately τ0.

[0126] Fig. 7B shows distribution diagrams of the net doping concentration (A), hydrogen concentration and helium concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) when the crystal defect region 19-2 on the lower surface 23 side is formed by implanting helium ions. This is the same as the example of Fig. 7A, except that the crystal defect region 19-2 on the lower surface 23 side is formed by implanting helium ions. The distributions of the net doping concentration (A) and carrier concentration (F) are the same as the example of Fig. 7A.

[0127] The distribution diagram (B) shows the distribution of chemical hydrogen and helium concentrations. The distribution of hydrogen concentration is the same as that in FIG. 7A. However, in this example, helium is distributed inside the buffer region 20. In this example, the peak of the helium concentration is located on the lower surface 23 side of the position Pb1.

[0128] The helium concentration peak may be located between adjacent hydrogen concentration peaks. That is, the helium concentration peak may be located between Pb4 and Pb3, between Pb3 and Pb2, or between Pb2 and Pb1. As an example, the helium concentration peak shown by the dashed line in the distribution diagram (B) is located between Pb2 and Pb1. Helium may be introduced in either one of the solid line distribution having a peak on the lower surface 23 side of Pb1 and the dashed line distribution having a peak between Pb2 and Pb1, or in both distributions.

[0129] The distribution diagram (C) shows the crystal defect density after annealing under a predetermined condition after implanting hydrogen ions and helium ions into the semiconductor substrate 10. The crystal defect density distribution in the crystal defect region 19-1 formed by implanting hydrogen ions is the same as the crystal defect density distribution of the crystal defect region 19-1 in the distribution diagram (C) of FIG. 7A. The crystal defect region 19-2a shown by the broken line in the distribution diagram (C) is a crystal defect region when helium is implanted at the position shown by the solid line in the distribution diagram (B). The crystal defect region 19-2b is a crystal defect region when helium is implanted at the position shown by the broken line in the distribution diagram (B). In the distribution diagrams (D) and (E), the distribution corresponding to the crystal defect region 19-2a is shown by the solid line, and the distribution corresponding to the crystal defect region 19-2b is shown by the broken line. The crystal defect density distribution of the crystal defect regions 19-2a and 19-2b formed by implanting helium ions has a shape similar to that of the helium concentration distribution. For example, the peak position of the crystal defect density and the peak position of the helium concentration coincide with each other.

[0130] The distribution diagram (D) shows the carrier lifetime distribution after annealing under predetermined conditions after implanting hydrogen ions and helium ions into the semiconductor substrate 10. The carrier lifetime distribution has a shape obtained by inverting the vertical axis of the crystal defect density distribution.

[0131] Distribution diagram (E) shows the distribution of carrier mobility after hydrogen ions and helium ions are implanted into the semiconductor substrate 10 and then annealed under predetermined conditions.

[0132] In the semiconductor substrate 10, hydrogen is present in a large amount in the buffer region 20 and in a region closer to the lower surface 23 than the buffer region 20. Therefore, dangling bonds are likely to be terminated, and it may be difficult to form the crystal defect region 19. In contrast, by forming the crystal defect region 19-2 by implanting helium ions, which have a larger mass than hydrogen ions, crystal defects such as vacancies and complex vacancies are likely to be formed. As a result, even if the crystal defects are terminated by annealing, crystal defects of a certain density can be left in the buffer region 20 and in the lower surface 23 than the buffer region 20. By providing the crystal defect region 19 in the buffer region 20, etc., the tail current can be precisely controlled during the end period of switching, such as turn-off or reverse recovery, of the semiconductor device 100.

[0133] FIG. 7C shows another example of distribution diagrams of net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F). The vertical and horizontal axes in each distribution diagram are the same as those in the corresponding distribution diagrams shown in FIG. 3. In this example, the crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) in the anode region 14 (base region 17 in which a channel is formed in the transistor section 70 described later) and the crystal defect region 19-1 are different from those in the examples of FIG. 7A and FIG. 7B. The distributions at other positions are the same as those in any of the examples of FIG. 7A and FIG. 7B.

[0134] In this example, the distributions of the crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) each have a peak in the crystal defect region 19-1. The peak of the crystal defect density distribution has a foot SV1 on the upper surface 21 side of the center peak position Ks, and a foot SV2 on the lower surface 23 side that is steeper than the foot SV1. The peak of the carrier lifetime distribution has a foot Sτ1 on the upper surface 21 side of the center peak position Ks, and a foot Sτ2 on the lower surface 23 side that is steeper than the foot Sτ1. The peak of the carrier mobility distribution has a foot Sμ1 on the upper surface 21 side of the center peak position Ks, and a foot Sμ2 on the lower surface 23 side that is steeper than the foot Sμ1. The peak of the carrier concentration distribution has a foot SN1 on the upper surface 21 side of the center peak position Ks, and a foot SN2 on the lower surface 23 side that is steeper than the foot SN1.

[0135] Each tail may be a portion from the apex of the peak to a predetermined reference value in each distribution. The reference value may be the minimum value Nr0 in the drift region 18 for the crystal defect density, the maximum value τ0 in the drift region for the carrier lifetime, the maximum value μ0 in the drift region 18 for the carrier mobility, and the minimum value N0 between the hydrogen concentration peak position Ps and the buffer region 20 for the carrier concentration. In this specification, "same" may include a case where there is an error of 10% or less.

[0136] In this example, the tails SV1, Sτ1, Sμ1, and SN1 do not reach the anode region 14 (the base region 17 in the transistor section 70). That is, the crystal defect density, carrier lifetime, carrier mobility, and carrier concentration of the anode region 14 and the base region 17 are the same as the above-mentioned reference values ​​Nr0, τ0, μ0, and N0. This reduces the effect of forming crystal defects on the anode region 14 and the base region 17. In particular, the fluctuation of the gate threshold is suppressed. The gate threshold is determined by the position of the peak concentration of the base region 17. If the crystal defect density at the peak position of the base region 17 is higher than Nr0, the interface state that affects the gate threshold may increase, and the gate threshold may change. By setting the crystal defect density at the peak position of the base region 17 to Nr0, the effect on the gate threshold can be minimized. For example, by adjusting the hydrogen ion implantation position and the annealing conditions after hydrogen ion implantation, it is possible to control so that each tail does not reach the anode region 14 and the base region 17.

[0137] FIG. 7D shows another example of distribution diagrams of net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F). The vertical and horizontal axes in each distribution diagram are the same as those in the corresponding distribution diagrams shown in FIG. 3. In this example, the crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) in the anode region 14 (base region 17 in the transistor section 70) and the crystal defect region 19-1 are different from those in the example of FIG. 7C. The distributions at other positions are the same as those in the example of FIG. 7C.

[0138] In this example, at least one of the tails SV1, Sτ1, Sμ1, and SN1 reaches the anode region 14 or the base region 17. However, the crystal defect density, carrier lifetime, carrier mobility, and carrier concentration in the anode region 14 and the base region 17 are sufficiently close to the above-mentioned reference values ​​Nr0, τ0, μ0, and N0.

[0139] In this example, the crystal defect density, carrier lifetime, carrier mobility, and carrier concentration at the center peak position Ks are Nrp, τp, μp, and Np. The crystal defect density, carrier lifetime, carrier mobility, and carrier concentration in the anode region 14 or the base region 17 are Nrb, τb, μb, and Nb. The crystal defect density Nrb, carrier lifetime τb, carrier mobility μb, and carrier concentration Nb may be values ​​at the position of the PN junction between the anode region 14 or the base region 17 and an N-type region such as the drift region 18. Note that the carrier concentration Nb may be the maximum value of the carrier concentration in the N-type region in contact with the PN junction.

[0140] The crystal defect density Nrb, carrier lifetime τb, carrier mobility μb, and carrier concentration Nb may be half or less, ¼ or less, 1 / 10 or less, or 1 / 100 or less of the crystal defect density Nrp, carrier lifetime τp, carrier mobility μp, and carrier concentration Np at the center peak position Ks. This can reduce the effect of the formation of crystal defects on the anode region 14 and the base region 17.

[0141] FIG. 8A is a diagram partially illustrating an example of the upper surface of the semiconductor device 200 according to this embodiment. The semiconductor device 200 of this embodiment is a semiconductor chip including a transistor section 70 and a diode section 80 provided adjacent to the transistor section 70. The upper surface of the semiconductor device 200 may be the same as the upper surface of the semiconductor device 100 illustrated in FIG. 1A. The transistor section 70 includes a transistor such as an IGBT. The boundary section 90 is a region of the transistor section 70 adjacent to the diode section 80. The diode section 80 includes a diode such as a free wheel diode (FWD) on the upper surface of the semiconductor substrate 10. FIG. 8A shows the upper surface of the chip around the chip end, and other regions are omitted.

[0142] 8A shows an active region of semiconductor substrate 10 in semiconductor device 200, but semiconductor device 200 may have an edge termination structure surrounding the active region. The active region refers to a region through which current flows when semiconductor device 200 is controlled to be in the on state. The edge termination structure relieves electric field concentration on top surface 21 of semiconductor substrate 10. The edge termination structure has, for example, a guard ring, a field plate, a resurf, or a structure combining these.

[0143] The semiconductor device 200 of this example is provided inside the semiconductor substrate 10 and includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 17, and a contact region 15 that are exposed on the upper surface of the semiconductor substrate 10. The semiconductor device 200 of this example also includes an emitter electrode 52 and a gate metal layer 50 that are provided above the upper surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0144] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the upper surface 21 of the semiconductor substrate 10, but is omitted in Fig. 8A. In the interlayer insulating film of this example, a contact hole 56, a contact hole 49, and a contact hole 54 are provided so as to penetrate the interlayer insulating film.

[0145] Moreover, the emitter electrode 52 is connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. An insulating film such as an oxide film is provided between the connection portion 25 and the upper surface 21 of the semiconductor substrate 10.

[0146] The gate metal layer 50 contacts the gate runner 48 through the contact hole 49. The gate runner 48 is formed of polysilicon doped with impurities or the like. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface 21 of the semiconductor substrate 10. The gate runner 48 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0147] The gate runner 48 of this example is formed from below the contact hole 49 to the tip of the gate trench portion 40. Between the gate runner 48 and the upper surface 21 of the semiconductor substrate 10, an insulating film such as an oxide film is formed.

[0148] At the tip of the gate trench portion 40, the gate conductive portion is exposed at the upper surface 21 of the semiconductor substrate 10. The gate trench portion 40 contacts the gate runner 48 at the exposed portion of the gate conductive portion.

[0149] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of aluminum or an aluminum-silicon alloy.

[0150] At least a portion of the gate metal layer 50 may be made of aluminum or an aluminum-silicon alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium, a titanium compound, or the like under the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 may also have a plug made of tungsten or the like in the contact hole.

[0151] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged at a predetermined interval along a predetermined arrangement direction (Y-axis direction in this example). The gate trench portion 40 in this example may have two extension portions 39 extending along an extension direction (X-axis direction in this example) parallel to the upper surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 41 connecting the two extension portions 39. At least a part of the connection portion 41 is preferably formed in a curved shape. By connecting the ends of the two extension portions 39 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 39. In this specification, each extension portion 39 of the gate trench portion 40 may be treated as one gate trench portion 40. The gate runner 48 may be connected to the gate conductive portion at the connection portion 41 of the gate trench portion 40.

[0152] The dummy trench portion 30 of this example may have a U-shape on the upper surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 of this example may have two extension portions 29 extending along the extension direction and a connection portion 31 connecting the two extension portions 29.

[0153] The emitter electrode 52 is formed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 17, and the contact region 15. The well region 11 is of the second conductivity type. The well region 11 is of the P+ type, for example. The well region 11 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 11. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 11.

[0154] In a plane parallel to the upper surface 21 of the semiconductor substrate 10, a mesa portion is provided adjacent to each trench portion in the Y-axis direction. A mesa portion is a portion of the semiconductor substrate sandwiched between two adjacent trench portions. The mesa portion may be a portion from the upper surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The region sandwiched between the extension portions of two adjacent trench portions may be defined as a mesa portion.

[0155] In the transistor section 70, a first mesa section 60 is provided adjacent to each trench section. In a boundary section 90 which is a boundary between the diode section 80 and the transistor section 70, a second mesa section 62 is provided in a region sandwiched between adjacent dummy trench sections 30. In the diode section 80, a third mesa section 64 is provided in a region sandwiched between adjacent dummy trench sections 30.

[0156] At both ends in the X-axis direction of the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64, as an example, a second conductivity type base region 17 is provided so as to be exposed on the upper surface 21 of the semiconductor substrate 10. In this example, the base region 17 is, as an example, a P-type. Note that FIG. 8A shows only one end of the base region 17 in the X-axis direction.

[0157] An emitter region 12 is provided on the upper surface of the first mesa portion 60 in contact with the gate trench portion 40. The emitter region 12 may be provided in the Y-axis direction from one of two trench portions extending in the X-axis direction to the other, sandwiching the first mesa portion 60. The emitter region 12 is also provided below the contact hole 54.

[0158] The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is provided in contact with the dummy trench portion 30. The emitter region 12 in this example is of a first conductivity type. As an example, the emitter region 12 in this example is of an N+ type.

[0159] A contact region 15 of a second conductivity type having a higher doping concentration than the base region 17 is provided on the upper surface of the first mesa portion 60. The contact region 15 in this example is P+ type, for example. In the first mesa portion 60, the emitter region 12 and the contact region 15 may be provided alternately in the extension direction of the gate trench portion 40. The contact region 15 may be provided in the Y-axis direction from one to the other of two trench portions extending in the X-axis direction with the first mesa portion 60 in between. The contact region 15 is also provided below the contact hole 54.

[0160] The contact region 15 may or may not be in contact with the gate trench portion 40. In addition, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is provided in contact with the dummy trench portion 30 and the gate trench portion 40.

[0161] A contact region 15 is provided on the upper surface of the second mesa portion 62. The area of ​​the contact region 15 provided on the upper surface of one second mesa portion 62 is larger than the area of ​​the contact region 15 provided on the upper surface of one first mesa portion 60. The area of ​​the contact region 15 provided on the upper surface of one second mesa portion 62 may be larger than the area of ​​the contact region 15 provided on the upper surface of one third mesa portion 64. In the second mesa portion 62, the contact region 15 is also provided below the contact hole 54.

[0162] The contact region 15 on the upper surface of the second mesa portion 62 may be provided in the entire region sandwiched between the base regions 17 provided at both ends in the X-axis direction of the second mesa portion 62. The second mesa portion 62 extracts carriers more effectively at the time of turn-off than the first mesa portion 60.

[0163] Contact regions 15 are provided on the upper surface of the third mesa portion 64 at both ends in the X-axis direction. A base region 17 is provided on the upper surface of the third mesa portion 64 in a region sandwiched between the contact regions 15 provided at both ends in the X-axis direction of the third mesa portion 64. The base region 17 may be provided in the entire region sandwiched between the contact regions 15 in the X-axis direction. In the third mesa portion 64, the base region 17 is also provided below the contact hole 54. The contact region 15 may also be provided below the contact hole 54.

[0164] In the third mesa portion 64, the contact region 15 and the base region 17 are formed from one dummy trench portion 30 to the other dummy trench portion 30 that sandwich the third mesa portion 64. That is, on the upper surface of the semiconductor substrate, the width in the Y-axis direction of the third mesa portion 64 is equal to the width in the Y-axis direction of the contact region 15 or the base region 17 provided in the third mesa portion 64.

[0165] The emitter region 12 may or may not be formed in the third mesa portion 64. In this example, the emitter region 12 is not formed in the third mesa portion 64.

[0166] In the semiconductor device 200 of the present example, a dummy trench portion 30 is provided in the diode portion 80. The linear extension portions 29 of adjacent dummy trench portions 30 may be connected by a connection portion 31. The third mesa portion 64 is a region sandwiched between the dummy trench portions 30.

[0167] The diode section 80 has a cathode region 82 of the first conductivity type on the lower surface 23 side of the semiconductor substrate 10. The cathode region 82 in this example is an N+ type, for example. In FIG. 8A, the region in which the cathode region 82 is provided in the top view of the semiconductor substrate 10 is indicated by a dashed line. The diode section 80 may be a region in which the cathode region 82 is projected onto the upper surface 21 of the semiconductor substrate 10. The diode section 80 may also include the entire third mesa section 64 in which the cathode region 82 is partially provided, and the dummy trench section 30 adjacent to the third mesa section 64. The region in which the cathode region 82 is projected onto the upper surface 21 of the semiconductor substrate 10 may be away from the contact region 15 on the positive side in the X-axis direction.

[0168] A collector region of the second conductivity type may be formed in a region of the lower surface 23 of the semiconductor substrate 10 where the cathode region 82 is not formed. The collector region in this example is, for example, a P+ type. The collector region may be formed at a position where the end of the contact hole 54 in the diode section 80 on the negative side in the X-axis direction is projected onto the lower surface 23 of the semiconductor substrate 10.

[0169] In the transistor portion 70 excluding the boundary portion 90, the contact hole 54 is formed above each of the contact region 15 and the emitter region 12. In the first mesa portion 60 excluding the first mesa portion 60 adjacent to the boundary portion 90, the contact hole 54 may be provided so as not to overlap with the gate trench portion 40 and the dummy trench portion 30 extending in the X-axis direction in the top view of FIG. 8A . The width of the contact hole 54 in the Y-axis direction may be smaller than the width of the emitter region 12 and the contact region 15 in the Y-axis direction.

[0170] In the transistor portion 70 excluding the boundary portion 90, the contact hole 54 may be provided continuously from above the contact region 15 provided on the most negative side in the X-axis direction of the first mesa portion 60 to above the contact region 15 provided on the most positive side in the X-axis direction in the top view of the semiconductor substrate 10 shown in Fig. 8A. The contact hole 54 may be provided so as to overlap at least a portion of the contact region 15 provided on the most negative side in the X-axis direction of the first mesa portion 60 in the top view of the semiconductor substrate 10 shown in Fig. 8A. The contact hole 54 may be provided so as to overlap at least a portion of the contact region 15 provided on the most positive side in the X-axis direction of the first mesa portion 60 in the top view of the semiconductor substrate 10 shown in Fig. 8A.

[0171] In the boundary portion 90, the contact hole 54 is formed above the contact region 15. In the second mesa portion 62, the contact hole 54 may be provided so as not to overlap with the dummy trench portion 30 extending in the X-axis direction in the top view of the semiconductor substrate 10 shown in FIG. 8A. The width of the contact hole 54 in the Y-axis direction may be smaller than the width of the contact region 15 in the Y-axis direction.

[0172] In the boundary portion 90, the contact hole 54 may be provided continuously in the X-axis direction above the contact region 15 provided in the second mesa portion 62 in the top view shown in Fig. 8A. The contact hole 54 may be provided so as to overlap at least a portion of the contact region 15 provided in the second mesa portion 62 in the top view shown in Fig. 8A.

[0173] In the diode portion 80, the contact hole 54 is formed above the base region 17 and the contact region 15. In the third mesa portion 64, the contact hole 54 may be provided so as not to overlap with the dummy trench portion 30 extending in the X-axis direction in the top view shown in FIG. 8A. The width of the contact hole 54 in the Y-axis direction may be smaller than the width of the base region 17 and the contact region 15 in the Y-axis direction.

[0174] In the diode section 80, the contact hole 54 may be provided continuously from above the contact region 15 provided on the most negative side in the X-axis direction of the third mesa section 64 to above the contact region 15 provided on the most positive side in the X-axis direction in the top view shown in Fig. 8A. The contact hole 54 may be provided so as to overlap at least a portion of the contact region 15 provided on the negative side in the X-axis direction of the third mesa section 64 in the top view shown in Fig. 8A. The contact hole 54 may be provided so as to overlap at least a portion of the contact region 15 provided on the positive side in the X-axis direction of the third mesa section 64 in the top view shown in Fig. 8A.

[0175] In the transistor section 70, a first conductive type accumulation region 16 may be provided below the base region 17. In this example, the accumulation region 16 is an N+ type, for example. In FIG. 8A, the range in which the accumulation region 16 is formed is indicated by a dashed line. The accumulation region 16 may be formed on the +X-axis direction side from the region where the contact region 15 at the end in the -X-axis direction and the contact hole 54 overlap, when viewed from above the semiconductor substrate. Note that the accumulation region 16 does not have to be provided in the diode section 80, but may be provided.

[0176] The semiconductor device 200 of this example has a crystal defect region 19 inside the semiconductor substrate 10. As shown in FIGS. 1A to 6, the semiconductor device 200 may have one or both of a crystal defect region 19-1 on the upper surface 21 side and a crystal defect region 19-2 on the lower surface 23 side. The semiconductor device 200 of this example has both crystal defect regions 19-1 and 19-2. The crystal defect region 19-2 may be provided in the entirety of the transistor section 70 and the diode section 80. The crystal defect region 19-1 may be provided in the entirety of the diode section 80 and in a part of the transistor section 70.

[0177] In FIG. 8A, the region where the crystal defect region 19-1 is provided is indicated by a dashed line and an arrow. In this example, the crystal defect region 19-1 is disposed in the entire diode portion 80 in the XY plane and in a region in the transistor portion 70 that does not overlap with the gate trench portion 40. The crystal defect region 19-1 may be provided continuously in the Y-axis direction from the diode portion 80 to the first mesa portion 60 adjacent to the gate trench portion 40 closest to the diode portion 80 in the transistor portion 70. In another example, the crystal defect region 19-1 may be disposed discretely in the Y-axis direction in the transistor portion 70 so as not to overlap with each gate trench portion 40.

[0178] Fig. 8B is a diagram partially illustrating another example of the upper surface of the semiconductor device 200. The semiconductor device 200 of this example differs from the example of Fig. 8A in the arrangement of the crystal defect regions 19-1. The other structures are the same as the example of Fig. 8A.

[0179] In the semiconductor device 200 of this example, the crystal defect region 19-1 is arranged to overlap with the gate trench portion 40 of the transistor portion 70. More specifically, among the gate trench portions 40 of the transistor portion 70, one or more gate trench portions 40 arranged closest to the diode portion 80 are arranged to overlap with the crystal defect region 19-1. The crystal defect region 19-1 may be arranged not to overlap with at least the first mesa portion 60 arranged in the center in the Y-axis direction among the gate trench portions 40 of each transistor portion 70.

[0180] Fig. 8C is a diagram partially illustrating another example of the upper surface of the semiconductor device 200. The semiconductor device 200 of this example differs from the example of Fig. 8A in the arrangement of the crystal defect region 19-1 and the cathode region 82. The other structures are the same as the example of Fig. 8A.

[0181] The crystal defect region 19-1 may be provided in a range wider than the cathode region 82 in the X-axis direction and the Y-axis direction. In FIG. 8C, the crystal defect region 19-1 is disposed in the boundary portion 90 and the diode portion 80 in the Y-axis direction, and is not disposed in the transistor portion 70 other than the boundary portion 90. The area of ​​the contact region 15 exposed on the upper surface of one of the second mesa portions 62 in the boundary portion 90 is larger than the area of ​​the contact region 15 exposed on the upper surface of one of the first mesa portions 60 in the transistor portion 70. The second mesa portion 62 may have a configuration in which the emitter region 12 in the first mesa portion 60 is replaced with the contact region 15. The cathode region 82 is provided in at least a part of the diode portion 80 in the Y-axis direction. In this example, the region sandwiched between the transistor portions 70 in the Y-axis direction is the diode portion 80. The cathode region 82 in FIG. 8C is not provided in one or more third mesa portions 64 closest to the boundary portion 90 in the diode portion 80. The cathode region 82 in FIG. 8C is provided in the diode section 80 away from the contact region 15 in the X-axis direction.

[0182] Furthermore, the end of the crystal defect region 19-1 in the X-axis direction is disposed between the end of the cathode region 82 in the X-axis direction and the gate metal layer 50. The end of the crystal defect region 19-1 in the X-axis direction may be disposed between the contact hole 54 and the gate metal layer 50 (crystal defect region 19-1a in FIG. 8C). In another example, the end of the crystal defect region 19-1 in the X-axis direction may be disposed between the dummy trench portion 30 and the gate metal layer 50 (crystal defect region 19-1b in FIG. 8C).

[0183] An end of the crystal defect region 19-1 in the X-axis direction may be located inside the well region 11 in top view (crystal defect region 19-1b in FIG. 8C). The P-type well region 11 has a higher doping concentration than the P-type anode region 14 or the base region 17. By providing the crystal defect region 19-1 in the well region 11 as well, the injection of holes from the well region 11 toward the cathode region 82 can be suppressed.

[0184] The end of the crystal defect region 19-1 in the Y-axis direction may be located in the first mesa portion 60 or the dummy trench portion 30 closer to the diode portion 80 than the gate trench portion 40 provided closest to the diode portion 80 among the gate trench portions 40 of the transistor portion 70 (crystal defect region 19-1c in FIG. 8C). This makes it possible to suppress the injection of holes from the transistor portion 70 toward the cathode region 82 without affecting the gate threshold value.

[0185] The crystal defect region 19-1 is X The crystal defect region 19-1 may extend in the axial direction to the gate runner 48 or the gate metal layer 50. X The end in the axial direction may be in the gate runner 48, may be in the gate metal layer 50, or may be located beyond the gate metal layer 50. This makes it possible to reduce carriers remaining in the gate runner 48 or the gate metal layer 50 and suppress the influence on the switching operation.

[0186] A gate insulating film is formed on the lower surface 23 side of the gate runner 48 or the gate metal layer 50, but this is also a region where an inversion layer channel is not formed. During ion implantation to form the crystal defect region 19-1, the implanted ions are also introduced into or pass through the gate insulating film on the lower surface 23 side of the gate runner 48 or the gate metal layer 50. Therefore, damage may also be formed in the gate insulating film during ion implantation. However, since an inversion layer channel is not formed on the lower surface 23 side of the gate runner 48 or the gate metal layer 50, the effect on the gate threshold is sufficiently small.

[0187] The contact region 15 on the upper surface of the second mesa portion 62 does not have to be provided in the entire region sandwiched between the base regions 17 provided at both ends of the second mesa portion 62 in the X-axis direction. Specifically, the contact region 15 on the upper surface of the second mesa portion 62 may simply cover both ends of the contact hole 54, and the base region 17 may be exposed on the upper surface of the second mesa portion 62 sandwiched between the contact regions 15. On the upper surface of the second mesa portion 62, the area of ​​the exposed base region 17 may be larger than the area of ​​the contact region 15 covering both ends of the contact hole 54, and may be 10 times or more larger. In addition, the configuration may be the same as that of the diode portion 80.

[0188] 8D is a diagram partially illustrating another example of the upper surface of the semiconductor device 200. The semiconductor device 200 of this example differs from the example of FIG. 8C in the arrangement of the cathode region 82 in the Y-axis direction. The other structures are the same as those of the example of FIG. 8C. The position of the end of the crystal defect region 19-1 in the Y-axis direction may be the same as that of the example of FIG. 8C.

[0189] The cathode region 82 in this example is provided over the entire diode portion 80 in the Y-axis direction. In addition, in the Y-axis direction, the crystal defect region 19-1 is provided in a portion of the transistor portion 70 that contacts the diode portion 80. The crystal defect region 19-1 may also be provided in the first mesa portion 60 other than the boundary portion 90. However, the crystal defect region 19-1 is not provided in a predetermined range including the center of the transistor portion 70 in the Y-axis direction. With this configuration, it is possible to suppress carriers from flowing from the cathode region 82 to the upper surface side of the transistor portion 70.

[0190] Fig. 9A is a diagram showing an example of the d-d' cross section in Fig. 8A. The d-d' cross section is a YZ plane passing through the emitter region 12 and the contact region 15 in the transistor section 70 and the diode section 80. In the d-d' cross section, the semiconductor device 200 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and the upper surface of the interlayer insulating film 38.

[0191] The region A corresponds to the semiconductor device 100 shown in Fig. 5. However, the semiconductor device 100 shown in Fig. 5 does not have the dummy trench portion 30 and the interlayer insulating film 38 shown in Fig. 9A. Also, the emitter electrode 52 in Fig. 9A corresponds to the upper surface electrode 53 in Fig. 5.

[0192] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as a metal.

[0193] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0194] The semiconductor substrate 10 includes a drift region 18 of a first conductivity type. In this example, the drift region 18 is an N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 without other doped regions being provided therein.

[0195] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided in the upper surface 21 of the semiconductor substrate 10. Each trench portion is provided from the upper surface 21, penetrating the base region 17, and reaching the drift region 18.

[0196] The gate trench portion 40 has a gate trench provided on the upper surface 21, and a gate insulating film 42 and a gate conductive portion 44 provided in the gate trench. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0197] The gate conductive portion 44 is provided inside the gate trench portion 40 and surrounded by the gate insulating film 42. The gate conductive portion 44 includes at least a region facing the adjacent base region 17 in the depth direction, with the gate insulating film 42 sandwiched therebetween. The gate trench portion 40 in this cross section is covered on the upper surface 21 with the interlayer insulating film 38. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 17 that contacts the gate trench.

[0198] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 side, and a dummy insulating film 32 and a dummy conductive portion 34 provided in the dummy trench. The upper end of the dummy trench may be at the same position as the upper surface 21 in the Z-axis direction. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench portion 30 and surrounded by the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.

[0199] The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0200] In the first mesa portion 60, an accumulation region 16 is provided above the drift region 18 in contact with the gate trench portion 40. When a plurality of accumulation regions 16 are provided, the accumulation regions 16 are arranged side by side in the Z-axis direction. As an example, the accumulation region 16 is an N+ type. The doping concentration of the accumulation region 16 is higher than that of the drift region 18, and the dopant accumulates at a higher concentration than in the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage can be reduced.

[0201] The accumulation region 16 may be in contact with the dummy trench portion 30 in the first mesa portion 60, or may be separated from the dummy trench portion 30. FIG. 9A shows an example in which the accumulation region 16 is provided in contact with the dummy trench portion 30.

[0202] In the first mesa portion 60, a base region 17 of the second conductivity type is provided above the accumulation region 16 in contact with the gate trench portion 40. The base region 17 is, for example, an N-type. In the first mesa portion 60, the base region 17 may be provided in contact with the dummy trench portion 30.

[0203] In the second mesa portion 62 of the boundary portion 90, a second conductivity type base region 17 is provided above the drift region 18 in contact with the dummy trench portion 30. In the third mesa portion 64 of the diode portion 80, a second conductivity type anode region 14 is provided above the drift region 18 in contact with the dummy trench portion 30. The anode region 14 is provided in contact with the upper surface 21.

[0204] In the first mesa portion 60, an emitter region 12 is provided in contact with the upper surface 21 and in contact with the gate trench portion 40 in the dd' cross section. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. In the first mesa portion 60, contact regions 15 are provided on the positive and negative sides in the X-axis direction of the dd' cross section in contact with the upper surface 21 and in contact with the gate trench portion 40.

[0205] In the second mesa portion 62, a contact region 15 is provided on the upper surface 21 adjacent to the dummy trench portion 30. The contact region 15 may be in contact with the dummy trench portion 30 or may be separated from the dummy trench portion 30. FIG. 9A shows an example in which the contact region 15 is provided in contact with the dummy trench portion 30.

[0206] In the transistor section 70, a collector region 22 of a second conductivity type is provided below the drift region 18. In this example, the collector region 22 is a P+ type, for example. The collector region 22 is provided in contact with the lower surface 23. In the diode section 80, a cathode region 82 of a first conductivity type having a doping concentration higher than that of the drift region 18 is provided below the drift region 18. In this example, the cathode region 82 is an N+ type, for example. The cathode region 82 is provided in contact with the lower surface 23.

[0207] In the semiconductor device 200 of this example, the semiconductor substrate 10 may have a buffer region 20 of a first conductivity type having a doping concentration higher than that of the drift region 18 between the drift region 18 and the lower surface 23 of the semiconductor substrate 10. The buffer region 20 is provided to include the first position Ps'. The buffer region of this example is, for example, an N+ type. In this example, the buffer region 20 is provided in contact with the drift region 18.

[0208] The semiconductor device 200 of this example has a region containing hydrogen provided inside the semiconductor substrate 10. In the semiconductor device 200 of this example, the hydrogen concentration distribution in the depth direction of the semiconductor substrate 10 has a peak at a first position Ps that is spaced a predetermined distance Dps from one main surface, i.e., an upper surface 21, of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.

[0209] In FIG. 9A, the peak of the hydrogen concentration distribution at the first position Ps is indicated by an "x" symbol (marker). The first position Ps is located on the upper surface 21 side of ½ of the thickness T of the semiconductor substrate 10. The semiconductor substrate 10 has a high concentration region 26 as a region containing hydrogen implanted at the first position Ps. In the XY plane, the high concentration region 26 is provided in the same range as the crystal defect region 19-1 shown in FIG. 8A. That is, in the XY plane, the high concentration region 26 is provided in the entire diode portion 80 and at least a part of the region of the transistor portion 70 that does not overlap with the gate trench portion 40.

[0210] In the semiconductor device 200 of this example, the hydrogen concentration distribution has peaks at multiple positions in the buffer region 20. That is, the hydrogen concentration distribution has peaks at four positions, positions Pb4, Pb3, Pb2, and Pb1, from the upper surface side to the lower surface side of the buffer region 20. In Fig. 9A, the hydrogen concentration distribution peaks at multiple positions in the Z-axis direction are indicated by "x" symbols (markers).

[0211] In this example, the buffer region 20 may be a region formed by annealing hydrogen implanted into the semiconductor substrate 10 at positions Pb4, Pb3, Pb2, and Pb1 from the lower surface 23. By annealing the semiconductor substrate 10 implanted with hydrogen, the hydrogen becomes donors, and the buffer region 20 having a doping concentration higher than that of the drift region 18 is formed. The formation of the buffer region 20 will be described later.

[0212] The first position Ps may be a peak position of the doping concentration of the high concentration region 26 after annealing the hydrogen-implanted semiconductor substrate 10. After annealing, the doping concentration at the first position Ps is 1×10 14 ( / cm 3 ) or more 1×10 15 ( / cm 3 ) or less.

[0213] In the semiconductor device 200 of this example, the buffer region 20 has a higher doping concentration than the drift region 18. Therefore, the buffer region 20 can function as a field stop region that prevents the depletion layer spreading from the lower surface sides of the anode region 14 and the base region 17 from reaching the cathode region 82 and the collector region 22.

[0214] The semiconductor device 200 of this example is provided with crystal defect regions 19-1 and 19-2. As shown in Fig. 8A, the crystal defect region 19-1 is provided in the entire diode portion 80 and at least a part of the region of the transistor portion 70 that does not overlap with the gate trench portion 40. The crystal defect region 19-2 may be provided in the entire diode portion 80 and the entire transistor portion 70 in the XY plane.

[0215] Fig. 9B is a diagram showing an example of the d-d' cross section in Fig. 8B. The semiconductor device 200 of this example is different from the semiconductor device 200 shown in Fig. 9A in the range in the XY plane in which the crystal defect region 19-1 and the high concentration region 26 are provided. The other structures are the same as those of the example shown in Fig. 9A.

[0216] In this example, the crystal defect region 19-1 and the high concentration region 26 are provided in the entire diode portion 80 and in a part of the transistor portion 70 in the XY plane. In the transistor portion 70, the crystal defect region 19-1 and the high concentration region 26 are provided in a region that is in contact with the diode portion 80 and overlaps with one or more gate trench portions 40.

[0217] Fig. 9C is a diagram showing an example of the d-d' cross section in Fig. 8C. The semiconductor device 200 of this example differs from the semiconductor device 200 shown in Fig. 9A in the range in the XY plane in which the crystal defect region 19-1c and the high concentration region 26 are provided, and in the boundary position between the collector region 22 and the cathode region 82. The other structures are the same as those of the example shown in Fig. 9A.

[0218] 10A is a diagram showing an example of an outline of a method for manufacturing a semiconductor device according to this embodiment. In this example, a crystal defect region 19-1 on the upper surface 21 side is formed by implanting hydrogen ions (protons in this example), and a crystal defect region 19-2 on the lower surface 23 side is formed by implanting helium ions. As an example, as shown in FIG. 10A, the method for manufacturing a semiconductor device of this example includes implanting ions into the lower surface 23 in step S1002 and laser annealing the lower surface 23 in step S1004 before implanting protons in step S1006 and thereafter.

[0219] In step S1002, ions to be implanted into the lower surface 23 are, for example, B (boron) and P (phosphorus). In step S1002, boron and phosphorus are, for example, implanted into a region to be P-type and a region to be N-type on the lower surface 23, respectively.

[0220] In step S1004, the boron and phosphorus implanted in step S1002 are laser annealed. Through step S1004, collector region 22 is formed in the region implanted with boron, and cathode region 82 is formed in the region implanted with phosphorus.

[0221] Subsequently, in step S1006, protons are injected from the lower surface 23. The proton injection in step S1006 may be performed multiple times as shown in steps S1006-1, S1006-2, S1006-3, and S1006-4. In this example, proton injection is performed four times in step S1006. In step S1006, protons are injected into the region where the buffer region 20 is to be formed.

[0222] In step S1008, the semiconductor substrate 10 into which the protons have been implanted is annealed at a second temperature. In this example, the second temperature may be 330° C. or more and 450° C. or less, for example, 370° C. Furthermore, the second temperature may be 350° C. or more and 420° C. or less, or 370° C. or more and 400° C. or less. The annealing time in step S1008 may be 30 minutes or more and 10 hours or less, and is 5 hours in this example. Furthermore, the annealing time in step S1008 may be 1 hour or more and 7 hours or less.

[0223] Next, in step S1010, helium ions are implanted from the lower surface 23. Protons are implanted from the upper surface 21. The helium ions are implanted to a depth where the defect density peak of the crystal defect region 19-2 is to be formed. The protons are implanted to a position deeper than the region where the defect density peak of the crystal defect region 19-1 is to be formed. The protons may be implanted to a depth where the high concentration region 26 is to be formed. Either the implantation of the helium ions or the implantation of the protons may be performed first.

[0224] In step S1012, the semiconductor substrate 10 implanted with protons and helium ions is annealed at a first temperature, which is lower than the second temperature. In this example, the first temperature may be 360°C.

[0225] The first temperature in step S1012 may be a temperature at which hydrogen terminates dangling bonds contained in vacancies and divacancies at the peak position Ps of the hydrogen ions implanted in step S1010 and its vicinity (e.g., in the region of FW1%). The first temperature may be, for example, 300°C or more and 420°C or less, and is 360°C in this example. Furthermore, the first temperature may be 330°C or more and 400°C or less, or 350°C or more and 380°C or less. Moreover, the first temperature may be less than 370°C, or 360°C or less.

[0226] The annealing time in step S1012 may be shorter than the annealing time in step S1008. The annealing time in step S1012 may be 30 minutes or more and 8 hours or less, and is 1 hour in this example. Furthermore, the annealing time in step S1012 may be 1 hour or more and 5 hours or less. By making at least one of the annealing temperature and the annealing time in step S1012 shorter than the annealing temperature and the annealing time in step S1008, it becomes easier to leave the crystal defects generated by implanting protons and helium ions. By such a process, a semiconductor device as shown in FIG. 7B can be formed.

[0227] Furthermore, after step S1012, an electrode formation step may be performed on the lower surface 23 (not shown). The electrode formation step includes a deposition step of one or more metal films. After the deposition step of the metal film, an electrode annealing step may be performed. The temperature of the electrode annealing step is lower than the first temperature. As an example, it may be 140° C. or more and 330° C. or less. The temperature of the electrode annealing step may be 220° C. or more.

[0228] In addition, the semiconductor device may be soldered to a circuit board such as a DCB (Direct Copper Bond) board after the semiconductor substrate is diced into chips. The soldering temperature at this time is defined as a third temperature. The first temperature of annealing in step S1012 is higher than the third temperature during soldering. As an example, the soldering temperature may be 280°C or higher and 400°C or lower. Note that the third temperature may be lower than, the same as, or higher than the temperature of the electrode annealing step as long as it is lower than the first temperature.

[0229] The soldering time may be 100 seconds or more and 500 seconds or less. The annealing time in step S1012 may be longer than the soldering time. Under these conditions, it is possible to prevent crystal defects from being terminated with hydrogen during soldering. The annealing time in step S1012 may be 10 minutes or more, or 30 minutes or more. The annealing time may be 2 hours or less, or 1 hour or less. From the above, it is preferable that T2>T1>T3, where T2 is the second temperature, T1 is the first temperature, and T3 is the third temperature.

[0230] 10B is a diagram showing another example of a method for manufacturing a semiconductor device. In this example, crystal defect region 19-1 on the upper surface 21 side and crystal defect region 19-2 on the lower surface 23 side are formed by proton implantation. Steps S1002 and S1004 in this example are similar to steps S1002 and S1004 shown in FIG. 10A.

[0231] In step S1006, protons are injected from the lower surface 23. The proton injection in step S1006 may be performed multiple times as shown in steps S1006-1, S1006-2, and S1006-3. In step S1006, protons are injected into the positions of the hydrogen peaks excluding one of the multiple hydrogen peaks to be formed in the buffer region 20. This example shows an example in which the proton injection is performed three times in step S1006.

[0232] In step S1008, the proton-implanted semiconductor substrate 10 is annealed at a second temperature. In this example, the second temperature may be 370° C. The annealing time may be 5 hours.

[0233] Next, in step S1011, protons are injected from the upper surface 21 and the lower surface 23. From the lower surface 23, protons are injected into the positions of hydrogen peaks that are not injected with protons in step S1006, among the multiple hydrogen peaks to be formed in the buffer region 20. From the upper surface 21, protons are injected into a position deeper than a region in the crystal defect region 19-1 where a defect density peak is to be formed. Either the injection of protons from the upper surface 21 or the injection of protons from the lower surface 23 may be performed first.

[0234] In step S1012, the semiconductor substrate 10 implanted with protons and helium ions is annealed at a first temperature. Step S1012 is the same as step S1012 shown in Fig. 10A. Through such a process, a semiconductor device as shown in Fig. 7A can be formed.

[0235] FIG. 11 is a diagram showing an example of a manufacturing method of a semiconductor device according to this embodiment. FIG. 11 is a diagram showing in detail step S1010 and step S1012 shown in FIG. 10A. As shown in FIG. 11, in step S1010, protons are implanted from one main surface of the semiconductor substrate 10, i.e., the upper surface 21, in the depth direction of the semiconductor substrate 10. In this example, protons are implanted in the depth direction of the semiconductor substrate 10 to a depth of a first position Ps that is spaced a distance Dps from the upper surface 21. In FIG. 11, the protons implanted to the depth of the first position Ps are indicated by "x". In step S1010, the amount of protons implanted is 1×10 12 ( / cm 2 ) or more 1×10 13 ( / cm 2 ) or less.

[0236] The implantation of protons from the upper surface 21 generates crystal defects from the upper surface 21 to the first position Ps of the semiconductor substrate 10. Furthermore, the implantation of protons from the upper surface 21 distributes the hydrogen concentration in the depth direction of the semiconductor substrate 10, with the hydrogen concentration peaking at the first position Ps. Furthermore, in step S1010, helium ions are implanted in the depth direction of the semiconductor substrate 10 from the lower surface 23. In this example, helium ions are implanted at the position Kb.

[0237] Next, in step S1012, the semiconductor substrate 10 implanted with protons and helium ions is annealed at a first temperature. The first temperature may be 360° C. The annealing time may be one hour. In step S1012, crystal defects caused by the implantation of protons and helium ions are terminated with hydrogen. This forms peaks of crystal defect density at positions Ks and Kb. In addition, the annealing causes the hydrogen implanted at the first position Ps to become a donor.

[0238] The semiconductor device of this example uses the position Ks as the peak of the concentration distribution and uses the crystal defect region 19-1 distributed in the depth direction of the semiconductor device as the upper surface side lifetime control region 74. Also, the semiconductor device of this example uses the region including the first position Ps where hydrogen has been converted into a donor as the high concentration region 26.

[0239] Fig. 12 is a diagram showing the distributions of the hydrogen concentration (B), the crystal defect density (C), and the carrier concentration (F) along the line h-h' in Fig. 11. In Fig. 12, the distributions before annealing in step S1010 in Fig. 11 are shown by dashed lines, and the distributions after annealing in step S1012 are shown by solid lines.

[0240] As shown in distribution diagram (B), the hydrogen concentration is distributed with a peak at a first position Ps before annealing. Hydrogen diffuses due to annealing, and the hydrogen concentration distribution spreads in the Z-axis direction. The hydrogen concentration distribution after annealing has a base S of the concentration distribution on the upper surface 21 side of the first position Ps. The hydrogen concentration is distributed more gently on the upper surface 21 side of the first position Ps than on the lower surface 23 side.

[0241] As shown in the distribution diagram (C), the distribution of the crystal defect density before annealing has the same shape as the hydrogen concentration distribution before annealing. For example, the peak position of the crystal defect density before annealing is the same as the peak position Ps of the hydrogen concentration before annealing. By annealing the semiconductor substrate 10, hydrogen diffuses in the Z-axis direction and terminates the dangling bonds. As described above, a large amount of hydrogen is present near the peak of the hydrogen concentration, so most of the crystal defects are terminated near the peak position Ps.

[0242] The distribution diagram (F) shows the distribution of carrier concentration after annealing. The distribution diagram (F) is the same as a part of the distribution diagram (F) in Fig. 7B. As shown in the distribution diagrams (B) and (C), by implanting hydrogen ions from the upper surface 21 side and annealing, a high concentration region 26 and a crystal defect region 19-1 are formed on the upper surface 21 side of the high concentration region 26.

[0243] Fig. 13 is a diagram showing another example of the method for manufacturing the semiconductor device according to this embodiment, which illustrates in detail steps S1006, S1008, S1011, and S1012 shown in Fig. 10B.

[0244] As shown in FIG. 13, the method for manufacturing a semiconductor device of this embodiment includes a step of injecting protons multiple times so that the positions of the peaks of the concentration distribution of hydrogen are different in the depth direction of the semiconductor substrate 10. That is, in step S1006, protons are injected from the other main surface of the semiconductor substrate 10, i.e., the lower surface 23, in the depth direction of the semiconductor substrate 10. In step S1006, protons are injected into the positions of hydrogen peaks excluding one of the multiple hydrogen peaks to be formed in the buffer region 20. In this embodiment, in step S1006, protons are injected sequentially into positions Pb4, Pb3, and Pb1. After the protons are injected in step S1006, the semiconductor substrate 10 is annealed in step S1008. As an example, the annealing temperature is 370° C. and the annealing time is 5 hours.

[0245] Subsequently, in step S1011, protons are implanted from the lower surface 23 to the position Pb2. Also, protons are implanted from the upper surface 21 to the position Ps.

[0246] Then, in step S1012, the semiconductor substrate 10 is annealed. As an example, the annealing temperature is 360° C. and the annealing time is one hour. In step S1012, crystal defect regions 19-1, 19-2, and high concentration regions 26 are formed.

[0247] 14 is a diagram showing another example of the method for manufacturing a semiconductor device according to this embodiment. The method for manufacturing a semiconductor device shown in FIG. 14 differs from the method for manufacturing a semiconductor device shown in FIG. 13 in that protons are implanted at position Pb2 instead of position Pb1 in step S1006 shown in FIG. 13, and that protons are implanted at position Pb1 in step S1011. In this example, the peak position Kb of the crystal defect density of the crystal defect region 19-2 is located closer to the lower surface 23 than position Pb1. In this way, the peak position Kb of the crystal defect density can be adjusted by adjusting the positions at which protons are implanted in steps S1006 and S1011.

[0248] Fig. 15 is a diagram showing another example of the outline of the method for manufacturing a semiconductor device according to this embodiment. The method for manufacturing a semiconductor device of this embodiment differs from the example of Fig. 10B in that an annealing step is provided between the step of implanting protons from the upper surface 21 and the step of implanting protons from the lower surface 23 in step S1011 shown in Fig. 10B. Steps S1002 to S1008 are the same as those in the example shown in Fig. 10B.

[0249] In this example, in step S1011-1, protons are implanted from the lower surface 23. After step S1011-1, annealing is performed in step S1012-1. The annealing temperature in step S1012-1 is lower than the annealing temperature in step S1008. The annealing time in step S1012-1 may be shorter than the annealing time in step S1008. The annealing is performed, for example, at 360° C. for 1 hour.

[0250] Next, in step S1011-2, protons are implanted from the upper surface 21. After step S1011-2, annealing is performed in step S1012-2. The annealing temperature in step S1012-2 is lower than the annealing temperature in step S1012-1. However, it is preferable that the annealing temperature in step S1012-2 is higher than the soldering temperature in the chip soldering process. Note that the order of steps S1011-1 and S1011-2 may be reversed.

[0251] 16 is a diagram illustrating the step of implanting hydrogen ions (protons in this example) from the upper surface 21 side of the semiconductor substrate 10 to form the crystal defect region 19 and the high concentration region 26. The region into which the protons are not implanted is covered with a mask 110 such as a photoresist. The mask 110 may be provided on the emitter electrode 52. The thickness T110 of the mask 110 is sufficiently larger than the depth (range) to which the protons are implanted into the semiconductor substrate 10. For example, when the range of the protons is 8 μm, the thickness T110 is 33 μm or more.

[0252] In the step of injecting protons, hydrogen ions may be injected with an acceleration energy that provides a range of 8 μm or more from the upper surface 21 of the semiconductor substrate 10. This allows the crystal defect region 19 to be formed below the lower end of each trench portion. The acceleration energy of the protons may be 600 keV or more, 1.0 MeV or more, or 1.5 MeV or more. This allows the proton range to be 8 μm or more. In the case of an acceleration energy of 1.0 MeV, the proton range is, for example, about 16 μm. In the case of an acceleration energy of 1.5 MeV, the proton range is, for example, about 30 μm.

[0253] The acceleration energy of the protons may be 5.0 MeV or more. In the case of an acceleration energy of 5.0 MeV, the range of the protons is, for example, about 215 μm. In this case, the protons can be injected into a deeper position. Also, even if the protons are injected from the lower surface 23 side of the semiconductor substrate 10, the protons can be injected near the lower end of the trench portion. Also, even before the step of grinding and thinning the lower surface 23 of the semiconductor substrate 10, the protons can be injected from the lower surface 23 side of the semiconductor substrate 10 to inject the protons near the lower end of the trench portion. After the protons are injected from the lower surface 23 of the semiconductor substrate 10, the lower surface 23 of the semiconductor substrate 10 may be ground.

[0254] The acceleration energy of the protons may be 11.0 MeV or less, or may be 5.0 MeV or less. This can prevent the protons from being implanted at too deep a position. Also, it can prevent the protons from penetrating the semiconductor substrate 10. The acceleration energy of the protons may be 2.0 MeV or less. In the case of an acceleration energy of 2.0 MeV, the range of the protons is, for example, about 47 μm.

[0255] The proton dose is 1.0×10 12 / cm 2 This allows the formation of defects at a sufficient density. The dose of protons is 1.0×10 15 / cm 2This makes it possible to suppress the effect of the crystal defect density on the anode region 14 or the base region 17 even if protons are implanted from the upper surface 21 with a range of, for example, 8 μm.

[0256] 17 is a diagram illustrating the step of implanting hydrogen ions (protons in this example) from the lower surface 23 side of the semiconductor substrate 10 to form crystal defect regions 19 and high concentration regions 26. Regions into which protons are not implanted are covered with a mask 110 such as photoresist. The mask 110 may be provided on the collector electrode 24. A thickness T110 of the mask 110 is sufficiently larger than the depth (range) to which protons are implanted into the semiconductor substrate 10.

[0257] When the mask 110 is an organic film such as a photoresist, the lower limit Y1 (μm) of the thickness T110 of the mask 110 may be expressed by the following relational equation (Mathematical Formula 1) with respect to the implantation depth of hydrogen ions, where X1 (μm) is the implantation depth of hydrogen ions. (Number 1) Y1 = 5.52317 × (X1) 0.79538 This allows the region covered with the mask 110 to adequately shield hydrogen ions. When the mask 110 is an organic film such as a photoresist, the lower limit Y2 (μm) of the thickness T110 of the mask 110 may be expressed by the following relational expression (Mathematical Expression 2) with respect to E1 (eV), where E1 is the acceleration energy when implanting hydrogen ions. (Number 2) Y2 = 1.07515 x 10 -11 ×(E1) 2 +3.83637×10 -5 ×(E1) As a result, the area covered with the mask 110 can sufficiently block hydrogen ions.

[0258] In the step of injecting protons, hydrogen ions may be injected with an acceleration energy that causes the distance between the proton injection position and the upper surface 21 of the semiconductor substrate 10 to be 8 μm or more. The acceleration energy of the protons may be 2.0 MeV or more, 3.0 MeV or more, or 4.0 MeV or more. By adjusting the acceleration energy, a high concentration region 26 can be formed on the upper surface 21 side of the semiconductor substrate 10. The high concentration region 26 may be formed at the position of the accumulation region 16.

[0259] Fig. 18 shows a depth distribution diagram of the net doping concentration (A), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) in the semiconductor device 100 shown in Fig. 17. As described above, in this example, the high concentration region 26 is formed by implanting hydrogen ions from the lower surface 23 of the semiconductor substrate 10.

[0260] As shown in distribution diagram (A), the net doping concentration may have a region from position Pb4 to position Pf on the upper surface 21 side where the concentration is higher than the concentration N0. Hydrogen ions pass through the semiconductor substrate 10 from the lower surface 23 side to position Ps, and crystal defects mainly consisting of vacancies and divacancies are formed. Since the hydrogen concentration is sufficiently high from position Pb4 to position Pf, the dangling bonds of the crystal defects are terminated with hydrogen, and hydrogen donors are formed.

[0261] As shown in the distribution diagram (B), the hydrogen concentration has a peak at position Ps. The hydrogen concentration distribution in this example has a skirt S extending from the peak position Ps toward one of the main surfaces (the lower surface 23 in this example). The hydrogen concentration between positions Ps and Pb4 may be higher than the hydrogen concentration in the anode region 14.

[0262] As shown in distribution diagram (C), the crystal defect density distribution has a peak at position Ks. The crystal defect density distribution has a tail SV1 extending from position Ks toward lower surface 23 and a tail SV2 extending toward upper surface 21. In this example, tail SV1 is gentler than tail SV2. The region where the crystal defect density is higher than concentration Nr0 is the region from position Pr to position Pf.

[0263] As shown in the distribution diagram (D), the carrier lifetime distribution has a peak at the position Ks. The carrier lifetime distribution has a tail Sτ1 extending from the position Ks toward the lower surface 23 and a tail Sτ2 extending toward the upper surface 21. In this example, the tail Sτ1 is gentler than the tail Sτ2. The region where the carrier lifetime is shorter than τ0 is the region from the position Pr to the position Pf.

[0264] As shown in distribution diagram (E), the carrier mobility distribution has a peak at position Ks. The carrier mobility distribution has a foot Sμ1 extending from position Ks toward the lower surface 23 and a foot Sμ3 extending toward the upper surface 21. In this example, the foot Sμ1 is gentler than the foot Sμ3. The region where the carrier mobility is lower than μ0 is the region from position Pr to position Pf.

[0265] As shown in distribution diagram (F), the carrier concentration distribution has a peak at position Ks. The carrier concentration distribution has a base SN1 extending from position Ks toward the lower surface 23 and a base SN3 extending toward the upper surface 21. In this example, base SN1 is gentler than base SN3. Bases SV1, Sτ1, Sμ1, and SN1 in this example may or may not reach the buffer region 20.

[0266] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0267] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0268] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 anode region, 15 contact region, 16 accumulation region, 17 base region, 18 drift region, 19 crystal defect region, 19-1 crystal defect region, 19-2 crystal defect region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 26 high concentration region, 27 lower electrode, 29 extension portion, 30 dummy trench portion, 31 connection portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 extension portion, 40 gate trench portion, 41 connection portion, 42 gate insulating film, 44 gate conductive portion, 48 gate runner , 49 contact hole, 50 gate metal layer, 52 emitter electrode, 53 upper electrode, 54 contact hole, 56 contact hole, 58 barrier metal, 60 first mesa portion, 62 second mesa portion, 64 third mesa portion, 70 transistor portion, 74 upper lifetime control region, 78 lower lifetime control region region, 80...diode portion, 81...extension region, 82...cathode region, 90...boundary portion, 92...edge termination structure portion, 100...semiconductor device, 110...mask, 116...gate pad, 118...emitter pad, 120...active portion, 140...periphery, 150...semiconductor device, 200...semiconductor device, 274...upper surface side lifetime control region

Claims

1. a semiconductor substrate having a dopant of a first conductivity type; an active portion including a transistor portion having an emitter region provided on one main surface of the semiconductor substrate, and a diode portion having an anode region provided on the one main surface; a high concentration region having a doping concentration higher than a concentration of a dopant in the semiconductor substrate, the high concentration region having a hydrogen concentration distribution in a depth direction of the semiconductor substrate having a peak at a first position; a first crystal defect region that is provided on one main surface side of the semiconductor substrate relative to the high concentration region and has a center peak where the crystal defect density is highest at a second position that is closer to the one main surface side than the first position, or that is provided on the other main surface side of the semiconductor substrate relative to the high concentration region and has a center peak where the crystal defect density is highest at a second position that is closer to the other main surface side than the first position; Equipped with the transistor portion has a collector region of a second conductivity type on the other main surface, the diode portion has a first conductivity type cathode region on the other main surface, the transistor portion has a plurality of gate trench portions or dummy trench portions arranged in an arrangement direction and extending in an extension direction; the transistor portion has a first mesa portion in contact with the gate trench portion or the dummy trench portion in the arrangement direction, the diode portion has a plurality of the dummy trench portions in the arrangement direction, the diode portion has a third mesa portion in contact with the dummy trench portion in the arrangement direction, the transistor section has the first mesa section sandwiched between one or more dummy trench sections in the arrangement direction, on the diode section side of the gate trench section provided closest to the diode section in the arrangement direction, ends of the first crystal defect region and the high concentration region in the arrangement direction are located in the first mesa portion or the dummy trench portion that is provided closer to the diode portion than the gate trench portion that is provided closest to the diode portion in the arrangement direction; At least a portion of the high concentration region is provided in the diode portion. Semiconductor device.

2. A semiconductor substrate having a dopant of a first conductivity type; an active portion including a transistor portion having an emitter region provided on one main surface of the semiconductor substrate, and a diode portion having an anode region provided on the one main surface; a high concentration region having a doping concentration higher than a concentration of a dopant in the semiconductor substrate, the high concentration region having a hydrogen concentration distribution in a depth direction of the semiconductor substrate having a peak at a first position; a first crystal defect region that is provided closer to one main surface of the semiconductor substrate than the high concentration region and has a center peak with the highest crystal defect density at a second position closer to the one main surface than the first position; Equipped with the transistor portion has a collector region of a second conductivity type on the other main surface of the semiconductor substrate; the diode portion has a first conductivity type cathode region on the other main surface, the transistor portion has a plurality of gate trench portions or dummy trench portions arranged in an arrangement direction and extending in an extension direction; the transistor portion has a first mesa portion in contact with the gate trench portion or the dummy trench portion in the arrangement direction, the diode portion has a plurality of the dummy trench portions in the arrangement direction, the diode portion has a third mesa portion in contact with the dummy trench portion in the arrangement direction, the transistor section has the first mesa section sandwiched between one or more dummy trench sections in the arrangement direction, on the diode section side of the gate trench section provided closest to the diode section in the arrangement direction, an end portion of the first crystal defect region in the arrangement direction is located in the first mesa portion or the dummy trench portion that is provided closer to the diode portion than the gate trench portion that is provided closest to the diode portion in the arrangement direction; The first position is disposed on the one main surface side of the center of the semiconductor substrate in the depth direction. Semiconductor device.

3. A semiconductor substrate having a dopant of a first conductivity type; an active portion including a transistor portion having an emitter region provided on one main surface of the semiconductor substrate, and a diode portion having an anode region provided on the one main surface; a high concentration region having a doping concentration higher than a concentration of a dopant in the semiconductor substrate, the high concentration region having a hydrogen concentration distribution in a depth direction of the semiconductor substrate having a peak at a first position; a first crystal defect region that is provided closer to one main surface of the semiconductor substrate than the high concentration region and has a center peak with the highest crystal defect density at a second position closer to the one main surface than the first position; Equipped with the transistor portion has a collector region of a second conductivity type on the other main surface of the semiconductor substrate; the diode portion has a first conductivity type cathode region on the other main surface, the transistor portion has a plurality of gate trench portions or dummy trench portions arranged in an arrangement direction and extending in an extension direction; the transistor portion has a first mesa portion in contact with the gate trench portion or the dummy trench portion in the arrangement direction, the diode portion has a plurality of the dummy trench portions in the arrangement direction, the diode portion has a third mesa portion in contact with the dummy trench portion in the arrangement direction, the transistor section has the first mesa section sandwiched between one or more dummy trench sections in the arrangement direction, on the diode section side of the gate trench section provided closest to the diode section in the arrangement direction, an end portion of the first crystal defect region in the arrangement direction is located in the first mesa portion or the dummy trench portion that is provided closer to the diode portion than the gate trench portion that is provided closest to the diode portion in the arrangement direction; The distance between the first position and the second position is 20 μm or less. Semiconductor device.

4. A semiconductor substrate having a dopant of a first conductivity type; an active portion including a transistor portion having an emitter region provided on one main surface of the semiconductor substrate, and a diode portion having an anode region provided on the one main surface; a high concentration region having a doping concentration higher than a concentration of a dopant in the semiconductor substrate, the high concentration region having a hydrogen concentration distribution in a depth direction of the semiconductor substrate having a peak at a first position; a first crystal defect region that is provided on one main surface side of the semiconductor substrate relative to the high concentration region and has a center peak where the crystal defect density is highest at a second position that is closer to the one main surface side than the first position, or that is provided on the other main surface side of the semiconductor substrate relative to the high concentration region and has a center peak where the crystal defect density is highest at a second position that is closer to the other main surface side than the first position; Equipped with the transistor portion has a collector region of a second conductivity type on the other main surface, the diode portion has a first conductivity type cathode region on the other main surface, the transistor portion has a plurality of gate trench portions or dummy trench portions arranged in an arrangement direction and extending in an extension direction; the transistor portion has a first mesa portion in contact with the gate trench portion or the dummy trench portion in the arrangement direction, the diode portion has a plurality of the dummy trench portions in the arrangement direction, the diode portion has a third mesa portion in contact with the dummy trench portion in the arrangement direction, the transistor section has the first mesa section sandwiched between one or more dummy trench sections in the arrangement direction, on the diode section side of the gate trench section provided closest to the diode section in the arrangement direction, an end portion of the first crystal defect region in the arrangement direction is located in the first mesa portion or the dummy trench portion that is provided closer to the diode portion than the gate trench portion that is provided closest to the diode portion in the arrangement direction; the semiconductor substrate further includes a well region of a second conductivity type that is provided from the one main surface to a depth deeper than the gate trench portion and the dummy trench portion and covers ends of the gate trench portion and the dummy trench portion in the extension direction; the first crystal defect region is formed in the extension direction from the active portion toward the well region, An end portion of the first crystal defect region in the extending direction is located inside the well region. Semiconductor device.

5. A semiconductor substrate having a dopant of a first conductivity type; an active portion including a transistor portion having an emitter region provided on one main surface of the semiconductor substrate, and a diode portion having an anode region provided on the one main surface; a high concentration region having a doping concentration higher than a concentration of a dopant in the semiconductor substrate, the high concentration region having a hydrogen concentration distribution in a depth direction of the semiconductor substrate having a peak at a first position; a first crystal defect region that is provided closer to one main surface of the semiconductor substrate than the high concentration region and has a center peak with the highest crystal defect density at a second position closer to the one main surface than the first position; Equipped with the transistor portion has a collector region of a second conductivity type on the other main surface of the semiconductor substrate; the diode portion has a first conductivity type cathode region on the other main surface, the transistor portion has a plurality of gate trench portions or dummy trench portions arranged in an arrangement direction and extending in an extension direction; the transistor portion has a first mesa portion in contact with the gate trench portion or the dummy trench portion in the arrangement direction, the diode portion has a plurality of the dummy trench portions in the arrangement direction, the diode portion has a third mesa portion in contact with the dummy trench portion in the arrangement direction, the transistor section has the first mesa section sandwiched between one or more dummy trench sections in the arrangement direction, on the diode section side of the gate trench section provided closest to the diode section in the arrangement direction, an end portion of the first crystal defect region in the arrangement direction is located in the first mesa portion or the dummy trench portion that is provided closer to the diode portion than the gate trench portion that is provided closest to the diode portion in the arrangement direction; The hydrogen concentration distribution in the depth direction of the semiconductor substrate is a first skirt that is provided on the one main surface side of the first position and in which the hydrogen concentration decreases from the first position toward the one main surface; a second base that is provided closer to the other main surface of the semiconductor substrate than the first position, and in which the hydrogen concentration decreases more steeply from the first position toward the other main surface than at the first base; A semiconductor device having the above structure.

6. A semiconductor substrate having a dopant of a first conductivity type; an active portion including a transistor portion having an emitter region provided on one main surface of the semiconductor substrate, and a diode portion having an anode region provided on the one main surface; a high concentration region having a doping concentration higher than a concentration of a dopant in the semiconductor substrate, the high concentration region having a hydrogen concentration distribution in a depth direction of the semiconductor substrate having a peak at a first position; a first crystal defect region that is provided closer to the other main surface of the semiconductor substrate than the high concentration region and has a center peak with the highest crystal defect density at a second position closer to the other main surface than the first position; Equipped with the transistor portion has a collector region of a second conductivity type on the other main surface, the diode portion has a first conductivity type cathode region on the other main surface, the transistor portion has a plurality of gate trench portions or dummy trench portions arranged in an arrangement direction and extending in an extension direction; the transistor portion has a first mesa portion in contact with the gate trench portion or the dummy trench portion in the arrangement direction, the diode portion has a plurality of the dummy trench portions in the arrangement direction, the diode portion has a third mesa portion in contact with the dummy trench portion in the arrangement direction, the transistor section has the first mesa section sandwiched between one or more dummy trench sections in the arrangement direction, on the diode section side of the gate trench section provided closest to the diode section in the arrangement direction, an end portion of the first crystal defect region in the arrangement direction is located in the first mesa portion or the dummy trench portion that is provided closer to the diode portion than the gate trench portion that is provided closest to the diode portion in the arrangement direction; The hydrogen concentration distribution in the depth direction of the semiconductor substrate is a first skirt that is provided on the other main surface side of the first position and in which the hydrogen concentration decreases from the first position toward the other main surface; a second base that is provided closer to the one main surface side of the semiconductor substrate than the first position, and in which the hydrogen concentration decreases more steeply from the first position toward the one main surface than the first base; A semiconductor device having the above structure.

7. the first mesa portion has the emitter region provided on the one principal surface, the transistor portion has a boundary portion adjacent to the diode portion, The boundary portion has a second mesa portion in which a second conductivity type base region is exposed on the one main surface. The semiconductor device according to claim 1 .

8. The distribution of the doping concentration in the depth direction has a first donor peak at the first position that is lower than a hydrogen concentration. The semiconductor device according to claim 1 .

9. The crystal defect density distribution of the first crystal defect region has a third tail that decreases in the first tail region from the center peak toward the other main surface. The semiconductor device according to claim 5 .

10. The crystal defect density distribution of the first crystal defect region has a third tail that decreases in the first tail region from the center peak toward the one main surface. The semiconductor device according to claim 6.

11. the transistor portion includes a plurality of the first mesa portions, At least one of the first mesa portions is sandwiched between the dummy trench portions that are in contact with the first mesa portion. The semiconductor device according to claim 1 .

12. the collector region of the transistor portion extends onto the other main surface of the boundary portion, The cathode region is not provided on the other main surface of one or more third mesa portions that are closest to the boundary portion in the diode portion, and the collector region of the boundary portion extends thereto. The semiconductor device according to claim 7.

13. An end portion of the first crystal defect region in the extending direction extends outside the active portion further than an end portion of the cathode region. The semiconductor device according to claim 1 .

14. The semiconductor substrate having a drift region of a first conductivity type having a doping concentration lower than that of the emitter region, The carrier concentration in the first crystal defect region is lower than the doping concentration in the drift region. The semiconductor device according to claim 1 .

15. The gate trench portion is a gate conductive portion formed of a conductive material; a gate insulating film insulating the gate conductive portion from the semiconductor substrate; a gate runner and a gate metal layer provided on the one main surface and connected to the gate conductive portion; When viewed from above, at least a portion of the first crystal defect region overlaps with the gate runner or the gate metal layer. The semiconductor device according to claim 13.

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