Vertical thin film transistor and memory circuit method for application of vertical thin film transistor as bit line connector for three-dimensional memory arrays

Abstract

The present invention provides a memory circuit comprising: (i) a semiconductor substrate having a planar surface in which a circuit for operating a memory is formed; (ii) a memory array formed on the planar surface, the memory array having one or more electrodes for the memory circuits in the memory array, each conductor extending along a first direction substantially parallel to the planar surface; and (iii) one or more transistors formed above, to the side of, or below a corresponding one of the conductors in the first conductor layer and above the planar surface of the semiconductor substrate, wherein each transistor (a) has a first drain / source region, a second drain / source region, and a gate region each made of a semiconductor material, the first drain / source region, the second drain / source region, or the gate region being formed on a metal silicide; and (b) selectively connecting the corresponding electrode to the circuit for operating the memory.

Description

[Technical field]

[0001] The present invention relates to thin film transistors having low defect concentrations, and more particularly to the use of thin film transistors having low defect concentrations in three dimensional memory arrays. [Background technology]

[0002] The non-provisional patent application discloses a three-dimensional array of thin-film storage transistors ("3D memory array") fabricated on a planar surface of a semiconductor substrate. For ease of reference, the direction perpendicular to the planar surface is referred to herein as the "Z-direction," while the two directions parallel to the planar surface and perpendicular to each other are referred to as the "X-direction" and "Y-direction," respectively. Multiple 3D memory arrays may be formed on a single semiconductor substrate.

[0003] The three-dimensional memory array includes a stack of NOR memory strings spaced apart from each other at regular intervals along the X-direction. Each stack of NOR memory strings has layers of NOR memory strings arranged on top of each other (i.e., along the Z-direction) and separated from each other by the layers. In one implementation, each stack has eight layers of NOR memory strings, and eight such stacks are provided along the X-direction. Each layer of NOR memory strings in each stack includes a first strip and a second strip including an n-type or p-type polysilicon layer separated from each other by a channel material-containing strip. The channel material-containing strip includes a polysilicon layer in contact with the polysilicon layers of the first strip and the second strip. The polysilicon layers in the channel material-containing strip may be low-doped polysilicon, and are preferably doped with a different conductivity type from the polysilicon layers of the first strip and the second strip. Each of the first strip, the second strip, and the channel material-containing strip has a length extending along the Y-direction and a narrow width along the X-direction. The polysilicon layers of the first and second strips form a common source and drain region for the layer of NOR memory strings.

[0004] As disclosed in the non-provisional patent application, each channel material-containing strip has two polysilicon layers exposed on opposing sidewalls of the stack, and the polysilicon layers are separated from each other by an insulating material. The polysilicon layers form channel regions of two thin-film storage transistors on opposing sides of the stack. Between adjacent stacks, conductor pillars (e.g., highly doped polysilicon) extending in the Z direction are spaced apart along the Y direction and insulated from each adjacent stack by charge trapping material (e.g., oxide-nitride-oxide triple layer) covering the stack's vertical sidewalls. Each conductor pillar functions as a gate electrode. Where the conductor pillar ("local word line") overlaps one of the channel regions and the adjacent common source and drain regions, a thin-film storage transistor and charge trapping material adjacent to the channel region are formed. In this manner, two NOR memory strings are formed on opposing sides of each layer of the NOR memory strings of each stack.

[0005] The non-provisional patent application discloses CMOS supporting circuitry for memory operations (e.g., various power supply circuits, address decoders, and sense amplifiers) formed on a semiconductor substrate beneath the three-dimensional memory array. In one implementation, to provide modularity, the circuitry for memory operations supporting each three-dimensional memory array above the semiconductor substrate is formed beneath the three-dimensional memory array itself.

[0006] The common drain regions ("bit lines") (as well as common source regions in some implementations) of the three-dimensional memory array extend in the Y direction beyond both sides ("array regions") of the three-dimensional memory array into "staircase regions." In each staircase region, the bit lines (or source lines) of each layer of NOR memory strings in each stack extend to different extents in the Y direction to form a staircase-like structure, with the widest extent being the layer of NOR memory strings closest to the semiconductor substrate and the narrowest extent being the layer of NOR memory strings furthest from the semiconductor substrate. As shown in various embodiments of the nonprovisional patent application, the staircase structure facilitates electrical connection between each bit line and a corresponding circuit for operating the memory (e.g., a sense amplifier). Summary of the Invention [Means for solving the problem]

[0007] In accordance with one embodiment of the present invention, a memory circuit includes: (i) a semiconductor substrate having a planar surface with circuitry formed therein for operating a memory; (ii) an array of memory cells formed over the planar surface in a memory array formed in a memory structure including a first conductor layer, the first conductor layer of the memory structure having one or more conductors each extending along a first direction substantially parallel to the planar surface and carrying electrical signals to or from the memory cells; and (iii) conductors and one or more transistors formed above, to the side of, or below corresponding ones of the conductors in the layer and above the planar surface of the semiconductor substrate, each transistor (a) having a first drain or source region, a second drain or source region, and a gate region, each of the first drain or source region, the second drain or source region, or the gate region, each of the first drain or source region, the second drain or source region, or the gate region being formed on a metal silicide; and (b) selectively connecting corresponding conductors in the first conductor layer to circuitry for operating the memory.

[0008] In one embodiment, the metal silicide layer comprises titanium silicide or nickel silicide.

[0009] In one embodiment, the memory circuit further includes a second conductor layer, a first drain or source region of each transistor connected to one of the conductors of the second conductor layer, and a second drain or source region of each transistor connected to one of the conductors of the first conductor layer. The memory circuit may further include a set of interconnect lines, and a gate terminal of each transistor connected to one of the interconnect lines.

[0010] In one embodiment, when current is present in the channel region of the transistor, the current flows in a direction substantially perpendicular to the planar surface.

[0011] In one embodiment, the memory array includes a number of levels each having a number of NOR memory strings, and the conductors of the first conductor layer form common bit lines for the NOR memory strings. Some of the common bits may be provided in a staircase structure extending from one or both sides of the memory array. Further, each step of the staircase structure may include a common bit line for a corresponding memory string level, and the transistors connected to the common bit line at each step of the staircase structure may form a bit line selector for the corresponding common bit line. The transistors of each bit line selector form a first group and a second group, and the bit line selector selects adjacent bit lines from one of the transistors of the first group and one of the transistors of the second group, and the contacts to the transistors of the first group are staggered with respect to the contacts to the transistors of the second group.

[0012] According to one embodiment of the present invention, a first method for fabricating a transistor includes the steps of: (i) providing a semiconductor substrate having a planar surface; (ii) providing a first semiconductor layer having a first conductivity type and a first doping concentration on the planar surface of the semiconductor substrate; (iii) providing a mold dielectric layer on the first semiconductor layer; (iv) etching the mold dielectric layer to form a trench substantially perpendicular to the planar surface and exposing a surface of the first semiconductor layer; and (v) etching the mold dielectric layer to form a trench. The method includes filling the trench with a second semiconductor layer having a second conductivity type different from the first conductivity type or a second doping concentration lower than the first doping concentration and having an amorphous state; (vi) converting a portion of the second semiconductor layer into a third semiconductor layer having the first conductivity type or a third doping concentration higher than the second doping concentration; (vii) providing a metal layer on the third semiconductor layer; and (viii) converting the metal layer into a metal silicide layer by annealing the metal layer.

[0013] The first method may further include, after providing the protective layer, (i) forming a second trench in the mold dielectric layer substantially perpendicular to the planar surface, exposing a portion of the second semiconductor, (ii) providing an insulator on the exposed portion of the second semiconductor, and (iii) filling the second trench by providing a conductive material insulated from the second semiconductor layer by the insulator. The conductive material may provide a gate electrode for the transistor.

[0014] According to one embodiment of the present invention, a second method for fabricating a transistor includes the steps of: (i) providing a semiconductor substrate having a planar surface; (ii) providing a first semiconductor layer having a first conductivity type and a first doping concentration on the planar surface of the semiconductor substrate; (iii) providing a mold dielectric layer on the first semiconductor layer; (iv) etching the mold dielectric layer to form a trench substantially perpendicular to the planar surface and exposing a surface of the first semiconductor layer; (v) providing a conductive material coating the exposed surface of the first semiconductor layer and sidewalls of the trench; and (vi) providing an insulator coating the conductive material. (vii) anisotropically etching away any conductive material or any portion of the insulating material in the trench to expose a surface of the first semiconductor layer; (viii) filling the trench with a second semiconductor layer having a second conductivity type different from the first conductivity type or a second doping concentration lower than the first doping concentration and having an amorphous state; (ix) converting a portion of the second semiconductor layer to a third semiconductor layer having the first conductivity type and a third doping concentration higher than the second doping concentration; (x) providing a metal layer on the third semiconductor layer; and (xi) converting the metal layer to a metal silicide layer by annealing the metal layer.

[0015] In the first and second methods, the step of converting a portion of the second semiconductor layer into the third semiconductor layer may include gas diffusion or ion implantation.

[0016] According to one embodiment of the present invention, a third method for fabricating a transistor includes the steps of: (i) providing a semiconductor substrate having a planar surface; (ii) providing a first semiconductor layer on the planar surface; (iii) providing a first insulating layer on the first semiconductor layer; (iv) providing a third semiconductor layer on the first insulating layer such that the third semiconductor layer is separated from the first semiconductor layer; (v) providing a second semiconductor layer in contact with both the first semiconductor layer and the third semiconductor layer, a portion of which is disposed above the third semiconductor layer; and (vi) providing a second semiconductor layer on the second semiconductor layer. The method includes providing an insulating layer; (vii) providing a conductive material on the second insulating layer; (viii) providing a passivation layer surrounding the conductive material, the second insulating layer, the second semiconductor layer, the third semiconductor layer, the first insulating layer, and the first semiconductor layer; (ix) forming a via by etching the passivation layer to expose a portion of the conductive material; (x) providing a metal layer on the exposed portion of the conductive material or on the exposed portion of the third semiconductor layer; and (xi) converting the metal layer to a metal silicide layer by annealing the metal layer.

[0017] The third method may further include forming a line structure around the third semiconductor layer, the first insulating layer, and the first semiconductor layer by etching the second semiconductor layer, the second insulating layer, and the conductor layer.

[0018] According to one embodiment of the present invention, a fourth method for fabricating a transistor includes the steps of: (a) providing a first semiconductor layer having a first conductivity type on a planar surface of a semiconductor substrate; (b) providing a dielectric material on the first semiconductor layer; (c) forming a first portion and a second portion of a cavity in the dielectric material reaching to the first semiconductor layer, the second portion of the cavity having a width that is significantly smaller than a width of the corresponding first portion of the cavity; (d) conformally providing an etch stop layer on sidewalls of the cavity; (e) conformally providing a sacrificial layer on the etch stop layer on the sidewalls of the first portion of the cavity, the sacrificial layer having a thickness to fill most of the second portion of the cavity; and (f) anisotropically etching the sacrificial layer and the etch stop layer. (g) providing an amorphous semiconductor material to fill the first portion of the cavity; (h) providing a metal layer on the amorphous semiconductor material; (i) annealing the metal layer to form an alloy of the semiconductor material; (j) converting the crystallized portion of the semiconductor material to a region of the semiconductor material having a first conductivity type by ion implantation; (k) removing the sacrificial layer from the first and second portions of the cavity; (l) conformally providing a gate dielectric material on sidewalls of the first and second portions of the cavity; and (m) filling the first and second portions of the cavity with the gate dielectric material.

[0019] In any of the first, second, third, and fourth methods, the metal silicide may include one or more of titanium silicide and nickel silicide. When the metal layer includes titanium, the annealing is performed at a temperature higher than 550°C for 1 second to 24 hours. In particular, when the metal layer is titanium, the annealing is performed at a temperature in the range of 550 to 600°C for 12 to 24 hours, at a temperature in the range of 600 to 750°C for 5 minutes to 12 hours, at a temperature in the range of 750 to 800°C for 1 to 5 minutes, or at a temperature in the range of 800 to 1000°C for 1 second to 1 minute. When the metal layer includes nickel, the annealing is performed at a temperature in the range of 350 to 450°C.

[0020] In any of the first, second, third and fourth methods, the amorphous semiconductor material is converted to a crystalline semiconductor material by annealing, the crystallization process being aided by the metal silicide adjacent to the amorphous semiconductor layer.

[0021] The present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0022] [Figure 1A] FIG. 1A illustrates an eight-layer staircase structure 100-L that includes eight bit lines in layers of eight NOR memory strings on one side of a three-dimensional memory array. [Figure 1B] FIG. 1B is a side view of the staircase structures 100-L and 100-R in the XZ plane. [Figure 1C] FIG. 1C is a top view illustrating an 8-bit bit line selector 150 (eg, the bit line selector for bit line 106-0 of FIG. 1A) at one selection level spanning eight stacks of a three-dimensional memory array. [Figure 1D] FIG. 1D is a schematic circuit diagram of an 8-bit bit line selector 150. As shown in FIG. [Figure 1E]FIG. 1E illustrates how, in a semiconductor substrate below the staircase structure, the sense amplifiers are connected to four 8-bit bit line selectors, each connected to a common bit line of a corresponding one of four levels of NOR memory strings in a 3D memory array. [Figure 2A] FIG. 2A illustrates vertical TFT schemes 201, 202, and 203 according to an embodiment of the present invention, in which vertical thin film transistors (vertical TFTs) are provided at corresponding positions on the upper, lower, and lateral sides of a staircase structure 200. [Figure 2B] FIG. 2B is a cross-sectional view of a vertical TFT 330 according to one embodiment of the present invention. [Figure 2C] FIG. 2C is a cross-sectional view of a vertical TFT 350 according to one embodiment of the present invention. [Diagram 3] FIG. 3 shows a bit line selector 300 formed using vertical TFTs on a staircase structure 320 according to one embodiment of the present invention. [Figure 4] FIG. 4 is a YZ plane cross-sectional view of the staircase structure 320 of FIG. 3 through the odd bit lines according to one embodiment of the present invention. [Diagram 5] FIG. 5 shows a staircase structure 320 in which bit line selection signals are connected to the gate terminals 233 of the corresponding vertical TFTs TR0, TR4, TR1, TR5 using global word lines 103-0, 103-4, 103-1, 103-5, and the drain terminals 231a of the vertical TFTs TR0, TR4, TR1, TR5 are connected using the conductor layer 212. [Figure 6] FIG. 6 is an isometric view of a number of vertical TFTs (e.g., vertical TFT 5) and a staircase structure 40 before interconnect conductors are formed on the top side of the staircase structure 40 and the vertical TFTs in accordance with one embodiment of the present invention. [Figure 7A] FIG. 7A illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7B-1]FIG. 7B-1 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7B-2] FIG. 7B-2 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7C] FIG. 7C illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7D-1] FIG. 7D-1 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7D-2] FIG. 7D-2 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7E-1] FIG. 7E-1 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7E-2] FIG. 7E-2 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7F-1] FIG. 7F-1 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7F-2] FIG. 7F-2 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7G-1] FIG. 7G-1 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7G-2] FIG. 7G-2 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7H-1] FIG. 7H-1 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7H-2] FIG. 7H-2 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7I] FIG. 7I illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7J-1] FIG. 7J-1 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7J-2] FIG. 7J-2 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7K-1] FIG. 7K-1 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7K-2] FIG. 7K-2 illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 7L] FIG. 7L illustrates a fabrication process for forming a vertical TFT according to one embodiment of the present invention. [Figure 8] FIG. 8 illustrates a vertical TFT 850 according to one embodiment of the present invention. [Figure 9A] FIG. 9A illustrates another method for fabricating a vertical TFT 850 according to one embodiment of the present invention. [Figure 9B] FIG. 9B illustrates another method of fabricating a vertical TFT 850 according to one embodiment of the present invention. [Figure 9C] FIG. 9C illustrates another method of fabricating a vertical TFT 850 according to one embodiment of the present invention. [Figure 9D] FIG. 9D illustrates another method of fabricating a vertical TFT 850 according to one embodiment of the present invention. [Figure 9E] FIG. 9E illustrates another method of fabricating a vertical TFT 850 according to one embodiment of the present invention. [Figure 9F] FIG. 9F illustrates another method of fabricating a vertical TFT 850 according to one embodiment of the present invention. [Figure 9G] FIG. 9G illustrates another method of fabricating a vertical TFT 850 according to one embodiment of the present invention. [Figure 9H] FIG. 9H illustrates another method of fabricating a vertical TFT 850 according to one embodiment of the present invention. [Figure 10]FIG. 10 illustrates a vertical TFT 280 according to one embodiment of the present invention. [Figure 11A] FIG. 11A illustrates a process for forming the vertical TFT 280 of FIG. 10 according to one embodiment of the present invention. [Figure 11B] FIG. 11B illustrates a process for forming the vertical TFT 280 of FIG. 10 according to one embodiment of the present invention. [Figure 11C] FIG. 11C illustrates a process for forming the vertical TFT 280 of FIG. 10 according to one embodiment of the present invention. [Figure 11D] FIG. 11D illustrates a process for forming the vertical TFT 280 of FIG. 10 according to one embodiment of the present invention. [Figure 11E] FIG. 11E illustrates a process for forming the vertical TFT 280 of FIG. 10 according to one embodiment of the present invention. [Figure 11F] FIG. 11F illustrates a process for forming the vertical TFT 280 of FIG. 10 according to one embodiment of the present invention. [Figure 12A] FIG. 12A illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12B] FIG. 12B illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12C] FIG. 12C illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12D] FIG. 12D illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12E]FIG. 12E illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12F] FIG. 12F illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12G] FIG. 12G illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12H] FIG. 12H illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12I] FIG. 12I illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12J] FIG. 12J illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 12K] FIG. 12K illustrates a vertical high mobility TFT 1220 connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. [Figure 13] FIG. 13 shows the vertical TFT of FIGS. 12A to 12K with some of the dielectric layers removed for clarity. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] 1A illustrates an eight-layer staircase structure 100-L that includes eight bitlines for eight levels of NOR memory strings on one side of a three-dimensional memory array. As shown in FIG. 1A, the staircase structure 100-L includes bitlines 106-0, . . . , 106-7 that extend along the Y direction and decrease in length as their location increases in the Z direction. The bitlines 106-0, 106-2, 106-4, 106-6 are electrically connected to conductors in corresponding conductor layers 101-1, 101-2, 101-3, 101-4 by corresponding conductor-filled vias 105-0, 105-2, 105-4, 105-6, respectively. In staircase structure 100-R (not shown in FIG. 1A), which corresponds to staircase structure 100-L, bitlines 106-1, 106-3, 106-5, 106-7 are electrically connected by corresponding conductor-filled vias 105-1, 105-3, 105-5, 105-7, respectively, to corresponding conductors in the same conductor layers 101-1, 101-2, 101-3, 101-4 described above. The conductors in conductor layers 101-1, 101-2, 101-3, 101-4 are each electrically connected to a vertical set of first interconnect conductors (the "first global wordlines").

[0024] The first global word lines of the staircase structure 100-L (and 100-R) each route electrical signals between auxiliary circuitry in the semiconductor substrate and selected bit lines in a similar level layer of NOR memory strings in the three-dimensional memory array. In this specification, "similar level" refers to layers of NOR memory strings located at approximately the same level as each other on a flat semiconductor substrate. As shown in FIG. 1A, the first global word line 103-6 is connected by via 101-6 to a conductor in conductor layer 101-4, which is electrically connected to bit line 106-6. The first global word line 103-6 is connected by conductor pillar or local word line 104-6 through conductor 107-6 and via to buried contact 108-6. Conductor 107-6 forms a conductor of a second set of interconnect conductors ("second global word lines") that run along a direction substantially parallel to the first global word lines under the three-dimensional memory array. Buried contact 108-6 is connected through a bit line selector circuit (not shown in FIG. 1A, but described below in conjunction with FIG. 1C) to a sense amplifier serving bit line 106-6. A second global word line 107-6 allows other circuitry (e.g., a bias voltage source) to connect to bit line 106-6.

[0025] In FIG. 1A, first global word line 103-4, like first global word line 103-6, is connected by via 102-4 to a conductor in conductor layer 101-3 that is electrically connected to bit line 106-2. First global word line 103-4 is connected by local word line 104-4 to second global word line 107-4 and a conductor filled via to buried contact 108-4. Buried contact 108-4 is connected through a bit line selector circuit to a sense amplifier serving bit line 106-4. Second global word line 107-6 allows other circuitry (e.g., a bias voltage source) to connect to bit line 106-6.

[0026] Figure 1B is a side view in the XZ plane of the staircase structures 100-L and 100-R, respectively. Figure 1B shows how the bit lines 106-0, 106-2, 106-4, and 106-6 are connected to the corresponding buried contacts 108-0, 108-4, 108-6, and 108-8 of the staircase structure 100-L in the manner already described above with reference to Figure 1A. Figure 1B also shows how the bit lines 106-1, 106-3, 106-5, and 106-7 are connected to the corresponding buried contacts 108-1, 108-3, 108-5, and 108-7 of the staircase structure 100-R in a similar manner. FIG. 1B also shows diagrammatically that buried contacts 108-0, . . . , 108-6, 108-7 are each connected through an eight-input selection circuit that selects one of eight bit lines of a like level across the eight stacks of the three-dimensional memory array.

[0027] Thus, the connection method shown in Figures 1A and 1B requires four additional conductor layers (i.e., conductor layers 101-1, 101-2, 101-3, and 101-4) for a three-dimensional memory array having eight levels. In general, the connection method of Figures 1A and 1B requires half as many additional conductor layers as the number of levels of the three-dimensional memory array. Also, as the number of levels of the three-dimensional memory array increases, the silicon real estate for the bit line selectors under the three-dimensional memory array increases proportionally. Figure 1C is a top view of an eight-bit bit line selector 150 (e.g., the bit line selector for bit line 106-0 in Figure 1A) at one select level across eight stacks of the three-dimensional memory array.

[0028] As shown in FIG. 1C, bit line BL0 <0> , BL0 <1> , , BL0 <7> are each connected to a corresponding one of the drain terminals of the eight CMOS transistors forming the bit line selector 150 in the semiconductor substrate. <0> , BL1 <1> , , BL1 <7> , and BL2 <0> , BL2 <1> , , BL2 <7> , and BL3 <0> , BL3 <1> , , BL3 <7> Each of the four 8-bit bit line selectors is connected to one of three other 8-bit bit line selectors. The source terminals of the 32 CMOS transistors in the four 8-bit bit line selectors are all commonly connected to terminal 151 of a sense amplifier that serves all 32 bit lines (i.e., the 32 bit lines correspond to each of the 8 bit lines in the four select levels of the staircase structure). In the bit line selector 150, a selection signal SEL <0> , S.E.L. <1> , ,SEL <7> are provided to corresponding ones of the gate electrodes of the eight CMOS transistors. Thus, when one of the select signals is activated, the corresponding CMOS transistor becomes conductive, thereby connecting the corresponding bit line to terminal 151 of the sense amplifier.

[0029] 1D is a schematic circuit diagram of an 8-bit bit line selector 150. In FIG. 1D, the eight CMOS transistors of the bit line selector 150 are grouped into four transistor pairs, with the two CMOS transistors of each transistor pair sharing a common source region with each other.

[0030] FIG. 1E illustrates how, in a semiconductor substrate below the staircase structure, the sense amplifiers are connected to four 8-bit bit line selectors, each connected to the bit lines of a corresponding one of four levels of NOR memory strings in a 3D memory array.

[0031] In one implementation of the method of FIGS. 1A-1E, for a three-dimensional memory array having eight levels, the four bit line selectors (e.g., bit line selector 150) below each staircase structure have a length of about 35 μm. 2 of semiconductor substrate area required for each 3D memory array. This represents approximately 28% of the semiconductor substrate area under the footprint of each 3D memory array. As the number of levels in the 3D memory array increases, the semiconductor area for the bit line selectors increases proportionally. The semiconductor area required for the bit line selectors in a 3D memory array with 16 or more levels exceeds the footprint of the 3D memory array itself.

[0032] According to one embodiment of the present invention, the bit line selector in the semiconductor substrate for connecting the bit line to the sense amplifier is eliminated by implementing it with a thin film transistor ("vertical TFT") fabricated on the top, bottom or side of the staircase structure. The vertical TFT allows the additional conductor layers required for the bit line connection (e.g., conductor layers 101-1, 101-2, 101-3, 101-4 in Figures 1A and 1B) to be reduced to one. The name vertical TFT is given because in some preferred embodiments, its channel current flows along the Z direction. It should be understood that the designation "vertical" for vertical TFTs is merely a convenient naming convention in this detailed description. As will become clear in the following description, the channel current of a vertical TFT preferably flows along the Z direction to minimize its footprint, but does not have to flow along the Z direction to function as intended.

[0033] 2A shows schemes 201, 202, 203 for providing vertical TFTs, in which the vertical TFTs are provided at corresponding positions on the upper, lower, and lateral sides of the staircase structure 200. As shown in FIG. 2A, in scheme 201, bit lines at the same level of the NOR memory strings of the three-dimensional memory array are connected to corresponding ones of the vertical TFTs fabricated on the upper side of the staircase structure 200 through conductor-filled vias (e.g., conductor-filled vias 105-0, 105-2, 105-4, 105-6 in FIG. 1A) (e.g., vertical TFTs 211-1, 211-3, 211-5, 211-7 connect corresponding bit lines in levels 1, 3, 5, 7, respectively). When the vertical TFTs are switched on, they connect corresponding bit lines to corresponding conductors in the single conductor layer 212. The conductors in conductor layer 212 may be connected to supporting circuitry (eg, sense amplifiers 214) in the semiconductor substrate by other conductors (eg, conductor pillars or local word lines) in the staircase structure 200.

[0034] In the scheme 202, bit lines in the same level of the NOR memory strings of the three-dimensional memory array are connected by available conductors through conductor-filled vias (e.g., conductor-filled vias 105-0, 105-2, 105-4, 105-6 in FIG. 1A) to corresponding ones of the vertical TFTs fabricated under the staircase structure 200 (e.g., vertical TFTs 217-1, 217-3, 217-5, 217-7 connect corresponding bit lines in levels 1, 3, 5, 7, respectively). For each bit line, such available conductors may include a short section of a corresponding first global word line (e.g., global word line 103-4 in FIG. 1A) and a short section of a corresponding local word line (e.g., local word line 104-4). When a vertical TFT is switched on, it connects the corresponding bit line to a corresponding conductor of the single conductor layer 215. The conductors in conductor layer 215 may be selectively connected to supporting circuitry (eg, sense amplifier 214) within the semiconductor substrate.

[0035] In scheme 203, bit lines in the same level of NOR memory strings of the three-dimensional memory array are connected by other conductors through conductor-filled vias (e.g., conductor-filled vias 105-0, 105-2, 105-4, 105-6 in FIG. 1A) to corresponding ones of vertical TFTs fabricated on the lateral sides of the staircase structure 200 (e.g., vertical TFTs 218-1, 218-3, 218-5, 218-7 connect corresponding bit lines in levels 1, 3, 5, 7, respectively). For each bit line, such available conductors may include a short section of a corresponding first global word line (e.g., global word line 103-4 in FIG. 1A) and a short section of a corresponding local word line (e.g., local word line 104-4). When a vertical TFT is switched on, it connects the corresponding bit line to a corresponding conductor of the single conductor layer 216. This conductor is connected to supporting circuitry (eg, sense amplifier 214) within the semiconductor substrate.

[0036] 2B is a cross-sectional view of a vertical TFT 330 according to one embodiment of the present invention. As shown in FIG. 2B, the vertical TFT 330 includes an annular gate electrode 233 (e.g., a polysilicon gate) surrounding a semiconductor structure, which is separated from the annular gate electrode 233 by an annular gate oxide 235. The term "annular" in this specification is intended to mean not only a circular ring, but also any shape of closed outer layer. The semiconductor structure is made of N + Doped drain region 231a, N - doped drain region 231b, channel region 236, N - doped source region 234b, and N + The vertical TFT 330 includes a doped source region 234a. The channel region 236 may be, for example, a p-type body region. When the voltage of the gate electrode 233 exceeds the threshold voltage value of the vertical TFT 330, the vertical TFT 330 becomes conductive and an N + Doped drain region 231a and N + A low resistance current path is provided between the doped source regions 234a.

[0037] 2C is a cross-sectional view of a vertical TFT 350 according to one embodiment of the present invention. As shown in FIG. 2C, the vertical TFT 350 includes an annular gate electrode 233 (e.g., a polysilicon gate) surrounding a semiconductor structure, which is separated from the annular gate electrode 233 by an annular gate oxide 235. The semiconductor structure of the vertical TFT 350 is N-type, similar to the vertical TFT 330 of FIG. 2B. + Doped drain region 231a, N - Doped drain region 231b, N - doped source region 234b, and N + 2B, the vertical TFT 350's channel or p-type body region 236 is annular and surrounds the oxide core 237. When the voltage on the gate electrode 233 exceeds the threshold voltage value of the vertical TFT 350, the vertical TFT 350 becomes conductive and the N + Doped drain region 231a and N + A low resistance current path is provided between the doped source regions 234a.

[0038] 2B and 2C are not drawn to scale. In one embodiment, the gate oxide 235 is 20 nm thick, the gate electrode 233 is 40 nm thick, and the channel length (i.e., length along the Z direction) of the p-type body region 236 is 500 nm. The footprint of the p-type body 236 may be 150 nm by 100 nm (X and Y directions, respectively) such that the channel width, approximated using the perimeter of the footprint, is also 500 nm. With these dimensions, the drain-source current (IDS) capability of the vertical TFT is approximately 2.25 μA when driven with a gate-source voltage (VGS) of 8 volts above the threshold voltage and a drain-source voltage (VDS) of 0.5 volts. As will be described below, if the channel region is a high-quality crystalline semiconductor (e.g., crystallization is enhanced by a metal silicide), the current capability can be significantly increased (e.g., 15 μA) for the above dimensions.

[0039] FIG. 3 illustrates a bitline selector 300 formed using vertical TFTs (i.e., scheme 201) on a staircase structure 320 according to an embodiment of the present invention. As shown in FIG. 3, the bitline selector 300 provides vertical TFTs for connecting to the bitlines of levels 1, 3, 5, and 7 of the staircase structure 320. As will be described below, to efficiently utilize space, two sets of vertical TFTs are provided for the bitlines of each level. One set of vertical TFTs is provided for connecting to the odd bitlines and the other set of vertical TFTs is provided for connecting to the even bitlines. For example, vertical TFT TR0 connects to the odd bitlines 302-1, 302-3, 302-5, and 302-7 of level 7, and vertical TFT TR4 connects to the even bitlines 302-0, 302-2, 302-4, and 302-6 of level 7. Similarly, vertical TFTs TR1, TR2, and TR3 connect to corresponding odd bit lines in levels 5, 3, and 1, respectively, and vertical TFTs TR5, TR6, and TR7 connect to corresponding even bit lines in levels 5, 3, and 1, respectively. This arrangement allows vertical TFTs serving adjacent bit lines to be staggered.

[0040] In one embodiment, each bit line has a width of 50 nm, and adjacent bit lines are spaced 80 nm apart. This results in a bit line pitch of 130 nm. The sense amplifiers serving adjacent bit lines (e.g., sense amplifier 301-0 serving adjacent bit lines 302-0, 302-1 in each of levels 1, 3, 5, and 7) are spaced apart by twice the bit line pitch (i.e., 260 nm). In this embodiment, the vertical TFTs providing the desired drive have a footprint of 150 nm by 100 nm (and a vertical channel length of 500 nm). Thus, in the bit line selector 300, two sets of vertical TFTs serving each level are arranged side-by-side along the Y direction. However, the contacts of the vertical TFTs are staggered such that the vertical TFTs serving adjacent bit lines are within 260 nm (i.e., twice the bit line pitch) of each other. Specifically, in one embodiment, the footprint of each vertical TFT exceeds the pitch of the bit lines in both the X-direction and the Y-direction. By staggering the adjacent vertical TFTs TR0, TR4, the total footprint of two adjacent vertical TFTs fits within an area of ​​320 nm (Y-direction) x 260 nm (X-direction). For a three-dimensional memory array having eight levels with an array length (i.e., the length of each NOR memory string along the Y-direction) of 160 μm, the staircase structure 320 only needs to extend 2 μm along the Y-direction to accommodate the bit line selector 300 of the present invention.

[0041] 4 is a YZ-plane cross-section view of the staircase structure 320 of FIG. 3 through the odd bit lines, according to one embodiment of the present invention. In FIG. 4, for illustrative purposes only, the vertical TFTs TR0 and TR1 are implemented by vertical TFTs of the type described for the vertical TFT 330 of FIG. 2B. Also in FIG. 4, the vertical TFTs TR2 and TR3 are implemented by vertical TFTs of the type described for the vertical TFT 350 of FIG. 2C. Any of the vertical TFTs disclosed herein are suitable for implementing any of the vertical TFTs TR0, TR1, TR2, TR3 shown in FIG. 4. Additionally, each vertical TFT in FIG. 4 includes a N-type TFT to provide good electrical contact. + A thin layer 332 of titanium nitride (TiN) is formed on the doped source region 234a. + A C49 titanium silicide (TiSi2) layer 331 is formed on each vertical TFT adjacent to the doped drain region 231a. As described below, for example, during the annealing step to form the TiSi2 layer, the TiSi2 layer provides a seed layer that initiates crystallization of any adjacent amorphous semiconductor material, resulting in crystallization of the adjacent amorphous semiconductor material. The crystalline semiconductor material thus formed has fewer defects and higher carrier mobility compared to a semiconductor layer crystallized without the presence of a seed layer. Alternatively, the semiconductor layer may be crystallized using a metal silicide, such as nickel silicide. In this alternative method, the metal silicide leaves a crystallized semiconductor behind the wave-front of the metal silicide layer, which has fewer defects and higher mobility.

[0042] 5 is a diagram showing how, in the staircase structure 320, the bit line selection signals are connected to the gate terminals of the corresponding vertical TFTs TR0, TR4, TR1, and TR5 using the global word lines 103-0, 103-4, 103-1, and 103-5, and the drain terminals of the vertical TFTs TR0, TR4, TR1, and TR5 are connected using the conductor layer 212. Note that FIG. 5 shows cross-sectional views in both the XY plane and the YZ plane. As shown in FIG. 5, the selection signals to the vertical TFTs TR0 and TR4 are connected to the bit lines of level 7 of the staircase structure 320 via the first global word lines 103-0 and 103-4, and the selection signals to the vertical TFTs TR1 and TR5 are connected to the bit lines of level 5 of the staircase structure 320 via the first global word lines 103-1 and 103-5. 5 also shows that the first global word line is used to connect to the local word lines, which are typically provided as conductor pillars, in the array portion of the three-dimensional memory array. The drain terminals (e.g., drain terminal 231a) of the vertical TFTs TR0, TR4, TR1, TR5 (and in other levels, vertical TFTs TR2, TR6, TR3, TR7) are provided by the same sense amplifier and connected to a common conductor in conductor layer 212. Thus, unlike the method shown in FIGS. 1A-1E, which requires an additional conductor layer equal to half the levels of the three-dimensional memory array, the method of FIGS. 2-5 requires only one additional conductor layer using vertical TFTs.

[0043] One of the major advantages of the vertical TFTs described herein is that the current flows in the Z direction, i.e., substantially perpendicular to the semiconductor substrate, resulting in a small footprint projected onto the surface of the underlying semiconductor substrate. In this specification, "footprint" refers to the area projected onto the semiconductor substrate when the vertical TFT is viewed from the top. In general, the current that flows through a vertical TFT when it is in the "on" or conductive state is proportional to the charge carrier mobility in its channel region. For the incorporation of vertical TFTs into memory cell operation, a larger "on" current is desired, so it is desirable for the charge carriers in the vertical TFT to have a high mobility.

[0044] The following description, whether or not described above, presents various embodiments of vertical TFTs within the scope of the present invention, and methods of forming such vertical TFTs. Process steps described in one embodiment of this specification can be used in other embodiments, even if those steps are not explicitly described in the context of the other embodiments. When a method of two or more specific steps is referred to herein, such specific steps may be performed in any order or simultaneously, unless otherwise stated herein or required by context. Similarly, such a method may include one or more other steps performed before a specific step, after a specific step, or between any two specific steps.

[0045] FIG. 6 is an isometric view of a plurality of vertical TFTs (e.g., vertical TFT 5) and a memory structure 40 before interconnect conductors are formed on the top of the memory structure 40 and the vertical TFTs including the staircase structure according to an embodiment of the present invention. The staircase structure of the memory structure 40 includes a number of conductor-filled vias (e.g., conductor-filled vias 17), each connected to a bit line (i.e., a common drain region) of each level of the three-dimensional memory array. In FIG. 6, the vertical TFTs are shown next to the staircase structure 40 (as described above with respect to scheme 203 of FIG. 2A). As shown in FIG. 6, the vertical TFTs 5 are electrically connected at their bottoms by a conductive element 15, which may be formed from the same material as the common drain region of the NOR memory string (i.e., a doped semiconductor layer that can be strapped to a metal layer to reduce resistance). This allows the conductive element 15 to be formed simultaneously with the bit lines during the same masking and etching steps. As shown in FIG. 6, the vertical TFT 5 includes a semiconductor pillar 90 concentrically surrounded by a gate oxide layer 100 and a gate electrode layer 110. The semiconductor pillar 90 includes a channel region (not shown) and a source region (not shown) for the vertical TFT 5. The conductive element 15 forms the drain region of the vertical TFT 5. The semiconductor pillar 90, which is substantially perpendicular to the surface of the semiconductor substrate, provides current flow along a vertical direction, which can significantly reduce the area on the semiconductor substrate. The following description includes process steps that enable the semiconductor pillar 90 to have a low crystal defect density and high charge carrier mobility in the channel region of the resulting vertical TFT, thereby providing improved current capability.

[0046] 7A-7L illustrate a fabrication process for forming a vertical TFT according to an embodiment of the present invention. As shown in FIG. 7A, first, a conductive interconnect 10 is formed on top of a semiconductor substrate and substantially parallel to the semiconductor substrate. Suitable materials for the interconnect 10 include molybdenum, cobalt, tungsten, titanium nitride, tantalum nitride, tantalum, titanium, combinations of one or more of the above, and any other suitable conductive material. The interconnect 10 includes a conductor-filled via 20 that allows connection of a staircase structure (e.g., the staircase structure of the memory structure 40 of FIG. 6) to a bitline. The conductive material in the conductor-filled via 20 may be the same as that used for the interconnect 10.

[0047] The interconnects 10 and conductor filled vias 20 are formed using any suitable method, such as, for example, a subtractive method in which a conductive material is deposited and defined by a photolithographic process, as known to those skilled in the art. The conductive material is deposited using any suitable method, such as, for example, evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), or electrochemical deposition, or other suitable method. Etching during the photolithographic process is accomplished using any suitable method, such as, for example, wet acid or base, corrosive gas (e.g., chlorine, bromine, or fluorine), or any suitable etchant. Alternatively, the interconnects 10 and conductor filled vias 20 may be formed using a damascene process, as known to those skilled in the art. In a damascene process, a trench is formed in a dielectric layer (e.g., silicon oxide or silicon nitride) and a suitable conductive material is deposited therein. The excess conductive material deposited on the dielectric layer and elsewhere is then selectively removed using any suitable method, such as, for example, etch-back using corrosive gases, wet acids or bases, or chemical mechanical polishing (CMP), with CMP being the most preferred method for this purpose. The trenches may be formed using any suitable method, such as, for example, anisotropic etching.

[0048] Referring to FIG. 7B-1, after forming the interconnects 10 and the conductor filled vias 20, a first n-type or p-type semiconductor layer 30 (e.g., silicon, germanium, or silicon germanium) is deposited as an amorphous semiconductor layer using any suitable technique (e.g., CVD, ALD, or sputtering). The first semiconductor layer 30 is reserved as a source or drain region of the vertical TFT 5 to be formed thereafter, and therefore, the first semiconductor layer 30 is hereinafter referred to as the "first source or drain layer 30". FIG. 7B-2 shows another view of the structure of FIG. 7B-1. The first source or drain layer 30 is then crystallized, as described below. In one embodiment, the first source or drain layer 30 may be formed simultaneously with the common drain region of the NOR memory string (i.e., formed from the same layer of semiconductor material as the common drain region). FIG. 7C shows an intermediate step of forming a vertical TFT 5 from a plurality of deposited semiconductor and insulating layers in the portion 40B and the three-dimensional memory structure 40A (including both the memory array and one or more steps). The formation of the three-dimensional memory structure (e.g., the memory structure 40A) is disclosed, for example, in the non-provisional patent application. In this intermediate step, the processing for the vertical TFT portion 40B is separated from the processing for the memory structure portion 40A. By using appropriate masking and etching steps, the upper layer of the vertical TFT portion 40B is removed, which stops at the first source or drain layer 30. Other layers (e.g., a metal layer 46 strapped to the first source or drain layer 30, etc.) may be present. The structure of FIG. 7B-1 would result from removing the upper layer from the vertical TFT portion 40B of FIG. 7C.

[0049] Then, as shown in the isometric view of FIG. 7D-1 and the cross-sectional view of FIG. 7D-2, after forming the first source or drain layer 30, a mold dielectric layer 50 (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxygen hydrogen carbide, fluorine doped silicon oxide, boron doped silicon oxide, or phosphorus doped silicon oxide, or any combination of these materials) is deposited on the first source or drain layer 30 using any suitable method, such as CVD, ALD, or spin-on.

[0050] The mold dielectric layer 50 is masked, patterned, and etched to form vias that expose the first source or drain layer 30. Then, as shown in the isometric view of FIG. 7E-1 and the cross-sectional view of FIG. 7E-2, after removing excess semiconductor material from the surface of the mold dielectric layer 50 using any suitable process such as etch-back or CMP, most preferably CMP, a second semiconductor layer 60 (e.g., silicon, germanium, or silicon germanium) is deposited in the vias using any suitable technique (e.g., CVD, ALD, or sputtering). The second semiconductor layer 60 is reserved as a channel region of the vertical TFT 5 to be formed subsequently, and therefore, the second semiconductor layer 60 is hereinafter referred to as a channel layer 60. The semiconductor layer 60 is preferably deposited as an amorphous semiconductor material.

[0051] The channel layer 60 may be doped in situ with the same or different conductivity type as the first source or drain layer 30. Then, as shown in the isometric view of FIG. 7F-1 and the cross-sectional view of FIG. 7F-2, a portion of the channel layer 60 may be doped using a non-in situ doping step (e.g., gas diffusion or ion implantation) to create a third semiconductor layer 70. Most preferably, the third semiconductor layer 70 is doped with the same conductivity type as the first source or drain layer 30. Since the third semiconductor layer 70 is reserved as another source or drain region of the vertical TFT 5 to be formed subsequently, the third semiconductor layer 70 will be referred to as the second source or drain layer 70 in the following.

[0052] If the first source or drain layer 30, the channel layer 60, and the second source or drain layer 70 comprise amorphous silicon as deposited, then a thin titanium (Ti) layer 72 (e.g., about 10 nm thick) is deposited on the second source or drain layer 70, with or without a protective layer 74 (e.g., titanium nitride or any other suitable material) deposited on the titanium layer 72. The resulting structure with the protective layer 74 deposited is shown in an isometric view in FIG. 7G-1 and in a cross-sectional view in FIG. 7G-2. The protective layer 74 is preferably deposited immediately after the deposition of the titanium layer 72. The resulting structure is then annealed in an inert atmosphere (e.g., nitrogen or argon) at a temperature suitable for crystallization of the amorphous silicon (e.g., at a temperature in the range of 550-1000° C. for 1 second to 24 hours). Alternatively, annealing may be performed at 550° C. for 24 hours, 600° C. for 12 hours, 750° C. for 5 minutes, or 800° C. for 1 minute, or any suitable temperature and time that crystallizes the silicon into high quality single crystal or polycrystalline silicon.

[0053] During the annealing process, the titanium layer 72 reacts with the underlying silicon to form titanium silicide 80. This provides a crystalline template suitable for the formation of crystalline silicon having a low defect concentration in the first source or drain layer 30, the channel layer 60, and the second source or drain layer 70 (see FIGS. 7H-1 and 7H-2). The resulting crystalline silicon having a low defect concentration contains carriers with higher mobility than conventional polycrystalline semiconductor materials known to have high defect concentrations.

[0054] According to a second embodiment, a thin nickel layer is deposited on the second source or drain layer 70 rather than a titanium layer 72. After nickel deposition, the structure is annealed at a low temperature (e.g., between about 350° C. and about 450° C.). During the anneal, a nickel silicide film is formed and diffuses through the second source or drain layer 70, the channel layer 60, and the first source or drain layer 30, thereby inducing the amorphous silicon in these semiconductor layers to crystallize into a low defect concentration form. The process is complete when the nickel silicide film reaches the outer silicon boundary of the structure.

[0055] As shown in isometric view in Figure 7H-1 and cross-sectional view in Figure 7H-2, titanium layer 72 and protective layer 74 are then removed by a selective wet etch (e.g., a combination of hydrogen peroxide and sulfuric acid). Titanium silicide film 80 is left behind, although in some embodiments titanium silicide film 80 is removed using other means. In some embodiments, formation of the crystalline semiconductor layer occurs at a later step in the fabrication sequence.

[0056] At this point, the semiconductor pillar 90 (i.e., the combination of the titanium silicide film 80, the crystallized channel layer 60, the crystallized first source or drain layer 30, and the second source or drain layer 70) is largely complete. Next, as shown in FIG. 7I, the mold dielectric layer 50 around the semiconductor layer 90 is etched to form a trench that extends the majority of the length of the semiconductor pillar 90. Next, as shown in the isometric view of FIG. 7J-1 and the cross-sectional view of FIG. 7J-2, a gate oxide 100 is conformally deposited using any suitable technique (e.g., CVD, ALD, or thermal oxidation) on the exposed surfaces of the semiconductor pillar 90 and the bottom of the trench. The gate oxide 100 can be any suitable material, such as, for example, silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, hafnium silicon oxide, or any combination of two or more of these materials.

[0057] A gate electrode layer 110 (e.g., titanium nitride, tantalum nitride, tungsten, or any combination of two or more thereof, or any suitable material) is then deposited on the gate oxide 100 to completely fill the remainder of the trench with the gate electrode layer 110 and to deposit the gate electrode layer 110 on any exposed areas. Any gate electrode and gate oxide material in exposed areas outside the trench is selectively removed using any suitable technique, such as, for example, etch-back or CMP. As shown in the isometric view of FIG. 7K-1 and the cross-sectional view of FIG. 7K-2, after selectively removing the gate electrode layer 110 and gate oxide 100, a surface 130 of the semiconductor pillar 90 and a surface 120 of the gate electrode layer 110 are exposed.

[0058] A dielectric layer is first deposited on the exposed portions of the gate electrode layer 110, the gate oxide 100, and the second source or drain layer 70. The dielectric layer is then patterned and etched to form vias that expose the surface 120 of the gate electrode layer 110 and the surface 130 of the second source or drain layer 70, and to provide trenches for interconnect conductors. The vias and trenches are then filled with a conductive material to form interconnects 150 that electrically connect the gate electrode layer 110 and the second source or drain layer 70 through the conductor-filled vias 140, as shown in FIG. 7L. At this point, the vertical TFT 135 is largely complete. Because the channel layer 60 has been crystallized in the presence of the metal silicide layer, the channel layer 60 has a lower concentration of crystal defects and a higher carrier mobility than a conventional polycrystalline semiconductor layer. The increased carrier mobility in the channel allows for a higher current in the vertical TFT in the conductive state.

[0059] FIG. 8 illustrates a vertical TFT 850 according to an embodiment of the present invention. Unlike the vertical TFT 135 of FIG. 7L, which has a rectangular cross-section in the XY plane, the vertical TFT 850 has a circular cross-section in the XY plane. The vertical TFT 850 may be used to implement the vertical TFT 5 of FIG. 6. The inset 830 is a partial isometric view of the vertical TFT 850 to more clearly show the first source or drain layer 30, the channel layer 60, the gate oxide layer 100, and the gate electrode layer 110. The fabrication steps of the vertical TFT 850 with a circular cross-section are substantially the same as the fabrication steps of the vertical TFT 5 of FIG. 7L, which has a rectangular cross-section.

[0060] 9A-9H show another method of fabricating a vertical TFT 850 according to an embodiment of the present invention. As shown in FIG. 9A, a via 901 is formed in a mold dielectric layer 50, thereby exposing a surface of the first source or drain layer 30. Next, as shown in the isometric view of FIG. 9B, an insulating layer 36 is conformally deposited on the via 901, thereby completely covering all exposed portions of the first source or drain layer 30 in the via 901. The insulating layer 36 is any suitable dielectric (e.g., about 10 nm of silicon oxide). Then, as shown in the isometric view of FIG. 9C, a gate electrode layer 110 is conformally deposited on the insulating layer 36. Next, as shown in the isometric view of FIG. 9D, an anisotropic etch is performed to remove portions of the gate electrode layer 110 and the insulating layer 36, thereby exposing the surface 102 of the first source or drain layer 30. This leaves the gate electrode layer 110 on the sidewalls of the via 901 with a thickness of most of its original thickness.

[0061] Next, as shown in the isometric view of FIG. 9E, a gate oxide layer 100 is conformally deposited on the gate electrode layer 110 and on the surface 102 of the first source or drain layer 30. Next, as shown in FIG. 9F, a portion of the gate oxide layer 100 is removed by anisotropic etching to expose the surface 102 of the first source or drain layer 30. Next, as shown in FIG. 9G, a channel layer 60 is deposited in an amorphous form in the via 901 to contact the first source or drain layer 30. Then, a portion of the channel layer 60 is removed from the top surface using CMP. Next, as shown in FIG. 9G, a second source or drain layer 70 is formed by doping the top surface portion of the channel layer 60 with a dopant having a different concentration or a different conductivity type than the channel layer 60. Next, any amorphous semiconductor material contained in the first source or drain layer 30, the second source or drain layer 70, and the channel layer 60 is crystallized by first depositing a titanium film on the surface 71 of the second source or drain layer 70, and then annealing at a temperature above 550° C. This forms a TiSi2 seed layer that serves as a seed for the crystallization of the channel layer 60 and the first and second source or drain layers 30, 70 in the manner described above, thereby obtaining minimal crystal defects and high carrier mobility in these semiconductor layers.

[0062] Thereafter, interconnections and other operations to electrically connect to the gate electrode layer 110 and the second source or drain layer 70 can be accomplished in the manner described above.

[0063] 10 is a diagram showing a vertical TFT 280 according to an embodiment of the present invention. As shown in FIG. 10, the vertical TFT 280 includes (i) a first highly doped source or drain layer 200a and a second highly doped source or drain layer 200b separated from each other by a dielectric layer 210, (ii) a lightly doped channel layer 220 in contact with both the first highly doped source or drain layer 200a and the second highly doped source or drain layer 200b, (iii) a gate oxide layer 230 in contact with the channel layer 220, and (iv) a gate electrode layer 240 in contact with the gate oxide layer 230. A conductor contact 250 provides individual contacts to the first highly doped source or drain layer 200a, the second highly doped source or drain layer 200b, and the gate electrode layer 240, respectively. In the vertical TFT 280, the channel layer 220 is fabricated such that charge carriers travel in a direction substantially perpendicular to the semiconductor substrate on which the vertical TFT 280 is fabricated (i.e., the Z-direction). The channel layer 220 may be initially deposited as an amorphous semiconductor material. The conductor contact 250 may also include a titanium or nickel layer in contact with either or both of the highly doped source or drain layers 200a, 200b. The titanium or nickel layer seeds the crystallization of any amorphous silicon in the channel layer 220 to a crystalline state with fewer crystal defects, thereby improving charge carrier mobility in the channel layer 220.

[0064] 11A-11F show a process for fabricating the vertical TFT 280 of FIG. 10 according to an embodiment of the present invention. As shown in FIG. 11A, a first highly doped source or drain layer 200a, a dielectric layer 210, and a second highly doped source or drain layer 200b are successively deposited as amorphous semiconductor materials. The resulting structure is then patterned and etched to form rectangular lines or strips as shown in FIG. 11A. A channel layer 220 is then deposited as amorphous semiconductor material on the structure shown in FIG. 11A, followed by sequential deposition of a gate oxide layer 230 and a gate electrode layer 240 on the strip. The resulting structure (structure 290) is then patterned and etched using photolithography steps to form lines where the channel layer 220, gate oxide layer 230, and gate electrode layer 240 wrap around the strip, as shown in FIG. 11B.

[0065] A dielectric layer 255 is then deposited on the structure 290 for passivation, as shown in FIG. 11C. FIG. 11D shows a cross section of the structure 290 through the semiconductor channel layer 220, the gate oxide layer 230, and the gate electrode layer 240. The dielectric layer 255 is then etched to form a via 260, thereby exposing a surface 270 of the gate electrode layer 240. Concurrently or alternatively, the passivation layer 255 may be etched to form a second via (not shown) to expose a portion of the second source or drain layer 200b. A conductor contact layer 250 (e.g., titanium or nickel) is then deposited in the via 260 to contact the surface 270. Concurrently or alternatively, a conductor contact layer may be deposited to contact the exposed portion of the second source or drain layer 200b. The titanium or nickel is deposited and the structure 290 is then annealed. This allows the TiSi2 or NiSi layer to form and seed the crystallization of the first highly doped source or drain layer 200a, the second highly doped source or drain layer 200b, and any adjacent semiconductor material in the channel layer 220 into a crystalline form with minimal crystal defects. If desired, optional additional conductor contacts 250 may be formed to contact the first highly doped source or drain layer 200a and the second highly doped source or drain layer 200b, as shown in FIG.

[0066] 12A-12K show a vertical TFT 1220 having high mobility connected to a memory cell of a NOR memory string of a memory structure 1210 according to yet another embodiment of the present invention. As mentioned above, a TFT with a vertical channel occupies less silicon area than a TFT with a horizontal channel. In this regard, the silicon area occupied by a TFT is the area that the TFT projects onto the surface of a planar substrate. In the embodiment shown in FIG. 12A-12K, the vertical TFT 1220 has critical dimensions that are both self-aligning and self-limiting, and therefore can be formed using only two masking steps. The reduced number of masking steps results in reduced fabrication costs and improved fabrication uniformity and consistency. Because the magnitude of the current through a vertical TFT in a conducting ("on") state is proportional to the charge carrier mobility, and because a larger "on" current is desired when such a vertical TFT operates in conjunction with a NOR memory string in memory structure 1210, a higher charge carrier mobility is desirable in the channel region of such a vertical TFT.

[0067] In connection with the following description, FIGS. 12A-12C are shown in isometric views, and FIGS. 12D-12K are shown in partial isometric views. As shown in FIG. 12A, a memory structure 1210 including an array of NOR memory strings is provided on a planar surface of a semiconductor substrate. The semiconductor substrate may include circuit devices (not shown) connected to the memory structure 1210. In FIG. 12A, vertical TFTs 1220 are provided in the memory structure 1210 and are connected to bit lines of the NOR memory strings of the memory structure 1210 by conductor filled vias 1230. Each bit line is a strip of highly doped semiconductor material that forms a common drain terminal for the memory transistors of the NOR memory string. As shown in FIG. 12A, for illustrative purposes, each bit line is connected to two vias 1230. In practice, any suitable number of vias may be connected to each bit line. Also, because the vertical TFT 1220 is located in the stepped portion of the memory structure 1210 , the vertical TFT 1220 does not occupy any silicon area not already occupied by the memory structure 1210 .

[0068] Formation of the vertical TFT 1220 begins after forming the vias 1230 using any suitable method, such as those described above or disclosed in the provisional patent application. A conductive semiconductor layer 1240 is then deposited, patterned, and etched into separate sections that are electrically isolated from one another. The conductive semiconductor layer 1240 may be n-type or p-type. Also, the conductive semiconductor layer 1240 may include silicon, silicon germanium, germanium, or any suitable semiconductor material deposited using any suitable technique (e.g., CVD, ALD, or sputtering). As shown in FIG. 12A, each section of the conductive semiconductor layer 1240 is electrically connected to a bit line of a NOR memory string of the memory structure 1210 through two conductive filled vias 1230.

[0069] To facilitate the following detailed description, the formation of the vertical TFT 1220 will be described with reference to a single section of the conductive semiconductor layer 1240 shown in FIG. 12B. This section of the conductive semiconductor layer 1240 will be referred to as the "first source or drain layer 1240" hereinafter, considering that it will form the source or drain region of the vertical TFT to be formed subsequently. After the first source or drain layer 1240 is formed as shown in FIG. 12B, a dielectric layer 1250 is deposited thereon (FIG. 12C). The dielectric layer 1250 may include any suitable dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, silicon oxycarbide, and silicon oxycarbide hydride) and may be deposited using any suitable technique (e.g., CVD or PVD). The dielectric layer 1250 is then patterned and etched to form two cavities, a channel cavity 1260 and a gate cavity 1270. In these cavities, channel regions and gate electrodes for the two vertical TFTs to be formed respectively are formed. The width of the gate cavity 1270 is much narrower than the width of the channel cavity 1260. The channel cavity 1260 and the gate cavity 1270 each extend the entire length of the dielectric layer 1250 to the first source or drain layer 1240.

[0070] Next, as shown in a partial isometric view in FIG. 12D, an etch stop layer 1280 (e.g., a silicon nitride layer having a thickness of about 10 nm) is conformally deposited inside the channel cavity 1260 and the gate cavity 1270 and on the dielectric layer 1250. Then, as shown in FIG. 12E, a sacrificial layer 1290 (e.g., a silicon oxide layer having a thickness of about 30 nm) is conformally deposited on the etch stop layer 1280. Both the etch stop layer 1280 and the sacrificial layer 1290 may be deposited using any suitable technique (e.g., CVD or ALD). In FIG. 12E, the gate cavity 1270 is mostly filled after deposition of the etch stop layer 1280 and the sacrificial layer 1290 due to its narrow width, while the channel cavity 1260 is left with an open shaft.

[0071] 12F, an anisotropic etch ("punch-through etch") is then used to remove portions of the etch stop layer 1280 and the sacrificial layer 1290, thereby exposing a surface 1300 of the first source or drain layer 1240 to the channel cavity 1260. The punch-through etch leaves the etch stop layer 1280 and the sacrificial layer 1290 on the sidewalls of the channel cavity 1260 and on the sidewalls of the gate cavity 1270.

[0072] Thereafter, as shown in FIG. 12G and the inset in FIG. 12G, a channel layer 1310 (e.g., an amorphous silicon, silicon germanium, germanium, or other semiconductor film having an appropriate n-type or p-type) is deposited using any suitable technique (e.g., CVD, ALD, or sputtering) to fill the channel cavity 1260. The channel layer 1310 is in electrical contact with the conductive semiconductor layer 1240 at the surface 1300. The channel layer 1310 may be doped in situ during deposition. A portion of the channel layer 1310 may be removed from the top surface of the dielectric layer 1250 using either an etch-back operation or CMP.

[0073] The channel layer 1310 is then crystallized using any suitable technique (e.g., a crystallization process in the presence of titanium or nickel silicide, as described above) to form a semiconductor pillar with a low crystal defect concentration. This results in high charge carrier mobility and substantial current. For example, the channel layer 1310 may be crystallized in the presence of TiSi2, which results from reaction of the thin titanium layer 1320 with the channel layer 1310 during annealing. Optionally, a protective layer (not shown) may be deposited on the channel layer 1310. The protective layer may be titanium nitride or other suitable material. The structure is then annealed in an inert atmosphere (e.g., nitrogen or argon) until a suitable crystallization temperature is reached (e.g., at a temperature in the range of 550-1000°C, for 1 second to 24 hours; specifically, 550°C for 24 hours, 600°C for 12 hours, 750°C for 5 minutes, or 800°C for 1 minute, or any suitable annealing conditions). 12H, during annealing, a portion of titanium layer 1320 reacts with the semiconductor of channel layer 1310 to form titanium silicide layer 1330. In this process, titanium silicide layer 1330 forms before crystallization of channel layer 1310 is complete, providing a suitable crystalline template for forming a crystalline semiconductor with high carrier mobility and low defect concentration.

[0074] Next, as shown in FIG. 12I, a portion of the crystallized channel layer 110 is doped by ion implantation to form a second highly doped source layer or highly doped drain layer 1345. Then, annealing is performed as necessary to activate the implanted dopant atoms. Also, the annealing causes the dopant atoms of the first source layer or drain layer 1240 to diffuse into the channel layer 1310, forming a lightly doped drain (LDD) region 1340. The LDD region 1340 has a dopant concentration that is smaller than the dopant concentration of the first source layer or drain layer 1240 and the second source layer or drain layer 1345, and larger than the dopant concentration of the channel layer 1310.

[0075] Referring to FIG. 12J, the sacrificial layer 1290 is then removed by a selective etch (e.g., hydrofluoric acid, which removes silicon oxide much more quickly than silicon nitride). Then, referring to FIG. 12K, that portion of the sacrificial layer 1290 is removed and the gate cavity 1270 is partially filled by conformally depositing or growing a gate dielectric layer 1350 (e.g., silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide). The gate dielectric layer 1350 is 3-100 nm thick, specifically 5-20 nm thick. The gate cavity 1270 is then filled with any suitable conductive material (e.g., doped silicon, doped silicon germanium, doped germanium, titanium, titanium nitride, tungsten, tungsten nitride, tungsten carbide, tungsten carbide nitride, tantalum, or tantalum nitride, or any combination thereof), as shown in FIG. 12K by gate electrode or conductor layer 1360. Excess material of the gate conductor layer 1360 (exposed by removal of the sacrificial layer 1290) overlying the top surface of the etch stop layer 1280 may be removed using etch-back or CMP. Separate contacts may then be provided to both the gate conductor layer 1360 and the channel layer 1310, as shown in FIG. 12A. At this point, the vertical TFT 1220 of FIG. 12A is largely fabricated. In each vertical TFT, the first source or drain layer 1240 and the LDD layer 1340 together function as a drain region (or alternatively as a source region), the second source or drain layer 1345 functions as a source region (or alternatively as a drain region), the channel layer 1310 functions as a channel region, the gate dielectric layer 1350 functions as a gate dielectric material, and the gate conductor layer 1360 functions as a gate electrode.

[0076] FIG. 13 shows the vertical TFT of FIGS. 12A to 12K with some of the dielectric layers removed for clarity.

[0077] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to limit the present invention. Various modifications and variations are possible within the scope of the present invention. The gist of the present invention is set forth in the appended claims.

Claims

1. 1. A memory circuit, comprising: a semiconductor substrate having a planar surface, the semiconductor substrate having circuitry for operating a memory fabricated at locations on the planar surface; an array of memory cells in a memory array formed in a memory structure formed on the planar surface, the memory structure including a first conductor layer, the first conductor layer of the memory structure having one or more conductors each extending along a first direction substantially parallel to the planar surface and carrying electrical signals to or from the memory cells; a selection circuit including one or more transistors fabricated above, to the side of, or below corresponding ones of the conductors of the first conductor layer and above the memory operating circuitry fabricated at locations on the planar surface of the semiconductor substrate; each of the transistors of the selection circuit includes a first drain or source region, a second drain or source region, and a gate region, each formed from a semiconductor material or a conductive material, electrically connected to a corresponding one of the conductors when a control signal causes the transistor to be in a conductive state; The first conductor layer of the memory structure is provided in a staircase structure having two or more steps; the first conductor layer is provided on one of the steps, the memory cells are organized into a plurality of levels, each level having a plurality of NOR memory strings; the conductors of the first conductor layer form a common bit line for the NOR memory strings; each step of the staircase structure includes the common bit line of a corresponding level of the NOR memory string; the transistors of the selection circuit connected to the common bit line at each of the steps of the staircase structure form a bit line selector for the common bit line; the transistors of each bit line selector form a first group and a second group; adjacent bit lines selected by the bit line selector are provided by the first group of transistors and the second group of transistors; A memory circuit in which contacts to the first group of transistors are staggered relative to contacts to the second group of transistors.

2. 2. The memory circuit of claim 1, one of the first drain or source region and the second drain or source region is formed adjacent a metal silicide layer; A memory circuit in which each transistor of the selection circuit selectively connects the corresponding one of the conductors in the first conductor layer to the circuitry for operating the memory.

3. 3. The memory circuit of claim 2, The memory circuit, wherein the metal silicide layer comprises titanium silicide or nickel silicide.

4. 2. The memory circuit of claim 1, an interconnect layer having a plurality of conductors; A memory circuit in which each of the conductors of the interconnect layer is electrically connected to one or more of the transistors of the selection circuit, such that when the transistors of the selection circuit are in a conductive state, the conductors of the interconnect layer are electrically connected to the conductors of the memory structure that correspond to the transistors.

5. 2. The memory circuit of claim 1, further comprising a second conductor layer within the memory array having a plurality of conductors; each of the first drain regions or source regions of the transistors of the selection circuit is connected to a corresponding one of the conductors of the second conductor layer; A memory circuit, wherein each of the second drain or source regions of the transistors of the selection circuit is connected to a corresponding one of the conductors of the first conductor layer.

6. 2. The memory circuit of claim 1, A memory circuit, wherein each of said staircase structures is disposed in a portion of said memory structure separated from said array of said memory cells.

7. 2. The memory circuit of claim 1, the transistors of the selection circuit, which are formed on the first conductor layer and which, when in a conductive state, electrically connect the conductors of the first conductor layer, are arranged in two columns; The memory circuit, wherein the transistors in each column extend along a second direction that is substantially parallel to the planar surface and substantially perpendicular to the first direction.

8. 2. The memory circuit of claim 1, further comprising a set of interconnect lines; A memory circuit in which a terminal of the gate region of each transistor of the selection circuit is connected to one of the interconnect lines.

9. 2. The memory circuit of claim 1, A memory circuit in which, when a current is present in a channel region of one of the transistors of the selection circuit, the current flows in a direction substantially perpendicular to the planar surface.

10. 2. The memory circuit of claim 1, The memory circuit, wherein the semiconductor material comprises one or more of polycrystalline silicon, polycrystalline silicon germanium, single crystal silicon, and single crystal silicon germanium.

11. 2. The memory circuit of claim 1, further comprising a set of interconnect lines; A memory circuit, wherein the first drain region or source region of each of the transistors of the selection circuit is connected to one of the interconnect lines.

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