Catalyst-promoted pattern transfer technology

Abstract

To provide semiconductor element architectures and manufacturing techniques that improve the reliability of catalyst-enhanced chemical etching (CICE).SOLUTION: The CICE, with applications to three-dimensional memory architectures and transistors, is a catalyst-based etching method that can be used for semiconductors and multilayer semiconductors and uses catalysts to etch semiconductor substrates and produce (shape) high-aspect-ratio features. The catalyst usually assists the chemical etching locally by digging into the substrate in the presence of an etching or oxidizing agent.SELECTED DRAWING: Figure 8C

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 591,326, filed November 28, 2017, entitled "FORMATION OF THREE-DIMENSIONAL MEMORY ARCHITECTURES USING CATALYST MESH PATTERNS," U.S. Provisional Patent Application No. 62 / 665,084, filed May 1, 2018, entitled "MULTILAYER ELECTROCHEMICAL ETCH PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION," U.S. Provisional Patent Application No. 62 / 701,049, filed June 20, 2018, entitled "CATALYST-BASED ELECTROCHEMICAL ETCH PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION," and U.S. Provisional Patent Application No. 62 / 729,361, filed September 10, 2018, entitled "CATALYST-ASSISTED CHEMICAL ETCH TECHNIQUES: APPLICATIONS IN SEMICONDUCTOR DEVICES," all of which are incorporated herein by reference for all purposes.

[0002] (Statement Regarding Federally Sponsored Research) This invention was made with government support under Grant No. EEC1160494 awarded by the National Science Foundation and Grant No. FA8650-15-C-7542 awarded by the Air Force Research Laboratory. The U.S. Government has certain rights in this invention.

[0003] (Technical field) Various embodiments of the present technology relate generally to semiconductor device architecture and fabrication techniques. More specifically, some embodiments of the present technology relate to silicon etching using catalytically promoted chemical etching techniques with applications to three-dimensional memory architectures and transistors. [Background technology]

[0004] Semiconductor manufacturing of various transistors, memory, integrated circuits, photonic devices, and other semiconductor elements has led to the proliferation of modern computing devices and other electronic systems. For example, computers, cell phones, automobiles, consumer electronics, etc. are all direct products of advances in semiconductor manufacturing. An essential part of the manufacturing (fabrication) of these devices is pattern transfer. Dry plasma etching processes used in the semiconductor industry to anisotropically etch highly controlled nanopatterns require expensive vacuum equipment and do not easily preserve cross-sectional shapes when patterning high aspect ratios. They suffer from etching challenges such as aspect ratio dependent etching (ARDE) and etch taper. Summary of the Invention

[0005] Various embodiments of the present technology relate generally to memory architectures and manufacturing techniques. More specifically, some embodiments of the present technology relate to silicon etching using catalytically promoted chemical etching techniques with application to three-dimensional memory architectures and transistors.

[0006] In one embodiment of the present technology, a method for preventing substantial collapse of a plurality of high aspect ratio semiconductor structures by catalyst-promoted chemical etching includes patterning a catalyst layer on a surface of a semiconductor material, where the catalyst layer includes an intended design and a plurality of lithographic links. Further, the plurality of lithographic links substantially connect one or more isolated features of the catalyst layer and / or the semiconductor material. The method further includes exposing the patterned catalyst layer on the surface of the semiconductor material to an etchant, where the patterned catalyst layer causes etching of the semiconductor material to form a plurality of interconnected high aspect ratio structures.

[0007] In another embodiment of the present technology, a method of preventing substantial collapse of a plurality of high aspect ratio semiconductor structures includes creating a structure with a capping material deposited either on a patterned catalytic layer or on top of a low height structure. The method further includes exposing the structure to an etchant. The method further includes forming a plurality of high aspect ratio semiconductor structures by using a catalytic chemical etch on the structure with the capping material to prevent substantial collapse of the plurality of high aspect ratio semiconductor structures.

[0008] In a further embodiment of the present technique, an apparatus for catalytically promoted chemical etching includes a plurality of sensors configured to detect an etching condition of a semiconductor material.

[0009] In another embodiment of the present technology, a method of making a plurality of substantially undisrupted alternating multi-layer stacked nanostructures includes creating a material stack comprising two or more layers of alternating semiconductor films, where each of the two or more layers of the alternating semiconductor films differs from the others in at least one of material, doping concentration, and dopant material, and further includes etching the material stack by catalytically promoted chemical etching such that the layers with different properties produce a plurality of etched nanostructures differing in at least one of morphology, porosity, etching rate, and thermal treatment rate.

[0010] In a further embodiment of the present technology, a method of making substantially undisrupted alternating multi-layer stacked features includes creating a material stack comprising two or more layers of alternating semiconductor films, where each of the two or more layers of the alternating semiconductor films differs from the others in at least one of material, doping concentration, and dopant material. The method further includes etching the material stack with a crystal orientation dependent etch to form a taper along a crystal plane. The method further includes etching the taper along a crystal plane to expose one of the two or more layers of the alternating semiconductor films during etching of a portion of the other layers to create a step structure.

[0011] Embodiments of the present technology also include a computer-readable storage medium that includes a set of instructions for causing one or more processors to perform the methods, method variations, and other operations described herein.

[0012] While multiple embodiments are disclosed, still other embodiments of the present technology will become apparent to those skilled in the art from the following detailed description, which shows and describes exemplary embodiments of the technology. As will be understood, the present technology can be modified in various ways without departing from the scope of the technology. Thus, the drawings and detailed description should be regarded as illustrative in nature and not restrictive.

[0013] Embodiments of the present technology will be described and explained with the aid of the accompanying drawings. [Brief description of the drawings]

[0014] [Figure 1A] FIG. 1 illustrates a Jet and Flash Imprint Lithography (J-FIL) enabled catalytically promoted chemical etching (CICE) for shaped nanowires in accordance with one or more embodiments of the present technology. [Figure 1B] 1B is a cross-sectional view of fabricating nanowires using the steps described in FIG. 1A in accordance with one or more embodiments of the present technology. [Diagram 2] FIG. 1 illustrates a SiSE (silicon superlattice etch) process control in accordance with one or more embodiments of the present technology. [Figure 3A] FIG. 1 illustrates a steep interface between porous and non-porous layers after SiSE on a substrate comprising alternating layers of epitaxial silicon with different doping concentrations, in accordance with one or more embodiments of the present technique. [Figure 3B] FIG. 1 illustrates a steep interface between porous and non-porous layers after SiSE on a substrate comprising alternating layers of epitaxial silicon with different doping concentrations, in accordance with one or more embodiments of the present technique. [Figure 4]FIG. 1 shows an SEM cross-section of silicon nanowires made with gold and platinum catalysts, with a magnified image of the catalyst mesh at the bottom of the nanostructure, in accordance with one or more embodiments of the present technology. [Figure 5A] 1A-1D illustrate a method of simultaneously connecting one or more isolated catalyst and high aspect ratio (HAR) nanostructures using connecting links of catalyst material and semiconductor structures, in accordance with one or more embodiments of the present technique. [Figure 5B] 1A-1C are top-down views illustrating connected regions that define high aspect ratio structures remaining after SiSE and non-connected regions that represent the geometry of catalytic features in accordance with one or more embodiments of the present technique. [Figure 6A] FIG. 2 illustrates a process chamber configuration of a CICE in accordance with one or more embodiments of the present technique. [Figure 6B] FIG. 2 illustrates a process chamber configuration of a CICE in accordance with one or more embodiments of the present technique. [Figure 6C] FIG. 2 illustrates a process chamber configuration of a CICE in accordance with one or more embodiments of the present technique. [Figure 6D] FIG. 2 illustrates a process chamber configuration of a CICE in accordance with one or more embodiments of the present technique. [Figure 6E] FIG. 2 illustrates a process chamber configuration of a CICE in accordance with one or more embodiments of the present technique. [Figure 7A] FIG. 1 illustrates an embodiment of an MSP-CICE processing chamber having a horizontal substrate, in accordance with one or more embodiments of the present technique. [Figure 7B] FIG. 1 illustrates an embodiment of an MSP-CICE processing chamber having a horizontal substrate, in accordance with one or more embodiments of the present technique. [Figure 8A] FIG. 1 illustrates an embodiment of an MSP-CICE tool setup in accordance with one or more embodiments of the present technology. [Figure 8B] FIG. 2 illustrates an example of a detailed processing chamber layout, in accordance with one or more embodiments of the present technique. [Figure 8C] FIG. 1 illustrates an example process flow in accordance with one or more embodiments of the present technology. [Figure 9] FIG. 1 illustrates a genetic algorithm-based controller that can be used to determine optimal process parameters for a target output in accordance with one or more embodiments of the present technique. [Figure 10A] FIG. 1 illustrates an example of a catalyst mesh according to one or more embodiments of the present technology. [Figure 10B] FIG. 1 illustrates an example of a catalyst mesh according to one or more embodiments of the present technology. [Figure 10C] FIG. 1 illustrates an example of a catalyst mesh according to one or more embodiments of the present technology. [Figure 10D] FIG. 1 illustrates an example of a catalyst mesh according to one or more embodiments of the present technology. [Figure 10E] FIG. 1 illustrates an example of a catalyst mesh according to one or more embodiments of the present technology. [Figure 11] FIG. 11 illustrates a process flow for HAR etching of slits and channels with a catalytic mesh pattern similar to that shown in FIG. [Figure 12] FIG. 1 illustrates a sacrificial processing flow for vertical channel 3D NAND in accordance with one or more embodiments of the present technology. [Figure 13] FIG. 1 illustrates a process flow and various paths for creating a 3D NAND array with SiSE in accordance with one or more embodiments of the present technology. [Figure 14] FIG. 1 illustrates a portion of a process flow for processing alternating layers of porous and non-porous silicon layers produced by SiSE to create a vertical channel 3D NAND array, in accordance with one or more embodiments of the present technology. [Figure 15] FIG. 1 illustrates a portion of a process flow for processing alternating layers of porous and non-porous silicon layers produced by SiSE to create a vertical channel 3D NAND array, in accordance with one or more embodiments of the present technology. [Figure 16] FIG. 1 illustrates a portion of a process flow for processing alternating layers of porous and non-porous silicon layers produced by SiSE to create a vertical channel 3D NAND array, in accordance with one or more embodiments of the present technology. [Figure 17] FIG. 1 illustrates an embodiment of a 3D NAND architecture with vertical gates and horizontal silicon channels in accordance with one or more embodiments of the present technology. [Figure 18A] FIG. 1 illustrates a layout and dimensions of a 3D NAND in accordance with one or more embodiments of the present technology. [Figure 18B] FIG. 1 illustrates a layout and dimensions of a 3D NAND in accordance with one or more embodiments of the present technology. [Figure 18C] FIG. 1 illustrates a layout and dimensions of a 3D NAND in accordance with one or more embodiments of the present technology. [Figure 19A] FIG. 17 illustrates an exemplary manufacturing template for producing the patterns shown in FIGS. 18A-18C. [Figure 19B] FIG. 17 illustrates an exemplary manufacturing template for producing the patterns shown in FIGS. 18A-18C. [Figure 19C] FIG. 17 illustrates an exemplary manufacturing template for producing the patterns shown in FIGS. 18A-18C. [Figure 19D] FIG. 1 provides an example of a lithographic link pattern where the links are made by imprint lithography (the template is made by electron beam lithography) and the dots are aligned and printed using imprint or photolithography, or vice versa. [Figure 20] 1A-1D illustrate exemplary photolithography processing steps for patterning a CICE catalyst, in accordance with one or more embodiments of the present technique. [Figure 21] FIG. 1 illustrates a process flow for creating a catalyst pattern having substantially connected catalytic features using self-assembly and lithography in accordance with one or more embodiments of the present technique. [Figure 22] FIG. 1 illustrates an example of a 3D NAND staircase etch in accordance with one or more embodiments of the present technology. [Figure 23]1A-1C illustrate a step or angled plasma etch process on bulk silicon with an alkaline etchant to create contact pads for wordlines in accordance with one or more embodiments of the present technique. [Figure 24] FIG. 2 illustrates an exemplary DRAM design with transistors, capacitors, and interconnects on nanowires etched by CICE in accordance with one or more embodiments of the present technology. [Figure 25A] 1A-1D illustrate two process flows for CICE wet anisotropic etching to create high aspect ratio pillars without collapse in accordance with one or more embodiments of the present technology. [Figure 25B] 1A-1D illustrate two process flows for CICE wet anisotropic etching to create high aspect ratio pillars without collapse in accordance with one or more embodiments of the present technology. [Figure 26] 1A-1D show SEM images illustrating collapse of unsupported features vs. supported features after CICE on silicon in accordance with one or more embodiments of the present technique. [Figure 27A] A diagram showing a 14nm FinFET with a taper angle of approximately 85 degrees and a physical half pitch (HP) of 24nm (Reference: TechInsights). [Figure 27B] FIG. 13 illustrates maximum fin height for different fin widths and etch taper angles in accordance with one or more embodiments of the present technique. [Figure 28] 1 is a plot showing the maximum untapered fin height before lateral collapse along the length of a 50 nm long fin without support / assist features. [Figure 29] FIG. 1 illustrates an example process flow for making finFETs using CICE in accordance with one or more embodiments of the present technology. [Diagram 30] 1 illustrates an example of a FinFET fabrication processing step after CICE, in accordance with one or more embodiments of the present technology. [Diagram 31]FIG. 1 illustrates an example process flow for making nanosheet FETs and lateral nanowire FETs using CICE, in accordance with one or more embodiments of the present technology. [Figure 32A] FIG. 13 shows a connecting link when the number of fins is greater than one. [Figure 32B] FIG. 13 shows links connecting all fins with isolated catalyst (top) or connected links and connected catalyst (bottom). [Figure 32C] 1 is a plot showing the critical height before collapse along the length of a connected fin structure for different fin widths, f, and numbers of fins ranging from 1 to 10. [Fig. 32D] 1 is a plot showing the critical height before collapse along the width of a connected fin structure for different fin widths, f, and numbers of fins ranging from 1 to 10.

[0015] The drawings are not necessarily drawn to scale. Similarly, for purposes of illustrating some of the embodiments of the present technology, some components and / or operations may be separated into different blocks or combined into a single block. Furthermore, while the present technology is susceptible to various modifications and alternative forms, specific embodiments are illustrated by way of example and are described in detail below. However, the intention is not to limit the present technology to the specific embodiments described. On the contrary, the present technology is intended to cover all modifications, equivalents, and alternatives within the scope of the technology as defined by the appended claims. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Various embodiments of the present technology describe novel anisotropic etching processes, for which fabrication tools are also disclosed, enabling the technology to be employed in the fabrication of semiconductor devices. Some embodiments use catalytically enhanced chemical etching (CICE) for the fabrication of transistors and various memory architectures. Furthermore, various embodiments of the CICE process have demonstrated very high aspect ratios without loss of feature size.

[0017] Various embodiments of the present technology also provide various control schemes for catalyst-based chemical etching. A wafer-scale multi-scale precision catalyst-influenced chemical etching (MSP-CICE) fabrication tool for this purpose is also disclosed. Some embodiments use various control schemes and tool designs to extend the performance of CICE from small areas (sub-150mm substrates) without etch depth control in the current literature to large areas (e.g., 300mm Si wafers) with local and global control and metrology. This allows the technology to be adopted for the fabrication of semiconductor devices such as 3D NAND flash, DRAM, FinFET and nanosheet transistors.

[0018] Various embodiments of the present technology relate generally to memory architectures and fabrication techniques. More specifically, some embodiments of the present technology relate to silicon etching using catalyst-promoted chemical etching techniques with applications to three-dimensional memory architectures and transistors. Scalability of advanced memory architectures with current pattern transfer technology is limited by etch mask degradation, sidewall damage and non-zero taper due to high aspect ratio plasma etching. Non-volatile semiconductor memories such as three-dimensional (3D) NAND flash require very high aspect ratio etching of over 64 layers of alternating materials to increase the storage capacity of flash drives. With the increase in layers, the cost and reliability of anisotropic, high aspect ratio channel and trench etching as well as step etching to define contacts to each layer become the main limiting factors for scaling. Non-zero plasma etch taper angles limit the maximum number of layer stacks that can be reliably achieved.

[0019] Dry plasma etching processes used in the semiconductor industry to anisotropically etch highly controlled nanopatterns require expensive vacuum equipment and do not easily preserve cross-sectional shapes when patterning high aspect ratios. They also suffer from etching challenges such as aspect ratio dependent etching (ARDE) and etch taper. In 3D NAND flash designs, simultaneous etching of circular channels and rectangular slits cannot be reliably achieved in plasma etches with precise control over the sidewalls. Similarly, for features with connecting links, sub-10 nm links between pillars cannot be preserved at high aspect ratios.

[0020] Furthermore, DRAM scaling is limited by the area occupied by the capacitor and the cell size factor. Thus, current techniques in scaling memory architectures are limited by the large number of lithography and high aspect ratio etching steps. Various embodiments provide improved techniques for DRAM manufacturing.

[0021] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present technology. However, it will be apparent to one skilled in the art that embodiments of the present technology may be practiced without some of these specific details.

[0022] The techniques presented herein can be embodied as dedicated hardware (e.g., circuits), as programmable circuits appropriately programmed with software or firmware, or as a combination of dedicated and programmable circuits. Thus, embodiments may include a machine-readable medium on which are stored instructions used to program a computer (or other electronic device) to perform a process. The machine-readable medium may include, but is not limited to, an optical disk, a compact disk read-only memory (CD-ROM), a magneto-optical disk, a ROM, a random access memory (RAM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic or optical card, a flash memory, or any other type of medium / machine-readable medium suitable for storing electronic instructions.

[0023] Phrases such as "in some embodiments," "according to some embodiments," "in an illustrated embodiment," "in another embodiment," and the like, may generally mean that the particular feature, structure, or characteristic that follows the phrase is included in at least one implementation of the technology, and may be included in more than one implementation. Additionally, such phrases do not necessarily refer to the same embodiment or different embodiments.

[0024] Various embodiments of the present technology use catalytically enhanced chemical etching (CICE) for the fabrication of transistors and various memory architectures. CICE is a process that is used to etch Si, Ge, Si x Ge 1-xCICE is a catalyst-based etching method that can be used with semiconductors such as GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, and multi-layer semiconductors. CICE uses catalysts to etch semiconductor substrates and has been used to fabricate high aspect ratio features using patterning techniques such as photolithography, e-beam lithography, nanosphere lithography, block copolymers, laser interference lithography, colloidal lithography, double patterning, quad patterning, nanoimprint lithography, and anodized aluminum oxide (AAO) templates to pattern the catalyst. The catalyst can be used with etch-retardant materials such as polymers, Cr, etc.

[0025] In some embodiments, the setup can be submerged in a solution containing an etchant (e.g., fluoride species HF, NHF, buffered HF, HSO, H0) and an oxidant (H02, V05, KMnO, dissolved oxygen, etc.). Other chemicals such as alcohols (ethanol, isopropyl alcohol, ethylene glycol), materials to control the uniformity of the etch (surfactants, soluble polymers, dimethylsulfoxide-DMSO), solvents (ion-exchanged water, DMSO, etc.), and buffers can also be included in the etching composition. The chemicals used can depend on the semiconductor substrate to be etched. Non-aqueous etchants can also be used as needed. Etchants can be in liquid or gas phase. Examples of such etchants for silicon substrates include ion-exchanged water, H0, H02, ethanol, and HF.

[0026] Materials such as metals (e.g., Ag, Au, Pd, Pt, Cu, W, Ru, Ir), compounds such as TiN, TaN, RuO2, IrO2, and other conductive metal oxides and nitrides, graphene, carbon, etc. can act as catalysts for CICE. The mechanism of the CICE process for etching Si involves the reduction of an oxidant by the catalyst, which then releases positively charged holes h +These holes are then injected through the metal to the metal-semiconductor interface, thereby oxidizing the semiconductor below the metal. The oxidized silicon is dissolved by the fluoride component of the etchant diffusing from the sides and through the catalyst, and the soluble products diffuse away. In the case of CICE of silicon with HF and H2O2, this redox reaction also produces hydrogen gas. Variables n=2 through 4 are determined by the ratio of oxidant to HF, which determines the etching regime that occurs.

[0027] [ka]

[0028] The etch rate of this process and the resulting morphology depend on the dopant type, concentration, catalyst film thickness, and etchant concentration. Greater uniformity / control of porosity has been achieved by hole diffusion during the etching process using both electric and magnetic fields. The resulting substrate with catalyst mesh is placed in an etchant solution and precisely etched to a certain depth that is actively controlled by an optical imaging system that can determine the etch depth in situ, temperature gradients, and electric fields. After CICE, the catalyst can be removed using chemical or plasma etching such as aqua regia, chlorine-based plasma, etc.

[0029] Silicon nanowires with diamond-shaped cross-sections fabricated using jet-and-flash imprint lithography (J-FIL) and gold-catalyzed CICE have been demonstrated (see, for example, Figure 1). Capacitors made with diamond-shaped silicon nanowires show a 90% higher specific capacitance than NWs with circular cross-sections of the same pitch, and the highest specific capacitance per area of ​​NWs in the literature. J-FIL and CICE have the potential to fabricate Si nanostructures at a fabrication cost of less than $1 per wafer, based on standard cost models.

[0030] FIG. 1A illustrates a J-FIL-enabled catalyst-enhanced chemical etching (CICE) process 100 for making nanowires, according to one or more embodiments of the present technology. As shown in FIG. 1A-1B, in process step 110, nanofeatures 111 (e.g., resist material) can be imprinted on a silicon substrate 112. Material (e.g., resist) can remain in the trenches 113 after the imprint process. In process step 120, a "descum" etch can be performed to remove the resist residual layer thickness (RLT) and to remove the resist in the trenches 113. One example of a descum etch uses oxygen and argon plasma to etch the resist material. In process step 130, gold (Au) 131 can be deposited in the trenches 113 and on the nanofeatures 111 using a directional deposition process, such as electron beam evaporation. Prior to the deposition of gold, an adhesion layer, such as Ti, can be deposited. In processing step 140, CICE can be used to form trenches 141 and gold 131 can be disposed at the bottom of the trenches 141 and on top of the nanofeatures 111. In processing step 150, the gold (Au) 131 and resist 111 can be removed and the structure can be cleaned using plasma etching or chemical etchants such as aqua regia, potassium iodide, and piranha in liquid or vapor form. Figure 1B shows a cross-sectional view of the fabrication of nanowires using the steps described in Figure 1A in accordance with one or more embodiments of the technology.

[0031] CICE is a superset of processes called metal-assisted chemical etching (MACE). Apart from metals, there are certain non-metallic catalysts such as graphene or TiN, TaN, RuO2, IrO2 that can potentially be used as catalysts. Furthermore, catalysts usually locally assist chemical etching by digging into the substrate in the presence of etchants and oxidants, but can also locally inhibit etching, as in the case of InP. To encompass all such processes, the various embodiments refer to the process as catalytically promoted chemical etching (CICE).

[0032] However, the CICE anisotropic wet etching method used in high aspect ratio etching steps currently does not have precise etch depth control and wafer-scale fabrication. Discontinuous catalyst features tend to wander during CICE processing and are prone to defects. The catalysts used are not easy to etch with plasma or wet etching without redeposition or undercutting. The lift-off process currently used to pattern noble metal catalysts is highly defect-prone. Various embodiments of the present technology enable the etching of arbitrary nanopatterns with feature sizes ranging from mm to nm by precisely controlling various sensors and actuators such as etchant solution chemistry, electric field, and optical / spectroscopic properties of the nanostructures.

[0033] According to various embodiments, CICE can be used to create nanostructures of bulk materials or alternating layers of materials such as superlattices. CICE of bulk materials can be used in devices such as finFETs and nanowire sensors. Superlattice nanostructures have applications such as 3D NAND flash memory devices and nanosheet transistors. Superlattices can be created by performing CICE on a bulk semiconductor substrate with a time-varying electric field or on a substrate with alternating layers of semiconductor materials with different doping concentrations, materials, dopant types, etc. In embodiments using silicon as at least one of the substrate materials, the process of CICE to create a superlattice is described as silicon superlattice etching (SiSE) as described below.

[0034] (Silicon Superlattice Etching (SiSE)) SiSE can be used on bulk silicon wafers or on alternating layers of silicon with different doping concentrations. An etchant (e.g. hydrofluoric acid HF), an oxidant (e.g. hydrogen peroxide H2O2), and optionally a low surface tension liquid (e.g. ethanol) or deionized water can etch the semiconductor substrate preferentially at the locations of the catalyst (e.g. Ag, Au, Pd, Pt, Cu, W, Ru, TiN, RuO2, IrO2, graphene, etc.). If necessary, non-aqueous etchants can also be used. Lithographic techniques (e.g. photolithography, e-beam lithography, double patterning, quad patterning, nanoimprint lithography, etc.) can be used to define the catalyst features. The resulting substrate with the catalyst mesh is placed in the MSP-CICE tool and precisely etched to a certain depth that is actively controlled by an optical imaging system, thermal actuators, and electric fields that can determine the etch depth based on electrical and optical properties during etching.

[0035] Heterojunction materials, alloys, and other semiconductors, such as III-V, II-VI, and IV, that can be etched by superlattice etching include Ge, Si x Ge 1-x , GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, etc., which may be included in the material design space, but are not discussed further herein for a variety of reasons including high cost of materials and deposition, lack of commercially available deposition and characterization methods, etc. Reliable large area wafer-scale etching using SiSE processes that can utilize various embodiments of silicon-containing SiSE processes does not currently exist in the prior art. Various embodiments shall incorporate various techniques to make this possible.

[0036] Silicon superlattice etching (SiSE) uses a catalyst to etch a semiconductor substrate while simultaneously creating a superlattice with alternating layers, at least one of which is porous. The alternating layers are formed by electric field parameter modulation and / or etching through layers with alternating doping characteristics. FIG. 2 illustrates a SiSE process control 200 according to one or more embodiments of the present technology. As shown in FIG. 2, a patterning operation 210 can produce a patterned catalyst on a silicon substrate. According to various embodiments, a bulk substrate (as shown at 212) or a substrate with alternating doping layers (as shown at 214) can be used. Either a bulk substrate or a substrate with alternating doping layers can be loaded into a silicon superlattice etching tool in a load operation 230. The SiSE process 240 can be precisely controlled to produce high aspect ratio nanostructures 250. According to various embodiments, high aspect ratio nanostructures 250 may have a height to critical dimension (eg, the average of the base and top diameters of the nanowire) ratio of 4:1, 5:1, or greater.

[0037] Various feedback parameters 260 can be measured directly or estimated from direct measurements, including, but not limited to, etchant performance parameters (e.g., concentration, volume, flow rate, Reynolds number, refractive index, etc.), electric field parameters (current, voltage, resistance, capacitance, etc.), optical variations across the wafer (e.g., reflectivity, intensity, etc.), ambient environment parameters (e.g., temperature, pressure, inert gas flow rate, vapor pressure, etc.), and / or other parameters. These can be used to generate feedback signals that can be used with the input etch control signals to control various system parameters (e.g., flow rate, etchant turbulence, temperature, pressure, concentration, illumination, and electric field parameters such as current, voltage, resistance, capacitance, frequency, duty cycle, amplitude, waveform type, distance between electrodes, etc.).

[0038] In the case of bulk silicon etched by a patterned catalyst with a modulated electric field (as shown at 212), the alternating layers differ in porosity. Modulation of parameters such as current density and illumination density over time can create porous semiconductor multi-layers. The current density can be modulated such that for a p-type silicon substrate, positive current density creates porosity as the catalyst sinks into the silicon, and zero or negative current density creates a crystalline layer with only catalytic etching, as shown in FIG. 2. This is unique compared to processes where only a modulated electric field is used without the presence of a catalyst, because in such cases it is not possible to create alternating layers where one of the layers has very low porosity. Some embodiments of such a multi-layer stack can include one set of alternating layers with less than 20% porosity and another set with layers with more than 30% porosity.

[0039] When epitaxial layers with alternating high and low doping concentrations are deposited at submicron thicknesses per layer (e.g., as shown in 214), the concentration gradient across the interface between the two layers is shallow due to limitations of the deposition process at high deposition rates and diffusion of dopants across the interface. This results in a lack of abrupt changes in doping across the thickness of the stack, such as a shallow gradient across the interface. In SiSE, the etch is tailored to ensure that the morphology changes from porous to non-porous at a specific doping concentration, thereby changing the shallow doping concentration gradient into a steep step function at the porous / non-porous interface.

[0040] As the SiSE progresses, the catalytic mesh etches the semiconductor material stack to expose high aspect ratio features with holes and slits for 3D NAND channels and wordline isolation, and fins and trenches for nanosheet FETs. SiSE can be stopped using etch stop layers and / or timed etches. The etchant composition and hole generation during processing result in alternating films with different morphologies based on their materials and doping concentrations, and the exact time at which the morphology changes can be detected by measuring electrical parameters such as resistance, voltage, current, and capacitance across the epitaxial layers. This information can then be used to precisely modulate the current across the stack.

[0041] 3A-3B show a steep interface between porous and non-porous layers after SiSE on a substrate comprising alternating layers of epitaxial silicon with different doping concentrations, according to one or more embodiments of the present technology. In Fig. 3A, an interface 310 between layer A of a porous film 320 and layer B of a non-porous film 330 is shown. In Fig. 3B, several collapsed walls 340 having porous and non-porous sections are shown.

[0042] (CMOS compatibility of CICE catalyst materials) Various embodiments of the CICE process can use patterned catalysts that sink into the substrate as the etch proceeds, leaving the unpatterned areas as high aspect ratio nanostructures. For semiconductor applications such as transistors and memory devices, the catalyst material should be CMOS compatible to allow for industry adoption and to prevent deep level defects in silicon. Materials such as Au, Ag, Pt, Cu, Pd, W, Ni, Ru, graphene, TiN, RuO2, etc. can be used as SiSE catalysts. When metals such as Au and Cu are processed at high temperatures, deep level defects appear. Since SiSE is a room to low temperature process, the impact of such defects may be minimal. Additionally, CMOS compatible catalysts such as Pt, Pd, Ru, TiN, etc. can be used.

[0043] FIG. 4 shows an SEM cross-section of silicon nanowires made with gold and platinum catalysts, with a close-up image of the catalyst mesh at the bottom of the nanostructure, according to one or more embodiments of the present technology. For a CMOS compatible catalyst such as platinum (FIG. 4), deposition and patterning should be high yielding. Platinum can be etched using plasma etching with Cl2 to form PtCl2. At temperatures above 210° C., PtCl2 is volatile and can therefore be used as a viable method to etch metals after deposition and lithography. A similar etching method can be used for palladium. Another deposition method is via electrodeposition after lithography, where the metal is deposited only on areas of the substrate not covered by resist. Alternatively, the metal is deposited on the lithographed areas and the substrate, such as by e-beam deposition, but only the areas in contact with the substrate are etched by MACE, without the need for lift-off.

[0044] To prevent catalyst mesh wander and for reliable transport of etchant solution, continuous patterns with connecting links and / or ceilings, electric fields can be used in various embodiments. The resulting high aspect ratio features can be prevented from collapsing by relaxation techniques such as using low surface tension gradients, supercritical drying and connected features. Wandering and collapse can also be prevented by using patterning techniques that consist of connecting links between desired features in both the catalyst and the substrate, and by using controlled deposition or etching after SiSE processing to convert the high aspect ratio linked features into the desired device structure.

[0045] A problem that occurs during high aspect ratio etching of cut features is that of collapse, which is very detrimental to device yield. Various embodiments solve this problem by creating interconnect nanostructures with sub-10 nm assist features that prevent collapse and provide stability to the structures during and after etching. For example, in Figures 5A-5B, a catalyst design for 3D NAND flash is shown. After SiSE, the resulting structures can be greater than 20 microns in height with feature sizes less than 40 nm.

[0046] FIG. 5A illustrates a method of simultaneously connecting various isolated catalyst 520 and high aspect ratio (HAR) nanostructures 540 using connecting links 510 in catalyst material and semiconductor structures according to one or more embodiments of the present technology. FIG. 5B illustrates a top view of connected regions 540 that define the high aspect ratio structures remaining after SiSE and unconnected regions that represent the geometry of the catalyst features 530 according to one or more embodiments of the present technology. According to various embodiments, the isolated catalyst portions are connected using a pattern that can be generated from an algorithm used to connect the isolated features using links to ensure that the HAR nanostructures remain standing, and also help prevent the catalyst mesh from wandering and create diffusion paths for the etchant reactants and products to ensure a uniform and controlled etch rate (FIG. 5A). Wandering can occur because the catalyst features are disconnected, but may be prevented in some embodiments using an electric field. The free-standing features are connected to prevent collapse by strengthening the high aspect ratio lines (FIG. 5B).

[0047] According to various embodiments, the creation of connected links can be done by defining nodes of catalytic material or semiconductor that can be isolated in an ideal intended design. The links can then be created to ensure that the CICE etched structures are mechanically stable. The links can also be optimized to ensure that the catalyst does not wander during CICE. Optimization of such process excursions on the catalyst design can be done using standard algorithms such as graph theory based methods and recursive partitioning methods.

[0048] The catalyst may include one or more of: a) lithographic links to prevent wobble - these features result in gaps in the etched structure that can be filled with material using various deposition processes such as atomic layer deposition, chemical vapor deposition, electroplating, etc., and / or b) lithographic gaps to prevent the etched structure from collapsing - these features result in stabilizing links within the etched structure. Based on design requirements, these links may be removed using lithography and etching, selective oxidation, selective oxidation and etching, etc. This can be done after depositing stabilizing materials in other areas as needed.

[0049] Linked structures result when the catalyst mesh contains both lithographic links and gaps. It is very difficult to fabricate sub-30 nm features with even smaller link connections. Patterning methods such as e-beam lithography can write sub-10 nm features but suffer from large overlay. Photolithography, on the other hand, has good overlay but poor resolution. Photolithography and imprint lithography (whose template is made by e-beam lithography) may be used to obtain the final linked structure that later becomes the nanoimprint template. An example of such a pattern is described in the 3D NAND and transistor device sections.

[0050] Besides using isolated or linked structures for catalysts, another method for extending the maximum aspect ratio used in various embodiments is by using a ceiling. The ceiling can be used to prevent collapse by etching the feature to a short, stable height using plasma etching or SiSE, depositing a ceiling, and continuing the SiSE process. The "ceiling" can also be a height along the length of the short pillar, such as L / 2, where L is the height of the short, stable pillar. This provides additional support as the feature is etched further, and the maximum aspect ratio is greater than that of the ceiling at the top of the short pillar. This provides structural stability to the high aspect ratio pillar and prevents collapse.

[0051] The ceiling can be deposited by methods such as graded deposition, filling with a polymer, etch-back and depositing the ceiling, or spin-coating. Materials that can be used for the ceiling include polymers, sputtered / deposited semiconductors, metals and oxides that do not react with the CICE etchant, etc. For Si CICE etchants, materials such as Cr, Cr2O3, carbon, silicon, Al2O3, polymers can be used. In some embodiments, the ceiling can also be made porous by an additional low-resolution lithography step or by a reaction that induces porosity in the ceiling material. Once the substrate is etched and the catalyst is removed using liquid or gas phase chemical etching, deposition of a memory film or dielectric filler by methods such as atomic layer deposition can be performed before removing the porous ceiling. The ceiling material can also be tailored to be non-selective to atomic layer deposition (ALD) to prevent multiple holes from closing and blocking the deposition path. After filling the feature, the ceiling is etched or polished. ALD can also be used to close high aspect ratio features after etching to create deep holes without the use of isolated catalyst.

[0052] (Etching tool) Various embodiments of the present technology provide a unique high-fidelity nanoscale fabrication system (multiscale precision CICE or MSP-CICE) capable of achieving wafer-scale etching of high aspect ratio nanostructures in semiconductor materials with features, such as a system that enables multiscale precision control of the CICE process based on 1) high speed (real-time), high spatial resolution functional or geometric metrology as the etch progresses for precise process monitoring and control, and / or 2) based on real-time metrology and an array of independently addressable actuators that locally control the etch process to enable controlled fabrication of devices with various arrays.

[0053] 6A-6E show processing chamber configurations of a CICE in accordance with one or more embodiments of the present technology. FIG. 6A shows a system with inkjet 605, etchant circulation system 610, front electrode 615, electric field supply 620, polymer wall 625, and back electrode contacts and thermal actuators 630. In the embodiment shown in FIG. 6A, a silicon wafer 635 can be placed between the front electrode 615 and the back electrode 630 to enable electric field control. FIG. 6B shows several embodiments of the electric field configuration of a CICE using a wafer chuck 640. FIG. 6C shows a setup for bulk delivery of etchant with a micromirror array for additional thermal control and back contacts of localized electric and thermal actuators used in some embodiments of the present technology. FIG. 6D shows a setup for bulk delivery of etchant with a micromirror array for additional thermal control, back contacts of localized electric and thermal actuators, and front electrode needle 645 used in some embodiments of the present technology. FIG. 6E shows a setup with a thermal chuck and recessed electrodes and thermal actuators 650 behind the substrate.

[0054] The embodiment shown in Figures 6A and 6B provides localized control of etchant concentration and electric field using inkjet 605 coupled to a local top electrode 615 and back electrode contact 630. Different areas for etching can be isolated from each other on the top of the wafer using polymer walls 625 that are tapered using low resolution lithography. In one embodiment, these walls can be made of different etchant resistant materials such as silicon nitride, aluminum oxide, amorphous carbon, silicon or chromium. In Figure 6A, the back electrode 630 includes both electric and thermal actuators, and the electrical contact is made using a conductive material such as metal, silicon, silicon carbide, which may or may not be doped to improve conductivity. In Figure 6B, the back electrical contact 630 is made using an electrolyte that is contained locally between the wafer 635 and the chuck 640. The electrolyte can be the same as the etchant or it can be a different conductive liquid such as a dilute acid, base or salt that is CMOS compatible. 6A and 6B, the backside electrode 630 can also include temperature control integrated into the electrode itself (FIG. 6A) or into the chuck (FIG. 6B).

[0055] In the embodiment shown in FIG. 6C, the backside electrode contact 630 and chuck 640 are similar to the configuration in FIG. 6B. Alternatively, the etchant may be distributed globally over the wafer using an inlet and circulated using an outlet for flow control. An optional diffuser (not shown) may be used to ensure uniform distribution of the etchant over the wafer. The different components of the etchant may be mixed in a separate mixing chamber or may be mixed dynamically by passing through the inlets and diffusers. The electrodes 615 may be made of metal mesh, doped silicon wafers, ITO (indium tin oxide) or other such materials and may be coated with etchant resistant materials such as polymers, PTFE, aluminum oxide, etc. The coated materials may be doped to improve electrical conductivity. Localized heating may be performed on either side of the wafer by a micromirror array on the top side of the wafer or by embedded thermal actuators in the chuck 640.

[0056] In the embodiment shown in FIG. 6D, the wafer 635 can face either the top or the bottom of the setup. The chuck 640 can be used to create an electric field using electrodes and an electrolyte. The electrolyte can be a very thin film, allowing local temperature control via embedded actuators in the chuck 640. Alternatively, a micromirror can be used. An optional diffuser (not shown in FIG. 6D) can be used for both uniform distribution of the etchant and optical metrology using embedded optical fibers. Local electric field control can be created via sharp electrode tips 645 or by embedded electrodes in the chuck 640.

[0057] FIG. 6E shows an embodiment where the wafer 635 faces the base of the setup. The base contains the electrodes and etchant at a low temperature. The wafer can be held upside down using a head chuck with electrical and thermal actuators. A thin film of electrolyte may be present on the head chuck to make good electrical contact. The wafer can be rotated using the head chuck, and an overflow chamber can be used to carry away excess etchant while the wafer is rotating. An optional diffuser (not shown) can be used at the base to allow the etchant to be distributed evenly. The diffuser can also include optical cables for measurement.

[0058] CICE can be performed using various etchant delivery methods with catalysts, electric, magnetic, temperature actuators, etc. for different applications such as electrochemical etching, electroless chemical etching, catalyst-promoted vapor phase etching, catalyst-promoted plasma etching, electrochemical / electroless chemical etching of "digital" layers (e.g., alternating pulsing of H2O2 vapor and HF vapor, alternating pulsing of H2O2 liquid and HF liquid, alternating pulsing of H2O2 vapor and HF liquid, alternating H2O2, plasma and fluoride ion flows / pressures to alternating porosity, strong oxidizers for porous layers and weak oxidizers for non-porous layers, etc.), magnetic field electrochemical / electroless chemical etching, gel-based etching (e.g., by adding thick polymeric material in local contact with the top / bottom of the wafer for localized thermal and electric field control, or by changing gel consistency with temperature).

[0059] In some embodiments, prior to the CICE process, the wetting properties of the etchant chemistry on the catalyst patterned substrate can be modified to make it more hydrophobic or hydrophilic. This helps improve the uniformity of the etch process by ensuring that the initiation of etching begins at the same time at all locations on the substrate. Exposing the substrate to vapor HF, piranha (different ratios of sulfuric acid and hydrogen peroxide), buffered oxide etch, hydrofluoric acid, etc., and rinsing with deionized water, isopropyl alcohol, acetone, etc., and drying to prevent water contamination can improve the wetting of the etchant on the substrate.

[0060] After the CICE process is completed, the substrate can be rinsed with deionized water, isopropyl alcohol, acetone, etc. to ensure that the etchant is completely removed from the substrate, thereby avoiding localized over-etching. The rinse station can be the same as the processing chamber where the wafer is rinsed with deionized water after removal of the etchant. It can also include a spinning system to dry the wafer after rinsing. Alternatively, the wafer can be moved to another rinse and dry station after the CICE process using automated handling.

[0061] FIG. 7A shows a cross-sectional view of an embodiment of an MSP-CICE processing chamber 700 with automated handling using a Z-motion actuator 710. The Z-motion actuator may include a voice coil in the head assembly, bearings 715 in the base assembly, and compliance in the actuator system to ensure a good seal is created to prevent leaks using a leak check sensor 720. The Z-motion actuator is used to lower the head assembly 725 towards the base assembly 730. The Z-motion actuator may be controlled using motion sensors, force sensors, or a combination thereof to ensure the head assembly, wafer, and base assembly assemble to form the proper seal required for the electrolyte in the head assembly and the etchant in the base assembly. In this embodiment, a Si wafer substrate 735 faces the base.

[0062] The base includes a base electrode 740, a power supply 745 to the base electrode, and a seal ring 750, which may be a rectangular cross-section ring or an O-ring (circular cross-section polymer ring) made of an etchant-resistant material such as fluoropolymer, Al2O3, SiC, Teflon coating material, etc., used to seal the etchant from the electrode and the Si wafer. The base also includes an inlet 755 and an outlet 760 for the flow and circulation of the etchant, and a diffuser 765 that may include an optical fiber for in-situ optical sensing of the etching process. The base may also include an overflow chamber (not shown) to ensure that the etchant is filled to the brim before loading the Si wafer. The head assembly includes a pin chuck zone 770, an electrolyte zone 785, and a power supply 795. The pin chuck zone is connected to one or more vacuum ports 775.

[0063] A thermal actuator 780 can be embedded behind the pin chuck zone. An embodiment using a thermal actuator with proportional-integral controlled thermoelectric heating / cooling elements such as thermistors and heat sinks is incorporated herein by reference (Ajay, P. et al., 2016. Multi-field sub-5 nm overlay in imprint lithography. Journal of vacuum science and technology. B, Nanotechnology & microelectronics: materials, processing, measurement, & phenomerna: JVST B, 34(6), p061605). Both inlet and outlet electrolyte ports 790 are used to pump electrolyte into one or more electrolyte zones and plug it during etching. This allows for a configuration in which the head assembly can rotate with the Si wafer while the base remains stationary. The electrolyte can be different from the etchant, for example a dilute acid, base, salt, etc. with sufficient conductivity to create an electric field across the Si wafer using the base electrode. A typical electrolyte includes dilute sulfuric acid.

[0064] FIG. 7B shows a cross-sectional view and a top view of an embodiment of the head chuck. The pin chuck zone 770 is used to hold the Si wafer 735, and the electrolyte zone 785 is used to make contact between the Si wafer and the electrolyte. In this embodiment, a liquid electrolyte is used to make a reliable ohmic contact with the Si wafer. In other embodiments, metal or SiC pads may be used instead of the liquid electrolyte in the "electrolyte zone". The pin chuck and electrolyte zones are separated from each other using a seal element 771 machined into the chuck. The local electric field boundaries at the electrolyte zone edges are discrete behind the Si wafer. However, depending on the thickness of the Si wafer and its electronic properties, the electric field lines between different electrolyte zones may meet in front of the Si wafer.

[0065] Electromagnetic simulations can be performed to determine the optimal placement of the electrolyte and pin chuck zones for effective local and global electric field control and edge uniformity. In one embodiment, the seal element is 1 mm wide, and the pin chuck and electrolyte zones are concentric, each 9 mm wide, terminating in a central circular area as shown in FIG. 7B. Vacuum port 775 may use pneumatic elements to ensure that the pin chuck zone is under vacuum and the wafer is held against the pins 772. Electrolyte flow port 790 is used to flow electrolyte after the Si wafer is held by the chuck. Discrete thermal actuators 780 can be integrated behind the pin chuck area of ​​the Si wafer to facilitate localized temperature control. In one embodiment, the head assembly includes a pin chuck element made of aluminum oxide material.

[0066] In FIG. 7, automatic handling can be achieved by starting with the separation between the head and base. The base is stationary and filled to the brim with etchant. This can be ensured using an overflow chamber and etchant level monitor. The etchant at the base can be recirculated using inlet and outlet valves. A robot arm is used to load the Si wafer onto the head chuck with the side to be etched facing the base. In one embodiment, the robot arm contacts the front side of the Si wafer at the edge (only the exclusion zone, which is a zone of about 1 to 2 mm at the edge of the wafer where no functional devices are fabricated) and aligns the back side of the wafer with the outer seal ring of the head chuck. This then holds the Si wafer using vacuum in the pin chuck zone. In an alternative embodiment, the head chuck may include "fingers" around the edge of the wafer that protrude and grab the edge of the wafer after the robot arm holding the wafer facing the base brings it under the head chuck. The fingers grab the edge of the wafer and then pull the wafer towards the pins of the head chuck. The vacuum zone then grabs the wafer, which can be detected using a vacuum sensor in the chuck vacuum line, and the fingers then move off the edge of the wafer and retract into the head.

[0067] Once a seal is created, electrolyte is pumped into one or more electrolyte zones. This section may be thin to ensure that only a small amount of electrolyte needs to be pumped. The head assembly with the Si wafer is then lowered towards the base using a Z-motion actuator. To ensure smooth contact with the etchant in the base and to minimize the formation of air bubbles at the etchant-wafer interface, the head assembly is tilted slightly as it is lowered using an element of the Z-motion actuator, such as a voice coil. Once one end makes contact with the etchant, the head assembly is tilted back to a horizontal configuration. This helps to prevent air bubbles from building up at the wafer-base interface. Any bearings in the base then clamp the assembly and use a force sensor to verify that a proper seal has been created between the base and the Si wafer.

[0068] Alternatively, excess etchant may flow into an overflow chamber near the edge of the wafer. A leak test sensor then verifies that the wafer is ready to be processed. CICE may be performed by initiating an electric field across the wafer. For processes that require an oxidizer such as H2O2, the oxidizer may be pumped into the etchant in the base after the wafer is clamped so that any initial contact does not prematurely initiate etching. In an alternative embodiment, the volume of etchant in the base is slightly less than the amount required to contact the front side of the Si wafer. Once the head assembly completes its z-motion toward the base, a small amount of etchant is added to the base chamber to contact the etchant with the Si wafer. To prevent air bubbles from adversely affecting the etch, the head may be tilted slightly to allow air bubbles to escape before returning to a horizontal position, creating a uniform etchant-wafer interface for CICE.

[0069] The removal of the wafer after the CICE process in FIG. 7 may also be handled automatically. Once the CICE process is complete, the head assembly including the wafer is separated from the base. The etched side of the wafer is then rinsed to remove the etchant on the surface. This can be done by rotating the head and spraying it with deionized water. The rinsing system is now moved to an area below the head and above the base. The rinsing system includes a drain, a spray for deionized water, and a source of heated air or nitrogen gas to dry the etched surface. Once the front side of the Si wafer is clean, the electrolyte in the head is drained and the wafer is placed face down on an edge contact in a rinsing station. The back side of the wafer is then rinsed and dried in a similar manner. The robot arm then removes the Si wafer and the rinsing system is moved away from the base and the center of the head. In an alternative embodiment, the head may move laterally to place the Si wafer in another rinsing station.

[0070] Wafer-scale etching of semiconductor bulk or superlattice nanostructures using CICE can use monitoring and control of a variety of parameters such as etch depth variation, porosity of alternating layers, stability of high aspect ratio nanostructures, etch anisotropy, wafer edge effects, electric field uniformity, illumination uniformity, etc. This allows monitoring of etch parameters layer by layer during SiSE, using local control of pattern geometry and measurements of current and voltage across the stack to determine the number of layers etched etc. with a high level of precision across the wafer.

[0071] Additionally, areas of the wafer used for peripheral and non-3D NAND array circuits must be protected from SiSE processing. This can be done by masking the non-array areas. Etch variations near the edges of these features can be adjusted using actuators.

[0072] Etchant flow through sub-40 nm holes when etched to depths of over 10 microns (AR>250) is enabled by the electric field and the creation of alternating porous layers. The porous layers enhance lateral etchant flow and control etch uniformity. Another method of increasing etchant flow, according to various embodiments, is by connecting multiple holes with a connected link pattern.

[0073] As etching progresses due to the increased aspect ratio, the etch rate may decrease due to slower diffusion of the etchant. Each etched layer of the superlattice can result in a step change in an electrical property, such as the current or voltage across the electrodes or the resistance of the stack, and such a change can be detected through a change in the electrical property across the stack. To counter this reduction in diffusion, some embodiments utilize alternating porous layers to ensure that there are multiple paths for the etchant to reach the etch front, i.e., the catalyst location. In some embodiments, the rotation of the substrate during the CICE process can be performed at an optimized speed to improve the uniformity of the etchant concentration from the center to the edge of the wafer.

[0074] The main cause of catalyst wander is the imbalance in the density of holes underneath the catalyst. To prevent catalyst wander and ensure vertical anisotropy of the etch, an electric field can be applied to direct the diffusion of holes to the bottom of the wafer. The required electric field changes as the SiSE progresses due to the change in resistivity between the electrodes as the number of alternating doped layers being etched changes. The voltage change can be compensated for by using a current-controlled power supply circuit.

[0075] Various embodiments of the SiSE tool system enable multi-scale precision control of the SiSE process based on real-time metrology and on an array of independently addressable actuators that locally control the etching process to enable controlled fabrication of devices with various geometries and multiple layers. Parameters such as resistivity and doping of the substrate material, the required geometry and aspect ratio, etchant ratio, electric field, temperature, and illumination of the process chamber can be altered to control the etching. Once the SiSE process is completed with in-line metrology, the solution in the machine must be flushed out and replaced with a catalytic wet etchant. Next, because capillary forces can cause high aspect ratio nanostructures to collapse as the device dries, we describe the use of efficient and highly controlled fluid exchange in combination with advanced drying techniques and novel mesh architectures and / or ceilings to prevent the collapse of the tape patterns.

[0076] In-line electrical metrology and electrochemical etch stop may be used in various embodiments. For example, electrical bias when applied to the semiconductor substrate can control the etch profile in real time. Excess etching due to migration of excess holes generated under the catalyst can be controlled by an external electric field. A negative bias at the backside of the wafer attracts excess holes and prevents unwanted porosity in the Si. A wide range of current, bias and polarity settings, including fast pulses and periodic reverse waveforms, control the electric field across the wafer in real time. Electric field parameters such as current, voltage, resistance, capacitance, waveform frequency, duty cycle, amplitude, distance between electrodes, etc. are used to detect changes in etch conditions as well as to control the porosity of the alternating layers while preventing catalyst wander.

[0077] Measuring the current and voltage across the substrate as the etch progresses can be used to determine the number of alternating layers that are etched in the 3D NAND Flash process, and the exact time at which the morphology changes can be detected by measuring electrical parameters such as resistance, voltage, current and capacitance across the epitaxial layers. This information can then be used to precisely modulate the current across the stack.

[0078] The electric field can be used for a variety of functions during CICE processing, such as creating alternating porous / non-porous layers, preventing catalyst drift during etching, maintaining uniformity across the wafer, detecting etch depth variations within a die, die-to-die, and center-to-edge variations, etc. Application of the electric field locally and globally across the substrate requires tool and process design to ensure compatibility with different CMOS processing equipment and constraints such as front and back contacts, edge width contacts, electrical back contact materials, etc. Some embodiments of this design are shown in Figures 6A-6E.

[0079] Multiple electric fields can be applied across the wafer to perform multiple functions, such as: 1) DC voltage across the wafer to prevent catalyst wander, 2) alternating electric fields with certain waveforms, frequencies, wavelengths and duty cycles to create alternating porous / non-porous layers, 3) detection of localized changes in etching from center to edge via pulsed electric fields at frequencies and voltages that do not affect the porosity of the substrate being etched, and / or 4) monitoring etch depth by measuring current, voltage, resistance, capacitance, etc. of each local electrode.

[0080] Apart from the electric field, temperature can also affect the etch rate of a CICE. For example, it has been shown in the literature that the etch rate of a CICE depends on the temperature of the etchant, decreasing exponentially near 0° C. (See: Backers, A. et al., 2016. Temperature-Dependent Pore Formation in Metal-Assisted Chemical Etching of Silicon. ECS JOURNAL of Solid State Science and Technology, 5(12), pp. 653-656, incorporated herein by reference in its entirety for all purposes). Various embodiments take advantage of this property by locally controlling the etch temperature by maintaining the local etchant temperature near zero degrees using coolants such as liquid nitrogen and dry ice, and locally modifying the temperature of the substrate. This can be done using a thermal chuck, micromirrors, or electrodes near the wafer that can locally heat the solution. Alternatively, the etchant temperature can be locally controlled by using individual wells on each die. The individual wells are filled with a finite, temperature-controlled volume of etchant, which is pumped or circulated. In some embodiments, the temperature can be precisely mapped across the wafer using a thermal camera, thermocouples, etc.

[0081] An optical imaging system is used to measure the reflectance of a large sample area in real time. The sample is illuminated with light of known spectral content. The light can be white light, colored light, a single wavelength, narrow or broad spectral band, etc. A camera can then image the sample reflecting this light. The camera can be monochrome, color (RGB), multispectral, high-pass spectrum, etc. The multi-megapixel resolution found in modern cameras allows millions of locations on the sample to be viewed simultaneously. The video frame rate allows in situ real-time measurements. Each image can be divided with a reference image to calculate a reflectance image of the sample or used as is. Image processing algorithms determine completion of processing and collect data on the uniformity of MSP-CICE within and between samples. In an embodiment where CICE is used to create Si nanowires (NWs), the optical properties of the tunable shaped Si NWs result in a broad spectrum of colors under white light illumination. In preliminary experiments using CICE, samples show large changes in hue during CICE etching. Because the pitch and diameter of the nanowires remain relatively fixed, observing the change in hue of the sample is a useful indicator of the nanowire height, and hence the etch depth. The change in hue can be characterized by measuring the reflectance of the sample as a function of the spectral content of the light present.

[0082] The spectral properties of the alternating layers can also be used to allow detection of the number of layers and porosity during the etching process. Infrared (IR) spectroscopy can be used to determine the etched layers in situ. This uses similar measurements to those used to characterize Bragg reflectors and rugate filters in the literature. In one embodiment, optical cables in the diffuser plate in the etching chamber can be used to incorporate such measurement elements.

[0083] Visible wavelengths from the backside of the wafer cannot detect etch depth during CICE. Instead, infrared (IR) spectroscopy can be used because it is a rapid, non-destructive, in-situ method to detect the etch status. Silicon is transparent at IR wavelengths, whereas catalysts such as Pt and Pd are not. This distinction can be used to determine both the etch rate and etch depth in a given CICE process.

[0084] The concentration of the etchant can be measured using a variety of techniques. For example, in some embodiments, a conductivity measurement may be used since HF has a linear dependence between concentration and conductivity. In some embodiments, a refractive index measurement may be used. For example, an optical metrology system can be used to measure the refractive index (RI) through a reflection-type geometry that uses an optical window in contact with the solution to avoid turbidity, diffraction, and absorption.

[0085] To ensure uniformity of etchant concentration across the wafer, the wafer can be rotated using a wafer chuck. Here, localized electric fields can be provided by connecting a spinning array of local electrodes on the chuck to a patterned stationary conductor disk. The local electrodes can be connected to a tapered turned stationary conductor disk using slip rings. Compatibility with the etchant chemistry can be ensured using a Teflon coating.

[0086] In some embodiments, a "pioneer" wafer can be used to optimize the etch and the pilot wafer can be inspected using a variety of in situ (online) and ex situ (offline) methods. Offline metrology consists of a variety of destructive and non-destructive inspection methods such as scatterometry, ellipsometry, optical property size measurement, laser scanning, scanning electron microscopy (SEM), atomic force microscopy (AFM), transmission electron microscopy (TEM), X-ray diffraction (XRD), etc. The collected data is analyzed using image processing algorithms to identify the causes of defects and process excursions.

[0087] Magnetic fields, pressure fluctuations, electromagnetic fields, solvents to improve uniformity and prevent bubble deposition, wafer rotation, edge effects, etchant spraying, and etchant atomization may also be included in some embodiments of the CICE tool as needed.

[0088] (Overall tool design and control scheme) Some embodiments provide a wafer-scale system for high aspect ratio etching of semiconductor substrates. The multi-scale precision (MSP) CICE system used in some embodiments can have a modular architecture that allows for the placement of sensors and actuators, such as large-scale array electrodes and real-time optical imaging systems. Figures 8A-8C show an example MSP_CICE tool setup, an example detailed process chamber layout, and an example process flow used in one or more embodiments. In some embodiments, a nonlinear optimal process control scheme can be used to achieve controlled wafer-scale nano-fabrication based on a large-scale array of independently controlled electrodes.

[0089] FIG. 8A shows a cross-sectional view of a complete etching tool with automated substrate, electrode and etching cell loading. FIG. 8B shows a detailed cross-sectional view of several embodiments of a processing chamber 815. As shown in FIG. 8B, the etching tool can include a loading dock 805, a robotic arm 810, a processing chamber 815, an upper electrode 820, a tunable light source 825, a wafer chuck 830, a wafer chuck holder 835, a stirrer 840, a power supply 845, a number of sensors 850, a drain 855, an optical metrology system 860, a high resolution camera 865, a lower electrode 870, a circulation setup 880, an exhaust 885, and an inlet flow 890. In the illustrated embodiment, the processing chamber 815 can include a robotic arm 810 that places a wafer on the wafer chuck 830. The wafer chuck 830 can be positioned on the wafer chuck holder 835. The wafer chuck holder and the wafer chuck assembly separate the electrolyte in contact with the lower electrode 870 and the upper electrode 820. This ensures that the electric field is applied across the wafer. The process chamber 815 can also include an in-line optical metrology system 860, which can include a high resolution camera 865 and a tunable light source 825. The process chamber 815 according to various embodiments can also include an etch flow system with inlet flows 890 for the lower electrolyte and upper electrolyte / etchant, an exhaust 855, and a circulation setup 880. The etch flow system can also include a stirrer 840 (e.g., a magnetic stirrer). A first electrode 820 and a second electrode 870 with a power supply 845 can be used to apply the electric field across the wafer. In-line metrology can be performed using embedded sensors 850 (e.g., temperature, electric field characteristics, fluid concentration characteristics, etc.). An exhaust 885 can be used to remove fumes. A processor 890 can control the process using one or more algorithms.

[0090] In the embodiment shown in Figures 8A-8B, a wafer with a patterned catalyst is loaded onto a loading dock 805. Using a robotic arm 810, the wafer can be transferred to a processing chamber 815. A transparent top electrode 820 can then be placed on rails above the wafer holder. Once processing is complete, the top electrode array 820 can be removed and the wafer is removed and returned to the loading dock 805. A key challenge in building this tool is that all elements of the system are compatible with HF (hydrofluoric acid). Various embodiments propose to do this by coating all equipment that comes into contact with HF with polymers such as Teflon PTFE, epoxy, TPX (or PMP), polypropylene (PP) and PVDF, which are also compatible with H2O2. TPX and epoxy are transparent and easy to process.

[0091] Based on the requirements of the application, the wafer chuck can be a Bernoulli chuck with no backside contact with the wafer, or it can have an O-ring on the front side of the wafer to contain the wet etchant. Flow valves and actuators can be used to control the relative ratios of the etchant components (HF, H2O2, ethanol, isopropyl alcohol, deionized water, etc.) in the chamber. The etchant can be distributed locally by inkjet or across the wafer by a flow valve. After etching and removal of the catalytic mesh, the etchant can be washed away with deionized water and replaced with a low surface tension liquid. A drain valve safely discards the fluid or stores the fluid for use in a subsequent etch.

[0092] 8C shows an example of the various processes that a wafer undergoes in an etch tool. The wafer can be loaded into the tool using a loading dock 812, which may contain a FOUP (front opening universal pod) of wafers. A robotic arm (or other transport mechanism) can transport the wafer from the loading dock 805 to a processing chamber 815. The processing chamber 815 may include one or more chambers for pre-processing 816, etching 818, post-processing 828, and a rinsing step 830.

[0093] The pretreatment step 816 may be a lift-off process or a surface modification step such as piranha (sulfuric acid and hydrogen peroxide), vapor HF, dilute HF, buffered oxide etch, or a distribution of ethanol, acetone, isopropyl alcohol, deionized water, etc. The pretreatment step may be via plasma activation using an oxidizing plasma such as oxygen or carbon dioxide plasma, or a hydrogenating plasma such as hydrogen or ammonia plasma. Helium or argon plasma may also be used.

[0094] An etching process 818 can then be performed on the wafer using sensors and actuators for in situ monitoring and control. ● Flow control 824 can include etchant concentration measurement. According to various embodiments, the concentration of the etchant is measured using two techniques: a) Conductivity measurement - HF has a linear dependence between concentration and conductivity, and b) Refractive Index Measurement - an optical metrology system measures the refractive index (RI) through a reflection type geometry that uses an optical window in contact with the solution to avoid turbidity, diffraction and absorption. Local Temperature Control 822: Etch rate depends on local temperature and mesh profile. Using a temperature actuator wafer chuck, various embodiments can control local temperature variations for process control. Environmental control of the processing chamber (not shown in FIG. 8C): The tool is enclosed and has a flow of inert gas. The pressure and overall temperature are monitored and controlled. A computer interface is used to facilitate operator safety and to monitor the etch using image processing, and to control the temperature and electric field. ● Electric field 826: Electric bias when applied to the semiconductor substrate can control the etch profile in real time. Over-etching due to migration of excess holes generated under the catalyst can be controlled by an external electric field. A negative bias at the backside of the wafer attracts the excess holes and prevents unwanted pitting of the Si. The etch rate decreases with increasing electric bias, but higher temperatures can be used to keep the etch rate high enough for high throughput. As the MSP-CICE is used for various pattern densities and shapes in different areas of the wafer, an electrode array is used to locally control and attenuate the electric field on different patterns to ensure etch uniformity. A wide range of current, bias and polarity settings, including fast pulses and periodic inverse waveforms, control the electric field across the wafer in real time. Transparent top electrodes such as ITO films on glass or sapphire wafers, doped Si wafers (transparent to IR), platinum mesh or optical fibers can be used above or below the wafer to perform optical measurements. The bottom electrodes can be arrayed for localized control, and a modular design is chosen to allow easy installation and investigation of various bottom electrode arrays. The top and bottom electrodes and the electrolyte are isolated from each other using a wafer chuck and wafer chuck-holder assembly. Crosstalk is minimized using simulation. Measurement of current and voltage across the substrate as etching progresses can be used to determine the number of alternating layers etched in 3D NAND flash processing or as an etch-stop indicator for nanostructure etching, for example when the substrate has a buried epilayer. In-line Optical Metrology 820: An optical imaging system including an RGB camera, optical fiber, and a spectral imaging setup is used to measure the reflectance of large sample areas in real time. Image processing algorithms determine completion of processing and collect data on the uniformity of MSP-CICE within and across samples.

[0095] Post-processing 828 may include etching the catalytic metal and rinsing and drying the substrate. To prevent collapse of the high aspect ratio etched nanostructures, fluid transfer can be used to prepare the wafer for transfer to a surface tension gradient (Marangoni effect), low surface tension fluid transfer, or critical point drying tool.

[0096] In one embodiment, the etch ratio can be adjusted to achieve the desired results based on the resistivity and doping of silicon and the required geometry and aspect ratio. Factors such as the electric field, temperature, and illuminance of the process chamber can also be altered to control the etch. Once the CICE process is complete, as detected by in-line metrology, the machine solution must be flushed out and replaced with a catalytic wet etchant. Then, efficient and highly controlled fluid exchange combined with advanced drying techniques and novel mesh architectures and / or ceilings are used to prevent the collapse of the tape pattern, as capillary forces can cause high aspect ratio nanowires to collapse when the device dries.

[0097] Once the design and fabrication of the MSP-CICE system (including the optical imaging system and electrical parameter measurements) is complete, optimal control techniques must be developed to operate the MSP-CICE system to fabricate wafer-scale device-specific VA-NSs. As explained earlier, it is important to have the ability to monitor the progress of etching at multiple different layers in a shaped nanowire for DRAM or 3D NAND flash stack. This requires local control of pattern geometry and measurement of current and voltage across the stack to determine, for example, the number of layers etched with a high level of precision across the entire wafer.

[0098] A key challenge is that a forward model of the entire system providing the relationship between the sensing output and the controlled variables across the wafer is expected to be highly nonlinear, making experimentally verified comprehensive models difficult to obtain due to the complexity of the MSP-CICE system. However, certain aspects of the process can be modeled through established physical models. For example, in various embodiments, the controlled variables can include temperature, chemical composition, and electric field, and the variation of the chemical composition can be analytically modeled with the help of equations governing transport. The control of the electric field and temperature can be distributed across a large array of actuators consisting of hundreds to thousands of actuators, providing localized control of the etch process. Their distribution can also be modeled using physical models. It can be modeled through a physical model.

[0099] However, models to establish the effect on the etching process are less clear. 2 It is expected to provide spectral information with high spatial resolution of 1 nm or better and high wavelength resolution of 1 nm or better. The optical, thermal, and electrical outputs of the system provide a large amount of sensory information that can be used to automatically control the process of the system using the aforementioned control variables. The automatic process control of the MSP-CICE system can be classified into two different categories: (i) offline optimization and adjustment of process parameters to obtain a target output, and (ii) real-time adjustment of process parameters to minimize defects and maximize yield. The latter relies on processes that are well established and provide large amount of data. The former relies on optimization of process parameters in the absence of large amount of data. In the following paragraphs, a scheme is described that can optimize process parameters to establish a baseline process for a given pattern geometry with the help of in-situ and offline measurements.

[0100] FIG. 9 shows a learning algorithm-based controller 900 that can be used to implement the first category of automatic process control in the absence of large data volumes: determining optimal process parameters for a target output with the help of learning algorithms, including evolutionary algorithms such as genetic algorithms, neural networks, etc. This scheme relies on both in-situ electrical and optical feedback, as well as offline measurements such as ellipsometry and CD-SEM on a pilot wafer. Due to the presence of this offline component, the cycle time for each experiment with a pilot wafer may be too high, so fewer experiments or each pilot wafer representing a combinatorial set is required, rather than individual experiments. This embodiment will be further described in the context of a genetic algorithm. The first step 910 of this scheme is to define a target output and a corresponding objective function for optimization. An initial "population" 920 is then generated. Genetic algorithms rely on interactions between individuals within the population, where each individual is a set of control variables or model parameters 925. In one embodiment, each population may be an experimental design and may be limited to a single wafer.

[0101] For example, if each wafer is comprised of 10×10 mm square zones that can provide electrical and optical feedback, then there can be O(700) such zones on each wafer, providing a population size of up to 700 for each experiment. In other embodiments, the population size can be kept to a lower number, such as 20, with each individual experiment having 35 copies across the wafer. This population is then used to perform the CICE process 930. Sensors are then used to extract information about the substrate before, during, and after CICE, as shown in step 940. The information sensed in this scheme can include the output of both in-line metrology sensors, such as imaging systems, and offline measurements on the wafer (CD-SEM, optical, electrical, etc.) (945). The sensed information is then fitted (950) against a desired output or objective function.

[0102] The desired output parameters include the spectral signature of the etched structures, electrical parameters such as resistance and capacitance across the wafer during the etch process, optical images of one or more portions of the wafer, and CD-SEM. Based on the objective function calculated using the sensed information, a new batch of control variables is generated using the population interaction parameters (965). CICE is then run using the new batch and the results are evaluated using the sensors. If the sensed information is within the desired range of results, the adjustment of the control variables is complete. If not, the control variable optimization process is repeated until the final number of wafers is reached (960). In one embodiment, the genetic algorithm controller is purposefully designed to approach the desired optimal process parameters for the actual process run, and the ultimate achievement of the desired process performance is taken over by a real-time in-situ process control scheme 935, which will be described next.

[0103] The second category of automated process control relies on data analysis for real-time adjustment of process parameters to achieve the desired process performance. Current advanced manufacturing factories, such as semiconductor manufacturing, rely heavily on these concepts to maximize manufacturing yields with high levels of automation. There are several concepts in this category of automated process control, ranging from run-to-run control to predictive maintenance. The key concept behind this scheme is to use large amounts of sensory information, such as in-situ light output, to perform real-time analysis based on heuristics (e.g., neural networks that determine the mapping between control and sensed variables), statistics (e.g., statistical process control), and physical or heuristic models to arrive at optimal process parameters. One example of a situation that would benefit from such a model is the ability to accurately predict the time delay from a change in a control variable to a corresponding change in the sensed output. Furthermore, such an approach can also be used to build a virtual MSP-CICE tool, a constantly adapting simulation of the actual tool that is a proxy for the physical forward model that can be used to tune the offline process via the first category. Such a virtual tool model is tool-specific and specific to the lithographic pattern being etched. Also, the same design may vary from tool to tool as manufacturing tolerances in electrical and thermal controllers etc. may cause different processing signatures in different tools.

[0104] Various embodiments of the CICE system include Si, Ge, Si x Ge 1-xA variety of substrates and multi-layers of semiconductors may be supported, including but not limited to GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, etc. Additionally, a variety of catalysts may be used, including but not limited to Ag, Au, Pd, Pt, Cu, Ni, Ti, Al, W, TiN, TaN, RuO2, IrO2, graphene, etc. Some embodiments of the MSP-CICE system may use a variety of patterning techniques, including but not limited to plasma etching, chemical vapor etching, electrodeposition (selective), etc. Removal techniques that may be used in some embodiments include but are not limited to chemical vapor etching, electrolytic etching, and / or wet chemical etching. Some embodiments may use, but are not limited to, a variety of etchants (e.g., HF, H2SO4, HCl, H2O, etc.), oxidants (e.g., H2O2, V2O5, KMnO4, O2, HNO3, electric field, etc.), solvents, additives (e.g., H2O, ethanol, IPA, DMSO, polymers (PVA, PLA, etc.), H2SO4, etc.), etchant conditions (e.g., liquid, vapor, solid gel, plasma), and / or catalyst-assisted etch processes (e.g., electrochemical etching, electroless chemical etching, gas phase etching, plasma etching, electrochemical / electroless chemical etching of "digital" layers, magnetic field electrochemical / electroless chemical etching, gel-based etching). Additionally, various local and global etch monitoring techniques may be used. Examples include, but are not limited to, electric fields (e.g., current, voltage, capacitance, inductance, impedance, conductance, etc.), optical metrology (e.g., using cameras, spectrophotometers, image processing, etc.), concentration measurements (e.g., refractive index, conductance of a solution), pressure (e.g., vapor pressure), and temperature (e.g., using thermocouples, IR cameras, etc.). Some embodiments may use local and global etching control based on electric fields (e.g., current, voltage, waveform, wavelength, frequency, duty cycle, pulsed electric fields, etc.), optical metrology (e.g., illumination), concentration (e.g., etchant concentration, mixing and diffusion), and / or temperature (e.g., using thermal chucks, micromirrors, etc.). Various embodiments of the setup can etch industry standard wafers or wafers undergoing standard CMOS processing.Some such embodiments may be compatible with the etchant. Some embodiments may provide automated handling of all substrate and etch ingredients and chemistries.

[0105] In one embodiment, the etchant can be in vapor form. The apparatus for vapor-based CICE includes local temperature control using a thermal chuck, monitoring of vapor pressure of each component, and / or application of an electric field in the form of a plasma. Vapor can be used to facilitate electrochemical / electroless chemical etching of the "digital" layers by: 1) alternating pulsing of H2O2 vapor and HF vapor; 2) alternating pulsing of H2O2 liquid and HF liquid; 3) alternating pulsing of H2O2 vapor and HF liquid; 4) alternating pulsing of H2O2 vapor and HF liquid; 5) alternating H2O2, plasma and fluoride ion flows / pressures to alternating porosity; and 6) using a strong oxidizer for porous layers and a weak oxidizer for non-porous layers.

[0106] (3D NAND Flash) The scalability of advanced memory architectures created by current pattern transfer techniques is limited by etch mask degradation, sidewall damage and non-zero taper due to high aspect ratio plasma etching. Non-volatile memory architectures such as 3D NAND flash require very high aspect ratio etching of over 64 layers of alternating materials to increase storage capacity per unit area. With increasing layers, the cost and reliability of (1) multi-layer deposition, (2) anisotropic high aspect ratio channel and trench etching, and (3) step etching to define contacts to each layer become the main limiting factors for scaling. Various embodiments provide vertical 3D memory architectures and semiconductor processing integration using anisotropic and highly selective etching techniques.

[0107] Various embodiments of the present technology define novel lithography patterns, material stacks and process flows that incorporate various interdisciplinary techniques to obtain improved memory performance and scalability. The 3D NAND Flash process flow incorporates semiconductor material stacks that enable metal or crystalline silicon gates, slope step etching, crystalline silicon channels and low-k porous dielectrics while reducing the number of lithography and high aspect ratio etching steps. In some embodiments, a wafer-scale multi-scale precision silicon superlattice etching (MSP-SiSE) fabrication tool for this purpose is also disclosed. The high selectivity and anisotropy of this etching technique allows for an unlimited number of 3D NAND Flash layers.

[0108] The ITRS roadmap for 3D NAND Flash predicts that the number of memory layers will steadily increase from 48 layers in 2016 to 512 in 2030, with an 80 nm half pitch. This requires significant development of highly anisotropic (-90°) high aspect ratio etching in alternating material layers. Current plasma etching methods involve expensive and time-consuming alternating deposition and etching steps to ensure this anisotropy and selectivity are maintained. Non-zero plasma etch taper angles limit the maximum number of layer stacks that can be reliably achieved. Non-zero taper also limits the number of layers that can be reliably scaled, as the channels etched by plasma etching have a much smaller critical dimension than the top layer defined by lithography. A workaround to overcome this limit by stacking multiple wafers with 64 memory layers each is inefficient, expensive, and increases the volume of the device. Separate lithography and etch steps are required for circular channels and rectangular slits because plasma etching cannot simultaneously and reliably etch different shapes due to aspect ratio dependent etching (ARDE). Fabrication of "steps" for contacts to individual layers requires multiple lithography and etch steps while trying to preserve etch masks. Various embodiments of the present technology aim to solve that by enabling inexpensive high aspect ratio etches with high selectivity and anisotropy that can scale to future demands of 3D NAND flash.

[0109] Two of the most popular architectures in the industry are BiCS and TCAT. Both architectures use the basic concept of stack (multiple layers of plates and dielectrics), punch (etch holes throughout the multi-layer stack), and plug (deposit memory film and pillar electrodes into the etched holes). A step etch is then performed to create contacts to each plate. BiCS uses a silicon oxide / poly-Si stack, while TCAT uses a silicon oxide / silicon nitride stack. In this case, silicon nitride is later replaced with a lower resistivity material for the conductors, such as tungsten. P-BiCS is a variation of BiCS that has better source-gate performance and lower.

[0110] A novel material stack and process flow is proposed that can be etched with SiSE for both vertical channel and vertical gate architectures. Catalyst patterns are defined lithographically such that both circular channels and rectangular slits can be etched simultaneously with high aspect ratio anisotropic etching. The material stack is made of bulk Si or alternating layers of semiconductor materials such as Si, Ge with different dopant types and / or doping concentrations. CICE etching results in layers with different etch and oxidation rates for layer-selective processing. This allows an increase in the number of layers and a decrease in the half pitch, resulting in a many-fold increase in storage capacity per die. Also, the cost per wafer is significantly increased by combining both channel and slit lithography steps with high aspect ratio etching steps. Any alkaline crystal plane dependent etch can be performed for tapers that can be converted to steps with plasma etching.

[0111] Some embodiments can be used for both charge trap (CT) and floating gate (FG) NAND flash memories. The bottom select gate (LSG) can be fabricated before or after the deposition of the alternating material stack. The memory material can be either CT or FG. A timed etch can be used to create a recess in the oxide porous layer of the 3D FG NAND. The deposition of polysilicon and core filler in the channel can be performed before (channel last processing) or after (dielectric last processing) the CICE etch. In one embodiment of the gate last approach, the Si and Ge layers can be etched and the Ge can be removed before filling with low-k dielectric. Thus, the final device is a 3D NAND flash memory array with more than 20 alternating layers of conductive (or doped semiconducting) and insulating materials, where the vertical gates or channels are highly vertical, with an angle greater than 89.5°. This angle is measured by taking a cross-sectional image using a scanning electron microscope (SEM) followed by image analysis software such as ImageJ. The average taper angle is measured using a nearly conformal straight line using a linear fit algorithm between the difference in feature sizes at the top and bottom of the critical feature. The critical dimension of the vertical gate architecture can be the width of the channel or the width of the trench between the channels. For vertical channel embodiments, the critical dimension is the diameter of the channel or the width of the trench between blocks of memory. Because the CICE process has vertical sidewall angles greater than 89.5°, the center-to-center distance between critical features such as circular channels and rectangular slits can be sub-20 nm. The dimensions of the critical features can be measured using metrology techniques such as SEM, CD-SEM, transmission electron microscope (TEM), atomic force microscope (AFM), etc. The circular channels can be arranged in a hexagonal fashion to create smaller 3D NAND cells.

[0112] The overall fabrication process for creating 3D NAND arrays for vertical channel and vertical gate architectures using SiSE is shown in Figure 13. As 3D NAND devices require alternating layers of conductive and insulating lines, the SiSE process is designed to obtain alternating layers of materials with different processing parameters such as oxidation and etching rates to allow further processing via substitution or modification of layer materials. As shown in Table 1, different routes can be taken to obtain alternating layers of conductive and insulating structures. Routes I and II describe the initial substrates required to obtain the superlattice. Route I uses a bulk silicon wafer without multilayer deposition, whereas Route II uses a stack of silicon layers with alternating doping concentrations. Routes A to G can be used with both routes I and II, i.e., bulk silicon or with alternating layers of Si with different doping concentrations. Route A provides options including step etching by using crystallographic or graded etching to create a taper. The dashed lines represent some of the options this step can be implemented in the process flow. Paths B through G describe some of the ways in which the superlattice produced by the SiSE process can be modified or replaced to obtain the final 3D NAND array.

[0113] Table 1: Routes I and II for 3D NAND array fabrication using SiSE based on Figure 13

[0114] [Table 1]

[0115] The main purpose of this alternating stack etch is to create a large difference in the etch rate or thermal treatment (such as oxidation or nitridation) rate between different layers (layer A and layer B in a bilayer stack) and use this difference to modify the stack and ultimately obtain an insulating / conducting multi-layer structure.

[0116] The porosity of the layer is a function of the etchant concentration, the doping of the silicon substrate, and the current density across the wafer in SiSE. Multi-layer embodiments of porous and non-porous silicon made in SiSE consist of porous layers with porosity between 30% and 75%, while non-porous layers have porosity less than 10%. Porosity is measured in cross-sectional SEM and TEM images and processed using image processing software such as ImageJ. Porosity of a single layer may be measured using gas adsorption experiments such as using the Brunauer-Emmett-Teller (BET) theory. Here, CICE is performed on a bulk substrate with a patterned catalyst and exposed to a current density to create a thick layer of porous silicon with porosity parameters corresponding to the porous set of alternating layers.

[0117] 10A-10E show an example of a catalyst mesh according to one or more embodiments of the present technology. In FIG. 10A, isolated catalyst nanodots 1010 and trenches 1020 are shown. In FIG. 10B, the catalyst nanodots 1010 and trenches / slits 1020 can be connected by lines 1030 (top view) or the diameter and alignment of the dots and trenches can be controlled to ensure a connection as shown in the bottom view of FIG. 10B. In FIG. 10C, staggered connected catalyst nanodots 1010 and trenches / slits 1020 are shown. In FIG. 10D, connecting links 1040 are shown patterned into catalyst features for a BiCS type layout with sparse wordline trenches / slits 1020. In FIG. 10E, connecting links 1040 are shown patterned into catalyst features for a P-BiCS type layout with wordline trenches / slits every two rows of channels.

[0154] In another embodiment, features such as VC 3D NAND holes or VC 3D NAND lines are etched into bulk silicon using plasma etching. A catalyst-free electrochemical etch is then performed on the etched substrate to create alternating layers of silicon with high and low porosity porous layers with sufficient etch or thermal treatment selectivity between the layers. This results in a multi-layer stack of high aspect ratio features. One of the layers is then oxidized or selectively replaced to create the 3D NAND device.

[0118] Route I - SiSE with catalysis and electrochemical etching A substrate, such as a bulk silicon wafer, is patterned with a catalyst and etched with a solution containing a fluoride species and (optionally) an oxidant species. During the SiSE process, an electric field parameter, such as current density, is modulated to create alternating layers of different porosity. In one embodiment, the current density is modulated using a square wave function with one zero and one non-zero value, such that a "zero value" current density etch proceeds with catalytic etching only, while a non-zero value uses a combination of catalytic and electric field etching to create porosity in the layer. The resulting superlattice thus comprises alternating layers of zero and non-zero porosity, along with high aspect ratio etched features that correspond to the inverse of the catalytic pattern. In another embodiment, the current density can be modulated using a square wave function with negative and positive values, such that a "negative value" current density etch prevents catalyst wander, and a "positive value" current density etch creates porosity in the layer. This route does not require expensive processing such as deposition and etching of multiple alternating layers of material.

[0119] Route II - SiSE with catalytic etching Route II requires alternating layers of semiconductor materials varying in at least one of the following: material type, doping concentration, and properties of the dopant material. These layers can be deposited via epitaxy, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. to create a superlattice in the SiSE. Table 1 shows an example of various combinations of alternating semiconductor multi-layers that can be used in the process flow described above, with silicon at the center. In Table 1, the donor and acceptor doping of silicon is indicated as p- and n-Si, with "++" indicating the doping concentration. For example, p++Si has a boron concentration of 1e18cm -3 This means highly doped silicon that is equal to or greater than 10 ...

[0120] The etched stack of alternating materials, with alternating morphology as a result of the SiSE process, is post-treated with thermal oxidation and / or ALD to obtain the desired stable configuration of etched channels and slits. FIG. 11 shows an embodiment of a process flow 1100 of alternating stacks of highly doped and undoped (or low doped) silicon. The highly p-doped silicon becomes porous, and this porosity can be controlled based on the etchant concentration and the doping of the silicon layer. The low doped silicon does not change morphology after etching. The porous silicon can then be oxidized at a much faster rate than the non-porous silicon. A thermal step that transports dopants out of the oxidized porous silicon (OPS) and flows more dopant gas then transforms the low doped silicon into word lines in the vertical channel regime. A short anisotropic oxide etch followed by ALD of metal makes the word lines continuous on both sides of the etched channel, and annealing forms a low resistivity silicide WL. This process is referred to as "dielectric / gate first" because the final etched and heat treated stack is the material stack that is deposited (or epitaxially grown) prior to the SiSE process.

[0121] FIG. 11 shows a process flow 1100 for high aspect ratio (HAR) etching of channels and slits with a catalytic mesh pattern similar to that shown in FIG. 10. The etched stack of alternating materials with staggered morphology as a result of the SiSE process is post-processed with sacrificial layer removal and atomic layer deposition (ALD) to obtain the desired stable configuration of etched channels and trenches / slits. As shown in FIG. 11, during process step 110, deposition of alternating multilayers is performed. This step is not necessary if the system starts with a bulk silicon substrate. During process step 1120, the catalytic mesh is patterned and then SiSE is performed to obtain alternating layers of porous and non-porous materials. During process step 1130, oxidation of the porous layers is performed. The oxidation process may also oxidize the thin edges of the non-porous layers that need to be removed. Process step 1140 is used to remove the oxide using an anisotropic etch such as an atomic layer etch or a plasma etch after lithography on the blocks of material that should not be etched. Processing steps 1150 to 1160 comprise multiple lithography, deposition and etch processes required to create a 3D NAND flash memory array. In some embodiments, processing step 1150 includes selective deposition of metal on a non-porous layer followed by silicide formation. Processing step 1160 includes lithography and deposition of memory films, e.g., triple layer silicon oxide, silicon nitride, silicon oxide (ONO), poly-Si with charge trapping (CT) 3D NAND, and deposition of core filler and low-k dielectrics using ALD and CVD.

[0122] FIG. 12 illustrates a sacrificial process flow 1200 for vertical channel 3D NAND, according to one or more embodiments of the present technology. This process is similar to that of FIG. 11, with the major difference being the post-processing steps after CICE. Instead of modifying one set of alternating layers, they are etched away and then replaced with a conductive material such as tungsten, cobalt, titanium nitride, tantalum nitride, etc. CICE is first performed during operation 1210 on an alternating stack of highly doped and undoped (or low doped) silicon. The highly doped silicon becomes porous, and this porosity can be controlled based on the etchant concentration and the doping of the silicon layers. The low doped silicon does not change morphology after etching; that is, it remains crystalline and non-porous. If bulk Si with a time-varying electric field is used to create layers with alternating porosity, alternating stacks are not required. Polysilicon and core filler are deposited in the cylindrical channel in operation 1220 to provide support during the sacrificial etch 1230 of one of the alternating layers. Subsequent deposition of metal (e.g., tungsten, cobalt, titanium nitride, tantalum nitride) using CVD, ALD, or electroplating in step 1240 creates the wordlines. This process is referred to as "dielectric / gate last" because the material stack deposited (or epitaxially grown) before the CICE process is replaced during process 1240, either partially (one set of alternating layers is replaced with metal) or completely (a second set is etched away and replaced with a low-k dielectric).

[0123] Table 2 shows some examples of layer modifications outlined in FIG. 13. Modifications where one layer is selectively "etched away" are sacrificial process flows where gates and / or dielectric films are replaced. This is similar to the TCAT process flow for 3D NAND manufacturing. Some embodiments of this are paths C, D, E, F, G and the process shown in FIG. 12. In such process flows, when one set of alternating layers is etched away, it is necessary to fill the vertical channels with material to support the structure. The etched stack of alternating materials, which has an alternating morphology as a result of the SiSE process, is post-processed with sacrificial layer removal and / or ALD to obtain the desired stable configuration of etched channels and slits. In one embodiment, the high aspect ratio lines are stabilized by creating lithographic links between them and then removing them. Polysilicon and core filler material are deposited in the cylindrical channels to provide support during the sacrificial etching of one of the alternating layers. Subsequent metal deposition (e.g., tungsten, cobalt, nickel, tantalum nitride, titanium nitride, copper) creates the wordlines. This process is called "dielectric / gate-last" because the material stack deposited (or epitaxially grown) before the SiSE process is replaced either partially (one set of alternating layers is replaced with metal) or completely (a second set is etched away and replaced with low-k dielectric).

[0124] Table 2: Pathway for 3D NAND array fabrication by changing materials in a superlattice made of SiSE based on Figure 13

[0125] [Table 2]

[0126] Figures 14 to 16 show a portion of a process flow for processing alternating layers of porous and non-porous silicon layers produced by SiSE to create a vertical channel 3D NAND array. Figure 14 includes one replacement step and represents path C of Figure 13. Figures 15 to 16 include two replacement steps, where Figure 15 represents path D as shown in Figure 13 and Figure 16 represents path G.

[0127] In Figure 14, there are several steps including: 1) SiSE to create high aspect ratio channels and slits with alternating layers of non-porous and porous Si; 2) oxidation of the porous layers where the thin edges of the non-porous layers and the connecting links are also oxidized; 3) lithography to block the slits by depositing a material such as a polymer and etching away the material in the area around the slits; 4) deposition of films using ALD and CVD to form the memory core, e.g. oxide-nitride-oxide layers, poly-Si and oxide core; and 5) material removal from the slits and lithography (polymer, oxidized connecting links, etc.) to protect the channels. 1) selective removal of material from the slits using selective etching such as oxygen plasma to remove the polymer or atomic layer etching to remove the oxide links; 2) selective removal of the silicon layer using an etchant such as TMAH without affecting the oxidized porous silicon layer; 3) deposition of a conductive material (e.g., W, Co, TiN) using chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering or physical vapor deposition (PVD) followed by etch-back to isolate the conductors; and 4) filling the exposed areas with an insulating material (not shown in the image).

[0128] Figure 15 includes the steps of: 1) SiSE to create high aspect ratio channels and slits with alternating layers of non-porous and porous Si, 2) oxidation of the porous layers where the thin edges of the non-porous layers and the connecting links are also oxidized, 3) lithography to block the slits by depositing a material such as a polymer and etching away the material in the area around the slits, 4) deposition of films using ALD and CVD to form the memory cores, e.g. oxide-nitride-oxide layers, poly-Si and oxide cores, and 5) material removal from the slits and lithography (selective removal of material from the slits, e.g. polymer and oxidized connecting links) to protect the channels. using selective etching such as oxygen plasma to remove the polymer and atomic layer etching to remove the oxide links); 6) selective removal of the oxide layer using an etchant such as HF without affecting the silicon layer; 7) deposition of a thin oxide layer using ALD and deposition of a conductive material (e.g., W, Co, TiN) using chemical vapor deposition, atomic layer deposition, sputtering, etc., followed by etch-back to isolate the conductors; 8) selective removal of the silicon layer using an etchant such as TMAH without affecting the deposited conductive material; and 9) deposition of an insulating material such as silicon oxide using ALD.

[0129] FIG. 16 includes the steps of: 1) SiSE to create high aspect ratio channels and slits with alternating layers of non-porous and porous Si; 2) lithography to block the slits by depositing a material such as a polymer and etching away the material in the area around the slits; 3) deposition of films to form the memory core, e.g., oxide-nitride-oxide layer, poly-Si and oxide core; and 4) lithography and material removal from the slits to protect the channel (selective removal of material from the slits, such as polymer and silicon connecting links, can be achieved by using oxygen plasma to remove the polymer and silicon phosphorus. 5) selective removal of the porous silicon layer using etchants such as HF or HF+H2O2 without affecting the non-porous silicon layer; 6) deposition of a conductive material (e.g., W, Co, TiN) using chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, etc., followed by etch-back to isolate the conductor lines; 7) selective removal of the silicon layer using etchants such as TMAH without affecting the deposited conductive material; and 8) deposition of an insulating material such as silicon oxide using ALD.

[0130] 17 shows an embodiment of a 3D NAND architecture with vertical gates and horizontal silicon channels. As shown in FIG. 17, which represents path F of FIG. 13, the steps include: 2) oxidation of the porous layers whereby the thin edges of the non-porous layers and the connecting links are also oxidized; 3) deposition of films forming the memory core, e.g., oxide-nitride-oxide layers, poly-Si and oxide core, using CVD, ALD, etc.; 4) lithography to create a mask for subsequent etching of the memory material; 5) etching of the memory material from the unpatterned areas using atomic layer etching, plasma etching, etc.; 6) deposition of gate material, such as W, poly-Si, Co, TiN, etc. (in other embodiments, the gate material can be patterned by removing the lithographed mask, depositing the gate material over the entire structure, performing lithography, and etching away the gate material in the unpatterned areas); 7) removal of excess gate material and the lithographed mask using plasma etching or chemical etching; and 8) filling the exposed areas with an insulating material, such as silicon oxide (not shown in the image).

[0131] The non-sacrificial route is similar to the BiCS 3D NAND fabrication process flow and does not involve the etching away of any layers such as route B. The etched stack of alternating materials with staggered morphology as a result of the SiSE process is post-treated with oxidation (thermal, anodic, etc.) and / or ALD to obtain the desired stable configuration of etched channels and slits. For example, highly p-doped silicon becomes porous and this porosity can be controlled based on the etchant concentration, electric field and doping of the silicon layer. Lightly doped silicon does not change morphology after etching. Porous silicon can then be oxidized at a much faster rate than non-porous silicon. A thermal step that transports dopants out of the oxidized porous silicon (OPS) and flows more dopant gas then transforms the lightly doped silicon into wordlines in the vertical channel regime. An optional short anisotropic oxide etch followed by ALD of metal makes the wordlines continuous on both sides of the etched channels and annealing forms the low resistivity silicide WL. This process is referred to as "dielectric / gate first" because the final etched and heat treated stack is the material stack that is deposited (or epitaxially grown) prior to the SiSE process.

[0132] It should be noted that the superlattices used in the various embodiments start with Table 2 (Porous Si / Non-Porous Si) but can be fabricated using Route I or II. Route A, which is also described as including a step etch, can be added to the process flow of any of the routes. Other embodiments of the superlattice include Ge, Si x Ge 1-xThe superlattice may include alternating layers of different materials and / or different porosities, such as GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, etc. All layers of the superlattice are also non-porous, and the alternating layers still have different process rates, such as oxidation, chemical etching, etc. An example is a p-doped Si / n-doped Si superlattice, where an alkaline etchant such as TMAH or KOH will only etch p-type Si under electrical bias. Route B can also be used to create a vertical gate based 3D NAND flash architecture with a crystalline horizontal silicon channel.

[0133] Various embodiments of the CICE process use a patterned catalyst that sinks into the substrate as etching proceeds, leaving the unpatterned areas as high aspect ratio features. The catalyst mesh can be patterned to etch both the channel and the word line slits (trench) in one lithography step, and the CICE process can etch both these features simultaneously. Some examples of catalyst meshes are shown in Figures 18A-18C. To prevent the catalyst mesh from wobbling and ensure transport of the etchant solution, electric fields, ceilings, and / or linked continuous patterns can be used. The resulting high aspect ratio features can be prevented from collapsing by mitigation techniques such as using surface tension gradient agents (ethanol, isopropyl alcohol, etc.), supercritical drying, and lithographically connected features. These two constraints can also be met by using patterning techniques with linked features, or by using controlled deposition or etching after the CICE process to convert the high aspect ratio linked structures into the desired 3D NAND configuration.

[0134] The fabrication of the SiSE catalyst pattern requires multiple lithography and etching steps. The critical dimensions and overlay requirements for various layout schemes of 3D NAN flash arrays based on both vertical channel (VC) and vertical gate (VG) architectures are shown in Figures 18A-18C. Figures 18A-18C show the etched features. As shown in Figures 18A-18C, "a" represents the width of the blocks of the memory channel, "b" represents the width of the lithography link, "c" is the distance between the blocks of width a, "d" represents the diameter of the circular channel, "e" is the pitch between the lateral holes, "f" is the shortest pitch of the holes arranged in a hexagon, and "g" is the shortest distance between the blocks of width "a" and the circular channel. The thin connecting lines of width "b" are called lithography links and connect isolated semiconductor features to improve the stability of the interconnected high aspect ratio multi-layer semiconductor structures that are subsequently etched. The intended design of the catalyst mesh depends on the layout of the 3D NAND flash array and incorporates lithographic links to stabilize the etched structures and optionally improve the diffusion of etchants as well as prevent wandering of the catalyst features.

[0135] 18A-18C show the layout and dimensions of an embodiment of a 3D NAND array. Two sets of dimensions are described below: one is aggressive scaling limited by lithography constraints, and the other is by assuming a minimum channel diameter of 50 nm for VC-based devices. VC-based devices have the potential for more aggressive scaling because lithography patterns require primarily lines and spaces (L / S) and not holes or pillars, where L / S can be made smaller through multiple patterning. It can be done.

[0136] Some embodiments of the dimensions of the features in FIG. 18 are as follows: FIG. 18A shows a VC 3D NAND configuration with two rows of staggered holes per block. For a half pitch of 20 nm (X direction), dots in Y direction of 25 nm, and blocks of 35 nm, a=60 nm, b=10 nm, c=10 nm, d=25 nm, e=40 nm, f=35 nm, and g=10 nm. For a half pitch of 35 nm (X direction), dots in Y direction of 42 nm, and blocks of 85 nm, a=110 nm, b=10 nm, c=20 nm, d=50 nm, e=70 nm, f=60 nm, and g=10 nm. FIG. 18B shows a VC 3D NAND configuration with four rows of staggered holes per block. For a half pitch of 20 nm (X direction), dots in Y direction of 25 nm, and blocks of 65 nm, a=120 nm, b=10 nm, c=10 nm, d=25 nm, e=40 nm, f=35 nm, and g=10 nm. For a half pitch of 35 nm (X direction), dots in Y direction of 42 nm, and blocks of 120 nm, a=220 nm, b=10 nm, c=20 nm, d=50 nm, e=70 nm, f=60 nm, and g=10 nm. Figure 18C shows a vertical gate 3D NAND geometry, where the lines of width "a" indicate the silicon channel dimensions, and in one embodiment, a=20 nm, b=10 nm, and c=20 nm.

[0137] The example dimensions listed in FIG. 18 are limited by the lithography and electronic properties required for the memory array. The VC 3D NAND channel holes must be filled with memory layers, e.g., oxide-nitride-oxide (ONO) and polysilicon channel materials. The minimum diameter of the poly-Si channel, constrained by the string read current and the allowable electric field enhancement, is about 20 nm. The minimum ONO thickness, constrained by device performance and reliability, is about 15 nm. Thus, the minimum hole diameter is about 50 nm. In certain process flows, an oxidation step is performed after the SiSE to create alternating layers of porous silicon oxide and non-porous silicon. In this oxidation step, a thin layer (less than 5 nm) of non-porous silicon at the edges can also be oxidized. This thin layer can be kept as a memory layer or removed. If removed, for example, oxidation followed by 5 nm of material removal changes the effective dimensions of the pattern with a factor of two change in the oxide dimensions, i.e., the diameter of the channel increases by 10 nm, the width of the word lines decreases by 10 nm, and then the width of the space between the lines increases by 10 nm. Therefore, the initial dimensions should be adjusted accordingly based on the final desired parameters.

[0138] Electron beam lithography can write sub-10 nm features but has large overlay, whereas photolithography has good overlay but low resolution, making it very difficult to fabricate sub-30 nm features with smaller contacts for structural stability. Some embodiments can use photolithography and imprint lithography to pattern the film.

[0139] The 3D NAND feature designs shown in Figures 18A-18C can be patterned using lithography techniques such as photolithography with multiple patterning, imprint lithography, e-beam lithography, directed self-assembly, laser interference lithography, etc. The process of creating masks for these various lithography techniques is described below.

[0140] (Patterning by imprint lithography) FIG. 19D shows a catalyst design with a linked structure to prevent wandering and improve diffusion. In one embodiment, the link pattern has a width of 10 nm, a pitch of 25 nm, and the lines are not regularly spaced. To fabricate such a pattern, a grid pattern is created using electron beam lithography. Elements of the grid are then removed by patterning the linked structure using electron beam lithography and etching away selected areas of the grid. The resulting pattern can then be etched into a template substrate to create a master template for imprint lithography.

[0141] Imprint lithography can be used to pattern non-periodic irregular patterns with high resolution and narrow pitch. For imprint lithography, a template can be made to print the catalyst patterns shown in Figures 18A to 18C. Template fabrication is shown in Figures 19A to 19C. Master templates 1910 and 1920 shown in Figures 19A and 19B can be made using electron beam lithography. In one embodiment, the features in Figure 19A can be made using two sets of L / S perpendicular to each other to create a 20nm x 20nm block with a pitch of 100nm, and the features in Figure 19B can be made using 20nm diameter holes with a pitch of 40nm and 20nm lines with a pitch of 80nm.

[0142] The final master template 1930 shown in FIG. 19C can be made by imprinting with the master template 1910 shown in FIG. 19A. The imprinted features are etched into a hard mask, and then the master template 1920 shown in FIG. 19 can be patterned after alignment with the features imprinted by the master template 19A. According to various embodiments, the alignment of the template can be performed using an alignment method, where within a lithography field, the template 1920 shown in FIG. 19 has features that are intentionally offset by changing direction and size from one subfield to the next. After imprinting, the subfield with the ideal alignment requirement is selected and used to create the final master template 1930 shown in FIG. 19C using a step-and-repeat method. Based on the overlay alignment requirement, the final master template 1930 shown in FIG. 19C can also be made using photolithography. In this case, the second template 1920 shown in Fig. 19B is a photolithography mask with larger dimensions to allow for photolithography resolution. These larger dimensions can then be reduced using plasma etching techniques. Fig. 19D is an example of a lithographically linked pattern where lines are made with imprint lithography (the template is made with e-beam lithography) and dots are aligned and printed using imprint or photolithography, or vice versa.

[0143] In another embodiment, the fabrication of a pattern such as that of Figure 19D is done using photolithography and multiple patterning. Then, the grid elements are removed by patterning and shrinking holes in selected areas and etching away the grid lines, thereby creating the link pattern. Due to the minimum pitch limitations of photolithography, the patterning of the holes may take multiple steps.

[0144] Current methods of photolithography are 193 nm wavelength with immersion, but use a three-layer resist and are limited to a half pitch of about 38 nm for lines and spaces. Methods such as Self-Aligned Double (SADP) / Quad (SAQP) patterning and Litho-Etch-Litho-Etch (LELE) are needed to achieve smaller dimensions and tighter pitches. This requires multiple deposition and etching steps and is inherently suitable for periodic patterns. However, the minimum resolution and pitch of circles is large. In a VG 3D NAND architecture without circles, photolithography and trim etching can be used to create lines and spaces perpendicular to each other. The process of patterning VG 3D NAND is more complex.

[0145] Figures 20a to 20j show how photolithography can be used to create such patterns. In Figure 20, the catalyst has been deposited after photolithography processing and the exposed areas (silicon) are now covered with catalytic material. The catalyst deposited over the patterned features can optionally be lifted off. Other embodiments can be used where photolithography is performed on a catalyst film and then the catalyst is etched away in the exposed areas. In that case the pattern would be the inverse of that shown in Figure 18.

[0146] Figures 20a to 20e show both cross-sections (top view) and top views of the lithography steps. Figures 20f to 20j show only top views. In Figure 20a, lithography links are created using a first hard mask, squares with 40 nm sides and a pitch of 80 nm (y-direction) and 40 nm (x-direction) patterned in polysilicon (pink) on a silicon nitride (blue) layer. In Figure 20b, a trim etch is performed to obtain squares with 10 nm sides. In Figure 20c, the features are planarized with spin-on glass to align and pattern lines with a width of 40 nm and a pitch of 80 nm. In Figure 20d, a spacer material is deposited to increase the line width to 70 nm. In Figure 20e, the lines and squares are etched into a hard mask layer, such as silicon nitride. In Figure 20f, LELE is performed. That is, 50 nm holes are aligned and patterned with a pitch (x-direction) of 80 nm and a pitch (y-direction) of 80 nm, and etched into the underlying silicon nitride with a trim etch to reduce the diameter to 25 nm. In Figures 20g, 20h, and 20i, step 20F is repeated with a shifted alignment. In Figure 20j, a catalyst material can be deposited.

[0147] Density multiplication can be used using direct self-assembly instead of multiple LELE steps in photolithography. Figure 21 shows a process flow for making catalyst patterns with substantially connected catalyst features using self-assembly and lithography. In Figure 21a, dots are patterned using photolithography. In Figure 21b, these dots are used to direct block copolymers to double the density using directed self-assembly. Lines are then patterned to block areas according to the design of the 3D NAND flash catalyst (Figure 21c). Subsequent etching transfers the dots not blocked by lines to a hard mask such as silicon nitride or carbon (Figure 21d). Another lithography step is performed to pattern lines (Figure 21e) and etch into the hard mask (Figure 21f). The resist is then removed to expose the final features of the hard mask (Figure 21g). In Figure 21h, the catalyst material is deposited. This process does not show lithography links, but can be incorporated into a process flow similar to Figure 20. Self-assembly patterning can also be used to create imprint lithography templates.

[0148] In 3D NAND flash designs, simultaneous etching of circular channels and rectangular slits cannot be reliably achieved in plasma etches with precise control over the sidewalls. Similarly, for features with connecting links, sub-10 nm connections between pillars cannot be maintained at high aspect ratios. Dry plasma etching processes used in the semiconductor industry to anisotropically etch highly controlled nanopatterns require expensive vacuum equipment and do not easily preserve cross-sectional shape when patterning high aspect ratios (>50:1). They suffer from etching challenges such as aspect ratio dependent etching (ARDE) and etch taper.

[0149] On the other hand, SiSE processing allows the anisotropic etching of the required patterns, allowing the creation of superlattices without loss of resolution. However, there are various challenges that need to be addressed to make SiSE a viable technology for commercialization. In this section, we discuss these challenges and solutions to achieve wafer-scale etching of high aspect ratio nanostructure stacks in semiconductor materials.

[0150] A step-by-step description of the different processes that can be used in this new manufacturing method is provided. The parameters that need to be optimized at each step for good electrical performance of the final device, mechanical stability at intermediate steps, CMOS compatibility, cost and throughput are also listed in the following sections.

[0151] Conventional 3D NAND processing uses alternating layers of SiO / SiN or SiO / poly-Si. These layers are etched and optionally replaced with a conductive material such as W to obtain a stack of alternating conductive and insulating lines that form the wordlines and dielectric of the 3D NAND cells. In various embodiments, alternating layers of semiconductor material may be used instead of SiO / SiN or SiO / poly-Si. Because SiSE can simultaneously etch semiconductor material while changing its morphology depending on tunable material properties such as doping concentration and dopant type, the alternating layers are designed to ensure selective removal or oxidation to obtain the final conductive and dielectric lines.

[0152] This is not an issue for Path I (see, for example, FIG. 13) where a bulk silicon substrate is used for SiSE and deposition of alternating layers need not be considered.

[0153] The method employed for deposition of the alternating layers or "superlattices" depends on commercial availability, cost, throughput, growth rate, thermal budget, number of layers, thickness of layers, mobility and resistivity of layers before and after etching, employability of crystallographic etching, etc. For example, poly-Si layers need to be thicker than epitaxial silicon to overcome grain boundary problems and to obtain good electrical conductivity of the etched word lines. Since dopant diffusion is higher in poly-Si than in crystalline Si, poly-Si layers may require thin diffusion barrier layers between alternating doped layers to suppress dopant diffusion between layers. In the case of epitaxial silicon, taper etching to create abrupt contacts can also be performed on crystalline layers by using alkaline etchants such as KOH, TMAH, and EDP.

[0154] Epitaxial (epi) growth of silicon in current production is based on chemical vapor deposition (CVD), a process in which thin solid films are synthesized from the gas phase by chemical reactions. High temperature epi growth of silicon above 1000 °C provides high throughput, in situ doping and prevents contamination. On the other hand, molecular beam epitaxy (MBE) allows for abrupt steps in the doping profile but has a very low growth rate. Low temperature epitaxy using CVD at about 650 to 850 °C offers a compromise for the growth of silicon superlattices as listed in Table 1. Temperature, pressure, gas flow rates, substrate preparation, surface treatment, and oxidation prevention are the main parameters that determine the quality of the epi superlattice. The partial pressure of the gas used for doping, such as B2H6 or PH3, determines the doping concentration of the epi layer. A lower total pressure during growth allows for better bonding due to reduced contamination from the gases of the previous layer. All of these parameters play an important role in epi growth, but as will be explained further below, the temperature, dopant concentration, and epi layer thickness are the most important as they determine what the outcome of the subsequent processing steps will be. Temperature: The temperature of epi growth depends on a variety of factors. Crystallinity of the epi film can be achieved at temperatures ranging from 500°C and above. At lower temperatures, dopant diffusion is reduced and in some embodiments steeper profiles can be obtained, but the growth rate is slower. Depending on the type of dopant in silicon and its diffusivity, in some embodiments the diffusivity across the highly doped / lightly doped interface can be calculated. Dopant Concentration: Using simulations of Fick's Law with appropriate modifications to electric field effects, concentration values, gradients, etc., we determine what the doping material and concentration will be for each alternating layer to obtain the required final diffusion profile. This depends on the temperature of the reaction chamber, the thermal budget required for subsequent processing steps, the concentration gradients across the layers, and the presence or absence of defects during epi growth. The diffusion coefficient of common dopants in silicon depends exponentially on temperature (D=D0.exp(-E a / kT). Slow diffusers (As and Sb) are preferred over fast diffusers (P, B and In), and the choice of dopant also depends on the solid solubility limit in silicon. Layer thickness: Depending on the width of the final wordline, the thickness of the conductive layer must be adjusted to minimize resistivity, while the thickness of the dielectric layer must be adjusted to reduce parasitic capacitance and maximize resistivity. If the wordline layer is composed of polycrystalline silicon, the increased resistance due to grain boundaries must be taken into account.

[0155] Consider the example of a P++ / P superlattice where one layer has a boron concentration of 1E18 and the other layer has a boron concentration of 1E15. For epitaxial growth at 650°C and 10 Pa pressure in an ultra-clean environment, the deposition rate is about 100 nm / min. At this temperature, the diffusion constant of B is 7.7E-20 cm 2 / s. To determine the diffusion profile, in some embodiments, it is necessary to know the thickness of each layer and the length of time the wafer is in the chamber, i.e., the number of layers that need to be grown. With a boron concentration of 1E18, the wordline resistivity is 0.04 ohm-cm. This can be further reduced by incorporating metal to form a silicide, or by annealing after a subsequent SiSE process to transfer all the dopants from the oxidized porous layer to the crystalline silicon layer. For a layer thickness of 100 nm, the total growth time for 256 layers is about 5 hours. The maximum diffusion then occurs in the first layer grown, and the diffusion length is X j =2 * sqrt(Dt). This gives a maximum diffusion length of 0.8 nm. Thus, the effect of temperature on the diffusion length is minimal since the diffusivity is very low at 650°C. Further factors such as multi-level concentration gradients and electric fields can be considered when using simulations. A slow deposition rate such as 100 nm / min is not justifiable from a cost perspective. At 1000°C, the deposition rate is 10 microns / min and 256 layers can be deposited in less than 3 minutes.

[0156] However, the diffusion constant of boron at this temperature is 1.39E-14 cm 2 / s and a diffusion length of 31 nm. To find a compromise between these two parameters, in some embodiments, a temperature of 800°C or thereabouts is chosen, which gives a deposition rate of 1 micron / min. This results in a deposition process of 256 layers taking about 30 minutes, and 10 minutes for 100 layers. The diffusion length of B is then about 6 nm at the bottom layer (worst case) for 256 layers and 3 nm for 100 layers. For a layer of 100 nm thickness, a sub-5 nm junction is sufficient. However, the junction length mentioned above indicates the distance from the interface where the concentration changes by 1 / e. This is not enough to make a reliable process. Therefore, the SiSE process is adjusted to ensure that the dopant concentration at which the morphology changes from solid to porous is abrupt. This can be done by adjusting the etchant concentration.

[0157] In some embodiments, plasma-enhanced ALD can be used to plug the pores of the porous layer. ALD of SiO2 is used to fill the holes and slits etched with SiSE. The substrate is then planarized to allow for the next processing steps, including lithography and plasma etching. According to various embodiments, lithography can be performed to open channels and prevent deposition of films in the slits. Memory layers (such as oxide-nitride-oxide), poly-Si channels, and core filler materials can then be deposited in these channels (vertical holes).

[0158] In the case of epitaxially grown silicon crystal layers, alkaline etching agents such as KOH and TMAH are used. <100> The crystal planes can be anisotropically etched, reducing the number of etching and lithography steps required for step etching to create contacts to each word line layer in the vertical channel structure. This alkaline wet etch can be performed on the as-grown epitaxial material stack before or after CICE. If one of the alternating layers is highly p-doped, TMAH can be used instead of KOH, depending on the relative etch rates along the crystal planes and with different dopant concentrations.

[0159] FIG. 22 shows an example of a 3D NAND step etch according to one or more embodiments of the present technology. After doped / undoped Si epitaxial growth, a taper etch process is performed using an alkaline etchant to create contact areas for the word lines. The length of the protrusion of the contact areas depends on the thickness of the insulating layer. Another embodiment of this process involves using electrochemical etching to create alternating layers of silicon with different porosity based on the doping of the individual layers, without CICE. This stack is then etched with a plasma etch and a slope etch before the electrochemical etch to create the steps.

[0160] Figure 23 is similar to Figure 22, with the main difference being that the taper etch is done on bulk Si instead of the alternating semiconductor layers. SiSE is then performed on the taper etched bulk Si, after which a selective plasma etch is performed to expose the contact areas on the conductor lines after the 3D NAND memory fabrication steps.

[0161] In path I, the bulk silicon is etched, and in path II, the epitaxially grown crystalline layer of silicon is etched. To create the taper, crystallographic etchants such as KOH, EDP, TMAH, etc. can be used. For example, 30% KOH or 10% TMAH at a temperature of 60° C. can be used.

[0162] Some embodiments use a step etch or angled plasma etch process on bulk silicon with an alkaline etchant to create the wordline contact area. The crystallographic etch creates a 54.74° taper, so the length of the contact pad protrusion depends on the thickness of the insulating layer. This reduces the number of etching and lithography steps required to etch the step and create contacts to each wordline layer in a vertical channel structure. However, the taper does not create vertical sidewalls of the steps, which can affect the reliability of the placement of the metal contacts to the wordlines. This can be corrected by increasing the thickness of the dielectric layer or the width of the wordlines depending on the area consumed by the step tread features. Alternatively, angled plasma etch with a Faraday cage can also be used to create the taper.

[0163] As SiSE progresses, the catalytic mesh etches the semiconductor material stack to expose high aspect ratio features with holes and slits for 3D NAND channels and word line isolation. SiSE can be stopped by using an etch stop layer, a timed etch, or by monitoring and controlling electric field parameters. The etchant composition and electron hole generation during processing result in alternating films with different morphologies based on their materials and doping concentrations. After SiSE, one of the layers can be selectively removed or modified (e.g., oxidized) to create the 3D NAND layers. The volume change during oxidation of porous silicon can be suppressed by controlling the porosity and pore density of the porous silicon layer, thereby reducing mechanical stress on the structure. The oxidation rate of the porous layer is much greater than that of single crystal silicon and can be performed at lower temperatures to increase selectivity. For example, at 700°C, the surface and bulk of the porous silicon layer (for individual layers thinner than 1 micron) is oxidized in 3 minutes, while the surface of crystalline silicon is only oxidized 3 nm with dry O2.

[0164] The difference in oxidation rate between the porous silicon layer and the crystalline silicon layer, and the difference in etch rate between the porous oxide and silicon or between the porous silicon and the crystalline silicon must be very high to ensure that there is no undercutting and to increase the number of memory layers that can be made in the SiSE process. Table 3 lists etchants that can be used to selectively remove a layer from the superlattice for various superlattice modifications to obtain a 3D NAND flash array with alternating layers of insulating and conductive films. Surfactants and other such chemicals can be added to the etchant to improve the etch selectivity from layer A to layer B in all applicable crystal orientations. The etchant may be in liquid or vapor form.

[0165] Table 3: List of etchants that can be used to selectively remove a layer from a superlattice.

[0166] [Table 3]

[0167] Table 4 shows examples of various combinations of alternating semiconductor multilayers and processing steps required to ensure selective removal or oxidation of one of the alternating layers to obtain the final metal line and dielectric layers. The donor and acceptor doping of silicon is designated p- and n-Si, with "++" indicating the doping concentration. For example, p++Si has a boron concentration of 1e18 cm -3 This means highly doped silicon that is equal to or greater than 10 ... <100> Step etching can also be performed if the layers grow epitaxially to obtain a crystalline morphology by etching the planes. The main feature of this alternating stack etching is to create a large difference in the etching or oxidation rate between the different layers (layers A and B in a bilayer stack), which can be used to modify the stack and ultimately obtain an insulated / conducting line.

[0168] Table 4: Examples of various combinations of semiconductor alternating multilayers and processing steps required to ensure selective removal or oxidation of one of the alternating layers to obtain the final metal line and dielectric layers.

[0169] [Table 4]

[0170] Various embodiments of the present technology may be used to create 3D NAND VCs without a replacement step, similar to BiCS processing. For example, in some embodiments, a substrate may be provided. Alternating layers of semiconductor material (e.g., doped or undoped Si) may then be deposited. Lithography and taper etching with a crystallographic anisotropic etchant may then be performed. The catalyst may then be patterned. For example, some embodiments may use discontinuous catalyst deposition-Pt, Pd, Ru, CMP / lift-off of the catalyst, or selective electrodeposition of Pt, Pd, or Ru. A SiSE process may then be performed and the catalyst removed using a wet etch (e.g., aqua regia) or isolated with an insulator. Layers may be selectively processed (e.g., oxidizing the porous layer and connecting links) and holes filled with atomic layer deposition (ALD). Lithography may be used to block off areas between wordlines before depositing memory materials such as oxide-nitride-oxide (ONO) with poly-Si core and / or oxide core filler. Material can then be removed from the wordline slits and a low-k dielectric can be deposited in the slits. The tapers can be etched using a plasma etch selective to one set of alternating layers to create steps along the etched tapers.

[0171] In some embodiments, a 3D NAND VC process with oxidation and replacement can be used, similar to the TCAT process. For example, in some embodiments, a substrate can be provided. Alternating layers of semiconductor material (e.g., doped or undoped Si) can then be deposited. Lithography and taper etching with a crystallographic anisotropic etchant can then be performed. The catalyst can then be patterned. For example, some embodiments may use discontinuous catalyst deposition-Pt, Pd, Ru, CMP / lift-off of the catalyst, or selective electrodeposition of Pt, Pd, or Ru. A SiSE process can then be performed and the catalyst removed using a wet etch (e.g., aqua regia) or isolated with an insulator. Layers can be selectively processed (e.g., oxidize the porous layer and connecting links) and holes can be filled with ALD. Lithography can be used to block off areas between wordlines and stabilizing cores (e.g., poly-Si core and oxide core filler) can be deposited.

[0172] Material can be removed from the word line slits. Atomic layer etching is used to remove the thin oxide layer surrounding the porous oxide / crystalline Si structure. The next set of processes to create the 3D NAND flash array may include one replacement step (e.g., selectively etch crystalline Si selective to porous oxide, seal holes with ALD, deposit memory material ONO, deposit W and etch back to isolate word lines, etc.), or two replacement steps (e.g., etch porous oxide selective to crystalline Si, deposit memory material ONO, deposit W and etch back to isolate word lines, etch Si selective to W, deposit SiO2, etc.), or (e.g., etch porous oxide selective to crystalline Si, deposit SiO2 and etch back to isolate, etch crystalline Si selective to deposited SiO2, deposit memory material ONO, deposit W and etch back to isolate word lines, etc.). A low-k dielectric can then be deposited in the slits. The tapers can be etched using a plasma etch selective to a set of alternating layers to create steps along the etched tapers.

[0173] In some embodiments, a displacement 3D NAND VC process can be used, similar to the TCAT process. For example, in some embodiments, a substrate can be provided. Alternating layers of semiconductor materials (e.g., doped or undoped Si, Si / SiGe, Si / Ge, etc.) can then be deposited. Lithography and taper etching can then be performed using a crystallographic anisotropic etchant. The catalyst can then be patterned. For example, some embodiments may use discontinuous catalyst deposition-Pt, Pd, Ru, CMP / catalyst lift-off, or selective electrodeposition of Pt, Pd, or Ru. A SiSE process can then be performed and the catalyst removed using a wet etch (e.g., aqua regia) or isolated with an insulator. The holes can be filled with ALD. Lithography can be used to block the areas between the wordlines, and stabilizing cores (e.g., poly-Si core and oxide core filler) can be deposited. Material can be removed from the wordline slits. The next set of processes to make a 3D NAND flash array may include one replacement step (e.g., etch porous silicon selective to crystalline Si, deposit memory material ONO, deposit W and etch back to isolate word lines, etch Si selective to W, deposit SiO2, etc.), or two replacement steps (e.g., etch porous silicon selective to crystalline Si, oxidize crystalline Si, deposit memory material ONO, deposit W and etch back to isolate word lines, etc.) or (e.g., etch porous silicon selective to crystalline Si, deposit SiO2 and etch back to isolate, etch crystalline Si selective to SiO2, deposit memory material ONO, deposit W and etch back to isolate word lines, etc.). A low-k dielectric can then be deposited in the slits. The tapers can be etched using a plasma etch selective to a set of alternating layers to create steps along the etched tapers.

[0174] In some embodiments, a 3D NAND process with vertical gates can be used. For example, in some embodiments, a substrate can be provided. Alternating layers of semiconductor materials (e.g., doped or undoped Si, Si / SiGe, Si / Ge, etc.) can then be deposited. Lithography and taper etching with a crystallographic anisotropic etchant can then be performed. The catalyst can then be patterned. For example, some embodiments can use discontinuous catalyst deposition-Pt, Pd, Ru, CMP / catalyst lift-off, or selective electrodeposition of Pt, Pd, or Ru. A SiSE process can then be performed and the catalyst can be removed using a wet etch (e.g., aqua regia) or isolated with an insulator. The layers can be selectively processed (e.g., oxidize the porous layers and connecting links). The holes can be filled with ALD. Lithography can be used to block off areas between the layers and ONO memory material can be deposited. Word lines can also be placed perpendicular to the horizontal channel lines. A low-k dielectric can then be deposited in the slits between the word lines. The taper can be etched using a plasma etch selective to one set of alternating layers to create steps along the etched taper.

[0175] In one embodiment, 3D NAND can be fabricated using silicon nanowires as the channel material followed by deposition of alternating layers of conductive and insulating materials. MSP-CICE and novel connecting link or ceiling based collapse mitigation techniques are used to pattern arrays of NWs instead of deep reactive ion etching processes. DRIE uses processes such as the Bosch process, which creates scalloped sidewalls that damage the surface and reduce FET performance. Various embodiments of the CICE process proposed here provide significantly less damage, smoother sidewalls and more refined profile, and therefore superior performance. High aspect ratio vertical NWs created using CICE can be used for vertical 3D NAND flash memory. This involves deposition of memory materials including high-k dielectrics with high trap density for charge storage by conformal ALD on the vertical NWs. A series of conductive materials separated by insulating materials are then deposited to form word lines and create NAND strings resulting in multi-layer ultra-high density 3D NAND flash memory.

[0176] DRAM products are approaching fundamental limits because scaling DRAM capacitors and transistors is very difficult in 2D structures. The current workaround is to use stack or trench capacitors to increase the capacitance per cell without compromising the (substrate) area. However, this approach has limitations in high aspect ratio trench etching for trench capacitors and stability for stack capacitors. Also, reducing the size of features impacts the reliability of planar and recessed channel or fin-based DRAM transistors. Certain DRAM cell configurations also fall short of the ideal 4F 2 Instead of cells, 5-6F 2 As feature sizes decrease from the current 20 nm half pitch to sub-10 nm by 2025, vertical cell access transistors with high aspect ratio capacitors will need to be self-aligned to be incorporated.

[0177] FIG. 24 shows an exemplary DRAM design with transistors, capacitors, and interconnects deposited on nanowires etched by CICE in accordance with one or more embodiments of the present technology. The top of FIG. 24 shows a cross-sectional view of the capacitor area. Bitlines run perpendicular to the page and connect the N+ doped silicon regions on top. Various embodiments may be fabricated using 4F 2 A vertical nanowire-based DRAM architecture is used that incorporates both gate-all-around transistors and self-aligned capacitors to generate cell size factors that allow scaling of DRAM to sub-10 nm half pitch. The vertical sidewall angle in CICE processing is greater than 89.5°, so the center-to-center distance between pillars can be sub-20 nm, sub-15 nm, sub-10 nm, etc. The pillar arrangement can be hexagonal to create smaller DRAM cells. The etched pillars can be aligned perpendicular to the substrate or at an angle based on the CICE etchant concentration. The cross-section of the pillars can be optimized to give the maximum surface area depending on whether they can be fabricated by conventional photolithography and nanoimprint lithography with acceptable defect levels.

[0178] To isolate the nanowires for each DRAM cell, an SOI (silicon-on-insulator) substrate can be used. In this case, the insulator acts as an etch stop for the CICE, isolating the individual nanowires. Alternatively, the base of the nanowires can be made porous using an electric field. Selective oxidation of the porous base can then be performed to electrically isolate the nanowires.

[0179] 25A-25B show two process flows of CICE wet anisotropic etching to create high aspect ratio pillars without collapse, according to one or more embodiments of the present technology. FIG. 25A shows a method of collapse prevention using a ceiling to extend the maximum aspect ratio used. Collapse prevention using a ceiling can be done by etching the feature to a short, stable height using plasma etching or SiSE, depositing a ceiling, and continuing the SiSE process. The "ceiling" can be a height along the length of the short pillar, such as L / 2, where L is the height of the short, stable pillar. This provides additional support as the feature is etched further, and the maximum aspect ratio is larger than the aspect ratio of the ceiling at the top of the short pillar. This provides structural stability to the high aspect ratio pillars and prevents collapse. The ceiling can be deposited by methods such as angled e-beam evaporation, polymer fill, etch back and deposit a ceiling, or spin coating. Materials that can be used for the ceiling include polymers, sputtered / deposited semiconductors, metals and oxides that do not react with the CICE etchants, such as Cr, Cr2O3, carbon, silicon, and Al2O3. In some embodiments, the ceiling can also be made porous by an additional low-resolution lithography step or by a reaction that induces porosity in the ceiling material, for example, the ceiling material can be amorphous or poly-Si that becomes porous in the CICE. Once the substrate is etched and the catalyst is removed, deposition of a memory film or dielectric filler by methods such as atomic layer deposition can be performed before removing the porous ceiling. The ceiling material can also be removed in certain areas or tailored to be non-selective to atomic layer deposition (ALD) to prevent multiple holes from closing and blocking the deposition path. After filling the features, the ceiling is etched or polished. ALD can also be used to close high aspect ratio features after etching to create deep holes (e.g., structural voids, openings, etc. defined by lithographic patterns) without the use of isolated catalyst.

[0180] FIG. 25B shows a link-based method to ensure the stability of etched nanostructures with diamond-shaped cross-sections. When the catalytic mesh comprises both lithographic links and gaps, the linked structures are created by etching. FIG. 26 shows SEM images showing the collapse of unsupported features vs. supported features after CICE on silicon, according to one or more embodiments of the present technology. Electron-beam lithography can write sub-10 nm features but with large overlay, whereas photolithography has good overlay but low resolution, making it very difficult to fabricate sub-30 nm features with smaller link contacts. Photolithography and imprint lithography (whose mask and template are made by electron-beam lithography) may be used to obtain the final linked structure that will later become the nanoimprint template.

[0181] In an alternative embodiment, holes can be etched in the CICE to create trench capacitor DRAM cells. This architecture uses 4F 2The layout can also be designed. The center-to-center distance between holes can be sub-20 nm, sub-15 nm, sub-10 nm, etc., due to the vertical sidewall angle greater than 89.5° in the CICE process. The holes can be arranged in a hexagonal pattern to create smaller DRAM cells. To enhance the diffusion of the etchant in the holes, an electric field can be used to create one or more layers of porosity along the length of the etched holes, except in the top region. The non-porous top region can be used to create silicon transistors for DRAM cells. The porous layer or layers can be selectively oxidized to electrically isolate the trench capacitor. The holes created in the porous layers can be filled using atomic layer deposition of insulating materials such as SiO2, SiN, SiON, etc. after the CICE process. Trench capacitors can be created in high aspect ratio holes by depositing capacitor materials such as electrodes (poly-Si, W, TiN, Co, TaN) and high-k dielectrics (HFO2, ZrO2, Al2O3) to create capacitor configurations such as MOS (metal-oxide-semiconductor), MIM (metal-insulator-metal), or MIMIM.

[0182] (Transistor) The semiconductor industry employs CMOS scaling to improve chip performance, reduce power consumption, and increase functionality, typically by increasing transistor density. This scaling is done by releasing a new technology node every 18 months or 2 years. Transistor density is increased by decreasing transistor dimensions such as gate length, gate oxide thickness, and spacer thickness. With the decrease in feature size, new technologies such as high-k dielectrics, metal gates, strain engineering, and low-k spacer dielectrics have been employed in planar or recessed transistors. However, to improve electrostatic properties despite reducing the area per transistor, 3D scaling in the form of FinFETs was introduced. As dimensions decreased to sub-20 nm, processing to create tall, thin fins with minimal sidewall damage and no collapse was challenging. At the sub-10 nm node, innovative methods have been proposed to improve electrostatic properties using horizontal nanosheets and nanowires.

[0183] However, in all these 3D geometries, structural stability and fabrication challenges combine to limit the potential of the technology. Taller fins and / or more stacked nanosheets and nanowires will improve chip performance and enable scaling to many technology nodes. However, plasma etching for fin fabrication suffers from etch taper and sidewall damage that impacts device performance. CICE can achieve high aspect ratio fins with less sidewall damage with sub-10 nm critical dimensions by eliminating etch taper and reducing the number of fins required per transistor. Large area control and in-line metrology are integrated into the first level wafer-scale fabrication of transistors with optimal cross sections ranging from rectangular fins to circular and shaped NWs. Various embodiments include a novel etch technique, Catalyst Enhanced Chemical Etching (CICE), and lithography requirements to enable the creation of high aspect ratio fins with vertical sidewalls without plasma damage.

[0217] CICE is a combination of Si, Ge, and Si x Ge 1-xIt is a catalyst-based etching method that can be used with semiconductors such as GaN, InP, GaAs, InAs, GaP, InGaS, InGaP, SiC, and multi-layers of semiconductors. An electric field may or may not be used with an etching catalyst. An etchant (e.g., hydrofluoric acid HF), an oxidant (e.g., hydrogen peroxide H2O2), and optionally a low surface tension liquid (e.g., ethanol) or deionized water can etch the semiconductor substrate preferentially at the locations of the catalyst (e.g., Ag, Au, Pd, Pt, Ru, Cu, W, TiN, TaN, RuO2, IrO2, graphene, etc.). Non-aqueous etchants can also be used if desired. Lithographic techniques (e.g., photolithography, e-beam lithography, double patterning, quad patterning, nanoimprint lithography, etc.) can be used to define the catalyst features. The resulting substrate with catalytic mesh is placed in an etchant solution and precisely etched to a certain depth that is actively controlled by the electric field and an optical imaging system that can determine the etch depth based on the electrical and optical properties during etching.

[0184] Thus, the final device is a finFET with high aspect ratio fins with an aspect ratio of more than 5:1, where the fin structure is very vertical with an angle of more than 89.5°. This angle is measured using a scanning electron microscope (SEM), TEM, AFM, etc., followed by image analysis software such as ImageJ. The average taper angle is measured using a nearly conformal straight line using a linear fit algorithm between the difference in feature sizes at the top and bottom of the critical feature. The critical dimension can be the width of the fin or the width of the trench between the fins. Because the vertical sidewall angle is greater than 89.5° in the CICE process, the center-to-center distance between critical features such as fin spacing and fin width can be sub-20 nm, sub-15 nm, sub-10 nm, etc.

[0185] For lateral nanowire and nanosheet FETs, the fin is constructed of alternating layers of material, where one of the layers is selectively removed and a dielectric and gate electrode are conformally deposited to surround the suspended lateral nanowire or nanosheet. The taper of nanosheet and lateral nanowire FETs is measured similarly to finFETs.

[0186] Plasma etching for fin fabrication has various process challenges including precision etching, etch taper, collapse, erosion and structural integrity, and sidewall damage, which impacts the device performance of the transistor. CICE allows for high aspect ratio and low sidewall damage for fins with sub-10 nm critical dimensions. The etch taper angle poses an additional challenge as it limits the maximum fin height for a given fin width. Increasing the fin height requires an increase in the fin width, which reduces the packing density of the transistor.

[0187] Figure 27A shows a 14 nm FinFET with a taper angle of about 85° and a physical half pitch (HP) of 24 nm used in the industry. The maximum fin height achievable with such a taper angle is calculated as Max Fin Height = 0.5 x Half Pitch x tan (Taper Angle). By improving the taper angle, the maximum fin height can be increased for different fin widths and half pitches (HP). This relationship is plotted in Figure 27B, showing the maximum fin height that can be etched for a given HP vs. etch taper angle. This shows the scaling potential of non-tapered etch processes such as CICE. This does not take into account the structural stability of the fins, which will be discussed later. The 100 nm fin height is not part of the active finFET, as this fin height is used for shallow trench isolation (STI).

[0188] High aspect ratio fins are prone to collapse, which can be mitigated by using connecting links that can be altered or removed once the transistor is fabricated and the fin is embedded in a stabilizing material such as an insulator.

[0189] Figure 28 is a plot showing the maximum height of a fin without taper before collapsing laterally along its length (50 nm in this case) without any support / assist features. Figure 28 shows the critical height of a fin unsupported by connecting links versus its half pitch for a length of 50 nm. This is calculated by equating the bending energy of the fin due to collapse to the surface energy required to separate the fin.

[0190]

number

[0191]

number

[0192] where E is the elastic modulus of the fin, I is the moment of inertia about the bending axis, w is the deflection of the fin, i.e., half the distance between the collapsed fins, γ sv is the surface energy of the fin material, and a and b are the dimensions of the fin perpendicular to the collapse direction (length vs. width).

[0193] Collapse occurs along the length of the fin at its shortest height, resulting in the height shown on the graph. Fins can be much longer based on the specific circuit design, but the shortest length of a fin is determined by the contact gate pitch (CGP) of the finFET. The minimum spacer thickness (t s ) is about 5 nm, and the source / drain (S / D) contact length (L c ) is about 15 nm, the contact gate pitch CGP = L G +2t s +L c This is because the transistor scaling is dependent on the gate length L, which varies between 10 and 25 nm. GIt is shown that the dependence of fin width on fin width is shown. The 50 nm case is considered to determine the maximum height of fins with different widths before a fin collapses laterally onto another fin. In some embodiments, a fin pitch of twice the fin width is adopted since the lack of etch taper allows the fin pitch to be reduced.

[0194] The main limitation of scaling to smaller fin widths is the instability of the structure. In FinFETs fabricated in bulk silicon, most of their length is utilized for shallow trench isolation (STI). Given that the minimum height required for STI is 100 nm, only fins with widths of 10 nm or more can be used. Furthermore, the active part of the fin is much shorter than the initial fin height. This can be partially mitigated by using SOI wafers. However, even for SOI finFETs, there is a limit to the maximum height that can be achieved with the fin. Etching taper helps to improve the structural stability of the fin to some extent, but ultimately limits the maximum possible height, as explained in Figure 27.

[0195] (FinFET processing flow) Various embodiments improve the structural stability of the fins by stabilizing the fins during and after etching using connecting links between the fins. After further processing of the device, the stabilization structures are removed or modified. In one embodiment, connecting links can also be used at the circuit design stage to link the sources and drains of adjacent finFETs along with epitaxial S / D contact formation. An example of a finFET process flow is shown in FIG. 29.

[0196] An embodiment of a CICE finFET process flow is shown in Figure 29, where the process steps are a) CICE of the connected fins and then removal of catalyst material, b) STI (shallow trench isolation) fill and etchback, involving atomic layer deposition (ALD) of STI material and etchback of the STI material using steam HF, atomic layer etching (ALE) or reactive ion etching (RIE), c) patterning and deposition of dummy gate and spacers, where polysilicon is used as dummy gate and silicon nitride is used as spacer on either side of the dummy gate, and d) oxide fill using ALD and planarization using chemical mechanical polishing (CMP), cut / etch removal of connection features (or links), where the connection features between fins are etched away using RIE, ALE, selective oxide and steam HF etching, etc., and the lithography mask for etching away the connection features can be designed to retain a certain connection based on the number of fins per transistor and the transistor circuit design. e) oxide fill and etchback; f) source / drain deposition using Si and Ge or epitaxial growth of Si with in situ doping; g) metal gate replacement and high-k dielectric deposition, where the dummy gate is replaced with a high-k dielectric and metal gate between the spacers to form the final high aspect ratio FinFET.

[0197] In other embodiments, catalytic connection links may be used in areas of the fins, and epitaxial growth of silicon may be used to join the missing portions. In areas where connection links have been removed, depending on location and circuit design, materials such as TiN, W, SiO2, SiN, Carbon, Si, Ge, etc. may be deposited based on the required electrical properties of the material, for example, whether the connection needs to be conductive, insulating, or semiconductive.

[0198] High aspect ratio FinFETs fabricated with CICE have connecting links between the fins to prevent collapse. These links must be removed during the fabrication process (step (d) of FIG. 29) to obtain the required fin design. In one embodiment, the finFET links are removed by first patterning and depositing dummy gates and spacers after CICE, followed by deposition of dielectric on all exposed areas. Photolithography is then performed to isolate the areas of fin links that need to be removed. The fin links are removed using atomic layer etching, plasma etching, etc. The plasma etch taper created during the etch does not affect the fin structure that is protected by the dummy gates and spacers. A subsequent S / D epitaxy step may replenish the fin material lost due to the plasma etch taper. Alternatively, selective oxidation and removal of the exposed fin links can be performed, and the oxidized fin links can be removed using vapor HF, plasma etching, wet etching to remove silicon oxide instead of silicon, thereby protecting the silicon fins due to the selective nature of the silicon oxide etch.

[0199] This method has the advantage that the overlay is very accurate, less than 2 nm, which ensures that excess material is not removed from the fins. Using spacer patterning, the width and pitch can be reduced from a photolithography resolution of 35-40 nm line / space to that of 20-25 nm line / space. To create cuts parallel to the fins and perpendicular to the fins, two photolithography steps can be used with the lines / spaces at 90 degrees to each other. EUV lithography can be used to create the same features without further spacer patterning. Based on the finFET design of the logic device, a catalyst pattern is designed to etch the fins and their connecting links. For example, in FIG. 32, the starting CICE catalyst pattern and the pattern after removing the connecting links are shown.

[0200] 30A-30E show an example of FinFET processing after CICE, according to one or more embodiments of the technology. More specifically, FIGS. 30A-30E show top views of connected fin structures, the design of which depends on the application of the finFET, such as SRAM and logic circuits. In FIG. 30A, the CICE etched structures are connected to prevent collapse. FIG. 30B shows dummy gate and spacer patterns designed to connect multiple fins as required by the circuit design. In FIG. 30C, lithography is used to expose the portions to be etched away (connection links). In FIG. 30D, the connection links are then etched away using atomic layer etching or plasma etching. Further finFET processing steps (not shown in FIGS. 30A-30E), such as source / drain epitaxial deposition, gate replacement, etc., can then be performed to obtain the final device circuit. FIG. 30E shows a schematic of the fins under part D remaining after all finFET processing steps.

[0201] Nanosheet FETs are created by etching a fin with alternating layers of semiconductor material and then removing one of the alternating layers, resulting in a suspended nanosheet. Nanosheet FETs have better electrostatics than finFETs due to their gate-all-around configuration, as opposed to the tri-gate structure of finFETs. Similar to the fin height limitations discussed in the previous section, the critical height of the alternating layers of semiconductor in a nanosheet fin limits the number of layers that can be etched using plasma etching. This limitation does not exist in SiSE processing, a subset of CICE that produces nanostructures with alternating layers instead of bulk Si. Nanosheet layer embodiments can be fabricated using Si and Si x Ge 1-x where the new critical height depends on the modified elastic modulus of the multi-layer stacked fin. Considering that each nanosheet is 5 nm thick and that the lower area of ​​the fin covered with STI is Si, the effective elastic modulus can be calculated with a "slab" model using the inverse law of composite mixtures:

[0202]

number

[0203] where E is the elastic modulus, V is the volume fraction, and the subscript f is, for example, Si x Ge 1-x or porous Si, and m is the remaining nanosheet material, e.g., Si.

[0204] For Si volume fractions of about 75% to 95%, the resulting effective elastic modulus is about 100 to 150 GPa, and the critical height of the nanosheet fin is similar to that of a finFET fin. The change in surface energy depends on the material of the surface on top of the fin it is contacting. In one embodiment, that material is silicon, and the effect of the nanosheet material is the same as that of a silicon finFET.

[0205] Alternatively, lateral nanowire FETs can be created in a similar manner by reducing the width of the fins. In SiSE processing, connected fins formed in finFETs using lithographic links can also be used on stacks of alternating layers of semiconductors.

[0206] Nanosheet FETs are similar to finFETs, with fins made of alternating layers of material instead of bulk silicon. One embodiment is a nanosheet FET with fins made of alternating layers of material instead of bulk silicon. x Ge 1-x The Si x Ge 1-x Layers are removed to give silicon nanosheets. Another embodiment consists of alternating layers of differently doped Si, which produces a sacrificial porous Si layer and a crystalline Si nanosheet. In a further embodiment, the silicon nanosheets are formed by depositing low doped Si / Si x Ge 1-x / Highly doped Si / Si x Ge 1-xAlternating stacks of low doped Si / Ge / high doped Si / Ge ensure that the sacrificial nanosheet etch is not affected, such as by using alternating stacks of low doped Si / Ge / high doped Si / Ge, where the highly doped Si is converted to porous Si and the low doped Si remains crystalline. The SiSE process is tailored to ensure that the morphology changes from porous to non-porous at a specific doping concentration, creating a multi-layer stack of porous and non-porous Si. The porous Si can be selectively removed to obtain suspended nanosheets of Si. The etchant composition and hole generation during the process result in alternating films with different morphologies based on their material and doping concentration. In another embodiment, the SiSE process is used with a time-varying electric field on bulk Si to create nanosheet fins with alternating layers of porous and non-porous Si. A typical process flow is described in FIG. 31. FIG. 31 shows an example of a process flow for making nanosheet FETs and lateral nanowire FETs with SiSE according to one or more embodiments of the present technology. The steps are a) removal of SiSE and catalyst material of connected fins, b) dielectric fill to create STI (shallow trench isolation) using atomic layer deposition (ALD), c) cut / etch away connection features, where the connection features between fins are etched away using RIE or ALE, and the lithography mask for etching away the connection features can be designed to retain certain connections based on the number of fins per transistor and the transistor circuit design, d) deposition of stress liner such as silicon nitride in the cut out areas using ALD, e) dielectric (STI) etchback and selective removal of alternating layers to obtain suspended nanosheets / nanowires, and f) patterning and deposition of dummy gates and spacers, where polysilicon is used as the dummy gates and silicon nitride is used as spacers on either side of the dummy gates. Spacers can be deposited around the dummy gate, excess spacer material can be patterned / etched, and oxide fill and planarization can be performed. g) S / D deposition where source and drain regions are deposited using Si and Ge or epitaxial growth of Si with in situ doping; and h) metal gate replacement and high-k dielectric deposition.

[0207] In another embodiment of the SiSE of the nanosheet FET, alternating layers of porous and non-porous Si can be created by using a time-varying electric field in conjunction with catalytic etching to create alternating layers of porous and non-porous Si by using bulk Si as the starting substrate instead of alternating epitaxial layers of material.

[0208] The selective removal of alternating layers of nanosheets is accomplished using selective etching processes. For example, Si / Si x Ge 1-x In the stack, HCl was used to x Ge 1-xFor Si / porous Si stacks, etchants such as HF, TMAH, vapor HF, HF, and weak oxidizers such as hydrogen peroxide can be used. x Ge 1-x / Highly doped (porous after CICE) Si / Si x Ge 1-x For stacks of multiple alternating materials such as those described above, HF is used to remove the porous Si, and then HCl is used to remove the Si. x Ge 1-x can be removed.

[0209] The catalyst is designed to prevent collapse such that all fins are connected using lithographic links. To further prevent catalyst wobble when SiSE and / or electric fields cannot be used to suppress wobble, a connecting link is created with the lithographic links that connects all catalyst regions while ensuring that all fins are connected to prevent collapse.

[0210] The critical height of the fin before collapse can be increased by using connecting links at the end of the fin near the S / D region. These links can be removed after stabilizing the fin with gate, spacer and dielectric. Figure 32 plots the critical height before lateral collapse for different number of fins along the length and width of the fin structure. For a 50 nm contact gate pitch (CGP), 10 nm wide connecting links are used on both sides of the fin to improve stability. As shown in Figure 32, the maximum height of the fin when all fins are interconnected in a square mesh can be simulated as a thin and long plate with three fixed faces.

[0211] FIG. 32A is a diagram of a connection link when the number of fins is greater than 1. For N=1, the length b is equal to the CGP of the finFET, but for N>1, the length b=CGP+2 *(link width). In FIG. 32B, the critical height before collapse along the length of the connected fin structure is shown for different fin widths, f, and numbers of fins ranging from 1 to 10. In FIG. 32C, the critical height before collapse along the width of the connected fin structure is shown for different fin widths, f, and numbers of fins ranging from 1 to 10. To prevent catalyst wobble in larger blocks of connected fins, a linked mesh can be used as shown below for a block of 6×4 fins. Multiple blocks can be completely separate or connected via semiconducting links. FIG. 32D is a plot showing the critical height before collapse along the width of the connected fin structure for different fin widths, f, and numbers of fins ranging from 1 to 10.

[0212] One of the key steps to create devices from connected fins etched using CICE is the dielectric etchback to create shallow trench isolation (STI) regions at the base of the fin. This step is required for all embodiments of this process except for SOI (silicon on insulator) wafers. A dielectric such as SiOx can be deposited on high aspect ratio fins with widths less than 15 nm using conformal deposition methods such as atomic layer deposition. A timed etchback of the dielectric creates an STI of about 100 nm thickness at the base of the fin, ideally leaving the fin itself unaffected. Typically, plasma etching is used for this process. However, the physics of the plasma etching process can damage the fin. Using vapor HF for a purely chemical process allows the dielectric to be etched back without damaging the fin. In one embodiment, a separate material (such as silicon nitride) can be deposited around the fin using ALD prior to the oxide dielectric deposition. This creates an etch stop on the fin to prevent damage during the selective chemical etch.

[0213] The uniformity of such an etch-back process from the center to the edge of the wafer needs to be controlled. This can be done using multiple temperature zones in the vapor HF setup. Using a "pioneer" wafer, a timed etch can be optimized and various regions with discontinuities in etch rate and depth can be mapped. The discontinuities can be smoothed out by creating local hot and cold zones to modify the local etch rate and create a uniform etch depth.

[0214] Alternatively, the silicon-containing polymer can be precisely dispensed using inkjet at locations with high etch rates, such as the edge of the wafer. The amount dispensed can be determined using data from a previous wafer. The substrate is then baked at an optimized temperature to intentionally create a non-uniform height of material on the substrate. This cancels the non-uniform etching caused by the vapor HF, thereby ensuring that the final etch uniformity for creating the STI in the fins is within specification.

[0215] In other embodiments, the bulk Si fin of the finFET and the nanosheet fin of the nanosheet FET can be electrically isolated from each other by creating a porous bottom layer during the SiSE process using electric fields, etchant concentrations, and / or doping concentrations of the layer being etched such that the layer becomes porous after etching. The porous bottom layer can be 100 nm thick. The porous layer is then selectively oxidized to create oxidized porous Si at the bottom of the fin. The oxidized porous Si then acts as a shallow trench isolation (STI) and electrically isolates the fin. In the case of the nanosheet FET, the alternating porous layers can also be oxidized when the porous bottom layer is oxidized.

[0216] Various embodiments of the present technology provide techniques for fabricating FinFETs. For example, in some embodiments, the catalyst can be patterned using lithography, depositing a discontinuous catalyst such as Pt, Pd, Ru, Au, etc., and performing chemical mechanical polishing or lift-off. Alternatively, selective electrodeposition of the catalyst can be performed after lithography. After SiSE processing, the catalyst material can be removed using a wet etch (e.g., aqua regia) or isolated from the device layers using an insulator. To create an STI layer, an insulator can be deposited and planarized. Lithography and etching of the excess fin connection structure can then be performed. Lithography and deposition of a stress liner material can then be performed. If necessary, an etch-back can be performed to obtain shallow trench isolation (STI) using methods such as timed vapor HF etching. For nanosheet transistors, the alternating layers are selectively removed to obtain suspended nanosheets. For example, some embodiments use a Si-to-Si selective etch-to-Si ... x Ge 1-x , and / or etch the porous Si selective to Si. The dummy gate can then be patterned. For example, in some embodiments, lithography of the dummy gate pattern may be performed and dummy gate material (oxide, poly-Si) may be deposited. Spacers can be deposited around the dummy gate and excess spacer material patterned / etched. Oxide fill and etchback may be performed. In some embodiments, lithography can be used to expose the S / D areas. S / D deposition (e.g., doped epi growth) may then be performed. The poly-Si dummy gate can be etched away and replaced with a high-k dielectric and metal gate. An insulator such as silicon oxide can then be deposited and planarized to complete the fabrication of the transistor layer. Further processing can then be performed to create metal layer contacts, thereby creating a working transistor device, and oxide fill and planarization of the metal layer can be completed.

[0217] (Conclusion) Unless the context clearly requires otherwise, throughout the description and claims, words such as "comprises," "comprising," and the like are to be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, "including but not limited to." As used herein, the words "connected," "coupled," or variations thereof, refer to a direct or indirect connection or coupling between two or more elements. The coupling or coupling between the elements may be physical, logical, or a combination thereof. Furthermore, the words "herein," "on," "below," and similar words, when used herein, refer to the specification as a whole and not to any particular portion of the specification. Where the context permits, words using the singular or plural in the above detailed description may also include the plural or singular, respectively. The word "or," in connection with a list of two or more items, encompasses all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0218] The above detailed description of examples of the present technology is not intended to be exhaustive or to limit the present technology to the precise form disclosed above. Although specific examples of the present technology are described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of the present technology. For example, while processes or blocks are presented in a given order, alternative implementations may perform routines including steps or use systems including blocks in different orders, and some processes or blocks may be deleted, moved, added, sub-divided, combined, and / or modified to provide alternatives or sub-combinations. Each of these processes or blocks may be implemented in a variety of ways. Also, while processes or blocks are at times shown as being implemented in sequence, these processes or blocks may instead be implemented or performed simultaneously, or may be implemented at different times. Furthermore, specific numerical values ​​described herein are merely examples, and alternative implementations may employ different values ​​or ranges.

[0219] The teachings of the technology provided herein may be applied to other systems, not necessarily those described above. Elements and operations of the various examples described above may be combined to provide further implementations of the technology. Some alternative implementations of the technology may include fewer elements as well as additional elements relative to the implementations described above.

[0220] These and other changes can be made to the technology in light of the detailed description above. The above description describes certain examples of the technology and describes the best mode contemplated, but no matter how detailed the above may appear in text, the technology can be practiced in many ways. Details of the system may vary considerably in a particular implementation while being encompassed in the technology disclosed herein. As described above, a specific term used in describing a certain characteristic or aspect of the technology should not be interpreted as suggesting that the term is redefined herein to be limited to a specific feature, characteristic, or aspect of the technology to which the term relates. In general, unless such language is expressly defined in the detailed description section above, the language used in the claims should not be interpreted as limiting the technology to the specific examples disclosed in the specification. Thus, the actual scope of the technology encompasses not only the disclosed examples but also all equivalent ways of practicing or implementing the technology based on the claims.

[0221] In order to reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but the applicant contemplates various aspects of the technology in any number of claim forms. For example, while only one aspect of the technology is recited as a computer-readable medium claim, other aspects may be embodied as a computer-readable medium claim as well, or in other forms, such as being embodied in a means-plus-function claim. Although claims intended to be treated under 35 U.S.C. § 112(f) begin with the phrase "means for," the use of the word "for" in other contexts is not intended for treatment under the provisions of 35 U.S.C. § 112(f). Accordingly, the applicant reserves the right to pursue additional claim forms after filing this application in order to pursue such additional claim forms in either the present application or any continuing application.

Claims

1. 1. A method for improving reliability of a catalytically promoted chemical etch, comprising: patterning a catalytic layer on a surface of a semiconductor material, wherein the catalytic layer includes a plurality of features and a plurality of lithographic links substantially connecting one or more isolated features of the plurality of features; exposing the patterned catalytic layer on the surface of the semiconductor material to an etchant, where the patterned catalytic layer causes etching of the semiconductor material to form a plurality of shaping structures corresponding to the plurality of features. A method comprising:

2. The method of claim 1, characterized in that the multiple lithography links prevent wobble.

3. 2. The method of claim 1, wherein the semiconductor material is one of a single crystal bulk silicon wafer, a polysilicon layer deposited on a substrate, an amorphous silicon layer deposited on a substrate, a silicon on insulator (SOI) wafer, and an epitaxial silicon layer grown on a substrate.

4. 10. The method of claim 1, wherein a time-varying electric field is used to fabricate multiple alternating layers of etched nanostructures, where at least one of the multiple alternating layers is porous.

5. The method of claim 1, wherein the plurality of lithography links are adapted to prevent collapse.

6. The forming structure includes gaps filled with material using a deposition process; The material includes one of SiO2, SiN, Si, W, TiN, and carbon.

2. The method of claim 1 .

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