Non-volatile memory device and method for manufacturing the same

Abstract

To provide a nonvolatile memory device capable of erasing stored data more efficiently and a method for manufacturing the same.SOLUTION: A nonvolatile memory device includes at least one memory cell, and the memory cell includes a substrate, a selection gate, a control gate, a floating gate, and an erase gate. The selection gate is disposed on the substrate and the control gate is disposed on the substrate, spaced apart from the selection gate in a lateral direction. The control gate includes a non-perpendicular surface. The floating gate includes a vertical portion and a horizontal portion. The vertical portion is disposed between the selection gate and the control gate and includes a first upper tip spaced apart in a lateral direction from the control gate. The horizontal part is disposed between the substrate and the control gate, and the horizontal part includes a side tip spaced apart from the control gate in the lateral and vertical directions. The erase gate covers the non-perpendicular surface of the control gate and the vertical and / or horizontal tips of the floating gate.SELECTED DRAWING: Figure 3

Description

Detailed Description of the Invention

[0001] (Background technology) (1. Technical Field) The present invention relates to a semiconductor device, and more particularly to a non-volatile memory device and a method for manufacturing the same.

[0002] 2. Description of the Prior Art Non-volatile memories are widely used in personal computers and electronic devices because, for example, they can repeatedly perform operations such as storing, reading, and erasing data, and the stored data is not lost after the non-volatile memory is shut down.

[0003] A conventional non-volatile memory has a stack gate structure including a tunnel oxide layer, a floating gate, a coupling dielectric layer, and a control gate in that order. When performing a program or erase operation on such a flash memory device, appropriate voltages are applied to the source region, drain region, and control gate, respectively, to inject or extract electrons from the floating gate.

[0004] In the program and erase operations of non-volatile memory, a larger gate coupling ratio (GCR) between the floating gate and the control gate generally means that a lower operating voltage is required for operation, thereby significantly increasing the operating speed and efficiency of the flash memory. However, during the program or erase operation, electrons must be injected into or extracted from the floating gate through a tunnel oxide layer disposed under the floating gate, which often damages the structure of the tunnel oxide layer and thus reduces the reliability of the memory device.

[0005] In order to improve the reliability of the memory device, an erase gate is employed and incorporated in the memory device, and electrons can be extracted from the floating gate by applying a positive voltage to the erase gate. In this way, electrons in the floating gate are extracted through the tunneling oxide layer disposed above the floating gate rather than through the tunneling oxide layer disposed below the floating gate, thus further improving the reliability of the memory device.

[0006] As the demand for highly efficient memory devices that can more efficiently erase stored data increases, a need remains to provide improved memory devices and methods of manufacturing the same.

[0007] (Prior art document) (Patent Document 1) U.S. Patent Publication of application No. 2021-0408119 A1 specification (Patent Document 2) U.S. Patent Application Publication No. 2014 / 0042383 A1 (Patent Document 3) U.S. Patent Application Publication No. 2012 / 0295413 A1 (Patent Document 4) U.S. Patent Application Publication No. 2013 / 0112935 A1 (Patent Document 5) Russian Patent Publication No. 2 297 625 C1 (Patent Document 6) U.S. Patent Application Publication No. 2016 / 0336415 A1 (Patent Document 7) U.S. Patent Application Publication No. 2016 / 0365350 A1 (Patent Document 8) U.S. Patent Application Publication No. 2013 / 0026552 A1 (Patent Document 9) U.S. Patent Application Publication No. 2016 / 0358928 A1 (Patent Document 10) Taiwan Patent Publication No. 202114174 Specification A (Patent Document 11) Taiwan Patent Publication No. 201644037 Specification A (Patent Document 12) Taiwan Patent Publication No. 201633319 Specification A (Patent Document 13) Taiwan Patent Publication No. 201839770 Specification A (Patent Document 14) U.S. Patent Application Publication No. 2013 / 0313626 A1 (Patent Document 15) U.S. Patent Application Publication No. 2021 / 0384205 A1 Specification (Patent Document 16) U.S. Patent Application Publication No. 2017 / 0040334 A1 (Patent Document 17) U.S. Patent Application Publication No. 2004 / 0041202 A1 (Patent Document 18) U.S. Patent Application Publication No. 2006 / 0205136 A1 (Patent Document 19) U.S. Patent Application Publication No. 2011 / 0281427 A1 (Patent Document 20) U.S. Patent Application Publication No. 2005 / 0269624 A1 (Patent Document 21) U.S. Patent Application Publication No. 2003 / 0162347 A1 (Patent Document 22) Russian Patent Publication No. 2 216 821 C2

[0008] (Summary of the invention) The present invention provides a non-volatile memory device and a method for manufacturing the non-volatile memory device, which is capable of erasing stored data more efficiently.

[0009] According to one embodiment of the present disclosure, a non-volatile memory device includes at least one memory cell, the memory cell including a substrate, a select gate, a control gate, a floating gate, and an erase gate. The select gate is disposed on the substrate, and the control gate is disposed on the substrate laterally spaced apart from the select gate. The control gate includes a non-vertical surface. The floating gate includes a vertical portion and a horizontal portion. The vertical portion includes a first top tip disposed between the select gate and the control gate and laterally spaced apart from the control gate. The horizontal portion is disposed between the substrate and the control gate, and includes a side tip laterally and vertically spaced apart from the control gate. The erase gate covers the non-vertical surface of the control gate and the tips of the vertical portion and / or the horizontal portion of the floating gate.

[0010] According to one embodiment of the present disclosure, a method for manufacturing a non-volatile memory device is provided, the method including: providing a substrate; forming a select gate in the substrate; forming a coincident conductive layer on the substrate and the select gate; forming a control gate covering the select gate and sidewalls of the substrate; the control gate includes a non-vertical surface; forming the control gate; etching the coincident conductive layer exposed from the control gate; the floating gate includes a vertical portion disposed between the select gate and the control gate and a horizontal portion disposed between the substrate and the control gate, both the vertical portion and the horizontal portion including tips; and forming an erase gate covering not only the non-vertical surface of the control gate but also the top and side tips of the vertical and horizontal portions of the L-shaped floating gate.

[0011] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0012] BRIEF DESCRIPTION OF THE DRAWINGS The drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0013] FIG. 1 is a schematic top view of a non-volatile memory device according to one embodiment of the present disclosure.

[0014] FIG. 2 is a schematic cross-sectional view of a non-volatile memory device corresponding to lines AA', BB', and CC' in FIG. 1, according to one embodiment of the present disclosure.

[0015] FIG. 3 is a schematic cross-sectional view of various non-volatile memory devices corresponding to line AA′ of FIG. 1, according to one embodiment of the present disclosure.

[0016] FIG. 4 is a schematic cross-sectional view of various non-volatile memory devices according to another embodiment of the present disclosure, corresponding to line AA′ of FIG.

[0017] 5 to 11 are schematic cross-sectional views of the nonvolatile memory device of FIGS. 1 and 4 at various stages in a method for manufacturing the nonvolatile memory device of the present invention according to an embodiment of the present invention.

[0018] (Detailed Description) The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. In the following, specific examples of components and configurations are described to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature in the following description can include an embodiment in which the first and second features are formed in direct contact, and can also include an embodiment in which an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure can repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, spatially relative terms such as "below," "below," "lower," "under," "up," "over," "upper," "further," "bottom," "top," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as "below" and / or "under" other elements or features will be oriented "above" and / or "over" the other elements or features. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0020] Although the present disclosure is described with respect to specific embodiments, the principles of the present disclosure as defined by the claims appended hereto can obviously be applied beyond the specifically described embodiments of the present disclosure described herein. Moreover, in the description of the present disclosure, some details have been left out so as not to obscure the inventive aspects of the present disclosure. The omitted details are within the knowledge of those skilled in the art.

[0021] 1 is a schematic top view of a non-volatile memory device according to an embodiment of the present disclosure. Referring to FIG. 1, the non-volatile memory device 100_1 may be a NOR flash memory device including at least one memory cell, such as four memory cells housed in first, second, third, and fourth memory cell regions, 110, 112, 114, 116, respectively. The structures of the first memory cell region 110 and the second memory cell region 112 are mirror images of each other, and the structures of the third memory cell region 114 and the fourth memory cell region 116 are mirror images of each other. According to an embodiment of the present disclosure, the non-volatile memory device 100_1 includes four or more memory cells, which may be arranged in an array having a number of rows and columns.

[0022] 1, the non-volatile memory device includes a substrate 200 and an isolation structure 102. The substrate 200 can be a semiconductor substrate, such as, but not limited to, a silicon substrate or a silicon-on-insulator (SOI) substrate. The isolation structure 102 can be made of an insulating material and is used to define an active area 103 of a memory cell.

[0023] Each of the memory cells includes a source region 222 and a drain region 244 disposed within an active region 103 defined by an isolation structure 102. The source region 222 and the drain region 244 can be doped regions of the same conductivity type, such as n-type or p-type. The conductivity type of the source region 222 and the drain region 244 is different from the conductivity type of the substrate 200 or different from the conductivity type of a doped well (not shown) used to contain the source region 222 and the drain region 244. The source region 222 is disposed at one end of the active region 103, and the drain region 244 is disposed at the other end of the active region 103. According to some embodiments of the present disclosure, the source region 222 is a continuous region that extends along the Y direction and is shared by memory cells of the same column.

[0024] Each memory cell may further include a select gate 206 disposed on the substrate 200 and adjacent to the drain region 244. The select gate 204 may extend along the Y direction and may be shared by memory cells located in the same column. The select gate 204 may be made of a conductive material such as polysilicon or metal, and the select gate 204 may act as a word line configured to turn on / off the channel regions of the memory cells disposed under the word line. Thus, the channel regions of the memory cells in the same column may be turned on or off simultaneously.

[0025] To insulate the select gate 204 from other conductive components, dielectric spacers 212 may be disposed on the sidewalls of the select gate 204. The dielectric spacers 212 may be, but are not limited to, single-layer, double-layer, or multi-layer spacers disposed on each sidewall of the select gate 204.

[0026] Each memory cell also includes a floating gate 224 disposed on the substrate 200 and adjacent to the source region 222. Thus, the floating gate 224 is disposed on one side of the select gate 204, and the drain region 244 is disposed on the other side of the select gate 204. The floating gates 224 are made of a conductive material, such as polysilicon or other semiconductors. The floating gates 224 are spaced apart from one another such that charges stored in the floating gates 224 are not directly transferred between adjacent floating gates 224. Because the floating gates 224 are spaced apart from one another, each of the floating gates 224 can be independently programmed or erased, thereby determining the state of each memory cell, such as state "1" or state "0". As shown in the cross-sectional view of FIG. 2, each floating gate 224 is an L-shaped floating gate having a vertical portion and a horizontal portion. The detailed structure of the floating gates 224 is described in the description corresponding to FIG. 2.

[0027] Each memory cell also includes a control gate 240 disposed on the substrate 200 and adjacent to the source region 222. The control gate 240 extends along the Y direction and may be shared by memory cells located in the same column. Thus, the floating gate 224 may be covered by the control gate 240 in the same column. Also, the floating gate 224 is an L-shaped floating gate having a vertical portion and a horizontal portion, and only the horizontal portion of the floating gate 224 is covered by the control gate 240, and the vertical portion of the floating gate 224 is not covered by the control gate 240. The control gate 240 may be made of a conductive material such as polysilicon or metal, and the control gate 240 is configured to create hot carriers (e.g., electrons) that are injected from the channel into the floating gate 224.

[0028] The non-volatile memory device 100 further includes an erase gate 236 extending along the Y direction. Moreover, the erase gate 236 may be a continuous layer extending from the first memory cell region 110 to the second memory cell region 112, filling a gap at the boundary between the first memory cell region 110 and the second memory cell region 112 (such as a gap between two adjacent floating gates 224 in the same row). Thus, the erase gate 236 may cover at least two floating gates 224 and two control gates 240 in the first memory cell region 110 and the second memory cell region 112. In an erase operation of the non-volatile memory 100, the erase gate 236 is biased, and the electrons stored in the floating gate 224 are mainly drawn out through the tip (referred to as a corner) of the horizontal portion (not shown) of the floating gate 224.

[0029] FIG. 2 is a schematic cross-sectional view of a non-volatile memory device corresponding to lines AA′, BB′, and CC′ in FIG. 1 according to an embodiment of the present disclosure. Referring to view AA′ in FIG. 2, the floating gate 224 is an L-shaped floating gate having a vertical portion 224_1, a horizontal portion 224_2, and a corner portion (not shown). The corner portion is a lower corner of the floating gate and is connected to both the vertical portion 224_1 and the horizontal portion 224_2. The vertical portion 224_1 of the floating gate 224 is disposed between the select gate 204 and the control gate 240, the horizontal portion 224_2 of the horizontal portion 224_2 is disposed between the substrate 200 and the control gate 240, and the horizontal portion 224_1 of the floating gate 224 includes a side tip 226a spaced apart from the control gate 240 in a side direction (e.g., X-direction). The top end of the vertical portion 224_1 of the floating gate 224 is higher than the top end of the select gate 204. In addition, the vertical portion 224_1 of the floating gate 224 further includes two first upper tips 228a and two first side walls. The first upper tips 228a face each other and are arranged along a first direction, for example, the X direction. The first side walls face each other and are arranged along a first direction, for example, the X direction, and the first side walls 230 are respectively connected to the first upper tips 228a of the vertical portion 224_1 of the floating gate 224.

[0030] 2, the control gate 240 includes a non-vertical surface 246, such as a sloped or curved surface. The non-vertical surface 246 may be a convex surface. The bottom surface of the control gate 240 is lower than the top surface of the vertical portion 224_1 of the floating gate 224.

[0031] 2, view AA', the erase gate 236 is a continuous layer that extends from the first memory cell region 110 to the second memory cell region 112. The erase gate 236 covers the non-vertical surface 246 of the control gate 240, the side tips 226a of the horizontal portion 224_2 of the floating gate 224, and the top surface of the vertical portion 224_1 of the floating gate 224. The erase gate 236 partially covers the non-vertical surface 246 of the control gate 240, and therefore a portion of the bottom surface of the erase gate 236 is a curved surface.

[0032] In the erase operation, the electrons stored in the floating gate 224 can be extracted not only from the first upper end 228a of the vertical portion 224_1 but also from the side end 226a of the horizontal portion 224_2, so that the electrons stored in the floating gate 224 can be more effectively discharged.

[0033] 2, the non-volatile memory device 100 further includes a coupling dielectric layer 238 disposed between the control gate 240 and the floating gate 224. The coupling dielectric layer 238 is an L-shaped coupling dielectric layer, and the coupling dielectric layer 238 is a composite dielectric layer including, but not limited to, silicon oxide / silicon nitride / silicon oxide.

[0034] 2, the non-volatile memory device 100 further includes an erase gate dielectric layer 234 disposed between the erase gate 236 and the floating gate 224, and between the erase gate 236 and the control gate 240. The erase gate dielectric layer 234 may be made of a dielectric layer that allows electrons initially stored in the floating gate 224 to pass through the erase gate dielectric layer 234 by a Fowler-Nordheim (FN) tunneling mechanism.

[0035] 2, the floating gate dielectric layer 218 is disposed between at least the substrate 200 and the floating gate 224. The material of the floating gate dielectric layer 218 is, for example, silicon oxide or other layers. During a programming operation, hot electrons can pass through the floating gate dielectric layer 218 and accumulate in the floating gate 224.

[0036] 2, the control gate 240 and the erase gate 236 may be disposed in the isolation structure 102. Thus, the control gate 240 may be disposed between the erase gate 236 and the isolation structure 102. Also, the isolation structure 102 shown in FIG. BB' is not covered by the floating gate 224.

[0037] 2, the vertical portion 224_1 of the floating gate 224 further includes a second upper tip 228b and a second sidewall 230 facing each other and disposed along a second direction, e.g., the Y direction, different from the first direction. The erase gate 236 extends along the second direction and covers the second upper tip 228b and the second sidewall 230 of the vertical portion 224_1 of the floating gate 224. Also, a lower portion of the second sidewall 230 can be covered by a bonding dielectric layer 238, and an upper portion of the second sidewall 230 can be covered by an erase gate dielectric layer 234. Due to the presence of the control gate 240, the bottom surface of the erase gate 236 extending beyond the second sidewall 230 of the floating gate 224 is spaced apart from the isolation structure 102.

[0038] Figure 3 is a schematic cross-sectional view of a non-volatile memory device corresponding to line AA' in Figure 1 according to an embodiment of the present invention. The structure shown in Figure 3 can be considered as an enlarged cross-sectional view of the structure shown in view AA' in Figure 2. Referring to Figure 3, the floating gate 224 is L-shaped, including a vertical portion 224_1, a horizontal portion 224_2, and a corner portion 224_3.

[0039] The top surface 225_1 of the vertical portion 224_1 includes a concave surface that makes the first upper tip 228a of the vertical portion 224_1 sharper, so that electrons initially stored in the floating gate 224 can be more effectively extracted from the first upper tip 228a of the vertical portion 224_1 of the floating gate 224.

[0040] The horizontal portion 224_2 includes a protruding portion 232 exposed from the control gate 240. An upper corner of the protruding portion 232 corresponds to a side tip 226a spaced laterally and vertically from the control gate 240. The side tip 226a of the floating gate 224 can be covered with a thin layer of a bonding dielectric layer 238. For example, the thickness of the bonding dielectric layer 238 covering the side tip 226a of the floating gate 224 can be about 5 angstroms to 30 angstroms, but is not limited thereto. In order to more efficiently erase the charge accumulated in the floating gate 224, the side tip 226a may not be covered by any bonding dielectric layer 238. Thus, the side tip 226a is in direct contact with the erase gate dielectric layer 234.

[0041] Corner 224_3 is the lower corner of the floating gate 224 and is laterally spaced from the control gate 240.

[0042] The coupling dielectric layer 238 is also L-shaped and includes a vertical portion 238_1 and a horizontal portion 238_2. The vertical portion 238_1 of the coupling dielectric layer 238 is disposed between the control gate 240 and the vertical portion 224_1 of the floating gate 224. The vertical portion 238_1 of the coupling dielectric layer 238 includes a top surface 239_1 having a curved contour. The horizontal portion 238_2 is disposed between the control gate 240 and the horizontal portion 224_2 of the floating gate 224, and an end 242 of the horizontal portion 238_2 of the coupling dielectric layer 238 extends from under the control gate 240 and is exposed from the control gate 240. The end 242 of the horizontal portion 238_2 of the coupling dielectric layer 238 includes a non-vertical sidewall 239_2 exposed from the control gate 240. The non-vertical sidewall 239_2 is a concave surface that directly contacts the erase gate dielectric layer 234.

[0043] The erase gate 236 fills the gap at the boundary between the first memory cell region 110 and the second memory cell region 112. Because the non-vertical sidewall 239_2 of the end 242 of the bonding dielectric layer 238 has a concave surface, a portion of the erase gate 236 can have a corresponding protrusion 250 extending toward the non-vertical sidewall 239_2 of the end 242 of the bonding dielectric layer 238. The protrusion 250 can cover the side tip 226a of the horizontal portion 224_2 of the floating gate 224, so that the erase gate 236 partially wraps around the side tip 226a of the floating gate 224. This allows electrons initially stored in the floating gate 224 to be more effectively extracted from the side tip 226a of the horizontal portion 224_2.

[0044] A dielectric spacer 212 is disposed between the select gate 204 and the vertical portion 224_1 of the floating gate 224, the dielectric spacer 212 including a curved upper surface 213 that is lower than an upper surface 225_1 of the vertical portion 224_1 of the floating gate 224.

[0045] 4 is a schematic cross-sectional view of a non-volatile memory device according to another embodiment of the present invention. The volatile memory devices 210, 220, 230 are similar to the volatile memory device 100 shown in FIG. 3, with the main difference being the configuration of the erase gate.

[0046] In the non-volatile memory device 210, the non-volatile memory device 210 includes a first erase gate 256a and a second erase gate 256b extending along the Y direction and separated from each other. The first erase gate 256a covers the side end 226a of the horizontal portion 224_2 of the floating gate 224, and the second erase gate 256b covers the top surface of the vertical portion 224_1 of the floating gate 224. During an erase operation, the first erase gate 256a is configured to be biased with a first voltage, and the second erase gate 256b is configured to be biased with a second voltage different from the first voltage. Thus, the values ​​of the first voltage and the second voltage can be individually adjusted to more effectively discharge the electrons stored in the floating gate 224.

[0047] Regarding the volatile memory device 220, the volatile memory device 220 is similar to the volatile memory device 210, but the second erase gate 256b is omitted so that the top surface of the vertical portion 224_1 of the floating gate 224 is not covered by another erase gate.

[0048] Regarding the volatile memory device 230, the volatile memory device 230 is similar to the volatile memory device 220, except that the first erase gate 256a includes a flat upper surface, and the height of the first erase gate 256a is up to 20% higher than the height of the select gate 204. Since the height of the first erase gate 256a is not much higher than the height of the select gate 204, the non-volatile memory device 230 can be easily integrated with other semiconductor devices, such as MOSFETs, in a digital circuit. This allows the non-volatile memory device 230 and the semiconductor devices in the digital circuit to be manufactured simultaneously without significant adjustments to the manufacturing process of the semiconductor devices.

[0049] 5 to 11 are cross-sectional views at various stages of a method for manufacturing the nonvolatile memory device of FIGS. 1 to 3 according to one embodiment of the present invention. In FIGS. 5 to 11, AA' corresponds to line AA' in FIG.

[0050] Referring to FIG. 5, the structure formed at this stage of fabrication includes at least one substrate 200 , at least one stacked structure 300 , dielectric spacers 212 and a floating gate dielectric layer 218 .

[0051] According to one embodiment of the present disclosure, the substrate 200 may be a semiconductor substrate having a suitable conductivity type, such as p-type or n-type, and the composition of the substrate 200 may include, but is not limited to, silicon, germanium, gallium nitride, or other suitable semiconductor materials.

[0052] At least one stacked structure 300 is on the substrate 200. For example, two stacked structures 300 are disposed on the substrate 200 and laterally spaced apart from each other. Each stacked structure 300 includes a gate dielectric layer 202, a select gate 204, and a sacrificial layer 208, which are stacked in sequence. The select gate 204 is made of a conductive material and is configured to switch on / off a carrier channel (referred to as a channel region) in the substrate 200 below the select gate 204 when biased with an appropriate voltage. The sacrificial layer 208 is the top layer in the stacked structure 300 and is a temporary layer configured to be removed before a subsequent process to form an erase gate in the select gate 204. In one embodiment, the select gate 204 formed in the manufacturing stage shown in FIG. 5 may be a conductive layer having a different pattern than the pattern of the select gate 204 shown in FIGS. 1 and 2. Therefore, if the select gate 204 shown in FIG. 5 has a different contour than the select gate 204 shown in FIGS. 1 and 2, the select gate 204 may be further patterned to become the select gate 204 shown in FIGS. 1 and 2 in the following manufacturing process.

[0053] The dielectric spacers 212 are formed on the sidewalls of the stacked structure 300. The material of the dielectric spacers 212 is, for example, silicon oxide / silicon nitride / silicon oxide or silicon nitride / silicon oxide.

[0054] The floating gate dielectric layer 218 is formed on the substrate 200 at least between the stacked structures 300, or even on both sides of the stacked structures 300. The material of the floating gate dielectric layer 218 is, for example, silicon oxide or other layer that allows hot electrons to pass through by tunneling effect. The method of forming the floating gate dielectric layer 218 is, for example, but not limited to, thermal oxidation or thermal evaporation.

[0055] 6, a conformal conductive layer 254 is formed on the substrate 200 and the select gate 204, and the conformal conductive layer 254 conforms to the shape of the underlying structure. The material of the conformal conductive layer is, for example, doped polysilicon, polycide, or other suitable conductive material. When the material of the conductive layer is doped polysilicon, the formation method includes, for example, performing an ion implantation step after an undoped polysilicon layer is formed by chemical vapor deposition, or performing chemical vapor deposition with in-situ dopant implantation.

[0056] Then, a photolithography and etching process is performed to etch the corresponding conductive layer. As a result, the conductive layer is patterned to form a plurality of conductive stripes (not shown) that are separated from each other in a top view. Each conductive stripe can extend along the X direction at least in the first memory cell region 110 and the second memory cell region 112.

[0057] 7, a bonding dielectric layer 258 covering the conformal conductive layer 254 is formed on the substrate 200. The conformal conductive layer 254 has a stripe shape in top view, so that the bonding dielectric layer 258 covers not only the top surface of the conformal conductive layer 254 but also the sidewalls (not shown) of the conformal conductive layer 254. The bonding dielectric layer 258 can be a composite dielectric layer including, but not limited to, silicon oxide / silicon nitride / silicon oxide.

[0058] A control gate layer 260 is then disposed on the bonding dielectric layer 258. The thickness of the control gate layer 260 can be appropriately controlled so that the control gate layer 260 can conform to the shape of the underlying structure. The control gate layer 260 can be formed of a conductive material such as, but not limited to, polysilicon or metal.

[0059] Next, referring to FIG. 8, the control gate layer 260 is etched by an anisotropic etching process to form the control gate 240 on the sidewall of the stacked structure 300. The control gate 240 is a self-aligned structure having a non-vertical surface 246, and therefore does not require the use of a photolithography process. After the formation of the control gate 240, the control gates 240 in each of the first memory cell region 110 and the second memory cell region 112 can be laterally separated from each other in the X direction. Furthermore, after the formation of the control gate 240, a portion of the bonding dielectric layer 258 disposed above the stacked structure 300 can be exposed from the control gate 240.

[0060] Referring to FIG. 9, by using the control gate layer 260 as an etching mask, an anisotropic etching process is performed on the coupling dielectric layer 238 to form an L-shaped structure of the coupling dielectric layer 238, which includes a vertical portion 238_1 and a horizontal portion 238_2. By properly controlling the etching method and the type or rate of etching, the top surface 239_1 of the vertical portion 238_1 can be flat or concave, lower than the top tip of the control gate 240. Furthermore, the end 242 of the horizontal portion 238_2 of the bonding dielectric layer 238 can extend from under the control gate 240 and is partially exposed from the control gate 240. The end 242 of the horizontal portion 238_2 of the bonding dielectric layer 238 includes a non-vertical sidewall 239_2 that extends and is exposed from the control gate 240. After forming the bonding dielectric layer 238 including the vertical portion 238_1 and the horizontal portion 238_2, a portion of the coincident conductive layer 254 located at the boundary between the first memory cell region 110 and the second memory cell region 112 can be exposed.

[0061] Then, referring to FIG. 10, the matching conductive layer 254 is etched using the control gate 240 and the bonding dielectric layer 238 as an etching mask to form the floating gate 224. The floating gate 224 is an L-shaped structure including a vertical portion 224_1 and a horizontal portion 224_2. By using the control gate 240 and the bonding dielectric layer 238 as an etching mask, there is no need to perform an additional photolithography process to define the shape of the floating gate 224. The horizontal portion 224_2 of the floating gate 224 includes a side tip 226a that is not covered by the control gate 240. In addition, during the formation of the floating gate 224, a part of the control gate 240 can be etched at the same time, and the height of the control gate 240 can be slightly reduced. However, even if the size of the control gate 240 is reduced during the etching process, the size of the bonding dielectric layer 238 is not significantly reduced because the composition of the bonding dielectric layer 238 is different from that of the floating gate 224. After formation of the floating gate 224 , the floating gate dielectric layer 218 may also be etched to expose the substrate 200 at the boundary between the first memory cell region 110 and the second memory cell region 112 .

[0062] 11, at least one drain region 244, such as two drain regions 244, may be formed on the sides of the select gate 204. The drain regions 244 are disposed in the first memory cell region 110 and the second memory cell region 112, respectively, and are electrically connected through vias or contacts in a subsequent manufacturing process. In addition, the source region 222 may be simultaneously formed in the substrate 200 between the control gates 220.

[0063] The method of forming the drain region 244 and the source region includes, for example, an ion implantation process. The implanted dopant can be an n-type or p-type dopant, which is determined according to the device design. The dopants and doping concentrations of the source region 222 and the drain region 244 can be the same or different.

[0064] An erase gate dielectric layer 234 is then formed conforming to the select gate 204 , the floating gate 224 and the control gate 240 .

[0065] Erase gates and other structures may then be formed to obtain a non-volatile memory device similar to the structure shown in FIGS.

[0066] Those skilled in the art will readily appreciate that numerous modifications and variations of the apparatus and methods may be practiced in light of the present disclosure. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims. [Brief description of the drawings]

[0067] [Figure 1] FIG. 1 is a schematic top view of a non-volatile memory device according to an embodiment of the present disclosure. [Diagram 2] 2 is a schematic cross-sectional view of a non-volatile memory device corresponding to lines AA', BB', and CC' in FIG. 1 according to an embodiment of the present disclosure. [Diagram 3] 2A-2C are schematic cross-sectional views of various non-volatile memory devices according to an embodiment of the present disclosure, corresponding to line AA' in FIG. 1; [Figure 4] 2A-2C are schematic cross-sectional views of various non-volatile memory devices according to another embodiment of the present disclosure, corresponding to line AA' in FIG. 1; [Diagram 5] 5A to 5C are schematic cross-sectional views of the non-volatile memory device of FIGS. 1 and 4 at different stages in a method of manufacturing the non-volatile memory device of FIG. [Figure 6] 5A to 5C are schematic cross-sectional views of the non-volatile memory device of FIGS. 1 and 4 at different stages in a method of manufacturing the non-volatile memory device of FIG. [Figure 7] 5A to 5C are schematic cross-sectional views of the non-volatile memory device of FIGS. 1 and 4 at different stages in a method of manufacturing the non-volatile memory device of FIG. [Figure 8] 5A to 5C are schematic cross-sectional views of the non-volatile memory device of FIGS. 1 and 4 at different stages in a method of manufacturing the non-volatile memory device of FIG. [Figure 9] 5A to 5C are schematic cross-sectional views of the non-volatile memory device of FIGS. 1 and 4 at different stages in a method of manufacturing the non-volatile memory device of FIG. [Figure 10] 5A to 5C are schematic cross-sectional views of the non-volatile memory device of FIGS. 1 and 4 at different stages in a method of manufacturing the non-volatile memory device of FIG. [Figure 11] 5A to 5C are schematic cross-sectional views of the non-volatile memory device of FIGS. 1 and 4 at different stages in a method of manufacturing the non-volatile memory device of FIG.

Claims

1. at least one memory cell; The at least one memory cell comprises: A substrate; a select gate disposed on the substrate; a control gate disposed in the substrate, laterally spaced from the select gate, the control gate including a non-vertical surface; a floating gate disposed on the substrate, a vertical portion disposed between the select gate and the control gate and including a first upper tip spaced laterally from the control gate; a floating gate including a horizontal portion disposed between the substrate and the control gate, the horizontal portion including a lateral tip spaced laterally and vertically from the control gate; an erase gate covering the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate; A non-volatile memory device, wherein the erase gate is used to extract electrons from the side tip of the floating gate during an erase operation of the non-volatile memory device.

2. The non-volatile memory device of claim 1 , wherein the non-vertical surface of the control gate comprises an inclined or curved surface.

3. The non-volatile memory device of claim 1 , wherein a bottom surface of the control gate is lower than a top surface of the vertical portion of the floating gate.

4. The non-volatile memory device of claim 1 , wherein the first top tip of the vertical portion of the floating gate is higher than a top surface of the select gate.

5. 2. The non-volatile memory device of claim 1, wherein the floating gate further comprises a corner at a bottom corner of the floating gate, the corner being laterally spaced from the control gate.

6. The vertical portion of the floating gate is Two first upper tips facing each other and arranged along a first direction; two first side walls that face each other, are arranged along the first direction, and are connected to the two first upper ends, respectively; two second side walls facing each other and arranged along a second direction different from the first direction, The non-volatile memory device of claim 1 , wherein the control gate extends along the second direction and covers the two second sidewalls of the vertical portion of the floating gate.

7. The non-volatile memory device of claim 1 , wherein the erase gate includes a top planar surface, and the height of the erase gate is up to 20% greater than the height of the select gate.

8. The non-volatile memory device of claim 1 , wherein the erase gate further covers a top surface of the vertical portion of the floating gate.

9. 2. The non-volatile memory device of claim 1, further comprising an additional erase gate laterally spaced from the erase gate and overlying an upper surface of the vertical portion of the floating gate.

10. 10. The non-volatile memory device of claim 9, wherein the erase gate is configured to be biased at a first voltage and the further erase gate is configured to be biased at a second voltage different from the first voltage.

11. a coupling dielectric layer disposed between the control gate and the floating gate; The coupling dielectric layer comprises: a vertical portion disposed between the control gate and the vertical portion of the floating gate; a horizontal portion disposed between the control gate and the horizontal portion of the floating gate; The non-volatile memory device of claim 1 , wherein a portion of said horizontal portion of said coupling dielectric layer extends beneath said control gate and is exposed from said control gate.

12. The non-volatile memory device of claim 11 , wherein the horizontal portion of the coupling dielectric layer includes a non-vertical sidewall exposed from the control gate.

13. 2. The non-volatile memory device of claim 1, further comprising a dielectric spacer disposed between the select gate and the vertical portion of the floating gate, the dielectric spacer including a curved upper surface that is lower than a top surface of the vertical portion of the floating gate.

14. the at least one memory cell includes a first memory cell and a second memory cell; each of the first memory cell and the second memory cell includes the select gate, the floating gate, and the control gate; the non-volatile memory device further includes a source region shared by the first memory cell and the second memory cell; The non-volatile memory device of claim 1 , wherein the source region is covered by the erase gate.

15. 15. The non-volatile memory device of claim 14, wherein the first memory cell and the second memory cell are mirror images of each other.

16. 15. The non-volatile memory device of claim 14, wherein the erase gate fills a gap between the control gates of the first memory cell and the second memory cell.

17. A method for manufacturing a non-volatile memory device includes the steps of: Providing a substrate; forming a select gate in the substrate; forming a coincident conductive layer on the substrate and on the select gate; forming a control gate covering a sidewall of the select gate and the coincident conductive layer and including a non-vertical surface; etching the conformal conductive layer exposed from the control gate; This forms a floating gate, The floating gate is a vertical portion disposed between the select gate and the control gate; a horizontal portion disposed between the substrate and the control gate, the horizontal portion including a lateral apex; forming an erase gate overlying the non-vertical surface of the control gate and the lateral tip of the horizontal portion of the floating gate; A method for manufacturing a non-volatile memory device, wherein the erase gate is used to extract electrons from the side tip of the floating gate during an erase operation of the non-volatile memory device.

18. forming a coupling dielectric layer overlying the conformal conductive layer prior to forming the control gate; after forming the control gate, etching the coupling dielectric layer exposed from the control gate; This exposes a portion of the conductive layer, and etching the portion of the conformal conductive layer exposed from the coupling dielectric layer; The method for manufacturing a non-volatile memory device according to claim 17, thereby forming the floating gate.

19. In the step of etching the conformal conductive layer, the coupling dielectric layer is a vertical portion disposed between the control gate and the select gate; a horizontal portion disposed between the control gate and the substrate, The method of claim 18 , wherein a portion of the horizontal portion of the coupling dielectric layer extends beneath the control gate and is exposed from the control gate.

20. 20. The method of claim 19, wherein in the step of etching the conformal conductive layer, the horizontal portion of the coupling dielectric layer includes a non-vertical sidewall exposed from the control gate.

21. forming the erase gate further comprises simultaneously forming an additional erase gate; 20. The method of claim 17, wherein the further erase gate is laterally spaced from the select gate and overlies an upper surface of the vertical portion of the floating gate.

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