Structure and method for fabricating a resistive memory having vertically defined filaments - Patents.com

Abstract

A semiconductor structure including a vertical resistance change memory cell and a method for fabricating the same includes forming a sacrificial layer over a transistor drain contact, forming a first dielectric layer over the sacrificial layer, forming a cell contact hole through the first dielectric layer, forming an access contact hole through the first dielectric layer and exposing the sacrificial layer, removing the sacrificial layer to form a cavity connecting the lower opening of the cell contact hole and the lower opening of the access contact hole, forming a second dielectric layer including a seam in the cell contact hole by atomic layer deposition, forming a bottom electrode in the cavity contacting the drain contact, the second dielectric layer, and the seam, and forming an top electrode over the first dielectric layer contacting the second dielectric layer and the seam.

Description

[Technical field]

[0001] The present invention relates generally to the field of semiconductors, and more particularly to a method for fabricating a resistive memory device. [Background technology]

[0002] Resistive Random Access Memory (ReRAM) is a type of non-volatile memory whose operating principle is based on the resistance difference between the on and off states. Conductive Bridge Random Access Memory (CBRAM) is another type of non-volatile memory whose operating principle is based on the resistance difference between the on and off states. Depending on the physical connection of multiple nano-sized filaments between the top and bottom electrodes of each memory cell in this type of non-volatile memory, high or low resistance is defined.

[0003] The problem with this kind of non-volatile memory, for example ReRAM or CBRAM, is that it is impossible to predict where and how many filaments will form in each memory cell of such a non-volatile memory. Therefore, in such a non-volatile memory, the behavior between memory cells may be non-uniform and unpredictable, which may result in a somewhat lower overall performance. The uncertainty of filament formation in each memory cell compared to another memory cell in such a non-volatile memory significantly affects the reliability of the operation of the non-volatile memory. Summary of the Invention

[0004] Various embodiments of the present invention involve fabricating a semiconductor structure that includes at least a resistive change memory cell (also referred to as a resistive change memory element). For example, the method and structure include forming at least one resistive change memory cell in a semiconductor structure. The method includes forming a sacrificial layer on and in contact with an electrical contact of the transistor; forming a first dielectric layer on and in contact with the sacrificial layer; forming a cell contact hole through the first dielectric layer to expose a first portion of the sacrificial layer; forming an access contact hole through the first dielectric layer to expose a second portion of the sacrificial layer; removing a remaining portion of the sacrificial layer, thereby forming a cavity directly connecting a lower opening of the cell contact hole and a lower opening of the access contact hole; forming a second dielectric layer on an inner wall of the first contact hole above the cavity, where a seam is formed in the second dielectric layer between the inner walls of the cell contact hole; forming a bottom electrode in a portion of the cavity in contact with an upper surface of the electrical contact and a lower surface of the second dielectric layer and a lower surface of the seam; and forming a top electrode on the dielectric layer and in direct contact with an upper surface of the second dielectric layer and an upper surface of the seam.

[0005] According to various embodiments, a semiconductor structure includes at least one memory cell including a transistor and a resistor. The semiconductor structure includes a transistor including a drain, a gate, and a source, and a vertical memory resistor element having first and second electrical contacts. Either the first or second of the electrical contacts is electrically connected to a drain of the transistor.

[0006] In one embodiment, the vertical memory resistor element includes a vertically oriented seam located proximate a central region of a length of the vertical memory resistor element from a first electrical contact to a second electrical contact. The vertically oriented seam extends from the first electrical contact to the second electrical contact. In one embodiment, the vertically oriented seam includes a conductive filament extending from the first electrical contact to the second electrical contact.

[0007] The accompanying drawings, in which like reference numbers indicate identical or functionally similar elements throughout the different views, and which, together with the following detailed description, are incorporated in and form a part of this specification, further illustrate various embodiments, and all serve to explain various principles and advantages according to the present invention. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional side view of an example semiconductor structure at a first point in an example fabrication process, such as for fabricating a resistive change memory device, in accordance with one embodiment of the present invention. [Diagram 2] 2 is a cross-sectional side view of the example semiconductor structure of FIG. 1 at a subsequent point in an example fabrication process. [Diagram 3] 3 is a cross-sectional side view of the example semiconductor structure of FIG. 2 at a subsequent point in the example fabrication process after vertical cell contact holes have been formed. [Figure 4] 4 is a cross-sectional side view of the example semiconductor structure of FIG. 3 at a subsequent point in the example fabrication process after vertical access contact holes have been formed. [Diagram 5] 5 is a top view of the semiconductor structure shown in FIG. [Figure 6] 5 is a cross-sectional side view of the example semiconductor structure of FIG. 4 at a subsequent point in the example fabrication process where the a-Si layer has been removed. [Figure 7] 7 is a cross-sectional side view of the example semiconductor structure of FIG. 6 at a subsequent point in the example fabrication process after atomic layer deposition of a dielectric filling the vertical cell contact holes and forming seams. [Figure 8] 8 is a cross-sectional side view of the example semiconductor structure of FIG. 7 at a subsequent point in an example fabrication process. [Figure 9] 9 is a cross-sectional side view of the example semiconductor structure of FIG. 8 at a subsequent point in the example fabrication process after forming a bottom electrode of a resistive change memory cell. [Figure 10]10 is a cross-sectional side view of the example semiconductor structure of FIG. 9 at a subsequent point in the example fabrication process after forming a top electrode of a resistive change memory cell. [Figure 11] 1 is a workflow diagram illustrating an exemplary fabrication process for fabricating a semiconductor structure including a resistive change memory cell in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] It is to be understood that the present invention is described with respect to an exemplary fabrication process for fabricating semiconductor structures, including field effect transistor semiconductor devices and / or other types of transistors, however, other semiconductor architectures, structures, substrate materials and process features and steps may be modified within the scope of the present invention.

[0010] The inventors have discovered that it would be highly desirable to have a resistive random access memory (ReRAM) that includes a conductive bridge random access memory (CBRAM) that forms a single filament at a predefined location in the resistive memory cell.

[0011] Various embodiments of the present invention include a new and novel architecture of a semiconductor structure including at least one non-volatile memory device. The memory device includes multiple resistive change memory cells (also referred to herein as resistive change memory elements) on the same semiconductor substrate, for example, on a wafer. This structure can be used to fabricate, for example, a CMOS non-volatile memory device in an integrated circuit.

[0012] When an element such as a layer, region or substrate is said to be "on," "on" or "above" another element, it is understood that the element may be directly "on," "on" or "above" the other element, or intervening elements may also be present. When an element such as a layer, region or substrate is said to be "under" or "below" another element, it is understood in the same but opposite sense. The element may be directly "below" or "below" the other element, or intervening elements may also be present. In contrast, when an element is said to be "directly on," "directly above," or "directly above" another element, or "directly below" or "directly below" another element, there are no intervening elements present. Also, when an element is said to be "connected" or "coupled" to another element, it is understood that the element is directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0013] The described embodiments may include a design for an integrated circuit chip, created in a graphical computer programming language and storable on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as a storage access network). If the designer does not fabricate the chip or the photolithography masks used to fabricate the chip, the designer may send the resulting design by physical means (e.g., by providing a copy of a storage medium storing the design) or transmit it electronically (e.g., via the Internet) directly or indirectly to such an entity. The stored design is then converted into a suitable format (e.g., GDSII) for fabrication of a photolithography mask, which typically contains multiple copies of the chip design to be formed on a wafer. The photolithography mask is used to define areas of the wafer (or layers thereon) to be etched or otherwise processed.

[0014] The methods described herein can be used as part of a process in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as bare dies, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination of these, as part of (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and a central processing unit.

[0015] Reference herein to "one embodiment" or "an embodiment" of the present invention, as well as other variations, means that the particular features, structures, characteristics, etc. described in connection with that embodiment are included in at least one embodiment of the present principles. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" and other variations in various places throughout the specification are not necessarily all referring to the same embodiment.

[0016] It should be understood that the various layers and / or regions shown in the accompanying drawings are not drawn to scale, and that one or more layers and / or regions of the type commonly used in complementary metal oxide semiconductor (CMOS), field effect transistors (FET), metal oxide semiconductor field effect transistors (MOSFET) or other semiconductor devices or combinations thereof may not be explicitly shown in a particular drawing. This does not imply that the layers and / or regions not explicitly shown are omitted from the actual device. Furthermore, certain elements may be omitted from a particular drawing for clarity and / or simplicity, if the description does not necessarily focus on the omitted elements. Also, the same or similar reference numbers used throughout the drawings are used to indicate the same or similar features, elements or structures, and thus a detailed description of the same or similar features, elements or structures will not be repeated from drawing to drawing.

[0017] Semiconductor devices and methods of forming the same according to various embodiments of the present invention may be employed in applications, hardware, or electronic systems, or combinations thereof. Suitable electronic hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., mobile phones and smartphones), solid-state media storage devices, functional circuits, and the like. Systems and hardware including semiconductor devices and structures are contemplated embodiments of the present invention. Given the teachings of the exemplary embodiments of the present invention described herein, one skilled in the art will be able to contemplate other implementations and applications of the embodiments of the present invention.

[0018] Various embodiments of the present invention can be implemented in connection with semiconductor devices and associated semiconductor fabrication processes that can use CMOS, MOSFET, or FET technologies, or a combination thereof. As non-limiting examples, the semiconductor devices can include, but are not limited to, CMOS, MOSFET, and FET devices, and / or semiconductor devices using CMOS, MOSFET, and / or FET technologies.

[0019] As used herein, "vertical" refers to a direction perpendicular to the substrate in any cross-sectional and three-dimensional views herein. Current may be described herein as flowing vertically (e.g., between a bottom electrode in a vertically oriented resistive change memory cell and a top electrode in a vertically oriented resistive change memory cell above the bottom electrode). As used herein, "horizontal" refers to a direction parallel to the substrate in any cross-sectional and three-dimensional views herein.

[0020] As used herein, "thickness," "thick," and the like refer to the size of an element (e.g., a layer, trench, hole, etc.) in a cross-sectional view, measured from the bottom surface to the top surface of the element, or from the left side surface to the right side surface of the element, or measured relative to a surface immediately adjacent and contacting the element (e.g., the surface on which the element is directly disposed), or any combination thereof.

[0021] Additionally, terms such as "width" or "width value" refer to the distance from a beginning point on a structure to an end point on that same structure at a critical dimension. For example, a width value can be measured horizontally along a critical dimension from the beginning of a vertical contact metal structure to an end point on that same vertical contact metal structure.

[0022] Unless otherwise specified, "height" or "height above a substrate" as used herein refers to the vertical size of an element in a cross-sectional view measured from the top surface of the substrate to the top surface of the element (e.g., layer, trench, hole, etc.). The thickness of an element may be equal to the height of the element if the element were directly above the substrate.

[0023] As used herein, the terms "lateral," "side," and "side" refer to a side of an element (e.g., a layer, an opening, a sidewall spacer, etc.), such as the left or right side in a cross-sectional view of the present specification.

[0024] Referring now to the drawings, in which like numbers represent the same or similar elements, FIGS. 1 through 4 are 4 is a cross-sectional side view illustrating the example semiconductor structure 100 at selected points in an example fabrication process. Line 5-5 shown in Figure 4 passes over the portion of the illustrated semiconductor structure 100 and corresponds to the top view of the example semiconductor structure 100 shown in Figure 5. Figures 6 through 10 are cross-sectional side views illustrating the example semiconductor structure 100 at subsequent selected points in the example fabrication process.

[0025] An example semiconductor structure 100 shown in FIG. 1 is used in this description to illustrate an example semiconductor fabrication process according to various embodiments of the present invention.

[0026] As shown in FIG. 1, according to one embodiment of a semiconductor fabrication process, a transistor integration fabrication process forms transistors supported on a circuit support substrate 102. The transistors include adjacent gate stacks interposed between respective source / drain stacks as shown in FIG. 1. The gate stacks and the source / drain stacks are formed in a dielectric layer 108 supported by the circuit support substrate 102. It should be noted that a transistor is one non-limiting example of one type of memory cell selector device that may be used in a non-volatile random access memory to select at least one memory cell. However, other types of memory cell selector devices may be used in accordance with various embodiments of the present invention. For example, a diode may be used as the memory cell selector device.

[0027] According to various embodiments, the substrate 102 comprises at least one material selected from the set of materials consisting of silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon germanium carbide (SiGeC), carbon-doped silicon germanium (SiGe:C), III-V or II-V compound semiconductors, organic semiconductors, layered semiconductors, silicon-on-insulator, SiGe-on-insulator, amorphous materials, polycrystalline materials, single crystal materials, or hybrid-orientation (HOT) semiconductor materials, or combinations of materials from this set.

[0028] Each source / drain stack includes a respective epitaxial active region 104, 106 in the substrate 102. Each source / drain stack includes a source / drain metal 114, 116 and a top metal contact 118, 120 disposed above the source / drain metal 114, 116, respectively.

[0029] The gate stacks may be disposed above the respective fin channels in the substrate 102. For example, the fin channel in FIG. 1 is located adjacent to and in contact with two epitaxial active regions 104, 106 that form a path for current to pass horizontally between the two epitaxial active regions 104 of the transistor below the gate stack in the substrate 102. The example gate stack shown in FIG. 1 includes a high-k dielectric layer 112 and a gate metal contact 110 disposed on and in contact with the high-k dielectric layer 112. The example shown in FIG. 1 represents an NFET or PFET transistor. It should be noted that the description herein is provided as a non-limiting example to illustrate various aspects of embodiments of the present invention. The example transistors described herein do not necessarily represent actual circuit layouts. The description of the example transistors is provided merely to illustrate that an example process flow according to an embodiment of the present invention may be effective for either or both NFET and PFET circuit elements.

[0030] A destination metal contact (also referred to as a destination electrical contact) 124 formed in the interlevel dielectric (ILD) layer 122 is electrically connected to the first drain / source metal contact 114 or the second drain / source metal contact 116 according to this example, or to a first set combination of the drain / source metal contacts 114 and 118 or a second set combination of the drain / source metal contacts 116, 120 according to various embodiments. According to this example, the destination metal contact 124 is electrically connected to the drain contacts 116 (e.g., the second set of drain / source metal contacts 116, 120) of the transistor drain active region 106 shown in FIG. 1. The destination metal contact 124 may also be referred to as a drain contact 124 in this description of an exemplary fabrication process. However, it will be apparent that any combination of metal contacts of a transistor may be electrically coupled to the destination metal contact 124 according to various embodiments.

[0031] Also, as noted above, a transistor is one example of a type of memory selector device that can be used in accordance with various embodiments. Other types of selector devices can be used instead or in addition to select at least one memory cell in a non-volatile memory device. Generally, the selector device contacts are electrically connected to the destination metal contacts 124. The selector device is electrically controllable to select a particular memory cell in the non-volatile memory device.

[0032] Figure 1 illustrates a point in an exemplary semiconductor fabrication process where a semiconductor material stack 102, 108, 122 is provided, including a substrate 102, a gate stack, and multiple drain / source stacks. An amorphous silicon (a-Si) sacrificial layer 126 is then deposited on the ILD layer 122, which is on the dielectric layer 108, as shown in Figure 1, and then a planarization process, such as a chemical and / or mechanical planarization (CMP) step or an etching step, is performed to remove excess material from a top surface of the a-Si sacrificial layer in the semiconductor structure 100, and optionally from a top surface of the wafer. The a-Si layer 126 may also be referred to as the sacrificial layer 126, since the a-Si layer 126 will be removed in a downstream fabrication process step.

[0033] 2, the a-Si layer 126 is then patterned into a circular (or rectangular or other) shape. A silicon dioxide (SiO2) layer 202, which may also be referred to as an ILD layer 202 or a first dielectric layer 202, is deposited on and contacts the top surface of the patterned a-Si layer 126, as shown in FIG. According to various embodiments, the first dielectric layer 202 comprises at least one dielectric selected from the set of dielectrics consisting of silicon nitride (SiN), silicon carbide (SiC), SiCO, silicon oxide, silicon dioxide (SiO2), carbon-doped silicon oxide (SiCOH), one or more silicon-based materials with partial or total replacement of Si by Ge, carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamide or SiLK™, other carbon-based materials, organic-inorganic materials such as spin-on-glass and silsesquioxane-based materials, diamond-like carbon (DLC), also known as amorphous hydrogenated carbon (α-C:H), or any of the above materials in porous form or in a form that changes during processing to porous and / or permeable, or from porous and / or permeable to non-porous and / or non-permeable.

[0034] As shown in FIG. 3, a vertically oriented cell contact hole 302, which may also be referred to as a vertical cell contact hole 302, is formed in the SiO2 layer 202 (also referred to as an ILD layer 202) above the a-Si layer 126 and continues down to the underside of the a-Si layer 126 or slightly through the a-Si layer 126. A vertical etching process, such as, but not limited to, a dry etching process using a fluoride-based chemistry or a reactive ion etching (RIE) process, or another etching process, may be used to form the vertically oriented cell contact hole 302. According to this embodiment, the vertically oriented cell contact hole 302 exposes the drain contact 124 within the vertical cell contact hole 302. However, the cell contact hole 302 is located above the drain contact 124, but not necessarily directly above it (e.g., vertically aligned with the drain contact 124). The cell contact hole 302 may be located at a horizontal location within the a-Si layer 126 adjacent to, but not necessarily directly above, the horizontal location of the drain contact 124 .

[0035] Continuing with the fabrication process, as shown in FIG. 4, a vertically oriented access contact hole 402, which may also be referred to herein as a vertical access contact hole 402, is patterned in the SiO2 layer 202 (which may also be referred to as an ILD layer 202 or a first dielectric layer 202, etc.) directly above and partially down into or through the sacrificial a-Si layer 126. The horizontal critical dimension (CD) of the vertically oriented access contact hole 402 may be much larger than the horizontal CD of the vertically oriented cell contact hole 302. The vertically oriented access contact hole 402 may be formed by a vertical etching process, such as, but not limited to, a dry etching process using a fluoride-based chemistry or a reactive ion etching (RIE) process, or other etching process.

[0036] The vertically oriented access contact hole 402 forms an access opening in the sacrificial a-Si layer 126, which can have a horizontal CD that is much larger than the horizontal CD of the vertically oriented cell contact hole 302. The vertically oriented access contact hole 402 can be used, for example, to facilitate an etching process to remove the sacrificial a-Si layer 126, thereby forming an empty opening or cavity 602 after removal of the sacrificial a-Si layer 126, as shown in FIG. 6. The vertically oriented access contact hole 402 also facilitates access into the empty opening or cavity 602 in downstream fabrication process steps. As described in more detail below, according to various embodiments, the vertically oriented access contact hole 402 facilitates access into the empty opening or cavity 602 for forming a bottom electrode 902 of a vertical memory cell 802 (see FIGS. 8, 9, and 10) formed in the vertically oriented cell contact hole 302.

[0037] Although the above describes the formation of the vertical access contact hole 402 and the formation of the vertical cell contact hole 302 separately from each other, it should be noted that the formation of these two holes 302, 402 may be performed simultaneously with each other or separately from each other according to various embodiments.

[0038] 5 illustrates a top view of the semiconductor structure 100 at this point in the exemplary semiconductor fabrication process. According to this embodiment, the vertical access contact hole 402 and the vertical cell contact hole 302 are horizontally adjacent to each other and are both located directly above the a-Si sacrificial layer 126.

[0039] Continuing with the exemplary semiconductor fabrication process, the a-Si sacrificial layer 126 is then completely removed by a selective isotropic etching process, as shown in FIG. 6. For example, a selective wet etching process can be an isotropic etching process. Optionally, the etching can be performed by another suitable wet or dry etching process. The selective etching leaves an empty space 602 (also sometimes referred to as a cavity 602) where material has been removed from the a-Si sacrificial layer 126. The cavity 602 connects the bottom opening of the vertically oriented cell contact hole 302 and the bottom opening of the vertically oriented access contact hole 402.

[0040] 7, the exemplary semiconductor fabrication process continues with atomic layer deposition (ALD) of a dielectric 702 on the exposed surfaces of the semiconductor structure 100 (e.g., the dielectric 702 is applied and formed on the inner walls of the vertical cell contact holes 302). A series of coating layers of the dielectric 702, e.g., about 15 nm thick each, are applied and formed progressively on the exposed surfaces of the semiconductor structure 100. The formed dielectric 702 fills the vertical cell contact holes 302 according to one embodiment. See also FIG. 8.

[0041] In this example, the dielectric 702 filling the vertical cell contact hole 302 includes a vertical seam 704 adjacent to a central region (centered horizontally relative to the sidewalls of the vertically oriented cell contact hole 302) of the vertical memory cell 802 (see, for example, FIGS. 8 and 10, which illustrate the fabrication of the vertical memory cell 802, including the top electrode 1004 and the bottom electrode 902 in FIG. 10). The dielectric 702 (which may also be referred to as the second dielectric layer 702) may include, as an example, a metal with an oxide. As another example, the second dielectric layer 702 may include a metal with a nitride. According to various embodiments, the second dielectric layer 702 includes at least one dielectric selected from a set of dielectrics consisting of a metal oxide, a metal nitride, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), carbon doped silicon nitride (SiCN), or boron doped silicon carbonitride (SiBCN), or any combination of these dielectrics.

[0042] According to this embodiment, the dielectric 702 is applied as a thin film using an ALD process to the exposed surfaces in the empty space 602, the exposed surfaces in the vertical cell contact holes 302 (e.g., on the inner walls of the vertical contact holes 302), the exposed surfaces in the vertical access contact holes 402 (e.g., on the inner walls of the vertical access contact holes 402), and the exposed surfaces of the top surface of the semiconductor structure 100, as shown in FIG. 7. The thickness of each thin film layer of the dielectric 702 applied by the ALD process can be about 15 nm thick according to this embodiment. However, other layer thicknesses can be applied according to various embodiments. The thin film layers of the dielectric 702 are applied progressively and successively to the exposed surfaces in the semiconductor structure 100 and formed thereon. According to this embodiment, after the successive application of the thin film layers on top of each other, the overall applied thin film thickness of the dielectric 702 will increase until it reaches a total thickness that is thicker than about half the diameter of the vertical cell contact holes 302. This film deposition process adds layer upon layer of thin film of dielectric 702 until it pinches off further application of the thin film layer of dielectric 702 in the vertical cell contact hole 302. This thin film deposition process also forms a vertical seam 704 in the dielectric layer 702 in the vertical cell contact hole 302.

[0043] The vertical seam 704 is formed in the vertical cell contact hole 302 of the second dielectric layer 702 as a result of an ALD process and / or another thin film deposition process that fills the vertical cell contact hole 302 with a series of progressively applied layers of the dielectric 702. The vertical seam 704 is formed proximate to a central region (horizontally centered relative to the sidewalls of the vertically oriented cell contact hole 302) of the dielectric 702 that fills the vertical cell contact hole 302, according to this embodiment. See also vertical memory cell 802 including a centrally located vertical seam 704 shown in FIG. 8.

[0044] In this embodiment, an ALD process is used because it ensures uniform seams in the center of the vertical cell contact holes 302. According to this embodiment, although an ALD process is used to apply the thin layer of dielectric 702 and to form the vertical seams 704 as described above, other thin film deposition processes can be used instead or in addition to applying the thin layer of dielectric 702 and / or to form the vertical seams 704. One example of a deposition process that can be used is a chemical vapor deposition (CVD) process. Another example of a deposition process that can be used is a physical vapor deposition (PVD) process.

[0045] The ALD process that can be used to progressively apply the successive layers of dielectric 702 filling the vertical cell contact holes 302 can be, for example, a thermal ALD process. As another example, the ALD process can be a plasma ALD process. The dielectric layer 702 filling the vertical cell contact holes 302, according to various embodiments, includes at least one dielectric selected from a set of dielectrics consisting of metal oxides, metal nitrides, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), carbon doped silicon nitride (SiCN), or boron and carbon doped silicon carbonitride (SiBCN), or any combination of these dielectrics.

[0046] The vertical seam 704 is formed by an ALD process proximate to a central region (horizontally centered relative to the sidewalls of the vertically oriented cell contact hole 302) of the dielectric 702 that, according to this example, fills the vertical cell contact hole 302. The vertical seam 704 can, according to various embodiments, be doped with a conductive material to form a single conductive (e.g., resistive) filament at a known location that extends vertically inward from the top electrode 1004 to the bottom electrode 902 of the vertical memory cell 802 (see FIG. 8 and FIG. 10, which show the fabrication of the vertical memory cell 802, where FIG. 10 includes the top electrode 1004 and bottom electrode 902).

[0047] The single conductive (resistive) filament configuration can provide significant advantages in non-volatile memories, such as resistive random access memories (ReRAMs), including conductive bridge random access memories (CBRAMs). In non-volatile memory devices, according to various embodiments, operation between memory cells can be reliably and uniformly generated across the memory cells in the non-volatile memory device. This results in superior overall performance of the non-volatile memory device. The single filament configuration of each vertical memory cell 802 (see FIGS. 8 and 10) provides reliability of filament formation and device operation in the non-volatile memory device. The reliability of operation of such non-volatile memory devices, such as ReRAM memory devices, is significantly improved. This, in turn, greatly increases the commercial viability of this type of resistive non-volatile memory device and associated semiconductor fabrication process.

[0048] Continuing with this exemplary semiconductor fabrication process, as shown in FIG. 8, optionally, excess dielectric 702 is removed from the open spaces 602, from the vertical access contact holes 402, and from the top surface of the semiconductor structure 100. To remove the excess dielectric 702, an isotropic etching process, dry or wet, or a combination of dry and wet etching, can be used. The dielectric 702 filling the vertical cell contact holes 302 is not removed. As shown in FIG. 8, the top and bottom surfaces of a vertical seam 704 adjacent to the central region of the vertical memory cell 802 (horizontally centered with respect to the sidewalls of the vertically oriented cell contact holes 302) will be exposed at the top and bottom openings of the vertical cell contact holes 302. This vertical seam 704 can be doped with a conductive material to form a single conductive (e.g., resistive) filament at a known location inside the vertical memory cell 802 (see FIG. 8) at the vertical cell contact hole 302, according to various embodiments.

[0049] To improve the switching characteristics of the filament 704 in the vertical memory cell 802, the seam 704 can be doped with a mobile element (e.g., a mobile metal species) such as copper (Cu) or silver (Ag). This doping can, for example, be performed by injecting a mobile metal species into the seam 704 to aid in the formation of the filament 704. There are various ways to dope the seam 704. For example, the doping can be performed using a dopant-containing electrode 902 or 1004.

[0050] As another example, doping may occur after Figure 9 and before Figure 10 in an exemplary fabrication process. Referring to Figure 10, after the dielectric plug material 1002 is formed, a dopant material may be deposited and driven into the seam 704 by a thermal anneal. After the dopant is driven into the seam 704, the dopant on the surface is removed, leaving only the dopant in the seam 704.

[0051] As described below with reference to FIG. 10, the top electrode 1004 (see FIG. 10) of the vertical memory cell 802 is formed in direct contact with the top surface of the vertical memory cell 802 and the top surface of the vertical seam (and filament) 704. The top electrode 1004 may be a dopant for doping a mobile element (e.g., a mobile metal species) into the vertical seam (and filament) 704, according to various embodiments. For example, according to certain embodiments, after depositing and contacting a metal such as copper (Cu) on the top surface of the vertical seam (and filament) 704 to form the top electrode 1004 for the vertical memory cell 802, copper atoms diffuse downward and migrate from the top electrode 1004 into the vertical seam (and filament) 704.

[0052] As shown in FIG. 9, a conductive material 902 can be deposited in the vertically oriented access contact hole 402, thereby filling the vacant space 602 below the vertical memory cell 802 (see FIG. 8) and contacting the bottom surface of the vertical memory cell 802 and the vertical seam 704, thereby forming a bottom electrode 902 for the vertical memory cell 802. The bottom electrode 902 for the vertical memory cell 802 is formed directly on top of and contacts the intended metal contact 124 (e.g., drain contact 124 of a transistor). The conductive material 902 may partially (or completely) fill the vertical access contact hole 402, or excess conductive material 902 may be deposited directly on and contact the top surface of the semiconductor structure 100, as shown in FIG. 9. The deposition of the conductive material 902 can be by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process, or by another conductive material deposition process, or by any combination of processes, that enables the conductive material 902 to fill the empty space 602 (see FIG. 8) below the vertical memory cell 802, thereby forming the bottom electrode 902 for the vertical memory cell 802.

[0053] Continuing with the description of the exemplary semiconductor fabrication process, as shown in FIG. 10, the conductive material 902 is removed from the vertical access contact hole 402 and from the top surface of the semiconductor structure 100. As an example, a dry etching process, such as a reactive ion etching (RIE) process using a fluoride-based chemistry, can vertically etch the conductive material 902 from the vertical access contact hole 402. The dry etching process, or optionally in combination with a suitable wet etching process, can be used to remove the conductive material 902 from the top surface of the semiconductor structure 100. The dielectric gap filling in the vertical access contact hole 402 forms a dielectric plug 1002 that fills the vertical access contact hole 402. The bottom electrode 902 remains in electrical contact with the bottom surface of the vertical memory cell 802, the bottom surface of the vertical seam 704, and the top surface of the intended metal contact 124 (e.g., the drain contact 124 of the transistor).

[0054] An exemplary semiconductor fabrication process may then deposit a conductive material, optionally followed by patterning, to form a top electrode 1004 in direct contact over the dielectric layer 702 and over the top surface of the vertical seam 704 (see vertical memory cell 802 shown in FIG. 8), as shown in FIG. 10. The top electrode 1004 contacts the top surface of the vertical seam (and filament) 704 adjacent to a central region of the vertical memory cell 802 (which is horizontally centered relative to the sidewalls of the vertically oriented cell contact hole 302), according to an exemplary fabrication process.

[0055] The top electrode 1004 (see FIG. 10) of the vertical memory cell 802 formed directly in contact with the top surface of the vertical seam (and filament) 704 can also act as a dopant to add mobile elements (e.g., mobile metal species) into the vertical seam (and filament) 704. For example, according to a particular embodiment, after depositing a conductive material, such as, but not limited to, copper (Cu) or silver (Ag) or another material, on the top surface of the vertical seam (and filament) 704 to form the top electrode 1004, the conductive material atoms (e.g., copper atoms) can diffuse downward and migrate from the top electrode 1004 into the vertical seam (and filament) 704, thereby doping the vertical seam (and filament) 704 with the conductive material atoms (e.g., copper atoms).

[0056] Apart from using the top electrode 1004 (and / or bottom electrode 902) as a dopant, a conductive material may be used as a dopant to dope the vertical seam (and filament) 704 by a doping process. The conductive material may be added as a dopant to dope the vertical seam (and filament) 704 by a separate doping process as part of the overall semiconductor fabrication process as described above. By way of example, and not by way of limitation, the conductive material to dope the vertical seam (and filament) 704 may include a mobile element (e.g., a mobile metal species) or a non-stoichiometric compound by adding a reactive element, or a combination. A non-stoichiometric compound refers to a compound that includes reactants in amounts that are not in a simple integer ratio or in a ratio that is not expected from an ideal chemical or reaction equation. For example, TiO2 is a stoichiometric titanium dioxide. However, TiOx with x less than or greater than 2 is considered to represent a non-stoichiometric titanium oxide.

[0057] As another example, the vertical seam 704 may be doped with a conductive material selected from the set of conductive materials consisting of metal oxides, non-conductive metal nitrides, copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La). Thus, the seam 704 may include a material selected from the set of materials consisting of metal oxides, non-conductive metal nitrides, copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La). As another example, the seam 704 may be doped with at least one of a mobile element or a non-stoichiometric compound by adding a reactive element.

[0058] According to various embodiments, the second dielectric layer 702 formed by the ALD process in the vertically oriented cell contact hole 302, thereby forming the vertical memory resistor element 802, comprises at least one material selected from the set of materials consisting of metal oxide, non-conductive metal nitride, silicon oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), carbon-doped silicon nitride (SiCN), or silicon boron carbonitride (SiBCN), or any combination of these materials. The formed second dielectric layer 702 may also comprise a material selected from the set of materials consisting of metal oxide, non-conductive metal nitride, aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), silicon (Si), germanium (Ge), copper (Cu), or lanthanum (La).

[0059] At least one of the top electrode 1004 or the bottom electrode 902 (see FIG. 10 ) comprises a conductive material selected from the set of conductive materials consisting of copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), nickel (Ni), platinum (Pt), tin (Sn), silver (Ag), gold (Au), a conductive metal compound material, or a conductive alloy including at least one of these conductive materials, according to various embodiments. The vertical seam 704 can comprise a single conductive filament 704 extending from the top electrode 1004 to the bottom electrode 902, according to various embodiments.

[0060] 11 illustrates an exemplary method 1100 for fabricating a semiconductor structure including vertical memory cells electrically connected to transistor devices on a substrate. Various embodiments of the invention may include some, but not necessarily all, of the method steps in the illustrated example.

[0061] The exemplary fabrication method begins at step 1102 and immediately proceeds to step 1104 with receiving a semiconductor substrate material stack including a substrate 102 supporting a gate stack and first and second source / drain stacks of a transistor. The gate stack is adjacent to and interposed between the first and second source / drain stacks in a dielectric layer 108. The gate stack includes a gate metal contact 110. The first source / drain stack includes drain metal contacts 116, 120. The second source / drain stack includes source metal contacts 114, 118. Directly above the dielectric layer 108 is an ILD layer 122. The ILD layer 122 includes a destination metal contact 124.

[0062] The semiconductor fabrication method continues at step 1106 with the deposition of an a-Si layer 126 directly on and in contact with the top surface of the ILD layer 122. The a-Si layer is patterned to form a patterned shape of the a-Si layer 126 directly on and in contact with the top surface of the intended metal contacts 124 of the transistor. In this embodiment, the intended metal contacts 124 include and are electrically coupled to at least one of the drain metal contacts 116, 120 or the source metal contacts 114, 118. A first dielectric layer 202 is deposited on the a-Si layer 126. A vertical etch is performed to pattern both a vertical cell contact hole 302 and a vertical access contact hole 402 through the first dielectric layer 202 and into the a-Si layer 26. In this embodiment, the vertical cell contact hole 302 and the vertical access contact hole 402 are horizontally adjacent to each other directly on the a-Si layer 126.

[0063] The semiconductor fabrication method continues with removing the a-Si layer 126 in step 1108. Next, ALD of the dielectric 702 is performed, thereby filling the vertical cell contact hole 302 and forming a vertical seam 704 near the central region of the memory cell 802 formed in the vertical cell contact hole 302. The ALD process is also performed on other exposed surfaces in the semiconductor structure 100. Next, the semiconductor fabrication method continues with isotropic etching to remove the excess dielectric 702 from the semiconductor structure 100, thereby exposing the seam 704 and leaving the open space 602 where the a-Si layer 126 has been removed. The semiconductor fabrication method includes doping of a mobile metal species into the seam 704. Next, a conductive material 902 is deposited in the open space 602, followed by isotropic etching, thereby forming the bottom electrode 902 of the memory cell 802. The bottom electrode 902 is electrically connected to the top surface of the target metal contact 124, the bottom surface of the memory cell 802, and the bottom surface of the seam 704.

[0064] The semiconductor fabrication method continues at step 1110 with a dielectric gapfill deposition in the vertical access contact hole 402, thereby forming a dielectric plug 1002. The method then continues with the deposition of a conductive material layer 1004 over and in contact with the top surfaces of the memory cells 802 and the top surfaces of the seams 704, and then patterning, thereby forming the top electrodes 1004 of the memory cells 802.

[0065] The fabrication method then ends at step 1112.

[0066] A design of a resistive non-volatile memory device, e.g., a ReRAM memory device, according to various embodiments, includes a plurality of vertical memory cells 802, each memory cell including a single vertical conductive seam 704. This can significantly improve the reliability of operation of the non-volatile memory device. Operation between memory cells can be ensured to occur uniformly across all memory cells in the non-volatile memory device, resulting in superior overall performance of the non-volatile memory device. The single filament configuration of each vertical memory cell 802 provides reliability of filament formation and device operation in the non-volatile memory device. According to various embodiments, this can also reduce fabrication process defects, which can reduce semiconductor product manufacturing costs. This in turn increases the commercial viability of this type of resistive non-volatile memory device and the associated semiconductor fabrication process.

[0067] Although specific embodiments of the present invention have been described, those skilled in the art will recognize that changes can be made to these specific embodiments without departing from the scope of the present invention. Therefore, the scope of the present invention is not limited to these specific embodiments, and it is intended that the appended claims cover all such applications, modifications, and embodiments within the scope of the present invention.

[0068] It should be noted that some features of the present invention may be employed in one embodiment of the present invention without the use of other features of the present invention. As such, the foregoing description should be considered as merely illustrative of the principles, teachings, examples and exemplary embodiments of this invention, and not in limitation of the invention.

[0069] Moreover, these embodiments are merely examples of the many advantageous uses of the innovative teachings described herein. In general, statements in the specification of this application do not necessarily limit any of the various claimed inventions. Also, some statements may apply to some innovative features of the invention but not to other features.

Claims

1. 1. A method of fabricating a semiconductor structure including at least one resistive change memory cell, comprising: forming a dielectric layer on inner walls of cell contact holes above a cavity in a semiconductor structure, the dielectric layer forming a seam in the dielectric layer between the inner walls of the cell contact holes; forming a bottom electrode within a portion of the cavity contacting an upper surface of a target electrical contact and a lower surface of the dielectric layer and a lower surface of the seam; forming a top electrode over the dielectric layer and in direct contact with a top surface of the dielectric layer and a top surface of the seam.

2. forming a sacrificial layer on and in contact with the target electrical contact; forming a second dielectric layer over and in contact with the sacrificial layer; forming the cell contact hole through the second dielectric layer and exposing a first portion of the sacrificial layer; forming an access contact hole through the second dielectric layer exposing a second portion of the sacrificial layer; 2. The method of claim 1, further comprising removing a remaining portion of the sacrificial layer, thereby forming the cavity directly connecting a lower opening of the cell contact hole and a lower opening of the access contact hole.

3. 2. The method of claim 1 , wherein the dielectric layer is formed by atomic layer deposition of a dielectric on the inner walls of the cell contact holes above the cavity, and the seams in the dielectric layer are formed by the atomic layer deposition of the dielectric.

4. 2. The method of claim 1, wherein the seam is vertically oriented and located adjacent a central region of the dielectric layer between the inner walls of the cell contact hole above the cavity.

5. The dielectric layer is 10. The method of claim 1, comprising at least one material selected from the set of materials consisting of metal oxide, non-conductive metal nitride, silicon oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, silicon oxycarbonitride (SiOCN), carbon doped silicon nitride (SiCN), or silicon boron carbonitride (SiBCN), or any combination of these materials.

6. The dielectric layer is 10. The method of claim 1, comprising at least one material selected from the group of materials consisting of a metal oxide, a non-conductive metal nitride, aluminum (Al), hafnium (Hf), zirconium (Zr), titanium (Ti), silicon (Si), germanium (Ge), copper (Cu), or lanthanum (La).

7. The method of claim 1 further comprising doping the seam with at least one of a mobile element or a non-stoichiometric compound by adding a reactive element.

8. 10. The method of claim 1, further comprising doping the seam with a conductive material selected from the group of conductive materials consisting of copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La).

9. The method of claim 1 , wherein the seam includes a conductive filament extending from the top electrode to the bottom electrode.

10. 2. The method of claim 1, wherein the top electrode, the dielectric layer, the seam including a conductive filament, the bottom electrode, and the target electrical contact together form a resistive memory cell in a semiconductor structure fabricated by the method.

11. 2. The method of claim 1, wherein at least one of the top electrode or the bottom electrode comprises a conductive material selected from the set of conductive materials consisting of copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), nickel (Ni), platinum (Pt), tin (Sn), silver (Ag), gold (Au), a conductive metal compound material, or a conductive alloy comprising at least one of the above conductive materials.

12. A semiconductor structure including at least one memory cell consisting of a transistor and a resistor, A target metal contact; a vertical memory resistor element having first and second electrical contacts and including a vertically oriented seam extending from the first electrical contact to the second electrical contact, one of the first and second electrical contacts being electrically connected to the destination metal contact; the vertical memory resistor element includes a dielectric material formed in a vertically oriented cell contact hole in a dielectric layer of the semiconductor structure to fill the cell contact hole; the vertical seam is surrounded by and in direct contact with the dielectric material forming the vertical memory resistor element, and comprises a conductive material selected from a set of conductive materials consisting of a doped mobile element, a doped non-stoichiometric compound containing a reactive element, or a combination of these conductive materials; Semiconductor structure.

13. 13. The semiconductor structure of claim 12, wherein said vertically oriented seam is located proximate a central region of a length of said vertical memory resistor element that extends from said first electrical contact to said second electrical contact, and said destination metal contact is electrically connected to a memory cell selector device.

14. 13. The semiconductor structure of claim 12 wherein said dielectric material comprises at least one material selected from the set of materials consisting of metal oxides, metal nitrides, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), carbon doped silicon nitride (SiCN), or boron doped silicon carbonitride (SiBCN), or any combination of these materials.

15. 13. The semiconductor structure of claim 12 wherein said vertically oriented seam comprises a single conductive filament extending from said first electrical contact to said second electrical contact.

16. 1. A method of fabricating a semiconductor structure including at least one resistive change memory cell, comprising: A substrate; a gate stack including a gate metal contact; a first source-drain stack including a first source / drain metal contact; a second source-drain stack including a second source / drain metal contact; providing a semiconductor material stack, the substrate supporting the gate stack and the first and second source-drain stacks; depositing an amorphous silicon (a-Si) layer directly on top of a target metal contact electrically connected to at least one of the first source / drain metal contact or the second source / drain metal contact and in contact with the top surface of the target metal contact; depositing an interlevel dielectric (ILD) layer directly on and in contact with an upper surface of the a-Si layer; performing a vertical etch in the ILD layer from a top surface of the ILD layer downward to at least a bottom surface of the ILD layer, the vertical etch forming vertical cell contact holes in the ILD layer and exposing the a-Si layer in the vertical cell contact holes; performing a vertical etch in the ILD layer from a top surface of the ILD layer downward to at least a bottom surface of the ILD layer, the vertical etch forming a vertical access contact hole in the ILD layer exposing the a-Si layer in the vertical access contact hole, the vertical access contact hole being horizontally adjacent to the vertical cell contact hole; performing an isotropic etch to remove the a-Si layer and leave open spaces in the a-Si layer; performing atomic layer deposition of a dielectric material that fills the vertical cell contact hole in the ILD layer and forms a vertical seam about a center of a vertical memory cell formed in the vertical cell contact hole; depositing a conductive material in the vertical access contact hole, the conductive material filling the vertical access contact hole and the open space and forming a bottom electrode directly on and in contact with a top surface of the target metal contact and in contact with a bottom surface of the vertical memory cell and the vertical seam; depositing a conductive material on and in contact with a top surface of the vertical memory cell and the vertical seam to form a top electrode of the vertical memory cell.

17. 17. The method of claim 16, further comprising doping the vertical seams with a conductive material selected from the group of conductive materials consisting of copper (Cu), titanium (Ti), aluminum (Al), hafnium (Hf), or lanthanum (La).

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