Image sensor chip with depth information

Abstract

To provide an image sensor chip that outputs depth information.SOLUTION: An image sensor chip 1 includes an SPAD array 11, a time-digital converter module 13, a first memory circuit 15, and a data processing circuit 17. The SPAD array 11 comprises a plurality of image sensor units IU. Each of the image sensor units IU has a plurality of SPAD units and a determination circuit. Each of the SPAD units outputs a photon detection result within a scan period, and the determination circuit generates an image detection signal S on the basis of the photon detection result. The time-digital converter module generates a plurality of first time data T1 in response to the image detection signal S. The first memory circuit temporarily stores the first time data T1. A data processing unit reads out the first time data T1 from the first memory circuit, and generates a plurality of second time data T2 corresponding to the first time data T1.SELECTED DRAWING: Figure 1

Description

Priority

[0001] This application claims priority from Taiwan Patent Application No. 111140148, filed on October 22, 2022, the entire contents of which are incorporated by reference herein. [Technical field] The present invention relates to an image sensor chip having depth information, more particularly to an image sensor chip comprising a single photon avalanche diode array providing depth information. [Background technology]

[0002] Single-photon detectors are capable of detecting weak optical signals in the environment due to their ability to detect a single photon, and are therefore applied in various fields such as quantum communication, biomedical photoelectric detection, and optical ranging. Currently, there are various single-photon detectors, such as charge-coupled devices (CCDs), quantum dot infrared photodetectors, and single-photon avalanche diode (SPAD) detectors.

[0003] Among these various types of single photon detectors, those using SPADs are especially preferred because they are compatible with the standard manufacturing process of complementary metal oxide semiconductor (CMOS). However, SPADs are sensitive to light and environmental noise, which generally leads to the problem of false detection of photons. Therefore, the detection results usually have poor accuracy. Moreover, if it is necessary to perform wide-range photon detection, a certain number of SPAD units must be equipped on the single photon detector. In that case, a huge amount of data needs to be output, which results in delayed output.

[0004] For the above reasons, there remains a need in the art for an image sensor chip that can accurately detect light to provide highly accurate depth measurements and quickly output the measurement results. Summary of the Invention

[0005] An object of the present invention is to provide an image sensor chip. The image sensor chip includes a single photon avalanche diode (SPAD) array, a time-to-digital converter (TDC) module, a first storage circuit, and a data processing circuit. The SPAD array includes a plurality of image sensor units. Each of the image sensor units includes a plurality of SPAD units and a decision circuit, each of the SPAD units is configured to output a photon detection result within a scan period, and the decision circuit is configured to generate an image detection signal based on the photon detection result. The TDC module is configured to generate a plurality of first time data in response to the image detection signal. The first storage circuit is configured to temporarily store the first time data. The data processing circuit is configured to read the first time data from the first storage circuit, and generate a plurality of second time data respectively corresponding to the first time data.

[0006] In some aspects of the invention, when at least two of the photon detection results of the same image sensor unit indicate that a photon has been detected, the corresponding image detection signal indicates that a photon has been detected.

[0007] In some aspects of the invention, when at least one of the photon detection results of the same image sensor unit indicates that a photon has been detected, the corresponding image detection signal indicates that a photon has been detected.

[0008] In some embodiments of the present invention, each of the decision circuits is configured to select one of a plurality of detection modes based on the control signal, and generate a corresponding image detection signal based on the corresponding photon detection result.

[0009] In some embodiments, the data processing circuit is further configured to sort the first time data, record a first one of the sorted first time data in a first number of bits, and record a difference value between each of the second to Nth sorted first time data and the first time data of the corresponding previous rank in a second number of bits, where the second number of bits is smaller than the first number of bits, and N is a positive integer.

[0010] In some embodiments of the present invention, the image sensor chip further comprises a second storage circuit, and the data processing circuit is further configured to output the compression instruction bit and the second time data to the second storage circuit.

[0011] In some embodiments of the present invention, the TDC module includes a plurality of TDC units, each of which corresponds to an image sensor unit in a one-to-one manner, and each of the TDC units is configured to start counting in response to a wake-up signal, and each of the TDC units is configured to stop counting and generate corresponding first time data in response to a corresponding image detection signal.

[0012] In some embodiments of the present invention, the TDC module includes a plurality of TDC units and a global timing generator. The TDC units correspond one-to-one to the image sensor units. The global timing generator is configured to generate a plurality of oscillating signals delayed by different time lengths in response to a wake-up signal, generate a plurality of first output bits by applying priority encoding to the oscillating signals, and output the first output bits to the TDC units. Each of the TDC units is further configured to start counting in response to a first one of the oscillating signals, and each of the TDC units is further configured to stop counting in response to a corresponding image detection signal and store a plurality of second output bits corresponding to the counting result. Each of the first time data includes a first output bit and a corresponding second output bit.

[0013] In some aspects of the present invention, the TDC module includes a plurality of TDC units and a global timing generator. The TDC units correspond one-to-one to the image sensor units. The global timing generator is configured to generate a plurality of oscillating signals delayed by different time lengths in response to a wake-up signal, generate a plurality of first output bits by applying priority encoding to the oscillating signals, output the first output bits to the TDC units, and start counting in response to a first one of the oscillating signals and output a plurality of second output bits to the TDC units. Each of the TDC units is further configured to stop updating a corresponding second output bit in response to a corresponding image detection signal, and each of the first time data includes a first output bit and a corresponding second output bit.

[0014] In some aspects of the invention, the global timing generator is further configured to adjust the time length in response to an adjustment signal.

[0015] In some embodiments of the present invention, the TDC module is further configured to transmit at least one locking signal, each of the at least one locking signal for temporarily stopping a corresponding image sensor unit from detecting photons.

[0016] In some embodiments of the present invention, the image sensor chip further comprises a clock generator configured to provide a first clock signal having a first frequency to the TDC module and a second clock signal having a second frequency to the data processing circuit.

[0017] The image sensor chip provided by the present invention has a special architecture, and each of the image sensor units in the SPAD array comprises multiple SPAD units. In this architecture, each of the image sensor units can be configured to determine that the image sensor unit detects a photon when at least one, at least two, or at least other number of the SPAD units detect a photon based on the requirements of the actual application. Each of the image sensor units can be configured to determine that the image sensor unit detects a photon when multiple SPAD units detect a photon, so that the misjudgment of the SPAD unit caused by environmental noise can be prevented. In addition, the data processing circuit of the image sensor chip can compress the first time data, so that the present invention can not only reduce the required output bandwidth but also improve the output speed. Therefore, the image sensor chip provided by the present invention can accurately detect light to provide high-precision depth measurement, and can quickly output the measurement result.

[0018] In order to make those skilled in the art fully understand the features of the invention recited in the claims, detailed technical details and preferred embodiments implemented in the present invention are described in the following paragraphs in conjunction with the accompanying drawings. [Brief description of the drawings]

[0019] [Figure 1] FIG. 1 is a schematic diagram of the architecture of an image sensor chip 1 in some embodiments of the present invention.

[0020] [Diagram 2] FIG. 2 is a schematic diagram of an image sensor unit IU in a specific example.

[0021] [Diagram 3] FIG. 3 is a schematic diagram of a determination circuit DU in a specific example.

[0022] [Figure 4] FIG. 4 is a schematic diagram of a decision circuit DU in another embodiment.

[0023] [Diagram 5] FIG. 5 is a schematic diagram of a decision circuit DU in yet another embodiment.

[0024] [Figure 6] FIG. 6 is a schematic diagram of a TDC module TM1 in a specific example.

[0025] [Figure 7] FIG. 7 is a schematic diagram of a TDC module TM2 in another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] In the following description, the image sensor chip with depth information provided by the present invention will be described with reference to specific embodiments. However, these embodiments are not intended to limit the present invention to any specific environment, application, or implementation described in these embodiments. Therefore, the description of these embodiments is for illustration purposes only, and not for limiting the scope of the present invention. Note that in the following embodiments and the accompanying drawings, illustrations of elements that are not related to the present invention are omitted. The dimensions and dimensional scales between individual elements in the accompanying drawings are shown only for the purpose of facilitating illustration and illustration, and are not intended to limit the scope of the present invention. In addition, unless further explained, expressions such as "a", "the" and the like described in the specification and claims include both the singular and plural forms.

[0027] FIG. 1 is a schematic diagram of an architecture of an image sensor chip 1 with depth information in some embodiments of the present invention. The image sensor chip 1 includes a single photon avalanche diode (SPAD) array 11, a time-to-digital converter (TDC) module 13, a first storage circuit 15, and a data processing circuit 17. The SPAD array 11 includes a plurality of image sensor units IU_1, IU_2, . . . , IU_N. It should be noted that the present invention does not limit the number of image sensor units IU_1, IU_2, . . . , IU_N included in the SPAD array 11. Furthermore, according to the requirements of practical applications, the image sensor units IU_1, IU_2, . . . , IU_N included in the SPAD array 11 may be arranged in a one-dimensional array or a two-dimensional array.

[0028] Each of the image sensor units IU_1, IU_2,...,IU_N includes a plurality of SPAD units and a decision circuit. For each of the image sensor units IU_1, IU_2,...,IU_N, each of the SPAD units included in the image sensor unit individually outputs a photon detection result during a scan period (i.e., outputs a signal indicating whether a photon is detected or not), and the decision circuit included in the image sensor unit generates an image detection signal based on the photon detection result. Therefore, during a scan period, the image sensor units IU_1, IU_2,...,IU_N of the SPAD array 11 generate image detection signals S_1, S_2,...,S_N, respectively.

[0029] For better understanding, please refer to the specific example shown in FIG. 2. However, this is not used to limit the scope of the present invention. In this specific example, an image sensor unit IU (representing any of image sensor units IU_1, IU_2, . . . , IU_N) includes four SPAD units SU1, SU2, SU3, SU4 and a decision circuit DU. The SPAD units SU1, SU2, SU3, SU4 have the same circuit configuration. Each of the SPAD units SU1, SU2, SU3, SU4 may include a photodiode, a quench circuit, and an inverter capable of operating under a high voltage, and these circuit elements can be coupled as shown in FIG. 2. A bias voltage V bias In the figure, the SPAD units SU1, SU2, SU3, and SU4 individually detect photons during a scan period and output photon detection results R1, R2, R3, and R4, respectively. The decision circuit DU generates an image detection signal IR based on the photon detection results R1, R2, R3, and R4. The image detection signal IR output by the image sensor unit IU indicates whether the image sensor unit IU detects a photon during the scan period.

[0030] In some embodiments, the decision circuit DU of the image sensor unit IU can be configured to generate an image detection signal indicating that the image sensor unit IU has detected a photon when at least two of the received photon detection results indicate that a photon has been detected. That is, the image sensor unit IU considers itself to have detected a photon when at least two of its SPAD units SU1, SU2, SU3, SU4 are excited. In this way, it is possible to prevent erroneous decision caused by noise interference of the SPAD units.

[0031] For better understanding, please refer to two specific examples shown in FIG. 3 and FIG. 4. However, these are not used to limit the scope of the present invention. FIG. 3 and FIG. 4 show different circuit configurations for the decision circuit DU, both of which are suitable for the image sensor unit IU shown in FIG. 2 (i.e., an embodiment in which the image sensor unit IU includes four SPAD units). In addition, the decision circuit DU shown in FIG. 3 and FIG. 4 is designed to operate under the operating voltage VDD for circuit operation. When two of the photon detection results R1, R2, R3, and R4 indicate that a photon has been detected, the image detection signal IR indicates that the image sensor unit IU has detected a photon. The image detection signal IR shown in FIG. 3 and FIG. 4 can be formulated by the following equations (1) and (2). IR=R1R2+R1R3+R1R4+R2R3+R2R4+R3R4(1) IR=R1(R2+R3+R4)+R2(R3+R4)+R3R4(2)

[0032] The decision circuits DU based on the circuit configurations shown in Figures 3 and 4 generate the same image detection signal IR. However, the decision circuit DU having the circuit configuration shown in Figure 4 has a smaller circuit area than the one employing the circuit configuration shown in Figure 3.

[0033] In some embodiments, the decision circuit of the image sensor unit IU can be configured to generate an image detection signal indicating that the image sensor unit IU has detected a photon when another number (e.g., three or more) of the received photon detection results indicate that the image sensor unit IU has detected a photon. That is, the image sensor unit IU considers itself to have detected a photon when the other number of its own SPAD units are excited. Such a configuration adopts a stricter rule to prevent false decisions caused by noise interference of the SPAD units.

[0034] In some embodiments, the decision circuit of the image sensor unit IU can be configured to generate an image detection signal indicating that the image sensor unit IU has detected a photon when at least one of the received photon detection results indicates that a photon has been detected. That is, the image sensor unit IU considers itself to have detected a photon if at least one of its SPAD units is excited. Such a configuration is suitable for applications that are intended to detect weak light and can tolerate erroneous decisions caused by noise interference of the SPAD units.

[0035] In some embodiments, the image sensor chip 1 can provide different detection modes for selection. In the different detection modes, the image sensor unit IU considers itself to have detected a photon when different numbers of its SPAD units are excited. For example, the image sensor chip 1 can provide a first detection mode and a second detection mode. In the first detection mode, the image sensor unit IU considers itself to have detected a photon when at least one of its SPAD units is excited. For the second detection mode, the image sensor unit IU considers itself to have detected a photon when at least two of its SPAD units are excited. In these embodiments, a decision circuit of the image sensor unit IU selects one of the detection modes based on the control signal, and then generates a corresponding image detection signal based on the corresponding photon detection result.

[0036] For better understanding, please refer to the concrete example shown in FIG. 5. However, this is not used to limit the scope of the present invention. The decision circuit DU shown in FIG. 5 is suitable for the image sensor unit IU shown in FIG. 2 (i.e., an embodiment in which the image sensor unit IU includes four SPAD units). The decision circuit DU includes two sub-circuits DU1 and DU2, where the sub-circuit DU1 corresponds to the first detection mode described above, and the sub-circuit DU2 corresponds to the second detection mode described above. The decision circuit DU selects the first detection mode or the second detection mode based on the control signal EN, and then generates a corresponding image detection signal IR based on the corresponding photon detection results R1, R2, R3, and R4. More specifically, when the control signal EN is enabled, the sub-circuit DU2 operates (i.e., selects the second detection mode), and when the control signal EN is disabled, the sub-circuit DU1 operates (i.e., selects the first detection mode).

[0037] As described above, during a scan period, the image sensor units IU_1, IU_2, . . . , IU_N of the SPAD array 11 generate image detection signals S_1, S_2, . . . , S_N, respectively.

[0038] The TDC module 13 generates a plurality of first time data T1_1, T1_2, . . . T1_N in response to the image detection signals S_1, S_2, . . . S_N, respectively. The first time data T1_1, T1_2, . . . T1_N correspond one-to-one to the image detection signals S_1, S_2, . . . S_N, and therefore the first time data T1_1, T1_2, . . . T1_N correspond one-to-one to the image sensor units IU_1, IU_2, . . . IU_N. Each of the first time data T1_1, T1_2, . . . T1_N represents a time length from the start of a scan period to a time when a corresponding image sensor unit detects a photon (i.e., a time length from when a laser pulse is emitted to when a corresponding reflected laser pulse from an object surface is detected). However, if the corresponding image sensor unit does not detect a photon, the first time data has a value of 0. Each of the first time data T1_1, T1_2,...,T1_N reflects depth information. That is, the depth (i.e., distance) between the image sensor units IU_1, IU_2,...,IU_N and the object surface can be calculated based on the first time data T1_1, T1_2,...,T1_N, respectively. The first time data T1_1, T1_2,...,T1_N generated by the TDC module 13 are temporarily stored in the first storage circuit 15.

[0039] In some embodiments, the TDC module 13 further transmits at least one lock signal, each of which is transmitted to one of the image sensor units IU_1, IU_2, . . . , IU_N, and each of which is for temporarily stopping (i.e., not exciting) the corresponding image sensor unit from detecting photons. More specifically, when the TDC module 13 detects from the image detection signal generated by the image sensor unit during the scanning period that the image sensor unit detects a photon, the TDC module 13 transmits a lock signal to the image sensor unit in a timely manner (e.g., immediately, in a very short time) to temporarily stop the image sensor unit from detecting photons until the arrival of the next scanning period. In this way, for any image sensor unit, only the first arriving photon is detected, and only the first time data of the first arriving photon is recorded by the TDC module 13.

[0040] Please refer to FIG. 1. As an example, the TDC module 13 detects from the image detection signal S_1 that the image sensor unit IU_1 has detected a photon, and as a result, the TDC module 13 transmits a lock signal L_1 to the image sensor unit IU_1, and temporarily stops the image sensor unit IU_1 from detecting photons until the arrival of the next scan period. Also, the TDC module 13 detects from the image detection signal S_N that the image sensor unit IU_N has detected a photon, and as a result, the TDC module 13 transmits a lock signal L_N to the image sensor unit IU_N, and temporarily stops the image sensor unit IU_N from detecting photons until the arrival of the next scan period. Note that the time when the TDC module 13 transmits the lock signal L_1 and the time when the TDC module 13 transmits the lock signal L_N may be different or the same.

[0041] The data processing circuit 17 reads out the first time data T1_1, T1_2, ..., T1_N from the first memory circuit 15, generates a plurality of second time data T2_1, T2_2, ..., T2_N corresponding respectively to the first time data T1_1, T1_2, ..., T1_N, and outputs these second time data T2_1, T2_2, ..., T2_N.

[0042] In some embodiments, the image sensor chip 1 has sufficient output bandwidth, and therefore the data processing circuit 17 does not compress the first time data T1_1, T1_2,...,T1_N. In these embodiments, the second time data T2_1, T2_2,...,T2_N are essentially equivalent to the first time data T1_1, T1_2,...,T1_N, respectively.

[0043] In some embodiments, the image sensor chip 1 compresses the first time data T1_1, T1_2, ..., T1_N to generate second time data T2_1, T2_2, ..., T2_N in order to reduce the required output bandwidth.

[0044] In some embodiments, the data processing circuit 17 sorts the first time data T1_1, T1_2, ..., T1_N from largest to smallest, records the first of the sorted first time data in a first number of bits, and records the difference value between each of the second to Nth sorted first time data and the first time data of the corresponding preceding order in a second number of bits (i.e., records the difference value between the second of the sorted first time data and the first of the sorted first time data in a second number of bits, records the difference value between the third of the sorted first time data and the second of the sorted first time data in a second number of bits, and so on). The second number of bits is smaller than the first number of bits, and N is a positive integer. The first time data recorded in the first number of bits and the (N-1) difference values ​​(each recorded in the second number of bits) constitute second time data T2_1, T2_2, . . . , T2_N.

[0045] In some embodiments, the image sensor chip 1 can provide two output modes, the first output mode being a compressed mode and the second output mode being a non-compressed mode. In these embodiments, the data processing circuit 17 further receives a compression setting CS. The compression setting CS is used to instruct the data processing circuit 17 to apply the first output mode (i.e., compression of the first time data) or the second output mode (i.e., non-compression of the first time data). The data processing circuit 17 further outputs a compression indication bit (not shown) indicating whether the second time data T2_1, T2_2, . . . , T2_N is compressed or not, so that the receiving side can correctly read the second time data T2_1, T2_2, . . . , T2_N in a corresponding procedure.

[0046] In some embodiments, the image sensor chip 1 further includes a second storage circuit 19. In these embodiments, the second storage circuit 19 temporarily stores and outputs the second time data T2_1, T2_2, . . . , T2_N. The second storage circuit 19 also stores a compression indication bit (if present).

[0047] Here, the TDC module 13 included in the image sensor chip 1 will be described in detail.

[0048] In some embodiments, the TDC module 13 includes a plurality of TDC units (not shown), which correspond one-to-one to the image sensor units IU_1, IU_2,..., IU_N. Each of the TDC units starts counting in response to a wake-up signal, and each of the TDC units stops counting in response to a corresponding image detection signal and generates corresponding first time data.

[0049] In some embodiments, the TDC module 13 includes a plurality of TDC units and a global timing generator. The TDC units correspond one-to-one to the image sensor units IU_1, IU_2, . . . , IU_N. The global timing generator is responsive to a start signal ST to generate one or more oscillating signals delayed by different time lengths. In one specific example, each of the oscillating signals is delayed by a positive integer multiple of 50 picoseconds, which represents the time resolution of the first time data T1_1, T1_2, . . . , T1_N generated by the TDC module 13. The global timing generator also generates a plurality of first output bits by applying a priority encoding to the oscillating signals (e.g., applying a priority encoding to a binary sequence 00001111111111112 to generate a corresponding hexadecimal sequence 0101 Hand outputs the first output bits to the TDC units. Further, each of the TDC units starts counting in response to a first one of the oscillation signals, and each of the TDC units stops counting in response to a corresponding image detection signal, and stores a plurality of second output bits corresponding to the counting results. Each of the first time data includes the first output bit and a corresponding second output bit. In some embodiments, the global timing generator further adjusts the above-mentioned time length in response to an adjustment signal.

[0050] For better understanding, please refer to the concrete example shown in Figure 6, which is not used to limit the scope of the present invention. The TDC module TM1 shown in Figure 6 includes a global timing generator GT1 and N TDC units TU1 (in Figure 6, the symbol xN represents N the same).

[0051] Here, the global timing generator GT1 will be described. The multiplexer 601 is configured to receive an adjustment signal PVT and a start signal ST. The adjustment signal PVT is used in a test phase for time length adjustment used by the 16-phase ring oscillator 607 to delay the oscillation signal so that the time length approaches a predetermined value (e.g., 50 picoseconds). The activation signal ST is used in an operation phase to indicate that a laser pulse is activated (e.g., if a laser pulse is generated every 200 nanoseconds, the multiplexer 601 will receive the activation signal ST every 200 nanoseconds). The selection signal SEL is used to determine whether the adjustment signal PVT or the start signal ST may pass through the multiplexer 601. The pre-processing circuit 603 is configured to receive a reset signal RST, which is used to reset the 16-phase ring oscillator 607 in the global timing generator GT1 to zero. The reset signal RST is also provided to the 8-bit counters 615 and registers 619 in all TDC units TU1 to reset them to zero. The pre-processing circuit 603 is configured to receive the output signals from the multiplexer 601 and send the output signals to a buffer 605 to increase their driving power. If the output signals received by the pre-processing circuit 603 from the multiplexer 601 are derived from a start-up signal ST, the signal output by the buffer 605 is the start-up signal STR with increased driving power. The start-up signal STR is supplied to a 16-phase ring oscillator 607.

[0052] The 16-phase ring oscillator 607 is configured to receive a delay control signal CT, which is used by the 16-phase ring oscillator 607 to achieve a required time resolution. The delay control signal CT can have different bit numbers in various embodiments depending on the target time resolution to be achieved. The delay control signal CT is used to adjust the delay unit amount of the 16-phase ring oscillator 607 (e.g., to control the charging time and / or discharging time by current), and the 16 phases of the 16-phase ring oscillator 607 perform different degrees of delay (e.g., 50 picosecond delay, 100 picosecond delay, etc.) on the activation signal STR, resulting in 16 oscillation signals D[15:0] delayed by different time lengths. The 16 oscillation signals D[15:0] are then passed to 16 buffers 609 (in FIG. 6, the symbol ×16 is used to indicate the presence of 16 buffers 609) respectively to increase the driving power, and 16 oscillation signals R[15:0] are obtained.

[0053] The priority encoding circuit 67 of the global timing generator GT1 is configured to generate four first output bits F[3:0] by applying priority encoding to the 16 oscillation signals R[15:0]. More specifically, the priority encoding circuit 67 includes an XOR operator 671, 15 buffers 673 (in FIG. 6, the symbol ×15 is used to indicate that there are 15 buffers 673), a 16-4 encoder 675, and four buffers 677 (in FIG. 6, the symbol ×4 is used to indicate that there are four buffers 677), and the 15 buffers 673 and the four buffers 677 are used to increase the driving power of the corresponding input signals. The 16 oscillation signals R[15:0] are processed in order by the XOR operator 671, the buffers 673, the 16-4 encoder 675, and the buffers 677, resulting in four first output bits F[3:0]. By applying priority encoding, the 16 signal lines are converted into 4 output lines, thereby preventing interference between high frequency signals. The first output bits F[3:0] are provided to the registers 619 of the N TDC units TU1.

[0054] As described above, the TDC module TM1 includes N TDC units TU1, and the symbol ×N in FIG. 6 indicates that there are N identical units. Here, one TDC unit TU1 is used as an example for explanation. The first oscillation signal R[0] of the 16 oscillation signals R[15:0] is supplied to the buffer 613 of the TDC section TU1 to increase the driving power, and is then supplied to the 8-bit counter 615 to start counting appropriately. The TDC unit TU1 stops counting in response to the corresponding image detection signal S (i.e., one of the above-mentioned image detection signals S_1, S_2, . . . , S_N), and stores a plurality of second output bits C[7:0] corresponding to the count result in the register 619. The 8-bit counter 615 operates by being supplied with only the oscillation signal R[0], so that signal interference due to excessive wiring can be prevented.

[0055] For each TDC unit TU1, the first output bits F[3:0] and its second output bits C[7:0] form corresponding first time data, with the first output bits F[3:0] being the lower bits (i.e., the finer granularity part) of the first time data and the second output bits C[7:0] being the upper bits (i.e., the coarser granularity part) of the first time data.

[0056] Note that the buffers 605, 609, 613, 617, 673, and 677 are all intended to increase the driving power of the corresponding signals, and may be omitted depending on the actual situation. Also, the number of phases of the 16-phase ring oscillator 607 and the number of bits of the 8-bit counter 615 do not limit the scope of the present invention. In other embodiments, the number of phases of the ring oscillator and / or the number of bits of the counter can be different values, in which case the number of corresponding output signals, the number of buffers, the number of input signals of the encoder, and the number of output signals of the encoder will change accordingly.

[0057] In some embodiments, the TDC module 13 includes a plurality of TDC units and a global timing generator. The TDC units correspond one-to-one to the image sensor units IU_1, IU_2, . . . , IU_N. The global timing generator generates a plurality of oscillating signals with different time lengths in response to a start signal ST, applies priority encoding to the oscillating signals to generate a plurality of first output bits, outputs the first output bits to the TDC units, starts counting in response to a first one of the oscillating signals, and outputs a plurality of second output bits to the TDC units. Each of the TDC units stops updating the corresponding second output bit in response to a corresponding image detection signal. Each of the first time data includes a first output bit and a corresponding second output bit.

[0058] For better understanding, please refer to the concrete example shown in FIG. 7. However, this is not used to limit the scope of the present invention. The TDC module TM2 shown in FIG. 7 includes a global timing generator GT2 and N TDC units TU2 (in FIG. 7, the symbol ×N represents N of the same). Compared with the example shown in FIG. 6, the global timing generator GT2 includes not only a multiplexer 601, a pre-processing circuit 603, a buffer 605, a 16-phase ring oscillator 607, 16 buffers 609, and a priority encoding circuit 67, but also a buffer 613, an 8-bit counter 615, and a buffer 617. Each of the N TDC units TU2 includes a register 619, but does not have a buffer 613, an 8-bit counter 615, and a buffer 617. Based on the description of FIG. 6, a person skilled in the art should understand how the TDC module TM2 operates, and therefore, detailed description will not be repeated here. In the case of the TDC module TM2, the buffer 613, the 8-bit counter 615, and the buffer 617 are incorporated in the global timing generator GT2. Therefore, the circuit area of ​​the TDC module TM2 is smaller than that of the TDC module TM1.

[0059] In some embodiments, the image sensor chip 1 further comprises a clock generator 12. For example, the clock generator 12 can be a multiplying delay locked loop (MDLL). The clock generator 12 is configured to provide a first clock signal CLK1 having a first frequency to the TDC module 13 and a second clock signal CLK2 having a second frequency to the data processing circuit 17 so that the TDC module 13 and the data processing circuit 17 can operate.

[0060] It should be recognized that in the present specification and claims, some terms (e.g., memory circuit, time data, number of bits, output bit, detection mode, output mode, frequency, clock signal) are preceded by "first" or "second". Please note that "first" and "second" are used only for the purpose of distinguishing different terms. If the order of these terms is not specified or cannot be derived from the context, the order of these terms is not limited by the preceding "first" and "second".

[0061] The image sensor chip provided by the present invention has a special architecture, and each of the image sensor units in the SPAD array comprises multiple SPAD units. In this architecture, each of the image sensor units can be configured to determine that the image sensor unit detects a photon when at least one, at least two, or at least other number of the SPAD units detect a photon based on the requirements of the actual application. Each of the image sensor units can be configured to determine that the image sensor unit detects a photon when multiple SPAD units detect a photon, so that the misjudgment of the SPAD unit caused by environmental noise can be prevented. In addition, the data processing circuit of the image sensor chip can compress the first time data, so that the present invention can not only reduce the required output bandwidth but also improve the output speed. Therefore, the image sensor chip provided by the present invention can accurately detect light to provide high-precision depth measurement, and can quickly output the measurement result.

[0062] The above disclosure relates to detailed technical contents and features of the invention. Those skilled in the art can make various modifications and substitutions based on the disclosure and suggestions of the invention described without departing from the features of the invention. However, such modifications and substitutions are not fully disclosed in the above description, but are substantially covered in the appended claims.

Claims

1. A plurality of image sensor units, each of the image sensor units comprising: a plurality of SPAD units, each configured to output a photon detection result within a scan period; and a single-photon avalanche diode (SPAD) array including a decision circuit configured to generate an image detection signal indicating that the image sensor unit detects a photon based on the photon detection result; a time-to-digital converter (TDC) module configured to generate a plurality of first time data in response to the image detection signal, the first time data being a time length from a start of a scan period to a time when each of the image sensor units detects a photon; a first storage circuit configured to temporarily store the first time data; a data processing circuit configured to read the first time data from the first storage circuit and generate a plurality of second time data each corresponding to the first time data. Image sensor chip.

2. The image sensor chip of claim 1 , wherein when at least two of the photon detection results of the same image sensor unit indicate that a photon has been detected, the corresponding image detection signal indicates that a photon has been detected.

3. The image sensor chip of claim 1 , wherein when at least one of the photon detection results of the same image sensor unit indicates that a photon has been detected, the corresponding image detection signal indicates that a photon has been detected.

4. 2. The image sensor chip of claim 1, wherein each of the decision circuits is configured to select one of a plurality of detection modes based on a control signal, and generate a corresponding image detection signal based on a corresponding photon detection result.

5. 2. The image sensor chip of claim 1, wherein the data processing circuit is further configured to sort the first time data, record a first one of the sorted first time data in a first number of bits, and record a difference value between each of the sorted first time data from a second one to an Nth one and a corresponding first time data of a previous rank in a second number of bits, wherein the second number of bits is smaller than the first number of bits, and N is a positive integer.

6. 6. The image sensor chip according to claim 5, wherein the data processing circuit is further configured to output a compression instruction bit and the second time data.

7. 7. The image sensor chip of claim 6, further comprising a second storage circuit configured to temporarily store the compression indication bit and the second time data.

8. The TDC module comprises a plurality of TDC units; The TDC units correspond one-to-one to the image sensor units, and each of the TDC units is configured to start counting in response to a start signal, and each of the TDC units is configured to stop counting and generate the corresponding first time data in response to a corresponding image detection signal.

2. The image sensor chip according to claim 1.

9. The TDC module includes: a plurality of TDC units in one-to-one correspondence with the image sensor units; a global timing generator configured to generate a plurality of oscillating signals delayed by different amounts of time in response to a wake-up signal, generate a plurality of first output bits by applying priority encoding to the oscillating signals, and output the first output bits to the TDC unit; Each of the TDC units is further configured to start counting in response to a first of the oscillator signals, and each of the TDC units is further configured to stop counting in response to a corresponding image detection signal and store a second plurality of output bits corresponding to a count result; each of the first time data includes the first output bit and a corresponding second output bit; 2. The image sensor chip according to claim 1.

10. The image sensor chip of claim 9 , wherein the global timing generator is further configured to adjust the time length in response to an adjustment signal.

11. The TDC module includes: a plurality of TDC units in one-to-one correspondence with the image sensor units; a global timing generator configured to generate a plurality of oscillating signals delayed by different amounts of time in response to a wake-up signal, generate a plurality of first output bits by applying priority encoding to the oscillating signals, output the first output bits to the TDC unit, and initiate a count in response to a first of the oscillating signals and output a plurality of second output bits to the TDC unit; Each of the TDC units is further configured to stop updating a corresponding one of the second output bits in response to a corresponding one of the image detection signals, and each of the first time data includes the first output bit and a corresponding one of the second output bits.

2. The image sensor chip according to claim 1.

12. The image sensor chip of claim 11 , wherein the global timing generator is further configured to adjust the time length in response to an adjustment signal.

13. 2. The image sensor chip of claim 1, wherein the TDC module is further configured to send at least one lock signal, each of the at least one lock signal for temporarily stopping a corresponding image sensor unit from detecting photons.

14. 2. The image sensor chip of claim 1, further comprising a clock generator configured to supply a first clock signal having a first frequency to the TDC module and to supply a second clock signal having a second frequency to the data processing circuit.

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