SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Abstract

To provide a semiconductor device that achieves miniaturization while maintaining high reliability and good electrical characteristics using an oxide semiconductor.SOLUTION: A semiconductor device includes: a first protective insulating layer 111; an oxide semiconductor layer 102 on the first protective insulating layer; a pair of electrodes 103 electrically connected to the oxide semiconductor layer; a gate insulating layer 104 located on the pair of electrodes and overlapping with the oxide semiconductor layer; a gate electrode 105 overlapping with the oxide semiconductor layer via the gate insulating layer; and a second protective insulating layer 112 covering the pair of electrodes and the gate electrode. The first protective insulating layer and the second protective insulating layer include aluminum oxide films having oxygen excess regions, and have regions in contact with each other in a region where the pair of electrodes and the gate electrode are not present.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general, including transistors, semiconductor circuits, arithmetic units, memory devices, imaging devices, and electro-optical devices. Equipment, power generation equipment (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic equipment are semiconductor devices. This is one aspect of the arrangement. [Background technology]

[0003] A technology for constructing transistors using a semiconductor thin film formed on a substrate with an insulating surface. The transistor is being used in integrated circuits (ICs) and image display devices (not simply called display devices). Semiconductors that can be used in transistors are widely used in electronic devices such as Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are in the spotlight.

[0004] For example, zinc oxide and In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2).

[0005] In addition, in order to improve the carrier mobility of transistors, the electron affinity (or conduction band A technique for stacking oxide semiconductor layers with different low-end states has been disclosed (Patent Document 3 and (See Patent Document 4). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-124360 A [Patent Document 4] JP 2011-138934 A Summary of the Invention [Problem to be solved by the invention]

[0007] In a semiconductor device including a transistor using an oxide semiconductor, high reliability can be achieved by This is an important issue for commercialization. In particular, fluctuations and deterioration of electrical characteristics of semiconductor devices can lead to low reliability. This is one of the factors that leads to a decline.

[0008] In view of the above problems, one embodiment of the present invention is a semiconductor device including an oxide semiconductor. An object of the present invention is to provide a highly reliable semiconductor device.

[0009] In addition, transistors are becoming faster, more power-efficient, less expensive, and more highly integrated. In order to achieve this, miniaturization of transistors is essential.

[0010] In view of the above, one embodiment of the present invention is a semiconductor device including an oxide semiconductor, which has good electrical characteristics. It is an object of the present invention to provide a semiconductor device that achieves miniaturization while maintaining performance.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary to solve all of these problems. Problems other than those mentioned above are not necessarily solved. It will become clear from the description of the specification, etc., and problems other than those mentioned above will not be identified from the description of the specification, etc. It is possible to extract [Means for solving the problem]

[0012] A semiconductor device according to one embodiment of the present invention includes a first protective insulating layer and an oxide film formed on the first protective insulating layer. A semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, and a source a gate insulating layer located on the source electrode and the drain electrode and overlapping the oxide semiconductor layer; A gate electrode overlapping the oxide semiconductor layer via an insulating layer, a source electrode, a drain electrode, and and a second protective insulating layer covering the gate electrode. The protective insulating layer includes an aluminum oxide film having an oxygen excess region, and the source electrode, the drain electrode, The gate electrode and the gate electrode are in contact with each other in a region where the gate electrode and the gate electrode are not present.

[0013] The gate electrode covers the upper surface and the side surface of the oxide semiconductor layer via a gate insulating layer. It is preferable to have such a configuration.

[0014] The oxide semiconductor layer has a thickness of 0.1 to 10 times the channel width. It is preferable that there is.

[0015] In the above, an oxide semiconductor insulating film is provided between the first protective insulating layer and the oxide semiconductor layer. a first oxide layer including at least one of the metal elements of the oxide semiconductor layer; The oxide semiconductor layer is provided between the gate insulating layer and the gate insulating layer, and the oxide semiconductor layer includes at least one metal element. and a second oxide layer formed on the first oxide layer. The conduction band minimum energy of the oxide layer is lower than that of the oxide semiconductor layer. It is preferable that the potential be in the range of 0.05 eV to 2 eV, which is close to the vacuum level.

[0016] The upper surface of the second oxide layer is connected to the lower surface of the source electrode, the lower surface of the drain electrode, and the gate Alternatively, the insulating layer 14 may be configured to be in contact with the lower surface of the insulating layer 14 .

[0017] Alternatively, the lower surface of the second oxide layer is in contact with the upper surface of the source electrode, the upper surface of the drain electrode, and The upper surface of the oxide semiconductor layer in a region where the source electrode and the drain electrode are not provided and It may be configured to be in contact with the side surface.

[0018] A semiconductor device according to another embodiment of the present invention includes an insulating layer having a groove, and a side surface and a A first protective insulating layer is provided so as to cover the bottom surface, and a groove is embedded in the first protective insulating layer. and a source electrode and a gate electrode electrically connected to the oxide semiconductor layer. a source electrode and a drain electrode, and a gate insulating layer positioned on the source electrode and the drain electrode and overlapping the oxide semiconductor layer. A gate insulating layer, a gate electrode overlapping the oxide semiconductor layer via the gate insulating layer, and a source electrode and a second protective insulating layer covering the first electrode, the drain electrode, and the gate electrode. Furthermore, the first protective insulating layer and the second protective insulating layer are made of aluminum oxide having an oxygen excess region. In the region including the tungsten film and not including the source electrode, the drain electrode, and the gate electrode, The electrodes have a region where they contact each other. Effect of the Invention

[0019] According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor has high reliability. A conductor device can be provided.

[0020] According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor has good electrical conductivity. It is possible to provide a semiconductor device that achieves miniaturization while maintaining thermal properties. [Brief description of the drawings]

[0021] [Figure 1] 1 shows a configuration example of a semiconductor device according to an embodiment. [Diagram 2] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Diagram 3] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 4] 1 shows a configuration example of a semiconductor device according to an embodiment. [Diagram 5] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 6] 1A to 1C illustrate an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 7] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 8] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 9] 1A to 1C are a configuration example and a circuit diagram of a semiconductor device according to an embodiment; [Figure 10] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 11] FIG. 2 is a diagram illustrating a band diagram according to an embodiment. [Figure 12] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 13] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 14] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 15] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 16] 1A to 1C are a configuration example and a circuit diagram of a semiconductor device according to an embodiment; [Figure 17] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 18] 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment; [Figure 19] 1 is a circuit diagram of a semiconductor device according to an embodiment. [Figure 20] 1 is a block diagram of a semiconductor device according to an embodiment. [Figure 21] 1 is a circuit diagram illustrating a memory device according to an embodiment. [Figure 22] 1 is an electronic device according to an embodiment. [Figure 23] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 24] 1A and 1B are diagrams showing a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. [Diagram 25] An example of structural analysis using transmission electron diffraction measurements, and a planar TEM image. [Figure 26] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 27] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 28] 1 shows a configuration example of a semiconductor device according to an embodiment. [Figure 29] 1 shows a configuration example of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention can be realized by the following embodiments. The present disclosure should not be construed as being limited to the contents of the preceding paragraph.

[0023] In the configuration of the invention described below, the same parts or parts having similar functions are The same reference numerals are used in common between different drawings, and the repeated explanations are omitted. When referring to a function, the hatch pattern may be the same and no particular symbol may be used.

[0024] In each figure described in this specification, the size, layer thickness, or area of ​​each component is indicated by the following formula: The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0025] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. The numbers are added for the purpose of convenience and are not intended to be limiting.

[0026] A transistor is a type of semiconductor device that controls the amplification of current or voltage and the conduction or non-conduction of electricity. In this specification, the transistor can realize a switching operation that controls the , IGFET(Insulated Gate Field Effect Trans istor) and thin film transistor (TFT: Thin Film Transistor ).

[0027] (Embodiment 1) In this embodiment, examples of the structure of a transistor and a semiconductor device according to one embodiment of the present invention will be described. An example of a manufacturing method thereof will be described with reference to the drawings.

[0028] When a transistor is manufactured using an oxide semiconductor, a carrier source of the oxide semiconductor One of the causes is oxygen vacancy. If there are many oxygen vacancies in the conductor, electrons are generated in the channel formation region, Normally-on transistors, increased leakage current, and threshold voltage fluctuations due to stress application This can cause defects in electrical characteristics such as shift.

[0029] In addition, in the oxide semiconductor layer, hydrogen, silicon, nitrogen, carbon, and a metal element other than the main component For example, some of the hydrogen in the oxide semiconductor layer forms a donor level, and Increase carrier density.

[0030] Therefore, in order to obtain stable electrical characteristics in a semiconductor device using an oxide semiconductor, By supplying sufficient oxygen to the oxide semiconductor layer, oxygen vacancies are reduced and impurities such as hydrogen are removed. It is necessary to take measures to reduce the concentration of these substances.

[0031] In view of this, in a semiconductor device according to one embodiment of the present invention, an oxygen excess region is provided so as to surround an oxide semiconductor layer. A protective insulating layer including an aluminum oxide film having the above structure is provided, and a channel is formed from the protective insulating layer. By supplying oxygen to the region, oxygen vacancies that may be formed in the channel formation region are compensated for. In addition, the protective insulating layer suppresses the release of oxygen from the oxide semiconductor layer and suppresses the formation of oxygen vacancies. do.

[0032] In one embodiment of the present invention, as a protective insulating layer for supplying oxygen to a channel formation region, In the above, an insulating layer having an aluminum oxide film containing excess oxygen is applied. The excess oxygen is, for example, oxygen contained in excess of the stoichiometric composition, or oxygen contained in excess of the stoichiometric composition when fabricating a semiconductor device. This refers to the oxygen that can be released by heating at a temperature equal to or lower than the heat treatment temperature applied during the manufacturing process. As an aluminum oxide film containing excess oxygen, AlO x (x is greater than 3 / 2) Use a membrane The excess oxygen contained in the aluminum oxide film is released by heating, and the oxide Since it is possible to supply the insulating layer including such an aluminum oxide film to the semiconductor layer, By providing the layers on the upper and lower sides of the oxide semiconductor layer, oxygen can be effectively supplied to the channel formation region. can be supplied.

[0033] The aluminum oxide film containing excess oxygen is formed by sputtering in an atmosphere containing oxygen, for example. It can be formed by film formation using a ring method or the like.

[0034] The aluminum oxide film can be used as an insulating layer such as a silicon oxide film or a silicon oxynitride film. The insulating layer has a lower permeability to oxygen and hydrogen than the oxide semiconductor layer. The aluminum oxide film is an insulating layer having a barrier property against oxygen and hydrogen. By providing an insulating layer containing It is possible to suppress the formation of hydrogen and to suppress the inclusion of hydrogen or hydrogen compounds.

[0035] In one embodiment of the present invention, the protective insulating layers provided above and below the oxide semiconductor layer are an oxide semiconductor layer; and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; In the region where no regions are present, the regions are in contact with each other. The semiconductor device has a structure in which an aluminum oxide film is provided so as to enclose an oxide semiconductor layer. With such a structure, the front channel side and the back channel side of the oxide semiconductor layer are In addition to the channel-side interface, oxygen desorption and / or hydrogen desorption on the side of the oxide semiconductor layer It is possible to suppress the inclusion of impurities and to supply oxygen. This suppresses fluctuations in the electrical characteristics of transistors in which channels are formed in the conductor layer, resulting in highly reliable semiconductors. It is possible to form a conductor device.

[0036] Therefore, in the semiconductor device of one embodiment of the present invention, oxygen vacancies in the channel formation region can be reduced. As a result, a highly reliable semiconductor having good electrical characteristics and suppressing fluctuations in the electrical characteristics is obtained. The device can be realized.

[0037] The effect of the configuration according to one aspect of the present invention can be explained, for example, as follows.

[0038] A semiconductor device according to one embodiment of the present invention includes an insulating layer including an aluminum oxide film having excess oxygen. The aluminum oxide film is provided so as to surround the oxide semiconductor layer. An oxide semiconductor layer in which a channel is formed by heat treatment in a manufacturing process of a semiconductor device Furthermore, the aluminum oxide film has a barrier property against oxygen and hydrogen. Therefore, oxygen is released from the oxide semiconductor layer surrounded by the insulating layer including the aluminum oxide film, and In addition, it is possible to prevent impurities such as hydrogen from being mixed into the oxide semiconductor layer. The oxide semiconductor layer is supplied and the inclusion of impurities such as hydrogen is suppressed. The oxide semiconductor layer is an oxide semiconductor layer.

[0039] In the above semiconductor device, a gate insulating layer is provided between the oxide semiconductor layer and the gate insulating layer. The gate electrode is provided so as to overlap with the side surface and the top surface of the channel formation region of the oxide semiconductor layer. In this structure, the oxide semiconductor layer is preferably Since the electric field is applied from the direction perpendicular to the top surface, the threshold voltage of the transistor is effectively controlled. It is possible to control the gain and improve the subthreshold coefficient (also called the S value).

[0040] Here, in order to achieve high density (high integration) of semiconductor devices, On the other hand, miniaturization of transistors leads to deterioration of their electrical characteristics. It is known that this may be the case.

[0041] For example, in silicon transistors, shortening the channel length leads to subthreshold It is known that short channel effects such as deterioration of the stress coefficient (S value) and fluctuation of the threshold voltage occur. It is being done.

[0042] However, a transistor using an oxide semiconductor has a high-temperature property that uses electrons as the majority carrier. Since it is an inversion type transistor, it has a short channel compared to silicon inversion type transistors. Drain-Induced Barrier Lowering (DIBL) occurs. A transistor using an oxide semiconductor is said to be resistant to the short-channel effect. This can also be rephrased.

[0043] Furthermore, there is concern that the on-state current may decrease if the channel width of the transistor is reduced. To improve flow, the active layer is thickened so that channels are formed on the sides of the active layer. A method is also known, but the surface area on which the channels are formed is increased, so the channel formation area The scattering of carriers increases at the interface between the gate insulating layer and the semiconductor region, so a sufficient improvement in on-current cannot be observed. It’s not easy to get into.

[0044] However, in the transistor according to one embodiment of the present invention, the oxide layer in which the channel is formed is The insulating layer includes an aluminum oxide film containing excess oxygen, and the insulating layer surrounds the semiconductor layer. By this, excess oxygen contained in the aluminum oxide film is supplied to the oxide semiconductor layer, and This can suppress release of oxygen from the oxide semiconductor layer and suppress the inclusion of impurities such as hydrogen. For the oxide semiconductor layer, oxygen vacancies and hydrogen are factors that generate carriers, so excess oxygen By providing an aluminum oxide film containing Possible scattering of carriers can be suppressed.

[0045] Therefore, even if the channel width is reduced, the thickness of the oxide semiconductor layer can be increased. By increasing the surface area overlapping with the gate electrode, the on-current can be improved sufficiently. In order to apply a sufficient electric field from the gate electrode to the side of the oxide semiconductor layer, The thickness of the oxide semiconductor layer is preferably equal to or larger than the channel width.

[0046] In addition, a metal oxide layer is provided in contact with the oxide semiconductor layer. By providing an oxide layer formed of the above-mentioned oxide, the above-mentioned scattering of carriers can be further suppressed. Therefore, it is effective.

[0047] When the channel length and the channel width of a transistor are reduced, a resist mask is used. The end faces of wiring, semiconductor layers, etc. processed by this method may be rounded (have curved surfaces). A thin insulating layer (for example, a gate insulating layer) is formed so as to cover the oxide semiconductor layer. If the thickness is too small, the coating property may be reduced, resulting in poor shape and making it difficult to obtain stable electrical characteristics. However, since the end face of the oxide semiconductor layer has a curved surface, the insulating film provided on the oxide semiconductor layer can be easily formed. This is preferable since it is possible to improve the coverage of the layer.

[0048] In addition, part of hydrogen in the oxide semiconductor layer is captured by oxygen vacancies, causing the oxide semiconductor layer to become an n-type As a result, the Fermi level (Ef) approaches the conduction band edge (Ec). The oxide semiconductor layer included in the On the other hand, when the oxide semiconductor layer is made intrinsic or substantially intrinsic, The Fermi energy of the oxide semiconductor layer is the mid-gap (energy In this case, the oxide semiconductor There is concern that a decrease in the number of carriers contained in the semiconductor layer may result in a decrease in field effect mobility.

[0049] However, in the transistor of one embodiment of the present invention, In addition to the gate field from the top, a gate field is applied from the side. A gate electric field is applied to the entire semiconductor layer, and the current flows through the bulk of the oxide semiconductor layer. This allows the suppression of fluctuations in electrical characteristics by using highly pure intrinsic material while also reducing the This makes it possible to improve the field effect mobility of the transistor.

[0050] More specifically, for example, the following configuration can be adopted.

[0051] [Configuration example 1] FIG. 1A is a schematic top view of a transistor 100 illustrated in this configuration example. (B) and (C) are schematic cross-sectional views taken along lines AB and CD in FIG. 1(A), respectively. In FIG. 1(A), some components are not shown for clarity.

[0052] The transistor 100 is provided on a substrate 101, and includes an island-shaped semiconductor layer 102 and a semiconductor layer A pair of electrodes 103 electrically connected to the semiconductor layer 102 and a semiconductor layer A gate insulating layer 104 overlapping the semiconductor layer 102 and a semiconductor layer 102 disposed on the gate insulating layer 104. and a gate electrode 105 overlapping the gate electrode 103 .

[0053] In addition, a first protective insulating layer 111 is provided between the substrate 101 and the semiconductor layer 102. In addition, a second protective insulating layer 112 is formed on the pair of electrodes 103 and the gate electrode 105. Furthermore, the first protective insulating layer 111 and the second protective insulating layer 112 are a pair of The electrode 103 and the gate electrode 105 are provided in contact with each other in a region where they are not provided. It is being done.

[0054] The semiconductor layer 102 includes an oxide semiconductor. It is preferable that the alloy contains aluminum (In) or zinc (Zn). Alternatively, the alloy contains both In and Zn. More preferably, In-M-Zn oxide (wherein M is Al, Ti, Ga, Metals such as Ge, Y, Zr, Sn, La, Ce or Hf are included.

[0055] One of the pair of electrodes 103 functions as a source electrode of the transistor 100, and the other In FIG. 1B, the pair of electrodes 103 each function as a drain electrode. The conductive layer 102 is provided in contact with the upper surface and the side surfaces.

[0056] The gate electrode 105 is connected to the upper surface and the side surfaces of the semiconductor layer 102 via the gate insulating layer 104. It is set up in such a way that it surrounds it.

[0057] Here, the channel length (L length) of a transistor is the distance between the opposing source and drain The channel width (W length) of a transistor is the width in the direction perpendicular to the channel length direction. The width of the semiconductor layer in the transistor is the width of the source electrode, drain electrode, and gate electrode. Depending on the shape of the electrode and semiconductor layer, the channel length and width may vary depending on the region (position). In that case, the average or minimum value of these may be used as the transition time. It can be applied as the channel length or channel width of a gate electrode.

[0058] The gate electrode 105 is provided so as to surround the side surface of the semiconductor layer 102. The side surface of the semiconductor layer 102 can also function as a channel formation region. The thickness of the semiconductor layer 102 is set to 0.05 times or more and 20 times or less, preferably, to the channel width. It is preferable that the ratio is 0.1 to 10. By making the shape like this, Even if the width of the panel is reduced, the decrease in on-current is suppressed, enabling finer and faster operation. This makes it possible to realize a transistor that can

[0059] In this manner, the gate electrode surrounds the upper and side surfaces of the semiconductor layer of the transistor. By actively using the channel formed near the side of the semiconductor layer, the on-state current can be reduced. The transistor structure with enhanced current is called the Surrounded Channel (SC This can also be called a channel structure.

[0060] The first protective insulating layer 111 and the second protective insulating layer 112 have an oxygen excess region, and An insulating material that has the function of suppressing the diffusion of oxygen (also called oxygen blocking properties) For example, the first protective insulating layer 111 and the second protective insulating layer 112 may be As the above, a layer containing an aluminum oxide film can be used. , aluminum oxide, gallium oxide, gallium oxide, yttrium oxide, nitric oxide Yttrium oxide, hafnium oxide, hafnium oxynitride, yttria stabilized zirconia ( A film containing an insulating material containing oxygen, such as YSZ, can also be applied.

[0061] The insulating film having an oxygen excess region is, for example, an insulating film having an oxygen excess region that is greater than the oxygen content that satisfies the stoichiometric composition. It is preferable to use an oxide insulating film containing oxygen in an amount greater than that of oxygen satisfying the stoichiometric composition. When the oxide insulating film contains a large amount of oxygen, some of the oxygen is released by heating.

[0062] In addition, the first protective insulating layer 111 and the second protective insulating layer 112 have an extremely low hydrogen content. It is preferable to use a material with the lowest possible insulating properties. For example, secondary ion mass spectrometry (SIMS) Hydrogen detected by Secondary Ion Mass Spectrometry The content of is 5×10 21 atoms / cm 3 Less than 2 x 10 21 atoms / cm 3 less than 1×10 21 atoms / cm 3 Absolute value including the area where Edge materials may be used.

[0063] The insulating material used for the first protective insulating layer 111 and the second protective insulating layer 112 is In addition, a material in which silicon oxide is contained in the above oxide can also be used. Recon in the range of 0.1% by weight to 30% by weight (e.g., 5% by weight, 10% by weight, etc.) Aluminum oxide containing silicon oxide in this range can be used. By this, the blocking property against oxygen is not deteriorated and the oxygen is desorbed by heating. The amount of oxygen can be increased and the stress in the film can be reduced.

[0064] [About each component] Each component of transistor 100 will now be described.

[0065] [Semiconductor Layer] The oxide semiconductor contained in the semiconductor layer 102 has a wider band gap than silicon. In addition, when an oxide semiconductor having a low carrier density is used, the transistor in an off state This is preferable since it is possible to reduce the current.

[0066] The crystallinity of the semiconductor used for the semiconductor layer 102 is an amorphous semiconductor, a crystalline semiconductor, or a Semiconductors (microcrystalline semiconductors, polycrystalline semiconductors, single crystal semiconductors, or semiconductors that have crystalline parts in part or in whole) In the case where a semiconductor having crystallinity is used for the semiconductor layer 102, either a semiconductor having crystallinity or a semiconductor having crystallinity may be used. This is preferable because it suppresses deterioration of the transistor characteristics.

[0067] In particular, the semiconductor layer 102 has a plurality of crystal parts, and the crystal parts have a c-axis that is the same as that of the semiconductor layer 10 2 (the upper surface of the first protective insulating layer 111 in FIG. 1) or the upper surface of the semiconductor layer 102. It is preferable to use a layer in which the crystals are oriented approximately perpendicular to the substrate and have no grain boundaries between adjacent crystal portions. It is.

[0068] By using such a material for the semiconductor layer 102, fluctuations in electrical characteristics are suppressed, A highly reliable transistor 100 can be achieved.

[0069] The semiconductor layer 102 may have a single layer structure or a stacked structure of two or more layers. In that case, two or more oxide semiconductor films having different compositions may be combined.

[0070] A preferred form of an oxide semiconductor applicable to the semiconductor layer 102 and a method for forming the same will be described below. This will be described in detail in a later embodiment.

[0071] 〔substrate〕 There is no particular restriction on the material of the substrate 101, but it should be strong enough to withstand the heat treatment during the process. Use materials with high heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, A substrate such as a fire substrate or an yttria-stabilized zirconia (YSZ) substrate is used as the substrate 101. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide or a polycrystalline semiconductor substrate may be used. Substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates can also be used. can.

[0072] In addition, various semiconductor substrates and SOI substrates on which semiconductor elements are provided are referred to as substrates 101. In this case, the transistor 100 may be disposed on the substrate 101 via an interlayer insulating layer. At this time, the transistor 10 is connected to the connection electrode embedded in the interlayer insulating layer. At least one of the pair of electrodes 103 and the gate electrode 105 of the semiconductor element 100 is electrically connected to the semiconductor element 100. The transistor 100 may be provided over a semiconductor element with an interlayer insulating layer interposed therebetween. By providing the transistor 100, the increase in area due to the addition of the transistor 100 can be suppressed. can be done.

[0073] [Gate electrode] The gate electrode 105 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or tantalum. or an alloy containing the above-mentioned metals or It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. One or more of the above metals may be used. Semiconductors such as etched polycrystalline silicon, silicides such as nickel silicide, etc. The gate electrode 105 may have a single layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a titanium film on an aluminum film, A two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, Two-layer structure with tungsten film laminated, tantalum nitride film or tungsten nitride film on tantalum A two-layer structure with a stainless steel film laminated on top of a titanium film and an aluminum film laminated on top of the titanium film. There are three-layer structures, such as a titanium film formed on top of the aluminum film. , tantalum, tungsten, molybdenum, chromium, neodymium, and scandium An alloy film made of one or more metals or a nitride film of these metals may be used.

[0074] The gate electrode 105 is made of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, etc. A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0075] In addition, between the gate electrode 105 and the gate insulating layer 104, an In-Ga-Zn-based oxynitride Semiconductor film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film ( InN, ZnN, etc.) may be provided. These films have a thermal conductivity of 5 eV or more, preferably 5.5 eV or more. Since the work function is larger than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor using the conductor can be shifted to the positive side, so that the so-called normal For example, an In-Ga-Zn oxynitride semiconductor When a conductive film is used, the nitrogen concentration is at least higher than that of the semiconductor layer 102, specifically, 7 atomic %. The above-mentioned In-Ga-Zn-based oxynitride semiconductor film is used.

[0076] [Gate insulation layer] The gate insulating layer 104 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, nitride Silicon or the like may be used, and the layer may be a laminate or a single layer.

[0077] The gate insulating layer 104 is made of hafnium silicate (HfSiO x ), nitrogen is added Added hafnium silicate (HfSi x O y N z ), hafnium aluminium doped with nitrogen Luminate (HfAl x O y N z ), hafnium oxide, yttrium oxide and other high The use of -k materials can reduce gate leakage of transistors.

[0078] [Pair of electrodes] The pair of electrodes 103 is made of a conductive material such as aluminum, titanium, chromium, nickel, or copper. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten. The metal or alloy containing the metal as the main component is used in a single-layer or multi-layer structure. For example, a single layer structure of aluminum film containing silicon, titanium on aluminum film, A two-layer structure with a copper film on a titanium film, a two-layer structure with a copper film on a titanium film, and a titanium film on a tungsten film. A two-layer structure in which a titanium film is laminated, and a copper film is laminated on a copper-magnesium-aluminum alloy film. Two-layer structure: a titanium film or titanium nitride film, and a layer of titanium or titanium nitride on top of the titanium film or titanium nitride film. An aluminum or copper film is laminated, and then a titanium or titanium nitride film is formed on top of it. A three-layer structure consisting of a molybdenum film or molybdenum nitride film and a molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on the molybdenum film, and a molybdenum film is further laminated on the aluminum film or copper film. Alternatively, there is a three-layer structure in which a molybdenum nitride film is formed. Alternatively, a transparent conductive material containing zinc oxide may be used.

[0079] The above is a description of an example of the configuration of the transistor 100 and each of its components.

[0080] [Production method example 1] An example of a method for manufacturing the transistor 100 illustrated in FIG. 1 will be described below with reference to the drawings. 2 is a schematic cross-sectional view illustrating each step in the manufacturing method exemplified below.

[0081] [Formation of first protective insulating layer] First, a first protective insulating layer 111 is formed on a substrate 101 (FIG. 2(A)).

[0082] The first protective insulating layer 111 is formed by, for example, a sputtering method in an atmosphere containing oxygen. In addition, the film can be formed by chemical vapor deposition (CVD) in an atmosphere containing oxygen. al Vapor Deposition) method, MBE (Molecular Beam) Epitaxy) method, ALD (Atomic Layer Deposition) method or by PLD (Pulsed Laser Deposition) method, etc. This is also fine.

[0083] For example, when an aluminum oxide film is used as the first protective insulating layer 111, The film can be formed using aluminum as a sputtering target in an atmosphere containing oxygen. The deposition gas may contain an inert gas such as a rare gas. The flow rate of oxygen relative to the flow rate is set to 20% or more, preferably 30% or more, more preferably 40% or more. In addition, the reactivity of aluminum as a sputtering target is The aluminum oxide film may be formed by sputtering. When used as a sputtering target, more oxygen can be contained in the film. Therefore, it is preferable.

[0084] [Formation of Semiconductor Layer] Next, a semiconductor film is formed on the first protective insulating layer 111. A resist mask is formed on the semiconductor film by a photolithography method or the like, and unnecessary parts of the semiconductor film are etched away. The resist mask is then removed, leaving the island-shaped semiconductor layer 102. can be formed (FIG. 2(B)).

[0085] Semiconductor films are formed by sputtering, CVD, MBE, ALD, or PLD. Alternatively, a liquid material such as a sol-gel method, a spray method, or a mist method can be used. A thin film formation technique using a material can also be used. The deposition of a semiconductor film is performed by the sputtering method. As the sputtering method, RF sputtering method, DC sputtering method, etc. In particular, the metal oxide generated during film formation can be removed by a sputtering method, AC sputtering method, etc. The DC sputtering method is used because it can reduce the thickness and make the film thickness distribution uniform. is preferred.

[0086] After the semiconductor film is formed, heat treatment may be performed. Preferably, the temperature is 300° C. or higher and 500° C. or lower, and the atmosphere is an inert gas, an oxidizing gas, and the like for 10 minutes. The heat treatment may be carried out in an atmosphere containing at least 1 ppm of fluorine or under reduced pressure. After heat treatment in an oxidizing gas atmosphere, oxidizing gas is added at a concentration of 10 ppm or less to replenish the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing the above-mentioned. Alternatively, oxygen is supplied to the semiconductor layer 102, and the oxide semiconductor in the semiconductor layer 102 is The heat treatment can reduce oxygen vacancies. This may be performed after the island-shaped semiconductor layer 102 is formed by processing the semiconductor film.

[0087] The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43 6 nm), H-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Also, the exposure may be performed by an immersion exposure technique. Light (EUV: Extreme Ultra-violet) or X-rays may also be used. Instead of light for exposure, electron beams can be used. Extreme ultraviolet light, X-rays, or The use of an electron beam is preferable because it enables extremely fine processing. When exposure is performed by scanning a beam such as a photomask, no photomask is required.

[0088] Here, as shown in FIG. 2B, the first protective insulating layer 111 is removed during etching of the semiconductor film. In some cases, a part of the semiconductor layer 102 is etched away and thinned in a region that does not overlap the semiconductor layer 102. The upper surface of the first protective insulating layer 111 around the semiconductor layer 102 is higher than the lower surface of the conductor layer 102. By lowering the surface, the gate electrode 105 to be formed later is disposed on the side surface of the semiconductor layer 102. As a result, the gate can be formed so as to surround the lower portion of the side surface of the semiconductor layer 102. The on-state current of the transistor 100 is increased by applying a sufficient electric field from the on-state electrode 105. 26, the gate electrode 10 is formed on the lower surface of the semiconductor layer 102. If a part of the first protective insulating layer 111 is etched so that the bottom surface of the insulating film 5 becomes lower, the thickness of the insulating film 5 becomes smaller. This is preferable because the on-current of the transistor 100 can be increased.

[0089] In addition, depending on the material used for the first protective insulating layer 111 and the etching conditions of the semiconductor film, In some cases, the first protective insulating layer 111 may not be etched. This is preferable because it improves the coverage of the film formed on the substrate 2.

[0090] As shown in FIG. 2B, the upper corners of the semiconductor layer 102 are gently curved. In particular, when the semiconductor layer 102 is finely processed, By forming the semiconductor layer 102 in such a shape, Since the coverage of the film provided on the upper portion of the transistor 100 is improved, the variation in the electrical characteristics of the transistor 100 is reduced. This is preferable because it can suppress noise and fluctuations.

[0091] [Formation of a pair of electrodes] Then, a conductive film is formed on the first protective insulating layer 111 and the semiconductor layer 102. A resist mask is formed on the conductive film by photolithography or the like, and unnecessary portions of the conductive film are removed. The resist mask is then removed to reveal a pair of The electrode 103 can be formed (FIG. 2(C)).

[0092] The conductive film can be formed by, for example, a sputtering method, a vapor deposition method, a CVD method, or the like. do.

[0093] Here, as shown in FIG. 2C, when the conductive film is etched, the upper part of the semiconductor layer 102 is A part of the film is etched, and the part that does not overlap with the pair of electrodes 103 may become thin. Therefore, the thickness of the semiconductor film that will become the semiconductor layer 102 must be predetermined in consideration of the etching depth. It is preferable to form the insulating layer 110 so as to be thick.

[0094] Although not shown in the figure, the first protection layer is also formed during etching of the conductive film in the same manner as described above. A part of the protective insulating layer 111 may be etched and thinned.

[0095] [Formation of Gate Insulating Layer and Gate Electrode] Next, an insulating film is formed on the semiconductor layer 102, the pair of electrodes 103, and the first protective insulating layer 111. A conductive film is then formed on the insulating film. A resist mask is formed on the conductive film using the resist mask, and unnecessary portions of the conductive film and the insulating film are etched away. The resist mask is then removed, leaving the gate electrode 105 and Then, a gate insulating layer 104 can be formed (FIG. 2(D)).

[0096] The insulating film that becomes the gate insulating layer 104 can be formed by sputtering, CVD, MBE, or ALD. In particular, the insulating film can be formed by a CVD method, preferably a PLD method. It is preferable to form the film by a plasma CVD method, since this method can improve the covering property. I wish.

[0097] The conductive film that becomes the gate electrode 105 is formed by, for example, sputtering, vapor deposition, or CVD. The film can be formed by the above method.

[0098] In this case, the gate insulating layer 104 is etched at the same time as the gate electrode 105 is formed. In the case where the gate insulating layer 104 is processed to have a top surface shape similar to that of the gate electrode 105, In the case where the gate insulating layer 104 extends beyond the gate electrode 105, Each of them may be processed separately to obtain the top surface shape. As exposure masks used in the lithography process, etc., gray-tone masks and half-tone masks are used. It is preferable to use a multi-tone mask since this can simplify the process.

[0099] [Formation of second protective insulating layer] Next, the first protective insulating layer 111, the pair of electrodes 103, the gate insulating layer 104, and the gate A second protective insulating layer 112 is formed on the base electrode 105 (FIG. 2(E)).

[0100] The second protective insulating layer 112 is formed in the same manner as the first protective insulating layer 111. can be done.

[0101] Here, the second protective insulating layer 112 is provided with a pair of electrodes 103 and a gate electrode 105. The insulating layer 111 is provided so as to contact the first insulating layer 111 in the region where the insulating layer 111 is not provided. The semiconductor layer 102 is surrounded by the first protective insulating layer 111 and the second protective insulating layer 112. can be done.

[0102] Through the above steps, the transistor 100 can be manufactured.

[0103] [Heat Treatment] After the second protective insulating layer 112 is formed, heat treatment may be performed. Oxygen is supplied to the semiconductor layer 102 from the protective insulating layer 111 and the second protective insulating layer 112. This can reduce oxygen vacancies in the semiconductor layer 102. The insulating layer 111 and the second protective insulating layer 112 suppress the release of oxygen from the semiconductor layer 102. As a result, the formation of oxygen vacancies in the semiconductor layer 102 can be suppressed.

[0104] The above is a description of the example of the manufacturing process of the transistor 100.

[0105] [Modification of Configuration Example 1] The following describes a transistor with a configuration that is partially different from the transistor illustrated in the above Configuration Example 1. A configuration example of the above will be described. Note that the explanation of the overlapping parts will be omitted, and the differences will be described. In addition, even if the position or shape of the components differs, their functions are the same. are the same, the same reference numerals will be used and the description will be omitted.

[0106] [Variation 1] 3A and 3B are schematic cross-sectional views of the transistors exemplified below. FIG. 1A can be used as a schematic diagram. The transistor shown in FIG. 3 mainly includes a semiconductor layer 102 and It differs in that an insulating layer 106 is provided between the first protective insulating layer 111 and the first insulating layer 106 .

[0107] The insulating layer 106 provided under the semiconductor layer 102 is made of a material that releases oxygen when heated. It is preferable that the insulating layer 106 contains an oxide insulating material. The heat generated during the heat treatment in the transistor manufacturing process causes more oxygen to be absorbed. It is possible to supply the insulating layer 106 and the semiconductor layer 102 to the conductive layer 102. The structure is surrounded by a first protective insulating layer 111 and a second protective insulating layer 112. The oxygen released from the insulating layer 106 flows to the outside (the substrate 101 side or the second protective insulating layer 112 side). Therefore, oxygen is more effectively supplied to the semiconductor layer 102. This can be done.

[0108] The insulating layer 106 may be provided so as to cover the upper surface of the first protective insulating layer 111. However, as shown in FIG. 3, the semiconductor layer 102 and the insulating layer 106 are formed so that their top surfaces are substantially the same. It is preferable that the above-mentioned processes are performed using the same resist mask. As a result, the first protective insulating layer 111 and the second protective insulating layer 112 are in contact with the gate electrode 105 and Since the electrodes 103 are not provided in the area where the electrodes 103 are provided, the oxygen diffusion path is blocked and the oxygen diffusion path is effectively blocked. Oxygen can be supplied to the semiconductor layer 102 .

[0109] The insulating layer 106 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable to use an oxide insulating material containing more oxygen than the oxygen required for the stoichiometric composition. When the film is heated, some oxygen is desorbed. The oxide insulating film containing The amount of oxygen released, calculated as oxygen atoms, was 1 .0×10 18 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 The oxide insulating film is as described above.

[0110] As the insulating layer 106, a silicon oxide film or a silicon oxynitride film is formed by a plasma CVD method. In the case of forming the silicon-containing film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of deposition gases containing silicon include silane, disilane, trisilane, and tetrasilane. Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and Nitric oxide, etc.

[0111] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180° C. or higher. The temperature is kept at 260° C. or less, and more preferably at 200° C. or more and 240° C. or less. By introducing gas, the pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less, and more preferably The pressure is between 100 Pa and 200 Pa, and the pressure applied to the electrodes in the treatment chamber is 0.17 W / cm 2 Below Upper 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 More than 0.35W / cm 2 Silicon oxide film or silicon oxynitride film is formed by supplying the following high frequency power. Complete.

[0112] As a film forming condition, high frequency power with the above power density is supplied to a processing chamber at the above pressure. This increases the efficiency of decomposition of the source gas in the plasma, increases the number of oxygen radicals, and increases the amount of oxygen in the source gas. As a result, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is the above temperature, the bond between silicon and oxygen is weak, so the bonding strength is reduced by heating. As a result, the mixture contains more oxygen than the stoichiometric composition. In addition, an oxide insulating film from which part of oxygen is released by heating can be formed.

[0113] [Modification 2] FIG. 4 shows an example in which a capacitor 120 is formed adjacent to a transistor 100. In FIG.

[0114] The capacitor 120 is formed by connecting one of the pair of electrodes 103 of the transistor 100 and the gate electrode 10 5 is processed to form an electrode 125, and the same conductive film as the gate insulating layer 104 is formed between the electrode 125 and the gate insulating layer 104. The insulating film is processed to form a dielectric layer 124.

[0115] In this manner, the capacitor element 120 is formed by processing the film used for manufacturing the transistor 100. In this way, the capacitor 120 can be manufactured simultaneously with the transistor 100 without increasing the number of steps. It can be made.

[0116] In FIG. 4, one of the pair of electrodes 103 of the transistor 100 is connected to the Although the configuration in which the second electrode is used as one electrode of the capacitor 120 is shown, the present invention is not limited to this. The pair of electrodes 103 of the transistor 100 are formed by processing the same conductive film. Alternatively, the gate electrode 105, the electrode 125, and the gate insulating layer 1 may be formed of a material other than the gate insulating layer. At least one of the insulating layer 04 and the dielectric layer 124 may be formed as a continuous integral body and used in common. .

[0117] Here, the materials used for the insulating films constituting the gate insulating layer 104 and the dielectric layer 124 are The following oxides are available: aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide It is preferable to use a high dielectric constant material such as tungsten, strontium titanate, or barium titanate. In addition, these materials may contain lanthanum, aluminum, yttrium, or tungsten. Materials containing metals such as fluorine and oxides of these metals may also be used. Alternatively, a laminate of films each containing the same may be used.

[0118] In addition, the insulating film is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. It is preferable to use such an insulating film. The heat generated during the heating process or the like supplies oxygen from the gate insulating layer 104 to the semiconductor layer 102. It can be provided.

[0119] The above is a description of the modified example.

[0120] [Configuration example 2] Below, a configuration example of a transistor having a configuration partly different from that of the above Configuration Example 1 will be described. Note that explanations of parts that overlap with those described above may be omitted.

[0121] FIG. 5A is a schematic top view of a transistor 200 according to this configuration example. (B) and (C) are schematic cross-sectional views taken along lines EF and GH in FIG. 5(A), respectively. In FIG. 5(A), some components are not shown for clarity.

[0122] The transistor 200 includes an insulating layer 207 having a groove provided on a substrate 201 and an insulating A semiconductor layer 202 is provided on the layer 207 so as to fill the grooves, and a semiconductor layer 2 A pair of electrodes 203 are provided on the semiconductor layer 202 and electrically connected to the semiconductor layer 202. A gate insulating layer 204 is disposed on the semiconductor layer 203 and overlaps the semiconductor layer 202. and a gate electrode 205 located above and overlapping the semiconductor layer 202 .

[0123] Further, below the semiconductor layer 202, a layer is formed so as to cover the side and bottom surfaces of the groove of the insulating layer 207. The first protective insulating layer 211 is provided on the insulating layer 211 as shown in FIG. As shown in FIG. 1, the insulating layer 207 is provided so as to cover the upper surface of the region where the groove is not provided. In addition, a second protective layer is preferably provided to cover the pair of electrodes 203 and the gate electrode 205. An insulating layer 212 is provided. A first protective insulating layer 211 and a second protective insulating layer 21 2 refers to a region where the pair of electrodes 203 and the gate electrode 205 are not provided. It is located adjacent to the

[0124] The semiconductor layer 202, the pair of electrodes 203, the gate insulating layer 204, the gate electrode 205, etc. The semiconductor layer 102, the pair of electrodes 103, the gate insulating layer 104, and the gate The same material as the first protective insulating layer 211 and the second protective insulating layer 212 can be used. The second protective insulating layer 212 is the same as the first protective insulating layer 111 and the second protective insulating layer 112 in the configuration example 1. The same material as that for the insulating layer 112 can be used.

[0125] The first protective insulating layer 211 covers the side and bottom surfaces of the grooves provided in the insulating layer 207. A semiconductor layer 202 is further provided so as to be embedded in the groove. The side and bottom surfaces of the protective layer 202 are surrounded by the first protective insulating layer 211. Therefore, the diffusion of impurities such as hydrogen from the insulating layer 207 to the semiconductor layer 202 is suppressed. In both cases, oxygen is prevented from being released from the semiconductor layer 202 toward the insulating layer 207. will be done.

[0126] In addition, the thickness of the semiconductor layer 202 can be increased by adjusting the depth of the groove. In addition, the on-state current of the transistor 200 can be increased, and the withstand voltage between the source and drain can be improved. For example, when a thick semiconductor layer is formed on a flat surface, the It becomes difficult for the film to cover the semiconductor layer, and the film is broken or low density is formed in the film. On the other hand, in this configuration example, the semiconductor is formed so as to fill the groove. The conductor layer 202 is provided, and the height of the upper surface of the conductor layer 202 and the height of the upper surface of the first protective insulating layer 211 are approximately equal to each other. Therefore, the coating properties of the film formed on the upper layer are not adversely affected. Therefore, the semiconductor layer 202 can be formed thick without affecting the thickness.

[0127] The above is a description of the configuration example of the transistor 200.

[0128] [Production method example 2] An example of a method for manufacturing the transistor 200 illustrated in FIG. 5 will be described below with reference to the drawings. 6A to 6C are schematic cross-sectional views illustrating each step in the fabrication method exemplified below.

[0129] [Formation of insulating layer] First, an insulating layer 207 is formed on a substrate 201 .

[0130] The insulating layer 207 can be formed by a sputtering method, a CVD method, a vapor deposition method, or the like. do.

[0131] The insulating layer 207 may be made of silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide. Silicon, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, Insulating materials such as yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride Edge materials may be used.

[0132] Alternatively, the insulating layer 207 may be formed by laminating films made of different insulating materials. By forming the layer 207 in a laminated structure, the film provided below can be prevented from being damaged during the subsequent formation of the groove. It can function as an etching stopper.

[0133] [Formation of Groove] Next, a resist mask is formed on the insulating layer 207 by using a photolithography method or the like. Then, the upper part of the insulating layer 207 is removed by etching. In this way, a groove can be formed in the insulating layer 207.

[0134] Here, as described above, by making the insulating layer 207 have a multi-layer structure made of different materials, Furthermore, the etching of the underlying layer can be easily performed. By using it as a topper, the bottom surface of the groove can be made flat, which is preferable.

[0135] In addition, when the groove is to be made deep, the resist mask is removed during etching. In that case, the insulating layer 207 may be etched away. A thin film made of a material that is difficult to remove (i.e., a material having a high selectivity for the insulating layer 207 relative to the thin film). The thin film is then etched using a resist mask. The upper part of the insulating layer 207 may be etched using this as a mask to form a groove. If the thin film used as the hard mask is insulating, the hard mask is removed after the groove is formed. It may be left as it is.

[0136] [Formation of first protective insulating layer] Next, a first protective insulating layer 21 is formed on the insulating layer 207 so as to cover the side and bottom surfaces of the groove. 1 is formed (Figure 6(A)).

[0137] The first protective insulating layer 211 was formed in the same manner as the first protective insulating layer 111 in the first manufacturing method. It is formed in the same way.

[0138] [Formation of Semiconductor Layer] Next, a semiconductor film is formed on the first protective insulating layer 211. The groove is completely covered with the semiconductor film. When the semiconductor film is completely embedded in the groove, the height of the upper surface of the portion overlapping the groove of the semiconductor film is set to be equal to or larger than the height of the first protective insulating layer. It is preferable to form the film so that the height is equal to or greater than the height of the portion of 211 that does not overlap with the groove portion. It is.

[0139] The semiconductor film can be formed in the same manner as in the above-mentioned Manufacturing Method Example 1.

[0140] After the semiconductor film is formed, a heat treatment may be performed. The heat treatment is performed in the same manner as in the above-mentioned Example 1 of the manufacturing method. By the heat treatment, the semiconductor film (or the semiconductor Oxygen is supplied to the oxide semiconductor layer 202, and oxygen vacancies in the oxide semiconductor included in the semiconductor layer 202 are reduced. The heat treatment may be performed immediately after the semiconductor film is formed, or after the semiconductor film is heated. Alternatively, the above-mentioned step may be performed after the island-shaped semiconductor layer 202 is formed by the above-mentioned process.

[0141] Next, a planarization process is performed so that the upper surface of the semiconductor film does not overlap the groove portion of the first protective insulating layer 211. By processing the semiconductor so that it matches the top surface of the missing part, Layer 202 can be formed (Figure 6(B)).

[0142] As a planarization process, for example, CMP (Chemical Mechanical Planarization) is used. For this purpose, a polishing process such as polishing or an etching process may be used.

[0143] Here, aluminum oxide or the like is used as the first protective insulating layer 211, and a planarization process is performed. When a polishing process such as CMP is used, the first protective insulating layer 211 acts as an etching stopper. Therefore, the thickness of the semiconductor layer 202 can be reduced by the planarization process. It is possible to suppress the thickness from becoming thicker, and further to reduce the variation in thickness.

[0144] [Formation of a pair of electrodes] Then, a conductive film is formed on the first protective insulating layer 211 and the semiconductor layer 202. A resist mask is formed on the conductive film by photolithography or the like, and unnecessary portions of the conductive film are removed. The resist mask is then removed to reveal a pair of An electrode 203 can be formed (FIG. 6(C)).

[0145] The conductive film can be formed by, for example, a sputtering method, a vapor deposition method, a CVD method, or the like. do.

[0146] Here, as shown in FIG. 6C, when the conductive film is etched, the upper part of the semiconductor layer 202 is A part of the electrode 203 is etched, and the part that does not overlap with the pair of electrodes 203 may become thin. Therefore, the thickness of the semiconductor film that becomes the semiconductor layer 202 (i.e., the depth of the groove) is adjusted by etching. It is preferable to form the hole thick in advance, taking into consideration the depth to be cut.

[0147] Although not shown in the figure, a part of the first protective insulating layer 211 is removed during etching of the conductive film. The film may also be etched and thinned.

[0148] [Formation of Gate Insulating Layer and Gate Electrode] Next, an insulating film is formed on the semiconductor layer 202, the pair of electrodes 203, and the first protective insulating layer 211. A conductive film is then formed on the insulating film. Then, a resist mask is formed on the conductive film, and unnecessary portions of the conductive film and the insulating film are etched away. Thereafter, the resist mask is removed, thereby removing the gate electrode 205 and A gate insulating layer 204 can be formed (FIG. 6(D)).

[0149] The insulating film that becomes the gate insulating layer 204 and the conductive film that becomes the gate electrode 205 are formed by the above-mentioned method. It can be formed in the same manner as in 1.

[0150] In this case, the gate insulating layer 204 is etched at the same time as the gate electrode 205 is formed. In the case where the gate insulating layer 204 is processed to have a top surface shape similar to that of the gate electrode 205, In the case where the gate insulating layer 204 extends beyond the gate electrode 205, Each of them may be processed separately to obtain the top surface shape. As exposure masks used in the lithography process, etc., gray-tone masks and half-tone masks are used. It is preferable to use a multi-tone mask since this can simplify the process.

[0151] [Formation of second protective insulating layer] Next, the first protective insulating layer 211, the pair of electrodes 203, the gate insulating layer 204, and the gate A second protective insulating layer 212 is formed on the base electrode 205 (FIG. 6(E)).

[0152] The second protective insulating layer 212 is formed in the same manner as the first protective insulating layer 211. can be done.

[0153] Here, the second protective insulating layer 212 is provided with a pair of electrodes 203 and a gate electrode 205. The first protective insulating layer 211 is provided in contact with the first protective insulating layer 211 in the region where the first protective insulating layer 211 is not provided. The semiconductor layer 202 is surrounded by the first protective insulating layer 211 and the second protective insulating layer 212. can be done.

[0154] Through the above steps, the transistor 200 can be manufactured.

[0155] [Heat Treatment] After the second protective insulating layer 212 is formed, heat treatment may be performed. Oxygen is supplied to the semiconductor layer 202 from the protective insulating layer 211 and the second protective insulating layer 212. In addition, oxygen vacancies in the semiconductor layer 202 can be reduced. The edge layer 211 and the second protective insulating layer 212 suppress the release of oxygen from the semiconductor layer 202. As a result, the formation of oxygen vacancies in the semiconductor layer 202 can be suppressed.

[0156] The above is a description of the example of the manufacturing process of the transistor 200.

[0157] [Modification of Configuration Example 2] The following describes a transistor with a configuration that is partially different from the transistor illustrated in the above configuration example 2. A configuration example of the above will be described. Note that the explanation of the overlapping parts will be omitted, and the differences will be described. In addition, even if the position or shape of the components differs, their functions are the same. are the same, the same reference numerals will be used and the description will be omitted.

[0158] [Variation 1] 7A and 7B are schematic cross-sectional views of the transistors exemplified below. FIG. 5A can be used as a schematic diagram. The transistor shown in FIG. 7 mainly includes a semiconductor layer 202 and It differs in that an insulating layer 206 is provided between the first protective insulating layer 211 and the first insulating layer 212 .

[0159] In the grooves provided in the insulating layer 207, the insulating layer 206 is The insulating layer 206 is provided to cover the side and top surfaces of the semiconductor layer 202. It is provided covering the upper and lower surfaces.

[0160] The insulating layer 206 provided under the semiconductor layer 202 is made of a material that releases oxygen when heated. It is preferable that the insulating layer 206 contains an oxide insulating material. The heat generated during the heat treatment in the transistor manufacturing process causes more oxygen to be absorbed. It is possible to supply the insulating layer 206 and the semiconductor layer 202 to the conductive layer 202. The structure is surrounded by the first protective insulating layer 211 and the second protective insulating layer 212. The oxygen released from the insulating layer 206 flows to the outside (the insulating layer 207 side or the second protective insulating layer 212 Therefore, oxygen is more effectively supplied to the semiconductor layer 202. It is possible.

[0161] The insulating layer 206 also covers the upper surface of the first protective insulating layer 211 in an area that does not overlap with the groove portion. However, it is processed so that it is provided inside the groove by flattening treatment. With such a configuration, the first protective insulating layer 211 and the second The protective insulating layer 212 is connected to the gate electrode 205 and the pair of electrodes 203 in a region where the gate electrode 205 and the pair of electrodes 203 are not provided. Therefore, the diffusion path of oxygen is blocked, and oxygen can be effectively supplied to the semiconductor layer 202. Cut.

[0162] The insulating layer 206, like the insulating layer 106, contains more oxygen than satisfies the stoichiometric composition. It is preferable to use an oxide insulating film containing oxygen.

[0163] [Modification 2] FIG. 8 shows an example in which a capacitor 220 is formed adjacent to a transistor 200. In FIG.

[0164] The capacitor 220 is formed by connecting one of the pair of electrodes 203 of the transistor 200 and the gate electrode 20 5 is processed to form an electrode 225, and the same conductive film as the gate insulating layer 204 is formed between the electrode 225 and the gate insulating layer 204. The insulating film is processed to form a dielectric layer 224.

[0165] In this manner, the capacitor element 220 is formed by processing the film used for manufacturing the transistor 200. In this way, the capacitor 220 can be manufactured simultaneously with the transistor 200 without increasing the number of steps. It can be made.

[0166] In FIG. 8, one of the pair of electrodes 203 of the transistor 200 is connected to the However, the present invention is not limited to this. The pair of electrodes 203 of the transistor 200 are formed by processing the same conductive film. In addition, the gate electrode 205 and the electrode 225, as well as the gate insulating layer 204 and At least one of the dielectric layers 224 may be made into a continuous, integral body and used in common.

[0167] Here, the materials used for the insulating films constituting the gate insulating layer 204 and the dielectric layer 224 are The following oxides are available: aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide It is preferable to use a high dielectric constant material such as tungsten, strontium titanate, or barium titanate. In addition, these materials may contain lanthanum, aluminum, yttrium, or tungsten. Materials containing metals such as fluorine and oxides of these metals may also be used. Alternatively, a laminate of films each containing the same may be used.

[0168] In addition, the insulating film is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. It is preferable to use such an insulating film. The heat generated during the heat treatment or the like causes oxygen to be introduced from the gate insulating layer 204 to the semiconductor layer 202. can be supplied.

[0169] [Modification 3] When multiple transistors are arranged on a substrate, one trench is required for each transistor. Instead of providing a trench for each of the transistors, one trench is provided for each of the transistors. This allows transistors to be integrated more densely.

[0170] As an example, in FIG. 9, four transistors 200 are connected in series. In the case where four transistors 200 are formed on the upper portion of one groove portion provided in the insulating layer 207, FIG. 9(A) is a schematic top view, and FIG. 9(B) is a cross-sectional view of FIG. 9(A). FIG. 1 is a schematic cross-sectional view at IJ.

[0171] As shown in FIG. 9B, four transistors are formed on the upper portion of one groove formed in the insulating layer 207. In addition, two adjacent transistors 200 are formed in common. The two transistors 200 are connected in series by providing a common electrode 203. On the other hand, the gate electrode 205 is provided independently for each transistor 200. is.

[0172] The first protective insulating layer 211 and the second protective insulating layer 212 are connected to the electrodes 203 provided on both ends. The transistors 200 are arranged so as to be in contact with each other in an outer region and surround the four transistors 200 .

[0173] An example of a circuit configuration to which such a series-connected transistor 200 can be applied is shown in FIG. The circuit shown in FIG. 9C has four transistors and three capacitors. In two adjacent transistors, the source or drain of one transistor is connected to the other A node is formed by electrically connecting the source or drain of one of the transistors, and the node One electrode of the capacitor is electrically connected to the gate.

[0174] For example, the capacitance element may have the configuration of the capacitance element 220 illustrated in the second modification. Cut.

[0175] The circuit shown in FIG. 9C can be used as a shift register by applying the following potentials: It can function as a

[0176] A common potential is applied to the other electrodes of the three capacitance elements. The gates of the first and third transistors from the left are connected to the same clock signal. The gates of the second and fourth transistors are fed with the same clock signal (CLK1). A signal (CLK2) is given. Also, one of the source or drain of the first transistor is The first one is the input terminal to which the input potential (IN) is applied, and the second one is the source or drain of the One of the inputs is the output terminal from which the output potential (OUT) is output. The potentials (e.g. high) that alternately turn on the transistors without overlapping each other By using a clock signal that is a clock signal with a potential of 100 V, the potential applied to the input terminal is The information can be shifted from left to right.

[0177] The configuration shown in FIG. 9D is a circuit diagram of a plurality of read-out electrodes connected in series to the circuit shown in FIG. Each of the transistors 260 is a capacitance element. The other electrode of each of the capacitance elements is electrically connected to a node. A potential for reading is applied. By using such a configuration, the circuit shown in FIG. The potential information held in the node to which one electrode of the capacitance element is connected can be read out at any time. The transistor 26 can function as a NAND type memory device. The transistor 0 may be a transistor including an oxide semiconductor, similar to the transistor 200. Alternatively, as exemplified in the following embodiments, transistors using different semiconductors may be used. It's fine.

[0178] The above is a description of the modified example.

[0179] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0180] (Embodiment 2) In this embodiment, a transistor having a configuration partially different from that of the transistor illustrated in the first embodiment is used. A configuration example of the transistor will be described. Note that the explanation of the parts that overlap with the above will be omitted. In addition, components with different positions or shapes will be described in detail. In cases where the functions are the same, the same reference numerals will be used and descriptions thereof will be omitted.

[0181] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer and a gate electrode overlapping with the oxide semiconductor layer. Between the insulating layer and the protective insulating layer, at least one of the metal elements constituting the oxide semiconductor layer is It is preferable that the oxide layer contains one metal element as a constituent element. A trap level is formed at the interface between the oxide semiconductor layer and an insulating layer overlapping the oxide semiconductor layer. Since the above-mentioned problem can be prevented, deterioration of the electrical characteristics of the transistor can be prevented. .

[0182] That is, in one embodiment of the present invention, at least the upper surface and the lower surface of the oxide semiconductor layer are made of an oxide semiconductor. The oxide layer acts as a barrier to prevent the formation of interface states in the carbon nanotube layer. The top and side surfaces of the oxide semiconductor layer in the panel width direction are connected to the gate electrode via the gate insulating layer. an insulating layer including an aluminum oxide film so as to cover the oxide semiconductor layer and to enclose the oxide semiconductor layer; In the above-described structure, the oxide semiconductor layer The formation of oxygen vacancies and the inclusion of impurities, which are factors that cause carrier generation in the semiconductor and at the interface, are suppressed. Since the oxide semiconductor layer can be highly purified and intrinsic, The term "oxidizing" refers to making the oxide semiconductor layer intrinsic or substantially intrinsic. This suppresses fluctuations in the electrical characteristics of transistors that include an organic semiconductor layer, thereby providing highly reliable semiconductor devices. It will be possible to provide

[0183] Note that in the case of being substantially intrinsic in this specification and the like, the carrier density of the oxide semiconductor layer is , 1×10 17 / cm 3 Less than 1×10 15 / cm 3 Less than or equal to 1 × 10 13 / cm 3 By making the oxide semiconductor layer highly intrinsic, the transistor has stable electrical characteristics. It is possible to give the

[0184] More specifically, for example, the following configuration can be adopted.

[0185] [Configuration example 1] 10A and 10B are schematic cross-sectional views of a transistor 150, which will be described below. For a schematic top view, FIG. 1A can be used. The embodiment is similar to that of the first embodiment in that it mainly has a first oxide layer 151 and a second oxide layer 152. This is different from the transistor 100 illustrated in the first embodiment.

[0186] The first oxide layer 151 is provided between the first protective insulating layer 111 and the semiconductor layer 102. The second oxide layer 152 is provided between the semiconductor layer 102 and the gate insulating layer 104. It is being done.

[0187] More specifically, the second oxide layer 152 has an upper surface that is in contact with the lower surfaces of the pair of electrodes 103 and The gate insulating layer 104 is provided in contact with the lower surface of the gate insulating layer 104 .

[0188] The first oxide layer 151 and the second oxide layer 152 are the same as the semiconductor layer 102. The oxides include those containing one or more of the metallic elements.

[0189] Note that the boundary between the semiconductor layer 102 and the first oxide layer 151 or the boundary between the semiconductor layer 102 and the second oxide layer 152 may be a thin film. The boundary with the oxide layer 152 may be unclear.

[0190] For example, the first oxide layer 151 and the second oxide layer 152 contain In or Ga. Representative examples include In-Ga oxides, In-Zn oxides, and In-M-Zn oxides ( M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf, and the semiconductor layer A material whose conduction band lower end energy is closer to the vacuum level than 102 is used. The energy of the bottom of the conduction band of the first oxide layer 151 or the second oxide layer 152 and the semiconductor The difference in energy between the bottom of the conduction band of the layer 102 and the bottom of the conduction band of the layer 103 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less It is preferable to set it to 0.4 eV or less.

[0191] The first oxide layer 151 and the second oxide layer 152 are disposed so as to sandwich the semiconductor layer 102. 52, an oxide having a higher Ga content that functions as a stabilizer compared to the semiconductor layer 102 By using the above, release of oxygen from the semiconductor layer 102 can be suppressed.

[0192] The semiconductor layer 102 is, for example, a layer of In:Ga:Zn=1:1:1 or 3:1:2. When an In-Ga-Zn oxide having a ratio of 1:1 is used, the first oxide layer 151 or the second oxide layer The material layer 152 may be, for example, In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1 In-Ga- with atomic ratios of 1:6:4, 1:6:8, 1:6:10, or 1:9:6 A Zn-based oxide can be used. The atomic ratios of the first oxide layer 151 and the second oxide layer 152 are plus or minus the above atomic ratios as errors. The composition of the first oxide layer 151 and the second oxide layer 152 is the same as that of the first oxide layer 151. The same materials may be used, or materials of different compositions may be used.

[0193] In addition, when an In-M-Zn oxide is used as the semiconductor layer 102, the semiconductor layer 102 and The target used for forming the semiconductor film is a metal element contained in the target. When the atomic ratio is In:M:Zn=x1:y1:z1, the value of x1 / y1 is 1 / 3 or less. z1 / y1 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less, It is preferable to use an oxide having an atomic ratio of 1 or more and 6 or less. Note that making z1 / y1 6 or less makes it easier to form the CAAC-OS film described later. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:1:1, 3:1:2, and the like.

[0194] Further, when an In-M-Zn-based oxide is used as the first oxide layer 151 and the second oxide layer 152, for forming the oxide films that become the first oxide layer 151 and the second oxide layer 152, the target used has an atomic ratio of the metal elements contained in the target of In:M:Zn = x2:y2:z2. When this is the case, x2 / y2 < x1 / y1, and it is preferable to use an oxide having an atomic ratio such that the value of z2 / y2 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less. Note that making z2 / y2 6 or less makes it easier to form the CAAC-OS film described later. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:4, 1:3:6, 1:3:8, and the like.

[0195] Further, by using, for the first oxide layer 151 and the second oxide layer 152, a material whose conduction band bottom energy is closer to the vacuum level than that of the semiconductor layer 102, a channel is mainly formed in the semiconductor layer 102, and the semiconductor layer 102 becomes the main current path. In this way, by sandwiching the semiconductor layer 102 in which the channel is formed with the first oxide layer 151 and the second oxide layer 152 containing the same metal element, the generation of these interface levels is suppressed, and the reliability in the electrical characteristics of the transistor is improved. Note that the present invention is not limited to these, and depending on the required semiconductor characteristics and electrical characteristics (field effect of the transistor characteristics)

[0196] However, it is not limited to these, and depending on the required semiconductor characteristics and electrical characteristics (field effect It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of the transistor, the semiconductor layer 102, the first oxide layer 151, and the The carrier density, impurity concentration, defect density, and atomic ratio of metal elements to oxygen of the oxide layer 152 of 2 It is preferable that the interatomic distance, density, etc. are appropriate.

[0197] Here, the thickness of the semiconductor layer 102 is at least thicker than that of the first oxide layer 151. It is preferable that the thicker the semiconductor layer 102 is, the higher the on-state current of the transistor can be. In addition, the first oxide layer 151 has an effect of suppressing the generation of interface states in the semiconductor layer 102. For example, the thickness of the semiconductor layer 102 is set to be equal to or larger than the thickness of the first oxide layer. The thickness of the layer 151 is more than 1 time, preferably 2 times or more, and more preferably 4 times or more. More preferably, it should be 6 times or more.

[0198] In addition, the second oxide layer 152, like the first oxide layer 151, is also formed at the interface of the semiconductor layer 102. It is sufficient that the thickness is such that the effect of suppressing the generation of the level is not lost. For example, the first oxide The thickness of the second oxide layer 152 may be equal to or less than that of the layer 151. Since the electric field from the gate electrode 105 may not reach the semiconductor layer 102 easily, It is preferable that the second oxide layer 152 is formed thin. The thickness of 2 is determined by taking into consideration the withstand voltage of the gate insulating layer 104 and the voltage at which the transistor 150 is driven. The number of times may be set appropriately depending on the situation.

[0199] As shown in FIG. 10B, the oxide layer 151 is more porous than the oxide layer 151 at its periphery. The upper surface of the first protective insulating layer 111 in the surrounding area is lowered, and the gate electrode 105 is disposed on the semiconductor layer 102. As a result, the lower part of the side surface of the semiconductor layer 102 is The electric field from the gate electrode 105 is sufficiently applied to the transistor 150 so as to increase the on-current of the transistor 150. Similarly, as shown in FIG. 27, the gate electrode 152 can be formed on the lower surface of the oxide layer 151. If the lower surface of the gate electrode 105 is lowered, the on-current of the transistor 150 can be increased. This is preferable because it is possible to

[0200] Here, the band structure in the channel formation region of the transistor 150 will be described. .

[0201] Figure 11 (A) and (B) show the energy band structure in the thickness direction of the channel formation region. is shown diagrammatically.

[0202] In Fig. 11(A) and (B), EcI1, EcS1, EcS2, EcS3, and EcI2 are the first protective insulating layer 111, the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 153, respectively. The energy of the bottom of the conduction band of the oxide layer 152 and the gate insulating layer 104 is shown in FIG. For convenience, the thickness of each layer is not taken into consideration here.

[0203] Here, the difference between the vacuum level and the conduction band minimum (also called the electron affinity) is The energy difference between the potential and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the measured energy. It can be measured using HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was determined by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (e.g. Measurements can be performed using a HI VersaProbe.

[0204] As shown in FIG. 11A, a first oxide layer 151, a semiconductor layer 102, a second oxide layer In 152, the energy of the conduction band minimum changes continuously with no barrier between them. This is because the compositions of the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are similar to each other. This allows oxygen to easily diffuse between the two layers, forming what may be called a mixed layer between the two layers. This is understandable.

[0205] In FIG. 11A, the first oxide layer 151 and the second oxide layer 152 are formed in the same energy state. The case of oxide layers with different energy gaps has been shown. For example, EcS3 is higher than EcS1. At higher energies, a portion of the band structure is shown in FIG. 11(B). Although not shown, EcS1 may have higher energy than EcS3.

[0206] 11A and 11B, the semiconductor layer 102 forms a well in the channel formation region. ), and it can be seen that a channel is formed in the semiconductor layer 102. 151, the semiconductor layer 102, and the second oxide layer 152 have a continuous conduction band minimum energy. Since the well is gradually changing, it can also be called a U Shape Well. A channel formed in this manner can also be called a buried channel.

[0207] The first oxide layer 151 and the second oxide layer 152 are formed of metal elements constituting the semiconductor layer 102. Since the first oxide layer 151, the semiconductor layer 102 and the second oxide layer 153 are oxides containing one or more elements, The laminated structure in which the oxide layer 152 is laminated is also called an oxide laminate in which the main component is commonly laminated. (Hereinafter, the first oxide layer 151, the semiconductor layer 102, and the second oxide layer 152 are stacked.) A laminated structure in which oxides are stacked together with a common main component is also called an oxide stack. The layers are not simply stacked, but are connected in a continuous junction (here, the energy of the conduction band minimum is particularly It is possible to fabricate the material so that a U-shaped well structure in which the temperature changes continuously between layers is formed. This is because defect levels such as trap centers and recombination centers are formed at the interfaces of the layers. When such impurities are present, the continuity of the energy band is lost and carriers are transported at the interface. is lost due to trapping or recombination.

[0208] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. Each layer is deposited in succession using a deposition device (e.g., a sputtering device) without exposure to air. Each chamber in the sputtering apparatus is preferably In order to remove impurities such as water as much as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum evacuation (5×10 -7 Pa~1×10 -4 It is preferable to use a temperature of up to about 10 Pa. Alternatively, a turbo molecular pump and cold trap can be combined to separate the chamber from the exhaust system. It is preferable to prevent backflow of gas into the bar.

[0209] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of the sputtering gas. The dew point is preferably -40°C or less, more preferably -80°C or less, and even more preferably -100°C or less. By using a gas highly purified by the above method, it is possible to prevent moisture and other substances from being absorbed into the oxide semiconductor as much as possible. This can be prevented.

[0210] A first oxide layer 151 and a second oxide layer 152 are provided on the upper or lower layer of the semiconductor layer 102. Layer 152 acts as a barrier layer and protects the insulating layer (first protective insulating layer 111) from the oxide stack. The influence of trap states formed at the interface between the gate insulating layer 104 and the oxide stack is Extending to the semiconductor layer 102, which is the main carrier path of the transistor can be suppressed.

[0211] For example, oxygen vacancies in a semiconductor layer occur deep within the energy gap of an oxide semiconductor. This manifests itself as a localized level at the energy position. The reliability of the transistor decreases when oxygen is trapped in the semiconductor layer. In the oxide stack, the oxide layer has a larger oxide content than the semiconductor layer 102. By providing oxide layers that are less likely to cause atomic deficiencies on the top and bottom of the semiconductor layer 102, For example, the semiconductor layer 102 can be used for a constant current measurement. Measured by the constant photocurrent method (CPM) The absorption coefficient due to the localized level is set to 1×10 -3 / cm, preferably less than 1×10 -4 / It can be less than cm.

[0212] In addition, the semiconductor layer 102 may be formed by forming an insulating layer having a different constituent element (e.g., an insulating layer including a silicon oxide film). When the layer contacts the interface between the two layers, an interface state is formed at the interface between the two layers, and the interface state forms a channel. In such a case, a second transistor with a different threshold voltage appears, However, the oxide stack can cause a shift in the apparent threshold voltage of the transistor. In the present invention, the first oxide layer 151 is formed by including one or more metal elements constituting the semiconductor layer 102. Therefore, an interface state is unlikely to be formed at the interface between the first oxide layer 151 and the semiconductor layer 102. Therefore, by providing the first oxide layer 151, the threshold voltage of the transistor and the like can be reduced. This can reduce the variation in electrical characteristics.

[0213] In addition, when a channel is formed at the interface between the gate insulating layer 104 and the semiconductor layer 102, the Interface scattering occurs at the interface, reducing the field-effect mobility of the transistor. In the oxide stack, a second oxide layer is formed by stacking one or more metal elements constituting the semiconductor layer 102. Since the second oxide layer 152 is included, the carrier is not generated at the interface between the semiconductor layer 102 and the second oxide layer 152. This makes it difficult for electrons to scatter, and the field effect mobility of the transistor can be increased.

[0214] [Configuration example 2] 12A and 12B are schematic cross-sectional views of a transistor 160, which will be described below. For a schematic top view, FIG. 1A can be used. The transistor 150 differs from the transistor 150 described above mainly in that the shape of the second oxide layer 152 is different. There are.

[0215] In the transistor 160, the second oxide layer 152 has a bottom surface that is in contact with the pair of electrodes 103. Further, a pair of electrodes 103 are provided. The insulating layer 104 is provided in contact with the upper surface and side surfaces of the semiconductor layer 102 in a small area.

[0216] In the configuration shown in FIG. 12, the top surface shape of the second oxide layer 152 and the gate insulating layer 104 is The same photomask is used to process the upper surface of the gate electrode 105 so that the upper surface of the gate electrode 105 roughly matches the upper surface of the gate electrode 105. In addition, the second protective insulating layer 112 is formed between the second oxide layer 152 and the gate insulating layer. The layer 104 is provided in contact with each end of the layer 104. Oxidation occurs from the semiconductor layer 102 through the second oxide layer 152 and the edge of the gate insulating layer 104. Therefore, it is possible to suppress the desorption of elements.

[0217] As shown in FIG. 12B, the semiconductor layer 102 of the transistor 160 has a top surface In addition, the side surface of the semiconductor layer 152 is also in contact with the second oxide layer 152. The channel forming region of 102 is surrounded by a first oxide layer 151 and a second oxide layer 152. It is composed of:

[0218] With this structure, the second oxide film provided in contact with the side surface of the semiconductor layer 102 The layer 152 can suppress the formation of interface states even on the side surfaces of the semiconductor layer 102. As a result, in the case where the channel formed near the side surface of the semiconductor layer 102 is actively used, Even if the transistor is turned on, the fluctuation of its electrical characteristics can be suppressed, resulting in high on-state current and high signal quality. Therefore, it is possible to realize a transistor having both high reliability and low noise.

[0219] As shown in FIG. 12B, the oxide layer 151 is more porous than the bottom surface of the oxide layer 151. The upper surface of the first protective insulating layer 111 in the surrounding area is lowered, and the gate electrode 105 is disposed on the semiconductor layer 102. As a result, the lower part of the side surface of the semiconductor layer 102 is The electric field from the gate electrode 105 is sufficiently applied to the transistor 160 so as to increase the on-current of the transistor 160. Similarly, as shown in FIG. 28, the gate electrode 152 can be formed on the lower surface of the oxide layer 151. If the lower surface of the gate electrode 105 is lowered, the on-current of the transistor 160 can be increased. This is preferable because it is possible to

[0220] In addition, by using the insulating layer 106 that releases oxygen when heated, as exemplified in the first embodiment, It is also possible.

[0221] 13A and 13B show a transistor 17 having a different configuration from the transistor 160. 0 is a schematic cross-sectional view.

[0222] The transistor 170 is mainly formed between the first oxide layer 151 and the first protective insulating layer 111. It differs from the transistor 160 in that it has an insulating layer 106 .

[0223] As shown in FIGS. 13A and 13B, a semiconductor layer 102, a first oxide layer 151, and The insulating layer 106 is processed into islands, and a second oxide layer 152 is provided to cover the islands. By providing the first protective insulating layer 111 on the lower side, the oxygen released by the insulating layer 106 is reduced. It can be effectively supplied to the semiconductor layer 102 via the first oxide layer 151 .

[0224] As shown in FIG. 13B, the insulating layer 106 is more likely to be covered with a thin film than the bottom surface of the insulating layer 106. The upper surface of the first protective insulating layer 111 is lowered, and the gate electrode 105 is disposed on the side of the semiconductor layer 102. As a result, the lower part of the side surface of the semiconductor layer 102 is surrounded by the insulating layer 104. The electric field generated by the gate electrode 105 is sufficient to increase the on-current of the transistor 170. Similarly, as shown in FIGS. 29(A) and 29(B), the lower surface of the oxide layer 151 can be If the bottom surface of the gate electrode 105 is lowered, the on-current of the transistor 170 is increased. This is preferable because it is possible to

[0225] 13C and 13D show transistors having a partially different configuration from the transistor 170. 1 shows a schematic cross-sectional view of a transistor 180. The transistor 180 is not processed as an island. The insulating layer 106 includes a first oxide layer 151 and a second oxide layer 152. The first oxide layer 151 and the second oxide layer 152 are made of a material having a sufficiently large band gap. Such a configuration can be realized by using

[0226] In the case of forming the transistor 180, the insulating layer 106 Then, the first oxide layer 151 and the second oxide layer 152 are etched to expose the first protective insulating layer. It is preferable to provide an area where the edge layer 111 and the second protective insulating layer 112 are in contact with each other. For example, In the region surrounded by the first protective insulating layer 111 and the second protective insulating layer 112, a plurality of transistors are formed. A configuration in which a star is provided may also be used.

[0227] As shown in FIG. 13D, the periphery of the semiconductor layer 102 is closer to the bottom surface of the semiconductor layer 102 than the bottom surface of the semiconductor layer 102. The upper surface of the first protective insulating layer 111 in the surrounding area is lowered, and the gate electrode 105 is disposed on the semiconductor layer 102. As a result, the lower part of the side surface of the semiconductor layer 102 is The electric field from the gate electrode 105 is sufficiently applied to the transistor 180 so as to increase the on-current of the transistor 180. Similarly, as shown in FIG. 29(C) and (D), If the bottom surface of the gate electrode 105 is lower than the surface of the transistor 180, the on-current of the transistor 180 is increased. This is preferable because it can increase the

[0228] [Configuration example 3] 14A and 14B are schematic cross-sectional views of a transistor 250, which will be described below. For a schematic top view, FIG. 1A can be used. The embodiment is similar to that of the first embodiment in that it mainly has a first oxide layer 251 and a second oxide layer 252. This is different from the transistor 200 illustrated in the first embodiment.

[0229] The first oxide layer 251 is provided between the first protective insulating layer 211 and the semiconductor layer 202. The second oxide layer 252 is provided between the semiconductor layer 202 and the gate insulating layer 204. It is being done.

[0230] More specifically, in the grooves provided in the insulating layer 207, the first oxide layer 251 is The first oxide layer 211 is formed on the side and the top of the first protective insulating layer 211. 51 is provided in contact with the lower surface and side surfaces of the semiconductor layer 202 .

[0231] The second oxide layer 252 has a lower surface in contact with the upper surfaces of the pair of electrodes 203. Furthermore, in the region where the pair of electrodes 203 is not provided, It is provided on the upper surface of layer 202 .

[0232] The first oxide layer 251 and the second oxide layer 252 are the same as the semiconductor layer 202. The oxides include those containing one or more of the metallic elements.

[0233] Note that the boundary between the semiconductor layer 202 and the first oxide layer 251 or the boundary between the semiconductor layer 202 and the second oxide layer 252 may be a thin film. The boundary with the oxide layer 252 may be unclear.

[0234] The first oxide layer 251 and the second oxide layer 252 may be, for example, the above-mentioned first oxide layer. Similar materials for layer 151 and second oxide layer 152 can be used.

[0235] In the configuration shown in FIG. 14, the top surface shape of the second oxide layer 252 and the gate insulating layer 204 is The same photomask is used to process the upper surface of the gate electrode 205 so that the upper surface of the gate electrode 205 roughly matches the upper surface of the gate electrode 205. In addition, the second protective insulating layer 212 is formed between the second oxide layer 252 and the gate insulating layer. The layer 204 is provided adjacent to each end of the layer 204. Oxidation occurs from the semiconductor layer 202 through the second oxide layer 252 and the edge of the gate insulating layer 204. Therefore, it is possible to suppress the desorption of elements.

[0236] As shown in FIG. 14B, the semiconductor layer 202 of the transistor 250 has a lower surface In addition, the side surface of the semiconductor layer 202 is in contact with the first oxide layer 251. is provided in contact with the second oxide layer 252. That is, the channel of the semiconductor layer 202 The formation region is surrounded by a first oxide layer 251 and a second oxide layer 252. .

[0237] With this structure, in the channel formation region of the semiconductor layer 202, Therefore, the formation of the interface state can be suppressed. This makes it possible to suppress the above problem, thereby achieving a highly reliable transistor.

[0238] Here, the thickness of the semiconductor layer 202 is formed to be at least thicker than that of the first oxide layer 251. It is preferable that the thicker the semiconductor layer 202 is, the higher the on-state current of the transistor can be. In addition, the first oxide layer 251 has the effect of suppressing the generation of interface states in the semiconductor layer 202. For example, the thickness of the semiconductor layer 202 is set to be equal to or larger than the thickness of the first oxide. The thickness of the layer 251 is more than 1 time, preferably 2 times or more, and more preferably 4 times or more. More preferably, it should be 6 times or more.

[0239] The depth of the groove provided in the insulating layer 207 is determined based on the thickness of the first protective insulating layer 211 and the thickness of the first oxide layer 212. This can be appropriately set in consideration of the thicknesses of the polymer layer 251 and the semiconductor layer 202 after processing. The width of the groove may be appropriately determined depending on the channel length and channel width of the transistor 250. Just set it.

[0240] In addition, the second oxide layer 252, like the first oxide layer 251, is also formed at the interface of the semiconductor layer 202. It is sufficient that the thickness is such that the effect of suppressing the generation of the level is not lost. For example, the first oxide The thickness of the second oxide layer 252 may be equal to or less than that of the layer 251. Since the electric field from the gate electrode 205 may not reach the semiconductor layer 202 easily, It is preferable that the second oxide layer 252 is formed thin. The thickness of 2 is determined by taking into consideration the withstand voltage of the gate insulating layer 204 and the voltage at which the transistor 250 is driven. The number of times may be set appropriately depending on the situation.

[0241] In addition, the insulating layer 206 that releases oxygen when heated, as exemplified in the first modification of the first embodiment, It can also be applied.

[0242] 14C and 14D show a transistor 27 having a different configuration from the transistor 250. 0 is a schematic cross-sectional view.

[0243] The transistor 270 is mainly formed between the first oxide layer 251 and the first protective insulating layer 211. and the semiconductor layer 202 is provided to cover the groove portion. It is different from transistor 250.

[0244] In this way, by providing the first oxide layer 251 so as to fill the groove, the channel In the formation region, the physical distance between the semiconductor layer 202 and the insulating layer 206 can be increased. Therefore, in the channel formation region, the boundary formed at the interface of the semiconductor layer 202 The surface level can be further reduced.

[0245] FIG. 15 shows a transistor 28 having a different configuration from the transistors 250 and 270. 0 in series. The transistor 280 is mainly It differs from transistor 270 in that layer 251 is provided over the trench.

[0246] In this manner, the insulating layer 206 is embedded in the groove, and the first oxide layer 251 and By providing the semiconductor layer 202, the volume of the insulating layer 206 can be easily increased. As a result, the amount of oxygen supplied to the semiconductor layer 202 can be increased. By adopting such a configuration, a step is not formed on the upper surface of the insulating layer 206. The first oxide layer 251 and the semiconductor layer 202 provided on the layer are not deteriorated in coverage. Therefore, the thickness of the insulating layer 206 can be increased.

[0247] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0248] (Embodiment 3) In this embodiment, an oxide semiconductor film that can be suitably used in a semiconductor device according to one embodiment of the present invention will be described. The conductor will now be described.

[0249] Oxide semiconductors have a large energy gap of 3.0 eV or more, making them suitable for The oxide semiconductor film obtained by processing the oxide semiconductor film under suitable conditions and sufficiently reducing the carrier density is applied. In a transistor with a low resistance, the leakage current between the source and drain in the off state (off current) can be made extremely low compared to conventional silicon-based transistors. .

[0250] The applicable oxide semiconductors include at least indium (In) or zinc (Zn It is particularly preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to gallium (Ga), tin (Sn), hafnium (Hf), and zirconium (Zr) , titanium (Ti), scandium (Sc), yttrium (Y), lanthanides (e.g. , cerium (Ce), neodymium (Nd), gadolinium (Gd), or It is preferable that one or more kinds of the amine compound are contained.

[0251] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. compounds, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg acids oxides, In-Mg oxides, In-Ga oxides, In-Ga-Zn oxides (IGZO (also written as In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga- Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Z n-based oxides, In-Zr-Zn-based oxides, In-Ti-Zn-based oxides, In-Sc-Zn In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide , In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, I n-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga- Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, I An n-Hf-Al-Zn oxide can be used.

[0252] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. The metal elements may be included.

[0253] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer In addition, M is selected from Ga, Fe, Mn, and Co. A metal element or elements, or the above-mentioned stabilizer elements. In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials represented by the formula:

[0254] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=1:3:2, In:Ga :Zn=1:3:4, In:Ga:Zn=1:3:6, In:Ga:Zn=3:1:2A Or, In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=2:1:3 and its composition It is preferable to use an oxide in the vicinity of the above.

[0255] When a large amount of hydrogen is contained in the oxide semiconductor film, the hydrogen is bonded to the oxide semiconductor. Some of the elements become donors and generate electrons, which are carriers. This causes a transistor Therefore, the threshold voltage of the oxide semiconductor film is shifted in the negative direction. After that, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film. It is preferable to remove the impurities to obtain a high purity so that the impurities are not included as much as possible.

[0256] Note that the oxide semiconductor film is dehydrated (dehydrogenated) to At the same time, oxygen may also decrease. A process of adding oxygen to an oxide semiconductor film to compensate for oxygen vacancies increased by a thermal oxidation process. In this specification and the like, when oxygen is supplied to an oxide semiconductor film, This may be referred to as oxygen addition treatment, or oxygen contained in the oxide semiconductor film may be added to the oxide semiconductor film to obtain a stoichiometric composition. When the oxygen concentration is increased beyond this range, it is sometimes referred to as hyperoxygenation treatment.

[0257] In this manner, the oxide semiconductor film is dehydrated by dehydration treatment (dehydrogenation treatment). By removing oxygen and filling the oxygen vacancies with oxygen addition treatment, the i-type (intrinsic) or The oxide semiconductor film can be an oxide semiconductor film that is nearly i-type and is substantially i-type (intrinsic). Note that the term "substantially intrinsic" means that the number of carriers derived from donors in the oxide semiconductor film is extremely small. (close to zero), carrier density is 1×10 17 / cm 3 Below, 1×10 16 / cm 3 below , 1×10 15 / cm 3 Below, 1×10 14 / cm 3 Below, 1×10 13 / cm 3 Below It says something.

[0258] In addition, a transistor including an i-type or substantially i-type oxide semiconductor film can be For example, a transistor using an oxide semiconductor film can be The drain current when the capacitor is off is 1×10 at room temperature (approximately 25°C). -18 Below A, Preferably 1 x 10 -21 A or less, more preferably 1×10 -24 A or below, or 85 1×10 at °C -15 A or less, preferably 1×10 -18 A or less, more preferably 1x 10 -21 A or less. Note that the off state of a transistor is an n-channel In the case of a transistor of this type, this refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. In general, if the gate voltage is 1V, 2V, or 3V less than the threshold voltage, , the transistor is turned off.

[0259] The structure of the oxide semiconductor film will be described below.

[0260] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystal-Oxide Semiconductor Film). (stalline oxide semiconductor) film, polycrystalline oxide semiconductor The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0261] First, we will explain the CAAC-OS film.

[0262] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle between 80° and 100°. Therefore, cases between 85° and 95° are also included.

[0263] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0264] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts aligned along the c-axis. .

[0265] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed using a quartz crystal microscope, clear boundaries between crystal parts were observed, i.e. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0266] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each layer of the CAAC-OS film is formed on a surface on which the film is to be formed (also called a surface on which the film is to be formed) or on a concave surface on the upper surface. The shape reflects a convexity, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0267] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0268] FIG. 23(a) is a cross-sectional TEM image of the CAAC-OS film. This is a cross-sectional TEM image of the same material as in 23(a), enlarged, with the atomic arrangement emphasized for ease of understanding. The tone is displayed.

[0269] Figure 23(c) shows the area surrounded by a circle (diameter approximately 4 mm) between AO and A' in Figure 23(a). From Fig. 23(c), it is clear that the c-axis orientation is In addition, the c-axis orientation is different between the A-O and O-A' sections, so the different graphs are formed. The c-axis angles between the AOs are 14.3° and 16. 6°, 26.4°, and so on. Similarly, OA Between these, the c-axis angle gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0270] In addition, when electron diffraction is performed on the CAAC-OS film, spots (bright points) indicating orientation are observed. For example, a thickness of 1 nm to 30 nm is observed on the top surface of the CAAC-OS film. When electron diffraction using an electron beam (also called nanobeam electron diffraction) is performed, spots are observed. (See FIG. 24(A)).

[0271] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that...

[0272] Most of the crystals in the CAAC-OS film are cubic with a side length of less than 100 nm. The size is small enough to fit inside the body. Therefore, the crystal part in the CAAC-OS film has a side length of 10 This includes sizes that fit within a cube of less than 3 nm, 5 nm, or 5 nm. However, multiple crystals in the CAAC-OS film are connected to form a single large crystal domain. For example, in a planar TEM image, 2 More than 5μm 2 More than or equal to 1000μm 2 In some cases, crystal regions having more than this amount may be observed.

[0273] X-ray diffraction (XRD) of CAAC-OS film When the structure was analyzed using the device, for example, CAAC-OS with InGaZnO4 crystals was In the out-of-plane analysis of the film, the diffraction angle (2θ) peaked at around 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a roughly vertical direction.

[0274] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to Even when the φ is fixed at around 56° and scanned, no clear peak appears.

[0275] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is in a plane parallel to the ab plane of the crystal.

[0276] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. For example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the face or top surface normal vector.

[0277] In addition, the distribution of the c-axis oriented crystal parts in the CAAC-OS film may not be uniform. For example, the crystals in the CAAC-OS film grow from the top surface of the CAAC-OS film. Therefore, when the crystal is formed, the region near the top surface has more c-axis oriented crystals than the region near the surface on which the crystal is formed. In addition, the proportion of the impurity part may increase in the CAAC-OS film. The region where the ZnO was added was altered, and regions with different proportions of c-axis oriented crystals were formed. This may also occur.

[0278] In addition, the out-of-plane crystal structure of the CAAC-OS film with InGaZnO4 crystals In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have the 2θ value of about 31°. It is preferable that the spectrum shows a peak at 2θ of about 36° and does not show a peak at 2θ of about 36°.

[0279] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is preferably made of silicon or a transition metal element other than the main component of the oxide semiconductor film. The elements that bond to oxygen stronger than the metal elements that form the oxide semiconductor film, such as Zn, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Since the diameter (or molecular radius) of the ions is large, when the ions are contained inside the oxide semiconductor film, the oxide semiconductor film The impurities contained in the oxide semiconductor film are disturbed, which causes a decrease in crystallinity. Pure materials may act as carrier traps or carrier generation sources.

[0280] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0281] The low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small carrier generation source, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics (noise) in which the threshold voltage is negative. It is also called "marine". It is rare for it to become "high purity genuine" or "substantially high purity". The intrinsic oxide semiconductor film has few carrier traps. Transistors using the film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time is long and the charge may behave as if it were a fixed charge. In addition, a transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. There may be cases where this occurs.

[0282] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0283] Next, a microcrystalline oxide semiconductor film will be described.

[0284] In the TEM image of the microcrystalline oxide semiconductor film, crystal parts can be clearly seen. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 to 3 nm or less. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called a T In EM images, grain boundaries may not be clearly visible.

[0285] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts, and therefore no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, XRD, which uses X-rays with a diameter larger than that of the crystal part, is used for nc-OS films. When structural analysis is performed using the out-of-plane method, the crystal planes are In addition, the peaks shown in the figure are not detected in the nc-OS film because the probe diameter is larger than that in the crystalline region. Electron diffraction (also called selected area electron diffraction) is performed using an electron beam (e.g., 50 nm or larger). On the other hand, for the nc-OS film, Nanobeam electron circuit using an electron beam with a probe diameter close to or smaller than the size of the crystal part. In addition, nanobeam electron diffraction was performed on the nc-OS film. When the image is taken, a circular (ring-shaped) area of ​​high brightness may be observed. When nanobeam electron diffraction was performed on the c-OS film, multiple spots were observed within the ring-shaped region. It may be measured.

[0286] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, the crystal orientation is not regular between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0287] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of AAC-OS films.

[0288] When an oxide semiconductor film has multiple structures, the structures can be resolved by using nanobeam electron diffraction. In some cases, analysis may be possible.

[0289] FIG. 24C shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and the optical system 12 below the optical system 12. a sample chamber 14, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, and an observation A transillumination system having a camera 18 installed in a chamber 20 and a film chamber 22 below the observation chamber 20. The figure shows a device for measuring electron diffraction. The camera 18 is installed facing the inside of the observation chamber 20. The room chamber 22 may not be provided.

[0290] FIG. 24(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 24(C). Inside the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 10 is irradiated onto a substance 28 placed in the sample chamber 14 via the optical system 12. The electrons are incident on a fluorescent screen 32 installed inside the observation chamber 20 via the optical system 16. On the light plate 32, a pattern appears according to the intensity of the incident electrons, which is called a transmission electron diffraction pattern. It is possible to measure the

[0291] The camera 18 is installed facing the fluorescent screen 32 and captures the pattern appearing on the fluorescent screen 32. It is possible to capture an image of the object by a straight line passing through the center of the lens of the camera 18 and the center of the fluorescent screen 32. The angle between the line and the upper surface of the fluorescent screen 32 is, for example, 15° to 80°, or 30° to 40°. The smaller the angle, the more accurate the image captured by the camera 18. However, if the angle is known in advance, the resulting transmission electron diffraction pattern will be significantly distorted. If the TEM image is obtained, it is possible to correct the distortion of the transmission electron diffraction pattern. In some cases, the camera 18 may be placed in the film chamber 22. The fluorescent screen may be installed in the room chamber 22 so as to face the direction of incidence of the electrons 24. A transmission electron diffraction pattern with little distortion can be captured from the back surface of the sample.

[0292] A holder for fixing a substance 28, which is a sample, is installed in the sample chamber 14. The holder is structured to be transparent to electrons passing through the material 28. The holder may have a function of moving the holder 28 in the X-axis, Y-axis, Z-axis, etc. For example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less m or less, 50 nm to 500 nm, 100 nm to 1 μm, etc. These ranges can be set optimally depending on the structure of the substance28. Good.

[0293] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. The method will be explained.

[0294] For example, as shown in FIG. 24(D), the irradiation position of the electron 24, which is a nanobeam, on the material By changing (scanning) the temperature, it is possible to observe how the structure of a substance changes. In this case, if the substance 28 is a CAAC-OS film, the structure shown in FIG. If the material 28 is an nc-OS film, the diffraction pattern is shown in FIG. 24(B). The diffraction pattern shown is observed.

[0295] By the way, even if material 28 is a CAAC-OS film, it may be partially composed of nc-OS film, etc. Therefore, the quality of the CAAC-OS film can be judged by the following: , the ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CAA For example, in a high-quality CAAC-OS film, If present, the CAAC ratio is 50% or more, preferably 80% or more, and more preferably 90% or more. The diffraction pattern is different from that of the CAAC-OS film. The area where this is observed is denoted as the non-CAAC rate.

[0296] As an example, the film is formed immediately after (denoted as-sputtered) or in an atmosphere containing oxygen. The top surface of each sample with CAAC-OS film after the heat treatment at 450 °C in air was scanned. Transmission electron diffraction patterns were obtained while scanning the sample at a speed of 5 nm / s for 60 s. The diffraction pattern was observed while scanning, and the observed diffraction pattern was captured as still images every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the A nano-beam of 1.5 m was used. The same measurements were performed on six samples. The rate was calculated using the average value of six samples.

[0297] The CAAC ratio in each sample is shown in FIG. The AAC ratio was 75.7% (non-CAAC ratio was 24.3%). The CAAC content of the treated CAAC-OS membrane was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after heat treatment at 450°C than immediately after film formation. That is, the non-CAAC ratio is reduced by heat treatment at a high temperature (e.g., 400°C or higher). In addition, the CAAC content is increased when the temperature is heated below 500°C. It can be seen that a CAAC-OS membrane with a high CAAC content can be obtained even with

[0298] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. The pattern was a folded pattern. In addition, the amorphous oxide semiconductor film was not observed in the measurement area. Therefore, the heat treatment could not produce a region with a structure similar to that of the nc-OS film. However, it is suggested that the structure of the neighboring domains influences the rearrangement of the CAAC domain. .

[0299] 25(B) and 25(C) show the CAAC- 25(B) and 25(C) are planar TEM images of the OS film. It can be seen that the CAAC-OS film after the 50°C heat treatment has a more homogeneous film quality. It can be seen that the film quality of the CAAC-OS film is improved by the heat treatment at a low temperature.

[0300] Using this measurement method, it is possible to analyze the structure of oxide semiconductor films with multiple structures. This may be the case.

[0301] (Embodiment 4) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. The description will be given with reference to the surface.

[0302] FIG. 16(A) shows a circuit diagram of the semiconductor device, and FIGS. 16(C) and 16(D) show cross-sectional views of the semiconductor device. 16(C) and (D) show, on the left side, the channel of the transistor 100. A cross-sectional view in the longitudinal direction is shown on the right, and a cross-sectional view in the channel width direction is shown on the right. To clarify that the transistor uses an oxide semiconductor, the word "OS" is added. It is attached.

[0303] The semiconductor device shown in FIG. 16(C) and (D) has a transistor using a first semiconductor material in the lower part. 2200 and a transistor using a second semiconductor material on the top. As a transistor using the second semiconductor material, the transistor exemplified in the first embodiment may be used. An example in which 100 is applied will be described.

[0304] In addition, in Fig. 17(A) and (B), a transistor using the second semiconductor material is shown. 1 shows an example of a cross-sectional structure in the case where the transistor 200 described in Embodiment 1 is used.

[0305] Here, the first semiconductor material and the second semiconductor material have different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon, ruthenium, silicon germanium, silicon carbide, or gallium arsenide, etc.) The second semiconductor material can be the oxide semiconductor described in Embodiment 1. Transistors that use single crystal silicon as a non-conductor material are easy to operate at high speeds. On the other hand, a transistor including an oxide semiconductor has a low off-state current.

[0306] Here, the transistor 2200 is described as a p-channel transistor. However, it goes without saying that different circuits can be constructed using n-channel transistors. In addition, the transistor using an oxide semiconductor as described in Embodiment 1 is not used. The specific configuration of the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, is described below. There is no need to be limited to what is shown here.

[0307] The configurations shown in Figures 16(A), (C), and (D) are p-channel transistors and n-channel A so-called CM type transistor is connected in series and the gates of each transistor are connected. 2 illustrates an example of the configuration of an OS circuit.

[0308] The on-state current of a transistor including an oxide semiconductor according to one embodiment of the present invention is increased. This enables the circuit to operate at high speed.

[0309] In the structure shown in FIG. 16C, a transistor 2200 is provided with an insulating layer 2201 therebetween. The transistor 100 is provided between the transistor 2200 and the transistor 1 A plurality of wirings 2202 are provided between the electrodes 2200. Also, a plurality of wirings 2202 are embedded in various insulating layers. The plugs 2203 electrically connect the wiring and electrodes provided on the upper and lower layers. In addition, an insulating layer 2204 that covers the transistor 100 and a wiring layer 2204 are provided on the insulating layer 2204. 2205 and a wiring 220 formed by processing the same conductive film as the pair of electrodes of the transistor. 6 and are provided.

[0310] In this way, by stacking two transistors, the area occupied by the circuit is reduced, Multiple circuits can be arranged at higher density.

[0311] In FIG. 16C, one of the source and drain of the transistor 100 and the transistor Either the source or drain of the capacitor 2200 is electrically connected to the The gate of the transistor 100 is connected to the wiring 2205 and the wiring 220 6. The gate of the transistor 2200 is connected to the plug 2203 and the wiring 2202 via the plug 2203 and the wiring 2202. and is electrically connected to

[0312] In the structure shown in FIG. 16D, a plug 2203 is formed in the gate insulating layer of the transistor 100. An opening for embedding is provided, and the gate of the transistor 100 and the plug 2203 are connected. This configuration not only makes it easier to integrate circuits, 16(C) , the number and length of wiring and plugs to be passed through can be reduced. , the circuit can be operated at a higher speed.

[0313] Here, in the configurations shown in FIGS. 16C and 16D, the transistor 100 and the transistor By changing the connection configuration of the electrodes of the capacitor 2200, various circuits can be configured. For example, as shown in FIG. 16(B), the source and drain of each transistor are connected. By connecting the two circuits, it can function as an analog switch. Cut.

[0314] In addition, the transistor shown in either the first or second embodiment may be used to A semiconductor device having an image sensor function for reading information can be manufactured.

[0315] FIG. 18 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0316] The photodiode 602 has one electrode connected to a photodiode reset signal line 658. The other electrode is electrically connected to the gate of transistor 640. 0 indicates that either the source or the drain is connected to the photosensor reference signal line 672, The other end of the input terminal is electrically connected to one of the source and drain of the transistor 656 . The transistor 656 has a gate connected to a gate signal line 659 and the other of the source and drain connected to a floating gate. It is electrically connected to the photo sensor output signal line 671 .

[0317] The photodiode 602 includes, for example, a semiconductor layer having a p-type conductivity and a high-resistance ( A pin type in which a semiconductor layer having an i-type conductivity and a semiconductor layer having an n-type conductivity are stacked. A photodiode of the above type can be applied.

[0318] By detecting the light incident on the photodiode 602, information on the detected object is read. When reading the information of the detected object, a light source such as a backlight is used. There can be.

[0319] Note that the transistor 640 and the transistor 656 may be the same as those described in either of Embodiments 1 and 2. A transistor in which a channel is formed in an oxide semiconductor, as shown in the example above, can be used. In FIG. 18, the transistor 640 and the transistor 656 include an oxide semiconductor. To make this clear, the transistor symbol is marked with "OS."

[0320] The transistor 640 and the transistor 656 are the same as those shown in the above embodiment. The oxide semiconductor layer in which the channel is formed is made of aluminum oxide containing excess oxygen. The oxide semiconductor layer is surrounded by an insulating layer including a silicon film. Therefore, the transistor 640 and the transistor The transistor 656 is an electrically stable transistor in which fluctuations in electrical characteristics are suppressed. By including a transistor, a semiconductor device having an image sensor function as shown in FIG. A highly reliable semiconductor device can be provided.

[0321] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0322] (Embodiment 5) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor that is not supplied with power is used. A semiconductor device (memory device) that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. An example of the apparatus will be described with reference to the drawings.

[0323] FIG. 19 shows a circuit diagram of the semiconductor device.

[0324] The semiconductor device shown in FIG. 19 includes a transistor 3200 using a first semiconductor material and a second The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 may be any of the transistors described in the above embodiment. can be done.

[0325] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The off-state current of the transistor 3300 is small, so that the transistor 3300 can be used. It is possible to retain memory contents for a longer period of time, i.e., no refresh operation is required. To provide a semiconductor memory device that does not require a refresh operation or requires an extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0326] In FIG. 19, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain electrode of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the gate electrodes of the transistor 3300. The gate electrode of the transistor 3200 and the The other of the source electrode and the drain electrode of the transistor 3300 is an electrode of the capacitor 3400. The fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400. are actively connected.

[0327] In the semiconductor device shown in FIG. 19, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows.

[0328] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is Then, a certain charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By setting the transistor 3300 in the off state, the The charge applied to the gate electrode is retained (retention).

[0329] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrodes is maintained for a long period of time.

[0330] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode of th_ H The figure shows the state when a low-level charge is applied to the gate electrode of the transistor 3200. Threshold V th_L The apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0 at the gate electrode of the transistor 3200, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V0 (>V th_H), then transistor 3200 is When a low-level charge is applied, the fifth wiring 3005 is in the "ON state". If the potential is V0( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0331] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 remains "on," that is, V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0332] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0333] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating layer does not occur at all. In a physical device, there is no limit to the number of times data can be rewritten, which is a problem with conventional non-volatile memory. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the data is written in a single bit, high speed operation can be easily achieved.

[0334] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0335] (Embodiment 6) In this embodiment, at least the transistors described in the embodiment can be used. Next, a CPU including the storage device described in the above embodiment will be described.

[0336] FIG. 20 shows a CPU using the transistor described in the first embodiment as at least a part thereof. FIG. 1 is a block diagram showing a configuration of an example.

[0337] The CPU shown in FIG. 20 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 20 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 20 is regarded as one core, and the core is divided into multiple The CPU may also be configured to include a processor core and each core may operate in parallel. The number of bits that can be handled by a computing circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0338] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0339] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads or writes register 1196 depending on the CPU state. .

[0340] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0341] In the CPU shown in FIG. 20, a memory cell is provided in the register 1196. The transistors shown in the above embodiments can be used as memory cells of the memory cell 1196. Cut.

[0342] In the CPU shown in FIG. 20, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0343] FIG. 21 is a circuit diagram of an example of a memory element that can be used as the register 1196. The memory element 700 includes a circuit 701 in which stored data is volatilized when the power is cut off, and a circuit 702 in which stored data is volatilized when the power is cut off. A circuit 702 in which data is not volatile, a switch 703, a switch 704, and a logic element 706 The circuit 702 includes a capacitor 707 and a circuit 720 having a selection function. The memory element 708 includes a transistor 709 and a transistor 710. The element 700 may further include other elements such as diodes, resistors, and inductors as necessary. It may also have.

[0344] Here, the memory device described in the above embodiment can be used for the circuit 702. When the supply of the power supply voltage to the memory element 700 is stopped, the gate of the transistor 709 in the circuit 702 is turned off. The ground potential (0V) or a potential that turns off the transistor 709 is continuously input to the output. For example, the gate of the transistor 709 is grounded via a load such as a resistor. It is completed.

[0345] The switch 703 is implemented by using a transistor 713 of one conductivity type (for example, an n-channel type). The switch 704 is configured to have a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first terminal of the switch 703 is a transistor 714. The second terminal of the switch 703 corresponds to one of the source and drain of the transistor 713. The switch 703 corresponds to the other of the source and drain of the transistor 713. A control signal RD input to the gate of the third transistor controls the conduction or non-conduction between the first and second terminals. The switch 713 is turned off (i.e., the on or off state of the transistor 713). The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714. The second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714. The first terminal of the switch 704 is turned on by a control signal RD input to the gate of the transistor 714. Conduction or non-conduction between the first terminal and the second terminal (i.e., the on or off state of the transistor 714) OFF state) is selected.

[0346] One of the source and drain of the transistor 709 is connected to one of the pair of electrodes of the capacitor 708. and the gate of the transistor 710. The node M2 ​​is connected to one of the source and drain of the transistor 710, which is supplied with a low potential power supply. The other is electrically connected to a wiring (for example, a GND line) that can be connected to a switch 703 The first terminal (one of the source and the drain of the transistor 713) is electrically connected to the first terminal of the transistor 713. The second terminal of the switch 703 (the other of the source and drain of the transistor 713) 704 (one of the source and drain of the transistor 714) The second terminal of the switch 704 (the other of the source and drain of the transistor 714) The switch 703 is electrically connected to a wiring that can supply a power supply potential VDD. A second terminal (the other of the source and drain of the transistor 713) and a first terminal of the switch 704 (one of the source and drain of the transistor 714) and the input terminal of the logic element 706 is electrically connected to one of a pair of electrodes of the capacitor 707. The other of the pair of electrodes of the capacitor 707 is a node M1. For example, a low power supply potential (GND, etc.) or a high power supply potential ( VDD or the like) can be input to one of the pair of electrodes of the capacitor 707. The other is electrically connected to a wiring that can supply a low potential power supply (for example, a GND line). A constant potential is input to the other of the pair of electrodes of the capacitor 708. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 708 can be connected to a low potential power supply. It is electrically connected to a wiring that can supply power (for example, a GND line).

[0347] The capacitors 707 and 708 are formed by accumulating parasitic capacitances of transistors and wirings. It is possible to omit it by using it in an extreme manner.

[0348] A control signal WE is input to a first gate (first gate electrode) of the transistor 709. The switches 703 and 704 are controlled by a control signal RD that is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by the When the first terminal and the second terminal of the switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no continuity between the terminals.

[0349] The other of the source and drain of the transistor 709 is connected to the data held in the circuit 701. In FIG. 21, the signal output from the circuit 701 is input to the transistor The second terminal of the switch 703 is connected to the other of the source and drain of the switch 709. The signal output from the other terminal of the transistor 713 (the other of the source and drain of the transistor 713) is The logic value of the inverted signal is inverted by the invertor 06 and is sent to the circuit 701 via the circuit 720. is entered.

[0350] In FIG. 21, the second terminal of the switch 703 (the source and drain of the transistor 713) The signal output from the other input is input to the circuit 70 via the logic element 706 and the circuit 720. 1 is an example of inputting the signal to the second terminal (transistor The signal output from the other of the source and drain of the transistor 713 is inverted in logic value. For example, the input from the input terminal may be input to the circuit 701 without being input to the circuit 701. When there is a node that holds a signal with the logic value of the signal input to the switch 70 inverted, A signal output from the second terminal of the third input terminal (the other of the source and drain of the transistor 713) is It can be input to the node.

[0351] The transistor 709 in FIG. 21 is the transistor described in Embodiment 1. In addition, the second gate ( It is preferable that the first gate has a control signal WE. The first gate can receive a control signal WE2, and the second gate can receive a control signal WE3. The constant potential may be, for example, a ground potential GND or a transistor potential. A potential smaller than the source potential of transistor 709 is selected. This is a potential signal for controlling the threshold voltage of the transistor 709. The transistor 709 has a second gate. It is also possible to use transistors that do not

[0352] In addition, in FIG. 21, among the transistors used in the memory element 700, The transistors other than the transistor 709 are formed on a layer or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor having a channel formed in a silicon layer or The memory element 7 can be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the semiconductor device 100 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 700 may include a transistor other than the transistor 709. The remaining transistors may include a transistor formed of an oxide semiconductor layer. The transistor is a transistor in which a channel is formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor.

[0353] For example, a flip-flop circuit can be used for the circuit 701 in FIG. The logic element 706 may be, for example, an inverter or a clocked inverter. This can be done.

[0354] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 700, The data stored in the circuit 701 is transferred to the capacitor 708 in the circuit 702. It can be held by this.

[0355] In addition, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer varies depending on the crystallinity. The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using this transistor as the transistor 709, the memory element 7 Even when power supply voltage is not supplied to the capacitor 700, the signal held in the capacitor 708 is maintained for a long period of time. In this way, the memory element 700 retains its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold

[0356] In addition, by providing the switches 703 and 704, the precharge operation Since the memory element is characterized by performing the above, the circuit 701 is restored to the original state after the power supply voltage is restarted. This shortens the time it takes to re-hold the data.

[0357] In the circuit 702, the signal held by the capacitor 708 is 10. Therefore, the supply of the power supply voltage to the memory element 700 is resumed. After that, the signal held by the capacitor 708 is transferred to the transistor 710 (on state, or off state) and can be read out from the circuit 702. Even if the potential corresponding to the signal held in 708 fluctuates slightly, the original signal can be read out accurately. It is possible to do so.

[0358] Such a memory element 700 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0359] In this embodiment, the memory element 700 is used as a CPU. 00 is DSP (Digital Signal Processor), Custom LS I, LSI such as PLD (Programmable Logic Device), RF -Can also be applied to ID (Radio Frequency Identification) It is Noh.

[0360] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0361] (Embodiment 7) In this embodiment, the transistor, the memory device, or the CPU described in the above embodiment Use of semiconductor devices such as DSP, custom LSI, PLD, RF-ID, etc. Next, an example of an electronic device that can be used with the above-mentioned configuration will be described.

[0362] The transistors, memory devices, CPUs, and the like exemplified in the above embodiments can be used in various applications. It can be applied to child devices (including gaming machines). Electronic devices include televisions, monitors, etc. display devices, lighting devices, personal computers, word processors, image reproducing devices, portable audio players, radios, tape recorders, stereos, telephones, cordless telephones telephones, mobile phones, car phones, transceivers, radios, game consoles, calculators, personal digital assistants, Child notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, Electric shavers, IC chips, microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, Vacuum cleaners, air conditioning equipment such as air conditioners, dishwashers, dish dryers, clothes dryers dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for DNA storage, radiation Radiation measuring devices, dialysis machines, X-ray diagnostic equipment, and other medical equipment. Smoke detectors, Examples of alarm devices include heat detectors, gas alarm devices, and security alarm devices. Traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems In addition, fuel-powered engines and non-aqueous secondary batteries are also used. Mobile objects propelled by electric motors using force are also included in the category of electronic devices. Examples of the above-mentioned vehicles include electric vehicles (EVs) and hybrid vehicles that combine internal combustion engines and electric motors. Hybrid electric vehicles (HEV), plug-in hybrid electric vehicles (PHEV), and these tire wheels are Tracked vehicles converted to limited tracks, motorized bicycles including electrically assisted bicycles, motorcycles, electric vehicles Wheelchairs, golf carts, small or large boats, submarines, helicopters, aircraft, rockets Some of these electronic devices include satellites, space probes, planetary probes, and spacecraft. A specific example is shown in FIG.

[0363] A television set 8000 shown in FIG. 22A includes a housing 8001 and a display unit 8002. It displays images on a display unit 8002 and outputs sound from a speaker unit 8003. The transistors described in the above embodiments can be assembled in a housing 8001. The semiconductor laser can be used in a driver circuit or pixel for operating the display unit 8002. .

[0364] The display unit 8002 is a light-emitting device having light-emitting elements such as a liquid crystal display device or an organic EL element in each pixel. Device, electrophoretic display device, DMD (Digital Micromirror Devi ce) and PDP (Plasma Display Panel) and other semiconductor display devices. There can be.

[0365] The television device 8000 may include a receiver, a modem, and the like. The device 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via The communication of information is carried out in a two-way manner (from sender to receiver, or between receivers, etc.) or in a two-way manner (between sender and receiver, or between receivers, etc.) It is also possible to do so.

[0366] The television device 8000 also includes a CPU 8004 for performing information communication, a memory The CPU 8004 and the memory may include the transistors shown in the above embodiments. , a storage device, or a CPU can be used to reduce power consumption.

[0367] The alarm device 8100 shown in FIG. 22(A) is a residential fire alarm, and detects smoke or heat. 8 is an example of an electronic device using a microcomputer 8101 and a power supply 8102. The computer 8101 may include a transistor, a memory device, or a CP Contains U.

[0368] In addition, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in FIG. The scanner may be a power supply including the transistor, memory device, or CPU described in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, In FIG. 22A, the CPU 8203 controls the indoor unit 8200. In the illustrated example, the CPU 8203 is provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The transistor shown in the above embodiment may be used as a CP of an air conditioner. By using U, power consumption can be reduced.

[0369] In addition, an electric refrigerator-freezer 8300 shown in FIG. 22(A) is the same as the transistor shown in the above embodiment. An example of an electronic device that includes a resistor, a memory device, or a CPU, etc. The storage unit 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, and a CPU 83 In FIG. 22A, a CPU 8304 is provided inside a housing 8301. The transistor described in the above embodiment is used as the CPU 830 of the electric refrigerator-freezer 8300. By using 4, power saving can be achieved.

[0370] 22B and 22C show an example of an electric vehicle, which is an example of an electronic device. The power of the secondary battery 9701 is supplied to the circuit 9 The output is adjusted by 702 and supplied to a driver 9703. The processor 9704 has a ROM, RAM, CPU, etc. that are not included in the above description. By using the transistor shown in the embodiment in the CPU of the electric vehicle 9700, power saving is achieved. This will help to strengthen our operations.

[0371] The driving device 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine. The processing device 9704 is configured in combination with the operation of the driver of the electric vehicle 9700. Information (acceleration, deceleration, stopping, etc.) and driving information (uphill, downhill, etc., information on the driving wheels) The circuit 970 outputs a control signal to the circuit 9702 based on input information (load information, etc.). 2 is a secondary battery 9701 that is supplied with electric energy in response to a control signal from a processing device 9704. The output of the drive unit 9703 is controlled by adjusting the gear ratio. If an AC motor is installed, Although not shown, an inverter for converting direct current to alternating current is also built in.

[0372] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done. [Explanation of symbols]

[0373] 100 transistors 101 Substrate 102 Semiconductor layer 103 Electrode 104 Gate insulation layer 105 Gate electrode 106 Insulating Layer 111 Protective insulation layer 112 Protective insulation layer 120 Capacitive element 124 Dielectric layer 125 electrode 150 Transistors 151 Oxide layer 152 Oxide layer 160 Transistors 170 Transistors 180 Transistors 200 Transistors 201 Substrate 202 Semiconductor layer 203 Electrode 204 Gate insulating layer 205 Gate electrode 206 Insulating Layer 207 Insulating Layer 211 Protective insulation layer 212 Protective insulation layer 220 Capacitive element 224 Dielectric layer 225 Electrode 250 Transistors 251 Oxide layer 252 Oxide layer 260 Transistors 270 Transistors 280 Transistors 602 Photodiode 640 Transistor 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photo sensor output signal line 672 Photosensor reference signal line 700 memory elements 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic Elements 707 Capacitive element 708 Capacitive element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 2200 Transistor 2201 Insulating layer 2202 Wiring 2203 Plug 2204 Insulating layer 2205 Wiring 2206 Wiring 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8004 CPU 8100 Alarm device 8101 Microcomputers 8102 Detector 8200 indoor unit 8201 Case 8202 Ventilator 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Case 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicle 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing Equipment

Claims

1. performing a CMP process on the indium oxide so that the indium oxide, which is an oxide semiconductor, remains in the groove of the insulating layer having the groove; The indium oxide is used as a channel forming region of a transistor. A method for manufacturing a semiconductor device.

2. A groove is formed in the insulating layer; forming indium oxide, which is an oxide semiconductor, on the insulating layer so as to fill the groove; The indium oxide is subjected to a CMP process so that the indium oxide remains in the groove portion; The indium oxide is used as a channel forming region of a transistor. A method for manufacturing a semiconductor device.

3. A groove is formed in the insulating layer; forming a protective insulating layer on the insulating layer; forming indium oxide, which is an oxide semiconductor, on the protective insulating layer so as to fill the groove; The indium oxide is subjected to a CMP process so that the indium oxide remains in the groove portion; The indium oxide is used as a channel forming region of a transistor. A method for manufacturing a semiconductor device.

4. In any one of claims 1 to 3, forming a gate insulating layer on the indium oxide; forming a gate electrode on the gate insulating layer; A method for manufacturing a semiconductor device.

5. an insulating layer having a groove; an oxide semiconductor layer located on the insulating layer and embedded in the groove; a gate insulating layer on the oxide semiconductor layer; a gate electrode overlapping the oxide semiconductor layer via the gate insulating layer; the oxide semiconductor layer contains indium oxide, the oxide semiconductor layer has a channel formation region of a transistor; Semiconductor device.

6. an insulating layer having a groove; a first protective insulating layer provided so as to cover a side surface and a bottom surface of the groove; an oxide semiconductor layer provided on the first protective insulating layer so as to be embedded in the groove; a gate insulating layer on the oxide semiconductor layer; a gate electrode overlapping the oxide semiconductor layer via the gate insulating layer; the oxide semiconductor layer contains indium oxide, the oxide semiconductor layer has a channel formation region of a transistor; Semiconductor device.

7. an insulating layer having a groove; a first protective insulating layer provided so as to cover a side surface and a bottom surface of the groove; an oxide semiconductor layer provided on the first protective insulating layer so as to be embedded in the groove; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; a gate insulating layer located on the source electrode and the drain electrode and overlapping the oxide semiconductor layer; a gate electrode overlapping the oxide semiconductor layer via the gate insulating layer; a second protective insulating layer covering the source electrode, the drain electrode, and the gate electrode; the first protective insulating layer and the second protective insulating layer have a region where they contact each other in a region where the source electrode, the drain electrode, and the gate electrode are not present, the oxide semiconductor layer contains indium oxide; Semiconductor device.

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