Display device

Abstract

To provide a display device capable of suppressing degradation of display quality.SOLUTION: A display device includes a substrate 10, a first insulating layer 11 disposed on the substrate, a second insulating layer 12 including a first lower electrode E11 and a second lower electrode E12 disposed on the first insulating layer, a first opening disposed on the first insulating layer and overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a first trench T12 positioned between the first opening and the second opening, an organic layer OR including a light-emitting layer, and an upper electrode E2 covering the organic layer, and the first trench has a bottom surface and first and second side surfaces rising from the bottom surface, and a distance between the first side surface and the second side surface at a top part of the first trench is smaller than a distance between the first side surface and the second side surface on the bottom surface of the first trench.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present embodiment relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. The display element has an organic layer between a pixel electrode and a common electrode. The organic layer includes a light-emitting layer as well as functional layers such as a hole transport layer and an electron transport layer. Such an organic layer is formed, for example, by a vacuum deposition method. It is desirable to arrange the organic layer separately for each pixel in order to suppress crosstalk between adjacent pixels, for example. For example, a method of forming an organic layer separately for each pixel by a deposition method without using a mask is being considered. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-135325 A [Patent Document 2] JP 2009-244527 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present embodiment is to provide a display device capable of suppressing degradation in display quality. [Means for solving the problem]

[0005] According to the present embodiment, a semiconductor device includes a substrate, a first insulating layer disposed on the substrate, a first lower electrode and a second lower electrode disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a first trench located between the first opening and the second opening, an organic layer including a light-emitting layer, and an upper electrode covering the organic layer, wherein the first trench has a bottom surface, and first and second side surfaces rising from the bottom surface, and the first side surface and the front surface of the upper portion of the first trench are spaced apart from each other. a distance between the first side and the second side is smaller than a distance between the first side and the second side at the bottom surface of the first trench, and the organic layer has a first portion covering the first lower electrode located at the first opening and covering a first surface of the second insulating layer located between the first trench and the first opening, a second portion covering the second lower electrode located at the second opening and covering a second surface of the second insulating layer located between the first trench and the second opening, and a third portion arranged on the bottom surface of the first trench and spaced apart from the first and second portions. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a configuration example of a display device according to this embodiment. [Diagram 2] FIG. 2 is a plan view showing a pixel. [Diagram 3] FIG. 3 is a cross-sectional view of the display device taken along the line AA' shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing the trenches, organic layers, etc. [Diagram 5] FIG. 5 is a plan view showing the organic layer. [Figure 6] FIG. 6 is a cross-sectional view of the display device taken along the line BB' shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a first modified example of this embodiment. [Figure 8] FIG. 8 is a plan view showing a second modified example of the present embodiment. [Figure 9] FIG. 9 is a plan view showing a third modified example of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the present embodiment will be described with reference to the drawings. Note that the disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in terms of width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0008] The display device DSP according to this embodiment is an organic electroluminescence display device having organic light emitting diodes (OLED) as display elements, and is mounted on televisions, personal computers, mobile terminals, mobile phones, and the like.

[0009] FIG. 1 is a plan view showing an example of the configuration of a display device DSP according to this embodiment. The first direction X, the second direction Y, and the third direction Z shown in the figure are mutually orthogonal. The first direction X, the second direction Y, and the third direction Z may intersect at an angle other than 90 degrees. In this specification, the direction toward the tip of the arrow indicating the third direction Z is referred to as "up", and the direction in the opposite direction from the tip of the arrow is referred to as "down". In addition, it is assumed that there is an observation position for observing the display device DSP at the tip side of the arrow indicating the third direction Z, and viewing from this observation position toward the XY plane defined by the first direction X and the second direction Y is referred to as planar viewing.

[0010] The display device DSP includes an insulating substrate 10. The substrate 10 may be glass or a flexible resin film. The display device DSP also includes a display area DA for displaying an image, and a non-display area NDA surrounding the display area DA.

[0011] The display device DSP includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y in a display area DA. Each pixel PX includes a plurality of sub-pixels SP1, SP2, and SP3. In one example, the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Note that the pixel PX may include four or more sub-pixels including sub-pixels of other colors such as white in addition to the above three sub-pixels.

[0012] An example of the configuration of one sub-pixel SP included in a pixel PX will be briefly described. That is, the subpixel SP includes a pixel circuit 1 and a display element 20 whose driving is controlled by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements constituted by, for example, thin film transistors.

[0013] With respect to the pixel switch 2, the gate electrode is connected to the scanning line GL, the source electrode is connected to the signal line SL, and the drain electrode is connected to one electrode constituting the capacitor 4 and the gate electrode of the drive transistor 3. With respect to the drive transistor 3, the source electrode is connected to the other electrode constituting the capacitor 4 and the power line PL, and the drain electrode is connected to the anode of the display element 20. The cathode of the display element 20 is connected to the power supply line FL. Note that the configuration of the pixel circuit 1 is not limited to the example shown in the figure.

[0014] The display element 20 is an organic light-emitting diode (OLED) that is a light-emitting element. For example, the subpixel SP1 includes a display element that emits light corresponding to a red wavelength, the subpixel SP2 includes a display element that emits light corresponding to a green wavelength, and the subpixel SP3 includes a display element that emits light corresponding to a blue wavelength. The configuration of the display element 20 will be described later.

[0015] The display device DSP includes power lines 51 and 52 located in the non-display area NDA, a plurality of peripheral electrodes 6, and pads PD1 and PD2. The non-display area NDA also includes a first area N1 and a second area N2 extending in the second direction Y, and a third area N3 extending in the first direction X. The first area N1, the display area DA, and the second area N2 are arranged in this order in the first direction X. A flexible wiring board (not shown) is mounted in the third area N3. The power line 51 is located in the first region N1, and the power line 52 is located in the second region N2. The peripheral electrodes 6 are arranged in the second direction Y in each of the first region N1 and the second region N2. The pads PD1 and PD2 are located in the third region N3. The power supply line 51 is electrically connected to a plurality of peripheral electrodes 6 located in the first region N1. The power supply line 51 is also electrically connected to a pad PD1. The power supply line 52 is electrically connected to a plurality of peripheral electrodes 6 located in the second region N2. The power supply line 52 is also electrically connected to a pad PD2.

[0016] FIG. 2 is a plan view showing the pixel PX. In FIG. 2, lower electrodes E11, E12, and E13 and an insulating layer 12 provided in the display device DSP are illustrated.

[0017] The lower electrode (first lower electrode) E11 is disposed in the subpixel SP1. The lower electrode (second lower electrode) E12 is disposed in the subpixel SP2. The lower electrode E13 is disposed in the subpixel SP3. The lower electrodes E11 to E13 are aligned in the first direction X. The lower electrodes including the lower electrodes E11 to E13 are electrodes disposed for each subpixel or each display element, and may be referred to as pixel electrodes, anodes, etc.

[0018] The insulating layer 12 is formed in a lattice shape in a plan view. The insulating layer 12 is formed to partition the display elements or sub-pixels, and may be called a rib, a partition wall, or the like. The insulating layer 12 has a first opening OP1 overlapping the lower electrode E11, a second opening OP2 overlapping the lower electrode E12, and a third opening OP3 overlapping the lower electrode E13. The insulating layer 12 covers the periphery of each of the lower electrodes E11 to E13, and the center of each of the lower electrodes E11 to E13 is exposed from the insulating layer 12 at the first opening OP1, the second opening OP2, and the third opening OP3.

[0019] The insulating layer 12 also has trenches T11, T12, T13, and T14 extending in the second direction Y and aligned in the first direction X, and trenches T21 and T22 extending in the first direction X and aligned in the second direction Y. The trench (first trench) T12 is located between the first opening OP1 and the second opening OP2. The trench T13 is located between the second opening OP2 and the third opening OP3. The trench T11 is located on the opposite side of the trench T12 across the first opening OP1. The trench T14 is located on the opposite side of the trench T13 across the third opening OP3. The trench T21 is connected to the trenches T11 to T14. The trench T22 is also connected to the trenches T11 to T14. The trench T21 is located on the opposite side to the trench T22 across the first opening OP1, the second opening OP2, and the third opening OP3.

[0020] Each trench does not overlap with the adjacent lower electrode in a plan view. The lower electrode E11 is located between the trenches T11 and T12, the lower electrode E12 is located between the trenches T12 and T13, and the lower electrode E13 is located between the trenches T13 and T14. The lower electrodes E11 to E13 are located between the trenches T21 and T22.

[0021] Here, the outer shape of the subpixel corresponds to, for example, the outer shape of the lower electrode. That is, the subpixels SP1, SP2, and SP3 constituting one pixel PX are each formed in a substantially rectangular shape extending in the second direction Y, and are aligned in the first direction X. The emission colors of adjacent subpixels aligned in the first direction X are different from each other. The areas of the subpixels SP1, SP2, and SP3 may be the same or may be different from each other as described later. The outer shape of the subpixels may be defined by the outer shape of a light-emitting region of a display element.

[0022] FIG. 3 is a cross-sectional view of the display device DSP taken along the line AA' shown in FIG. The display device DSP includes a substrate 10, switching elements SW1 and SW2, an insulating layer 11, lower electrodes E11 and E12, an insulating layer 12, an organic layer OR, and an upper electrode E2. The display element 20A includes the lower electrode E11, a first portion OR1 of the organic layer OR, and an upper electrode E2. The display element 20B includes the lower electrode E12, a second portion OR2 of the organic layer OR, and an upper electrode E2.

[0023] The switching elements SW1 and SW2 are disposed on a substrate 10. The switching elements SW1 and SW2 correspond to, for example, the drive transistor 3 shown in FIG. 1. An insulating layer (first insulating layer) 11 is disposed on the substrate 10 and covers the switching elements SW1 and SW2. The insulating layer 11 corresponds to a base layer for the display elements 20A and 20B, and is, for example, an organic insulating layer. Note that the pixel switch 2 of the pixel circuit 1 shown in FIG. 1 and the like are disposed on the substrate 10 and covered by the insulating layer 11, but are not shown here.

[0024] The lower electrodes E11 and E12 are disposed on the insulating layer 11. The lower electrode E11 is electrically connected to the switching element SW1 through a contact hole CH1 formed in the insulating layer 11. The lower electrode E12 is electrically connected to the switching element SW2 through a contact hole CH2 formed in the insulating layer 11.

[0025] The lower electrodes E11 and E12 are transparent electrodes formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The lower electrodes E11 and E12 may be metal electrodes formed of a metal material such as silver or aluminum. The lower electrodes E11 and E12 may be a laminate of a transparent electrode and a metal electrode. For example, the lower electrodes E11 and E12 may be configured as a laminate in which a transparent electrode, a metal electrode, and a transparent electrode are laminated in this order, or may be configured as a laminate of three or more layers.

[0026] The insulating layer (second insulating layer) 12 is disposed on the insulating layer 11 and covers the periphery of each of the lower electrodes E11 and E12. The insulating layer 12 is, for example, an organic insulating layer. The insulating layer 12 has the above-mentioned first opening OP1, second opening OP2, and trench T12, a first surface SF1, and a second surface SF2. The first opening OP1 penetrates the insulating layer 12 to the lower electrode E11. The second opening OP2 penetrates the insulating layer 12 to the lower electrode E12. The first surface SF1 is located between the trench T12 and the first opening OP1. The second surface SF2 is located between the trench T12 and the second opening OP2. The insulating layer 12 has a thickness TH. In the illustrated example, the thickness TH corresponds to the distance between the highest position of the insulating layer 12 and the insulating layer 11, and is, for example, 1.5 to 2.0 μm.

[0027] The trench T12 has a bottom surface BS, and a first side surface SS1 and a second side surface SS2 rising from the bottom surface BS. The first side surface SS1 and the second side surface SS2 face each other with a gap in between in the first direction X. The first side surface SS1 is connected to the first surface SF1. The second side surface SS2 is connected to the second surface SF2. The trench T12 corresponds to a space surrounded by the first side surface SS1, the second side surface SS2, and the bottom surface BS. The trench T12 has a depth D. The depth D is, for example, 0.5 to 1.0 μm.

[0028] The trench T12 has a gap GP1 between the first side surface SS1 and the second side surface SS2 at its top UP, and a gap GP2 between the first side surface SS1 and the second side surface SS2 at its bottom surface BS. The gap GP1 is smaller than the gap GP2. That is, the trench T12 is formed such that the width along the first direction X decreases from the bottom surface BS toward the top surface UP. In other words, the first side surface SS1 is inclined with respect to the normal direction of the bottom surface BS so as to overlap with the bottom surface BS. Similarly, the second side surface SS2 is inclined with respect to the normal direction of the bottom surface BS so as to overlap with the bottom surface BS.

[0029] The organic layer OR has a first portion OR1, a second portion OR2, and a third portion OR3. The first portion OR1 covers the lower electrode E11 located at the first opening OP1 and the first surface SF1. The second portion OR2 covers the lower electrode E12 located at the second opening OP2 and the second surface SF2. The third portion OR3 is located at the bottom surface BS of the trench T12. The third portion OR3 is spaced apart from the first portion OR1 and the second portion OR2. The organic layer OR includes an emitting layer EL as described later, and the first portion OR1, the second portion OR2, and the third portion OR3 include an emitting layer EL of the same color. In addition to the emitting layer EL, the organic layer OR includes at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

[0030] The upper electrode E2 covers the organic layer OR. That is, the upper electrode E2 covers each of the first portion OR1, the second portion OR2, and the third portion OR3. The upper electrode E2 covers the third portion OR3 inside the trench T12 and contacts the bottom surface BS. The upper electrode E2 contacts the first side surface SS1 and the second side surface SS2 inside the trench T12. The upper electrode E2 is a transparent electrode formed of a transparent conductive material such as ITO or IZO. The upper electrode E2 is electrically connected to the power supply line FL located in the display area DA shown in FIG. 1. The upper electrode E2 is an electrode commonly disposed for a plurality of sub-pixels or a plurality of display elements, and may be referred to as a common electrode, a counter electrode, a cathode, or the like. The upper electrode E2 may be covered with a transparent protective layer (including at least one of an inorganic insulating layer and an organic insulating layer).

[0031] In the display element 20A, the first portion OR1 is located between the lower electrode E11 and the upper electrode E2, and therefore can form a light-emitting region. In the display element 20B, the second portion OR2 is located between the lower electrode E12 and the upper electrode E2, and therefore can form a light-emitting region. The third portion OR3 is located between the insulating layer 12 and the upper electrode E2, and is completely separated from the first portion OR1 and the second portion OR2, and therefore does not emit light. In addition, the region of the first portion OR1 that covers the first surface SF1 is located between the insulating layer 12 and the upper electrode E2, and therefore hardly emits light. Similarly, the region of the second portion OR2 that covers the second surface SF2 is located between the insulating layer 12 and the upper electrode E2, and therefore hardly emits light.

[0032] The organic layer OR is formed by, for example, a vacuum deposition method. The organic material for forming the organic layer OR is discharged from a deposition source as shown by the dashed line in the figure. After forming the insulating layer 12 having the first opening OP1, the second opening OP2, and the trench T12, an organic material for forming the organic layer OR is evaporated. Since the first side surface SS1 is inclined so as to overlap with the bottom surface BS, the organic layer OR is hardly formed on the first side surface SS1. As a result, the organic layer OR is formed with the first portion OR1 and the third portion OR3 being separated. Similarly, since the second side surface SS2 is inclined so as to overlap with the bottom surface BS, the organic layer OR is hardly formed on the second side surface SS2. As a result, the organic layer OR is formed with the second portion OR2 and the third portion OR3 being separated. Furthermore, the organic layer OR is hardly formed in the region of the bottom surface BS that overlaps with the first side surface SS1 and the second side surface SS2 in the third direction Z. Since the upper electrode E2 is formed by sputtering, it is continuously formed on the organic layer OR, the bottom surface BS, the first side surface SS1, and the second side surface SS2.

[0033] According to this embodiment, the insulating layer 12 has a trench T12. The trench T12 is formed so that the width along the first direction X decreases from the bottom surface BS toward the upper portion UP. Therefore, the organic layer OR can be formed separately in the trench T12 into a first portion OR1 located in the subpixel SP1 and a second portion OR2 located in the subpixel SP2. That is, the organic layer OR can be formed separately for each subpixel by full surface deposition without using a mask. This suppresses crosstalk between adjacent subpixels. Furthermore, since no separate member is required for separating the organic layer OR, the manufacturing cost can be reduced.

[0034] The distance between the first side surface SS1 and the second side surface SS2 can be rephrased as the width of the trench T12. In the example shown in FIG. 3, the first side surface SS1, the second side surface SS2, and the bottom surface BS are flat surfaces, but they may be curved surfaces. When the first side surface SS1, the second side surface SS2, and the bottom surface BS are flat surfaces, the maximum width of the trench T12 corresponds to the width of the bottom surface BS. However, when the first side surface SS1, the second side surface SS2, and the bottom surface BS include curved surfaces, the maximum width of the trench T12 does not necessarily correspond to the width of the bottom surface BS, and the width of the trench T12 may be maximum above the bottom surface BS. In this case, for example, the width of the trench T12 is maximum at a position that is 1 / 2 or less, or even 1 / 3 or less, of the height of the trench T12.

[0035] When the potential of the lower electrodes E11 and E12 is relatively higher than that of the upper electrode E2, the lower electrodes E11 and E12 correspond to the anode and the upper electrode E2 corresponds to the cathode. When the potential of the upper electrode E2 is relatively higher than that of the lower electrodes E11 and E12, the upper electrode E2 corresponds to the anode and the lower electrodes E11 and E12 correspond to the cathode.

[0036] Also, for example, an organic layer OR including an emitting layer EL of the same color is arranged in all the subpixels SP of the display area DA. When the emission color of each display element is white, a multi-color display can be realized by arranging a color filter facing the display element. When the emission color of each display element is ultraviolet light, a multi-color display can be realized by arranging a light conversion layer facing the display element.

[0037] FIG. 4 is a cross-sectional view showing the trench T12, the organic layer OR, and the like. The organic layer OR includes a first layer L1, a second layer L2, and a third layer L3 that are stacked together. That is, the first portion OR1, the second portion OR2, and the third portion OR3 include a first layer L1, a second layer L2, and a third layer L3 that are stacked together, respectively. As described above, the organic layer OR includes an emitting layer EL, and the emitting layer EL is, for example, any one of the first layer L1, the second layer L2, and the third layer L3.

[0038] The first portion OR1 is in contact with the first side surface SS1. At the first side surface SS1, the end portion EG11 of the first layer L1 is covered by the second layer L2, and the end portion EG21 of the second layer L2 is covered by the third layer L3. The second portion OR2 is in contact with the second side surface SS2. At the second side surface SS2, the end portion EG12 of the first layer L1 is covered by the second layer L2, and the end portion EG22 of the second layer L2 is covered by the third layer L3.

[0039] In this embodiment, the first side surface SS1 and the second side surface SS2 are inclined so as to overlap the bottom surface BS, and therefore the second layer L2 covers the first layer L1, and the third layer L3 is evaporated to cover the second layer L2. This makes it possible to prevent the first layer L1 and the second layer L2 from being exposed from the third layer L3, and to prevent the upper electrode E2 from contacting the first layer L1 and the second layer L2. This makes it possible to prevent current leakage from the first layer L1 and the second layer L2 to the upper electrode E2, and to prevent performance degradation of the display element.

[0040] For example, the first layer L1 and the third layer L3 are functional layers, and the second layer L2 is an emitting layer EL. The first layer L1 and the third layer L3 are, for example, a hole injection layer, a hole transport layer, a hole blocking layer, an electron injection layer, an electron transport layer, and an electron blocking layer, but may be other functional layers. Each of the first layer L1 and the third layer L3 is not limited to a single layer, and may be a laminate in which a plurality of functional layers are laminated. At least one of the first layer L1 and the third layer L3 may be omitted. As an example, when the lower electrode corresponds to an anode, the first layer L1 between the light-emitting layer EL and the lower electrode includes at least one of a hole injection layer and a hole transport layer, and the third layer L3 between the light-emitting layer EL and the upper electrode E2 includes at least one of an electron transport layer and an electron injection layer.

[0041] 5 is a plan view showing the organic layer OR, in which the region where the organic layer OR is disposed is indicated by diagonal lines. The first portion OR1 is disposed in the subpixel SP1. The second portion OR2 is disposed in the subpixel SP2. The first portion OR1 and the second portion OR2 are aligned in the first direction X.

[0042] The third portion OR3 is formed in a lattice shape in a plan view. The third portion OR3 has portions OR31, OR32, and OR33 extending in the second direction Y and aligned in the first direction X, and portions OR34 and OR35 extending in the first direction X and aligned in the second direction Y. The portion OR32 is located between the first portion OR1 and the second portion OR2. The portion OR31 is located on the opposite side of the portion OR32 across the first portion OR1. The portion OR33 is located on the opposite side of the portion OR32 across the second portion OR2. The portion OR34 is connected to the portions OR31 to OR33. The portion OR35 is connected to the portions OR31 to OR33. The portion OR34 is located on the opposite side of the portion OR35 across the first portion OR1 and the second portion OR2.

[0043] The portions OR31 to OR33 are located in the trenches T11 to T13, respectively, and the portions OR34 and OR35 are located in the trenches T21 and T22, respectively. The outer shape of the first portion OR1 is larger than the outer shape of the lower electrode E11 in plan view, and the outer shape of the second portion OR2 is larger than the outer shape of the lower electrode E12 in plan view.

[0044] FIG. 6 is a cross-sectional view of the display device DSP taken along the line BB' shown in FIG. The peripheral electrode 6 and the power line 52 are located on the insulating layer 11. The insulating layer 12 covers the peripheral electrode 6 and the power line 52. The organic layer OR is not formed in the non-display area NDA. The upper electrode E2 covers the insulating layer 12 in the non-display area NDA and is connected to the peripheral electrode 6 via a contact hole CH3 formed in the insulating layer 12. In the illustrated example, the peripheral electrode 6 and the power line 52 are located in the same layer as the lower electrode E10, but they may be located in a layer different from the lower electrode E10.

[0045] Fig. 7 is a cross-sectional view showing a first modified example of the present embodiment. The configuration shown in Fig. 7 differs from the configuration shown in Fig. 3 in that trench T12 penetrates insulating layer 12 to insulating layer 11. In the illustrated example, the bottom surface BS corresponds to the upper surface of the insulating layer 11. Therefore, the third portion OR3 and the upper electrode E2 are in contact with the insulating layer 11 in the trench T12. The first modified example can also provide the same effects as those described above.

[0046] Fig. 8 is a plan view showing a second modified example of the present embodiment. The configuration shown in Fig. 8 is different from the configuration shown in Fig. 2 in the layout of subpixels SP1, SP2, and SP3.

[0047] The bottom electrodes E11 and E12 are aligned in the second direction Y. The bottom electrode E13 is aligned in the first direction X with the bottom electrodes E11 and E12.

[0048] The insulating layer 12 has trenches T15, T16, and T17 extending in the second direction Y and aligned in the first direction X, and trenches T23, T24, and T25 extending in the first direction X and aligned in the second direction Y. The trench T16 is located between the first opening OP1 and the second opening OP2 and the third opening OP3. The trench T15 is located on the opposite side of the trench T16 across the first opening OP1 and the second opening OP2. The trench T17 is located on the opposite side of the trench T16 across the third opening OP3. The trench T23 is connected to the trenches T15 to T17. The trench T24 is connected to the trenches T15 and T16. The trench T25 is connected to the trenches T15 to T17. The trench T23 is located on the opposite side of the trench T25 across the first opening OP1, the second opening OP2, and the third opening OP3. The trench T24 is located between the first opening OP1 and the second opening OP2.

[0049] Each trench does not overlap with an adjacent lower electrode in a plan view. In the first direction X, the lower electrodes E11 and E12 are located between the trenches T15 and T16, and the lower electrode E13 is located between the trenches T16 and T17. In the second direction Y, the lower electrode E11 is located between the trenches T23 and T24, the lower electrode E12 is located between the trenches T24 and T25, and the lower electrode E13 is located between the trenches T23 and T25.

[0050] The subpixels SP1 and SP2 are aligned in the second direction Y, the subpixels SP1 and SP3 are aligned in the first direction X, and the subpixels SP2 and SP3 are aligned in the first direction X. The subpixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and the subpixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The emission colors of the subpixels SP1 to SP3 are different from each other. The areas of the subpixels SP1 to SP3 are different from each other. The area of ​​the subpixel SP2 is larger than the area of ​​the subpixel SP1, and the area of ​​the subpixel SP3 is larger than the area of ​​the subpixel SP2. The area of ​​the subpixel SP1 may be the same as the area of ​​the subpixel SP2. In this second modified example as well, the same effects as those described above can be obtained.

[0051] Fig. 9 is a plan view showing a third modified example of the present embodiment. The configuration shown in Fig. 9 is different from the configuration shown in Fig. 2 in the layout of subpixels SP1, SP2, and SP3. The direction DR1 shown in Fig. 9 is inclined at an angle θ1 counterclockwise with respect to the second direction Y, and the direction DR2 shown in Fig. 9 is inclined at an angle θ2 clockwise with respect to the second direction Y.

[0052] The insulating layer 12 has a plurality of trenches T1 extending in a direction DR1 and aligned in a direction DR2, and a plurality of trenches T2 extending in a direction DR2 and aligned in the direction DR1. The plurality of bottom electrodes E11 and the plurality of first openings OP1 are located in the plurality of red subpixels SP1, respectively. The plurality of bottom electrodes E12 and the plurality of second openings OP2 are located in the plurality of green subpixels SP2, respectively. The plurality of bottom electrodes E13 and the plurality of third openings OP3 are located in the plurality of blue subpixels SP3, respectively.

[0053] The multiple lower electrodes E11 and E12 are alternately arranged in the direction DR1 between two adjacent trenches T1. The multiple lower electrodes E12 and E13 are alternately arranged in the direction DR1 between two adjacent trenches T1. The multiple lower electrodes E11 and E12 are alternately arranged in the direction DR2 between two adjacent trenches T2. The multiple lower electrodes E12 and E13 are alternately arranged in the direction DR2 between two adjacent trenches T2. Each of the trenches T1 and T2 does not overlap with the adjacent lower electrode in a plan view.

[0054] The subpixels SP1 and SP3 are formed in a substantially square shape, some of the subpixels SP2 are formed in a substantially rectangular shape extending in the direction DR1, and other subpixels SP2 are formed in a substantially rectangular shape extending in the direction DR2. The areas of the subpixels SP1 to SP3 are different from each other. The area of ​​the subpixel SP3 is larger than the area of ​​the subpixel SP1, and the area of ​​the subpixel SP1 is larger than the area of ​​the subpixel SP2. In this third modified example as well, the same effects as those described above can be obtained.

[0055] As described above, according to this embodiment, it is possible to obtain a display device capable of suppressing deterioration in display quality.

[0056] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0057] DSP... display device, 10... substrate, 11, 12... insulating layer, E11, E12, E13...lower electrode, OP1...first opening, OP2...second opening, OP3...third opening, T11~T17, T21~T25...Trench, EL...light-emitting layer, E2...upper electrode, BS...bottom surface, SS1...first side surface, SS2...second side surface, UP...Top, GP1, GP2...Interval, SF1...1st surface, SF2...2nd surface, OR...organic layer, OR1...first part, OR2...second part, OR3...third part, L1...first layer, L2...second layer, L3...third layer, EG11, EG12, EG21, EG22...ends, DA...display area, NDA...non-display area, 51, 52...power lines, 6...peripheral electrode.

Claims

1. A substrate; a first insulating layer disposed on the substrate; a first bottom electrode and a second bottom electrode disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer, the second insulating layer having a first opening overlapping the first bottom electrode, a second opening overlapping the second bottom electrode, and a first trench located between the first opening and the second opening; an organic layer including a light-emitting layer; an upper electrode covering the organic layer; A display area for displaying an image and a non-display area surrounding the display area; a power line located in the non-display area; a peripheral electrode located in the non-display area and electrically connected to the power supply line; a third lower electrode provided in the display region; Equipped with The first trench has a bottom surface and a first side surface and a second side surface rising from the bottom surface, a distance between the first side surface and the second side surface at an upper portion of the first trench is smaller than a distance between the first side surface and the second side surface at a bottom surface of the first trench; The organic layer is a first portion covering the first lower electrode located in the first opening and covering a first surface of the second insulating layer located between the first trench and the first opening; a second portion covering the second lower electrode located in the second opening and covering a second surface of the second insulating layer located between the first trench and the second opening; a third portion disposed on the bottom surface of the first trench and spaced apart from the first portion and the second portion; the first portion includes a first layer, a second layer, and a third layer that are stacked together, the first portion being in contact with the first side surface; an end of the first layer is covered by the second layer on the first side; an end of the second layer is covered by the third layer on the first side; the light-emitting layer is any one of the first layer, the second layer, and the third layer, the second insulating layer covers the peripheral electrode located in the non-display area; the upper electrode is connected to the peripheral electrode through a contact hole formed in the second insulating layer in the non-display region; the second insulating layer covers an end portion of the third lower electrode provided in the display region; the second insulating layer has a third side surface rising from a surface covering an end portion of the third lower electrode in the display region; A display device, wherein the second insulating layer does not have a side surface rising from a surface covering the peripheral electrode in the non-display area.

2. The display device of claim 1 , wherein the first portion, the second portion, and the third portion include the light-emitting layers of the same color.

3. The display device according to claim 1 , wherein the upper electrode covers the third portion inside the first trench and is in contact with the first side surface and the second side surface.

4. The second insulating layer further comprises: a second trench located on an opposite side of the first trench across the first opening; a third trench and a fourth trench each connected to both the first trench and the second trench, The display device according to claim 1 , wherein the third trench is located on an opposite side of the first opening from the fourth trench.

5. The display device of claim 1 , wherein the organic layer further comprises at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

6. 6. The display device according to claim 1, wherein the first trench penetrates the second insulating layer to the first insulating layer.

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