Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device capable of reducing a leak current due to a parasitic transistor generated in a separation region.SOLUTION: A semiconductor device comprises: a high-side circuit region 18 arranged on a P-type semiconductor substrate 10; a first N-type well 11; a second N-type well 12 arranged in a level shift resurf MOS 19; a separation region 13 located between the high-side circuit region 18 and the level shift resurf MOS 19 and separating between the first N-type well 11 and the second N-type well 12 by the P-type semiconductor substrate; an insulation layer 14 located on the separation region 13; wiring 15 provided on the insulation layer 14 and electrically connected to the second N-type well 12; and a P-type region 16 located below the wiring 15 and arranged on a surface side of the P-type semiconductor substrate in the separation region 13.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a conventional semiconductor device, one example of an efficient layout of a level-shift resurf MOS and a high-side isolation island (high-side circuit region) is a layout method in which the level-shift resurf MOS is arranged in a high-voltage termination region arranged around the high-side isolation island in a plan view, and the level-shift resurf MOS is isolated from the high-side isolation island by an isolation region formed by dividing one area of ​​the high-side isolation island and interposing a thin region of a P-type semiconductor substrate. An insulating layer is arranged on the isolation region, the high-side isolation island, and the level-shift resurf MOS, and wiring is arranged on the insulating layer. Note that related technologies are disclosed in Patent Documents 1 and 2.

[0003] With the above-mentioned layout method, in order to reduce the chip area, it is necessary to narrow the isolation region (a narrow region of the P-type semiconductor substrate) between the high-side isolation island and the level-shift RESURF MOS (to completely deplete it during high-voltage operation).

[0004] However, when the isolation region is narrowed, an inversion layer may be formed in the region (isolation region) of the P-type semiconductor substrate between the drain region (N-type well) of the level-shift RESURF MOS and the N-type region of the high-side isolation island, and a leakage current may flow due to the application of a high voltage to the wiring that exists above the region through an insulating layer.In particular, when the voltage of the high-side isolation island is low and the depletion of the isolation region is incomplete, a leakage current may occur due to a parasitic transistor in the isolation region that separates the level-shift RESURF MOS and the high-side isolation island.

[0005] In order to reduce the leakage current due to the parasitic transistor, it is necessary to increase the concentration of the isolation region. However, doing so reduces the withstand voltage of the high-side isolation island and the level-shift RESURF MOS, resulting in the problem that they cannot be used at the desired voltage. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2015-170733 A [Patent Document 2] Japanese Patent Application Publication No. 9-283716 Summary of the Invention [Problem to be solved by the invention]

[0007] Various aspects of the present invention aim to provide a semiconductor device that can reduce leakage current due to parasitic transistors generated in an isolation region without reducing the breakdown voltage of the level-shift RESURF MOS and the high-side isolation island and without increasing the isolation distance. Another object of the various aspects of the present invention is to provide a method for manufacturing a semiconductor device that can reduce leakage current caused by a parasitic transistor occurring in an isolation region without increasing the number of manufacturing steps. [Means for solving the problem]

[0008] Various aspects of the present invention are described below.

[0009] [1] A semiconductor substrate of a first conductivity type; a high side circuit region disposed on the semiconductor substrate in a plan view; a first second-conductivity-type well disposed on a front surface side of the semiconductor substrate and located in the high-side circuit region; a high-voltage termination region disposed on the periphery of the high-side circuit region in a plan view; a level-shift RESURF MOS located in the high-voltage termination region in a plan view; a second well of the second conductivity type disposed on the front surface side of the semiconductor substrate and disposed in the level-shift RESURF MOS; an isolation region located between the high-side circuit region and the level-shift RESURF MOS, and isolating the first well of the second conductivity type and the second well of the second conductivity type by the semiconductor substrate of the first conductivity type; an insulating layer overlying the first well of a second conductivity type, the isolation region, and the second well of a second conductivity type; a wiring disposed on the insulating layer and electrically connected to the second well of the second conductivity type; a first conductivity type region located under the wiring and disposed on a front surface side of the first conductivity type semiconductor substrate of the isolation region; the first conductivity type region is isolated from the first second conductivity type well and the second second conductivity type well by the first conductivity type semiconductor substrate of the isolation region, A semiconductor device, characterized in that an impurity concentration of the first conductivity type region is higher than an impurity concentration of a semiconductor substrate of the first conductivity type.

[0010] [2] In paragraph [1] above: The semiconductor device, wherein the width of the first conductivity type region is 0.5 μm or more and 4 μm or less (preferably 1.5 μm or more and 4 μm or less).

[0011] [3] In [1] or [2] above, The semiconductor device is characterized in that the distance between the first well of the second conductivity type and the second well of the second conductivity type is 17 μm or more and 27 μm or less (preferably 20 μm or more and 27 μm or less).

[0012] [4] In any one of paragraphs [1] to [3] above, A semiconductor device, wherein the first conductivity type region has a depth of 0.5 μm or more and 2.5 μm or less.

[0013] [5] In any one of paragraphs [1] to [4] above, The semiconductor device is characterized in that the thickness of the insulating layer is 0.6 μm or more and 2 μm or less (preferably 0.85 μm or more and 2 μm or less).

[0014] [6] A step (a) of forming, in a semiconductor substrate of a first conductivity type, a first well of a second conductivity type located in a high side circuit region and a second well of a second conductivity type located in a level shift resurf MOS arranged outside the high side circuit region in a planar view, and forming an isolation region located between the high side circuit region and the level shift resurf MOS in a planar view and isolating the first well of a second conductivity type and the second well of a second conductivity type by the semiconductor substrate of the first conductivity type; (b) forming a first first-conductivity type region having an impurity concentration higher than that of the semiconductor substrate on a surface side of the first-conductivity type semiconductor substrate in the isolation region; (c) forming an insulating layer over the first well of second conductivity type, the first region of first conductivity type, the isolation region, and the second well of second conductivity type; and (d) forming an interconnection located on the insulating layer and electrically connected to the second well of the second conductivity type, the wiring is located above the first conductivity type region, A method for manufacturing a semiconductor device, characterized in that the first conductivity type region is isolated from each of the first second conductivity type well and the second second conductivity type well by the first conductivity type semiconductor substrate of the isolation region.

[0015] [7] In paragraph [6] above: 12. A method for manufacturing a semiconductor device, comprising the steps of: forming a first conductivity type region on a surface side of the first conductivity type semiconductor substrate in the isolation region; and forming a first conductivity type impurity diffusion layer in the second second conductivity type well. Effect of the Invention

[0016] According to various aspects of the present invention, it is possible to provide a semiconductor device that can reduce leakage current due to a parasitic transistor generated in an isolation region without reducing the breakdown voltage of the level-shift RESURF MOS and the high-side isolation island and without increasing the isolation distance. Furthermore, according to various aspects of the present invention, it is possible to provide a method for manufacturing a semiconductor device that can reduce leakage current caused by a parasitic transistor occurring in an isolation region without increasing the number of manufacturing steps. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view taken along line AA' shown in FIG. [Diagram 3] 3 is a cross-sectional view showing a modified example of the semiconductor device shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0019] Fig. 1 is a plan view showing a semiconductor device according to one embodiment of the present invention, and Fig. 2 is a cross-sectional view taken along line AA' shown in Fig. 1.

[0020] 2, the semiconductor device has a first conductivity type semiconductor substrate (Psub) 10. The first conductivity type is, for example, P type, and this semiconductor substrate is a P-type semiconductor substrate 10.

[0021] As shown in FIG. 1, a high-side circuit region (high-side isolation island) 18 is formed in a P-type semiconductor substrate (corresponding to the P-type semiconductor substrate 10 shown in FIG. 2) in a plan view. 1, a high-voltage termination region 20 is arranged on the periphery of the high-side circuit region (high-side isolation island) 18 in plan view. A low-side circuit region (low-side circuit area) (not shown) is arranged outside this high-voltage termination region 20. Furthermore, a level-shift RESURF MOS 19 is arranged in the high-voltage termination region 20 in plan view.

[0022] 1, the level-shifting RESURF MOS 19 is isolated from the high-side isolation island 18 by an isolation region 13. This isolation region 13 has a narrow region of P-type semiconductor substrate 10 that divides an area of ​​the high-side isolation island 18 (see FIG. 2).

[0023] 2, a first second-conductivity-type well 11 located in a high-side circuit region 18 is disposed on the surface side of a P-type semiconductor substrate 10. The second conductivity type is, for example, N-type, and this well is a first N-type well 11. An N-type contact layer 31 is formed on the surface side of the first N-type well 11.

[0024] 2, a second second-conductivity-type well 12 is disposed on the front surface side of a P-type semiconductor substrate 10 in the level-shift RESURF MOS 19. This second-conductivity-type well is a second N-type well 12.

[0025] 1, an isolation region 13 is formed between the high-side circuit region 18 and the level-shift RESURF MOS 19. As shown in FIG. 2, this isolation region 13 is located between the first N-type well 11 and the second N-type well 12, and is a region for isolating the first N-type well 11 and the second N-type well 12 by the P-type semiconductor substrate 10.

[0026] 2, a P-type impurity diffusion layer (also referred to as a "first conductive type impurity diffusion layer") 17 and a P-type well 35 are formed on the surface side of the second N-type well 12. A first P-type impurity diffusion layer 22 is formed on the surface side of the P-type well 35, and a gate insulating film 25 is formed on this first P-type impurity diffusion layer 22. A gate electrode 26 is formed on this gate insulating film 25.

[0027] Moreover, an N-type source diffusion layer 23 and a second P-type impurity diffusion layer 27 are formed on the surface side of the first P-type impurity diffusion layer 22, and the second P-type impurity diffusion layer 27 is disposed adjacent to the N-type source diffusion layer 23. A backgate electrode 24 is formed on the N-type source diffusion layer 23 and the second P-type impurity diffusion layer 27.

[0028] In addition, an N-type drain contact layer 28 is formed on the surface side of the second N-type well 12, and a P-type impurity diffusion layer 17 is located between the N-type drain contact layer 28 and the P-type well 35. A drain wiring 30 is formed on the N-type drain contact layer 28, and the drain wiring 30 is electrically connected to the N-type drain contact layer 28 and the wiring 15.

[0029] An N-type impurity diffusion layer 29 is formed on the P-type impurity diffusion layer 17, the second N-type well 12, and the first N-type well 11, and the N-type impurity diffusion layer 29 is disposed adjacent to the N-type drain contact layer 28. The N-type impurity diffusion layer 29 is also formed on the first N-type well 11. The N-type impurity diffusion layer 29 protrudes up to the P-type semiconductor substrate 10 in the isolation region 13.

[0030] This N-type impurity diffusion layer 29 is a layer that constitutes a so-called (triple) RESURF structure for making the surface electric field of the drift portion uniform.

[0031] As shown in FIG. 2, an insulating layer 14 is formed on the first N-type well 11, the isolation region 13 and the second N-type well 12. As shown in FIG.

[0032] A wiring 15 is formed on the insulating layer 14 and is electrically connected to the second N-type well 12 .

[0033] The purpose of the wiring 15 is to stabilize the surface of the isolation region 13. In other words, by forming the wiring 15 on the insulating layer 14, it is possible to prevent the effects of external electric fields and charged particles that affect the isolation region 13, which has a low impurity concentration, stabilize the characteristics, and suppress changes over time.

[0034] A wiring 21 is formed on the insulating layer 14, and this wiring 21 is electrically connected to the second N-type well 12 via an N-type drain contact layer 28. This wiring 21 extends in a direction perpendicular to the paper surface of Fig. 2, forms a ring, and aims to make the electric field in the drift section uniform. In other words, by forming the wiring 21 on the insulating layer 14, it is possible to stabilize the breakdown voltage of the RESURF MOS.

[0035] A first conductivity type region 16 is formed on the surface side of the P-type semiconductor substrate (Psub) 10 of the isolation region 13, and this first conductivity type region is a P-type region 16. This P-type region 16 is located under the wiring 15.

[0036] The P-type region 16 is isolated from each of the first N-type well 11 and the second N-type well 12 by the P-type semiconductor substrate (Psub) 10 of the isolation region 13. In other words, the P-type semiconductor substrate 10 exists between the P-type region 16 and the first N-type well 11, and the P-type semiconductor substrate 10 exists between the P-type region 16 and the second N-type well 12. Therefore, the P-type region 16 is isolated from each of the first N-type well 11 and the second N-type well 12.

[0037] The impurity concentration of the P-type region 16 is higher than the impurity concentration of the P-type semiconductor substrate 10 (see FIG. 2). This makes it possible to reduce the leakage current caused by the parasitic transistor without increasing the chip area.

[0038] According to this embodiment, an isolation region 13 is formed by the P-type semiconductor substrate 10 to isolate the first N-type well 11 and the second N-type well 12, and a P-type region 16 is formed on the surface side of the isolation region 13 of the P-type semiconductor substrate 10. As a result, even if a high voltage is applied to the wiring 15 located on the insulating layer 14 and electrically connected to the second N-type well 12, the P-type region 16 functions as an inversion prevention layer, so that the leakage current due to the parasitic transistor in the isolation region 13 shown in FIG. 2 can be reduced. In other words, even if the separation distance between the level-shift RESURF MOS 19 and the high-side isolation island 18 is narrowed to reduce the chip area, the leakage current due to the parasitic transistor can be suppressed. Therefore, the leakage current due to the parasitic transistor can be reduced without increasing the chip area.

[0039] In other words, in the case of isolation region 13 without P-type region 16, narrowing the separation distance between level-shift resurf MOS 19 and high-side isolation island 18 increases the leakage current due to the parasitic transistor in isolation region 13 when a high voltage is applied to wiring 15 on insulating layer 14, whereas forming P-type region 16 in isolation region 13 between level-shift resurf MOS 19 and high-side isolation island 18 makes it possible to reduce the leakage current due to the parasitic transistor in isolation region 13 when a high voltage is applied to wiring 15 on insulating layer 14, even if the separation distance is narrowed. Therefore, the leakage current due to the parasitic transistor can be reduced without increasing the chip area.

[0040] Moreover, the width C of the P-type region 16 is preferably 0.5 μm or more and 4 μm or less, and more preferably 1.5 μm or more and 4 μm or less. This allows a withstand voltage of about 600 V to 1200 V of the high side drive voltage to be obtained when the power supply voltage Vcc is 20 V to 26 V, and makes it easier to reduce the leakage current caused by the parasitic transistor in the isolation region without increasing the chip area. In other words, the leakage generation potential difference can be greatly improved while maintaining the withstand voltage of the level shift RESURF.

[0041] The distance B between the first N-type well 11 and the second N-type well 12 is preferably 17 μm to 27 μm, more preferably 20 μm to 27 μm. This makes it easier to reduce the leakage current caused by the parasitic transistor in the isolation region without increasing the chip area. In other words, the leakage generation potential difference can be greatly improved while maintaining the breakdown voltage of the level shift RESURF.

[0042] The depth of the P-type region 16 is preferably 0.5 μm to 2.5 μm, more preferably 1.5 μm to 2.5 μm, which makes it easier to reduce leakage current due to parasitic transistors in the isolation region without increasing the chip area.

[0043] The thickness of the insulating layer 14 is preferably 0.6 μm or more and 2 μm or less, and more preferably 0.85 μm or more and 2 μm or less.

[0044] A method for manufacturing the above-mentioned semiconductor device will be described below. The method for manufacturing the semiconductor device includes steps (a) to (d).

[0045] First, the step (a) will be described. 1 and 2, a first N-type well 11 and a second N-type well 12 are formed in a P-type semiconductor substrate 10, which is a semiconductor substrate (Psub) of a first conductivity type. As a result, an isolation region 13 is formed between the first N-type well 11 and the second N-type well 12. This isolation region 13 is a region that isolates a high-side isolation island 18 and a level-shift resurf MOS 19 by the P-type semiconductor substrate 10 located in the isolation region. In other words, the isolation region 13 is a region that is located between the high-side isolation island 18 and the level-shift resurf MOS 19, and isolates the first N-type well 11 and the second N-type well 12 by the P-type semiconductor substrate 10.

[0046] The first N-type well 11 is a first well of the second conductivity type located in a high-side circuit region (high-side isolation island) 18. The second N-type well 12 is a second well of the second conductivity type, and is located in a level-shift RESURF MOS 19 arranged outside the high-side isolation island 18.

[0047] Furthermore, before forming the first N-type well 11 and the second N-type well 12 in the P-type semiconductor substrate 10, a third N-type well 33 is formed in the P-type semiconductor substrate 10. The third N-type well 33 is located below the first N-type well 11.

[0048] Furthermore, a third N-type well 33 is formed in the P-type semiconductor substrate 10 at the same time as the first N-type well 11 and the second N-type well 12 are formed in the P-type semiconductor substrate 10. The third N-type well 33 is formed so as to overlap the first N-type well 11. That is, impurity ions are introduced into the first and second N-type wells 11 and 12 in the same process, impurity ions are introduced into the third N-type well 33 in a subsequent process, and then the first to third N-type wells are formed by thermal diffusion.

[0049] Next, the step (b) will be described. A first first conductivity type region (also called a "P type region") 16 having a higher impurity concentration than the P type semiconductor substrate 10 is formed on the surface side of the isolation region 13 of the P type semiconductor substrate 10. The impurity concentration of the P type semiconductor substrate 10 is 1×10 14 / cm 3 More than 2×10 14 / cm 3 The impurity concentration of the P-type region 16 is preferably 2.3×10 16 / cm 3 More than 2.8 x 10 16 / cm 3 It would be better if it was less than this.

[0050] Next, the step (c) will be described. An insulating layer 14 is formed on the first N-type well 11, the P-type region 16, the isolation region 13 and the second N-type well 12. The impurity concentration of the first N-type well 11 is 7.5×10 16 / cm3 More than 8.5 x 10 16 / cm 3 The impurity concentration of the second N-type well 12 is preferably 9.5×10 15 / cm 3 Above 1.05 x 10 16 / cm 3 It would be better if it was less than this.

[0051] The following step may be included between step (b) and step (c). A first P-type impurity diffusion layer 22 is formed on the surface side of the P-type well 35. Next, an N-type impurity diffusion layer 29 is formed on the P-type impurity diffusion layer 17, the second N-type well 12 and the first N-type well 11.

[0052] Next, an N-type source diffusion layer 23 is formed on the surface side of the first P-type impurity diffusion layer 22. A second P-type impurity diffusion layer 27 is formed on the surface side of the first P-type impurity diffusion layer 22. An N-type drain contact layer 28 is formed on the surface side of the second N-type well 12. An N-type contact layer 31 is formed on the surface side of the first N-type well 11.

[0053] Next, a gate insulating film 25 is formed on the first P-type impurity diffusion layer 22 .

[0054] Next, the step (d) will be described. A wiring 15 is formed on the insulating layer 14. This wiring 15 is electrically connected to the second N-type well 12. This wiring 15 is located above a P-type region 16.

[0055] In detail, in the step (d), the gate electrode 26 may be formed on the gate insulating film 25, and the wiring 15 and the wiring 21 may be formed on the insulating layer 14.

[0056] Next, the insulating layer 50 is formed on the wiring 15, the wiring 21, the gate electrode 26 and the insulating layer 14.

[0057] Next, the drain wiring 30 is formed on the insulating layer 50, and the backgate electrode 24 is formed on the N-type source diffusion layer 23 and the second P-type impurity diffusion layer 27.

[0058] In the semiconductor device manufactured by the above manufacturing method, the P-type region 16 is isolated from the first N-type well 11 and the second N-type well 12 by the isolation region 13 of the P-type semiconductor substrate 10.

[0059] According to this embodiment, an isolation region 13 is formed by the P-type semiconductor substrate 10 to isolate the first N-type well 11 and the second N-type well 12, and a P-type region 16 is formed on the surface side of the isolation region 13 of the P-type semiconductor substrate 10. This makes it possible to reduce the leakage current caused by the parasitic transistor in the isolation region 13 shown in FIG. 2 even if a high voltage is applied to the wiring 15 located on the insulating layer 14 and electrically connected to the second N-type well 12. In other words, even if the separation distance between the level-shift RESURF MOS 19 and the high-side isolation island 18 is narrowed to reduce the chip area, the leakage current caused by the parasitic transistor can be suppressed. Therefore, the leakage current caused by the parasitic transistor can be reduced without increasing the chip area.

[0060] 2, the step (b) may be a step of forming a P-type region 16 on the surface side of the P-type semiconductor substrate 10 in the isolation region 13 and simultaneously forming a first conductive type impurity diffusion layer (also referred to as a "P-type impurity diffusion layer") 17 in the second N-type well 12. In this way, the P-type region (P-type impurity diffusion layer) 16 can be formed without increasing the number of resist masks, and an increase in manufacturing costs can be suppressed.

[0061] In other words, since the P-type impurity diffusion layer 17 is an impurity diffusion layer formed in a conventional semiconductor device, if the P-type impurity diffusion layer 16 is formed using a resist mask for forming the P-type impurity diffusion layer 17, there is no need to add a new resist mask, and the P-type impurity diffusion layer 16 can be formed without increasing the number of resist masks. As a result, an increase in costs can be suppressed. The impurity concentration of the P-type impurity diffusion layer 17 is 1.4×10 16 / cm 3 More than 1.6 x 10 16 / cm 3 It would be better if it was less than this.

[0062] In addition, the above step (b) may be a step of forming a P-type region 16 on the surface side of the P-type semiconductor substrate 10 of the isolation region 13, and at the same time forming a P-type impurity diffusion layer 17 and a P-type well 35 in the second N-type well 12, as shown in FIG.

[0063] FIG. 3 shows a modified example of the semiconductor device shown in FIG. 2. The same parts as those in FIG. 2 are given the same reference numerals, and only the different parts will be described.

[0064] The semiconductor device shown in Fig. 3 is obtained by removing the N-type impurity diffusion layer 29 from the semiconductor device shown in Fig. 2. The P-type impurity diffusion layer 17 is a layer that constitutes a so-called double RESURF structure.

[0065] The modified example shown in FIG. 3 also provides the same effects as those of this embodiment. [Explanation of symbols]

[0066] 10 First conductive type semiconductor substrate (P-type semiconductor substrate, Psub) 11 First second conductive type well (first N-type well) 12 Second second conductive type well (second N-type well) 13 Separation area 14 Insulating layer 15 Wiring 16 First conductivity type region (P type region) 17 First conductive type impurity diffusion layer (P-type impurity diffusion layer) 18 High side circuit area (high side isolation island) 19 Level shift resurf MOS 20 High voltage termination area B: Distance between the first second-conductivity-type well and the second second-conductivity-type well (distance between the first N-type well and the second N-type well) C Width of the first conductivity type region (width of the P type region)

Claims

1. a semiconductor substrate of a first conductivity type; a high side circuit region disposed on the semiconductor substrate in a plan view; a first second-conductivity-type well disposed on a front surface side of the semiconductor substrate and located in the high-side circuit region; a high-voltage termination region disposed on the outer periphery of the high-side circuit region in a plan view; a level-shift RESURF MOS located in the high-voltage termination region in a plan view; a second well of the second conductivity type disposed on the front surface side of the semiconductor substrate and disposed in the level-shift RESURF MOS; an isolation region located between the high-side circuit region and the level-shifting RESURF MOS and isolating the first well of the second conductivity type and the second well of the second conductivity type by a semiconductor substrate of the first conductivity type; an insulating layer overlying the first well of a second conductivity type, the isolation region, and the second well of a second conductivity type; a wiring disposed on the insulating layer and electrically connected to the second well of the second conductivity type; a first conductivity type region located under the wiring and disposed on a front surface side of the first conductivity type semiconductor substrate of the isolation region; the first conductivity type region is isolated from the first second conductivity type well and the second second conductivity type well by the first conductivity type semiconductor substrate of the isolation region, a first conductivity type region having an impurity concentration higher than an impurity concentration of a semiconductor substrate of the first conductivity type;

2. In claim 1, A semiconductor device, wherein the width of the first conductivity type region is 0.5 μm or more and 4 μm or less.

3. In claim 1 or 2, a distance between the first well of the second conductivity type and the second well of the second conductivity type is 17 μm or more and 27 μm or less.

4. In any one of claims 1 to 3, A semiconductor device, wherein the first conductivity type region has a depth of 0.5 μm or more and 2.5 μm or less.

5. In any one of claims 1 to 4, The semiconductor device is characterized in that the thickness of the insulating layer is 0.6 μm or more and 2 μm or less.

6. a step (a) of forming, in a semiconductor substrate of a first conductivity type, a first well of a second conductivity type located in a high side circuit region and a second well of a second conductivity type located in a level shift resurf MOS arranged outside the high side circuit region in a plan view, and forming an isolation region located between the high side circuit region and the level shift resurf MOS in a plan view and isolating the first well of a second conductivity type and the second well of a second conductivity type by the semiconductor substrate of the first conductivity type; a step (b) of forming a first first-conductivity type region having an impurity concentration higher than that of the semiconductor substrate on a surface side of the first-conductivity type semiconductor substrate of the isolation region; (c) forming an insulating layer over the first well of second conductivity type, the first region of first conductivity type, the isolation region, and the second well of second conductivity type; and (d) forming an interconnection located on the insulating layer and electrically connected to the second well of the second conductivity type, the wiring is located above the first conductivity type region, A method for manufacturing a semiconductor device, characterized in that the first conductivity type region is isolated from each of the first second conductivity type well and the second second conductivity type well by a semiconductor substrate of the first conductivity type in the isolation region.

7. In claim 6, a first conductivity type region formed on a surface side of the first conductivity type semiconductor substrate in the isolation region, and a first conductivity type impurity diffusion layer formed in the second second conductivity type well.

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