Enhanced 3D NAND gate stack

Abstract

An exemplary method for forming a semiconductor structure may include forming a first silicon oxide layer overlying a semiconductor substrate. The method may include forming a first silicon layer overlying the first silicon oxide layer. The method may include forming a silicon nitride layer overlying the first silicon layer. The method may include forming a second silicon layer overlying the silicon nitride layer. The method may include forming a second silicon oxide layer overlying the second silicon layer. The method may include removing the silicon nitride layer. The method may include removing the first silicon layer and the second silicon layer. The method may include forming a metal layer between and in contact with each of the first silicon oxide layer and the second silicon oxide layer.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. patent application Ser. No. 62 / 932,861, filed Nov. 8, 2019, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] Technical Field

[0002] The present technology relates to semiconductor processing and materials. More specifically, the present technology relates to methods for forming enhanced semiconductor structures. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods of forming and removing exposed material. Stacked memories, such as vertical or 3D NAND, may involve the formation of a series of alternating layers of dielectric material through which multiple memory holes or apertures can be etched. The material properties of the layers, as well as the process conditions and materials of the etch, can affect the uniformity and integrity of the structures formed. As devices continue to scale, conventional techniques may not be adequate for processing.

[0004]

[0004] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technique addresses these and other needs. Summary of the Invention

[0005]

[0005] An exemplary method of forming a semiconductor structure may include forming a first silicon oxide layer overlying a semiconductor substrate. The method may include forming a first silicon layer overlying the first silicon oxide layer. The method may include forming a silicon nitride layer overlying the first silicon layer. The method may include forming a second silicon layer overlying the silicon nitride layer. The method may include forming a second silicon oxide layer overlying the second silicon layer. The method may include removing the silicon nitride layer. The method may include removing the first silicon layer and the second silicon layer. The method may include forming a metal layer between and in contact with each of the first silicon oxide layer and the second silicon oxide layer.

[0006] In some embodiments, the silicon nitride layer may be removed by a wet etching process. The first silicon layer and the second silicon layer may be removed by a dry etching process. The second silicon layer and the second silicon oxide layer may form a composite film characterized by a Young's modulus of about 90 GPa or greater. The metal layer may be or may include tungsten. The method may include forming a liner layer along the first silicon oxide layer and the second silicon oxide layer after removing the first silicon layer and the second silicon layer. The formation of the first silicon oxide layer may occur in a first processing chamber. The removal of the first silicon layer and the second silicon layer may occur in a second processing chamber. The method may include transferring the semiconductor substrate from the first processing chamber to a second processing chamber while maintaining vacuum conditions. The first silicon oxide layer and the second silicon oxide layer may be characterized by a thickness of about 50 nm or less.

[0007]

[0007] Some embodiments of the present technology may include a method of forming a semiconductor structure. The method may include forming a first silicon oxide layer overlying a semiconductor substrate. The method may include forming a first amorphous silicon layer overlying the first silicon oxide layer. The method may include forming a silicon nitride layer overlying the first amorphous silicon layer. The method may include forming a second amorphous silicon layer overlying the silicon nitride layer. The method may include forming a second silicon oxide layer overlying the second amorphous silicon layer. The method may include removing the silicon nitride layer. The method may include contacting the first and second amorphous silicon layers with the first and second silicon oxide layers, respectively. did It may also include converting to a metallic material.

[0008] In some embodiments, converting may include flowing a metal-containing precursor to contact the first and second amorphous silicon layers. The method may include forming a volatile silicon-containing by-product while forming a layer of metallic material. The method may include forming a layer of metallic material extending between the first and second silicon oxide layers. The silicon nitride layer may be removed by a wet etching process. The first and second amorphous silicon layers may be characterized by a thickness of about 5 nm or less.

[0009]

[0009] Some embodiments of the present technology may include a method of forming a semiconductor structure. The method may include forming a first silicon oxide layer overlying a semiconductor substrate. The first silicon oxide layer may include a nitrogen dopant or a silicon-rich stoichiometry. The method may include forming a silicon nitride layer overlying the first silicon oxide layer. The method may include forming a second silicon oxide layer overlying the silicon nitride layer. The second silicon oxide layer may include a nitrogen dopant or a silicon-rich stoichiometry. The method may include removing the silicon nitride layer. The method may include treating the first silicon oxide layer and the second silicon oxide layer.

[0010] In some embodiments, the treating may include performing a water vapor anneal. The first silicon oxide layer may include an incorporated nitrogen dopant at a nitrogen concentration of about 5% or less. The first silicon oxide layer may be characterized by a Young's modulus of about 110 GPa or greater. The first silicon oxide layer may be characterized by an oxygen to silicon stoichiometry of about 1.8:1 or less. The first silicon oxide layer may be characterized by a Young's modulus of about 130 GPa or greater. After treating, the first silicon oxide layer and the second silicon oxide layer may be characterized by a breakdown voltage of about 9 MV / cm or greater.

[0011]

[0011] Such techniques may provide numerous advantages over conventional systems and techniques. For example, the process may produce films that are characterized by improved resistance to deformation during removal operations. Additionally, operation of embodiments of the present techniques may produce films that are protected from thinning during removal operations. These and other embodiments, along with their many advantages and features, are described in more detail in the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed techniques may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 illustrates a top view of one embodiment of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2A]

[0014] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Figure 2B]

[0015] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Diagram 3]

[0016] 5 illustrates exemplary operations in a method of forming a semiconductor structure in accordance with some embodiments of the present technique. [Figure 4A-4D]

[0017] 13A-13D show schematic cross-sectional views of a fang during a forming operation in accordance with some embodiments of the present technology. [Diagram 5]

[0018] 5 illustrates exemplary operations in a method of forming a semiconductor structure in accordance with some embodiments of the present technique. [Figures 6A-6D]

[0019] 1A-1D show schematic cross-sectional views of a substrate during a forming operation according to some embodiments of the present technique; [Figure 7]

[0020] 5 illustrates exemplary operations in a method of forming a semiconductor structure in accordance with some embodiments of the present technique. [Figure 8A-8D]

[0021] 1A-1D show schematic cross-sectional views of a substrate during a forming operation according to some embodiments of the present technique; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0022] Some drawings are included as schematics. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to a realistic depiction and may include material that is emphasized for illustrative purposes.

[0015]

[0023] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any of the similar components having the same first reference number, regardless of the letter.

[0016]

[0024] In the transition from 2D NAND to 3D NAND, many process operations are modified from vertical to horizontal operations. In 3D NAND processing, stacks of placeholder layers and dielectric materials may form inter-electrode dielectric layers or inter-poly dielectric ("IPD") layers. A wide variety of operations may be performed on these placeholder layers to place structures before the material is completely removed and replaced with metal. As memory devices continue to shrink and more cells are developed per stack, the thickness of the dielectric and placeholder layers continues to decrease. When a memory hole is formed, the opening may extend through all of the alternating layers of material before accessing the underlying substrate. Subsequent processing may form stepped structures for contacts, laterally excavate the placeholder material, and form conductive material within the recesses.

[0017] In many techniques, wet etching is utilized to access each of the cell placeholder materials to perform lateral etching of the placeholders. For example, in many oxide-nitride stacks, the nitride may be removed by wet etching, which may include a thermal phosphoric acid treatment that may be selective to the nitride relative to the oxide. However, small form factor structures may cause collapse or deformation of the pattern due to the surface tension of the etchant, for example, during subsequent drying operations. The oxide layer may feature reduced stiffness or resistance to the effects of surface tension, which may cause deformation of the dielectric material during the etching process. Depending on the required structural aspects and removal, thinning of the dielectric material layer may also occur during removal of the placeholder.

[0018]

[0026] The present technique overcomes these problems by producing a structurally strengthened dielectric layer, which may better withstand the effects of wet etching processes. Additionally, aspects of the present technique may advantageously enhance metal fill. After describing an exemplary system that may be configured to implement aspects of the present technique, a number of exemplary methods and materials are described.

[0019]

[0027] While the remaining disclosure will utilize the disclosed techniques to produce specific structures, such as for memory, and will invariably identify specific deposition and removal processes, it will be readily understood that the systems and methods are equally applicable to many other processes and semiconductor structures. Thus, the present technique should not be considered limited to use with the described deposition and etch processes or chambers alone. Additionally, while exemplary chambers and systems are described to provide a foundation for the present technique, it should be understood that the present technique can be applied to virtually any semiconductor processing chamber or system that can enable the described processing operations.

[0020]

[0028] FIG. 1 illustrates a top view of one embodiment of a processing system 100 of deposition, etch, annealing or other processing chambers, according to an embodiment. In this view, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robot arm 104 and placed in a low pressure holding area 106, which is then placed into one of the substrate processing chambers 108a-f in tandem sections 109a-c. A second robot arm 110 can be used to transfer the substrate wafer from the holding area 106 to the substrate processing chambers 108a-f and from the substrate processing chambers 108a-f back to the holding area 106. Each substrate processing chamber 108a-f can be equipped to perform many substrate processing operations, including dry etch processes, removal processes, atomic layer deposition, chemical vapor deposition, physical vapor deposition, deposition processes as described herein, in addition to general etching, pre-cleaning, degassing, orientation, and other substrate processing.

[0021]

[0029] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be specifically configured to deposit a dielectric material on a substrate as described below, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit a dielectric film on a substrate. One or more of the described processes may be performed in one or more chambers separate from the fabrication system shown in various embodiments. It will be understood that additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for dielectric films are contemplated in the system 100.

[0022]

[0030] FIG. 2 shows a schematic cross-sectional view of an exemplary processing chamber 200 according to some embodiments of the present technique. This diagram may show a schematic of a system incorporating one or more aspects of the present technique and / or which may be specifically configured to perform one or more operations according to embodiments of the present technique. Further details of the method performed in the chamber 200 or a specifically configured chamber may be further described below. Although the chamber 200 may be utilized to form a film layer according to some embodiments of the present technique, it should be understood that the method may be similarly performed in any chamber in which film formation may occur. The processing chamber 200 may include a chamber body 202, a substrate support 204 disposed within the chamber body 202, and a lid assembly 206 coupled with the chamber body 202 and confining the substrate support 204 within a processing space 220. A substrate 203 may be provided to the processing space 220 through an opening 226. The opening 126 may be conventionally sealed for processing using a slit valve or door. The substrate 203 may be mounted on a surface 205 of the substrate support during processing. The substrate support 204 is rotatable along an axis 247, as indicated by arrow 245, where the shaft 244 of the substrate support 204 may be located. Alternatively, the substrate support 204 may be elevated and rotated as needed during the deposition process.

[0023]

[0031] The plasma profile modulator 211 may be disposed in the process chamber 200 to control the plasma distribution across the substrate 203 disposed on the substrate support 204. The plasma profile modulator 211 may include a first electrode 208, which may be disposed adjacent to the chamber body 202 and may separate the chamber body 202 from other components of the lid assembly 206. The first electrode 208 may be part of the lid assembly 206 or may be a separate sidewall electrode. The first electrode 208 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 208 may be a continuous member along the periphery of the process chamber 200 surrounding the process space 220 or may be discontinuous at selected locations as desired. The first electrode 208 may be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as a secondary gas distributor.

[0024]

[0032] The insulator(s) 210a, 210b may be a dielectric material such as a ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, and may contact the first electrode 208 and electrically and thermally isolate the first electrode 208 from the gas distributor 212 and the chamber body 202. The gas distributor 212 may define an aperture 218 for distributing process precursors into the process space 220. The gas distributor 212 may be coupled to a first power source 242, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be coupled to a process chamber. In some embodiments, the first power source 242 may be an RF power source. In some embodiments, the first power source 242 may also be an inductively coupled plasma coil extending around the inlet 214, which may be used to generate or deliver plasma effluents into the process space 220.

[0025]

[0033] The gas distributor 212 can be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 212 can also be formed of conductive and non-conductive components. For example, the body of the gas distributor 212 can be conductive while the faceplate of the gas distributor 212 can be non-conductive. The gas distributor 212 can be powered by, for example, a first power source 242 as shown in FIG. 2, or the gas distributor 212 can be coupled to ground in some embodiments.

[0026]

[0034] The first electrode 208 may be coupled to a first tuning circuit 228 that may control a ground path of the processing chamber 200. The first tuning circuit 228 may include a first electronic sensor 230 and a first electronic controller 234. The first electronic controller 234 may be or include a variable capacitor or other circuit element. The first tuning circuit 228 may be or include one or more inductors 232. The first tuning circuit 228 may be any circuit that allows for a variable or controllable impedance under the plasma conditions present in the processing space 220 during processing. In some embodiments as shown, the first tuning circuit 228 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 230. The first circuit leg may include a first inductor 232a. The second circuit leg may include a second inductor 232b coupled in series with the first electronic controller 234. The second inductor 232b may be disposed between the first electronic controller 234 and a node connecting both the first and second circuit legs to the first electronic sensor 230. The first electronic sensor 230 may be a voltage or current sensor and may be coupled to the first electronic controller 234. This may provide some degree of closed loop control of the plasma conditions within the process space 220.

[0027]

[0035] The second electrode 222 may be coupled to the substrate support 204. The second electrode 222 may be incorporated into the substrate support 204 or may be coupled to a surface of the substrate support 204. The second electrode 222 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 222 may be a tuning electrode and may be coupled to a second tuning circuit 236 by a conduit 246 (e.g., a cable having a selected resistance (e.g., 50 ohms, etc.)) disposed in a shaft 244 of the substrate support 204. The second tuning circuit 236 may have a second electronic sensor 238, a second electronic controller 240, which may be a second variable capacitor. The second electronic sensor 238 may be a voltage sensor or a current sensor and may be coupled to the second electronic controller 240 to provide further control over the plasma conditions in the process space 220.

[0028]

[0036] A third electrode 224, which may be a bias electrode and / or an electrostatic chuck electrode, may be coupled to the substrate support 204. The third electrode may be coupled to a second power source 250 through a filter 248. The filter 148 may be an impedance matching circuit. The second power source 250 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 250 may be RF bias power.

[0029]

[0037] The lid assembly 206 and substrate support 204 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. During operation, the processing chamber 200 may provide real-time control of plasma conditions within the processing space 220. A substrate 203 may be disposed on the substrate support 204. Processing gases may be flowed through the lid assembly 206 using the inlet 214 according to any desired flow scheme. Gases may be exhausted from the processing chamber 200 through the outlet 252. The outlet 252 may be coupled to a pump, such as any exhaust pump, including a turbomolecular pump in some embodiments. Power may be coupled to the gas distributor 212 to establish a plasma within the processing space 220. In some embodiments, the substrate may be subjected to an electrical bias using the third electrode 224.

[0030]

[0038] Upon exciting a plasma in the process space 220, a potential difference may be established between the plasma and the first electrode 208. A potential difference may also be established between the plasma and the second electrode 222. The electronic controllers 234, 240 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 228 and 236. Set points may be provided to the first tuned circuit 228 and the second tuned circuit 236 to provide independent control of the deposition rate and uniformity of the plasma density from the center to the edge of the substrate. In an embodiment where the electronic controllers are both variable capacitors, these variable capacitors may be independently adjusted by electronic sensors to maximize the deposition rate and minimize thickness non-uniformity.

[0031]

[0039] Each of the tuning circuits 228, 236 may have a variable impedance that may be adjusted using a corresponding electronic controller 234, 240. If the electronic controller 234, 240 is a variable capacitor, the respective capacitance range of the variable capacitor and the first inductor 232a and the second inductor 232b may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and the capacitance range of each variable capacitor may be minimum. Thus, when the capacitance of the first electronic controller 234 is minimum or maximum, the impedance of the first tuning circuit 228 may be high, resulting in a plasma shape with minimal spatial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 234 reaches a value that minimizes the impedance of the first tuning circuit 228, the spatial coverage of the plasma may grow to a maximum and effectively cover the entire working area of ​​the substrate support 204. As the capacitance of the first electronic controller 234 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and reduce spatial coverage of the substrate support. The second electronic controller 240 has a similar effect, and as the capacitance of the second electronic controller 240 changes, the spatial coverage of the plasma above the substrate support may increase or decrease.

[0032]

[0040] The electronic sensors 230, 238 may be used to tune the corresponding circuits 228, 236 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be attached to each sensor, and the sensors may be provided with control software that determines adjustments to the respective electronic controllers 234, 240 to minimize deviations from the set point. As a result, the plasma shape may be selected and dynamically controlled during processing. Although the above description is based on the electronic controllers 234, 240 being variable capacitors, it should be understood that any electronic components having adjustable characteristics may be used to provide the tuning circuits 228 and 236 with adjustable impedance.

[0033]

[0041] FIG. 2B shows a schematic cross-sectional view of a plasma chamber 260 according to some embodiments of the present technology. This diagram may show a schematic of a system incorporating one or more aspects of the present technology and / or may be specifically configured to perform one or more operations according to embodiments of the present technology, for example, utilizing an inductively coupled plasma source. Utilizing a chamber incorporating an inductively coupled plasma may allow additional plasma parameters to be controlled, which may affect the film produced. For example, the chamber may provide a lower processing pressure, which may affect film formation and properties. The plasma chamber 260 may include a chamber body 262 and a lid assembly 264, which may be coupled to the chamber body. The lid assembly 264 may include a precursor delivery assembly 266 and a lid 268. The lid 268 may define an aperture or opening 270, which may provide access to one or more process precursor gases within the processing chamber.

[0034]

[0042] The precursor delivery assembly 266 may be disposed above the lid 268 and may extend through an opening 270. The precursor delivery assembly 266 may be coupled to a precursor source 272, which may provide one or more process precursors into the substrate processing region 275 through an inlet 274. The substrate 276 may be disposed on a substrate support 278 disposed within or extending into the substrate processing region 275 and may be coupled to a bias power supply or other materials or electronics. The one or more process precursor gases may be exhausted from the substrate processing region 275 through an exhaust ring 280, which may be coupled to an exhaust pump 282. In some embodiments, the pump 282 may be a turbomolecular pump, which may enable an operating pressure of about 1 Torr or less, about 500 mTorr or less, about 100 mTorr or less, about 50 mTorr or less, about 20 mTorr or less, about 5 mTorr or less, or less.

[0035]

[0043] Coupled with the lid assembly 264 may be one or more coils for energizing the precursors to generate plasma effluents. The coils may include many coil sets, such as an inner coil 284, an intermediate coil 286, and an outer coil 288, all of which may be positioned proximate to the lid 268 and may extend around the opening 270, for example. The inner coil 284 and the outer coil 288 may be electrically coupled to an RF power source 290 through a matching circuit 292. Power applied from the RF power source 290 to the outer coil 446 may be inductively coupled through the lid 268 to generate a plasma from the process precursors provided from the precursor source 272 in the substrate processing region 275. The RF power source 290 may provide current at many different frequencies to control the plasma density, such as the number of ions per unit volume in the plasma. This may define a density of ion flux, which corresponds to the plasma density over time. The bias power supply can control the voltage between the substrate 276 and the generated plasma, and thus the energy and directionality of the ions, for example, to approach the substrate. As a result, the plasma chamber 260 can independently control both the ion flux and the ion energy.

[0036]

[0044] The heater assembly 294 may be disposed adjacent to the lid 268, or in some embodiments, between the lid and the coil as shown. The heater assembly 294 may be secured to the lid 408 using a clamp member 296. The surface of the substrate may be maintained at a temperature range ranging between about 100° C. and about 500° C. or greater. The plasma chamber 260 may be used in any number of embodiments to produce a film as described further below.

[0037]

[0045] FIG. 3 illustrates an exemplary operation of a processing method 300 according to an embodiment of the present technique. The method may be performed in a variety of processing chambers, including the processing chamber 200 described above, and may be incorporated into the system 100, for example. The method 300 may include several optional operations that may or may not be specifically associated with some embodiments of the method according to the present technique. For example, many operations are described to provide a broader range of structure formations, but may not be critical to the technique or may be performed by alternative methodologies as will be readily understood. The method 300 may describe operations shown generally in FIGS. 4A-4D. These figures are described in conjunction with the operations of the method 300. It should be understood that the figures show only partial schematic views, and that a substrate may include any number of structural sections having the aspects as shown in the figures, as well as alternative structural aspects that may still benefit from the operations of the present technique.

[0038]

[0046] Method 300 may include additional operations prior to the initiation of the recited operations. For example, the additional processing operations may include forming structures on the semiconductor substrate, which may include both the formation and removal of materials. Prior to delivering the substrate into a semiconductor processing chamber in which method 300 may be performed, processing operations may be performed in the chamber in which method 300 may be performed, or processing may be performed in one or more other processing chambers. In any case, method 300 may include delivering a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 200 described above, or other chamber that may include the components described above. The substrate may be deposited on a substrate support. The substrate support may be a pedestal, such as substrate support 204, and may be present in a processing region of a chamber, such as processing space 220 described above. An exemplary substrate 405 is shown in FIG. 4A and may be or may include aspects of a substrate on which operations according to the present technology may be performed.

[0039]

[0047] The substrate 405 can be any number of materials on which a material may be deposited. The substrate can be silicon, germanium, a dielectric material including silicon oxide or silicon nitride, a metallic material, or any number of combinations of these materials (which may be the substrate 405 or the material formed on the substrate 405). In some embodiments, optional processing operations such as pre-treatment may be performed to prepare the surface of the substrate 405 for deposition. Additionally, removal of material such as reduction of native oxide or etching of material, or any other operation that may prepare one or more exposed surfaces of the substrate 405 for deposition may be performed.

[0040]

[0048] The method 300 may include forming a first silicon oxide layer overlying the substrate, such as the illustrated layer 407 of FIG. 4A, in operation 305. The formation may be performed using a silicon-containing precursor and / or an oxygen-containing precursor. While some conventional techniques may include forming a nitride layer overlying an oxide, in some embodiments a first silicon layer may be formed over the first silicon oxide layer in operation 310. As illustrated in FIG. 4A, a layer 409 may be formed above the nitride layer. The silicon layer may include any number of silicon or silicon-containing materials, and in some embodiments may be or include amorphous silicon. The silicon layer may be formed with a silicon precursor. The method may include forming a silicon nitride layer overlying the silicon layer in operation 315. The formation may be performed using a silicon-containing precursor and a nitrogen-containing precursor. The nitride layer 411 may extend over the silicon layer and may be separated from the oxide layer by the silicon layer 409. Each of the oxide, silicon, and nitride layers may be formed in the same chamber or in different chambers on the same tool. In some embodiments, each of the layers may be formed during a plasma enhanced chemical vapor deposition process. Between each deposition operation, a purge process may be performed to create separate transitions between layers, which may limit surface roughness in the layer operations.

[0041]

[0049] A second silicon layer may be formed over the silicon nitride layer in operation 320. The second silicon layer may be similar to the first silicon layer and may be formed by a similar process as the first silicon layer in some embodiments. As illustrated in FIG. 4A, silicon layer 413 may be similar or identical to silicon layer 409. The two layers may include a nitride layer 411 between them. A second silicon oxide layer may be formed over the second silicon layer in operation 325. As shown in the figure, layer 415 may be formed above silicon layer 413. In some embodiments, the second silicon oxide layer may be similar to the first silicon oxide layer and may be formed by a similar process.

[0042]

[0050] The second silicon oxide layer 415 may be the beginning of a second segment of material formed over the substrate. The described operations may be repeated any number of times until a predetermined number of pairs of layers may be formed that may constitute a stack of layers. For example, any number of layers may be generated within the structure, for example, from about 10 or less layers of material to 200 or more layers of material. FIG. 4A shows a structure 400 encompassed by the present technology, including a developed stack of alternating layers, which may maintain the alternating structure described. It should be understood that in some embodiments of the present technology, any of the layers may be the first layer formed or the last layer of the stack. Between each layer of silicon oxide and silicon nitride, there may be an intervening layer of silicon, such as amorphous silicon. The overall stack may include any number of sets of layers, including about 2 sets or more, about 10 sets or more, about 50 sets or more, about 100 sets or more, or more sets of layers. Thus, in some embodiments, operations 305 to 320 may be repeated any number of times to generate a stack of any size. The operation may be stopped to complete lamination at any layer before continuing with further processing. Any specific number set falling within any of these described ranges should be understood as if specifically set forth herein, and the drawings are included solely to illustrate example structures.

[0043]

[0051] With respect to the deposition precursors used during any of the formation operations, any number of precursors may be used in the present technique. Silicon-containing precursors that may be used during any of the silicon oxide, silicon, or silicon nitride formation may include, but are not limited to, silane (SiH4), disilane (Si2H6), or other organosilanes, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), and other silicon-containing precursors that may be used for silicon-containing film formation. Oxygen-containing precursors used in any of the operations described throughout the present technique may include O2, N2O, NO2, O3, H2O, and any other oxygen-containing precursors that may be used for silicon oxide film formation or other film formation. Nitrogen-containing precursors used in any of the operations may include N2, N2O, NO2, NH3, N2H2, and any other nitrogen-containing precursors that may be used for silicon nitride film formation. Any of the forming operations may include one or more additional precursors, such as an inert precursor, which may include Ar, He, Xe, Kr, nitrogen, hydrogen, or other precursors.

[0044]

[0052] The thickness of the film can be any range of thickness to produce a memory or other semiconductor structure. For example, in some embodiments, the oxide or nitride layer can be about 100 nm or less, about 90 nm or less, about 80 nm or less, about 70 nm or less, about 60 nm or less, about 50 nm or less, about 45 nm or less, about 40 nm or less, about 35 nm or less, about 30 nm or less, about 25 nm or less, about 20 nm or less, about 15 nm or less, about 10 nm or less, or less. In some embodiments, the oxide or nitride layer can be thinner than the other dielectric or placeholder material layers to accommodate the layer of silicon while maintaining the overall stack thickness. In some embodiments, the silicon can increase the overall thickness of the stack. In some embodiments, a sufficient oxide thickness can be maintained to limit crosstalk or leakage between developed cells, and the thickness of the nitride layer can be reduced to accommodate the incorporated layer of silicon. A silicon layer may be characterized by a thinner thickness than an oxide or nitride layer, and may be characterized by a thickness of about 10 nm or less, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4 nm or less, about 3 nm or less, about 2 nm or less, about 1 nm or less, or less.

[0045]

[0053] The temperature and pressure during any operation, either formation or removal, can be controlled depending on the operation being performed. Typically, the pressure in the process chamber can be about 30 Torr or less, and may be about 20 Torr or less, about 15 Torr or less, about 12 Torr or less, about 10 Torr or less, about 8 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less than that. For some embodiments including a process chamber including an inductively coupled plasma source and / or a turbomolecular pump, the process pressure may be further reduced to about 100 mTorr or less, about 90 mTorr or less, about 80 mTorr or less, about 70 mTorr or less, about 60 mTorr or less, about 50 mTorr or less, about 40 mTorr or less, about 30 mTorr or less, about 20 mTorr or less, about 10 mTorr or less, about 5 mTorr or less, about 2 mTorr or less, or less than that.

[0046]

[0054] Either the forming or removing operations may be performed at one or more processing temperatures, which may be about 200° C. or higher, about 250° C. or higher, about 300° C. or higher, about 350° C. or higher, about 400° C. or higher, about 450° C. or higher, about 500° C. or higher, or higher. Various plasma sources, precursor flow rates, and other chamber conditions may be modified during either the forming or other processing operations as well. After the stack of materials is prepared, further processing operations may be performed. For example, an annealing operation may be performed at a temperature, for example, about 700° C. or higher, in some embodiments, and may be performed at a temperature that may be about 750° C. or higher, about 800° C. or higher, about 850° C. or higher, about 900° C. or higher, or higher. Annealing may be performed with a heated precursor, such as an inert precursor including nitrogen. A reactive ion etching process may be performed to generate one or more openings, such as memory holes, through the stack of layers. Further, stepped structures may be formed in outer regions of the stack, and additional processing may be performed to create memory or other semiconductor structure aspects. To begin creating memory cells, a placeholder material, such as a silicon nitride layer, may be removed from the structure.

[0047]

[0055] In operation 330, the silicon nitride layer(s) may be removed from the stack of layers, as shown in FIG. 4B. Many removal operations may be performed, and in some embodiments, a wet etching process using, for example, hot phosphoric acid may be performed to remove the nitride film. After the etching process is performed, the wet etchant is often dried from the structure. The surface tension of the etchant may affect the oxide layer. Conventionally formed cells having alternating oxide and nitride layers may cause deformation of the oxide, which may be characterized by a decrease in thickness and / or stiffness. For example, the Young's modulus of silicon oxide may be about 85 GPa or less, or about 80 GPa or less, which may increase the possibility of deformation during the etchant drying process. Although the Young's modulus of silicon oxide may be slightly increased with conditioned deposition, the Young's modulus may still plateau at less than about 90 GPa, or less than about 88 GPa. As a result, the surface tension generated by the wet etchant may overcome the strength of the film and cause distortion of the film.

[0048]

[0056] Some aspects of the present technology that incorporate a silicon layer between a nitride layer and an oxide layer may form an oxide reinforcement, which may facilitate resistance to surface tension associated with drying of etchant materials. For example, silicon, such as amorphous silicon, may be characterized by a higher Young's modulus. When incorporated into an oxide layer, the silicon layer or a layer adjacent to the silicon oxide layer may produce a composite material that includes an oxide that may be characterized by a Young's modulus of about 90 GPa or more, about 92 GPa or more, about 94 GPa or more, about 96 GPa or more, about 98 GPa or more, about 100 GPa or more, about 102 GPa or more, or higher. Similarly, an amorphous silicon layer may improve the hardness of the film. Whereas silicon oxide may be characterized by a hardness of less than 12 GPa, and may be characterized by a hardness of about 11.7 GPa or less, about 11.6 GPa or less, or less, the incorporation of a silicon layer may improve the hardness to about 12.0 GPa or more, and may improve the hardness of the composite layer to about 12.2 or more, about 12.4 or more, about 12.5 or more, about 12.6 or more, about 12.7 or more, about 12.8 or more, about 12.9 or more, about 13.0 or more, or more. As a result, the composite film can withstand the surface tension effects of the dried etchant material.

[0049]

[0057] Furthermore, amorphous silicon is more resistant to wet etching, and nitride removal may be characterized by a higher selectivity to silicon over oxide. For example, the wet etchant may extend through a larger area of ​​the structure, which may maintain contact with the edge region of the oxide layer for a longer period of time, causing thinning of the oxide layer in some areas. The amorphous silicon layer may protect the entire area of ​​the oxide and extend completely across the entire formed structure. The amorphous silicon may cover the edge region of the oxide layer, which may limit long-term interaction with the wet etchant. Thus, the oxide layer may be further protected from thinning by the wet etchant.

[0050]

[0058] After removal of the silicon nitride, in some embodiments, a layer of silicon may be removed. Metal filling may occur in the opened access, but the loss of volume from the silicon layer may increase the metal line resistance. Therefore, a second removal process may be performed to selectively remove the first and second layers of silicon from the remaining oxide layer, as shown in operation 225 and in FIG. 4C. Selectively removing silicon relative to silicon oxide may be performed with a variety of processes, and in some embodiments may include a dry etching process, including a plasma dry etching process.

[0051]

[0059] In some embodiments, the substrate may be transferred from a first processing chamber or processing system to a second processing chamber on the same system or to a separate system on which the dry etch chamber may be located. In some embodiments, the dry etch chamber and the deposition chamber may be on the same chamber system, which may allow the substrate to be transferred from the first processing system to the second processing chamber while maintaining vacuum conditions. In some embodiments, the wet etch process may occur on a similar or different processing system, which may include transferring the substrate between chambers and / or systems during operation of the method.

[0052]

[0060] When delivered to the dry etch processing chamber, the substrate may have the nitride layer removed, leaving exposed regions or layers of silicon, such as amorphous silicon, and layers of oxide that may be at least partially disposed between the regions or layers of silicon. The silicon removal operation may be performed with one or more precursors, including fluorine-containing precursors, and may also include one or more additional precursors, which may include inert or noble gases, such as hydrogen-containing precursors, and other materials that may facilitate the etching process. In some embodiments, one or both of the fluorine-containing precursor or hydrogen-containing precursor may be flowed into a remote plasma region of the dry etch processing chamber. For example, the remote plasma region may be fluidly coupled to the processing region that contains the substrate, but the regions may be physically separated, such as by a showerhead that may act as an electrode in the remote plasma region. A remote plasma system may also be externally coupled to the chamber and provide plasma effluents into the chamber.

[0053]

[0061] The plasma effluent of the precursors may be delivered into the processing region to contact the silicon layer and selectively remove them from the oxide layer. The processing conditions may be configured in one or more ways to provide selective etching of silicon relative to oxide, which may be characterized by a selectivity of about 100:1 or greater. For example, the processing chamber, pedestal, or substrate may be maintained at a temperature between about 40° C. and about 150° C. during the etching or removal operation, and the pressure in the processing chamber may be maintained at about 12 Torr or less, for example. Additionally, in some embodiments, the flow rate of the fluorine-containing precursor and / or the hydrogen-containing precursor may be adjusted to maintain a flow rate ratio between the precursors.

[0054]

[0062] For example, in some embodiments, the removal can be performed while maintaining an atomic flow ratio of hydrogen to fluorine of about 10:1 or more. Such a process can maintain a hydrogen-terminated surface, which can allow fluorine to selectively remove silicon relative to oxide. Exemplary hydrogen-containing precursors can include one or more precursors that contain hydrogen, such as diatomic hydrogen, ammonia, hydrocarbons, or other precursors that contain hydrogen. Exemplary fluorine-containing precursors can include one or more precursors that include, by way of non-limiting example, atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, fluorinated hydrocarbons, sulfur hexafluoride, or xenon difluoride. After removal of the silicon layer, further processing can be performed, including metallization.

[0055]

[0063] In some embodiments, additional operations may be performed to improve the nucleation and formation of metal in the trenches outlined by the oxide material. For example, in some embodiments, a liner or other material may be formed along the exposed surface of the oxide in optional operation 340, illustrated as material 420 in FIG. 4D. The liner material may include a number of barrier or liner metals, including metal nitrides such as titanium nitride, which may include any number of transition metals or other materials. The liner material may be formed conformally along the oxide layer and may protect the oxide surface from diffusion or exposure to emissions of metal-containing precursors, which may include halogen materials or other materials that may react with the oxide.

[0056]

[0064] In operation 345, a metal layer, if incorporated, may be formed between layers of oxide and / or liner material, as shown as material 425 in FIG. 4D. One or more metal-containing or deposition precursors may be used to deposit the metal material in the open trench area and form a conductive cell material between the layers of oxide material. For example, tungsten, cobalt, or other conductive metals or materials may be used as the metal for cell formation in embodiments of the present technology.

[0057]

[0065] As mentioned above, the liner material may be incorporated into the trench to facilitate the nucleation of a metal material, such as tungsten in one non-limiting embodiment. Tungsten and other metal materials may not be easily deposited on silicon oxide, and therefore an additional layer of material may often be included to facilitate deposition. Furthermore, since the oxide material may act to separate cells, such as in memory applications, limiting the diffusion or removal of metal from the metal deposition by-products may limit crosstalk and prevent short circuits or device malfunction. However, the incorporation of the liner material, even at a thickness of a few nanometers or less, may further limit the volume that may be occupied by the metal. As stack dimensions continue to shrink, the reduced amount of metal may dramatically increase the resistance of the material.

[0058]

[0066] As previously mentioned, the silicon layer may improve the oxide resistance to deformation or collapse during wet etch removal of the silicon nitride layer. In some embodiments of the present technology, the formed silicon layer may also be utilized to facilitate the formation of tungsten or other metals. Referring to FIG. 5, an exemplary operation in a method 500 of forming a semiconductor structure according to some embodiments of the present technology is shown. The method may include forming a stack structure and converting aspects of the structure for metal incorporation. The method 500 may include any number of similar operations described above for the method 300 and may include any operation, material, or property of any of the aspects described above. Furthermore, the method may be performed in a variety of processing chambers, including the processing chamber 200 described above, and may be incorporated into the system 100, for example. The method 500 may describe operations shown generally in FIGS. 6A-6D. These figures are described in conjunction with the operations of the method 500. It should be understood that the figures show only partial schematic views and that a substrate may include any number of structural sections having the aspects as shown in the figures, as well as alternative structural aspects that may still benefit from the operations of embodiments of the present technology.

[0059]

[0067] Similar to that described above for method 300, method 500 may include forming a first oxide layer over the substrate at operation 505. A first amorphous silicon layer may be formed over the silicon oxide layer at operation 510. A silicon nitride layer may be formed over the amorphous silicon layer at operation 515. A second amorphous silicon layer may be formed over the silicon nitride layer at operation 520. A second silicon oxide layer may be formed over the second amorphous silicon layer at operation 525. Any of these operations may be performed using any of the precursors described above, any of the processing conditions or considerations described above, and may include any aspect or property of any of the aforementioned processes, materials, or properties.

[0060]

[0068] The stack may extend in any number of layers and include any number of constituent layers of material as described above. For example, the described operations may be repeated any number of times until a predetermined number of pairs of layers that may constitute a stack of layers may be formed. For example, any number of layers may be produced in the structure, from about 10 or less layers of material to 200 or more layers of material. The stack may begin or end with any of the layers described. In FIG. 6A, only one encompassing configuration is shown, with silicon layer 613 encompassing silicon layer 609 and nitride layer 611, with all three layers between oxide layers 607 and 615 formed above substrate 605. As described above, additional operations may be performed in some cases, such as memory hole formation or other film formation aspects. As shown in FIG. 6B, after the formation of the film and any additional optional operations, the silicon nitride layer may be removed in operation 530. As described above, the removal may be performed using a wet etchant, but additional techniques may be included in the technology as well.

[0061]

[0069] The method 300 above encompassed an embodiment in which the silicon layer is subsequently removed, such as by a dry etching process. The present technology also encompasses processes in which the silicon layer may alternatively be utilized in the conversion reaction. For example, in operation 535, the silicon layer may be converted to a metal-containing layer 620, as shown in FIG. 6C. Some metal materials may be used to perform the conversion reaction of amorphous silicon, which may provide an exchange of silicon for a metal material. By performing an exchange reaction, a metal material may be formed along the silicon oxide surface while maintaining a relatively inconspicuous transition between the layers. This may allow metal formation without additional formation of a liner and / or nucleation layer, as described above. Removing the formation of the liner layer may produce a thicker and more overall volumetric metal material between the oxide layers, which may improve the resistance through the metal.

[0062]

[0070] The conversion reaction may include flowing a metal-containing precursor into the processing region to contact the amorphous silicon layer and causing a reaction between the materials. The reaction may be based at least in part on a thermally activated reaction, and the conversion may be carried out at a temperature of about 300° C. or higher, and may be carried out at a temperature of about 350° C. or higher, about 400° C. or higher, about 450° C. or higher, about 500° C. or higher, about 550° C. or higher, about 600° C. or higher, about 650° C. or higher, about 700° C. or higher, about 750° C. or higher, or higher. For example, the exchange of tungsten with silicon may be carried out by the following reaction: may occur along TIFF0007657793000001.tif7170 where X may be, for example, 1 or 2 and Y may be, for example, 2 or 4, among other integers or decimals.

[0063]

[0071] As a result, the reaction may form volatile silicon by-products while leaving solid metal to form a layer of metal material. The thickness of the silicon layer may affect the material since exchange reactions may be performed. For example, if the silicon layer extends beyond a certain threshold, complete conversion may not occur and residual silicon may be trapped between the oxide layer and the formed layer of metal. As a result, in some embodiments, the silicon layer may be maintained at a thickness of about 5 nm or less, and may be maintained at a thickness of about 4 nm or less, about 3 nm or less, about 2 nm or less, or less.

[0064]

[0072] By carrying out the conversion reaction, the formation at the edge region can be maintained while the metal-containing precursor extends into the trench. Thus, pinch-off and void formation can be reduced in some embodiments. After the conversion of the silicon material to metal, additional processing can be performed to complete the layer of metal-containing material. As shown in FIG. 6D, the metal material 625 can be extended to connect the converted portions of the metal material to produce a substantially or completely continuous layer of metal material extending between the oxide layers. Thus, in some embodiments, the volume of metal material can be increased in structures where nucleation and / or barrier layers cannot be incorporated along the silicon oxide material.

[0065]

[0073] Embodiments of the present technology may also include additional conditioning to strengthen the oxide layer to limit or prevent deformation or collapse during wet process removal of the silicon nitride material. In some embodiments of the present technology, the formed silicon oxide layer may be conditioned with doping to enhance resistance to deformation due to surface tension effects. Referring to FIG. 7, an exemplary operation in a method 700 of forming a semiconductor structure according to some embodiments of the present technology is shown. The method may include forming a stack structure utilizing a modified silicon oxide material as a dielectric layer. The method 700 may include any number of similar operations described above for the method 300 or the method 500, and may include any operation, material, or property of any aspect previously described. Furthermore, the method may be performed in a variety of processing chambers, including the processing chamber 200 described above, and may be incorporated into the system 100, for example. The method 700 may describe the operations shown generally in FIGS. 8A-8D. These figures will be described in conjunction with the operations of the method 700. It should be understood that the drawings are only partial schematic views and that the substrate may include any number of structural sections having the aspects as shown in the drawings, as well as alternative structural aspects that may still benefit from the operation of embodiments of the present technology.

[0066]

[0074] In some embodiments, the method 700 may include forming a modified oxide layer over the substrate in operation 705 and as shown as layer 807 over the substrate 805 in FIG. 8A. The modified layer may include one or more dopants or stoichiometric adjustments. A silicon nitride layer may be formed over the amorphous silicon layer in operation 710. This may be illustrated as layer 809 in FIG. 8A. A second modified silicon oxide layer may be formed over the silicon nitride layer in operation 715. This may be illustrated as layer 811 in FIG. 8A. The second modified layer may also include one or more dopants or stoichiometric adjustments. This may be similar or different to the first silicon oxide layer in embodiments of the present technology. In some embodiments of the present technology, additional processing may be performed, including, for example, memory hole or step formation. In operation 720, as shown in FIG. 8B, the layer of silicon nitride may be removed, which may also be performed by any removal technique, including wet etch removal as described above.

[0067]

[0075] The modified silicon oxide layer may be modified to increase resistance to deformation from wet etching effects. Wet etching effects may be caused by the surface tension of the etchant used to remove the nitride. In some embodiments, one or more dopants may be incorporated to increase the Young's modulus of the silicon oxide, which may also increase the hardness of the material. For example, in some embodiments, a nitrogen dopant may be incorporated into the film during formation to provide an amount of nitrogen incorporated into the oxide film. During layer formation, nitrogen or a nitrogen-containing precursor may be flowed with the silicon-containing precursor and / or the oxygen-containing precursor. The nitrogen-containing precursor may include any of the nitrogen-containing precursors described above, and any combination of the precursors described above.

[0068]

[0076] Nitrogen incorporation may be performed to increase film properties and enhance structural integrity, and by incorporating nitrogen doping, the Young's modulus of the modified oxide may be increased to about 90 GPa or more, and may be increased to about 95 GPa or more, about 100 GPa or more, about 105 GPa or more, about 110 GPa or more, about 115 GPa or more, about 120 GPa or more, about 125 GPa or more, or higher. Furthermore, the stiffness of the film may be increased to about 12 GPa or more, and may be increased to about 13 GPa or more, about 14 GPa or more, about 15 GPa or more, about 16 GPa or more, about 17 GPa or more, or higher.

[0069]

[0077] Since nitride removal may operate selectively to oxide materials, increasing the nitrogen doping in the oxide film may increase the etching properties of the oxide material. Thus, in some embodiments, to maintain selectivity during nitride removal, the nitrogen incorporation may be maintained at about 10 at.% or less, and may be maintained at about 8 at.% or less, about 7 at.% or less, about 6 at.% or less, about 5 at.% or less, about 4.5 at.% or less, about 4.0 at.% or less, about 3.5 at.% or less, about 3 at.% or less, about 2.5 at.% or less, about 2 at.% or less, about 1.5 at.% or less, about 1 at.% or less, about 0.5 at.% or less, or less. To ensure increased structural integrity, the nitrogen incorporation may be maintained at about 0.5 at.% or more, or higher.

[0070]

[0078] Furthermore, in some embodiments, the stoichiometry of the silicon oxide film can be adjusted to increase the film properties. By increasing the silicon-like properties of the film, the structural integrity can be increased compared to silicon oxide films. In order to increase the stoichiometry of the formed film, in some embodiments, the delivery of the precursors can be modified from standard silicon oxide deposition conditions. For example, during some processes, the silicon to oxide atomic ratio can be up to 1:7 in some embodiments. During the formation method according to some embodiments of the present technology, the silicon to oxide ratio can be adjusted to about 1:7 or less, and can be adjusted to about 1:6 or less, about 1:5 or less, about 1:4 or less, about 1:3 or less, about 1:2 or less, about 1:1 or less, or less. By providing a formation process that is relatively oxygen deficient compared to other formations, the oxygen to silicon ratio in the produced film may be about 2.0:1 or less, may be about 1.9:1 or less, may be about 1.8:1 or less, may be about 1.7:1 or less, may be about 1.6:1 or less, may be about 1.5:1 or less, or less.

[0071]

[0079] By increasing silicon incorporation in the film, the Young's modulus of the modified oxide may be increased to about 100 GPa or more, and may be increased to about 110 GPa or more, about 120 GPa or more, about 125 GPa or more, about 130 GPa or more, about 135 GPa or more, about 140 GPa or more, about 145 GPa or more, about 150 GPa or more, about 155 GPa or more, about 160 GPa or more, or higher. Additionally, the hardness of the film may be increased to about 12 GPa or more, and may be increased to about 13 GPa or more, about 14 GPa or more, about 15 GPa or more, about 16 GPa or more, about 17 GPa or more, or higher. Any of the aforementioned additional treatments may also be incorporated into optional operations of one or more aspects of method 700, including nitrogen or other high temperature annealing after film formation.

[0072]

[0080] The dielectric material of the stack may separate cells, such as memory cells, that are created by subsequent processing. Nitrogen doping, silicon-rich films, or other doping or modification may affect leakage of the created film, which may affect device performance. Thus, in some embodiments, the method 700 may include treating the modified oxide material at operation 725 after etching or removing the nitride layer. The treatment may include removing dopant concentrations or adjusting film properties to be more silicon oxide, as in the embodiment shown as silicon oxide layer 815 in FIG. 8C. For example, treating the modified oxide may include performing an oxygen treatment, which in some included embodiments may include a water vapor anneal or other oxygen treatment. Annealing may be performed to extract nitrogen or other dopants and / or increase oxygen incorporation in the film, which may be performed at any temperature described above, including temperatures of 500° C. or higher, or higher temperatures. As shown in FIG. 8D, additional operations may optionally be performed to form a metal layer 820, which may include any of the materials, including the optional liners, discussed above.

[0073]

[0081] After water vapor annealing, testing has shown that nitrogen incorporation can be reduced to nominal levels, such as those found in standard oxide films. Furthermore, the stoichiometry of the treated films can be characterized by a substantially or essentially 2:1 oxygen to silicon ratio. The leakage current density in the treated films is approximately 1×10 -6 A / cm 2 It may be maintained at less than about 8×10 -7 A / cm 2 Below, approximately 5×10 -7 A / cm 2 Below, approximately 2×10 -7 A / cm 2 Below, approximately 1×10 -7 A / cm 2 Below, approximately 9×10 -8 A / cm 2 Below, approximately 8×10 -8 A / cm 2 Below, approximately 7×10-8 A / cm 2 Below, approximately 6×10 -8 A / cm 2 Below, approximately 5×10 -8 A / cm 2 Below, approximately 4×10 -8 A / cm 2 Below, approximately 3×10 -8 A / cm 2 Below, approximately 2×10 -8 A / cm 2 Below, approximately 1.5×10 -8 A / cm 2 Below, approximately 1.2×10 -8 A / cm 2 Below, approximately 1×10 -8 A / cm 2 It may be maintained at or below that.

[0074]

[0082] Additionally, the treated oxide layer may be characterized by a breakdown voltage of about 6.0 MV / cm or greater, and may be characterized by a breakdown voltage of about 7.0 MV / cm or greater, about 7.5 MV / cm or greater, about 8.0 MV / cm or greater, about 8.5 MV / cm or greater, about 9.0 MV / cm or greater, about 9.5 MV / cm or greater, about 10.0 MV / cm or greater, about 10.5 MV / cm or greater, about 11.0 MV / cm or greater, about 11.5 MV / cm or greater, about 12.0 MV / cm or greater, about 12.5 MV / cm, or greater. As a result, the present techniques can produce oxide films that can be strengthened as composite layers, and can also produce modified oxide layers, either of which can be substantially retained or treated to resist deformation and collapse during wet etching or other removal processes and improve electrical performance.

[0075]

[0083] In the above description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional details.

[0076]

[0084] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Thus, the above description should not be considered as limiting the scope of the present technology. Additionally, while a method or process may be described sequentially or stepwise, it should be understood that the operations may be performed simultaneously or in a different order than described.

[0077]

[0085] Where a range of values ​​is provided, it is to be understood that each intervening value between the upper and lower limits of that range is specifically disclosed to the smallest unit of the lower limit, unless the context clearly indicates otherwise. Any narrower ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also encompassed. The upper and lower limits of these smaller ranges may be individually included or excluded from the range, and each range in which either, neither or both limits are included in the smaller ranges is also encompassed within the scope of the technology, subject to any specifically excluded limits in the stated range. Where one or both limits are included in a stated range, ranges excluding either or both of those inclusive limits are also included.

[0078]

[0086] As used in the specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes reference to one or more layers and equivalents known to those skilled in the art, and so forth.

[0079]

[0087] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. 1. A method of forming a semiconductor structure, comprising: forming a first silicon oxide layer overlying a semiconductor substrate; forming a first silicon layer overlying the first silicon oxide layer; forming a silicon nitride layer overlying the first silicon layer; forming a second silicon layer overlying the silicon nitride layer; forming a second silicon oxide layer overlying the second silicon layer; removing the silicon nitride layer; removing the first silicon layer and the second silicon layer; forming a metal layer between each of the first and second silicon oxide layers; and

2. The method for forming a semiconductor structure of claim 1 , wherein the silicon nitride layer is removed by a wet etching process.

3. 10. The method of forming a semiconductor structure of claim 1, wherein the first silicon layer and the second silicon layer are removed by a dry etching process.

4. 10. The method for forming a semiconductor structure of claim 1, wherein said second silicon layer and said second silicon oxide layer form a composite film characterized by a Young's modulus of about 90 GPa or greater.

5. The method for forming a semiconductor structure of claim 1 , wherein the metal layer comprises tungsten.

6. 2. The method of forming a semiconductor structure of claim 1, further comprising forming a liner layer along the first silicon oxide layer and the second silicon oxide layer after removing the first silicon layer and the second silicon layer.

7. forming the first silicon oxide layer occurs in a first processing chamber and removing the first silicon layer and the second silicon layer occurs in a second processing chamber, the method comprising:

10. The method of forming a semiconductor structure of claim 1, further comprising transferring the semiconductor substrate from the first processing chamber to the second processing chamber while maintaining a vacuum condition.

8. 10. The method of forming a semiconductor structure of claim 1, wherein the first silicon oxide layer and the second silicon oxide layer are characterized by a thickness of about 50 nm or less.

9. 1. A method of forming a semiconductor structure, comprising: forming a first silicon oxide layer overlying a semiconductor substrate; forming a first amorphous silicon layer overlying the first silicon oxide layer; forming a silicon nitride layer overlying the first amorphous silicon layer; forming a second amorphous silicon layer overlying the silicon nitride layer; forming a second silicon oxide layer overlying the second amorphous silicon layer; removing the silicon nitride layer; and converting the first and second amorphous silicon layers into a metallic material in contact with the first and second silicon oxide layers, respectively; and

10. The converting step comprises: flowing a metal-containing precursor to contact the first amorphous silicon layer and the second amorphous silicon layer; forming a volatile silicon-containing by-product while forming the layer of metallic material.

10. The method of claim 9 for forming a semiconductor structure, comprising:

11. 10. The method of forming a semiconductor structure of claim 9, further comprising forming a layer of metallic material extending between the first silicon oxide layer and the second silicon oxide layer.

12. 10. The method of forming a semiconductor structure of claim 9, wherein the silicon nitride layer is removed by a wet etching process.

13. 10. The method of forming a semiconductor structure of claim 9, wherein the first amorphous silicon layer and the second amorphous silicon layer are characterized by a thickness of about 5 nm or less.

14. 1. A method of forming a semiconductor structure, comprising: forming a first silicon oxide layer overlying a semiconductor substrate, the first silicon oxide layer including a nitrogen dopant or a silicon-rich stoichiometry and characterized by a Young's modulus of 110 GPa or greater; forming a silicon nitride layer overlying the first silicon oxide layer; forming a second silicon oxide layer overlying the silicon nitride layer, the second silicon oxide layer including a nitrogen dopant or a silicon-rich stoichiometry; removing the silicon nitride layer; and Treating the first silicon oxide layer and the second silicon oxide layer. and

15. 15. The method of forming a semiconductor structure of claim 14, wherein said treating comprises performing a water vapor anneal.

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