Memory device

Abstract

To provide a semiconductor device with a novel structure, in which a memory content can be held even in a situation with no power supply in a memory holding period, and the number of times of writing is not limited.SOLUTION: A semiconductor device includes a first transistor including a first channel formation region including a semiconductor material other than an oxide semiconductor, a second transistor including a second channel formation region including an oxide semiconductor material over the first transistor, and a capacitor element. One of a second source electrode and a second drain electrode of the second transistor is connected electrically to one electrode of the capacitor element.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. They are broadly divided into volatile and non-volatile types, which retain their memory contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from the transistors. By storing charge in the capacitor, information is stored.

[0004] According to the above principle, when information is read from a DRAM, the charge on the capacitor is lost. Every time information is read, a write operation is required again. A leakage current exists in the transistor, and charge flows out even when the transistor is not selected. Therefore, the data retention period is short. Refresh operations are required, making it difficult to sufficiently reduce power consumption. In addition, if the power supply is cut off, the memory contents are lost, so magnetic recording is necessary for long-term memory retention. Therefore, alternative storage devices using electrical and optical materials are needed.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store data. No refresh operation is required to retain data, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, if the power supply is cut off, the memory contents are lost. In this regard, there is no difference with DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data is retained for an extremely long period of time. The advantage is that it lasts a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. For example, see Patent Document 1.

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem that the memory element may become non-functional after a certain number of writes. In order to alleviate the effect of this problem, for example, the number of write operations to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of life span is not solved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to hold charge on the floating gate or to remove that charge. This requires high voltage and a circuit for it. It takes a relatively long time to erase or write data, and it is not easy to speed up writing and erasing. There is also the problem that... [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above problems, in one embodiment of the disclosed invention, a memory device in which power is not supplied during a memory retention period is provided. A new structure that allows memory contents to be retained even in difficult situations and has no limit on the number of times it can be written. An object is to provide a semiconductor device. [Means for solving the problem]

[0011] In the disclosed invention, a semiconductor device is formed using a highly purified oxide semiconductor. Since a transistor using a tantalum oxide semiconductor has an extremely low leakage current, , it is possible to retain information for a long period of time.

[0012] One embodiment of the disclosed invention is a first channel type semiconductor device using a semiconductor material other than an oxide semiconductor. a first channel forming region, impurity regions provided so as to sandwich the first channel forming region, a first gate insulating layer on the gate forming region; a first gate electrode on the first gate insulating layer; a first source electrode and a first drain electrode electrically connected to the pure region; A first transistor and a second source electrode and a second drain electrode above the first transistor. a second source electrode and a second drain electrode; A second channel forming region using a conductive material and a second gate electrode on the second channel forming region. a second transistor having a gate insulating layer and a second gate electrode on the second gate insulating layer. a second source electrode or a second drain electrode of the second transistor; In the semiconductor device, one of the gate electrodes and one of the electrodes of the capacitor are electrically connected to each other.

[0013] In the above, the capacitance element has a second source electrode or a second drain electrode and a second gate The first gate insulating layer and a capacitance element electrode on the second gate insulating layer. .

[0014] In the above, a third source electrode and a third drain electrode are provided above the first transistor. a third source electrode and a third drain electrode, and the third source electrode and the third drain electrode are electrically connected to the oxide semiconductor A third channel forming region using a dielectric material and a third gate electrode on the third channel forming region. a third transistor having a third gate insulating layer and a third gate electrode on the third gate insulating layer. a source line, a bit line, a word line, a first signal line, and a second signal line; a gate electrode of the first gate electrode, one of a second source electrode and a second drain electrode, and an electrode of a capacitance element The source line and the third source electrode are electrically connected to each other. The bit line and the third drain electrode are electrically connected to each other, and the first signal line and the second source electrode are electrically connected to each other. The other of the first source electrode and the second drain electrode is electrically connected to the second signal line. The gate electrode is electrically connected, and the word line is electrically connected to the other electrode of the capacitor element. The configuration may be a continuous one.

[0015] In the above, the first transistor is used to form a logic circuit (arithmetic circuit) or a driving circuit. A path can be constructed.

[0016] In this specification, the terms "above" and "below" refer to the positional relationship of components "directly above" or "below." For example, "gate electrode on a gate insulating layer" is not limited to "directly under". ", it excludes those that include other components between the gate insulating layer and the gate electrode. In addition, the terms "upper" and "lower" are merely used for the convenience of explanation and are not to be specifically mentioned. Except in certain cases, this also includes those with the top and bottom reversed.

[0017] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0018] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification and the like, the terms "source" and "drain" may be used interchangeably. It is possible.

[0019] In this specification, "electrically connected" means "something that has some kind of electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects.

[0020] For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as Effect of the Invention

[0021] In one embodiment of the present invention, a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor are A semiconductor device using the above-mentioned transistor stack structure is provided.

[0022] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0023] In addition, the semiconductor device according to the disclosed invention does not require a high voltage to write information. There is no problem with degradation of the molecules. For example, unlike conventional non-volatile memory, there is no electron transfer to the floating gate. Since there is no need to inject or extract electrons from the floating gate, there is no degradation of the gate insulating layer and In other words, the semiconductor device according to the present invention does not have the same problems as the conventional non-volatile semiconductor memory device. There is no limit to the number of times it can be rewritten, which is a problem with nonvolatile memory, and reliability is dramatically improved. Furthermore, information is written depending on the on / off state of the transistor. Therefore, high-speed operation can be easily realized. In addition, there is no need to perform an operation to erase information. There are also benefits to this.

[0024] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. Therefore, by using this, various circuits that require high-speed operation (logic circuits, driver circuits, etc.) ) can be suitably realized.

[0025] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief description of the drawings]

[0026] [Figure 1] FIG. [Diagram 2] FIG. [Diagram 3] FIG. [Figure 4] FIG. [Diagram 5] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views relating to a manufacturing process of an SOI substrate. [Figure 12] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 13] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 14] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 15] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 16] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. [Figure 17] A diagram showing the results of a memory window width investigation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and may be modified in various forms and without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0028] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0029] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0030] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. 1 to 5. Note that in the circuit diagrams, To indicate that it is a transistor, the symbol OS may also be added.

[0031] (Outline of the configuration of the semiconductor device) FIG. 1 is a conceptual diagram showing an example of a configuration of a semiconductor device according to one embodiment of the disclosed invention. Typically, the device has a memory circuit in the upper part and a logic circuit (arithmetic circuit) that requires high speed operation in the lower part. The semiconductor device has a stacked structure including a transistor (also referred to as a transistor circuit) and a driver circuit.

[0032] The semiconductor device shown in FIG. 1 has a memory cell array 10 in an upper portion and a column decoder 11 in a lower portion. 20, row decoder 30, IO controller 40, IO buffer 50, command buffer A semiconductor device having driving circuits such as a memory 60, an address buffer 70, and a controller 80 ( The lower part may have a calculation circuit such as a CPU. Although a memory device has been described as an example of a semiconductor device, one embodiment of the disclosed invention is not limited to this. Not limited.

[0033] <Cross-sectional structure of semiconductor device> FIG. 2 is a cross-sectional view showing an example of a specific configuration of a semiconductor device. FIG. 2(A) shows a first example. FIG. 2(B) shows a cross section of the semiconductor device according to the second example. The semiconductor device shown in FIG. 2A and FIG. 2B has a lower portion including a semiconductor other than an oxide semiconductor. A transistor (transistor 170 or transistor 570) using the material The transistor 162 and the capacitor 164 are formed using an oxide semiconductor. Transistors using materials other than oxide semiconductors can easily operate at high speed and are useful for logic circuits. On the other hand, transistors using oxide semiconductors are It is used in memory circuits and other devices that utilize this characteristic.

[0034] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. The technical essence of the present invention is to use an oxide semiconductor as the transistor 162 to store data. Since the purpose is to use the semiconductor device, it is not necessary to limit the specific configuration of the semiconductor device to that shown here. .

[0035] The transistor 170 in FIG. 2A includes a semiconductor material (e.g., silicon). A channel forming region 116 is provided on the substrate 100, and a The impurity region 114 and the high-concentration impurity region 120 (collectively referred to as simply "non-doped region") are provided in the a gate insulating layer 108 provided on the channel forming region 116; A gate electrode 110 provided on the gate insulating layer 108 is electrically connected to the impurity region. A source or drain electrode 130a and a source or drain electrode 130b has.

[0036] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, the sidewall insulating layer 118 does not overlap the substrate 100 when viewed from a direction perpendicular to the surface of the substrate 100. The region has a high-concentration impurity region 120, and a metal compound A region 124 is formed on the substrate 100. The region 124 surrounds the transistor 170. A separation insulating layer 106 is provided, and an interlayer insulating layer 126 is provided to cover the transistor 170. and an interlayer insulating layer 128. and the source electrode or drain electrode 130b are formed between the interlayer insulating layer 126 and the interlayer insulating layer 12 8 is electrically connected to the metal compound region 124 through an opening formed in the , source or drain electrode 130a, and source or drain electrode 130 b is connected to the high concentration impurity region 120 and the impurity region 114 via the metal compound region 124 In addition, in order to integrate the transistor 170, the side wall In some cases, the insulating layer 118 is not formed.

[0037] The transistor 570 in FIG. 2B is a semiconductor layer on the nitrogen-containing layer 502 and the oxide film 512. A channel forming region 534 provided in a layer including a conductive material (e.g., silicon, etc.) and A low concentration impurity region 532 and a high concentration impurity region 533 are provided so as to sandwich a channel forming region 534. A dopant region 530 (collectively referred to as an impurity region) and a channel forming region 534 A gate insulating layer 522a is provided on the gate insulating layer 522a. a source electrode or drain electrode 540a electrically connected to the impurity region; and a source or drain electrode 540b.

[0038] Here, a sidewall insulating layer 528 is provided on the side surface of the gate electrode 524. In addition, when viewed from a direction perpendicular to the surface of the base substrate 500, the sidewall insulating layer 528 is overlapped with the sidewall insulating layer 528. The region that is not covered by the transistor 570 has a high concentration impurity region 530. As shown in FIG. 1, an interlayer insulating layer 536 and an interlayer insulating layer 538 are provided. The source or drain electrode 540a and the source or drain electrode 540b are formed on the interlayer insulating layer 53. 6 and the high concentration impurity region 530 through an opening formed in the interlayer insulating layer 538. In addition, in order to integrate the transistor 570, the sidewall insulation In some cases, layer 528 may not be formed.

[0039] The transistor 162 in FIG. 2(A) and FIG. 2(B) is provided on the insulating layer 138. The source or drain electrode 142a and the source or drain electrode 142 b, a source electrode or drain electrode 142a, and a source electrode or drain electrode 1 The oxide semiconductor layer 144 electrically connected to the source electrode or the drain electrode 42b is The gate electrode 142a, the source electrode or the drain electrode 142b, and the oxide semiconductor layer 144 are covered with the gate electrode 142a. a gate insulating layer 146 provided over the gate insulating layer 146 so as to overlap with the oxide semiconductor layer 144; and a gate electrode 148a.

[0040] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144. It is preferable that the gas is highly purified by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / c m 3 Less than 5×10 18 atoms / cm 3 Less than or equal to 5×10 1 7 atoms / cm 3 Note that the hydrogen concentration in the oxide semiconductor layer 144 is as follows: Secondary Ion Mass Spectrometry (SIMS) As shown in the figure, the hydrogen concentration was sufficiently reduced to produce a high-purity The defect level in the energy gap caused by oxygen deficiency is eliminated by supplying sufficient oxygen. In the oxide semiconductor layer 144 in which the carrier concentration is reduced, the carrier concentration is 1×10 12 / cm 3 Less than, hope Preferably 1×10 11 / cm 3 Less than 1.45×10 10 / cm 3 less than For example, the off-current density at room temperature (off-current divided by the channel width of the transistor) is value) is 10zA / μm to 100zA / μm (1zA (zeptoampere) is 1×10 -2 1 In this way, the oxide semiconductor is made i-type (intrinsic) or substantially i-type. By using a conductor, the transistor 162 can have excellent off-state current characteristics. do.

[0041] Note that in the transistor 162 in FIG. 2, the oxide semiconductor layer 144 is not processed into an island shape. In addition, contamination of the oxide semiconductor layer 144 due to etching during processing can be prevented.

[0042] The capacitor 164 includes a source or drain electrode 142 a, an oxide semiconductor layer 144 , a gate The gate insulating layer 146 and the electrode 148b are the source electrode or drain electrode. The drain electrode 142a functions as one electrode of the capacitance element 164, and the electrode 148b functions as the capacitance element 164. This serves as the other electrode of the capacitor 164 .

[0043] In the capacitor 164 in FIG. 2, the oxide semiconductor layer 144 and the gate insulating layer 146 are stacked. By this, the insulation between the source electrode or drain electrode 142a and the electrode 148b is reduced. This ensures sufficient security.

[0044] In the transistor 162 and the capacitor 164, the source electrode or the drain electrode The ends of the electrode 142a and the source or drain electrode 142b are tapered. Here, the taper angle is preferably set to, for example, 30° or more and 60° or less. The taper angle is the angle at which a layer having a tapered shape (e.g., a source electrode or a drain electrode 1 42a) from a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The inclination angle between the side and bottom of the layer is shown. The end of the electrode 142b is tapered to form a This is because the covering property of 144 can be improved and step disconnection can be prevented.

[0045] In addition, an interlayer insulating layer 150 is provided on the transistor 162 and the capacitance element 164. An interlayer insulating layer 152 is provided on the interlayer insulating layer 150 .

[0046] <Modifications of the semiconductor device> 3A and 3B are cross-sectional views showing modified examples of the configuration of a semiconductor device. FIG. 3(A) shows a cross section of a semiconductor device according to the first modification, and FIG. 3(B) shows a cross section of a semiconductor device according to the second modification. The semiconductor device shown in FIG. 3(A) and FIG. This corresponds to a modified example of the configuration shown in 2(A).

[0047] The difference between the semiconductor device shown in FIG. 3(A) and the semiconductor device shown in FIG. 2(A) is the interlayer insulation. Between the edge layer 128 and the insulating layer 138, the insulating layer 132 and the insulating layer 134 may be included. Here, the insulating layer 132 is made of silicon nitride to which hydrogen is added, and the insulating layer 1 Silicon nitride without hydrogen added is used for the insulating layer 34. Also, the insulating layer 138 is made of oxide. It is preferable that the material used is silicon.

[0048] In this manner, the insulating layer 132 made of silicon nitride to which hydrogen is added is provided in the lower layer, and the insulating layer 132 made of silicon nitride to which hydrogen is added is provided in the upper layer. By adopting a configuration having an insulating layer 134 made of silicon nitride to which no silicon is added, Hydrogen is added to the material (e.g., silicon) that constitutes the channel forming region 116 of the transistor 170. In addition, the characteristics of the transistor 170 are improved by supplying the Preventing hydrogen, which causes deterioration of the characteristics of the transistor 162, from entering the oxide semiconductor layer 144 The insulating layer 132 made of hydrogen-added silicon nitride can be formed by plasma. It can be formed by a method such as a CVD method. Also, silicon nitride without hydrogen added can be used. The insulating layer 134 made of copper can be formed by a sputtering method or the like. In this case, for example, the deposition atmosphere is a nitrogen atmosphere or a mixed atmosphere of nitrogen and argon. The sputtering target may be silicon that does not contain hydrogen.

[0049] The difference between the semiconductor device shown in FIG. 3B and the semiconductor device shown in FIG. 2A is the interlayer insulation. The difference is whether or not there is an insulating layer 134 between the edge layer 128 and the insulating layer 138. The layer 134 is made of silicon nitride to which hydrogen is not added. The interlayer insulating layer 128 and the insulating layer 138 are made of silicon nitride to which hydrogen is added. It is preferable that the insulating layer 100 be made of silicon oxide.

[0050] In this way, the interlayer insulating layer 126 is made of hydrogen-doped silicon nitride. By adopting a configuration having an insulating layer 134 made of silicon nitride that is not Hydrogen is supplied to the material (e.g., silicon) constituting the channel forming region 116 of the stadium 170. In addition, the characteristics of the transistor 170 can be improved. To prevent hydrogen, which causes deterioration of the characteristics of the capacitor 162, from being mixed into the oxide semiconductor layer 144. The interlayer insulating layer 126 made of silicon nitride to which hydrogen is added can be etched by plasma C. It can be formed by the VD method or the like. Also, silicon nitride without hydrogen added can be used. The insulating layer 134 can be formed by a sputtering method or the like. For example, the deposition atmosphere is a nitrogen atmosphere or a mixed atmosphere of nitrogen and argon, and the sputtering is performed. The target to be deposited may be silicon that does not contain hydrogen.

[0051] <Modifications of the upper transistor and capacitor element> Next, a modification of the transistor 162 and the capacitor element 164 in the upper part of FIG. 2 is shown in FIG. show.

[0052] The transistor and the capacitor shown in FIG. 4A are the upper transistors of the semiconductor device shown in FIG. This is one of the modified examples of the transistor and the capacitance element.

[0053] The difference between the structure illustrated in FIG. 4A and the structure illustrated in FIG. 2 is that the oxide semiconductor layer is formed into an island shape. That is, in the structure shown in FIG. 2, the oxide semiconductor layer 144 is A source or drain electrode 142a and a source or drain electrode 142b In contrast, in the structure shown in FIG. 144 includes an insulating layer 138, a source or drain electrode 142a, and a source or drain electrode 142b. The oxide semiconductor layer 144 is formed of an island-shaped oxide semiconductor layer 144. The end portion is preferably tapered. The taper angle is, for example, 30° to 60°. It is preferable that:

[0054] In addition, in the capacitor 164, an oxide semiconductor layer 144 and a gate insulating layer 146 are stacked. As a result, the insulation between the source electrode or drain electrode 142a and the electrode 148b is improved. can be sufficiently secured.

[0055] The transistor and the capacitor shown in FIG. 4B are the upper transistors of the semiconductor device shown in FIG. This is one of the modified examples of the transistor and the capacitance element.

[0056] The difference between the configuration shown in FIG. 4B and the configuration shown in FIG. 2 is that the insulating layer 143 is is formed on the drain electrode 142a and the source or drain electrode 142b. Furthermore, the oxide semiconductor layer 144 is formed on the insulating layer 143, the source electrode or the drain electrode. The insulating layer 142 is formed to cover the in-electrode 142a and the source or drain electrode 142b. The oxide semiconductor layer 144 is exposed through an opening in the insulating layer 143. The source electrode or drain electrode 142a is provided in contact with the source electrode or drain electrode 142a.

[0057] By providing the insulating layer 143, the gate electrode and the source electrode or the drain electrode are This reduces the capacitance formed in the transistor, thereby enabling the transistor operation to be performed at a high speed.

[0058] The transistor and the capacitor shown in FIG. 4C are the same as those shown in FIG. 4A and FIG. 4B. The configuration is partially different from that of the capacitor and the capacitance element.

[0059] The difference between the configuration shown in FIG. 4C and the configuration shown in FIG. 4A is that the insulating layer 143 is A source or drain electrode 142a and a source or drain electrode 142b are formed on the Furthermore, the oxide semiconductor layer 144 is formed on the insulating layer 143, the source electrode, or the The insulating layer 142 is formed so as to cover the drain electrode 142a and the source or drain electrode 142b. The difference between the configuration shown in FIG. 4(C) and the configuration shown in FIG. 4(B) is The feature of the present invention is that the oxide semiconductor layer 144 is formed in an island shape. 4B) can be obtained in combination with the effect of the configuration of FIG.

[0060] <Circuit Configuration and Operation of Semiconductor Device> Next, an example of the circuit configuration of the semiconductor device and its operation will be described. 1 is an example of a circuit configuration using the semiconductor device shown in FIG.

[0061] In the semiconductor device shown in FIG. 5(A-1), a first wiring (1st Line: source line) The source electrode of the transistor 160 is electrically connected to the second wiring (also referred to as 2n The drain electrode of the transistor 160 is electrically connected to the bit line (also called the bit line). Also, the third line (also called the first signal line) and the trans The fourth transistor 162 is electrically connected to either the source electrode or the drain electrode of the fourth transistor 162. The line (also called the 4th Line: second signal line) and the gate electrode of the transistor 162 , are electrically connected to the gate electrode of the transistor 160 and the The other of the source electrode and the drain electrode of the capacitor 162 is electrically connected to one of the electrodes of the capacitor 164. , and a fifth wiring (also called a word line) and a capacitor element 164 The other electrode is electrically connected.

[0062] Here, the transistor 160 and the transistor 162 are formed using the above-described oxide semiconductor. The above-described transistor using an oxide semiconductor has a low off-state current. Therefore, the transistor 162 is turned off. This allows the potential of the gate electrode of the transistor 160 to be held for an extremely long period of time. By providing the capacitance element 164, the gate of the transistor 160 This makes it easier to hold the charge given to the electrode, and easier to read out the stored information. Note that the transistor 162 using an oxide semiconductor has a channel length (L) of 10 nm. Since the device is 1000 nm or less, it consumes little power and operates at extremely high speeds. It has the following characteristics.

[0063] In the semiconductor device shown in FIG. 5A-1, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0064] First, the writing and holding of information will be explained. The transistor 162 is turned on by applying a potential that turns the transistor 162 on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the That is, a predetermined charge is applied to the gate electrode of the transistor 160. Here, the charge that gives two different potential levels (hereafter, Low level) is Then, a fourth charge (called a low-level charge or a high-level charge) is applied. The potential of the wiring is set to a potential at which the transistor 162 is turned off, By turning off the transistor 160, the charge applied to the gate electrode of the transistor 160 is held. will be held (retained).

[0065] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long period of time.

[0066] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the transistor electrode, the second wiring has a different potential. If the transistor 160 is an n-channel type, a high level is applied to the gate electrode of the transistor 160. Apparent threshold V for a given charge th_H The gate of transistor 160 The apparent threshold voltage V when a low-level charge is applied to the th_L Lower Here, the apparent threshold voltage is the voltage at which the transistor 160 is turned on. Therefore, the potential of the fifth wiring is defined as the potential of the fifth wiring required to make the fifth wiring V rank th_H and V th_L By setting the potential V0 to the intermediate potential V0, the The charge applied to the gate electrode can be determined. For example, in writing, If a charge is applied, the potential of the fifth wire is V0 (> V th_H ) Then, The transistor 160 is in the "on state." If a low level charge is applied, The potential of the fifth wire is V0( <V th_L ), the transistor 160 remains in the "off state" Therefore, by checking the potential of the second wiring, the stored information can be read. It can be put out.

[0067] When memory cells are arranged in an array, only the information of a desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and To prevent the information in other memory cells from being read, a transistor is placed between each memory cell. 60 are connected in parallel, the first memory cell that is not the object of reading For the wiring of 5, the transistor 160 is in the "off state" regardless of the state of the gate electrode. That is, V th_H A smaller potential can be applied to each memory cell. When the transistors 160 are connected in series between the inputs, the For the fifth wiring of the memory cell that does not have a gate electrode, the transistor 1 The potential at which 60 is in the "on state," that is, V th_L The larger potential is applied to the fifth wire. should be given to

[0068] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the fourth wiring is held in the same manner as when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned off. By turning off the transistor 162, the gate voltage of the transistor 160 is The poles are now given a charge related to the new information.

[0069] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and makes it possible to suppress a decrease in operation speed caused by the erase operation. That is, high speed operation of the semiconductor device is achieved.

[0070] The source electrode or drain electrode of the transistor 162 is connected to the gate of the transistor 160. The flow cell is electrically connected to a gate electrode, and is used as a non-volatile memory element. This has the same effect as the floating gate of a floating gate type transistor. In the figure, the source electrode or drain electrode of the transistor 162 and the gate of the transistor 160 The portion to which the gate electrode is electrically connected is sometimes called the floating gate portion FG. When the transistor 162 is off, the floating gate portion FG is embedded in an insulator. It can be seen that the floating gate portion FG holds electric charge. The off-state current of the transistor 162 using 1 / 10 ... It is possible to ignore the loss of charge stored in the FG part. The transistor 162 can provide a nonvolatile memory device.

[0071] For example, if the off-state current density of transistor 162 at room temperature is 10 zA (1 zeptoampere A) is 1 x 10 -21 A) and the capacitance of the capacitance element 164 is about 1 pF. There are at least 10 6 It is possible to hold data for more than 10 seconds. It goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0072] In this case, the gate problem pointed out in the conventional floating gate type transistor is There is no problem of deterioration of the gate insulating film (tunnel insulating film). This solves the problem of deterioration of the gate insulating film when electrons are injected into the floating gate. This means that there is no theoretical limit to the number of times you can write to a file. In addition, the conventional floating gate transistor requires The high voltage that was previously required is no longer necessary.

[0073] The semiconductor device shown in FIG. 5(A-1) includes elements such as transistors that constitute the semiconductor device. can be replaced with a circuit like that shown in Figure 5(A-2) assuming that includes resistance and capacitance. That is, in FIG. 5(A-2), the transistor 160 and the capacitor 164 are Each is considered to be composed of resistance and capacitance. R1 and C1 are the resistance and capacitance values ​​of the capacitive element 164, respectively, and the resistance value R1 is the capacitance value of the capacitive element 164. R2 and C2 correspond to the resistance of the insulating layer that constitutes 64. The resistance R2 is the resistance and capacitance of the transistor 160. The capacitance C2 corresponds to the resistance due to the gate insulation layer in the gate insulator state. This corresponds to the capacitance formed between the gate electrode and the source electrode or the drain electrode. , the resistance value R2 is the resistance value between the gate electrode and the channel forming region of the transistor 160. For illustrative purposes only, some of the connections are shown as dotted lines to make this point clear.

[0074] The resistance between the source and drain electrodes of the transistor 162 when it is in the off state (actual R1 and R2 are R1 ≧ ROS (R1 is less than ROS). When R2≧ROS (R2 is equal to or greater than ROS), the charge retention period (information retention period) is The hold-up time (which can also be referred to as the hold-up time) is determined primarily by the off-state current of transistor 162. It will be possible.

[0075] On the other hand, if the above relationship is not satisfied, the off-state current of the transistor 162 is not sufficiently small. However, it is difficult to ensure a sufficient retention period. This is because the leakage current is large. It is desirable that the above relationship be satisfied.

[0076] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1≧C2 (C1 is equal to or greater than C2). By increasing C1, the potential of the floating gate FG is controlled by the fifth wiring. When the fifth wiring is connected to the fifth wiring (for example, when reading), the fluctuation of the potential of the fifth wiring can be suppressed to a low level. This is why.

[0077] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are controlled by the gate insulation layers of transistors 160 and 162. The same applies to C1 and C2. Therefore, the material and thickness of the gate insulating layer It is desirable to appropriately set the above-mentioned relationship.

[0078] The semiconductor device shown in FIG. 5B does not include the transistor 160 in FIG. In the semiconductor device shown in FIG. Line (also called the first signal line) and the source electrode or drain electrode of the transistor 162 The second line (also called the second signal line) is electrically connected to the first line. The gate electrode of the transistor 162 is electrically connected to the The other of the source electrode or the drain electrode of the transistor 162 and one of the electrodes of the capacitor element 164 , and are electrically connected to a third wiring (also called a capacitance line) and a capacitance element 1 The other electrode of 64 is electrically connected.

[0079] Here, the above-described transistor including an oxide semiconductor is used as the transistor 162. The above-described transistor using an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 162 is turned off, It is possible to hold a given potential for an extremely long period of time. The transistor 162 using a conductor has a channel length (L) of 10 nm or more and 1000 nm or less. Therefore, it has the features of low power consumption and extremely high operating speed.

[0080] The semiconductor device shown in FIG. 5B has a feature that a potential applied to the capacitor 164 can be held. By utilizing this characteristic, it is possible to write, retain, and read information as follows.

[0081] First, we will explain how to write and store information. For simplicity, we will use the third arrangement. The potential of the second wiring is fixed. This sets the potential at which the first transistor 162 is turned on, thereby turning on the first The potential of the wiring is applied to one of the electrodes of the capacitor 164. A predetermined charge is applied to the second wiring (write). By setting the potential at which the transistor 162 is turned off, the transistor 162 is turned off. The charge applied to the capacitor 164 is held (retained). As shown, the off-state current is extremely small, so that charge can be retained for a long period of time.

[0082] Next, the reading of information will be described. In this state, when the potential of the second wiring is set to a potential at which the transistor 162 is turned on, The first wiring has a different potential depending on the amount of charge held in the capacitor 164. By monitoring the potential of the first wiring, the stored data can be read out.

[0083] When information is read, the charge in the capacitance element 164 is lost, so that the charge cannot be written again. It is important to note that the following will be carried out:

[0084] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the second wiring is held when the transistor 162 is turned on. This causes the transistor 162 to be turned on. (a potential related to new data) is applied to one electrode of the capacitor 164. The potential of the wiring is set to a potential at which the transistor 162 is turned off, By turning off the capacitor 164, the capacitor 164 is in a state where a charge related to new information is provided. It becomes a state of mind.

[0085] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information, which allows the semiconductor device to operate at high speed.

[0086] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of positive hole-causing transistors instead of n-type transistors. It goes without saying that a p-type transistor can be used as the carrier.

[0087] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0088] (Embodiment 2) In this embodiment, a method for manufacturing a semiconductor device using an oxide semiconductor will be described. A method for manufacturing the transistor 162 in the main part will be described with reference to FIG. Since the manufacturing process of the transistor 162 is described as an example, A detailed description of the transistor 170 and the like present under 62 will be omitted.

[0089] First, an insulating layer 138 is formed on the interlayer insulating layer 128. Then, a conductive layer is formed on the insulating layer 138. The conductive layer is selectively etched to form a source electrode or a drain electrode 142a. Then, a source or drain electrode 142b is formed (see FIG. 6(A)).

[0090] The insulating layer 138 functions as a base and is formed by using a PVD method, a CVD method, or the like. The insulating layer 138 can be made of silicon oxide, silicon oxynitride, or silicon nitride. The material used is an inorganic insulating material such as hafnium oxide, aluminum oxide, or tantalum oxide. The insulating layer 138 is preferably formed so as to contain as little hydrogen or water as possible. It is also possible to employ a structure in which the insulating layer 138 is not provided.

[0091] The conductive layer is formed by using PVD methods such as sputtering and CVD methods such as plasma CVD. The conductive layer can be formed of a material such as aluminum, chromium, copper, Tantalum, titanium, molybdenum, tungsten, or any of the above elements. Manganese, magnesium, zirconium, beryllium, etc. can be used. Alternatively, any one of these materials or a combination of two or more of these materials may be used. Titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Alternatively, a material containing a combination of two or more of these elements may be used.

[0092] The conductive layer may have a single layer structure or a laminated structure of two or more layers. A single layer structure of a titanium nitride film or titanium film, a single layer structure of an aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, the conductive layer has a tapered shape. A source electrode or drain electrode 142a and a source electrode or drain electrode 142 It has the advantage of being easy to process into b.

[0093] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium zinc oxide alloy (In2O3-ZnO), or a combination of these metal oxide materials It is possible to use one containing silicon or silicon oxide.

[0094] The etching of the conductive layer is performed so that the source or drain electrodes 142a and It is preferable to perform this step so that the end of the source or drain electrode 142b has a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The ends of the source or drain electrodes 142a and 142b are The gate insulating layer 14 to be formed later is etched to have a tapered shape. The taper angle is the angle at which the taper A layer having a shape (for example, a source electrode or a drain electrode 142a) is The inclination angle between the side and bottom of the layer when observed from a direction perpendicular to the surface of the layer. Shows.

[0095] The channel length (L) of the transistor is defined as the distance between the bottom end of the source or drain electrode 142a and the , and the distance between the lower end of the source electrode or drain electrode 142b. The mask shape used for forming transistors with a channel length (L) of less than 25 nm is When performing exposure of the composition, extreme ultraviolet rays with a wavelength of several nm to several tens of nm are used. It is preferable to use ultraviolet light for the mask formation. The exposure has high resolution and a large depth of focus. It is also possible to set the channel length (L) to 10 nm or more and 1000 nm (1 μm) or less. It is possible to increase the operating speed of the circuit. It is also possible to reduce

[0096] In addition, the source electrode or drain electrode 142a and the source electrode or drain electrode 1 An insulating layer may be formed on 42b. By providing the insulating layer, the later formed A gate electrode, a source electrode or a drain electrode 142a, and a source electrode or a drain electrode It is possible to reduce the parasitic capacitance between the drain electrode 142b.

[0097] Next, the source or drain electrode 142a and the source or drain electrode 1 An oxide semiconductor layer 144 is formed so as to cover 42b (see FIG. 6B).

[0098] The oxide semiconductor layer 144 is made of a quaternary metal oxide such as In-Sn-Ga-Zn-O or a ternary The In-Ga-Zn-O system, In-Sn-Zn-O system, In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. , Zn-Mg-O, Sn-Mg-O, In-Mg-O, and single-component metal oxides. The material can be formed using oxide semiconductors such as In-O, Sn-O, and Zn-O. .

[0099] Among them, In-Ga-Zn-O oxide semiconductor materials have a sufficiently high resistance in the absence of an electric field. Since it is possible to sufficiently reduce the field current and the field effect mobility is high, It is suitable as a semiconductor material for use in devices.

[0100] A representative example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0, m is not necessarily a natural number). Also, M is used instead of Ga. Using InMO3(ZnO) m (m>0, m is not necessarily a natural number) Here, M is gallium (Ga), aluminum (Al), Selected from iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. It represents one or more metallic elements. For example, M is Ga, Ga, and Al. , Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. The above composition is derived from the crystal structure and is merely an example. It should be noted that this is merely

[0101] The oxide semiconductor layer 144 is formed by sputtering with a target of In:Ga: The composition formula is Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less). For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] In addition, a target having a composition ratio of In2O3:Ga2O 3:ZnO=1:1:1 [molar ratio] and In2O3:G A target with a composition ratio of a2O3:ZnO=1:1:4 [molar ratio] and In2O A target having a composition ratio of 3:ZnO=1:2 [molar ratio] can also be used.

[0102] In this embodiment, the oxide semiconductor layer 144 having an amorphous structure is made of In-Ga-Zn-O based metal. The layer is formed by sputtering using a metal oxide target.

[0103] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more. More preferably, the relative density is 99.9% or more. A metal oxide target with a high relative density is used. This makes it possible to form the oxide semiconductor layer 144 with a dense structure.

[0104] The oxide semiconductor layer 144 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration is reduced to 10 ppb or less. It is.

[0105] When the oxide semiconductor layer 144 is formed, for example, a processing object is placed in a processing chamber kept in a reduced pressure state. The object is held in a container, and the temperature of the object is kept at 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 40°C. The object to be treated is heated to 0° C. or lower. The temperature of the object to be treated may be room temperature. Then, while removing moisture from the treatment chamber, hydrogen, water, etc. A sputtering gas from which the oxide semiconductor layer 144 is removed is introduced, and the oxide semiconductor layer 144 is formed using the above target. The oxide semiconductor layer 144 is formed while the object to be processed is heated. It is possible to reduce impurities contained in the conductor layer 144. In addition, damage caused by sputtering is reduced. To remove moisture from inside the processing chamber, an adsorption type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. A turbo pump with a cold trap can also be used. Hydrogen and water can be removed from the processing chamber by evacuating using a cryopump or the like. Since the impurities can be removed, the impurity concentration in the oxide semiconductor layer 144 can be reduced.

[0106] The conditions for forming the oxide semiconductor layer 144 include, for example, the distance between the processing object and the target. The diameter was 170 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the atmosphere was oxygen (oxygen Air (flow ratio 100%) atmosphere, or argon (flow ratio 100%) atmosphere, or For the pulsed direct heating, a mixed atmosphere of oxygen and argon can be used. When a DC power supply is used, the powdery substances (also called particles or dust) formed during film formation can be removed. The thickness of the oxide semiconductor layer 144 is preferably 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less, more preferably 1 nm or less By using the oxide semiconductor layer 144 having such a thickness, miniaturization is possible. However, the short channel effect associated with the oxide semiconductor material can be suppressed. The appropriate thickness varies depending on the material and application of the semiconductor device. The method can be selected according to the purpose.

[0107] Before the oxide semiconductor layer 144 is formed by a sputtering method, argon gas is introduced. Then, a reverse sputtering process is performed to generate plasma, and the surface to be formed (for example, the surface of the interlayer insulating layer 128) is In this case, the reverse sputtering is preferably performed by removing the deposits of the above-mentioned. Instead of bombarding the sputtering target with ions, the treatment surface is bombarded with ions. This is a method of modifying the surface by bombarding the surface with ions. The method is to apply a high-frequency voltage to the surface to be treated in an argon atmosphere, and In addition, nitrogen, helium, or An atmosphere such as oxygen may be used.

[0108] After that, the oxide semiconductor layer 144 is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (including water and a hydroxyl group) from the oxide semiconductor layer 144. ) is removed, the structure of the oxide semiconductor layer is adjusted, and the defect level in the energy gap is reduced. The temperature of the first heat treatment can be, for example, 300° C. or more and less than 550° C., or 40 The temperature must be between 0℃ and 500℃.

[0109] The heat treatment is carried out, for example, by placing the workpiece in an electric furnace using a resistance heating element, and heating the workpiece in a nitrogen atmosphere. The heat treatment can be performed under conditions of 450° C. and 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the air. Do not allow leakage or contamination with water or hydrogen.

[0110] The heat treatment device is not limited to an electric furnace, and may be heat conducted from a medium such as a heated gas or heat radiation. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment ) equipment can be used. The LRTA equipment uses halogen lamps, metal halide lamps, etc. , xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a light bulb. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas used is argon. Inert gases such as rare gases or nitrogen that do not react with the workpiece during heat treatment are used. Used.

[0111] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and left for several minutes. After the heating, the workpiece may be taken out of the inert gas atmosphere and subjected to GRTA treatment. GRTA processing allows high-temperature heat treatment in a short time. The present invention can be applied even under temperature conditions exceeding 100°C. During the treatment, inert gas is used instead of oxygen. By performing the first heat treatment in an atmosphere containing oxygen, This is because it is possible to reduce defect levels in the energy gap caused by oxygen deficiency. .

[0112] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing 1,2-dichloroethane (CO), which is the main component, and does not contain water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into heat treatment equipment Purity should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0113] In either case, the first heat treatment reduces impurities and produces an i-type (intrinsic semiconductor) or i-type By forming the oxide semiconductor layer 144 that is close to the It is possible to realize the above.

[0114] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. The heat treatment can also be called a dehydration treatment or a dehydrogenation treatment. The dehydrogenation treatment is performed after the formation of an oxide semiconductor layer, after the formation of a gate insulating layer, or after the formation of a gate electrode. It is also possible to carry out the dehydration treatment at a timing such as after the dehydration treatment. The hydrogenation treatment may be carried out not only once but also multiple times.

[0115] Next, the gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144 (see FIG. 6C). The gate insulating layer 146 can be formed by using a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (Hf SixOy(x>0, y>0)), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0)), nitrogen doped hafnium aluminate (H fAl x O y N z (x>0, y>0, z>0) The gate insulating layer 146 may have a single layer structure or a stacked layer structure. The thickness is not particularly limited, but when miniaturizing a semiconductor device, the operation of the transistor For example, when silicon oxide is used, the thickness is 1n. The thickness m can be set to 100 nm or more, and preferably 10 nm or more and 50 nm or less.

[0116] As described above, when the gate insulating layer 146 is thinned, the gate resistance due to the tunnel effect and the like is reduced. To solve the gate leakage problem, the gate insulating layer 146 is provided with an oxide halide. Funium, Tantalum Oxide, Yttrium Oxide, Hafnium Silicate (HfSixOy( x>0, y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x >0, y>0, z>0), nitrogen doped hafnium aluminate (HfAl x O y N z (x>0, y>0, z>0)) By using a high-k material for the gate insulating layer 146, the electrical characteristics are maintained while It is possible to increase the film thickness to suppress gate leakage. A film including a material, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, It may have a laminated structure with a film containing any of aluminum oxide and the like.

[0117] After the gate insulating layer 146 is formed, a second thermal annealing is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0 and 350°C. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. In addition, when the gate insulating layer 146 contains oxygen, the oxide semiconductor layer 144 By supplying oxygen to the oxide semiconductor layer 144, oxygen vacancies in the oxide semiconductor layer 144 are compensated for, so that the oxide semiconductor layer 144 becomes an i-type (intrinsic semiconductor) or Alternatively, an oxide semiconductor layer that is as close to i-type as possible can be formed.

[0118] In this embodiment, the second heat treatment is performed after the gate insulating layer 146 is formed. The timing of the second heat treatment is not particularly limited. For example, the second heat treatment may be performed after the formation of the gate electrode. Alternatively, a second heat treatment may be performed after the first heat treatment. The first heat treatment may be combined with the second heat treatment, or the second heat treatment may be combined with the first heat treatment. It's okay to let them sleep.

[0119] Next, a gate electrode is formed on the gate insulating layer 146 in a region overlapping with the oxide semiconductor layer 144. The gate electrode 148a is formed on the gate insulating layer 146. The conductive layer is then selectively etched to form the insulating layer. The conductive layer that becomes the gate electrode 148a can be formed by a PVD method such as a sputtering method. The source electrode can be formed by using a CVD method such as a plasma CVD method. The same applies to the drain electrode 142a and the like, and the descriptions therefor can be taken into consideration. In forming the gate electrode 148a, the electrode 14 of the capacitance element 164 in the previous embodiment is 8b can be formed together.

[0120] Next, an interlayer insulating layer 150 and an interlayer insulating film 152 are formed on the gate insulating layer 146 and the gate electrode 148a. An insulating layer 152 is formed (see FIG. 6(E)). The can be formed by using a PVD method, a CVD method, etc. Also, silicon oxide, oxynitride, etc. Inorganic materials such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The insulating film can be formed using a material containing an insulating material. However, one embodiment of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. It is also possible to adopt a configuration in which no.

[0121] It is preferable that the interlayer insulating layer 152 is formed so that its surface is flat. By forming the interlayer insulating layer 152 so as to have a flat surface, when the semiconductor device is miniaturized, Even in such a case, electrodes, wiring, and the like can be suitably formed on the interlayer insulating layer 152. The interlayer insulating layer 152 is planarized by a method such as CMP (chemical mechanical polishing). This can be done using the method.

[0122] Through the above steps, the transistor 162 including the purified oxide semiconductor layer 144 is completed. (See FIG. 6(E)).

[0123] The transistor 162 illustrated in FIG. 6E includes an oxide semiconductor layer 144 and an oxide semiconductor layer 14 4, a source electrode or drain electrode 142a electrically connected to the source electrode or drain The source electrode 142b, the oxide semiconductor layer 144, the source or drain electrode 142a, A gate insulating layer 146 covers the source or drain electrode 142b. The gate electrode 148a on the upper side, the gate insulating layer 146 and the interlayer insulating layer on the gate electrode 148a A layer 150 and an interlayer insulating layer 152 on the interlayer insulating layer 150 .

[0124] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below The carrier density of the oxide semiconductor layer 144 is 100 nm, which is lower than that of a typical silicon wafer. The carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., 1 ×10 12 / cm 3 less than 1.45×10 10 / cm 3 (Less than) As a result, the off-state current of the transistor 162 is sufficiently small. The off-current density (off-current divided by the transistor channel width) at to 100zA / μm (1zA (zeptoampere) is 1×10 -21 A) or so.

[0125] By using the oxide semiconductor layer 144 which has been highly purified and made intrinsic, The off-state current of the transistor can be sufficiently reduced. This makes it possible to obtain a semiconductor device capable of retaining stored data for an extremely long period of time.

[0126] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0127] (Embodiment 3) In this embodiment, a transistor using an oxide semiconductor (particularly, an oxide semiconductor having an amorphous structure) is A method for manufacturing the transistor will be described with reference to FIG. This can be used in place of the transistor 162 in the embodiment. The transistor according to the embodiment has a part of the configuration in common with the transistor according to the previous embodiment. Therefore, the following mainly describes the differences. The following explanation will be given using a top-gate transistor as an example. This is not limited to the T type.

[0128] First, an insulating layer 202 is formed on a processing object 200. Then, an oxide semiconductor is formed on the insulating layer 202. A conductor layer 206 is formed (see FIG. 7(A)).

[0129] The workpiece 200 is, for example, the interlayer insulating layer 128 in the previous embodiment. It is preferable that the surface of 200 has an arithmetic mean roughness (Ra) of 1 nm or less. As semiconductor devices become more miniaturized, the masks used for patterning The requirements for exposure conditions are increasing, but by making the surface highly flat, the requirements for exposure conditions can be met. This is because it is easy to respond even when the requirements are high. For example, an area of ​​10 μm × 10 μm can be measured.

[0130] The insulating layer 202 corresponds to the insulating layer 138 in the previous embodiment, and functions as a base. For details, the above embodiment can be referred to. It is also possible.

[0131] The oxide semiconductor layer 206 corresponds to the oxide semiconductor layer 144 in the above embodiment. For materials, manufacturing methods, and other details that can be used, the above embodiments can be referred to. do.

[0132] In this embodiment, the oxide semiconductor layer 206 having an amorphous structure is formed using an In-Ga-Zn-O based metal oxide. It is formed by a sputtering method using a metal oxide target.

[0133] Next, the oxide semiconductor layer 206 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 206a is formed.

[0134] The oxide semiconductor layer 206 can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions are adjusted according to the material so that the layer can be etched into the desired shape. The etching gas, etching solution, etching time, temperature, etc. are set appropriately.

[0135] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), Carbon (CCl4, etc.). Also, gases that contain fluorine (fluorine-based gases, such as tetrafluoride Carbon (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane ( CHF3), hydrogen bromide (HBr), oxygen (O2), and helium (He ), or a gas containing a rare gas such as argon (Ar), etc. may also be used.

[0136] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A method of etching a silicon wafer using a plasma-coupled plasma (PPS) can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the workpiece side) The amount of electric power to be used, the electrode temperature on the workpiece side, etc. are set appropriately.

[0137] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. This is also fine.

[0138] The end portion of the oxide semiconductor layer 206a is preferably etched to have a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. The taper angle is a value obtained by forming a layer having a tapered shape (for example, the oxide semiconductor layer 206a) at a temperature of 1000.degree. When observed from a direction perpendicular to the cross section (a plane perpendicular to the surface of the workpiece), The inclination angle between the bottom surface and the oxide semiconductor layer 206a is shown. By etching, the source electrode or drain electrode 208a, which will be formed later, The coverage of the source electrode or drain electrode 208b is improved, and step disconnection can be prevented. .

[0139] After that, the oxide semiconductor layer 206a is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (water or a hydroxyl group) from the oxide semiconductor layer 206a. The structure of the oxide semiconductor layer is adjusted to reduce the defect level in the energy gap. For details, the above embodiment can be referred to. In addition, when the heat treatment (first heat treatment) is performed after etching, wet etching is used. Even if the etching rate is high, etching can be performed at a high rate. This has the advantage of shortening the time required for etching.

[0140] Note that the first heat treatment is performed on the oxide semiconductor layer 2 before it is processed into the island-shaped oxide semiconductor layer 206a. In that case, the workpiece 20 is removed from the heating device after the first heat treatment. 0 and undergoes a photolithography process.

[0141] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. The heat treatment may also be called a dehydration treatment, a dehydrogenation treatment, or the like. The hydrogenation treatment may be performed after the formation of the oxide semiconductor layer or after a source electrode or a After the drain electrode is laminated, after the gate insulating layer is formed, etc. In addition, such dehydration and dehydrogenation treatments can be carried out not only once but multiple times. You may go several times.

[0142] Next, a conductive layer is formed in contact with the oxide semiconductor layer 206a. By selectively etching the source or drain electrode 208a, the source or drain A conductive layer, a source electrode, or a drain electrode is formed (see FIG. 7(B)). The electrode 208a, the source electrode or the drain electrode 208b, and other details are the same as those described above. The description of the conductive layer, source electrode, drain electrode, etc. in the embodiment can be taken into consideration. .

[0143] Next, a gate insulating layer 212 is formed in contact with a part of the oxide semiconductor layer 206a (FIG. 7(C) For details of the gate insulating layer 212, see the gate insulating layer 212 in the previous embodiment. Please refer to the descriptions regarding the above.

[0144] After the gate insulating layer 212 is formed, a second thermal annealing is performed in an inert gas atmosphere or an oxygen atmosphere. For details of the second heat treatment, the above embodiment can be referred to. .

[0145] In this embodiment, the second heat treatment is performed after the gate insulating layer 212 is formed. The timing of the second heat treatment is not particularly limited. For example, the second heat treatment may be performed after the formation of the gate electrode. Heat treatment 2 may be performed.

[0146] Next, a gate electrode was formed on the gate insulating layer 212 in a region overlapping with the oxide semiconductor layer 206a. The gate electrode 214 is formed on the gate insulating layer 212 (see FIG. 7(D)). After forming a conductive layer, the conductive layer is selectively patterned to form the insulating film. For details, the above-described embodiment may be referred to. At this time, the electrodes of the capacitor element in the above embodiment can also be formed.

[0147] Next, an interlayer insulating layer 216 and an interlayer insulating film 217 are formed on the gate insulating layer 212 and the gate electrode 214. An edge layer 218 is formed (see FIG. 7(E)). For details, the above embodiment may be referred to. It is also possible to adopt a structure in which no interlayer insulating layer is provided.

[0148] As described above, a transistor using the purified amorphous oxide semiconductor layer 206a was obtained. Depending on the conditions of the heat treatment, the oxide semiconductor layer 250 may be formed. There may be a small amount of crystalline components present in 206a.

[0149] By using the oxide semiconductor layer 206a which has been highly purified and made intrinsic, The off-state current of the transistor can be sufficiently reduced. This makes it possible to obtain a semiconductor device capable of retaining memory contents for an extremely long period of time. .

[0150] In this embodiment, a top-gate transistor is used. In the above description, the lower part of the drain electrode and the upper part of the oxide semiconductor layer are in contact with each other. The transistors to which the configuration of the embodiment can be applied are not limited to this. For example, A transistor of the type having a source electrode and a drain electrode and an oxide semiconductor layer A part of the configuration of this embodiment is applied to a configuration in which the upper part contacts the lower part (such as the configuration shown in FIG. 2 or FIG. 4). Also, a bottom gate type transistor can be used. The bottom of the drain electrode is in contact with the top of the oxide semiconductor layer. A transistor having an upper portion of a source electrode and a drain electrode, and a lower portion of an oxide semiconductor layer. A part of the configuration of this embodiment can be applied to a configuration in which the That is, various transistors including an oxide semiconductor having an amorphous structure can be realized according to this embodiment. can be realized

[0151] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0152] (Embodiment 4) In this embodiment, a method for manufacturing a transistor using an oxide semiconductor will be described with reference to FIGS. In this embodiment, a first oxide semiconductor layer having a crystalline region is used as the oxide semiconductor layer. a second oxide semiconductor layer formed by crystal growth from a crystalline region of the first oxide semiconductor layer; The transistor in question is the same as that in the previous embodiment. This can be used in place of the transistor 162. Such a transistor has a part of its configuration in common with the transistor according to the previous embodiment. For this reason, the following will mainly discuss the differences.

[0153] In addition, when the necessary thickness can be ensured by the first oxide semiconductor layer alone, the second oxide semiconductor layer In the following, a top-gate type transistor will be used as an example. However, the transistor structure is not limited to the top gate type.

[0154] First, an insulating layer 302 is formed on the processing object 300. Then, a first forming an oxide semiconductor layer, and performing a first heat treatment to at least a surface of the first oxide semiconductor layer; The region containing the oxide semiconductor layer is crystallized to form the first oxide semiconductor layer 304 (see FIG. 8A). .

[0155] For details of the processing target 300 (such as details of the surface), the above embodiment can be referred to.

[0156] The insulating layer 302 functions as a base. The details of the insulating layer 302 are also described in the previous embodiment. Note that a structure in which the insulating layer 302 is not provided may be used.

[0157] The first oxide semiconductor layer is formed in a manner similar to that of the oxide semiconductor layer in the above embodiment. For this reason, the first oxide semiconductor layer and the method for forming the first oxide semiconductor layer will be described in detail below. However, in this embodiment, the first heat treatment is performed to form a first In order to intentionally crystallize the oxide semiconductor layer, an oxide semiconductor that is easily crystallized is used. It is preferable to form a first oxide semiconductor layer. For example, ZnO can be mentioned. In-Ga-Zn-O oxide semiconductors are also known. For example, a high concentration of Zn tends to crystallize, while a high concentration of metal elements (In, Ga, and Z) In n), the proportion of Zn in the alloy is 60 atom % or more, and it is not desirable to use the alloy for this purpose. The thickness of the first oxide semiconductor layer is preferably greater than or equal to 1 nm and less than or equal to 10 nm. In this embodiment, the thickness is set to 3 nm as an example. The appropriate thickness varies depending on the material and the application of the semiconductor device, so the thickness should be determined according to the material and the application of the semiconductor device. The selection may be made according to the application.

[0158] The temperature of the first heat treatment is 550° C. or higher and 850° C. or lower, preferably 600° C. or higher and 750° C. or lower. The heat treatment time should be between 1 minute and 24 hours. The temperature and time of the heat treatment vary depending on the type of oxide semiconductor, etc.

[0159] Moreover, it is preferable that the atmosphere for the first heat treatment does not contain hydrogen, water, or the like. For example, nitrogen, oxygen, and rare gases (helium, neon, argon, etc.) with sufficient water removal. It can be an atmosphere.

[0160] Heat treatment equipment includes electric furnaces, as well as equipment that uses heat conduction from a medium such as heated gas or heat radiation. For example, a Lamp Radiation Atomic Energy Transmitter (LRTA) can be used to heat the object to be treated. Rapid Thermal Anneal (GRTA) equipment, Gas Rapid Thermal Anneal (GRTA) equipment RTA (Rapid Thermal Anneal) equipment l) Equipment can be used. LRTA equipment includes halogen lamps, metal halide lamps, etc. xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp It is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as benzene or nitrogen. is used.

[0161] By the above-mentioned first heat treatment, at least a region including a surface of the first oxide semiconductor layer is crystallized. The crystalline region extends from the surface of the first oxide semiconductor layer to the inside of the first oxide semiconductor layer. The crystal growth proceeds toward the crystal region. The crystal region may contain plate-like crystals with an average thickness of 1 nm to 10 nm. In some cases, the oxide semiconductor layer may include crystals whose c-axes are oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer. Here, "approximately parallel" refers to a state within ±10° from the parallel direction, and "approximately perpendicular" refers to a state within ±10° from the parallel direction. This refers to a state within ±10° of the direction.

[0162] In addition, the first heat treatment forms a crystalline region and removes hydrogen from the first oxide semiconductor layer. It is desirable to remove hydrogen and other substances (including water and hydroxyl groups). Nitrogen and oxygen with a purity of 6N (99.9999%) or more (i.e. impurity concentration of 1ppm or less) The first heat treatment is preferably performed in a nitrogen or rare gas (helium, neon, argon, etc.) atmosphere. More preferably, the purity is 7N (99.99999%) or more (i.e., the concentration of impurities is 0.1 ppm or less). In addition, it is preferable to use ultra-dry air with H2O of 20 ppm or less. Alternatively, the first heat treatment may be performed in ultra-dry air with an H2O concentration of 1 ppm or less.

[0163] In addition, the first heat treatment is performed to form a crystalline region and to supply oxygen to the first oxide semiconductor layer. For example, by performing the heat treatment in an oxygen atmosphere, the first oxide Oxygen can be supplied to the semiconductor layer.

[0164] In this embodiment, the first heat treatment is performed in a nitrogen atmosphere at 700° C. for 1 hour. After removing hydrogen and the like from the oxide semiconductor layer, the atmosphere is switched to an oxygen atmosphere, The first heat treatment is performed to supply oxygen to the inside of the oxide semiconductor layer. Since the structure is the same, it is possible to carry out separate processes for the purpose of removing hydrogen and supplying oxygen. For example, after heat treatment to remove hydrogen, etc., or treatment to supply oxygen, In this case, it is possible to carry out a heat treatment for crystallization.

[0165] By such a first heat treatment, a crystalline region is formed and hydrogen (including water and hydroxyl groups) is removed. Thus, a first oxide semiconductor layer to which oxygen is supplied is obtained.

[0166] Next, a first oxide semiconductor layer 304 having a crystalline region at least in a region including a surface thereof is formed with A second oxide semiconductor layer 305 is formed (see FIG. 8B). If the necessary thickness can be ensured by the layer 304 alone, the second oxide semiconductor layer 305 is not necessary. In this case, the step of forming the second oxide semiconductor layer 305 can be omitted.

[0167] The second oxide semiconductor layer 305 is formed in a manner similar to that of the oxide semiconductor layer in the above embodiment. Therefore, the second oxide semiconductor layer 305 and a method for forming the second oxide semiconductor layer 305 will be described in detail below. For details, the above embodiment can be referred to. Note that the second oxide semiconductor layer 305 is It is preferable that the first oxide semiconductor layer 303 is formed thicker than the first oxide semiconductor layer 304. The sum of the thicknesses of the layer 304 and the second oxide semiconductor layer 305 is 1 nm or more and 50 nm or less, preferably The second oxide semiconductor layer 305 can be formed to a thickness of 1 nm to 10 nm. In this embodiment, the thickness is set to 7 nm as an example. The appropriate thickness varies depending on the conductor material and the application of the semiconductor device. The material may be selected depending on the material and the application.

[0168] The second oxide semiconductor layer 305 is made of a material having the same main component as the first oxide semiconductor layer 304. Therefore, it is desirable to use materials with close lattice constants after crystallization (mismatch of 1% or less). When such a material is used, the second oxide semiconductor layer 305 is crystallized. Therefore, crystal growth using the crystalline region of the first oxide semiconductor layer 304 as a seed can be easily promoted. Furthermore, when the main components are the same, the interface properties and electrical characteristics are also improved.

[0169] In addition, if the desired film quality can be obtained by crystallization, a second film may be formed using a material with a different main component. Alternatively, the oxide semiconductor layer 305 may be formed in the same manner as above.

[0170] Next, the second oxide semiconductor layer 305 is subjected to a second heat treatment, and the first oxide semiconductor layer 304 The crystalline region is used as a seed for crystal growth to form a second oxide semiconductor layer 306 (FIG. 8( When the second oxide semiconductor layer 305 is not formed, this step can be omitted. can.

[0171] The temperature of the second heat treatment is 550° C. or higher and 850° C. or lower, preferably 600° C. or higher and 750° C. or lower. The heating time of the second heat treatment is from 1 minute to 100 hours, preferably from 5 hours to 100 hours. The heat treatment time is set to 20 hours or less, typically 10 hours. It is preferable that the atmosphere during the process does not contain hydrogen, water, etc.

[0172] The details of the atmosphere and the effects of the heat treatment are the same as those of the first heat treatment. The heat treatment apparatus that can perform this is the same as that for the first heat treatment. By sometimes placing the inside of the furnace in a nitrogen atmosphere and sometimes placing the inside of the furnace in an oxygen atmosphere during cooling, Hydrogen and the like can be removed in the atmosphere, and oxygen can be supplied in the oxygen atmosphere.

[0173] By performing the above-described second heat treatment, the oxide semiconductor layer 304 is formed. The crystal growth is caused to proceed from the crystalline region to the entire second oxide semiconductor layer 305, so that the second oxide semiconductor A conductor layer 306 can be formed. In addition, hydrogen (including water and hydroxyl groups) and the like are removed. In addition, the second oxide semiconductor layer 306 to which oxygen is supplied can be formed. The heat treatment can also improve the orientation of the crystalline region of the first oxide semiconductor layer 304. be.

[0174] For example, an In-Ga-Zn-O-based oxide semiconductor material is used for the second oxide semiconductor layer 306. In this case, the second oxide semiconductor layer 306 is InGaO3(ZnO). m (m: What is a natural number? (not limited to) and In2Ga2ZnO7 (In:Ga:Zn:O=2:2: Such crystals may include crystals having a crystallinity of 1:7 [atom ratio]. According to the theory, the c-axis of the second oxide semiconductor layer 306 is aligned in a direction substantially perpendicular to the surface of the second oxide semiconductor layer 306. is oriented in the direction.

[0175] Here, the above-mentioned crystal has a-axis and b-axis parallel lattices. Each layer contains either In, Ga, or Zn. Specifically, the above crystal has a layer containing In and a layer not containing In (Ga or a layer containing Zn) are stacked in the c-axis direction.

[0176] In the case of In-Ga-Zn-O oxide semiconductor crystals, the in-plane direction of the layer containing In, In other words, the electrical conductivity in the directions parallel to the a-axis and b-axis is good. In a-Zn-O oxide semiconductor crystals, electrical conduction is mainly controlled by In. The 5s orbital of one In atom overlaps with the 5s orbital of the adjacent In atom, resulting in a carrier This is due to the formation of apas, etc.

[0177] In addition, the first oxide semiconductor layer 304 may have an amorphous region at the interface with the insulating layer 302. In the case of the structure, the second heat treatment is performed to form a thin film on the surface of the first oxide semiconductor layer 304. Crystal growth proceeds from the crystalline region toward the bottom of the first oxide semiconductor layer 304. In some cases, the amorphous region may be crystallized. Depending on the processing conditions, the amorphous regions may remain.

[0178] In addition, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are made of oxides having the same main component. In the case of using an oxide semiconductor material, as shown in FIG. 8C, a first oxide semiconductor layer 304 and The second oxide semiconductor layer 306 may have the same crystal structure as the first oxide semiconductor layer 304. As indicated by the dotted line in FIG. 1C, the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 The boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 becomes indistinguishable. can sometimes be considered as the same layer.

[0179] Next, the first oxide semiconductor layer 304 and the The second oxide semiconductor layer 306 is processed to form the island-shaped first oxide semiconductor layer 304a and the island-shaped second oxide semiconductor layer 304b. A second oxide semiconductor layer 306a is formed (see FIG. 8D). After the treatment, processing into an island-shaped oxide semiconductor layer is performed. After processing, a second heat treatment may be performed. In this case, if wet etching is used, Even if the etching rate is high, the etching can be performed without any problems. This has the advantage of reducing the time required for testing.

[0180] The etching of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 is performed using a drive motor. Either dry etching or wet etching may be used. In order to etch the oxide semiconductor layer into a desired shape, Etching conditions (etching gas, etching solution, etching time, temperature, etc.) are adjusted according to the material. The thickness of the first oxide semiconductor layer 304 and the thickness of the second oxide semiconductor layer 306 are appropriately set. The etching can be performed in a manner similar to that of the oxide semiconductor layer in the above embodiment. For details, please refer to the above embodiment.

[0181] Note that a region to be a channel formation region in the oxide semiconductor layer has a flat surface. For example, the surface height (PV) of the second oxide semiconductor layer 306 is preferably In the region overlapping with the electrode (channel forming region), the thickness is 1 nm or less (preferably 0.5 nm or less). In addition, the height difference is preferably, for example, 10 μm×10 μm. It can be measured in areas.

[0182] Next, a conductive layer is formed so as to be in contact with the second oxide semiconductor layer 306a. The conductive layer is selectively etched to form the source or drain electrode 308a, For details, refer to the previous embodiment. Just take into consideration the form.

[0183] Note that in the step shown in FIG. 8D, the first oxide semiconductor layer 304a or the second oxide semiconductor The source or drain electrode 308a of the semiconductor layer 306a, The crystal layer in contact with the electrode 308b may become amorphous. Not all regions of the oxide semiconductor layer 304a and the second oxide semiconductor layer 306a are crystalline. .

[0184] Next, a gate insulating layer 312 is formed in contact with a part of the second oxide semiconductor layer 306a. The above embodiment may be referred to for details. A gate electrode is formed in a region overlapping the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a. Then, a layer is formed on the gate insulating layer 312 and the gate electrode 314. An interlayer insulating layer 316 and an interlayer insulating layer 318 are formed (see FIG. 8(E)). Please refer to the previous embodiment.

[0185] After the gate insulating layer 312 is formed, a third heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the third heat treatment is preferably 200° C. or more and 450° C. or less. For example, in an oxygen-containing atmosphere at 250°C for 1 hour, By performing the third heat treatment, the electrical characteristics of the transistor are improved. In addition, when the gate insulating layer 312 is an insulating layer containing oxygen, In this case, oxygen can be supplied to the second oxide semiconductor layer 306a.

[0186] In this embodiment, the third heat treatment is performed after the gate insulating layer 312 is formed. The timing of the third heat treatment is not limited to this. In addition, the timing of the third heat treatment may be different from that of the second heat treatment. Therefore, when oxygen is supplied to the second oxide semiconductor layer 306a, the third heat treatment is omitted. It may be omitted.

[0187] In this manner, the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a were formed. The used transistor 350 is completed (see FIG. 8(E)).

[0188] The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are thus highly purified and intrinsic. By using the compound semiconductor layer 306a, the off-state current of the transistor can be sufficiently reduced. By using such transistors, it is possible to maintain memory contents for a very long period of time. Thus, a semiconductor device capable of being held is obtained.

[0189] In this embodiment, a top-gate transistor is used. In the above description, the lower part of the drain electrode and the upper part of the oxide semiconductor layer are in contact with each other. The transistors to which the configuration of the embodiment can be applied are not limited to this. For example, A transistor of the type having a source electrode and a drain electrode and an oxide semiconductor layer A part of the configuration of this embodiment is applied to a configuration in which the upper part contacts the lower part (such as the configuration shown in FIG. 2 or FIG. 4). Also, a bottom gate type transistor can be used. The bottom of the drain electrode is in contact with the top of the oxide semiconductor layer. A transistor having an upper portion of a source electrode and a drain electrode, and a lower portion of an oxide semiconductor layer. A part of the configuration of this embodiment can be applied to a configuration in which the That is, according to this embodiment, various transistors including an oxide semiconductor layer having a crystalline region can be fabricated. This can be realized

[0190] Further, in this embodiment, a first oxide semiconductor having a crystalline region is used as the oxide semiconductor layer. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are crystal-grown from the crystalline region of the first oxide semiconductor layer 304a. The use of the oxide semiconductor layer 306a improves the field effect mobility and provides good electrical characteristics. For example, a transistor having a field effect mobility μ>100 cm can be realized. 2 / V s. This allows various logic circuits that require high-speed operation to be The above transistor can also be applied to the above.

[0191] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0192] (Embodiment 5) In this embodiment, a method for manufacturing a transistor using an oxide semiconductor will be described with reference to FIGS. The transistor in question is a substitute for the transistor 162 in the previous embodiment. The transistor according to the present embodiment can be used in various ways. The configuration is the same as that of the transistor according to the previous embodiment. In the following, we will use a top-gate transistor as an example. As will be explained, the structure of the transistor is not limited to the top gate type.

[0193] First, an insulating layer 402 is formed on a processing object 400. Then, an oxide film is formed on the insulating layer 402. A semiconductor layer 406 is formed (see FIG. 9A). For details, refer to the above embodiment. That's good.

[0194] Next, the oxide semiconductor layer 406 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 406a is formed, and a conductive layer is formed so as to cover the oxide semiconductor layer 406a. The conductive layer 408 and the insulating layer 410 are formed (see FIG. 9(B)). Although it is not a necessary component, it is preferable to selectively attach the side of the source electrode or drain electrode to be formed later. In addition, it is effective to oxidize the gate electrode and the source or drain electrode. This is also effective in reducing the capacitance between the

[0195] For details of the formation of the island-shaped oxide semiconductor layer 406a, the heat treatment, and the like, see the above embodiment. The above embodiment can be referred to for details of the conductive layer 408. That's good.

[0196] The insulating layer 410 can be formed by using a CVD method, a sputtering method, or the like. The insulating layer 410 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or oxide. It is preferable that the insulating layer 4 contains hafnium oxide, tantalum oxide, or the like. The insulating layer 410 may have a single-layer structure or a multi-layer structure. Although not limited thereto, it can be, for example, 10 nm or more and 200 nm or less.

[0197] The conductive layer 408 and the insulating layer 410 are then selectively etched to form source or drain electrodes. A source or drain electrode 408a, a source or drain electrode 408b, an insulating layer 410a, an insulating layer 410b is formed (see FIG. 9(C)). The process for forming the drain electrode is the same as that for forming the aluminum, titanium, molybdenum, Materials such as copper are suitable for the subsequent plasma oxidation process and are used as source or drain electrodes. The material is suitable for the source electrode 408a, the source electrode, or the drain electrode 408b.

[0198] Next, oxidation treatment is performed to supply oxygen to the oxide semiconductor layer 406a (see FIG. 9D). By the oxidation treatment, a part of the source electrode or drain electrode 408a (particularly, The oxidized region 411a is located on the side of the source electrode or drain electrode 408b. An oxidized region 411b is formed in a part of the substrate 411 (particularly, the part corresponding to the side surface) (FIG. 9(D) )). In addition, the source electrode or drain electrode 408a and the An oxidized region is also formed on the outer periphery of the source or drain electrode 408b.

[0199] The oxidation process uses oxygen plasma excited by microwaves (300MHz to 300GHz). It is preferable to use an oxidation treatment using microwaves (plasma oxidation treatment). By exciting the plasma, a high-density plasma is realized, which prevents damage to the oxide semiconductor layer 406a. This is because the page size can be sufficiently reduced.

[0200] More specifically, for example, the frequency is set to 300 MHz to 300 GHz (typically 2.45 GHz). Hz), pressure is 50 Pa to 5000 Pa (typically 500 Pa), and the temperature of the workpiece is 2 The temperature is set to 00 to 400°C (typically 300°C), and the above-mentioned Processing can be performed.

[0201] By the above oxidation treatment, oxygen is supplied to the oxide semiconductor layer 406a; It is possible to sufficiently reduce damage to the oxide semiconductor layer 406a while suppressing energy loss caused by oxygen deficiency. In other words, the defect states in the oxide semiconductor layer 406a can be reduced. The characteristics can be further improved.

[0202] Note that the oxide semiconductor layer 406 can be formed by the above-mentioned method while sufficiently reducing damage to the oxide semiconductor layer 406a. If there is a method that can supply oxygen to a, it can be used for plasma oxidation treatment using microwaves. For example, a method such as heat treatment in an atmosphere containing oxygen can be used. do.

[0203] In addition to the oxidation treatment, a treatment for removing water, hydrogen, and the like from the oxide semiconductor layer 406a may be performed. In this case, for example, a plasma treatment using a gas such as nitrogen or argon may be performed. It can be used.

[0204] The oxidized regions 411a and 411b formed by the above oxidation treatment are When transistors 450 are miniaturized (e.g., when the channel length is less than 1000 nm), As transistors become smaller, the gate insulating layer is becoming increasingly The thickness of the gate insulating layer is required to be small, but the presence of the oxide region makes it possible to reduce the thickness of the gate insulating layer. The gate electrode and the source electrode or the drain electrode may be separated due to patterning or poor coverage. This is because it is possible to prevent shorting of the gate electrodes. A thickness of about 10 nm or more is sufficient to be effective.

[0205] The oxidation treatment is also effective in improving the film quality of the exposed insulating layer 402 .

[0206] In addition, the source electrode or drain electrode 408a and the source electrode or drain electrode 408 The insulating layer 410a and the insulating layer 410b have the same function as each other in preventing oxidation of the upper part of the insulating layer 410a and the upper part of the insulating layer 410b. In order to carry out the above plasma treatment while leaving the mask used in the etching process, This is because it involves great difficulties.

[0207] Next, the gate insulating layer 406a was removed from the oxide semiconductor layer 406b without exposing it to the air. Then, a gate insulating layer 412 is formed so as to overlap with the oxide semiconductor layer 406a over the gate insulating layer 412. A gate electrode 414 is formed in the region, and a layer is formed on the gate insulating layer 412 and the gate electrode 414. An interlayer insulating layer 416 and an interlayer insulating layer 418 are formed (see FIG. 9(E)). , the above embodiments can be referred to.

[0208] Through the above steps, the transistor 450 including an oxide semiconductor is completed.

[0209] In this embodiment, in order to supply oxygen to the oxide semiconductor layer 406a, 06a is subjected to oxygen plasma treatment. This improves the characteristics of the transistor 450. In addition, the region corresponding to the side of the source electrode or drain electrode is oxidized. Therefore, the gate electrode- It is possible to prevent a short circuit between the source electrode (or the drain electrode). 11a, the oxide region 411b creates a moderate offset region, so that the oxide semiconductor The change in the electric field from the layer to the interface with the source electrode (or drain electrode) is kept low. It is also possible.

[0210] In addition, by providing an insulating layer on the source electrode and the drain electrode, The capacitance (parasitic capacitance) formed between the drain electrode and the gate electrode is reduced, and It is possible to achieve high speed operation.

[0211] In this embodiment, a top-gate transistor is used. In the above description, the lower part of the drain electrode and the upper part of the oxide semiconductor layer are in contact with each other. The transistors to which the configuration of the embodiment can be applied are not limited to this. For example, A transistor of the type having a source electrode and a drain electrode and an oxide semiconductor layer A part of the configuration of this embodiment can be applied to the configuration in which the upper portion is in contact with the lower portion. According to this embodiment, a semiconductor device including an oxide semiconductor to which oxygen is supplied and an electrode having an oxidized region is provided. It is possible to realize a variety of transistors including

[0212] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0213] (Embodiment 6) In this embodiment, a manufacturing method of a semiconductor device using a semiconductor material other than an oxide semiconductor, specifically Specifically, a method for manufacturing the transistor 170 in the lower part of FIG. 2A will be described with reference to FIGS. Explain using (A).

[0214] First, a substrate 100 containing a semiconductor material is prepared (see FIG. 10(A)). The substrate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. The substrates can be used for semiconductor devices such as silicon germanium, compound semiconductor substrates, and SOI substrates. In this embodiment, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. In general, an "SOI substrate" is a substrate that has silicon on an insulating surface. In this specification, the term refers to a substrate having a layer other than silicon on an insulating surface. The term "S" also includes a substrate having a semiconductor layer made of the material. The semiconductor layer of the SOI substrate is not limited to a silicon layer. This includes a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. It shall be so.

[0215] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 10A.) The protective layer 102 is made of, for example, silicon oxide or silicon nitride. For example, an insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity are, for example, phosphorus or arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. For example, nium, gallium, etc. can be used.

[0216] Next, etching is performed using the protective layer 102 as a mask, and the This removes a portion of the substrate 100 from the exposed area. A semiconductor region 104 separated from the region is formed (see FIG. 10(B)). For this purpose, it is preferable to use dry etching, but wet etching may also be used. The etching gas and etching solution should be selected appropriately depending on the material to be etched. can be done.

[0217] Next, an insulating layer is formed so as to cover the semiconductor region 104, and a region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 10(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. Methods for removing the insulating layer include polishing such as CMP and etching. Either of them may be used. After the semiconductor region 104 is formed or after the element isolation insulation After the layer 106 is formed, the protective layer 102 is removed.

[0218] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0219] The insulating layer will later become the gate insulating layer and is obtained using a method such as CVD or sputtering. Silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, etc. tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0 , y>0), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAl x O y N z ( It is preferable to use a single layer structure or a laminate structure of a film including x>0, y>0, z>0). The surface of the semiconductor region 104 is oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment, for example, using He, Ar, Uses a mixture of rare gases such as Kr and Xe, oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen. The thickness of the insulating layer is preferably, for example, 1 nm or more and 100 nm or less. Preferably, the thickness is 10 nm or more and 50 nm or less.

[0220] The layer containing a conductive material is a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, a semiconductor material such as polycrystalline silicon can be used to form the conductive layer. A layer containing the material may be formed. The method of forming the layer is not particularly limited, and may be a deposition method, a CVD method, a sputtering method, or the like. Various film formation methods such as a deposition method, a deposition method, a spin coating method, etc. can be used. In this embodiment, an example in which a layer containing a conductive material is formed using a metal material is shown. Let us assume that.

[0221] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, a gate electrode 110 is formed (see FIG. 10(C)).

[0222] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 10(C)). By doping the semiconductor region 104 with phosphorus (P) or arsenic (As), an impurity region with a shallow junction depth is formed. In this case, an n-type transistor is formed. To achieve this, phosphorus or arsenic is added, but to form a p-type transistor, boron (B) is added. Impurities such as fluorine (Al) or aluminum (Al) may be added to the impurity region 114. As a result, a channel formation region 116 is formed below the gate insulating layer 108 in the semiconductor region 104. (See FIG. 10(C)). Here, the concentration of the added impurity can be appropriately set. However, when semiconductor elements are highly miniaturized, it is desirable to increase the concentration. In addition, a process of forming the impurity region 114 after forming the insulating layer 112 is adopted here. However, the insulating layer 112 may be formed after the impurity regions 114 are formed.

[0223] Next, the sidewall insulating layer 118 is formed (see FIG. 10(D)). The edge layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying anisotropic By performing a high-precision etching process, the structure can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 11 It is preferable to expose the top surface of the semiconductor device 4. The sidewall insulating layer 118 is preferably formed for the purpose of high integration. In some cases, it may not be formed due to the target.

[0224] Next, a semiconductor device is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. Then, an insulating layer is formed on the impurity region 114. Then, phosphorus (P) or arsenic ( As) or the like is added to form a high-concentration impurity region 120 (see FIG. 10(E)). Thereafter, the insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, and the high concentration impurities are removed. A metal layer 122 is formed so as to cover the object region 120 and the like (see FIG. 10(E)). 122 is formed by various deposition methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can be formed by reacting with the semiconductor material that constitutes the semiconductor region 104. It is preferable to form the insulating layer using a metal material that becomes a metal compound with low resistance when the insulating layer is formed. Examples of such metal materials include titanium, tantalum, tungsten, nickel, and copper. Examples include baltic and platinum.

[0225] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 10(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 11 A metal compound region is also formed in the portion of the first insulating film 110 that comes into contact with the metal layer 122.

[0226] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in the region, and the conductivity is sufficiently increased. This sufficiently reduces the electrical resistance and improves the device characteristics. After forming region 124, metal layer 122 is removed.

[0227] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as niobium. It is also possible to form the layer using an organic insulating material such as acrylic resin. The insulating layer 126 and the insulating layer 128 are stacked in a stacked structure. The interlayer insulating layer is not limited to the above. It may be a single layer or a laminated structure of three or more layers. After the formation of 128, the surface is planarized by CMP or etching. It is desirable.

[0228] Thereafter, openings are formed in the interlayer insulating layers 126 and 128, reaching the metal compound region 124. A source electrode or drain electrode 130a and a source electrode or drain electrode 130b are formed in the opening. The electrode 130b is formed (see FIG. 10(H)). The source electrode or drain electrode 130a The source electrode or drain electrode 130b is formed by, for example, PVD or CV in the area including the opening. After forming a conductive layer using the D method, etc., etching and CMP are used to It can be formed by removing a part of the conductive layer.

[0229] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as a natural oxide film) on the formation surface is reduced, and the lower electrode (here, the metal compound region 124 ) and the titanium nitride film formed thereafter has the function of reducing the contact resistance with the It has a barrier function that suppresses the diffusion of conductive materials. In addition, titanium and titanium nitride are used After the barrier film is formed, a copper film may be formed by plating.

[0230] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface of the electrode is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. The necessary tungsten film, titanium film, titanium nitride film, etc. are removed, and the flatness of the surface is improved. In this way, the source electrode or drain electrode 130a, By planarizing the surface including the source or drain electrode 130b, This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0231] In this case, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the source electrode 130a or the drain electrode 130b is shown, in this process, An electrode in contact with the source electrode 110 may also be formed. The drain electrode 130a can be used as a source electrode or a drain electrode 130b. There is no particular limitation on the material, and various conductive materials can be used. For example, molybdenum Titanium, Chromium, Tantalum, Tungsten, Aluminum, Copper, Neodymium, Scandium In addition, in consideration of the heat treatment to be performed later, a conductive material such as silicon can be used. The source or drain electrode 130a and the source or drain electrode 130b are subjected to a heat treatment. It is preferable to form the plate using a material having sufficient heat resistance to withstand such a temperature.

[0232] In this manner, a transistor 170 is formed using the substrate 100 containing a semiconductor material (see FIG. The transistor 170 using a material other than an oxide semiconductor can operate at high speed. Since this is possible, a logic circuit (also called an arithmetic circuit) can be constructed using the transistor. In addition, a driver circuit for driving the memory circuit described in the above embodiment can be used. It can also be used for.

[0233] After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. By adopting a multilayer wiring structure having a laminated structure of an interlayer insulating layer and a conductive layer, A highly integrated semiconductor device can be provided.

[0234] For example, after the above process, an insulating layer 138 may be formed and an opening may be formed in the insulating layer 138. Further, the opening is provided with an electrode 142c connected to the source electrode or drain electrode 130a, and An electrode 142d connected to the source electrode or drain electrode 130b may be formed. (See Figure 2(A)).

[0235] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0236] (Embodiment 7) In this embodiment, a manufacturing method of a semiconductor device using a semiconductor material other than an oxide semiconductor, specifically Specifically, a method for manufacturing the transistor 570 in the lower part of FIG. 2B will be described with reference to FIGS. First, a single crystal semiconductor layer is provided on a base substrate. A method for producing an OI substrate will be described with reference to FIG. 11. Then, A method for manufacturing a transistor will be described with reference to FIGS.

[0237] <Method of manufacturing SOI substrate> First, a base substrate 500 is prepared (see FIG. 11A). A substrate made of an insulating material can be used. Specifically, aluminosilicate glass, aluminum Various glass materials used in the electronics industry, such as barium borosilicate glass and niobium borosilicate glass Examples of the substrate include a glass substrate, a quartz substrate, a ceramic substrate, and a sapphire substrate. The ceramic substrate is made of silicon and aluminum oxide, and has a thermal expansion coefficient close to that of silicon. This is also fine.

[0238] The base substrate 500 may be a semiconductor substrate such as a single crystal silicon substrate or a single crystal germanium substrate. When a semiconductor substrate is used as the base substrate 500, a glass substrate is used. The upper limit of the heat treatment temperature is higher than when using a substrate, so it is possible to obtain a high-quality SOI substrate. Here, the semiconductor substrate is solar cell grade silicon (SOG-Si A polycrystalline silicon (Solar Grade Silicon) substrate may also be used. A conductive substrate may be used. When using solar cell grade silicon or polycrystalline semiconductor substrate, In comparison with the case where a single crystal silicon substrate is used, the manufacturing cost can be reduced. do.

[0239] In this embodiment mode, a case where a glass substrate is used as the base substrate 500 will be described. By using a glass substrate, which is inexpensive and can be made large, as the base substrate 500, the cost can be reduced. It is possible to streamline the process.

[0240] It is preferable that the surface of the base substrate 500 be cleaned in advance. Specifically, a mixture of hydrochloric acid and hydrogen peroxide (HPM), sulfuric acid, and hydrogen peroxide is applied to the base substrate 500. Hydrogen peroxide mixed solution (SPM), ammonia hydrogen peroxide mixed solution (APM), dilute hydrofluoric acid (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. By carrying out such a cleaning process, the flatness of the surface of the base substrate 500 can be improved and the base This achieves the removal of abrasive particles remaining on the surface of the base substrate 500, etc.

[0241] Next, a nitrogen-containing layer 502 (e.g., a silicon nitride film (SiN x ) and silicon oxynitride film (SiN x O y ) (x>y) and other nitrogen-containing insulating films The nitrogen-containing layer 502 is formed by a CVD method, a sputtering method, or the like (see FIG. 11B). The method can be used to form the insulating layer.

[0242] The nitrogen-containing layer 502 formed in this embodiment is a layer to which a single crystal semiconductor layer is bonded later. The nitrogen-containing layer 502 is a layer (bonding layer) for bonding the nitrogen-containing layer 502 to the sodium contained in the base substrate. As a barrier layer to prevent impurities such as sodium from diffusing into the single crystal semiconductor layer. It works.

[0243] As described above, in this embodiment, the nitrogen-containing layer 502 is used as a bonding layer. It is preferable to form the nitrogen-containing layer 502 so that the surface of the substrate 501 has a predetermined flatness. The average surface roughness (Ra, also called the arithmetic mean roughness) is 0.5 nm or less, and the root mean square roughness ( Rms) is 0.60 nm or less, more preferably, the average surface roughness is 0.35 nm or less, The nitrogen-containing layer 502 is formed so that the average roughness is 0.45 nm or less. Surface roughness and root mean square roughness can be measured, for example, in an area of ​​10 μm × 10 μm. The range is from 10 nm to 200 nm, preferably from 50 nm to 100 nm. By improving the flatness of the surface as described above, it is possible to prevent poor bonding of the single crystal semiconductor layer. can be done.

[0244] Next, a bond substrate is prepared. Here, a single crystal semiconductor substrate 510 is used as the bond substrate. (See FIG. 11(C)). In this case, a single crystal substrate is used as the bond substrate. The crystallinity of the bond substrate does not need to be limited to single crystal.

[0245] The single crystal semiconductor substrate 510 may be, for example, a single crystal silicon substrate or a single crystal germanium-based A single crystal semiconductor substrate made of a group 14 element, such as a single crystal silicon germanium substrate, is used. In addition, by using a compound semiconductor substrate such as gallium arsenide or indium phosphide, Commercially available silicon substrates are 5 inch (125 mm) and 6 inch (125 mm) in diameter. (150mm), 8 inch diameter (200mm), 12 inch diameter (300mm), 1 inch diameter A typical example is a circular substrate having a size of 6 inches (400 mm). The shape of 10 is not limited to a circle, but may be, for example, a rectangle. The crystalline semiconductor substrate 510 is formed by a CZ (Czochralski) method or an FZ (Floating Zone) method. It can be prepared using

[0246] An oxide film 512 is formed on the surface of the single crystal semiconductor substrate 510 (see FIG. 11(D)). In order to remove contaminants, a mixed solution of hydrochloric acid and hydrogen peroxide (HPM) is used before the formation of the oxide film 512. ), Sulfuric acid hydrogen peroxide solution mixture (SPM), Ammonia hydrogen peroxide solution mixture (APM) , dilute hydrofluoric acid (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. It is preferable to clean the surface of the crystalline semiconductor substrate 510 in advance. It may be discharged and washed.

[0247] The oxide film 512 is, for example, a single layer of a silicon oxide film, a silicon oxynitride film, or the like, or a multilayer. The oxide film 512 can be formed by a method such as thermal oxidation, CVD, etc. In addition, when the oxide film 512 is formed by the CVD method, In order to achieve good bonding, tetraethoxysilane (abbreviation: TEOS, a chemical It is preferred to form the silicon oxide film using an organosilane such as Si(OC2H5)4). It is nice.

[0248] In this embodiment, a single crystal semiconductor substrate 510 is subjected to thermal oxidation treatment to form an oxide film 512 (Here, SiO x Thermal oxidation is performed by adding halogen to an oxidizing atmosphere. It is preferable to carry out the above steps.

[0249] For example, the single crystal semiconductor substrate 510 is subjected to a thermal oxidation process in an oxidizing atmosphere containing chlorine (Cl). By carrying out the above process, an oxide film 512 that is oxidized with chlorine can be formed. The oxide film 512 becomes a film containing chlorine atoms. Collects pure heavy metals (e.g. Fe, Cr, Ni, Mo, etc.) and forms metal chlorides By removing the etched portion to the outside, contamination of the single crystal semiconductor substrate 510 can be reduced. After bonding with the base substrate 500, impurities such as Na from the base substrate are fixed. Therefore, contamination of the single crystal semiconductor substrate 510 can be prevented.

[0250] The halogen atoms contained in the oxide film 512 are not limited to chlorine atoms. The surface of the single crystal semiconductor substrate 510 may be oxidized by fluorine. The method is to immerse the material in a HF solution and then perform thermal oxidation in an oxidizing atmosphere. One method is to add it to an oxidizing atmosphere and perform thermal oxidation treatment.

[0251] Next, ions are accelerated by an electric field and irradiated onto the single crystal semiconductor substrate 510. An embrittled region 514 in which the crystal structure is damaged is formed at a predetermined depth in a crystalline semiconductor substrate 510 (FIG. 1 1(E)).

[0252] The depth of the region where the embrittlement region 514 is formed depends on the kinetic energy, mass and charge of the ion, The embrittlement region 514 can be adjusted by adjusting the incidence angle of the ions. The ion is injected into the region at a depth approximately equal to the penetration depth. The thickness of the single crystal semiconductor layer separated from the single crystal semiconductor substrate 510 can be adjusted. For example, the thickness of the single crystal semiconductor layer is 10 nm or more and 500 nm or less, preferably 50 nm or more and 2 The average penetration depth may be adjusted to about 00 nm or less.

[0253] The ion irradiation process can be performed using an ion doping device or an ion implantation device. A typical example of an ion doping device is an ion doping device that uses plasma generated by exciting a process gas. There is a non-mass separation type apparatus in which all the ion species generated are irradiated onto the workpiece. The ion species in the plasma are irradiated onto the workpiece without being mass-separated. An ion implanter is a mass separation type device. In an ion implanter, the ion species in the plasma are The ions are mass-separated, and an ion species having a specific mass is irradiated onto the object to be processed.

[0254] In this embodiment mode, hydrogen is added to the single crystal semiconductor substrate 510 using an ion doping apparatus. A gas containing hydrogen is used as the source gas. For the H3 + It is better to increase the ratio of H + , H2 + , H3 + Total H3 for quantity + The ratio of is 50% or more (more preferably 80% or more). H3 + By increasing the ratio, the efficiency of ion irradiation can be improved.

[0255] The ions to be added are not limited to hydrogen, and ions such as helium ions may also be added. In addition, the type of ions to be added is not limited to one, and multiple types of ions may be added. For example, when hydrogen and helium are irradiated simultaneously using an ion doping device, separate The number of steps can be reduced compared to the case where irradiation is performed in a single step, and the single crystal semiconductor It is possible to suppress surface roughness of the layer.

[0256] When the embrittled region 514 is formed using an ion doping apparatus, heavy metals are also simultaneously However, the ions are irradiated through the oxide film 512 containing halogen atoms. By performing irradiation, contamination of the single crystal semiconductor substrate 510 with these heavy metals can be prevented. can.

[0257] Next, the base substrate 500 and the single crystal semiconductor substrate 510 are placed opposite to each other, and the nitrogen-containing layer 502 is The surface is then bonded to the oxide film 512. As a result, the base substrate 500 and the single crystal semiconductor substrate The plate 510 is attached to the substrate 510 (see FIG. 11(F)).

[0258] When bonding, 0. 001N / cm 2 More than 100N / cm 2 For example, 1N / cm 2 More than 20N / cm 2 It is recommended to apply the following pressure. By applying pressure, the bonding surfaces will come closer and become tightly attached. At the contacted portion, a bond is formed between the nitrogen-containing layer 502 and the oxide film 512, and the nitrogen-containing layer 502 and the oxide film 512 are bonded to each other. The spontaneous bonding of the two surfaces occurs over almost the entire surface. This bonding is caused by van der Waals forces and hydrogen The bond is functional and can be carried out at room temperature.

[0259] Before the single crystal semiconductor substrate 510 and the base substrate 500 are bonded to each other, It is preferable to perform a surface treatment on the surface of the single crystal semiconductor. This makes it possible to improve the bonding strength at the interface between the main substrate 510 and the base substrate 500.

[0260] Surface treatment can be wet treatment, dry treatment, or a combination of wet and dry treatment. Also, different wet treatments can be used in combination. Alternatively, different dry processes may be used in combination.

[0261] After the bonding, a heat treatment may be performed to increase the bonding strength. The treatment temperature is a temperature at which separation does not occur in the embrittled region 514 (for example, room temperature or higher, 400° C. The nitrogen-containing layer 502 and the oxide film 512 are heated in this temperature range. The above heat treatment may be performed in a heating furnace such as a diffusion furnace or a resistance heating furnace, or in a RTA (instantaneous thermal annealing) furnace. Thermal annealing, Rapid Thermal Anneal equipment, microwave heating equipment, etc. The above temperature conditions are merely examples and may be used in the present invention. This is not to be construed as limiting the present invention.

[0262] Next, heat treatment is performed to separate the single crystal semiconductor substrate 510 at the embrittlement region. A single crystal semiconductor layer 5 is formed on a base substrate 500 via a nitrogen-containing layer 502 and an oxide film 512. 16 (see FIG. 11(G)).

[0263] It is desirable that the heat treatment temperature during the above separation be as low as possible. This is because the lower the temperature at the time of the treatment, the more the surface roughness of the single crystal semiconductor layer 516 can be suppressed. For example, the heat treatment temperature during the separation may be 300° C. or higher and 600° C. or lower. A temperature between 400°C and 500°C is more effective.

[0264] After the single crystal semiconductor substrate 510 is separated, the single crystal semiconductor layer 516 is Heat treatment is performed at a temperature of 0° C. or higher to reduce the concentration of hydrogen remaining in the single crystal semiconductor layer 516. This may be allowed.

[0265] Next, the surface of the single crystal semiconductor layer 516 is irradiated with laser light to improve the flatness of the surface. A single crystal semiconductor layer 518 having improved thermal conductivity and reduced defects is formed. Instead of the irradiation treatment, a heat treatment may be performed.

[0266] In this embodiment, immediately after the heat treatment for separating the single crystal semiconductor layer 516, However, one embodiment of the disclosed invention should not be interpreted as being limited thereto. After the heat treatment for separating the single crystal semiconductor layer 516, an etching treatment is performed to separate the single crystal semiconductor layer 516. After removing the areas with many defects on the surface of the conductor layer 516, the laser light irradiation process may be performed. Then, the flatness of the surface of the single crystal semiconductor layer 516 is improved, and then laser light irradiation is performed. The etching process may be wet etching or dry etching. In the present embodiment, the laser light is irradiated as described above. After the irradiation, a thinning step may be performed to reduce the thickness of the single crystal semiconductor layer 516. The semiconductor layer 516 can be thinned by dry etching or wet etching, or Both may be used.

[0267] Through the above steps, an SOI substrate having a single crystal semiconductor layer 518 with good characteristics can be obtained. (See Figure 11(H)).

[0268] <Method of manufacturing a transistor> Next, a method for manufacturing a transistor 570 using the above-mentioned SOI substrate will be described with reference to FIG. and explain.

[0269] FIG. 12A is a cross-sectional view showing a part of an SOI substrate produced by the method shown in FIG.

[0270] First, the single crystal semiconductor layer 518 is processed into an island shape to form a semiconductor layer 520 (FIG. 12(B) )). Before and after this process, in order to control the threshold voltage of the transistor, In addition, impurities that give n-type conductivity or p-type conductivity are added to the semiconductor layer. In the case where the semiconductor is silicon, the impurity that gives n-type conductivity is, for example, For example, phosphorus or arsenic can be used. In addition, impurities that impart p-type conductivity include For example, boron, aluminum, gallium, etc. can be used.

[0271] Next, an insulating layer 522 is formed to cover the semiconductor layer 520 (see FIG. 12(C)). The edge layer 522 will later become a gate insulating layer. The material and the method for forming the insulating layer 522 are as follows: For details, please refer to the description of the gate insulating layer (such as the gate insulating layer 108) in the previous embodiment. It is possible.

[0272] Next, a conductive layer is formed on the insulating layer 522, and then the conductive layer is selectively etched to form a semiconductor A gate electrode 524 is formed above the semiconductor layer 520 (see FIG. 12(D)). The material and the method for forming No. 4 are the same as those of the gate electrode (gate electrode 110, etc.) according to the previous embodiment. Please refer to the description regarding this.

[0273] Next, the gate electrode 524 is used as a mask to introduce impurities that impart one conductivity type into the semiconductor layer 520. The impurity region 526 is formed by doping (see FIG. 12(E)). To form a p-type transistor, phosphorus (P) or arsenic (As) is added. When forming a capacitor, it is possible to dope it with impurities such as boron (B) or aluminum (Al). Here, the concentration of the added impurity can be set appropriately.

[0274] Next, a sidewall insulating layer 528 is formed on the side surface of the gate electrode 524. The insulating layer 528 is formed so as to cover the insulating layer 522 and the gate electrode 524. Then, the insulating layer is subjected to a highly anisotropic etching process to form a self-aligned structure. At this time, the insulating layer 522 may be partially etched to form the gate insulating layer 5 At the same time as forming 22a, the impurity region 526 may be exposed.

[0275] Next, the gate electrode 524 and the sidewall insulating layer 528 are used as a mask to form a first conductivity type. The impurity element to be added is added to the impurity region 526. The impurity element added is an impurity element of the same conductivity type as the impurity element added in the previous step. The impurity element is added to the semiconductor layer 520 at a concentration higher than that in the previous step. A pair of high concentration impurity regions 530, a pair of low concentration impurity regions 532, and a channel forming A high concentration impurity region 530 is formed in the source region 534 (see FIG. 12(G)). The gate electrode functions as a drain region.

[0276] When the semiconductor layer 520 is made of a material containing silicon, the source region and the drain region To further reduce the resistance of the region, a portion of the semiconductor layer 520 is silicided. Silicidation may be achieved by contacting a metal with a semiconductor layer and subjecting the metal to a heat treatment (e.g. This is done by reacting the silicon in the semiconductor layer with the metal using a method such as GRTA method, LRTA method, etc. For the silicide region, cobalt silicide or nickel silicide can be formed. When the semiconductor layer 520 is thin, the silicide reaction is allowed to proceed to the bottom of the semiconductor layer 520. Metal materials that can be used for silicidation include titanium, nickel, tantalum, and tantalum. ungsten, molybdenum, cobalt, zirconium, hafnium, tantalum, vanadium , neodymium, chromium, platinum, palladium, etc. Also, when exposed to laser light, This also allows the formation of a silicide region.

[0277] Next, an interlayer insulating layer 536 and an interlayer insulating layer 537 are formed to cover the respective components formed by the above-mentioned steps. The interlayer insulating layer 536 and the interlayer insulating layer 538 are formed by oxidation. Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as niobium. It is also possible to form the layer using an organic insulating material such as acrylic resin. The interlayer insulating layer 536 and the interlayer insulating layer 538 are stacked in the semiconductor device. The interlayer insulating layer is not limited to the above. It may be a single layer or a laminated structure of three or more layers. After the formation of 538, the surface is planarized by CMP or etching. It is desirable.

[0278] Next, openings are formed in the interlayer insulating layers 536 and 538, reaching the high concentration impurity region 530. A source electrode or drain electrode 540a is formed in the opening, and a source electrode or drain electrode A source electrode or drain electrode 540a is formed (see FIG. 12(H)). The material and manufacturing method of the source electrode or drain electrode 540b are Please refer to the description regarding the electrode 130a, the source electrode or the drain electrode 130b, etc. stomach.

[0279] Through the above steps, a transistor 570 using an SOI substrate is formed (see FIG. 12H). The transistor 570 using a material other than an oxide semiconductor can operate at high speed. A logic circuit (also called an arithmetic circuit) can be configured using the transistor. The semiconductor memory device can also be used for a driver circuit for driving the memory circuit described in the above embodiment. Cut.

[0280] After the above steps, electrodes, wiring, an insulating layer, etc. may be further formed. By adopting a multilayer wiring structure having a laminated structure of an interlayer insulating layer and a conductive layer, A highly integrated semiconductor device can be provided.

[0281] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0282] (Embodiment 8) In this embodiment, an application example of the semiconductor device shown in the previous embodiment will be described with reference to FIGS. 4 will be used to explain.

[0283] 13(A) and 13(B) are diagrams illustrating the semiconductor device (hereinafter, referred to as a memory cell) shown in FIG. FIG. 13(A) is a circuit diagram of a semiconductor device formed using a plurality of ) is a circuit diagram of a so-called NAND type semiconductor device in which memory cells 190 are connected in series. FIG. 13B shows a so-called NOR type semiconductor device in which memory cells 190 are connected in parallel. FIG. 2 is a circuit diagram of a conductor device.

[0284] The semiconductor device shown in FIG. 13A includes a source line SL, a bit line BL, a first signal line S1, and m The second signal line S2, m word lines WL, and a plurality of memory cells 190(1, 1) to 190 (m, 1) are arranged in a vertical array of m rows by 1 column. , a single source line SL and a single bit line BL are provided. By having n source lines SL and n bit lines BL, the memory cell array can be divided into m vertical lines (rows) by n horizontal lines (columns). ) memory cell array.

[0285] In each memory cell 190, the gate electrode of transistor 160 and the gate electrode of transistor 162 One of the source electrode and the drain electrode of the capacitor 164 is electrically connected to Also, the first signal line S1 and the source electrode or the drain electrode of the transistor 162 are connected to each other. The other of the gate electrodes is electrically connected to the second signal line S2 and the gate of the transistor 162. The electrode of the capacitor 164 is electrically connected to the word line WL. The other is electrically connected.

[0286] The source electrode of the transistor 160 in the memory cell 190 is connected to the adjacent memory cell The drain electrode of the transistor 160 in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 in the memory cell 190. The drain electrode of the transistor 160 is connected to the transistor of the adjacent memory cell 190. 160 is electrically connected to the source electrode of the memory cell 160. The drain of the transistor 160 of the memory cell 190 provided at one end of the The electrode is electrically connected to a bit line. The source electrode of the transistor 160 in the memory cell 190 at the other end is , and is electrically connected to the source line.

[0287] The semiconductor device shown in FIG. 13A performs writing and reading operations on a row-by-row basis. The write operation is performed as follows: A transistor is connected to the second signal line S2 of the row to be written. 162 is applied with a potential to be turned on, and the transistor 162 of the row to be written is turned on. As a result, the first signal line S1 is connected to the gate electrodes of the transistors 160 in the specified row. A potential of 0.01V is applied to the gate electrode, and a predetermined charge is applied to the gate electrode. Data can be written to the memory cells in a row.

[0288] The read operation is performed as follows: First, the word lines WL other than the row where the read is to be performed are In addition, the transistor 160 is turned on regardless of the charge on the gate electrode of the transistor 160. A potential is applied so that the transistors 160 in the rows other than the one being read out are turned on. Then, the gate electrode of the transistor 160 is connected to the word line WL of the row to be read. The charge applied to the transistor 160 selects the on or off state of the transistor 160. Then, a constant potential is applied to the source line SL, and a potential is applied to the bit line BL. A read circuit (not shown) connected to the source line SL is set to an operating state. Since the multiple transistors 160 between the LSB lines BL are in the on state except for the row to be read out, The conductance between the source line SL and the bit line BL is 60 of the row to be read. Depending on the charge on the bit electrode, the potential of the bit line BL read by the read circuit has different values. In this manner, data can be read from the memory cells of a specified row.

[0289] The semiconductor device shown in FIG. 13B includes n source lines SL, bit lines BL, and a first signal line S1, m second signal lines S2 and word lines WL, and a plurality of memory cells 190 (1, 1 )~190(m,n) are memos arranged in a matrix of m (rows) x n (columns). The gate electrode of each transistor 160 and the transistor 16 One of the source electrode or drain electrode of the second transistor and one of the electrodes of the capacitor 164 are electrically connected to each other. The source line SL and the source electrode of the transistor 160 are electrically connected to The bit line BL and the drain electrode of the transistor 160 are electrically connected to each other. In addition, the first signal line S1 and the source electrode or the drain electrode of the transistor 162 The other is electrically connected to the second signal line S2 and the gate electrode of the transistor 162. The word line WL and the other electrode of the capacitor element 164 are electrically connected to each other. are electrically connected.

[0290] The semiconductor device shown in FIG. 13B performs writing and reading operations on a row-by-row basis. The write operation is performed in the same manner as in the semiconductor device shown in FIG. The operation is as follows. First, a transistor is connected to the word line WL other than the row to be read. A potential at which the transistor 160 is turned off regardless of the charge on the gate electrode of the transistor 160. Then, the transistors 160 other than the row to be read are turned off. The word line WL of the row to be read is connected to the gate electrode of the transistor 160 by the charge. , a potential (read potential) that selects the on or off state of the transistor 160 Then, a constant potential is applied to the source line SL, and the read A read circuit (not shown) is set in an operating state. The inductance is determined by the state of transistor 160 of the row being read. That is, the readout is performed by the charge held by the gate electrode of the transistor 160 in the row to be read out. The potential of the bit line BL read by the read circuit is a different value. Data can be read from the memory cells.

[0291] Next, an example of a read circuit that can be used in the semiconductor device shown in FIG. 4 will be used to explain.

[0292] FIG. 14(A) shows a schematic diagram of a read circuit. The read circuit is made up of a transistor and a sensor. It has a differential amplifier circuit.

[0293] When reading, terminal A is connected to the bit line to which the memory cell to be read is connected. A bias potential Vbias is applied to the gate electrode of the transistor, and the potential at terminal A is The position is controlled.

[0294] The memory cell 190 exhibits different resistance values ​​depending on the data stored therein. When the transistor 160 of the selected memory cell 190 is in an on state, the memory cell 190 is in a low resistance state. When the transistor 160 of the selected memory cell 190 is in an off state, the memory cell 190 is in a high resistance state. .

[0295] When the memory cell is in the high-resistance state, the potential of terminal A becomes higher than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "1") corresponding to the potential of terminal A. On the other hand, when the memory ce ll is in the low-resistance state, the potential of terminal A becomes lower than the reference potential Vref, and the sense amplifier ci rcuit outputs a potential (data "0") corresponding to the potential of terminal A.

[0296] In this way, by using the read circuit, data can be read from the memory cell. Note that the read circuit of this embodiment is an example. Other known circuits may also be used. In addition, the read circuit may have a precharge circuit. Instead of the reference potential Vref, a reference bit line may be connected. Also, the read circuit may have a precharge circuit. It may be configured such that a reference bit line for reference is connected instead of the reference potential Vref.

[0297] FIG. 14(B) shows a differential sense amplifier, which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin( + ) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output.

[0298] FIG. 14(C) shows a latch-type sense amplifier, which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, the control signal Sp is set to High and the control signal Sn is set to Low to cut off the power supply potential (Vd d). Then, the potentials for comparison are applied to V1 and V2. After that, when the control signal S p is set to Low and the control signal Sn is set to High to supply the power supply potential (Vdd), the comparison is performed. If the input potentials V1in and V2in satisfy V1in > V2in, the output of V1 is Hi gh, and the output of V2 is Low. If V1in < V2in, the output of V1 is L ow, and the output of V2 is High. By utilizing such a relationship, the difference between V1in and V2in can be amplified.

[0299] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0300] (Embodiment 9) In this embodiment, an example of a semiconductor device using the transistors shown in the previous embodiment will be described with reference to FIG. 15.

[0301] FIG. 15(A) shows an example of a semiconductor device having a configuration corresponding to a so-called DRAM (Dynamic Random Access Memory). The memory cell array 620 shown in FIG. 15(A) has a configuration in which a plurality of memory cells 630 are arranged in a matrix. The memory cell array 620 has m first wirings and n second wirings. Note that the memory cell 630 corresponds to the semiconductor device shown in FIG. 5(B). In this embodiment, the first wiring in FIG. 5(B) is referred to as a bit line BL, and the second wiring is referred to as a word line WL.

[0302] The memory cell 630 is composed of a transistor 631 and a capacitor element 632. The gate electrode of the transistor 631 is connected to the first wiring (word line WL). Also, one of the source electrode or drain electrode of the transistor 631 is connected to the second wiring line BL) and the other of the source electrode or the drain electrode of the transistor 631. is connected to one of the electrodes of the capacitance element. The other electrode of the capacitance element is connected to the capacitance line CL The transistor 631 is connected to the transistor 632 and is applied with a constant potential. The transistor shown is applied.

[0303] The transistor described in the above embodiment has an extremely small off-state current. For this reason, the semiconductor device shown in FIG. 15(A) is recognized as a so-called DRAM. When the transistor is applied to a semiconductor memory device, a substantially non-volatile memory can be obtained.

[0304] Figure 15(B) shows a so-called SRAM (Static Random Access Memory). An example of a semiconductor device having a structure corresponding to the memory cell shown in FIG. The array 640 may be configured to have a plurality of memory cells 650 arranged in a matrix. In addition, the memory cell array 640 includes a first wiring (word line WL), a second wiring ( The pixel has a plurality of bit lines (BL) and a plurality of third wirings (inverted bit lines / BL).

[0305] The memory cell 650 includes a first transistor 651 to a sixth transistor 656. The first transistor 651 and the second transistor 652 serve as selection transistors. In addition, one of the third transistor 653 and the fourth transistor 654 The second transistor is a p-channel transistor (here, the fourth transistor 654). In other words, the third transistor 653 is a The transistor 653 and the fourth transistor 654 form a CMOS circuit. Similarly, a fifth transistor 655 and a sixth transistor 656 form a CMOS circuit is configured.

[0306] A first transistor 651, a second transistor 652, a fourth transistor 654, The sixth transistor 656 is an n-channel transistor, and in the above embodiment The third transistor 653 and the fifth transistor The transistor 655 is a p-channel transistor and is made of an oxide semiconductor or other The insulating film 10 can be formed using a material such as silicon.

[0307] The structures, methods, and the like described in this embodiment mode may be appropriately combined with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0308] (Embodiment 10) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 16. In this embodiment, Telephones, mobile phone devices, portable information terminals (including portable game consoles, audio playback devices, etc.) (including digital cameras, digital video cameras, etc.), electronic paper, televisions The above-mentioned semiconductor device is installed in an electronic device such as a television (also called a television or television receiver). This section explains the case where the device is applied.

[0309] FIG. 16A shows a notebook personal computer, which includes a housing 701, a housing 702, The display unit 703 and the keyboard 704 are included. The semiconductor device shown in the above embodiment is provided inside the semiconductor device. The device is capable of writing and reading information at high speed, storing data for a long period of time, and being Power consumption has been reduced sufficiently. This allows data to be written and read at high speed and for a long period of time. A notebook-type personal computer capable of storing data for a long period of time and with sufficiently low power consumption. A computer is realized.

[0310] FIG. 16B shows a personal digital assistant (PDA), and a main body 711 includes a display unit 713 and an external The terminal 715 and the operation button 714 are provided. The main body 711 includes a stylus 712 for operating the terminal. The semiconductor device shown in the above embodiment is It has high speed readout, long-term memory retention, and low power consumption. This allows for high speed writing and reading of information, long-term memory retention, and Furthermore, a portable information terminal with sufficiently reduced power consumption is realized.

[0311] FIG. 16C shows an electronic book 720 equipped with electronic paper. The electronic book 720 is made up of a housing 721 and a housing 72 The display device 720 is configured with two housings, namely, housing 721 and housing 723. The housing 721 and housing 723 each include a display unit 7 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737. The housing 7 is connected to the housing 7 via the shaft portion 737, and can be opened and closed around the shaft portion 737. 21 includes a power source 731, operation keys 733, a speaker 735, etc. At least one of the housings 723 is provided with the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can write and read data at high speed and can be used for a long period of time. It is possible to retain memory, and power consumption is sufficiently reduced. It is a type of memory that can store data for a long period of time and consumes a sufficiently low amount of power. A child book is realized.

[0312] FIG. 16D shows a mobile phone that is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 slide and unfold as shown in FIG. 16(D). It can be folded up and folded up, making it possible to make it compact and suitable for carrying. The housing 741 also includes a display panel 742, a speaker 743, a microphone 744, and an operation Key 745, pointing device 746, camera lens 747, external connection terminal 74 The housing 740 also includes a solar cell 749 for charging the mobile phone. , an external memory slot 750, etc. Also, the antenna is built into the housing 741. At least one of the housing 740 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. The semiconductor device described in the above embodiment is provided with a write / read device. It has high speed, long-term memory retention, and low power consumption. This allows for high speed writing and reading of information, long term storage, and low power consumption. Thus, a mobile phone in which noise is sufficiently reduced is realized.

[0313] FIG. 16E shows a digital camera, which includes a main body 761, a display unit 767, an eyepiece unit 763, and an operation unit. The device is made up of an operation switch 764, a display unit 765, a battery 766, etc. The semiconductor device shown in the above embodiment is provided in the semiconductor device 761. The semiconductor device can write and read information at high speed and retain data for a long period of time. Moreover, power consumption is sufficiently reduced. Therefore, writing and reading of information can be performed at high speed. This will realize a digital camera that can store data for a long period of time and consumes very little power. will be done.

[0314] FIG. 16F shows a television device 770, which includes a housing 771, a display unit 773, a stand, and the like. The television device 770 is operated by a switch provided in the housing 771. The housing 771 and the remote control 780 can be used. The semiconductor device described in the above embodiment is mounted on the device 780. The semiconductor device shown in FIG. 1 is capable of writing and reading information at high speed and storing data for a long period of time. Moreover, the power consumption is sufficiently reduced. Therefore, writing and reading of information is highly efficient. A television device capable of high speed, long-term memory retention, and sufficiently reduced power consumption is provided. It will be realized.

[0315] As described above, the electronic device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This makes it possible to realize electronic devices with reduced power consumption. EXAMPLES

[0316] The number of times that the semiconductor device according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will now be explained with reference to FIG.

[0317] The semiconductor device used in the investigation has a circuit configuration shown in FIG. In addition, an oxide semiconductor is used for the transistor corresponding to the transistor 162. The capacitance element corresponding to the capacitor 164 had a capacitance of 0.33 pF.

[0318] The investigation involves setting the initial memory window width and holding data and writing data a given number of times. This is done by comparing the memory window width after the repetition. To write data, 0 V or 5V to the wire corresponding to the fourth wire, and 0V or 5V to the wire corresponding to the fourth wire. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor Since the transistor corresponding to the transistor 162 is in the off state, the floating gate portion FG The applied potential is maintained. If the potential of the wiring corresponding to the fourth wiring is 5V, Since the transistor corresponding to the transistor 162 is in the on state, the wiring corresponding to the third wiring The line potential is applied to the floating gate portion FG.

[0319] The memory window width is one of the indicators that show the characteristics of a memory device. Between the states, the potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 The shift of the curve (Vcg-Id curve) showing the relationship between the drain current Id of the transistor The different memory states are 0V to the floating gate FG and (hereinafter referred to as the Low state) and 5V is applied to the floating gate FG. The memory window width is a given state (hereinafter referred to as the High state). This can be confirmed by sweeping the potential Vcg in the low and high states. In all cases, Vds=1V.

[0320] Figure 17 shows the initial memory window width and the 1×10 9 Notes after writing times The results of the investigation of the rewindow width are shown in Fig. 17. In Fig. 17, the solid line indicates the first write, and the broken line indicates the The line is 1×10 9 The left curve of both the solid and dashed lines indicates the H The curve on the right side shows the write operation in the light state, and the curve on the left side shows the write operation in the low state. The vertical axis indicates Vcg (V), and the vertical axis indicates Id (A). 9 Before writing After that, the potential Vcg was swept in the high and low states. You can see that the width has not changed. 1×10 9 Before and after the write operation, The fact that the window width does not change means that the characteristics of the semiconductor device do not change at least during this period. This indicates that.

[0321] As described above, the semiconductor device according to one embodiment of the disclosed invention can store and write data many times. The characteristics do not change even after repeated use. In other words, one embodiment of the disclosed invention provides extremely reliable It can be said that a highly efficient semiconductor device can be realized. [Explanation of symbols]

[0322] 10 Memory Cell Array 20 Column Decoder 30 Low Decoder 40 IO Controller 50 IO Buffers 60 Command Buffers 70 Address Buffer 80 Controller 100 Substrates 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer Insulation Layer 128 Interlayer Insulation Layer 130a source electrode or drain electrode 130b Source electrode or drain electrode 132 Insulating Layer 134 Insulating Layer 138 Insulating Layer 142a Source electrode or drain electrode 142b Source or drain electrode 142c electrode 142d electrode 143 Insulating Layer 144 Oxide semiconductor layer 146 Gate Insulation Layer 148a Gate electrode 148b Electrode 150 Interlayer insulation layer 152 Interlayer insulation layer 160 Transistors 162 Transistor 164 Capacitive element 170 Transistors 181 Memory Cell Array 190 memory cells 200 Processing object 202 Insulating layer 206 Oxide semiconductor layer 206a Oxide semiconductor layer 208a Source electrode or drain electrode 208b Source electrode or drain electrode 212 Gate insulating layer 214 Gate electrode 216 Interlayer Insulation Layer 218 Interlayer Insulation Layer 250 Transistors 300 Processing object 302 Insulating layer 304 First oxide semiconductor layer 304a First oxide semiconductor layer 305 Second oxide semiconductor layer 306 Second oxide semiconductor layer 306a Second oxide semiconductor layer 308a Source electrode or drain electrode 308b Source electrode or drain electrode 312 Gate insulation layer 314 Gate electrode 316 Interlayer Insulation Layer 318 Interlayer Insulation Layer 350 Transistors 400 Processing object 402 Insulating layer 406 Oxide semiconductor layer 406a Oxide semiconductor layer 408 Conductive Layer 408a Source electrode or drain electrode 408b Source or drain electrode 410 Insulating layer 410a Insulating layer 410b Insulating layer 411a Oxidized area 411b Oxidized region 412 Gate insulation layer 414 Gate electrode 416 Interlayer Insulation Layer 418 Interlayer Insulation Layer 450 Transistors 500 Base Board 502 Nitrogen-containing layer 510 Single crystal semiconductor substrate 512 Oxide film 514 Embrittlement area 516 Single crystal semiconductor layer 518 Single crystal semiconductor layer 520 Semiconductor layer 522 Insulating layer 522a Gate insulating layer 524 Gate electrode 526 Impurity region 528 Sidewall insulation layer 530 High concentration impurity region 532 Low concentration impurity region 534 Channel Formation Region 536 Interlayer Insulation Layer 538 Interlayer Insulation Layer 540a Source electrode or drain electrode 540b Source electrode or drain electrode 570 Transistor 620 Memory Cell Array 630 memory cells 631 Transistor 632 Capacitor 640 Memory Cell Array 650 memory cells 651 Transistor 652 Transistor 653 Transistor 654 Transistor 655 Transistor 656 Transistor 701 Case 702 Case 703 Display section 704 Keyboard 711 Main unit 712 Stylus 713 Display section 714 Operation button 715 External Interface 720 e-books 721 Case 723 Case 725 Display section 727 Display section 731 Power supply 733 Operation Key 735 Speaker 737 Shaft 740 Case 741 Case 742 Display Panel 743 Speakers 744 Microphone 745 Operation Key 746 Pointing Device 747 Camera Lenses 748 External connection terminal 749 Solar Cells 750 external memory slot 761 Main unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television Equipment 771 Case 773 Display section 775 Stand 780 Remote Controlled Device

Claims

1. a memory cell array having a plurality of memory cells arranged in a matrix; a first driver circuit electrically connected to the bit line; a second drive circuit electrically connected to the word line; Each of the plurality of memory cells includes a first transistor and a capacitance element; one of a source and a drain of the first transistor is electrically connected to the bit line; the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor; a gate electrode of the first transistor is electrically connected to the word line; the first transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer has crystals oriented such that a c-axis is perpendicular to a surface of the oxide semiconductor layer, the oxide semiconductor layer has a region in contact with an upper surface of the first insulating layer, a first conductive layer having a function as a gate electrode of the first transistor is provided above the oxide semiconductor layer with a second insulating layer having a function as a gate insulating layer interposed therebetween; a second conductive layer having a function as one of a source electrode and a drain electrode of the first transistor, the second conductive layer having a region in contact with a top surface of the first insulating layer and having a function as one electrode of the capacitor; a third conductive layer having a function as the other electrode of the capacitance element is provided above the second conductive layer via the second insulating layer and has the same material as the first conductive layer; a first transistor being turned on to apply a potential to one electrode of the capacitor, and then the first transistor being turned off to hold the charge applied to the capacitor.

2. a memory cell array having a plurality of memory cells arranged in a matrix; a first driver circuit electrically connected to the bit line; a second drive circuit electrically connected to the word line; Each of the plurality of memory cells includes a first transistor and a capacitance element; one of a source and a drain of the first transistor is electrically connected to the bit line; the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor; a gate electrode of the first transistor is electrically connected to the word line; the first transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer has crystals oriented such that a c-axis is perpendicular to a surface of the oxide semiconductor layer, the oxide semiconductor layer contains In, The crystal has an In-containing layer parallel to the a-axis and the b-axis, the oxide semiconductor layer has a region in contact with an upper surface of the first insulating layer, a first conductive layer having a function as a gate electrode of the first transistor is provided above the oxide semiconductor layer with a second insulating layer having a function as a gate insulating layer interposed therebetween; a second conductive layer having a function as one of a source electrode and a drain electrode of the first transistor, the second conductive layer having a region in contact with a top surface of the first insulating layer and having a function as one electrode of the capacitor; a third conductive layer having a function as the other electrode of the capacitance element is provided above the second conductive layer via the second insulating layer and has the same material as the first conductive layer; a first transistor being turned on to apply a potential to one electrode of the capacitor, and then the first transistor being turned off to hold the charge applied to the capacitor.

3. In claim 2, The memory device, wherein electrical conduction of the crystallized oxide semiconductor layer is controlled by the In-containing layer.

4. a memory cell array having a plurality of memory cells arranged in a matrix; a first driver circuit electrically connected to the bit line; a second drive circuit electrically connected to the word line; Each of the plurality of memory cells includes a first transistor and a capacitance element; one of a source and a drain of the first transistor is electrically connected to the bit line; the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor; a gate electrode of the first transistor is electrically connected to the word line; the first transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer has crystals oriented such that a c-axis is perpendicular to a surface of the oxide semiconductor layer, The oxide semiconductor layer has a hydrogen concentration of 5×10 １９ atoms / cm ３ is as follows: the oxide semiconductor layer has a region in contact with an upper surface of the first insulating layer, a first conductive layer having a function as a gate electrode of the first transistor is provided above the oxide semiconductor layer with a second insulating layer having a function as a gate insulating layer interposed therebetween; a second conductive layer having a function as one of a source electrode and a drain electrode of the first transistor, the second conductive layer having a region in contact with a top surface of the first insulating layer and having a function as one electrode of the capacitor; a third conductive layer having a function as the other electrode of the capacitance element is provided above the second conductive layer via the second insulating layer and has the same material as the first conductive layer; a first transistor being turned on to apply a potential to one electrode of the capacitor, and then the first transistor being turned off to hold the charge applied to the capacitor.

5. a memory cell array having a plurality of memory cells arranged in a matrix; a first driver circuit electrically connected to the bit line; a second drive circuit electrically connected to the word line; Each of the plurality of memory cells includes a first transistor and a capacitance element; one of a source and a drain of the first transistor is electrically connected to the bit line; the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor; a gate electrode of the first transistor is electrically connected to the word line; the first transistor has a channel formation region in an oxide semiconductor layer, the oxide semiconductor layer has crystals oriented such that a c-axis is perpendicular to a surface of the oxide semiconductor layer, the oxide semiconductor layer has an i-type or substantially i-type region, the oxide semiconductor layer has a region in contact with an upper surface of the first insulating layer, a first conductive layer having a function as a gate electrode of the first transistor is provided above the oxide semiconductor layer with a second insulating layer having a function as a gate insulating layer interposed therebetween; a second conductive layer having a function as one of a source electrode and a drain electrode of the first transistor, the second conductive layer having a region in contact with a top surface of the first insulating layer and having a function as one electrode of the capacitor; a third conductive layer having a function as the other electrode of the capacitance element is provided above the second conductive layer via the second insulating layer and has the same material as the first conductive layer; a first transistor being turned on to apply a potential to one electrode of the capacitor, and then the first transistor being turned off to hold the charge applied to the capacitor.

6. In any one of claims 1 to 5, At least one of the first drive circuit and the second drive circuit includes a second transistor; The second transistor has silicon in a channel formation region.

7. In any one of claims 1 to 6, The oxide semiconductor layer is any one of an In-Sn-Ga-Zn-O based, an In-Ga-Zn-O based, an In-Sn-Zn-O based, an In-Al-Zn-O based, an In-Zn-O based, an In-Mg-O based, and an In-O based.

8. In any one of claims 1 to 7, Among the plurality of memory cells, at least two memory cells arranged in the same column are electrically connected to the same bit line; At least two of the memory cells arranged in the same row are electrically connected to the same word line.

9. In any one of claims 1 to 8, The memory device, wherein the memory cell array is provided above the first drive circuit and above the second drive circuit.

10. In any one of claims 1 to 9, Each of the plurality of memory cells includes a third transistor; a gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor and one electrode of the capacitor.

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