Semiconductor Device

Abstract

To provide a semiconductor device of a novel structure, which can retain storage contents even in a situation where power is not supplied during storage retention period and which has no limits on the number of write times.SOLUTION: A semiconductor device comprises a transistor and a capacitative element. The transistor includes a first oxide semiconductor layer, a source electrode and a drain electrode which contact the first oxide semiconductor layer, a gate electrode overlapping the first oxide semiconductor layer and a gate insulation layer provided between the first oxide semiconductor layer and the gate electrode. The capacitative element includes a source electrode or a drain electrode, a second oxide semiconductor layer which contacts the source electrode or the drain electrode and a capacitative element electrode which contacts the second oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a method for driving the same. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. They are broadly divided into volatile types, which retain their memory contents even if the power supply is cut off, and non-volatile types, which retain their memory contents even if the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from the transistors. By storing charge in the capacitance element, information is stored.

[0004] According to the above principle, in DRAM, when information is read, the charge in the capacitance element is lost, so Each time the memory element is read, a write operation is required again. In a transistor, the leakage current between the source and drain in the off state (off current) Even when the transistor is not selected, charge flows in and out, so the data The retention period is short. Therefore, a rewrite operation (refresh operation) is required at regular intervals. It is difficult to reduce the power consumption. Since the capacity of the memory is lost, other storage devices using magnetic or optical materials are required for long-term memory retention. It will be necessary to place

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store data. No refresh operation is required to retain data, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, if the power supply is cut off, the memory contents are lost. In this regard, there is no difference with DRAM.

[0006] A typical example of a non-volatile memory device is a flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data is retained for an extremely long period of time. The advantage is that it lasts a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. For example, see Patent Document 1.

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem that the memory element may become non-functional after a certain number of writes. In order to alleviate the effect of this problem, for example, the number of write operations to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of life span is not solved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] Also, to inject charge into the floating gate or to remove that charge. A high voltage is required, and a circuit for this is also required. It takes a relatively long time to erase or write data, and it is not easy to speed up writing and erasing. There is also the problem that... [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above problems, in one embodiment of the disclosed invention, power is not supplied during the memory retention time. A new structure that allows memory contents to be retained even in difficult situations and has no limit on the number of times it can be written. An object is to provide a semiconductor device. [Means for solving the problem]

[0011] In the disclosed invention, a material capable of sufficiently reducing the off-state current of a transistor, e.g. For example, a semiconductor device is formed using an oxide semiconductor material which is a wide gap semiconductor. By using semiconductor materials that can sufficiently reduce the off-state current of the transistor, In addition, oxide semiconductor materials have a high dielectric constant. Therefore, by using an oxide semiconductor material as the dielectric of the capacitive element, the capacitance per unit area can be increased. It is possible to increase the

[0012] One embodiment of the present invention includes a transistor and a capacitor. a gate insulating layer on the gate electrode; and a first oxide layer on the gate insulating layer and overlapping the gate electrode. a source electrode electrically connected to the first oxide semiconductor layer on the first oxide semiconductor layer; The capacitance element has a source electrode and a drain electrode, and the capacitance element has a capacitance equal to the source electrode or the drain electrode. a first electrode made of a first conductive layer; a second oxide semiconductor layer in contact with the first electrode; and a second electrode in contact with the oxide semiconductor layer.

[0013] Another embodiment of the present invention is a semiconductor device including a transistor and a capacitor. an electrode; a gate insulating layer on the gate electrode; and a first oxide layer on the gate insulating layer overlapping the gate electrode. a second oxide semiconductor layer on the first oxide semiconductor layer and electrically connected to the first oxide semiconductor layer; A source electrode and a drain electrode, a first oxide semiconductor layer, a source electrode, and a drain electrode a first oxide semiconductor layer over the insulating layer; and an electrode overlapping with the first oxide semiconductor layer over the insulating layer. a first electrode, a second oxide semiconductor layer in contact with the first electrode, and a second oxide semiconductor layer and a second electrode made of the same conductive layer as the source electrode or the drain electrode, the second electrode being in contact with the source electrode or the drain electrode. It is a semiconductor device.

[0014] Another embodiment of the present invention is a transistor and a capacitor. On the source and drain electrodes, a first oxide semiconductor layer electrically connected to the gate electrode; and a gate insulating film on the first oxide semiconductor layer. a gate insulating layer and a gate electrode overlapping the first oxide semiconductor layer on the gate insulating layer; The capacitance element includes a first electrode made of the same conductive layer as the source electrode or the drain electrode, and a first a second oxide semiconductor layer in contact with the electrode; and a second electrode in contact with the second oxide semiconductor layer. The semiconductor device has the following features.

[0015] In addition, a metal oxide layer may be provided between the first electrode and the second oxide semiconductor layer. .

[0016] In addition, a metal oxide layer may be provided between the second electrode and the second oxide semiconductor layer. .

[0017] The gate electrode is made of an In-Ga-Zn-ON compound conductor. Good too.

[0018] The second oxide semiconductor layer may be formed of any one of silicon, germanium, cerium, titanium, and tungsten. One or more of the following elements: tenn, aluminum, copper, yttrium, lanthanum, and vanadium 1×10 20 atoms / cm 3 It may include more than one.

[0019] In addition, the first oxide semiconductor layer and the second oxide semiconductor layer are non-single crystal and have an ab-plane When viewed from the top, the atomic arrangement is triangular or hexagonal, and the metal elements are aligned along the c-axis. or an oxide semiconductor including a phase in which metal elements and oxygen elements are arranged in a layered form, It is non-single crystal and has a triangular or hexagonal atomic arrangement when viewed from the ab plane, and In the c-axis, the phases in which metal elements are arranged in layers or metal elements and oxygen elements are arranged in layers are included. The nitride semiconductor may include an oxynitride semiconductor.

[0020] In addition, a driving circuit including a transistor, a capacitor, and a material other than an oxide semiconductor and a path.

[0021] In the above description, a transistor may be formed using an oxide semiconductor. The present invention is not limited to this. For example, wide-gap semiconductor materials with an energy gap Eg of more than 3 eV ( More specifically, for example, silicon carbide may be used.

[0022] In this specification, the terms "above" and "below" refer to the positional relationship of components "directly above" or "below." For example, "gate electrode on a gate insulating layer" is not limited to "directly under". ", it excludes those that include other components between the gate insulating layer and the gate electrode. do not have.

[0023] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0024] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification and the like, the terms "source" and "drain" may be used interchangeably. It is possible.

[0025] In this specification, "electrically connected" means "something that has some kind of electrical effect" " includes cases where the device is connected via a "device that has some electrical function." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects.

[0026] For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. switching elements, resistor elements, inductors, and other elements with various functions. Included. Effect of the Invention

[0027] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced. Also, when there is no power supply (although the potential is Even if the contents are stored in a hard disk (preferably fixed), it is possible to retain the contents for a long period of time. It is possible.

[0028] In addition, since oxide semiconductor materials have a high dielectric constant, they can be used as dielectrics for capacitance elements. By using this, it is possible to increase the capacitance per unit area. Since the area of ​​the quantum elements is reduced, high integration is possible, and the semiconductor device can be made smaller. It is also possible to reduce the frequency of refresh operations and further reduce power consumption. It is.

[0029] In addition, the semiconductor device according to the disclosed invention does not require a high voltage to write information. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed by the memory, high-speed operation can be easily realized. Another advantage is that no action is required.

[0030] Furthermore, transistors using materials other than oxide semiconductors can operate at sufficiently high speed. Therefore, it is possible to realize various circuits (logic circuits, driver circuits, etc.) that require high speed operation. It is possible.

[0031] Therefore, transistors using materials other than oxide semiconductors (transistors using oxide semiconductors) The peripheral circuits, such as the driver circuits, use MOS transistors (which can operate at higher speeds than MOS transistors), and the By integrating a transistor using a semiconductor and a memory circuit using a capacitance element, It is possible to realize a semiconductor device having unprecedented features. [Brief description of the drawings]

[0032] [Figure 1] FIG. [Diagram 2] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Diagram 3] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 4] FIG. [Diagram 5] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 7] FIG. [Figure 8] FIG. [Figure 9] 1A to 1C are a cross-sectional view, a plan view, and a circuit diagram of a semiconductor device. [Figure 10] 1A and 1B are cross-sectional and conceptual diagrams of a semiconductor device. [Figure 11] FIG. [Figure 12] FIG. [Figure 13] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 14] FIG. 1 is a block diagram of a semiconductor device. [Figure 15] FIG. 1 is a block diagram of a semiconductor device. [Figure 16] FIG. 1 is a block diagram of a semiconductor device. [Figure 17] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device. [Figure 18] 1A to 1C illustrate a method for evaluating a semiconductor layer. [Figure 19] FIG. 1 shows the results of CV measurement. [Figure 20] FIG. 1 shows the results of CV measurement. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and may be modified in various forms and without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0034] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0035] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0036] (Embodiment 1) In this embodiment, a structure of a semiconductor device and a manufacturing method thereof according to one embodiment of the present invention will be described. This will be described with reference to FIGS.

[0037] <Cross-sectional structure of semiconductor device> FIG. 1 shows an example of the configuration of a semiconductor device. FIG. 1(A) to FIG. 1(D) show cross sections of the semiconductor device. The semiconductor device shown in FIG. 1A and FIG. 1C has an oxide semiconductor in a channel formation region. The transistor 160 includes a semiconductor layer, and the capacitor 164 includes an oxide semiconductor layer. The semiconductor device illustrated in FIG. 1B and FIG. 1D has a channel formation region including an oxide semiconductor and a capacitor 164 using an oxide semiconductor as a dielectric. .

[0038] Although the above transistor will be described as an n-channel transistor, It goes without saying that a channel type transistor can be used. The technical essence of the invention is to use an oxide semiconductor as a transistor 160 to store data. The specific configuration of the semiconductor device is as follows: It is not necessary to be limited to what is shown here.

[0039] The transistor 160 in FIG. 1A includes a gate electrode 14 provided on an insulating layer 140. 8a, a gate insulating layer 146 covering the gate electrode 148a, and a gate insulating layer 146 on the gate insulating layer 146. The first oxide semiconductor layer 144a overlaps the first electrode 148a. A source electrode or a drain electrode electrically connected to the first oxide semiconductor layer 144a on the first oxide semiconductor layer 144b. The transistor has a drain electrode 142b and a drain or source electrode 142a. The transistor 160 is not limited to be provided on the insulating layer 140. For example, the transistor 160 may be provided on a substrate having an insulating surface. It may be on a substrate.

[0040] The capacitor 164 in FIG. 1A includes a first electrode 148b and a second electrode 148c connected to the first electrode 148b. a source electrode in contact with the second oxide semiconductor layer 144b; Here, the source or drain electrode 14 2 b functions as a second electrode of the capacitor 164 .

[0041] That is, it can be said as follows. The capacitor 164 has a first electrode 148b and The second oxide semiconductor layer 144b and the second electrode are provided. The positive or negative electrode 142a is made of the same conductive layer as the positive or negative electrode 142b.

[0042] The work function of the first electrode 148b is larger than the electron affinity of the second oxide semiconductor layer 144b. For example, the second oxide semiconductor layer 144b may be formed using an In-Ga- When Zn-O oxide is used, its electron affinity is about 4.6 eV. In this case, a material having a work function larger than the electron affinity of the second oxide semiconductor layer 144b is, for example, nitrogen. Indium nitride, zinc nitride, nickel, molybdenum oxide, tungsten oxide, In-Ga- Zn-ON compound conductors and the like are examples.

[0043] (Work function of the first electrode 148b)-(Electron affinity of the second oxide semiconductor layer 144b) In most cases, the second acid is at least 0.5 electron volts, preferably at least 1 electron volt. In other words, no electrons flow into the second oxide semiconductor layer 144b. exhibits sufficient insulating properties and can be used as a capacitive element.

[0044] (Work function of the first electrode 148b)-(Electron affinity of the second oxide semiconductor layer 144b) Even if the potential is 0.5 eV or more, the potential may vary depending on the material of the source electrode or drain electrode 142b. As a result, electrons are transferred from the source or drain electrode 142b to the second oxide semiconductor layer 144b. This is because the work function of the source or drain electrode 142b is This can occur when the electron affinity of the second oxide semiconductor layer 144b is smaller than that of the second oxide semiconductor layer 144b. In this case, the voltage applied to the first electrode 148b and the source or drain electrode 142b and Depending on the voltage and polarity, it can function as a capacitance element without causing the inflow of electrons. However, if the source electrode or drain electrode 142b is made of the same material as the first electrode 148b, If the material is made of the materials listed above or materials with equivalent or higher work functions, the voltage and It can be used as a capacitive element regardless of its polarity.

[0045] Here, the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b are formed of hydrogen or the like. It is preferable that the impurities are sufficiently removed to achieve a high level of purity. In addition, the supply of sufficient oxygen reduces the defect levels in the energy gap. Specifically, for example, the first oxide semiconductor layer 144a and the second oxide semiconductor layer The hydrogen concentration in the oxide semiconductor layer 144b is 5×10 19 atoms / cm 3 The following is preferable: 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 The above-mentioned first oxide semiconductor layer 144a and the second oxide semiconductor layer 1 The hydrogen concentration in 44b was measured by secondary ion mass spectrometry (SIMS). The hydrogen concentration was measured by mass spectroscopy. The amount of oxygen in the fuel is sufficiently reduced and the fuel is highly purified, and the energy loss caused by oxygen deficiency is reduced by providing sufficient oxygen. The first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b have reduced defect levels in the -gap. In the semiconductor layer 144b, the carrier concentration is 1×10 12 / cm 3 Less than 1×1, preferably 0 11 / cm 3 Less than 1.45×10 10 / cm 3 For example, The off-state current at room temperature (off-state current divided by the channel width of the transistor) is 10zA / μm to 100zA / μm (1zA (zeptoampere) is 1×10 -21 A) is about the same. By using an i-type (intrinsic) or substantially i-type oxide semiconductor as shown in A transistor 160 with extremely excellent off-state current characteristics can be obtained.

[0046] In addition, when the oxide semiconductor layer is i-type (intrinsic) or substantially i-type, the dielectric constant Specifically, the dielectric constant of the In-Ga-Zn-O-based oxide semiconductor layer can be increased. The dielectric constant can be about 15. This is because the dielectric constant of silicon oxide is about 4. Therefore, the i-type (intrinsic) or substantially i-type oxide semiconductor By using the dielectric layer as the dielectric of the capacitance element 164, the capacitance per unit area of ​​the capacitance element 164 can be increased. The amount can be increased.

[0047] The oxide semiconductor layer may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0048] Preferably, the oxide semiconductor layer is made of CAAC-OS (C Axis Aligned Cr The layer is a crystalline oxide semiconductor (SOxO2) layer.

[0049] The CAAC-OS layer is neither completely single crystalline nor completely amorphous. The oxide semiconductor layer has a crystalline-amorphous mixed phase structure in which a crystalline portion is included in an amorphous phase. The crystal portion is often small enough to fit within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the observation image by a microscope, the boundary between the amorphous and crystalline parts in the CAAC-OS layer was In addition, the grain boundaries in the CAAC-OS layer were not clearly observed by TEM. Therefore, the CAAC-OS layer is not characterized by electron transfer due to grain boundaries. The decrease in mobility is suppressed.

[0050] The c-axis of the crystalline part in the CAAC-OS layer is the normal vector of the surface on which the CAAC-OS layer is formed. The three are aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. It has a square or hexagonal atomic arrangement, and when viewed perpendicular to the c-axis, the metal atoms are arranged in layers or In addition, between different crystal parts, a The orientation of the a-axis and the b-axis may be different. In this specification, when it is simply described as vertical , the range of 85° or more and 95° or less is also included.

[0051] In the CAAC-OS layer, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS layer, when crystal growth is performed from the surface side of the oxide semiconductor layer, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS layer, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0052] The c-axis of the crystalline part in the CAAC-OS layer is the normal vector of the surface on which the CAAC-OS layer is formed. The shape of the CAAC-OS layer (the surface on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. The c-axis direction of the crystal part is the normal vector of the surface on which the CAAC-OS layer is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0053] The electrical characteristics of transistors using the CAAC-OS layer change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0054] Further, part of oxygen contained in the oxide semiconductor layer may be replaced with nitrogen.

[0055] The second oxide semiconductor layer 144b contains more oxygen than the stoichiometric composition. Silicon, germanium, cerium, titanium, tungsten, and aluminum are also suitable. One or more elements of metals such as aluminum, copper, yttrium, lanthanum, vanadium, etc. The second oxide semiconductor layer 144b may contain these elements. The insulating properties can be improved.

[0056] The concentration of silicon, germanium and metal elements is 1×10 20 at oms / cm 3 More than 1×10 21 atoms / cm 3 More preferably, 5×10 21 atoms / cm 3 It can be more than that.

[0057] In the transistor 160 and the capacitor 164, the gate electrode 148a, the first The electrode 148b, the gate insulating layer 146, the first oxide semiconductor layer 144a and the second oxide The end of the semiconductor layer 144b is preferably tapered. Here, the taper angle is For example, the taper angle is 30° or more and 60° or less. A layer (for example, a gate electrode 148a) is cut in a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate). The gate electrode 148a is a gate electrode having a first side and a second side. The first electrode 148b, the gate insulating layer 146, the first oxide semiconductor layer 144a and the second oxide The end of the compound semiconductor layer 144b is tapered to form a source electrode or a drain electrode. The coverage of the drain electrode 142b and the source electrode 142a is improved, and the step-disconnection This is because it is possible to prevent the above.

[0058] In addition, an insulating layer 150 is provided over the transistor 160 and the capacitor 164. do.

[0059] The transistor 162 and the capacitor 164 shown in FIG. 1 is a modified example of the resistor 160 and the capacitive element 164.

[0060] The difference between the configuration shown in FIG. 1A and the configuration shown in FIG. 1B is the transistor 162 is at the point including the electrode 152 on the insulating layer 150. The transistor 162 has a channel Above and below the first oxide semiconductor layer 144a having the formation region, two gate electrodes are provided via an insulating layer. The transistor is a dual-gate transistor having an electrode layer. 162 is a gate electrode 148a, a gate insulating layer 146 on the gate electrode 148a, and a gate A first oxide semiconductor layer 144a overlapping the gate electrode 148a on the gate insulating layer 146; A source electrically connected to the first oxide semiconductor layer 144a on the second oxide semiconductor layer 144a is The semiconductor device has a source electrode or drain electrode 142b and a drain electrode or source electrode 142a. Further, the first oxide semiconductor layer 144a, the source or drain electrode 142b, and and an insulating layer 150 on the drain or source electrode 142a, and a first and an electrode 152 overlapping with the oxide semiconductor layer 144a.

[0061] In FIG. 1B, the gate electrode 148a and the electrode 152 function together as a gate electrode. The potential of the electrode 152 may be the same as or different from that of the gate electrode 148a. The gate electrode 148a and the gate electrode 148b may be connected to GND, 0V, or may be in a floating state. The electrode 152 controls the electric field applied to the first oxide semiconductor layer 144a. The threshold voltage of the transistor 162 can be controlled.

[0062] The transistor 160 and the capacitor 164 shown in FIG. 1 is a modified example of the capacitor 160 and the capacitive element 164.

[0063] The difference between the configuration shown in FIG. 1(A) and the configuration shown in FIG. 1(C) is that the capacitance element 16 in FIG. In the fourth embodiment, the first electrode 148b has a metal oxide layer on the surface in contact with the second oxide semiconductor layer 144b. Furthermore, in the capacitor 164 of FIG. The drain electrode 142b has a metal oxide layer on a surface thereof that is in contact with the second oxide semiconductor layer 144b. Furthermore, in the transistor 160 of FIG. The metal oxide semiconductor layer 144a is formed on the surface of the source electrode 142a that is in contact with the first oxide semiconductor layer 144a. It may have a layer 141a.

[0064] When the second oxide semiconductor layer 144b and the first electrode 148b are in contact with each other, the first electrode 148b As a result, oxygen may be removed from the second oxide semiconductor layer 144b. When oxygen is taken away from the conductor layer 144b, the oxygen vacancies increase. The conductivity of the compound semiconductor layer 144b becomes high, and there is a risk that the compound semiconductor layer 144b will no longer function as a dielectric of the capacitance element. There is.

[0065] Therefore, the first electrode having the metal oxide layer 149b in contact with the second oxide semiconductor layer 144b is The metal oxide layer 149b is preferably a second oxide semiconductor layer. This can prevent oxygen from being taken away from the first electrode 144b by the first electrode 148b. Oxygen is supplied from the metal oxide layer 149b to the second oxide semiconductor layer 144b. This also makes it possible to further reduce oxygen deficiencies in the conductor layer 144b.

[0066] The metal oxide layer 141b and the metal oxide layer 141a are made of a highly conductive metal oxide. By using a layer having a high conductivity, the capacitance element 164 and the transistor This allows good electrical connection with the motor 160 to be maintained.

[0067] In addition, the second oxide semiconductor layer 144b and the source or drain electrode 142b are in contact with each other. In this case, the source or drain electrode 142b is used to separate the second oxide semiconductor layer 144b. When oxygen is removed from the second oxide semiconductor layer 144b, oxygen The second oxide semiconductor layer 144b with the increased oxygen vacancies has high electrical conductivity. , there is a risk that it will no longer function as a dielectric for the capacitive element.

[0068] Therefore, a source electrode having a metal oxide layer 141b in contact with a second oxide semiconductor layer 144b is The metal oxide layer 141b is preferably a first electrode or drain electrode 142b. The source electrode or drain electrode 142b loses oxygen from the oxide semiconductor layer 144b. In addition, the metal oxide layer in contact with the first oxide semiconductor layer 144a can be prevented from being damaged. Alternatively, the drain electrode 141a may be replaced with the source electrode 142a. The positive or source electrode 142a can be formed simultaneously with the metal oxide layer 141b. By forming the metal oxide layer 141b and the metal oxide layer 141a, a first oxide semiconductor Oxygen is supplied to the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b. Therefore, oxygen vacancies in the layer 144a and the second oxide semiconductor layer 144b can be further reduced. .

[0069] Note that whether oxygen is removed from the second oxide semiconductor layer 144b depends on the conditions of a subsequent step. When oxygen is not taken away from the second oxide semiconductor layer 144b, the metal The oxide layer 149b and the metal oxide layer 141b may not be formed.

[0070] FIG. 1C illustrates a case where a metal oxide layer 149b and a metal oxide layer 141b are provided. Although shown in the figure, the present invention is not limited to this. Only the metal oxide layer 149b or the metal oxide layer 141b Alternatively, only the metal oxide layer 149b or only the metal oxide layer 141b may be provided. In this case, the capacitance per unit area is further increased, which is preferable.

[0071] The transistor 162 and the capacitor 164 shown in FIG. 1 is a modified example of the capacitor 160 and the capacitive element 164.

[0072] The difference between the configuration shown in FIG. 1C and the configuration shown in FIG. 1D is the transistor 162 is at the point including the electrode 152 on the insulating layer 150. The transistor 162 has a channel Dual-gate type, which has two gate electrode layers arranged above and below the region with an insulating layer between them Specifically, the transistor 162 has a gate electrode 148a and a gate The first oxide semiconductor layer 144a on the first electrode 148a and the first oxide semiconductor layer 144a A source electrode or drain electrode 1 electrically connected to the first oxide semiconductor layer 144a 42b and a drain or source electrode 142a. The conductor layer 144a, the source or drain electrode 142b and the drain electrode An insulating layer 150 on the first electrode 142a, and a first oxide semiconductor layer 144a on the insulating layer 150. and an overlapping electrode 152.

[0073] In FIG. 1D, the gate electrode 148a and the electrode 152 function together as a gate electrode. The potential of the electrode 152 may be the same as or different from that of the gate electrode 148a. The gate electrode 148a and the gate electrode 148b may be connected to GND, 0V, or may be in a floating state. The electrode 152 controls the electric field applied to the first oxide semiconductor layer 144a. The threshold voltage of the transistor 162 can be controlled.

[0074] <Method for Manufacturing Semiconductor Device> Next, the transistor 160 and the transistor 162 shown in FIG. The manufacturing method will be described with reference to FIGS.

[0075] First, a conductive layer is formed on the insulating layer 140, and the conductive layer is processed to form the first electrode 148b. And a gate electrode 148a is formed (see FIG. 2(A)).

[0076] The insulating layer 140 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, The insulating layer 140 is formed using a material containing an inorganic insulating material such as aluminum oxide. Alternatively, the insulating layer 1 may be formed using an organic insulating material such as polyimide or acrylic. The substrate 40 can be formed in a single layer structure or a laminated structure using the above-mentioned materials. In this embodiment, a case where silicon oxide is used as the insulating layer 140 will be described.

[0077] The transistors 160 and 162 are formed on the insulating layer 140. For example, the semiconductor device may be fabricated on a substrate having an insulating surface. Insulating substrates made of insulators such as glass substrates, ceramic substrates, quartz substrates, and sapphire substrates A semiconductor substrate made of a semiconductor material such as silicon, a conductive material made of a conductor such as metal or stainless steel, A substrate, a surface of which is covered with an insulating material, etc. can be used. Flexible substrates such as sticks generally tend to have a low heat resistance, but this can be achieved during subsequent fabrication processes. If it can be tolerated, it can be used.

[0078] The first electrode 148b and the gate electrode 148a are made of molybdenum, titanium, tantalum, or tantalum. Metallic materials such as tin, aluminum, copper, neodymium, scandium, etc., or materials mainly composed of these The first electrode 148b and the gate electrode 148c can be formed of an alloy material. The electrode 148a may have a single-layer structure or a multi-layer structure. It can also be a two-layer structure with copper laminated on a magnesium-aluminum alloy layer, or It may also have a three-layer structure in which molybdenum, aluminum, and molybdenum are laminated in that order.

[0079] The first electrode 148b and the gate electrode 148a are made of an In-Ga-Zn-ON compound. Alternatively, the gate electrode 148a may be formed using a material having a large work function, such as an InP. -By using materials with a large work function such as Ga-Zn-ON compound conductors, The electrical characteristics of the resistor 160, such as the threshold voltage, can be controlled.

[0080] Next, an insulating layer is formed and processed to form a gate electrode 148a. An insulating layer 146 is formed (see FIG. 2B). The insulating layer is processed to form a first electrode 148b. By removing the insulating layer from above, the first electrode 148b and the second oxide semiconductor layer to be formed later are exposed. The conductor layer 144b can be provided in contact with the dielectric layer 144b. The layer that functions as a dielectric constant can be the second oxide semiconductor layer 144b alone. The capacity is improved compared to the case where an insulating layer and the second oxide semiconductor layer 144b are stacked as a conductor. The dielectric of the capacitance element 164 can be formed thin. This allows the capacitance per unit area of ​​the capacitor 164 to be increased.

[0081] The gate insulating layer 146 can be formed by a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The gate insulating layer 146 is preferably formed to include a single layer structure. Alternatively, the above materials may be combined to form a laminate structure. Although not limited thereto, when miniaturizing a semiconductor device, in order to ensure the operation of a transistor, For example, when silicon oxide is used, the thickness is 1 nm to 100 nm. m or less, preferably 10 nm or more and 50 nm or less.

[0082] The gate insulating layer 146 may be formed using an insulating material containing a Group 13 element and oxygen. Many oxide semiconductor materials contain Group 13 elements, and insulating materials containing Group 13 elements are oxides. It has good compatibility with oxide semiconductors, and by using it as an insulating layer in contact with an oxide semiconductor layer, The state of the interface with the insulating semiconductor layer can be kept good. By material is meant that the insulating material contains one or more group 13 elements. An example of an insulating material containing hydrogen is aluminum oxide. Therefore, the use of the material is advantageous in that the oxide semiconductor layer This is also preferable in terms of preventing water from entering the device.

[0083] The insulating layer in contact with the first oxide semiconductor layer 144a is formed by heat treatment in an oxygen atmosphere or It is preferable to add oxygen to the insulating material to make it have a higher oxygen content than the stoichiometric composition ratio. The addition of oxygen is preferably performed by doping, ion implantation, ion doping, or the like. The doping of oxygen means adding oxygen to the bulk. The term bulk is used to clarify that oxygen is added not only to the surface of the thin layer but also to the inside of the thin layer. In addition, oxygen doping is done by adding oxygen plasma to the bulk. Oxygen plasma doping is included.

[0084] For example, aluminum oxide is used as an insulating layer in contact with the first oxide semiconductor layer 144a. In this case, the aluminum oxide can be obtained by heat treatment in an oxygen atmosphere or by oxygen doping. The composition is AlO X (X=3+α, 0<α<1).

[0085] By performing oxygen doping treatment, etc., an insulating film having a region with more oxygen than the stoichiometric composition ratio is formed. When the insulating layer having such a region is in contact with the oxide semiconductor layer, As a result, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and the oxide semiconductor layer and the The present invention reduces oxygen defects at the interface between the oxide semiconductor layer and the insulating layer, and makes the oxide semiconductor layer i-type or can be made as close as possible to type i.

[0086] The insulating layer having a region with more oxygen than the stoichiometric composition ratio can be used in place of the gate insulating layer 146. In addition, the insulating layer may be formed as a base layer for the transistor 160, and may be formed in a later process. It may be applied to the insulating layer 150 to be fabricated, or may be applied to some or all of these. .

[0087] In this embodiment, the gate insulating layer 146 is formed by a sputtering method. The silicon oxide used shall be 10 nm or more and 50 nm or less.

[0088] Next, an oxide semiconductor layer is formed and processed to form a gate insulating layer 146. A first oxide semiconductor layer 144a is formed so as to overlap with the gate electrode 148a. The second oxide semiconductor layer 148b is in contact with the first electrode 148b or the metal oxide layer 149b. 44b is formed (see FIG. 2(C)).

[0089] The material used for the oxide semiconductor layer is the quaternary metal oxide In-Sn-Ga-Zn -O oxides, ternary metal oxides such as In-Ga-Zn-O oxides, In-Sn- Zn-O oxide, In-Al-Zn-O oxide, Sn-Ga-Zn-O oxide, A The oxides are I-Ga-Zn-O, Sn-Al-Zn-O, and binary metal oxides. In-Zn-O oxides, Sn-Zn-O oxides, Al-Zn-O oxides, Zn- Mg-O oxides, Sn-Mg-O oxides, In-Mg-O oxides, In-Ga-O In-O oxide, Sn-O oxide, Zn-O oxide, etc. In addition, the above materials may contain SiO2. -Zn-O oxides are oxides containing indium (In), gallium (Ga), and zinc (Zn). The composition ratio is not particularly important. It may contain other elements.

[0090] The thickness of the oxide semiconductor layer is preferably 3 nm or more and 30 nm or less. If the conductor layer is made too thick (for example, 50 nm or thicker), the transistor will be normally on. In addition, compared with the thickness of the second oxide semiconductor layer 144b, For example, this is because the capacitance of the capacitive element 164 becomes smaller.

[0091] The oxide semiconductor layer is formed by a method that is unlikely to be contaminated with impurities such as hydrogen, water, a hydroxyl group, or a hydride. The oxide semiconductor layer is preferably formed by using a sputtering method, for example. It is possible.

[0092] In this embodiment, the oxide semiconductor layer is formed by using an In-Ga-Zn-O oxide target. The film is formed by a sputtering method.

[0093] The In-Ga-Zn-O oxide target may have a composition ratio of, for example, In2O 3: It is possible to use an oxide target with a Ga2O3:ZnO=1:1:1 [molar ratio]. The material and composition of the target do not have to be limited to those described above. For example, In The oxide target with a composition ratio of 2O3:Ga2O3:ZnO=1:1:2 [molar ratio] It can also be used.

[0094] The relative density of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99. The oxide formed by using a metal oxide target with a high relative density is This is because the compound semiconductor layer can be made dense.

[0095] The oxide semiconductor layer is preferably a CAAC-OS layer. The i-type (intrinsic semiconductor) or substantially i-type CAAC-OS layer to which It can be formed as follows.

[0096] First, a first oxide semiconductor layer is formed on a substrate by sputtering, molecular beam epitaxy, or atomic layer deposition. The film is formed by deposition or pulsed laser deposition. The substrate is heated during the formation. As a result, an oxide semiconductor layer in which the proportion of crystalline regions is high relative to amorphous regions can be obtained. For example, the substrate temperature may be set to 150° C. or higher and 450° C. or lower. The temperature is set to 200°C or higher and 250°C or lower.

[0097] By increasing the substrate temperature, the oxide of CAAC-OS can be crystallized more. do.

[0098] Next, the substrate may be subjected to a first heat treatment. By performing the first heat treatment, the substrate becomes more amorphous. The ratio of a crystalline region to a crystalline region of the oxide semiconductor layer can be increased. The heating may be performed at a temperature of, for example, 200° C. or higher and lower than the distortion point of the substrate. By performing the heat treatment, hydrogen atoms contained in the oxide semiconductor layer are removed. The atmosphere is not limited, but may be an oxidizing atmosphere, an inert atmosphere, or an oxidizing atmosphere. The treatment is carried out in a normal atmosphere or a reduced pressure atmosphere. The treatment time is 3 minutes to 24 hours. The treatment time is increased. It is possible to form an oxide semiconductor layer having a higher ratio of crystalline regions to amorphous regions. However, heat treatment for more than 24 hours is not preferred because it leads to a decrease in productivity.

[0099] An oxidizing atmosphere is an atmosphere containing an oxidizing gas. The oxidizing gas is oxygen, ozone, or It is preferable that the gas used is nitrous oxide or the like, and does not contain water, hydrogen, etc. The purity of oxygen, ozone, and nitrous oxide introduced into the equipment must be 8N (99.999999%) or higher. The oxidizing atmosphere is preferably 9N (99.9999999%) or more. It may be mixed with an inert gas. In that case, the oxidizing gas must be at least 10 ppm. This is to be included.

[0100] Here, the inert atmosphere is nitrogen, rare gas (helium, neon, argon, krypton, The main component of the atmosphere is an inert gas such as xenon. The atmosphere should contain less than 10 ppm of reactive gas.

[0101] The first heat treatment is performed using an RTA (Rapid Thermal Anneal) device. By using an RTA, heat treatment can be performed at a temperature above the distortion point of the substrate for a short period of time. Therefore, an oxide semiconductor layer having a high ratio of crystalline regions to amorphous regions can be formed. The time required for formation can be reduced.

[0102] As an oxide, it has the chemical formula InMO3(ZnO) m Materials with the formula (m>0) may be used. Here, M is one or more metal elements selected from Ga, Al, Mn, and Co. For example, M may be Ga, Ga and Al, Ga and Mn, or Ga and Co. etc. may also be used.

[0103] Also, nitrogen 5×10 19 / cm 3 More than 1×10 20 / cm 3 More than 7 atomic % In-Ga-Zn-O oxides containing less than 100% of the ZnO content are oxides containing a hexagonal crystal structure aligned with the c-axis. between the In-O crystal plane (a crystal plane containing indium and oxygen) and the In-O crystal plane , a layer containing Ga and Zn. Or, an In-Ga layer containing nitrogen in the above range. In a-Zn-O oxides, multiple layers are formed between the In-O crystal planes. It is also possible to provide a layer having Ga and Zn.

[0104] In addition, a second oxide semiconductor layer is formed over the first oxide semiconductor layer to form an oxide stack. The first oxide semiconductor layer and the second oxide semiconductor layer may be formed by the same method. can be done.

[0105] When the second oxide semiconductor layer is formed, the substrate is heated, so that the first oxide semiconductor layer is The second oxide semiconductor layer can be crystallized using the conductor layer as a seed crystal.

[0106] Note that after the second oxide semiconductor layer is formed, a second heat treatment may be performed. The second heat treatment may be performed in the same manner as the first heat treatment. Alternatively, the second thermal oxide layer may be a layer having a high ratio of crystalline regions to the total region. By performing the treatment, the first oxide semiconductor layer is used as a seed crystal to bond the second oxide semiconductor layer. At this time, the first oxide semiconductor layer and the second oxide semiconductor layer are simultaneously crystallized. Alternatively, the first oxide semiconductor layer and the second oxide semiconductor layer may be homo-grown with one element. The oxide semiconductor layer of 2 is hetero-growth composed of at least one different element. It's okay to do so.

[0107] By reducing impurities and adding oxygen in the above manner, it is possible to produce i-type (intrinsic semiconductor) or substantially In the formation of such an oxide semiconductor layer, an i-type CAAC-OS can be formed. By doing so, it is possible to realize a transistor with extremely excellent characteristics.

[0108] In addition, when an oxide semiconductor is i-type (intrinsic) or substantially i-type, the dielectric constant is Specifically, the relative dielectric constant of In-Ga-Zn-O oxide is about 15. This is quite large compared to the relative dielectric constant of silicon oxide, which is about 4. Therefore, the i-type (intrinsic) or substantially i-type oxide semiconductor is used as a capacitor. By using it as the dielectric of the element 164, the capacitance per unit area of ​​the capacitive element 164 is increased. It is possible.

[0109] In addition, the oxide semiconductor layer is processed to form a first oxide semiconductor layer 144a and a second oxide semiconductor layer 144b. After the conductor layer 144b is formed, oxygen may be added to the second oxide semiconductor layer 144b. The second oxide semiconductor layer 144b is formed of a material containing silicon, germanium, cerium, and titanium. of metals such as tungsten, aluminum, copper, yttrium, lanthanum, and vanadium One or more of these elements may be added. By adding these elements, the second oxide This can improve the insulating properties of the semiconductor layer 144b.

[0110] The method of addition may be ion implantation or ion doping. The concentration of oxygen added is 1×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 If the oxygen concentration is in this range, the crystal is not distorted. Silicon, germanium can be incorporated into the oxide semiconductor without causing any damage. and for metallic elements, 1×10 20 atoms / cm 3 More than 1×102 1 atoms / cm 3 More preferably, 5×10 21 atoms / cm 3 That is all It is possible.

[0111] Next, the conductive layer 142 is formed (see FIG. 2D). b and the gate electrode 148a may be formed of the same material and with the same structure.

[0112] Next, the conductive layer 142 is processed to form a source electrode or drain electrode 142b and a drain electrode Then, a gate electrode or source electrode 142a is formed (see FIG. 3(A)).

[0113] Next, the source or drain electrode 142b, the drain or source electrode 142a The insulating layer 150 is formed so as to cover the first oxide semiconductor layer 144a. 0 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide The insulating layer 150 is formed using a material containing an inorganic insulating material such as tungsten. By using a low-k material, when various electrodes and wiring are provided on the insulating layer 150, This is preferable because it is possible to sufficiently reduce the capacitance caused by the insulating layer 150. A porous insulating layer using the above-mentioned materials may be applied to the insulating layer. The dielectric constant is reduced compared to high-temperature insulating layers, further reducing the capacitance caused by electrodes and wiring The insulating layer 150 can be made of an organic insulating material such as polyimide or acrylic. The insulating layer 150 may be formed of a single layer or a multilayer structure using the above-mentioned materials. can be formed to have a layered structure (see FIG. 3(B)).

[0114] Through the above steps, the transistor 160 and the capacitor 164 each using an oxide semiconductor layer are completed. (See FIG. 3(B)).

[0115] Further, an electrode 152 may be formed on the insulating layer 150. The electrode 152 is a first electrode 14. The electrode 1 can be formed of the same material and structure as the gate electrode 148a. The transistor 162 can control electrical characteristics such as a threshold voltage by the transistor 52 .

[0116] Through the above steps, a transistor 162 having the electrode 152 is completed (see FIG. 3C).

[0117] Next, the transistor 160 and the transistor 162 shown in FIG. A method for producing the above will be described.

[0118] First, the insulating layer 140 is formed. The insulating layer 140 is described with reference to FIG. This can be taken into consideration.

[0119] Next, a conductive layer is formed on the insulating layer 140, and the conductive layer is processed to form a first electrode 148b. Then, the first electrode 148b and the oxide layer to be formed later are formed. Before the semiconductor layer is in contact with the first electrode 148b, the first electrode 148b is oxidized or is formed by a sputtering method or a CV method. The metal oxide layer 149b is formed by using Method D.

[0120] The materials and structures of the first electrode 148b and the gate electrode 148a are shown in FIG. However, high-density oxygen plasma treatment or thermal oxidation can be used. When the metal oxide layer 149b is formed, the first electrode 148b and the gate electrode 148 It is preferable that a contains tungsten, titanium or zirconium. This is because these oxides have high electrical conductivity. Alternatively, a layer containing the metal oxide may be formed as the metal oxide layer 149b. The time for this may be before the insulating layer is formed or after the gate insulating layer 146 is formed. A metal oxide layer may be laminated on both the first electrode 148b and the gate electrode 148a. It may be laminated on only one electrode 148b.

[0121] The method for forming the metal oxide layer 149b is not particularly limited, but may be, for example, high-density oxygen plasma treatment. The high density oxygen plasma treatment can be carried out by, for example, helium, argon, This is done using a mixture of oxygen and rare gases such as krypton and xenon. In this case, plasma By exciting the plasma with microwaves, a high density plasma with a low electron temperature can be generated. The oxygen radicals (OH radicals) generated in such high-density plasma can be By oxidizing the surface of the first electrode 148b by the method described above, the thickness of the first electrode 148b can be reduced by 1 nm or more. A metal oxide layer 149b having a thickness of 20 nm or less, preferably 5 nm to 10 nm, is formed. It is possible.

[0122] The oxidation of the first electrode 148b by the high-density oxygen plasma treatment described above is a solid-phase growth. In addition, the interface state density between the first electrode 148b and the metal oxide layer 149b is extremely low. In addition, the first electrode 148b can be directly oxidized by high-density oxygen plasma treatment. As a result, the variation in thickness of the formed metal oxide layer 149b can be suppressed.

[0123] Alternatively, the first electrode 148b may be thermally oxidized to form the metal oxide layer 149b. In this way, when thermal oxidation is used, a substrate having a certain degree of heat resistance is required. It is necessary to use

[0124] Alternatively, a layer formed by a sputtering method or a CVD method is processed to form a metal oxide layer 149b. The sputtering method may be described later. The method of forming layers can be taken into consideration.

[0125] In this embodiment, a metal oxide film having a thickness of 5 nm or more and 10 nm or less is formed by high-density oxygen plasma treatment. A layer 149b is formed.

[0126] The metal oxide layer 149b is used to form a first oxide semiconductor layer 144b to a second oxide semiconductor layer 144c that will be formed in a later step. In addition, the metal oxide layer 149 can be prevented from losing oxygen to the first electrode 148b. b to a second oxide semiconductor layer 144b to be formed in a later step, The oxygen deficiency in the semiconductor layer 144b can be further reduced. By using the material layer 149b, it is possible to prevent the capacitance of the capacitive element 164 from decreasing.

[0127] Next, an insulating layer is formed and processed to form a gate electrode 148a. An insulating layer 146 is formed. For the gate insulating layer 146, refer to the description of FIG. I can pour drinks.

[0128] Next, an oxide semiconductor layer is formed and processed to form a gate insulating layer 146. A first oxide semiconductor layer 144a is formed so as to overlap with the gate electrode 148a. The second oxide semiconductor layer 148b is in contact with the first electrode 148b or the metal oxide layer 149b. The oxide semiconductor layer, the first oxide semiconductor layer 144a and the second oxide semiconductor layer 44b are formed. For the semiconductor layer 144b, the description of FIG.

[0129] Next, a metal oxide layer is formed. The metal oxide layer is formed by using a CVD method, a sputtering method, or the like. The metal oxide layer can be formed by using tungsten oxide, titanium oxide, zirconium oxide, etc. It is preferable that the structure contains In-Ga-Zn-ON compound. This is because these metal oxides have high electrical conductivity. The thickness of the metal oxide layer is not particularly limited, but For example, the thickness of the film may be 1 nm or more and 20 nm or less, and preferably 5 nm or more and 10 nm or less. can.

[0130] Next, the conductive layer 142 is formed. The conductive layer 142 includes the first electrode 148b and the gate electrode. The conductive layer 142 and the first Before the oxide semiconductor layer 144a and the second oxide semiconductor layer 144b come into contact with each other, It is preferable to form an oxide layer.

[0131] Next, the conductive layer 142 and the metal oxide layer are processed to form a source electrode or a drain electrode 142. b, the metal oxide layer 141b, the drain or source electrode 142a, and the metal oxide A layer 141a is formed.

[0132] By using the metal oxide layer 141a having high conductivity, the capacitor 164 and the transistor 16 In addition, the metal oxide layer 141b and the metal The oxide layer 141a prevents the first oxide semiconductor layer 144a and the second oxide semiconductor layer 1 In addition, the metal oxide layer 141b and the metal oxide layer 44b can be prevented from losing oxygen. The first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b are formed from the metal oxide layer 141a. oxygen is supplied to the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b. The oxygen vacancies in 144b can be reduced.

[0133] Next, the source or drain electrode 142b, the metal oxide layer 141b, and the drain electrode or source electrode 142a, metal oxide layer 141a, and first oxide semiconductor layer 144a An insulating layer 150 is formed to cover the gate insulating layer 146. The insulating layer 150 is made of the same material as the gate insulating layer 146. It can be formed with materials and configurations.

[0134] Through the above steps, the transistor 160 and the capacitor 164 each using an oxide semiconductor layer are completed. (See Figure 1(C)).

[0135] Further, an electrode 152 may be formed on the insulating layer 150. The electrode 152 is a first electrode 14. The electrode 1 can be formed of the same material and structure as the gate electrode 148a. The transistor 162 can control electrical characteristics such as a threshold voltage by the transistor 52 .

[0136] Through the above steps, a transistor 162 having the electrode 152 is completed (see FIG. 1D).

[0137] (Embodiment 2) In this embodiment mode, a structure of a semiconductor device different from that in Embodiment Mode 1 and a manufacturing method thereof will be described. This will be described with reference to FIGS.

[0138] <Cross-sectional structure of semiconductor device> FIG. 4 shows an example of the configuration of a semiconductor device. FIG. 4(A) and FIG. 4(B) show cross-sectional views of the semiconductor device. The semiconductor device shown in FIG. 4(A) and FIG. 4(B) has an oxide film in the channel formation region. A transistor 160 using a semiconductor and a capacitor 164 using an oxide semiconductor as a dielectric are provided. Yes.

[0139] The transistor 160 in FIG. 4A has a source electrode or The drain electrode 142b and the drain or source electrode 142a and the source electrode On the drain or source electrode 142b and the drain or source electrode 142a, a source electrode Alternatively, the drain electrode 142b and the drain or source electrode 142a are electrically connected The first oxide semiconductor layer 144a is connected to the first oxide semiconductor layer 144a, and the gate insulating film 144b covers the first oxide semiconductor layer 144a. A gate insulating layer 146 and a gate insulating film 147 overlapping the first oxide semiconductor layer 144a on the gate insulating layer 146. and a port electrode 148a.

[0140] The capacitor 164 in FIG. 4A includes a source or drain electrode 142b and a The second oxide semiconductor layer 144b is in contact with the source or drain electrode 142b. The first electrode 148b is in contact with the oxide semiconductor layer 144b. The drain electrode 142 b functions as a second electrode of the capacitor 164 .

[0141] That is, it can be said as follows. The capacitor 164 has a first electrode 148b and The second oxide semiconductor layer 144b and the second electrode are provided. The positive or negative electrode 142a is made of the same conductive layer as the positive or negative electrode 142b.

[0142] In addition, an insulating layer 150 is provided over the transistor 160 and the capacitor 164. do.

[0143] The transistor 160 and the capacitor 164 shown in FIG. 4B are the same as those shown in FIG. 1 is a modified example of the resistor 160 and the capacitive element 164.

[0144] The difference between the configuration shown in FIG. 4(A) and the configuration shown in FIG. 4(B) is that the capacitance element 16 in FIG. In FIG. 4, the source or drain electrode 142b is in contact with the second oxide semiconductor layer 144b. The metal oxide layer 149b is provided on the surface facing the capacitor 164 in FIG. In the example, the first electrode 148b has a metal oxide layer on the surface in contact with the second oxide semiconductor layer 144b. 4B, the drain electrode 141b is provided. Alternatively, a metal oxide layer 142a is formed on the surface where the source electrode 142a contacts the first oxide semiconductor layer 144a. 49a.

[0145] When the second oxide semiconductor layer 144b is in contact with the source or drain electrode 142b, Oxygen is released from the second oxide semiconductor layer 144b by the source or drain electrode 142b. When oxygen is removed from the second oxide semiconductor layer 144b, oxygen vacancies occur. The second oxide semiconductor layer 144b in which the oxygen vacancies are increased has high electrical conductivity, and the capacitance There is a risk that it will no longer function as a dielectric for the element.

[0146] Therefore, a source electrode having a metal oxide layer 149b in contact with the second oxide semiconductor layer 144b is The metal oxide layer 149b is preferably a first electrode or drain electrode 142b. This can prevent oxygen from being taken away from the second oxide semiconductor layer 144b. A drain electrode or a source electrode having a metal oxide layer 149a in contact with an oxide semiconductor layer 144a. The metal oxide layer 149b and the metal oxide layer 149a may be formed. This allows oxygen to be supplied to the second oxide semiconductor layer 144b, The oxygen vacancies in 4b can be further reduced.

[0147] When the second oxide semiconductor layer 144b and the first electrode 148b are in contact with each other, There is a possibility that oxygen is taken away from the second oxide semiconductor layer 144b by the second oxide semiconductor layer 48b. When oxygen is taken away from the compound semiconductor layer 144b, oxygen vacancies increase. The second oxide semiconductor layer 144b becomes highly conductive and does not function as a dielectric of the capacitance element. There is a risk.

[0148] Therefore, the first electrode having the metal oxide layer 141b in contact with the second oxide semiconductor layer 144b is The metal oxide layer 141b is preferably a second oxide semiconductor layer 148b. Therefore, oxygen can be prevented from being taken away from the source electrode or drain electrode 144b by the source electrode or drain electrode 142b. In addition, the gate insulating layer 146 and the gate electrode 148 can be formed at the same time as the metal oxide layer 141b. A metal oxide layer 141a may be formed between the metal oxide layer 141a and the metal oxide layer 141b.

[0149] Note that whether oxygen is removed from the second oxide semiconductor layer 144b depends on the conditions of a subsequent step. When oxygen is not taken away from the second oxide semiconductor layer 144b, the metal The oxide layer 149b and the metal oxide layer 141b may not be formed.

[0150] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the transistor 160 shown in FIG. 4A will be described with reference to FIGS. He explains.

[0151] First, a conductive layer 142 is formed on an insulating layer 140 (see FIG. 5(A)).

[0152] The description in Embodiment 1 can be referred to for the material and structure of the conductive layer 142.

[0153] Next, the conductive layer 142 is processed to form a source or drain electrode 142b and a drain An electrode or source electrode 142a is formed (see FIG. 5(B)).

[0154] Next, an oxide semiconductor layer is formed and processed to form a source electrode or a drain electrode. The in-electrode 142b and the drain or source electrode 142a are electrically connected to each other. The first oxide semiconductor layer 144a is formed as shown in FIG. A second oxide semiconductor layer 144b is formed in contact with the source electrode or drain electrode 142b. (See FIG. 5(C)). At this time, it is preferable to carry out a first heat treatment. Regarding the material and configuration of the body layer and the first heat treatment, the description of the first embodiment can be referred to. can.

[0155] Next, an insulating layer is formed on the first oxide semiconductor layer 144a, and the insulating layer is processed to form a gate. The gate insulating layer 146 is formed (see FIG. 5(D)). The material and the configuration of the gate insulating layer 146 are as follows: Please refer to the description of embodiment 1.

[0156] After the insulating layer is formed, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The heat treatment may be performed in the same manner as the first heat treatment. oxygen is supplied to the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b; The oxygen vacancies in the first oxide semiconductor layer 144a and the second oxide semiconductor layer 144b are filled. As a result, an i-type (intrinsic semiconductor) or substantially i-type oxide semiconductor layer can be formed. .

[0157] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide The semiconductor layer can be highly purified so that it contains as little hydrogen-containing material as possible. .

[0158] In this embodiment, the second heat treatment is performed after the insulating layer is formed. The timing of the step is not limited to this. For example, the insulating layer is processed to form the gate insulating layer 146. Alternatively, the second heat treatment may be performed after the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. It may be allowed.

[0159] The second oxide semiconductor layer 144b may be doped with oxygen. By doping the layer 144b with oxygen, the second oxide semiconductor layer 144b becomes more i-type. The method of oxygen doping can be described in the same manner as in the gate insulating layer of the first embodiment. The descriptions in the above may be taken into consideration.

[0160] Next, the conductive layer 148 is formed (see FIG. 6A). The material and the structure of the conductive layer 148 are as follows: The description in embodiment 1 can be referred to.

[0161] Next, the conductive layer 148 is processed to form the first oxide semiconductor layer 144a on the gate insulating layer 146. A gate electrode 148a is formed so as to overlap with the second oxide semiconductor layer 144. A first electrode 148b is formed on and in contact with b (see FIG. 6B).

[0162] Next, the first electrode 148b, the second oxide semiconductor layer 144b, the gate insulating layer 146, the gate An insulating layer 150 is formed so as to cover the bottom electrode 148a. The material and configuration of the insulating layer 150 are For this embodiment, the description in Embodiment 1 can be referred to (see FIG. 6C).

[0163] Through the above steps, the transistor 160 and the capacitor 164 each using an oxide semiconductor layer are completed. (See FIG. 6(C)).

[0164] Next, a manufacturing method of the transistor 160 shown in FIG.

[0165] First, a conductive layer 142 is formed on an insulating layer 140, and a metal oxide layer is formed on the conductive layer 142. The materials and structures of the conductive layer 142 and the metal oxide layer are the same as those described in Embodiment 1. It is possible.

[0166] Next, the conductive layer 142 and the metal oxide layer are processed to form the source or drain electrode 14 2b, metal oxide layer 149b, drain or source electrode 142a and metal oxide A layer 149a is formed.

[0167] Next, an oxide semiconductor layer is formed and processed to form a source electrode or a drain electrode. The in-electrode 142b and the drain or source electrode 142a are electrically connected to each other. The first oxide semiconductor layer 144a is formed as shown in FIG. Thus, the second oxide semiconductor layer 144b is formed in contact with the metal oxide layer 149b. The description in Embodiment 1 can be referred to for the materials and structures of the semiconductor layers.

[0168] Next, an insulating layer is formed on the first oxide semiconductor layer 144a, and the insulating layer is processed to form a gate. The material and the configuration of the gate insulating layer 146 are the same as those in the first embodiment and the second embodiment. The description of Figure 4(A) can be taken into consideration.

[0169] Next, the first oxide semiconductor layer 144a, the second oxide semiconductor layer 144b, and the conductive layer 1 48, the first oxide semiconductor layer 144a and the second oxide semiconductor layer 14 A metal oxide layer is formed between the first electrode 4b and the conductive layer 148. Materials and Composition of the Metal Oxide Layer Please refer to the description in embodiment 1 for details.

[0170] Next, the conductive layer 148 is formed. The material and the configuration of the conductive layer 148 are the same as those described in the first embodiment. can be taken into consideration.

[0171] The metal oxide layer and conductive layer 148 are then processed to form a first oxide layer on the gate insulating layer 146. The metal oxide layer 141a and the gate electrode 148a are formed so as to overlap the metal semiconductor layer 144a. At the same time, a metal oxide layer 141b and a metal oxide layer 141c are formed in contact with the second oxide semiconductor layer 144b. Then, the first electrode 148b is formed.

[0172] Next, the first electrode 148b, the second oxide semiconductor layer 144b, the gate insulating layer 146, the gate An insulating layer 150 is formed so as to cover the bottom electrode 148a. The material and configuration of the insulating layer 150 are Please refer to the description of embodiment 1.

[0173] Through the above steps, the transistor 160 and the capacitor 164 each using an oxide semiconductor layer are completed. do.

[0174] <Cross-sectional structure of semiconductor device> 7 and 8 are examples of the configuration of a semiconductor device. 7(A) to 8(C) show cross sections of the semiconductor device. The semiconductor devices shown in FIGS. 8A to 8C are transistors using an oxide semiconductor in a channel formation region. A transistor 160 or a transistor 162 and a capacitance element 1 using an oxide semiconductor as a dielectric It has 64.

[0175] The transistor 160 in FIG. 7A includes a gate electrode 14 provided on an insulating layer 140. 8a, a gate insulating layer 146 covering the gate electrode 148a, and a source A drain electrode 142b and a source electrode 142a are connected to the source electrode 142b. On the source or drain electrode 142b and the drain or source electrode 142a A source or drain electrode 142b and a drain or source electrode 142a A first oxide semiconductor layer is electrically connected to and overlaps the gate electrode 148a on the gate insulating layer 146. The transistor 160 has a gate insulating layer 146 and a conductor layer 144a. A source or drain electrode 142b and a drain or source electrode 142a A structure having a metal oxide layer in contact therewith is also possible.

[0176] The capacitor 164 in FIG. 7A includes a first electrode 148b and a second electrode 148c connected to the first electrode 148b. a source electrode in contact with the second oxide semiconductor layer 144b; Here, the source or drain electrode 14 2 b functions as a second electrode of the capacitor 164 .

[0177] That is, it can be said as follows. The capacitor 164 has a first electrode 148b and The second oxide semiconductor layer 144b and the second electrode are provided. The positive or negative electrode 142a is made of the same conductive layer as the positive or negative electrode 142b.

[0178] Note that the capacitor 164 is formed by a combination of the first electrode 148b and the second oxide semiconductor A metal oxide layer may be provided on the surface in contact with the conductor layer 144b. The capacitor 164 has a metal oxide layer on the second oxide semiconductor layer 144b. It is also possible.

[0179] In addition, an insulating layer 150 is provided over the transistor 160 and the capacitor 164. do.

[0180] The transistor 162 and the capacitor 164 shown in FIG. 7B are the same as those shown in FIG. 1 is a modified example of the resistor 160 and the capacitive element 164.

[0181] The difference between the configuration shown in FIG. 7(A) and the configuration shown in FIG. 7(B) is that the transistor 162 is at the point including the electrode 152 on the insulating layer 150. The transistor 162 has a channel Above and below the first oxide semiconductor layer 144a having the formation region, two gate electrodes are provided via an insulating layer. The transistor is a dual-gate transistor having an electrode layer. 162 is a gate electrode 148a, a gate insulating layer 146 on the gate electrode 148a, and a gate A source or drain electrode 142b and a drain electrode or A source electrode 142a, a source electrode or a drain electrode 142b, and a drain electrode or On the source electrode 142a, a source electrode or a drain electrode 142b and a drain electrode or The first oxide semiconductor layer 144a is electrically connected to the source electrode 142a. a drain or source electrode 142a and a first acid An insulating layer 150 is formed on the oxide semiconductor layer, and a first oxide semiconductor layer 144a is overlapped on the insulating layer 150. and an electrode 152.

[0182] In FIG. 7B, the gate electrode 148a and the electrode 152 function together as a gate electrode. The potential of the electrode 152 may be the same as or different from that of the gate electrode 148a. The gate electrode 148a and the gate electrode 148b may be connected to GND, 0V, or may be in a floating state. The electrode 152 controls the electric field applied to the first oxide semiconductor layer 144a. The threshold voltage of the transistor 162 can be controlled.

[0183] The transistor 160 and the capacitor 164 shown in FIG. 8A are the same as those shown in FIG. 1 is a modified example of the resistor 160 and the capacitive element 164.

[0184] The difference between the configuration shown in FIG. 7A and the configuration shown in FIG. 8A is the capacitance element 164. In FIG. 7A, a source electrode or a drain electrode is formed on the first electrode 148b. 8A, a source electrode or drain electrode 142b is provided, whereas in FIG. An electrode 147b is provided on top of electrode 142b.

[0185] The transistor 160 and the capacitor 164 shown in FIG. 8B are the same as those shown in FIG. 1 is a modified example of a resistor 162 and a capacitor element 164.

[0186] The difference between the configuration shown in FIG. 7B and the configuration shown in FIG. 8B is the capacitance element 164. In FIG. 7B, a source electrode or a drain electrode is formed on the first electrode 148b. 8B, a source electrode or drain electrode 142b is provided, whereas in FIG. A first electrode 148b is provided on top of electrode 142b.

[0187] In addition, the transistor 162 has a source electrode or a drain electrode on the gate insulating layer 146. 142b, a metal oxide in contact with the drain or source electrode 142a and the electrode 152 It may also be configured to have layers.

[0188] The transistor 160 in FIG. 8C is a first oxide semiconductor layer provided on the insulating layer 140. A conductor layer 144a and a first oxide semiconductor layer 144a on the first oxide semiconductor layer 144a. The source or drain electrode 142b and the drain electrode or The source electrode 142a, the first oxide semiconductor layer 144a, the source electrode or the drain electrode 1 42b and a gate insulating layer 146 on the drain or source electrode 142a, and A gate electrode 148a is provided on the insulating layer 146 and overlaps with the first oxide semiconductor layer 144a. Note that the transistor 160 has a source electrode and a drain electrode over the first oxide semiconductor layer 144a. The metal oxide layer 141b contacting the drain electrode 142b and the source electrode 142b are A structure including a metal oxide layer 141a in contact with the electrode 142a may also be used.

[0189] The capacitor 164 in FIG. 8C includes the electrode 147b and the second oxide semiconductor layer 144b. and a source or drain electrode 142b. A metal oxide layer is formed on the surface of the electrode 147b where the electrode 147b and the second oxide semiconductor layer 144b are in contact with each other. The capacitor 164 may have a structure including a second oxide semiconductor layer 1 A metal oxide layer may be provided on 44b.

[0190] The transistor 160 and the capacitor 164 in FIG. 8D are the same as those in FIG. 1 is a modified example of the transistor 160 and the capacitance element 164.

[0191] The difference between the configuration shown in FIG. 8(C) and the configuration shown in FIG. 8(D) is that the transformer in FIG. The transistor 160 includes an impurity region 144c and an impurity region 144d in the first oxide semiconductor layer 144a. It is a point having area 144d.

[0192] The impurity region 144c and the impurity region 144d are connected to the source electrode or the drain electrode 142. b. Using the drain or source electrode 142a and the gate electrode 148a as a mask, By injecting impurities through the gate insulating layer 146, it is possible to form the gate insulating layer in a self-aligned manner. Cut.

[0193] Impurities include the V group (group 15) elements nitrogen (N), phosphorus (P), arsenic (As), Antimony (Sb) or the like can be used. In this embodiment, nitrogen is implanted. An example is given below.

[0194] The method of injecting impurities may be ion implantation or ion doping. In the ion implantation method, a source gas is turned into plasma, and the ion species contained in the plasma are The ions are extracted, mass-separated, and accelerated to produce an ion beam. In the ion doping method, a source gas is injected into a plasma. The ion species are extracted from the plasma by the action of a specific electric field. In this method, the electrons are accelerated without being mass-separated and then injected into the workpiece as an ion beam. The desired impurity (here, nitrogen) is implanted using an ion implantation method accompanied by desorption. If an element other than the above (for example, a metal element) is added to the first oxide semiconductor layer 144a, In addition, the ion doping method is more efficient than the ion implantation method in that it has an ion beam. Since the area of ​​the irradiated film can be increased, impurities can be doped by ion doping. By adding this, the tact time can be shortened.

[0195] The nitrogen concentration in the impurity region 144c and the impurity region 144d is 5×10 19 atoms / c m 3 It is preferable that the concentration of nitrogen in the impurity region 144c and the impurity region 144d is more than 1. The elementary concentration is determined by secondary ion mass spectrometry (SIMS). The measurements were made using a spectroscopy.

[0196] The nitrogen concentration in the impurity region 144c and the impurity region 144d is 1×10 2 0 atoms / cm 3 or more and less than 7 atomic %, the impurity region 144c, By performing a heat treatment after the formation of the impurity region 144d, the crystal structure becomes a wurtzite structure. The temperature of the heat treatment is 300°C or higher and 600°C or lower, preferably 350°C or higher and 50°C or lower. It is best to keep it below 0℃.

[0197] As shown in this embodiment, impurity implantation is performed through the gate insulating layer 146. This can reduce excessive damage to the first oxide semiconductor layer 144a.

[0198] In this embodiment, the method of introducing impurities through the gate insulating layer 146 is described below. However, the present invention is not limited to this. For example, impurity injection through an insulating layer to be formed later may be used. Input processing may be performed.

[0199] In this manner, in the first oxide semiconductor layer 144a, the channel formation region is sandwiched between the insulators. By providing the pure region, the impurity region has a higher energy gap than the channel formation region. Therefore, a transistor with this structure is This allows information to be written at high speed.

[0200] In addition, by providing impurity regions on either side of the channel forming region, This structure alleviates the electric field concentration.

[0201] The impurity regions 144c and 144d are formed by injecting impurities into the first Since the resistance of the oxide semiconductor layer 144a is low, it is called a low-resistance region (also called an n-type region). It is also possible.

[0202] In FIG. 8D, the oxide semiconductor has a low-resistance region (an impurity region 144c and an impurity region 144d). Although a method for forming the region 144d) has been described above, In the present invention, the impurity regions which function as source regions or drain regions are self-aligned. As one method for manufacturing the oxide semiconductor layer, the surface of the oxide semiconductor layer is exposed and then argon-precipitated. A plasma treatment is performed to reduce the resistivity of the region of the oxide semiconductor layer exposed to the plasma. A method for achieving this has been disclosed (S. Jeon et al. "180 nm Gate Linearization" in ength Amorphous InGaZnO Thin Film Transi stor for High Density Image Sensor Appli cation”, IEDM Tech. Dig., p.504, 2010.).

[0203] However, in the above-mentioned manufacturing method, after forming the gate insulating layer, the source region or the drain region is It is necessary to partially remove the gate insulating layer to expose what will become the gate region. Therefore, when the gate insulating layer is removed, the underlying oxide semiconductor layer is also partially over-etched. As a result, the thickness of the portion that is to become the source region or drain region becomes smaller. This results in increased resistance in the source or drain regions and over-etching. This makes the transistor more susceptible to defective characteristics.

[0204] To advance miniaturization of transistors, it is necessary to adopt dry etching methods with high processing accuracy. However, the overetching is performed because the selectivity between the oxide semiconductor layer and the gate insulating layer is low. This is particularly likely to occur when a dry etching method in which sufficient space cannot be secured is used.

[0205] For example, if the oxide semiconductor layer is thick enough, over-etching is not a problem. In the case where the channel length is set to 200 nm or less, the channel length is set to 100 nm or less in order to prevent the short channel effect. The thickness of the oxide semiconductor layer in the portion that becomes the hole formation region is 20 nm or less, and preferably 10 nm or less. When dealing with such a thin oxide semiconductor layer, it is necessary to Overetching of the layer may result in increased resistance of the source or drain regions, as discussed above. In addition, this is undesirable because it causes defects in the characteristics of the transistor.

[0206] However, as in the present embodiment, the injection of impurities into the oxide semiconductor layer is performed by By leaving the gate insulating layer unexposed, the oxide semiconductor layer is not over-etched. This can prevent the oxide semiconductor layer from being damaged and reduce excessive damage to the oxide semiconductor layer. The characteristics and reliability of the transistor can be improved.

[0207] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible.

[0208] (Embodiment 3) In this embodiment, a memory configured using the semiconductor device according to the first and second embodiments is An example of the recell 170 is shown in FIG.

[0209] Memory Cell Configuration FIG. 9A is a cross-sectional view of the memory cell 170, FIG. 9B is a top view of the memory cell 170, FIG. 9C shows a circuit diagram of the memory cell 170.

[0210] 9(A) and 9(B) show a semiconductor device corresponding to FIG. 1(A), but according to the present invention One embodiment is not limited to this. Alternatively, the configuration of another semiconductor device having a similar function may be applied. .

[0211] The memory cell 170 shown in FIGS. 9A, 9B, and 9C includes a transistor 160 and It has a capacitance element 164 .

[0212] In the memory cell 170 shown in FIG. The source electrode 142a is disposed through an opening in the insulating layer 150 and the insulating layer 154. It is electrically connected to the line 156. In FIG. 9A, the insulating layer 150 and the insulating layer 1 54 is laminated, but is not limited to this. Alternatively, only one layer may be provided.

[0213] In the memory cell 170 shown in FIG. 9C, a first wiring (also called a bit line BL) and a The second transistor 160 is electrically connected to one of the source electrode and the drain electrode. The wiring (also called the word line WL) and the gate electrode of the transistor 160 are electrically connected. The other of the source electrode or the drain electrode of the transistor 160 is connected to A third wiring (also referred to as a capacitance line CL) is electrically connected to one of the electrodes of the capacitor 164. ) is electrically connected to the other electrode of the capacitor 164.

[0214] Here, the transistor 160 is formed using the oxide semiconductor described in Embodiments 1 and 2. The transistor using the oxide semiconductor described in the first and second embodiments is applied. The off-state current of the transistor is extremely small. By turning off the capacitor 60, the potential applied to the capacitor 164 can be maintained for an extremely long time. Note that the transistor 160 including an oxide semiconductor can be The channel length (L) is set to 10 nm or more and 1000 nm or less, so power consumption is small and It also has the advantage of being extremely fast.

[0215] In addition, the capacitor 164 uses the oxide semiconductor described in the first and second embodiments as a dielectric. Since the oxide semiconductor has a high dielectric constant, the dielectric constant of the capacitor 164 is By using the capacitor 164 as a gate insulating film, the capacitance per unit area of ​​the capacitor 164 can be increased.

[0216] The semiconductor device shown in FIG. 9C has a feature that a potential applied to the capacitor 164 can be held. By utilizing this characteristic, it is possible to write, retain, and read information as follows.

[0217] First, we will explain how to write and store information. For simplicity, we will use the third arrangement. The potential of the second wiring is fixed. This sets the potential at which the first transistor 160 is turned on, thereby turning on the first The potential of the wiring is applied to one of the electrodes of the capacitor 164. A predetermined charge is applied to the second wiring (write). By setting the potential at which the transistor 160 is turned off, the transistor 160 is turned off. The charge applied to the capacitor 164 is held (retained). As described above, the off-state current is extremely small, so that the charge can be retained for a long period of time.

[0218] Next, the reading of information will be described. In this state, when the potential of the second wiring is set to a potential at which the transistor 160 is turned on, The first wiring has a different potential depending on the amount of charge held in the capacitor 164. By monitoring the potential of the first wiring, the stored data can be read out.

[0219] When information is read, the charge of the capacitance element 164 is lost, so that the charge is not rewritten. It is important to note that the following will be carried out:

[0220] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the second wiring is held in the same manner as when the transistor 160 is turned on. This causes the transistor 160 to be turned on. (a potential related to new data) is applied to one electrode of the capacitor 164. The potential of the wiring is set to a potential at which the transistor 160 is turned off. By turning off the capacitor 164, the capacitor 164 is in a state where a charge related to new information is provided. It becomes a posture.

[0221] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information, which allows the semiconductor device to operate at high speed.

[0222] The above explanation is for n-type transistors (n-channel transistors) that use electrons as carriers. ) is used, but instead of n-type transistors, Needless to say, a p-type transistor can be used.

[0223] (Embodiment 4) In this embodiment, a semiconductor device configured using the semiconductor device according to any one of the first to third embodiments is The configuration of the device will be described with reference to FIGS.

[0224] (Configuration of Semiconductor Device) FIG. 10A is a conceptual diagram illustrating an example of a structure of a semiconductor device according to one embodiment of the present invention. The semiconductor device has a memory circuit in the upper part and requires high speed operation to drive the memory circuit in the lower part. The semiconductor device has a multilayer structure and includes peripheral circuits such as a driver circuit and a control circuit. The operating circuit and the control circuit may be a logic circuit or may have an analog circuit. The signal processing circuit may also include an arithmetic circuit.

[0225] The semiconductor device shown in FIG. 10A is a memory device having a plurality of memory cells as a memory circuit in the upper portion. The rechargeable battery has a rechargeable battery array 201, and a first driving circuit 211, a second driving circuit 212, and a third driving circuit 213 at the bottom. A third driving circuit 213, a fourth driving circuit 214, a fifth driving circuit 215, and a controller 21 8, the memory cell array 201 including the address buffer 221, the I / O buffer 220, etc. The first driver circuit 211 is a column driver. The second driver circuit 212 includes a column decoder 217a and a sense amplifier group 216a. The memory cell 210 includes a sense amplifier group 217b and a sense amplifier group 216b.

[0226] The substrate on which the peripheral circuit 210 shown in FIG. 10A is provided is, for example, a substrate made of silicon or gel. Semiconductor substrates made of the 14th element, such as arsenic, silicon germanium, silicon carbide, etc. In addition, compound semiconductor substrates such as gallium arsenide and indium phosphide, and SOI substrates can be used. Generally, an "SOI substrate" is a structure in which a silicon layer is provided on an insulating surface. In this specification, however, it refers to a semiconductor substrate made of a material other than silicon on an insulating surface. The term "SOI substrate" also includes substrates having a conductor layer. This includes a structure in which a semiconductor layer is provided on an insulating substrate via an insulating layer. By forming the peripheral circuit 210 using the above-mentioned substrate, the peripheral circuit 210 can be operated at high speed. This is preferable because it allows the

[0227] <Cross-sectional structure of semiconductor device> FIG. 10B is a cross-sectional view of the semiconductor device. The semiconductor device shown in FIG. The upper part of the memory cell array 201 has a peripheral circuit 210. In the example shown in FIG. 1, a transistor 160 using an oxide semiconductor is provided, and a peripheral circuit 210 in the lower part is provided using an oxide semiconductor. The semiconductor device includes a transistor 159 using a semiconductor material other than a nitride semiconductor. For details of the memory cell 170 provided in the upper portion, see the first to third embodiments. The description can be taken into consideration.

[0228] The transistor 159 and the transistor 160 are an n-channel transistor and a p-channel In this example, transistor 159, transistor The transistors 160 will be described as n-channel transistors. In one embodiment, the technical essence is to use an oxide semiconductor or the like to maintain an off-state current in order to retain information. The transistor 160 and the capacitor 164 are made of a semiconductor material that can be sufficiently reduced in size. Therefore, the semiconductor device is characterized by the fact that the materials used in the semiconductor device and the structure of the semiconductor device are The specific configuration need not be limited to that shown here.

[0229] The transistor 159 is provided on a substrate 100 that includes a semiconductor material (such as silicon). A channel forming region 116 is formed by arranging impurity layers 116 so as to sandwich the channel forming region 116. A region 120, a metal compound region 124 in contact with the impurity region 120, and a channel forming region 1 A gate insulating layer 108 is provided on the gate insulating layer 108. A source or drain electrode 110 electrically connected to the metal compound region 124 30b, and a drain or source electrode 130a. An insulating layer 128 is provided to cover the source or drain electrode 130. b. The drain or source electrode 130a is connected to the insulating layer 128 through an opening. , electrically connected to the metal compound region 124. Also, on the insulating layer 128, An electrode 136a is formed in contact with the drain electrode 130b, and a drain electrode An electrode 136b is formed in contact with the source electrode 130a.

[0230] In addition, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 159. In order to achieve high integration, the transistors are It is preferable that the transistor 159 does not have a sidewall insulating layer. When the characteristics of the gate electrode 159 are important, a sidewall insulating layer is formed on the side of the gate electrode 110. a region having a different impurity concentration formed in a region overlapping the sidewall insulating layer; The impurity region 120 may be provided including the above.

[0231] The transistor 160 in FIG. 10B includes the transistor described in any of Embodiments 1 to 3. A transistor 160 or a transistor 162 can be used.

[0232] The capacitor 164 described in any of Embodiments 1 to 3 is used as the capacitor 164. It is possible.

[0233] An insulating layer 150 and an insulating layer 154 are provided on the transistor 160 and the capacitance element 164. The drain electrode or source electrode 142a of the transistor 160 is connected to the The wires 156 are electrically connected through openings formed in the insulating layers 150, 154, etc. The wiring 156 is a wiring that electrically connects one memory cell to another memory cell. The wiring 156 is connected to the drain or source electrode 142a, the electrode 126, and This electrically connects the lower peripheral circuit 210 and the electrode 130c through the , and can be electrically connected to the memory cell array 201 in the upper layer.

[0234] In the semiconductor device shown in FIG. 10B, the memory cell array 201 in the upper part and the peripheral circuit An insulating layer 140 is provided between the path 210 .

[0235] The transistor 159 is formed using a semiconductor material other than an oxide semiconductor. Examples of semiconductor materials other than silicon include silicon, germanium, and silicon germanium. , silicon carbide, gallium arsenide, etc., and a single crystal semiconductor is used. It is preferable to use an organic semiconductor material. The transistor can operate at a sufficiently high speed. Various circuits that require high-speed operation due to the transistors used (logic circuits, driver circuits, etc.) It is possible to preferably realize the above.

[0236] On the other hand, an oxide semiconductor material is used in the transistor 160. A transistor using the oxide semiconductor material shown in the present invention can have an extremely low off-state current. This characteristic allows memory cell 170 to retain its stored contents for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operations to be reduced significantly, resulting in reduced power consumption. In addition, even if there is no power supply (although it is preferable that the potential is fixed), It is possible to retain the stored contents for a long period of time.

[0237] In addition, the above-mentioned oxide semiconductor is used as a dielectric for the capacitor 164. Since an oxide semiconductor has a high dielectric constant, the capacitance can be increased by using the oxide semiconductor as the dielectric of the capacitor 164. The capacitance per unit area of ​​the element 164 can be increased.

[0238] In this way, transistors using materials other than oxide semiconductors (transistors using oxide semiconductors) The peripheral circuits, such as driver circuits, use transistors (which can operate at higher speeds than conventional transistors), and oxide A transistor using a nitride semiconductor (or, more broadly, a transistor with a sufficiently low off-state current) ) and a memory circuit including a capacitor using an oxide semiconductor. It is possible to realize a semiconductor device having never before seen features.

[0239] In FIG. 10, one layer of memory cell array 201 is stacked on peripheral circuit 210. 11 and 12 show an example in which the ion exchange film 10 is inserted into the ion exchange film 10, but the embodiment of the present invention is not limited to this. As shown, two or more memory cell arrays may be stacked.

[0240] 11 and 12 are cross-sectional views of a storage device. The semiconductor memory device has a plurality of memory cells formed in multiple layers, and a peripheral circuit 304 at the bottom. Of the memory cells, memory cell 370a and memory cell 370b are shown as representatives.

[0241] Note that the transistor 371a and the capacitor 372a included in the memory cell 370a are replaced with The table shows the transistor 371b and the capacitor 372b included in the memory cell 370b. The transistor 371a and the transistor 371b are each formed in an oxide semiconductor layer. The transistor has a channel formed in an oxide semiconductor layer. The configuration of the register is the same as that described in the other embodiments. The capacitor elements 372a and 372b are made of an oxide semiconductor as a dielectric. Regarding the capacitance element that uses an oxide semiconductor as a dielectric, Since the configuration is the same as that described in the other embodiments, the description will be omitted.

[0242] An electrode 351a formed in the same layer as the source and drain electrodes of the transistor 371a The transistor 37 is electrically connected to the electrode 303a via the electrode 352a. The electrode 351c formed in the same layer as the source electrode and drain electrode of 1b is an electrode 352c. 3, which is electrically connected to electrode 303c.

[0243] In addition, the peripheral circuit 304 uses a semiconductor material other than an oxide semiconductor for a channel formation region. The transistor 301 is made of a semiconductor material (e.g., silicon An element isolation insulating layer 306 is provided on a substrate 300 including the above-mentioned elements, and the element isolation insulating layer 306 surrounds the substrate 300. A transistor can be obtained by forming a channel region in the region. The transistor 301 can be formed on a semiconductor layer such as a silicon layer on an insulating surface. Alternatively, the transistor may have a channel formed in the silicon layer of the SOI substrate. The configuration of the transistor 301 can be a known configuration, so the description will be omitted. Omitted.

[0244] Between the layer in which the transistor 371a is formed and the layer in which the transistor 301 is formed, The wiring 310a and the transistor 301 are formed. An insulating layer 340a is provided between the wiring 310a and the wiring 310b. An insulating layer 341a is provided between them, and a wiring 310b and a transistor 371a are formed. An insulating layer 342a is provided between the layers.

[0245] Similarly, a layer in which the transistor 371b is formed and a layer in which the transistor 371a is formed Between the wiring 310c and the transistor, a wiring 310c and a wiring 310d are formed. An insulating layer 340b is provided between the layer on which the stator 371a is formed and the wiring 310c and the wiring An insulating layer 341b is provided between the wiring 310d and the transistor 371. An insulating layer 342b is provided between the layer on which b is formed.

[0246] Insulating layer 340a, insulating layer 341a, insulating layer 342a, insulating layer 340b, insulating layer 341b, The insulating layer 342b functions as an interlayer insulating layer, and the surface thereof is preferably flattened. can.

[0247] The wiring 310a, the wiring 310b, the wiring 310c, and the wiring 310d are used to connect the memory cells to each other. It is possible to perform an electrical connection between the peripheral circuit 304 and the memory cells, and an electrical connection between the peripheral circuit 304 and the memory cells.

[0248] The electrodes 303 included in the peripheral circuit 304 are electrically connected to the circuit provided above. can be done.

[0249] For example, as shown in FIG. 11, the electrode 303 is electrically connected to the wiring 310a by the electrode 355. The wiring 310a can be electrically connected to the electrode 351b via the electrode 353a. The electrode 351b is formed in the same layer as the transistor 371a. Although not shown, the transistor 371a or the capacitor 372a may be electrically connected to the In addition, the electrode 351b is electrically connected to the wiring 353b via the electrode 352b. The wiring 353b can be electrically connected to the wiring 310c via the electrode 303b. This can be done.

[0250] In FIG. 11, the electrode 303 and the transistor 371a are electrically connected to each other through a wiring 310a. However, the present invention is not limited to this. The electrical connection may be made via the wiring 310b, or via both the wiring 310a and the wiring 310b. Alternatively, as shown in FIG. 12, the electrode 303 and the transistor 37 The electrical connection with 1a may be made without the wiring 310a or 310b. The electrode 303 is electrically connected to the wiring 353b via the electrode 353. 353b is electrically connected to the source or drain of the transistor 371a. As a result, electrical connection can be established between the electrode 303 and the transistor 371a.

[0251] 11 and 12, two memory cells (memory cell 370a and memory cell 3 70b) is shown as an example of a stacked configuration, but the number of stacked memory cells is not limited to this. I can't.

[0252] 11 and 12, a layer in which the transistor 371a is formed and a layer in which the transistor 3 Between the layer in which 01 is formed, there is a wiring layer in which the wiring 310a is formed and a wiring layer in which the wiring 310b is formed. The present invention is not limited to a configuration in which two wiring layers are provided, but the present invention is not limited to this. Between the layer in which the transistor 371a is formed and the layer in which the transistor 301 is formed, Alternatively, one wiring layer may be provided, or three or more wiring layers may be provided.

[0253] 11 and 12, a layer in which the transistor 371b is formed and a layer in which the transistor 3 Between the layer in which 71a is formed, there is a wiring layer in which the wiring 310c is formed and a wiring 310d is formed. Although the configuration in which two wiring layers are provided with the formed wiring layer is shown, the present invention is not limited to this. Between the layer in which the transistor 371b is formed and the layer in which the transistor 371a is formed In addition, one wiring layer may be provided, or three or more wiring layers may be provided.

[0254] (Embodiment 5) In this embodiment, the semiconductor device described in the above embodiment is applied to a mobile phone, a smartphone, An example of application to a portable device such as an electronic book will be described with reference to FIGS.

[0255] In mobile devices such as mobile phones, smartphones, and e-books, image data is temporarily stored. SRAM or DRAM is used in the following. SRAM or DRAM is used The reason is that flash memory has a slow response time and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed: .

[0256] In a normal SRAM, one memory cell is made up of transistors 401 to 404 as shown in FIG. It is composed of six transistors, X decoder 407 and Y decoder 408. The transistor 403 and the transistor 405 are driven by the transistor 408. 4 and transistor 406 form an inverter, enabling high-speed operation. The memory cell is composed of six transistors, so the cell area is large. When the minimum dimension of the design rule is F, the area of ​​the SRAM memory cell is usually 100 ~150F 2 For this reason, SRAM has the highest cost per bit among all types of memory. There is a problem.

[0257] On the other hand, in a DRAM, the memory cell is made up of a transistor 411, The capacitor element 412 is connected to the X decoder 413 and the Y decoder 414. Each cell is composed of one transistor and one capacitance, and has a small area. The memory cell area of ​​a DRAM is usually 10F 2 However, DRAM is always refreshed. The problem is that the memory requires a flash memory, and power consumption occurs even if the memory is not rewritten. do.

[0258] However, the memory cell area of ​​the semiconductor device described in the above embodiment is 10F 2 Before and after And frequent refreshing is not required. Therefore, the area is small and the power consumption is low. It may be a reduced memory cell.

[0259] Next, Fig. 14 is a block diagram of a portable device. The portable device shown in Fig. 14 includes an RF circuit 501, Analog baseband circuit 502, digital baseband circuit 503, battery 504 , a power supply circuit 505, an application processor 506, a flash memory 510, A spray controller 511, a memory circuit 512, a display 513, a touch sensor 5 19, audio circuit 517, keyboard 518, etc. Display 513 is composed of a display unit 514, a source driver 515, and a gate driver 516. The application processor 506 includes a CPU 507, a DSP 508, and an interface 509 (IF509). Generally, the memory circuit is composed of SRAM or DRAM. However, the semiconductor device described in the previous embodiment can be used for the memory circuit 512. This allows for high-speed writing and reading of information and reduced power consumption in portable devices. It can be said that:

[0260] Next, FIG. 15 shows a semiconductor device according to the above embodiment that is incorporated in a memory circuit 600 of a display. The memory circuit 600 shown in FIG. It is composed of a switch 604, a switch 605 and a memory controller 601. The semiconductor device described in the previous embodiment is applied to the memory 602 and the memory 603. .

[0261] First, certain image data is generated by an application processor (not shown). The formed image data (input image data 1) is input to the memory via the switch 604. The image data stored in the memory 602 (stored image data 1) is connected to a display 607 via a switch 605 and a display controller 606. and displayed.

[0262] If there is no change in the input image data 1, the stored image data 1 is usually at a frequency of about 30 to 60 Hz. The display controller 606 reads the data from the memory 602 via the switch 605. It is revealed.

[0263] Next, for example, when the user rewrites the screen (i.e., the input image data If there is a change, the application processor receives the new image data (input image data 2 The input image data 2 is stored in the memory 603 via the switch 604. During this time, the stored image data 1 is periodically read out from the memory 602 via the switch 605. When the new image data (stored image data 2) is completely stored in the memory 603, From the next frame of the display 607, the stored image data 2 is read out, and the switch 605 , and via a display controller 606, the stored image data is displayed on a display 607. 2 is sent and displayed. This readout is followed by the next new image data being sent to the memory. This continues until the data is stored in 602.

[0264] In this way, the memory 602 and the memory 603 alternately write and read data. The display 607 is displayed by reading out the data from the memory 602. The memory 603 is not limited to being separate memories, but may be a single memory divided and used. The semiconductor device described in the above embodiment may be used for the memory 602 and the memory 603. By using this technology, information can be written and read at high speed and power consumption is reduced. The display may be a display having a display.

[0265] Next, FIG. 16 is a block diagram of an electronic book. The electronic book shown in FIG. , power supply circuit 702, microprocessor 703, flash memory 704, audio circuit 70 5, keyboard 706, memory circuit 707, touch panel 708, display 709, The display controller 710 is configured as the semiconductor device described in the previous embodiment. The device can be used with a memory circuit 707. The memory circuit 707 temporarily stores the contents of the book. An example of a function that temporarily holds the contents of an e-book is For example, when a user is reading an e-book, the user may want to use the highlight function. In such a case, it is necessary to mark a specific part. The e-book has a highlight function that allows you to change the display color, underline, and By making the text bold or changing the font, you can differentiate it from the surroundings. The highlight function is a function that remembers and retains information about the areas specified by the user. If this information is to be stored for a longer period of time, it may be copied to flash memory 704. Even in such a case, the semiconductor device described in the above embodiment can be used. This allows for high-speed writing and reading of information and consumes less power, making it an electronic book. It is possible.

[0266] (Embodiment 6) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 17. In this embodiment, Telephones, mobile phone devices, portable information terminals (including portable game consoles, audio playback devices, etc.) (including digital cameras, digital video cameras, and other cameras, electronic paper, televisions, etc.) The above-mentioned semiconductors are used in electronic devices such as televisions and television receivers. A case where the device is applied will be described.

[0267] FIG. 17A shows a notebook personal computer, which includes a housing 801, a housing 802, The display unit 803 and the keyboard 804 are included. At least one of the semiconductor devices is provided. A notebook-type personal computer with high-speed data writing and reading and low power consumption. The computer is realized.

[0268] FIG. 17B shows a tablet terminal 810. The tablet terminal 810 has a display unit 8 12, a housing 813 having a display unit 814, and an operation button 815, The tablet terminal 810 has an external interface 816. The housing 811 and the housing 813 are provided with electronic circuits. The electronic circuit is provided with the semiconductor device described in the above embodiment. Tablet-type devices that can write and read information quickly and consume less power are becoming available. It will be realized.

[0269] FIG. 17C shows an electronic book 820 equipped with electronic paper. The electronic book 820 is made up of a housing 821 and a housing 822. The display device 8 is configured with two housings, housing 821 and housing 823. 25 and a display unit 827 are provided. The housing 821 and the housing 823 are connected by a shaft portion 837. The housing 8 is connected to the housing 8 via the shaft 837, and can be opened and closed around the shaft 837. 21 includes a power source 831, operation keys 833, a speaker 835, etc. At least one of the housings 823 is provided with the semiconductor device described in the above embodiment. This allows for high-speed writing and reading of information, while consuming less power. is realized.

[0270] FIG. 17D shows a mobile phone that is composed of two housings, a housing 840 and a housing 841. Furthermore, the housing 840 and the housing 841 slide and unfold as shown in FIG. 17(D). It can be folded up and folded up, making it possible to make it compact and suitable for carrying. The housing 841 also includes a display panel 842, a speaker 843, a microphone 844, and an operation Key 845, pointing device 846, camera lens 847, external connection terminal 84 The housing 840 also includes a solar cell 849 for charging the mobile phone. , an external memory slot 850, etc. Also, the antenna is built into the housing 841. At least one of the housing 840 and the housing 841 is provided with the semiconductor device shown in the previous embodiment. This allows for high-speed writing and reading of information while also reducing power consumption. Thus, a mobile phone with reduced noise is realized.

[0271] FIG. 17E shows a digital camera, which includes a main body 861, a display unit 867, an eyepiece unit 863, and an operation unit. The device is made up of an operation switch 864, a display unit 865, a battery 866, etc. The semiconductor device described in the above embodiment is provided in the inside of 861. A digital camera with high speed writing and reading and low power consumption is realized. .

[0272] FIG. 17F shows a television device 870, which includes a housing 871, a display unit 873, a stand, and the like. The television device 870 is operated by a switch provided in the housing 871. The housing 871 and the remote control 880 can be used. The semiconductor device described in the above embodiment is mounted on the device 880. A television device with high speed writing and reading and reduced power consumption is realized. can be.

[0273] As described above, the electronic device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This makes it possible to realize electronic devices with reduced power consumption.

[0274] In the following Examples 1 and 2, an oxide semiconductor layer was actually fabricated and its relative dielectric constant was measured. The results of the determination will be explained with reference to FIGS. 18 to 20. EXAMPLES

[0275] As shown in FIG. 18A, an oxide semiconductor (referred to as OS in the figure) is formed on a p-type silicon substrate. In this example, an oxide semiconductor layer was formed at 100 nm, and its CV (capacitance and voltage) was measured. The conductor used was an In-Sn-Zn-O oxide. The oxide semiconductor layer was formed by sputtering using an oxide target with a 1:3 (atomic ratio). From the CV measurement results, the storage capacitance (C0) (see FIG. 18(B)) was calculated. The dielectric constant was calculated from the storage capacitance (C0) using Equation 1. Let the electric permittivity be ε, the dielectric constant of a vacuum be ε0, the area be S, and the relative dielectric constant be d.

[0276]

number

[0277] Figure 19 shows the CV measurement results. The horizontal axis shows the applied voltage and the vertical axis shows the capacitance. = 7. As a result of the calculation, the oxide target with In:Sn:Zn = 2:1:3 (atomic ratio) The relative dielectric constant (d) of the oxide semiconductor layer formed using this was about 20. EXAMPLES

[0278] In this embodiment, an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1 is used. Using an In-Ga-Zn-O oxide target, the same process as in Example 1 was carried out. The relative dielectric constant was measured.

[0279] Figure 20 shows the CV measurement results. The number of samples is n=5. As a result of calculation, In:Ga:Z Ratio of oxide semiconductor layer formed using an oxide target with n=1:1:1 (atomic ratio) The dielectric constant (d) was about 15.

[0280] From the results of Example 1 and Example 2, it was found that the oxide semiconductor layer had a relative dielectric constant of about 4. It was shown that the thermal conductivity was sufficiently high compared to that of silicon oxide, which is [Explanation of symbols]

[0281] 100 Substrates 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Gate electrode 116 Channel formation region 120 Impurity region 124 Metal compound area 126 electrode 128 Insulating Layer 130a Drain electrode or source electrode 130b Source electrode or drain electrode 130c electrode 136a electrode 136b Electrode 140 Insulating layer 141a Metal oxide layer 141b Metal oxide layer 142 Conductive Layer 142a Drain or source electrode 142b Source or drain electrode 144a First oxide semiconductor layer 144b Second oxide semiconductor layer 144c impurity region 144d Impurity region 146 Gate Insulation Layer 147b Electrode 148 Conductive Layer 148a Gate electrode 148b First electrode 149a Metal oxide layer 149b Metal oxide layer 150 Insulating layer 152 Electrode 154 Insulating Layer 156 Wiring 159 Transistor 160 Transistors 162 Transistor 164 Capacitive element 170 memory cells 201 Memory cell array 210 Peripheral circuits 211 Drive circuit 212 Drive circuit 213 Drive circuit 214 Drive circuit 215 Drive circuit 216a Sense Amplifiers 216b Sense Amplifiers 217a Column Decoder 217b Column Decoder 218 Controller 220 I / O buffers 221 Address Buffer 300 Substrates 301 Transistor 303 Electrode 303a electrode 303b electrode 303c electrode 304 Peripheral Circuits 306 Element isolation insulating layer 310a Wiring 310b Wiring 310c wiring 310d Wiring 340a Insulating layer 340b Insulating layer 341a Insulating layer 341b Insulating layer 342a Insulating layer 342b Insulating layer 351a electrode 351b electrode 351c electrode 352a electrode 352b electrode 352c electrode 353 Electrode 353a electrode 353b Wiring 355 Electrode 370a Memory Cell 370b Memory Cell 371a Transistor 371b Transistor 372a Capacitive element 372b Capacitive element 401 Transistor 402 Transistor 403 Transistor 404 Transistor 405 Transistor 406 Transistor 407 X Decoder 408 Y Decoder 411 Transistor 412 Capacitive element 413 X Decoder 414 Y decoder 501 RF circuit 502 Analog Baseband Circuit 503 Digital Baseband Circuit 504 Battery 505 Power supply circuit 506 Application Processor 507 CPU 508 DSP 509 Interface 510 Flash Memory 511 Display Controller 512 Memory Circuit 513 Display 514 Display section 515 Source Driver 516 Gate Driver 517 Audio Circuit 518 Keyboard 519 Touch Sensor 600 Memory Circuit 601 Memory Controller 602 Memory 603 Memory 604 Switch 605 Switch 606 Display Controller 607 Display 701 Battery 702 Power supply circuit 703 Microprocessor 704 Flash Memory 705 Audio Circuit 706 Keyboard 707 Memory Circuit 708 Touch Panel 709 Display 710 Display Controller 801 Case 802 Case 803 Display section 804 Keyboard 810 Tablet PC 811 Case 812 Display section 813 Case 814 Display section 815 Operation button 816 External Interface 817 Stylus 820 e-books 821 Case 823 Case 825 Display section 827 Display section 831 Power supply 833 Operation Key 835 Speaker 837 Shaft 840 Case 841 Case 842 Display Panel 843 Speaker 844 Microphone 845 Operation Key 846 Pointing Device 847 Camera Lenses 848 External connection terminal 849 Solar Cells 850 external memory slot 861 Main unit 863 Eyepiece 864 Operation switch 865 Display section 866 Battery 867 Display section 870 Television Equipment 871 Case 873 Display section 875 Stand 880 Remote Controlled Device

Claims

1. A first conductive layer; and a first oxide semiconductor layer having a region on the first conductive layer; a second oxide semiconductor layer having a region on the first conductive layer; a first insulating layer having a region on the first oxide semiconductor layer; a second conductive layer having an area on the first insulating layer; a third conductive layer having a region on the second oxide semiconductor layer, the first oxide semiconductor layer contains In, the second oxide semiconductor layer contains In, the first oxide semiconductor layer has a channel formation region of a transistor, the second conductive layer has a region overlapping with the first oxide semiconductor layer with the first insulating layer interposed therebetween; the second conductive layer has a region that functions as a gate electrode of the transistor, the first oxide semiconductor layer has a region overlapping with a first region of the first conductive layer; the first oxide semiconductor layer is electrically connected to the first conductive layer; the second oxide semiconductor layer has a region overlapping with a second region of the first conductive layer; the third conductive layer has a region overlapping with the second region through the second oxide semiconductor layer and without a conductive layer; the third conductive layer has a region that functions as an electrode of a capacitor element, the third conductive layer has a region that overlaps with the second region and is not in contact with an insulating layer that is formed simultaneously with the first insulating layer, The first conductive layer comprises molybdenum, titanium, or copper.

2. A first conductive layer; and a first oxide semiconductor layer having a region on the first conductive layer; a second oxide semiconductor layer having a region on the first conductive layer; a first insulating layer having a region on the first oxide semiconductor layer; a second conductive layer having an area on the first insulating layer; a third conductive layer having a region on the second oxide semiconductor layer, the first oxide semiconductor layer contains In, the second oxide semiconductor layer contains In, the first oxide semiconductor layer has a channel formation region of a transistor, the second conductive layer has a region overlapping with the first oxide semiconductor layer with the first insulating layer interposed therebetween; the second conductive layer has a region that functions as a gate electrode of the transistor, the first oxide semiconductor layer has a region overlapping with a first region of the first conductive layer; the first oxide semiconductor layer is electrically connected to the first conductive layer; the second oxide semiconductor layer has a region overlapping with a second region of the first conductive layer; the third conductive layer has a region overlapping with the second region through the second oxide semiconductor layer and without a conductive layer; the third conductive layer has a region that functions as an electrode of a capacitor element, the third conductive layer has a region that does not overlap with an insulating layer formed simultaneously with the first insulating layer in a plan view; The first conductive layer comprises molybdenum, titanium, or copper.

3. In claim 1 or 2, The first conductive layer has a region overlapping with the second conductive layer.

4. In any one of claims 1 to 3, the first oxide semiconductor layer contains Ga and Zn, The second oxide semiconductor layer contains Ga and Zn.

Images