Semiconductor Device

Abstract

To enable further miniaturization of a semiconductor device.SOLUTION: A manufacturing method for a semiconductor device includes the steps of forming a recess in an upper part of a gate trench portion having a gate conductive portion formed of a conductive material and a gate insulating film insulating the gate conductive portion from a semiconductor substrate, forming a first insulating film on the semiconductor substrate so as to fill the recess, and forming a second insulating film on the first insulating film, and further includes the steps of etching the first insulating film while leaving at least a portion of a portion formed above an upper surface of the semiconductor substrate, forming a tapered side surface in the second insulating film, and forming a first electrode provided above the upper surface of the semiconductor substrate and in contact with the tapered side surface, and after the step of forming the first electrode, a lower end of the tapered side surface comes into contact with the first insulating film.SELECTED DRAWING: Figure 18a

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices such as insulated gate bipolar transistors (IGBTs) have been known (see, for example, Patent Documents 1 and 2). Patent Document 1: JP 2015-135982 A Patent Document 2: JP 2015-070192 A Summary of the Invention [Problem to be solved by the invention]

[0003] In semiconductor devices, further miniaturization is preferred. [Means for solving the problem]

[0004] In a first aspect of the present invention, A semiconductor device is provided that includes a semiconductor substrate having a trench portion in which a conductive portion is provided. The semiconductor device may include a first insulating film in contact with an upper surface of the trench portion and an upper surface of the semiconductor substrate, a second insulating film made of a different material from the first insulating film and having a lower surface in contact with the upper surface of the first insulating film, and a metal electrode filled inside a contact hole penetrating the first insulating film and the second insulating film. In any of the above semiconductor devices, in a cross section of the trench portion passing through the contact hole in the arrangement direction, the width of the lower surface of the second insulating film may be smaller than the width of the upper surface of the first insulating film, and the metal electrode may be in contact with the upper surface of the first insulating film.

[0005] In any of the above semiconductor devices, the first insulating film may have a thickness smaller than that of the second insulating film. In any of the above semiconductor devices, the metal electrode may have a barrier metal provided continuously on an upper surface and a side surface of the first insulating film and an upper surface and a side surface of the second insulating film. In any of the above semiconductor devices, the first insulating film may be provided along a corner of the metal electrode. In any of the above semiconductor devices, an upper surface of the conductive portion of the trench portion and an upper surface of the semiconductor substrate may be provided in parallel.

[0006] In a second aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate having a trench portion in which a conductive portion is provided. The semiconductor device may include a first insulating film in contact with an upper surface of the trench portion and an upper surface of the semiconductor substrate, a second insulating film having a lower surface in contact with the upper surface of the first insulating film and made of a different material from the first insulating film, and a metal electrode filling a contact hole penetrating the first insulating film and the second insulating film. In any of the above semiconductor devices, in a cross section of the trench portion passing through the contact hole in the arrangement direction, the width of the lower surface of the second insulating film is smaller than the width of the upper surface of the first insulating film, the metal electrode is in contact with the upper surface of the first insulating film, and the metal electrode may include a barrier metal provided continuously on the upper surface and side surface of the first insulating film and the upper surface and side surface of the second insulating film.

[0007] In any of the above semiconductor devices, the metal electrode may have a plug formed containing tungsten. In any of the above semiconductor devices, the second insulating film may have a tapered side surface formed in a tapered shape. In any of the above semiconductor devices, the tapered side surface may have a width in a depth direction larger than a width in the arrangement direction.

[0008] In any one of the semiconductor devices described above, an upper surface of the first insulating film and an upper surface of the second insulating film may be provided parallel to an upper surface of the conductive portion. In any one of the semiconductor devices described above, an upper surface of the conductive portion may be located at the same position in a depth direction as an upper surface of the semiconductor substrate.

[0009] In any of the above semiconductor devices, the trench portion may have a third insulating film insulating the conductive portion from the semiconductor substrate. In any of the above semiconductor devices, the first insulating film may have a lower oxygen content than the third insulating film.

[0010] In any one of the above semiconductor devices, the first insulating film is made of SiN (silicon nitride), HfO 2 (Hafnium oxide), TiO 2 (Titanium oxide), Ta 2 O 5 (tantalum pentoxide), TiN (titanium nitride) and HfSiO (hafnium silicate).

[0011] In any of the above semiconductor devices, the second insulating film may be PSG or BPSG.

[0012] In a third aspect of the present invention, A semiconductor device is provided that includes a semiconductor substrate having a trench portion. The semiconductor device may include a metal electrode in contact with an upper surface side of the semiconductor substrate, a first insulating film made of SiN (silicon nitride) and provided between the semiconductor substrate and the metal electrode and in contact with the metal electrode, and a second insulating film made of a material different from the first insulating film and provided on an upper surface of the first insulating film and in contact with the metal electrode and the first insulating film. In any of the above semiconductor devices, the first insulating film may be provided along a corner of the metal electrode.

[0013] In any of the semiconductor devices described above, in a cross section in the arrangement direction, a width of a lower surface of the second insulating film may be larger than a width of the conductive portion.

[0014] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0015] [Figure 1] 1 is a diagram partially illustrating an example of the upper surface of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2a] FIG. 2 is a diagram showing an example of a-a' cross section in FIG. [Figure 2b] FIG. 2B is an enlarged view of area A1 in FIG. 2A. [Figure 2c] 1. FIG. 4 is a diagram showing another example of the aa' cross section in FIG. [Figure 3a] 1. FIG. 4 is a diagram showing another example of the aa' cross section in FIG. [Figure 3b] FIG. 3B is an enlarged view of area A2 in FIG. [Figure 4a] 1. FIG. 4 is a diagram showing another example of the aa' cross section in FIG. [Figure 4b] FIG. 4b is an enlarged view of area A3 in FIG. 4a. [Figure 5a] 1. FIG. 4 is a diagram showing another example of the aa' cross section in FIG. [Figure 5b] FIG. 5b is an enlarged view of area A4 in FIG. 5a. [Figure 6] 1 is a diagram partially illustrating the upper surface of a semiconductor device 150 of a comparative example. [Figure 7a] FIG. 7 is a diagram showing an example of the zz' cross section in FIG. [Figure 7b] FIG. 2b is an enlarged view of region Z in FIG. 2a. [Figure 8a] 1. FIG. 4 is a diagram showing another example of the aa' cross section in FIG. [Figure 8b] FIG. 8b is an enlarged view of area A4 in FIG. 8a. [Figure 9a]1. FIG. 4 is a diagram showing another example of the aa' cross section in FIG. [Figure 9b] FIG. 9b is an enlarged view of area A5 in FIG. 9a. [Figure 10a] 1. FIG. 4 is a diagram showing another example of the aa' cross section in FIG. [Figure 10b] FIG. 10b is an enlarged view of area A6 in FIG. [Figure 11] 1 is a diagram partially illustrating another example of the upper surface of the semiconductor device 100 according to the present embodiment. [Figure 12a] 12 is a diagram showing an example of the bb' cross section in FIG. [Figure 12b] FIG. 12b is an enlarged view of region B1 in FIG. [Figure 13a] 12 is a diagram showing another example of the bb' cross section in FIG. [Figure 13b] FIG. 13B is an enlarged view of region B2 in FIG. 13A. [Figure 14a] 12 is a diagram showing another example of the bb' cross section in FIG. [Figure 14b] FIG. 14B is an enlarged view of region B3 in FIG. [Figure 15a] 12 is a diagram showing another example of the bb' cross section in FIG. [Figure 15b] FIG. 15B is an enlarged view of region B4 in FIG. 15A. [Figure 16a] 12 is a diagram showing another example of the bb' cross section in FIG. [Figure 16b] FIG. 16B is an enlarged view of region B5 in FIG. 16A. [Figure 17a] 12 is a diagram showing another example of the bb' cross section in FIG. [Figure 17b] FIG. 17b is an enlarged view of region B6 in FIG. 17a. [Figure 18a] 2A to 2C are diagrams illustrating an example of a method for manufacturing the semiconductor device 100 according to the present embodiment. [Figure 18b] 5A to 5C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the present embodiment. [Figure 19] 5A to 5C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0017] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0018] In this specification, technical matters may be described using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and a depth direction perpendicular to the top surface of the semiconductor substrate is defined as the Z axis.

[0019] In each embodiment, an example is shown in which the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are reversed. In addition, when P+ type (or N+ type) is described in this specification, it means that the doping concentration is higher than that of P type (or N type), and when P- type (or N- type) is described, it means that the doping concentration is lower than that of P type (or N type).

[0020] In this specification, the doping concentration refers to the concentration of an impurity that has become a donor or an acceptor. In this specification, the difference in concentration between the donor and the acceptor may be referred to as the doping concentration. Also, the peak value of the doping concentration distribution in a doping region may be referred to as the doping concentration in the doping region.

[0021] 1 is a diagram partially illustrating an example of the top surface of a semiconductor device 100 according to this embodiment. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80 provided adjacent to the transistor section 70. The transistor section 70 includes a transistor such as an IGBT. The boundary section 90 is a region of the transistor section 70 adjacent to the diode section 80. The diode section 80 includes a diode such as an FWD (Free Wheel Diode) on the top surface of the semiconductor substrate. FIG. 1 shows the top surface of the chip around the chip end, and other regions are omitted.

[0022] 1 shows an active region of a semiconductor substrate in semiconductor device 100, but semiconductor device 100 may have an edge termination structure surrounding the active region. The active region refers to a region through which current flows when semiconductor device 100 is controlled to an on-state. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure that combines these.

[0023] The semiconductor device 100 of this example is provided inside a semiconductor substrate and includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 that are exposed on the upper surface of the semiconductor substrate. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 that are provided above the upper surface of the semiconductor substrate. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0024] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the upper surface of the semiconductor substrate, but is omitted in Fig. 1. In the interlayer insulating film of this example, contact holes 56, 49, and 54 are provided so as to penetrate the interlayer insulating film.

[0025] Moreover, the emitter electrode 52 is connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. An insulating film such as an oxide film is provided between the connection portion 25 and the upper surface of the semiconductor substrate.

[0026] The gate metal layer 50 contacts the gate runner 48 through the contact hole 49. The gate runner 48 is formed of polysilicon doped with impurities or the like. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate. The gate runner 48 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0027] The gate runner 48 of this example is formed from below the contact hole 49 to the tip of the gate trench portion 40. An insulating film such as an oxide film is formed between the gate runner 48 and the upper surface of the semiconductor substrate.

[0028] The upper surface side of the semiconductor substrate of the gate conductive portion is exposed at the tip of the gate trench portion 40. The gate trench portion 40 contacts the gate runner 48 at the exposed portion of the gate conductive portion.

[0029] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of aluminum or an aluminum-silicon alloy.

[0030] At least a portion of the gate metal layer 50 may be made of aluminum or an aluminum-silicon alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal made of titanium, a titanium compound, or the like under the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 may also have a plug made of tungsten or the like in the contact hole.

[0031] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged at a predetermined interval along a predetermined arrangement direction (Y-axis direction in this example). The gate trench portion 40 in this example may have two extension portions 39 extending along an extension direction (X-axis direction in this example) parallel to the upper surface of the semiconductor substrate and perpendicular to the arrangement direction, and a connection portion 41 connecting the two extension portions 39. At least a part of the connection portion 41 is preferably formed in a curved shape. By connecting the ends of the two extension portions 39 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 39. In this specification, each extension portion 39 of the gate trench portion 40 may be treated as one gate trench portion 40. The gate runner 48 may be connected to the gate conductive portion at the connection portion 41 of the gate trench portion 40.

[0032] The dummy trench portion 30 of this example may have a U-shape on the upper surface of the semiconductor substrate, similar to the gate trench portion 40. That is, the dummy trench portion 30 of this example may have two extension portions 29 extending along the extension direction and a connection portion 31 connecting the two extension portions 29.

[0033] The emitter electrode 52 is formed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is of the second conductivity type. The well region 11 is of the P+ type, for example. The well region 11 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 11. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 11.

[0034] In a plane parallel to the top surface of the semiconductor substrate, a mesa portion is provided adjacent to each trench portion in the Y-axis direction. The mesa portion is a portion of the semiconductor substrate sandwiched between two adjacent trench portions. The mesa portion may be a portion from the top surface of the semiconductor substrate to the depth of the deepest bottom of each trench portion. The mesa portion may be a region sandwiched between the extension portions of two adjacent trench portions.

[0035] In the transistor section 70, a first mesa section 60 is provided adjacent to each trench section. In the boundary section 90, a second mesa section 62 is provided in a region sandwiched between adjacent dummy trench sections 30. In the diode section 80, a third mesa section 64 is provided in a region sandwiched between adjacent dummy trench sections 30.

[0036] At both ends in the X-axis direction of the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64, for example, a second conductivity type base region 14 is provided exposed on the upper surface of the semiconductor substrate. In this example, the base region 14 is, for example, a P-type. Note that FIG. 1 shows only one end of the base region 14 in the X-axis direction.

[0037] An emitter region 12 is provided on the upper surface of the first mesa portion 60 in contact with the gate trench portion 40. The emitter region 12 may be provided in the Y-axis direction from one of two trench portions extending in the X-axis direction to the other, sandwiching the first mesa portion 60. The emitter region 12 is also provided below the contact hole 54. In FIG. 1, the boundary of the emitter region 12 that overlaps with the contact hole 54 in a top view of the semiconductor substrate is indicated by a dashed line.

[0038] The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is provided in contact with the dummy trench portion 30. The emitter region 12 in this example is of a first conductivity type. As an example, the emitter region 12 in this example is of an N+ type.

[0039] A contact region 15 of a second conductivity type having a higher doping concentration than the base region 14 is provided on the upper surface of the first mesa portion 60. The contact region 15 in this example is P+ type, for example. In the first mesa portion 60, the emitter region 12 and the contact region 15 may be provided alternately in the extension direction of the gate trench portion 40. The contact region 15 may be provided in the Y-axis direction from one to the other of two trench portions extending in the X-axis direction with the first mesa portion 60 in between. The contact region 15 is also provided below the contact hole 54. In FIG. 1, the boundary of the contact region 15 overlapping with the contact hole 54 in the top view of the semiconductor substrate is indicated by a dashed line.

[0040] The contact region 15 may or may not be in contact with the gate trench portion 40. In addition, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is provided in contact with the dummy trench portion 30 and the gate trench portion 40.

[0041] A contact region 15 is provided on the upper surface of the second mesa portion 62. The area of ​​the contact region 15 provided on the upper surface of one second mesa portion 62 is larger than the area of ​​the contact region 15 provided on the upper surface of one first mesa portion 60. The area of ​​the contact region 15 provided on the upper surface of one second mesa portion 62 may be larger than the area of ​​the contact region 15 provided on the upper surface of one third mesa portion 64. In the second mesa portion 62, the contact region 15 is also provided below the contact hole 54.

[0042] The contact region 15 on the upper surface of the second mesa portion 62 may be provided in the entire region sandwiched between the base regions 14 provided at both ends in the X-axis direction of the second mesa portion 62. The second mesa portion 62 extracts carriers more effectively at the time of turn-off than the first mesa portion 60.

[0043] Contact regions 15 are provided on both ends in the X-axis direction on the upper surface of the third mesa portion 64. Furthermore, a base region 14 is provided on the upper surface of the third mesa portion 64 in a region sandwiched between the contact regions 15 provided on both ends in the X-axis direction of the third mesa portion 64. The base region 14 may be provided in the entire region sandwiched between the contact regions 15 in the X-axis direction. In the third mesa portion 64, the base region 14 is also provided below the contact hole 54. The contact region 15 may also be provided below the contact hole 54.

[0044] In the third mesa portion 64, the contact region 15 and the base region 14 are formed from one dummy trench portion 30 to the other dummy trench portion 30 that sandwich the third mesa portion 64. That is, on the upper surface of the semiconductor substrate, the width in the Y-axis direction of the third mesa portion 64 is equal to the width in the Y-axis direction of the contact region 15 or the base region 14 provided in the third mesa portion 64.

[0045] The emitter region 12 may or may not be formed in the third mesa portion 64. In this example, the emitter region 12 is not formed in the third mesa portion 64.

[0046] In the semiconductor device 100 of the present example, a dummy trench portion 30 is provided in the diode portion 80. The linear extension portions 29 of adjacent dummy trench portions 30 may be connected by a connection portion 31. The third mesa portion 64 is a region sandwiched between the dummy trench portions 30.

[0047] The diode section 80 has a cathode region 82 of a first conductivity type on the lower surface side of the semiconductor substrate. The cathode region 82 in this example is an N+ type, for example. In FIG. 1, the region in which the cathode region 82 is provided in the top view of the semiconductor substrate is indicated by a dashed line. The diode section 80 may be a region in which the cathode region 82 is projected onto the upper surface of the semiconductor substrate. The diode section 80 may also include the entire third mesa section 64 in which the cathode region 82 is partially provided, and the dummy trench section 30 adjacent to the third mesa section 64. The region in which the cathode region 82 is projected onto the upper surface of the semiconductor substrate may be away from the contact region 15 on the positive side in the X-axis direction.

[0048] A collector region of a second conductivity type may be formed in a region of the lower surface of the semiconductor substrate where the cathode region 82 is not formed. The collector region in this example is, for example, a P+ type. The collector region may be formed at a position where the end of the contact hole 54 in the diode section 80 on the negative side in the X-axis direction is projected onto the lower surface of the semiconductor substrate.

[0049] In the transistor portion 70 excluding the boundary portion 90, the contact hole 54 is formed above each of the contact region 15 and the emitter region 12. In the first mesa portion 60 excluding the first mesa portion 60 adjacent to the boundary portion 90, the contact hole 54 may be provided so as not to overlap with the gate trench portion 40 and the dummy trench portion 30 extending in the X-axis direction in the top view of FIG. 1. The width of the contact hole 54 in the Y-axis direction may be smaller than the width of the emitter region 12 and the contact region 15 in the Y-axis direction.

[0050] In the transistor portion 70 excluding the boundary portion 90, the contact hole 54 may be provided continuously from above the contact region 15 provided on the most negative side in the X-axis direction of the first mesa portion 60 to above the contact region 15 provided on the most positive side in the X-axis direction in the top view of Fig. 1. The contact hole 54 may be provided so as to overlap with at least a portion of the contact region 15 provided on the most negative side in the X-axis direction of the first mesa portion 60 in the top view of Fig. 1. The contact hole 54 may be provided so as to overlap with at least a portion of the contact region 15 provided on the most positive side in the X-axis direction of the first mesa portion 60 in the top view of Fig. 1.

[0051] In the boundary portion 90, the contact hole 54 is formed above the contact region 15. In the second mesa portion 62, the contact hole 54 may be provided so as not to overlap with the dummy trench portion 30 extending in the X-axis direction in the top view of FIG. 1. The width of the contact hole 54 in the Y-axis direction may be smaller than the width of the contact region 15 in the Y-axis direction.

[0052] 1, in the boundary portion 90, the contact hole 54 may be provided continuously in the X-axis direction above the contact region 15 provided in the second mesa portion 62. The contact hole 54 may be provided so as to overlap at least a portion of the contact region 15 provided in the second mesa portion 62.

[0053] In the diode portion 80, the contact hole 54 is formed above the base region 14 and the contact region 15. In the third mesa portion 64, the contact hole 54 may be provided so as not to overlap with the dummy trench portion 30 extending in the X-axis direction in the top view of FIG. 1 . The width of the contact hole 54 in the Y-axis direction may be smaller than the width of the base region 14 and the contact region 15 in the Y-axis direction.

[0054] In the diode section 80, the contact hole 54 may be provided continuously from above the contact region 15 provided on the most negative side in the X-axis direction of the third mesa section 64 to above the contact region 15 provided on the most positive side in the X-axis direction in the top view of Fig. 1. The contact hole 54 may be provided so as to overlap with at least a part of the contact region 15 provided on the negative side in the X-axis direction of the third mesa section 64 in the top view of Fig. 1. The contact hole 54 may be provided so as to overlap with at least a part of the contact region 15 provided on the positive side in the X-axis direction of the third mesa section 64 in the top view of Fig. 1.

[0055] In the semiconductor device 100 of this example, a first conductivity type accumulation region 16 is provided below the base region 14 inside the semiconductor substrate. The accumulation region 16 in this example is an N+ type, for example. In Fig. 1, the range in which the accumulation region 16 is formed is indicated by a dashed line. The accumulation region 16 may be formed on the +X-axis direction side from a region where the contact region 15 at the end in the -X-axis direction and the contact hole 54 overlap, when viewed from above the semiconductor substrate.

[0056] 2a is a diagram showing an example of the a-a' cross section in FIG. The a-a' cross section is a YZ plane passing through the emitter region 12 and the contact region 15 in the transistor section 70 and the diode section 80. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a protective insulating film 36, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10, a part of the upper surface of the protective insulating film 36, and the upper surface of the interlayer insulating film 38.

[0057] Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are formed of a conductive material such as metal. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 is referred to as the depth direction (Z-axis direction).

[0058] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0059] The semiconductor substrate 10 includes a drift region 18 of a first conductivity type. In this example, the drift region 18 is an N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 without other doped regions being provided therein.

[0060] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided in the upper surface 21 of the semiconductor substrate 10. Each trench portion is provided from the upper surface 21, penetrating the base region 14, and reaching the drift region 18.

[0061] The gate trench portion 40 has a gate trench provided on the upper surface 21, and a gate insulating film 42 and a gate conductive portion 44 provided in the gate trench. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0062] The gate conductive portion 44 is provided inside the gate trench portion 40 and surrounded by the gate insulating film 42. The gate conductive portion 44 includes at least a region facing the adjacent base region 14 in the depth direction, with the gate insulating film 42 sandwiched therebetween. The gate trench portion 40 in this cross section is covered on the upper surface 21 with the interlayer insulating film 38. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0063] In FIG. 2a, Y1 and Y1' are the upper ends of the gate trench portion 40. The positions of the upper ends Y1 and Y1' in the Z-axis direction are equal to the position of the upper surface 21 in the Z-axis direction. The gate trench portion 40 may be a region below the positions of the upper ends Y1 and Y1' in the Z-axis direction. That is, the gate trench portion 40 may be a region below the upper surface 21 in the Z-axis direction. Note that the upper ends Y1 and Y1' may be the upper ends of the gate trench portion 40 in a YZ plane other than the a-a' cross section, such as a YZ plane passing through the contact region 15 in the first mesa portion 60.

[0064] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 side, and a dummy insulating film 32 and a dummy conductive portion 34 provided in the dummy trench. The upper end of the dummy trench may be at the same position as the upper surface 21 in the Z-axis direction. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench portion 30 and surrounded by the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.

[0065] The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0066] Y1'' is the upper end of the dummy trench portion 30. The position of the upper end Y1'' in the Z-axis direction is equal to the position of the upper surface 21 in the Z-axis direction. The dummy trench portion 30 may be a region below the position of the upper end Y1'' in the Z-axis direction. In other words, the dummy trench portion 30 may be a region below the upper surface 21 in the Z-axis direction. The upper end Y1'' may be the upper end of the dummy trench portion 30 in a YZ plane other than the a-a' cross section, such as a YZ plane passing through the contact region 15 in the first mesa portion 60.

[0067] In the first mesa portion 60, one or more accumulation regions 16 are provided above the drift region 18 in contact with the gate trench portion 40. The accumulation region 16 is a region in which dopants (donors in this case) are accumulated at a higher concentration than in the drift region 18. When a plurality of accumulation regions 16 are provided, the respective accumulation regions 16 are arranged side by side in the Z-axis direction. As an example, the accumulation region 16 is of N+ type. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage can be reduced.

[0068] One or more accumulation regions 16 may be in contact with the dummy trench portion 30 in the first mesa portion 60, but may be separated from the dummy trench portion 30. FIG. 2a shows an example in which the accumulation region 16 is provided in contact with the dummy trench portion 30. The accumulation region 16 may be provided in the second mesa portion 62 and the third mesa portion 64, but may not be provided. FIG. 2a shows an example in which the accumulation region 16 is provided in the second mesa portion 62 and the third mesa portion 64.

[0069] In the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64, a plurality of accumulation regions 16 may be provided in the Z-axis direction. FIG. 2a shows an example in which two accumulation regions 16 are provided in the Z-axis direction. A drift region 18 may be provided between the accumulation region 16-1 and the accumulation region 16-2 in the Z-axis direction. By providing a plurality of accumulation regions 16, the electron current is likely to flow near the center of the first mesa portion 60. Therefore, the hole distribution near the bottom of the first mesa portion 60 can be divided near the center of the first mesa portion 60. Therefore, the accumulation of holes at the lower end of the gate trench portion 40 can be suppressed. As a result, the displacement current of the transistor portion 70 can be reduced.

[0070] In the first mesa portion 60, a base region 14 of the second conductivity type is provided above the accumulation region 16 in contact with the gate trench portion 40. The base region 14 is, for example, an N-type. In the first mesa portion 60, the base region 14 may be provided in contact with the dummy trench portion 30.

[0071] In the second mesa portion 62 of the boundary portion 90, a second conductivity type base region 14 is provided above the drift region 18 in contact with the dummy trench portion 30. In the third mesa portion 64 of the diode portion 80, a second conductivity type base region 14 is provided above the drift region 18 in contact with the dummy trench portion 30. In the third mesa portion 64, the base region 14 is provided in contact with the upper surface 21.

[0072] In the first mesa portion 60, an emitter region 12 is provided in contact with the upper surface 21 and in contact with the gate trench portion 40 in the a-a' cross section. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. In the first mesa portion 60, contact regions 15 are provided on the positive and negative sides in the X-axis direction in contact with the upper surface 21 and in contact with the gate trench portion 40.

[0073] In the second mesa portion 62, a contact region 15 is provided on the upper surface 21 adjacent to the dummy trench portion 30. The contact region 15 may be in contact with the dummy trench portion 30, or may be separated from the dummy trench portion 30. FIG. 2a shows an example in which the contact region 15 is provided in contact with the dummy trench portion 30.

[0074] A first conductive type buffer region 20 may be provided below the drift region 18. The buffer region 20 is, for example, N+ type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0075] In the transistor section 70, a P+ type collector region 22 exposed at the lower surface 23 is provided below the buffer region 20. In the diode section 80, an N+ type cathode region 82 exposed at the lower surface 23 is provided below the buffer region 20. In the boundary section 90, either the collector region 22 or the cathode region 82 is provided below the buffer region 20. In the boundary section 90 of this example, the collector region 22 is provided below the buffer region 20.

[0076] The diode section 80 is a region overlapping with the cathode region 82 in the direction perpendicular to the lower surface 23. The transistor section 70 is a region, excluding the boundary section 90, that overlaps with the collector region 22 in the direction perpendicular to the lower surface 23 and in which predetermined unit configurations including the emitter region 12 and the contact region 15 are regularly arranged.

[0077] The interlayer insulating film 38 is provided above the gate trench portion 40 and the dummy trench portion 30. The interlayer insulating film 38 may be a silicate glass such as PSG or BPSG. The interlayer insulating film 38 may also be an oxide film, a nitride film, or the like.

[0078] The semiconductor device 100 of this example has a protective insulating film 36 made of a different material from the interlayer insulating film 38 and the gate insulating film 42 between the interlayer insulating film 38 and the gate trench portion 40 in the depth direction (Z-axis direction) of the semiconductor substrate 10. In this example, the protective insulating film 36 is also provided inside the gate trench portion 40 and inside the dummy trench portion 30, i.e., below the upper surface 21. The protective insulating film 36 is provided in contact with the gate insulating film 42. The oxygen content of the protective insulating film 36 may be lower than the oxygen content of the gate insulating film 42. The oxygen content of the protective insulating film 36 may be 1 / 10 or less of the oxygen content of the gate insulating film 42.

[0079] The protective insulating film 36 is, for example, silicon nitride (SiN). Other high-dielectric constant (high-k) insulating films such as hafnium oxide (HfO2), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), titanium nitride (TiN), and hafnium silicate (HfSiO) can also be used as the protective insulating film 36.

[0080] Fig. 2b is an enlarged view of region A1 in Fig. 2a. Fig. 2b shows an enlarged view of the vicinity of the upper surface 21 of the first mesa portion 60.

[0081] In this example, Tp and Tp' are the upper ends of the gate conductive portion 44. In this example, the upper ends Tp and Tp' of the gate conductive portion 44 are disposed below the upper surface 21. The positions of the upper ends Tp and Tp' in the Z-axis direction may be the same.

[0082] In the semiconductor device 100 of the present embodiment, the protective insulating film 36 is provided above at least a portion of the gate conductive portion 44 inside the gate trench portion 40. This embodiment is an example in which the protective insulating film 36 is provided above the entire gate conductive portion 44 inside the gate trench portion 40. The protective insulating film 36 may be in contact with the gate conductive portion 44.

[0083] In this example, Tp'' is the upper end of the dummy conductive portion 34. In this example, the upper end Tp'' of the dummy conductive portion 34 is disposed below the upper surface 21. The position of the upper end Tp'' in the Z-axis direction may be the same as the positions of the upper end Tp and the upper end Tp' in the Z-axis direction.

[0084] In this example, a protective insulating film 36 is provided above at least a portion of the dummy conductive portion 34 in a direction parallel to the upper surface 21. This example is an example in which the protective insulating film 36 is provided above the entire dummy conductive portion 34 in a direction parallel to the upper surface 21. The protective insulating film 36 may be in contact with the dummy conductive portion 34.

[0085] The depth Di is the depth in the Z-axis direction from the position of the upper surface 21 in the Z-axis direction to the lower end Z1 of the protective insulating film 36 in the Z-axis direction. The depth De is the depth in the Z-axis direction from the position of the upper surface 21 in the Z-axis direction to the lower surface of the emitter region 12 in the emitter region 12. As the depth Di is increased, the upper surface of the gate conductive portion 44 is disposed lower, so that it becomes necessary to inject the dopant to a deeper position from the upper surface 21 in order to form the emitter region 12. Injecting the dopant to a deeper position from the upper surface 21 increases the thermal history in the heat treatment process for forming the emitter region 12. For this reason, the depth Di is preferably 0.7 times or more and 0.9 times or less than the depth De.

[0086] The depth Di may be 0.2 μm or more and 0.4 μm or less. The depth Di is, for example, 0.3 μm. The depth De may be 0.35 μm or more and 0.45 μm or less. The depth De is, for example, 0.4 μm.

[0087] In this example, the width Wiv is the thickness of the protective insulating film 36 above the upper surface 21. That is, the width Wiv is the width in the Z-axis direction from the upper surface 21 to the upper surface of the protective insulating film 36. The width Wsiv is the thickness of the interlayer insulating film 38 provided on the upper surface of the protective insulating film 36. That is, the width Wsiv is the width in the Z-axis direction from the upper surface of the protective insulating film 36 to the upper surface of the interlayer insulating film 38.

[0088] The width Wiv may be smaller than the width Wsiv. The width Wiv may be 1 / 20 or more and 1 / 5 or less of the width Wsiv. By making the width Wiv smaller than the width Wsiv, the positioning accuracy of the protective insulating film 36 in the direction parallel to the upper surface 21 can be made higher than the positioning accuracy of the interlayer insulating film 38.

[0089] The width Wiv may be 0.05 μm or more and 0.20 μm or less. For example, the width Wiv is 0.1 μm. The width Wsiv may be 0.6 μm or more and 1.0 μm or less. For example, the width Wsiv is 0.8 μm.

[0090] In the semiconductor device 100 of this embodiment, since the width Wiv is smaller than the width Wsiv, the protective insulating film 36 can be positioned more precisely in the direction parallel to the upper surface 21 than the interlayer insulating film 38. Therefore, even if the first mesa portion 60 is narrowed, a short circuit between the GEs can be prevented. Therefore, the characteristics of the semiconductor device 100 can be improved while the semiconductor device 100 is further miniaturized.

[0091] In this example, the width Wt is the width of the gate trench portion 40 in the Y-axis direction. End E is the end of the protective insulating film 36 on the positive side in the Y-axis direction that is provided above the gate trench portion 40. End E' is the end of the protective insulating film 36 on the negative side in the Y-axis direction. End E'' is the end of the protective insulating film 36 on the positive side in the Y-axis direction that is provided above the dummy trench portion 30.

[0092] In this example, end E is positioned in the Y-axis direction at a distance of width Wit from the sidewall on the positive side in the Y-axis direction of the gate trench portion 40. End E' is positioned in the Y-axis direction at a distance of width Wit' from the sidewall on the negative side in the Y-axis direction of the gate trench portion 40. In other words, the width Wih is greater than the width Wt. End E'' is positioned in the Y-axis direction at a distance of width Wit'' from the sidewall on the positive side in the Y-axis direction of the dummy trench portion 30.

[0093] In this example, end F is the end on the positive side in the Y axis direction of the interlayer insulating film 38 provided above the gate trench portion 40. End F' is the end on the negative side in the Y axis direction of the interlayer insulating film 38. End F'' is the end on the positive side in the Y axis direction of the interlayer insulating film 38 provided above the dummy trench portion 30.

[0094] In this example, end F is arranged at a distance of width Wsit in the Y-axis direction from the side surface of the gate conductive portion 44 on the positive side in the Y-axis direction. End F' is arranged at a distance of width Wsit' in the Y-axis direction from the side surface of the gate trench portion 40 on the negative side in the Y-axis direction. End F'' is arranged at a distance of width Wsit'' in the Y-axis direction from the side surface of the dummy conductive portion 34 on the positive side in the Y-axis direction.

[0095] In this example, the protective insulating film 36 is provided in contact with the first mesa portion 60. That is, the protective insulating film 36 is provided in contact with a part of the upper surface 21 of the first mesa portion 60. On the positive side of the protective insulating film 36 in the Y axis direction provided above the gate trench portion 40, the protective insulating film 36 and the first mesa portion 60 are in contact with each other at a width Wit. On the negative side of the protective insulating film 36 in the Y axis direction, the protective insulating film 36 and the first mesa portion 60 are in contact with each other at a width Wit'. On the positive side of the protective insulating film 36 in the Y axis direction provided above the dummy trench portion 30, the protective insulating film 36 and the first mesa portion 60 are in contact with each other at a width Wit''.

[0096] In the semiconductor device 100 of this embodiment, the protective insulating film 36 is in contact with the first mesa portion 60, and the width Wih is larger than the width Wt. The protective insulating film 36 can be positioned with higher accuracy than the interlayer insulating film 38. Therefore, the width Wit and the width Wit' can be secured while the width Wih is larger than the width Wt. Therefore, even if the interlayer insulating film 38 is shifted to the positive side in the Y-axis direction by the width Wsit' or more or to the negative side in the Y-axis direction by the width Wsit or more due to process variations, a short circuit between the contact provided in the contact hole 54 and the gate conductive portion 44 can be suppressed. That is, in the semiconductor device 100 of this embodiment, the protective insulating film 36 protects the gate insulating film 42 and the gate conductive portion 44, so that a GE-to-GE short circuit, that is, a short circuit between the gate metal layer 50 and the emitter electrode 52 can be prevented. Therefore, while preventing a GE-to-GE short circuit, the mesa width can be narrowed, the IE effect can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0097] In this example, vertex P is the vertex on the positive side in the Y-axis direction of the interlayer insulating film 38 provided above the gate trench portion 40. Vertex P' is the vertex on the negative side in the Y-axis direction of the interlayer insulating film 38. Vertex P'' is the vertex on the positive side in the Y-axis direction of the interlayer insulating film 38 provided above the dummy trench portion 30. In the Z-axis direction, the positions of vertex P, vertex P', and vertex P'' are equal to the position of the upper surface of the interlayer insulating film 38.

[0098] In this example, the width Wih is the width of the protective insulating film 36 in the Y-axis direction. The width Wsihu1 is the width from apex P to apex P' of the interlayer insulating film 38 in the Y-axis direction. Furthermore, the width Wsihd1 is the width of the interlayer insulating film 38 in the Y-axis direction at the position where the interlayer insulating film 38 and the protective insulating film 36 contact in the Z-axis direction. In this example, the side surface of the interlayer insulating film 38 is equal to the XZ plane, so the widths Wsihu1 and Wsihd1 are equal. Furthermore, the widths Wsihu1 and Wsihd1 are equal to the width of the interlayer insulating film. The width Wih may be larger than the widths Wsihu1 and Wsihd1.

[0099] Moreover, in this example, the width Wc is the width in the Y-axis direction from the end E' to the end E". That is, the width Wc is the width in the Y-axis direction at the upper surface 21 of the contact hole 54. The width Wm is the mesa width of the first mesa portion 60. Moreover, the width Wss1 is the width in the Y-axis direction from the apex P' to the apex P". That is, in this example, the width Wss1 is the width in the Y-axis direction from the side surface on the negative side in the Y-axis direction of the interlayer insulating film 38 provided above the gate trench portion 40 to the side surface on the positive side in the Y-axis direction of the interlayer insulating film 38 provided above the dummy trench portion 30.

[0100] In the semiconductor device 100 of this embodiment, the width Wsihu1 and the width Wsihd1 are smaller than the width Wih, so that the width Wss1 can be made larger than the width Wc. Therefore, the contact filled in the contact hole 54 is more likely to be filled up to the lower end of the contact hole 54 than when the width Wss1 and the width Wc are equal. That is, the contact is more likely to come into contact with the upper surface 21 over the width Wc. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be reduced. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be reduced.

[0101] Fig. 2c is a diagram showing another example of the a-a' cross section in Fig. 1. The example shown in Fig. 2c shows an example in which a barrier metal 58 is provided on the upper surfaces of the first mesa portion 60, the second mesa portion 62, and the third mesa portion, the upper surface and side surface of the protective insulating film 36, and the upper surface and side surface of the interlayer insulating film 38 in the example of Fig. 2a. As shown in Fig. 2c, the barrier metal 58 may be provided continuously on the upper surfaces of the first mesa portion 60, the second mesa portion 62, and the third mesa portion, the upper surface and side surface of the protective insulating film 36, and the upper surface and side surface of the interlayer insulating film 38.

[0102] For example, aluminum (Al) can be used for the contact provided in the contact hole 54. The barrier metal 58 suppresses the diffusion of aluminum into the inside of the semiconductor substrate 10. For example, titanium nitride (TiN) can be used for the barrier metal 58.

[0103] Fig. 3a is a diagram showing another example of the a-a' cross section in Fig. 1. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 2a in that the protective insulating film 36 is not provided above the upper surface 21 in the semiconductor device 100 shown in Fig. 2a. In this example, the positions of the upper surfaces of the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64 are equal to the position of the upper surface of the protective insulating film 36 in the Z-axis direction.

[0104] Fig. 3b is an enlarged view of region A2 in Fig. 3a. As shown in Fig. 3b, in the semiconductor device 100 of this example, the position of the top surface of the first mesa portion 60 is the same as the position of the top surface of the protective insulating film 36 in the Z-axis direction.

[0105] The width Wih' of the protective insulating film 36 in the Y-axis direction in this example is smaller than the width Wih in the semiconductor device 100 shown in Fig. 2b. In this example, the width Wih' is equal to the width Wt.

[0106] The thickness, i.e., width Wsiv', of the interlayer insulating film 38 in this example is larger than the width Wsiv in the semiconductor device 100 shown in Fig. 2b. Also, the width Wc' in the Y-axis direction at the top surface 21 of the contact hole 54 in this example is larger than the width Wc in the semiconductor device 100 shown in Fig. 2b.

[0107] In the semiconductor device 100 of this example, the width Wsihu1 and the width Wsihd1 are smaller than the width Wih', so that the width Wss1 can be made larger than the width Wc'. In this example, the width Wc' is equal to the width Wm. The width Wc' is larger than the width Wc in the semiconductor device 100 shown in FIG. 2b. Therefore, the contact filled in the contact hole 54 contacts the upper surface 21 at a width Wc' larger than the width Wc in the example shown in FIG. 2b. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 and the contact region 15 can be further reduced compared to the semiconductor device 100 shown in FIG. 2b.

[0108] Fig. 4a is a diagram showing another example of the a-a' cross section in Fig. 1. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 2a in that the protective insulating film 36 is not provided below the upper surface 21 in the semiconductor device 100 shown in Fig. 2a. In this example, the positions of the upper surfaces of the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64 are equal to the position of the lower surface of the protective insulating film 36 in the Z-axis direction.

[0109] Fig. 4b is an enlarged view of region A3 in Fig. 4a. As shown in Fig. 4b, in the semiconductor device 100 of this example, the position in the Z-axis direction of the upper surface of the gate conductive portion 44 and the position in the Z-axis direction of the upper surface of the gate insulating film 42 are equal to the position in the Z-axis direction of the upper surface 21. The protective insulating film 36 contacts the gate conductive portion 44 and the gate insulating film 42 at a position on the upper surface 21 in the Z-axis direction.

[0110] In the semiconductor device 100 of this example, since the width Wiv is smaller than the width Wsiv, the protective insulating film 36 can be positioned more accurately in the direction parallel to the top surface 21 than the interlayer insulating film 38. Therefore, even if the first mesa portion 60 is further narrowed, a GE-to-GE short circuit can be prevented. Therefore, while preventing a GE-to-GE short circuit, the mesa width can be narrowed, and the on-voltage of the transistor portion 70 can be reduced by enhancing the IE effect.

[0111] In the semiconductor device 100 of this embodiment, the protective insulating film 36 is in contact with the first mesa portion 60, and the width Wih is larger than the width Wt. The protective insulating film 36 can be positioned with higher accuracy than the interlayer insulating film 38. Therefore, the width Wit and the width Wit' can be secured while the width Wih is larger than the width Wt. Therefore, even if the interlayer insulating film 38 is shifted to the positive side in the Y-axis direction by the width Wsit' or more or to the negative side in the Y-axis direction by the width Wsit or more due to process variations, a short circuit between the contact provided in the contact hole 54 and the gate conductive portion 44 can be suppressed. That is, in the semiconductor device 100 of this embodiment, the protective insulating film 36 protects the gate insulating film 42 and the gate conductive portion 44, so that a GE-to-GE short circuit, that is, a short circuit between the gate metal layer 50 and the emitter electrode 52 can be prevented. Therefore, while preventing a GE-to-GE short circuit, the mesa width can be narrowed, the IE effect can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0112] In addition, in the semiconductor device 100 of this embodiment, since the widths Wsihu1 and Wsihd1 are smaller than the width Wih, the width Wss1 can be made larger than the width Wc. Therefore, the contact filled in the contact hole 54 is more likely to be filled up to the lower end of the contact hole 54 than when the widths Wss1 and Wc are equal. That is, the contact is more likely to come into contact with the upper surface 21 over the width Wc. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be reduced. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be reduced.

[0113] 5a is a diagram showing another example of the a-a' cross section in FIG. 1. The semiconductor device 100 of this example is different from the semiconductor device 100 shown in FIG. 2a in that the protective insulating film 36 is provided to cover the inner wall of the gate trench portion 40, the upper surface of the gate insulating film 42, and the upper surface of the gate conductive portion 44, as well as the inner wall of the dummy trench portion 30, the upper surface of the dummy insulating film 32, and the upper surface of the dummy conductive portion 34, and the interlayer insulating film 38 is also provided below the upper surface 21. In this example, the interlayer insulating film 38 is also provided inside the gate trench portion 40 and the dummy trench portion 30.

[0114] Fig. 5b is an enlarged view of region A4 in Fig. 5a. As shown in Fig. 5b, in the semiconductor device 100 of this example, the protective insulating film 36 is provided to cover the inner wall of the gate trench portion 40, the upper surface of the gate insulating film 42, and the upper surface of the gate conductive portion 44, as well as the inner wall of the dummy trench portion 30, the upper surface of the dummy insulating film 32, and the upper surface of the dummy conductive portion 34. The interlayer insulating film 38 is provided from above the upper surface 21 to the inside of the gate trench portion 40 and the dummy trench portion 30.

[0115] In the semiconductor device 100 of this example, since the width Wiv is smaller than the width Wsiv, the protective insulating film 36 can be positioned more accurately in the direction parallel to the top surface 21 than the interlayer insulating film 38. Therefore, even if the first mesa portion 60 is further narrowed, a GE-to-GE short circuit can be prevented. Therefore, while preventing a GE-to-GE short circuit, the mesa width can be narrowed, and the on-voltage of the transistor portion 70 can be reduced by enhancing the IE effect.

[0116] In the semiconductor device 100 of this embodiment, the protective insulating film 36 is in contact with the first mesa portion 60, and the width Wih is larger than the width Wt. The protective insulating film 36 can be positioned with higher accuracy than the interlayer insulating film 38. Therefore, the width Wit and the width Wit' can be secured while the width Wih is larger than the width Wt. Therefore, even if the interlayer insulating film 38 is shifted to the positive side in the Y-axis direction by the width Wsit' or more or to the negative side in the Y-axis direction by the width Wsit or more due to process variations, a short circuit between the contact provided in the contact hole 54 and the gate conductive portion 44 can be suppressed. That is, in the semiconductor device 100 of this embodiment, the protective insulating film 36 protects the gate insulating film 42 and the gate conductive portion 44, so that a GE-to-GE short circuit, that is, a short circuit between the gate metal layer 50 and the emitter electrode 52 can be prevented. Therefore, while preventing a GE-to-GE short circuit, the mesa width can be narrowed, the IE effect can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0117] In addition, in the semiconductor device 100 of this embodiment, since the widths Wsihu1 and Wsihd1 are smaller than the width Wih, the width Wss1 can be made larger than the width Wc. Therefore, the contact filled in the contact hole 54 is more likely to be filled up to the lower end of the contact hole 54 than when the widths Wss1 and Wc are equal. That is, the contact is more likely to come into contact with the upper surface 21 over the width Wc. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be reduced. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be reduced.

[0118] Fig. 6 is a diagram partially illustrating the upper surface of a comparative semiconductor device 150. The comparative semiconductor device 150 differs from the semiconductor device 100 illustrated in Fig. 1 in that contact holes 254 are provided above the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64 in the semiconductor device 100 illustrated in Fig. 1.

[0119] Fig. 7a is a diagram showing the z-z' cross section in Fig. 6. As shown in Fig. 7a, the semiconductor device 150 of the comparative example is not provided with the protective insulating film 36. In the semiconductor device 150 of the comparative example, the interlayer insulating film 238 is provided on the upper surface 21. That is, in the Z-axis direction, the position of the upper surface 21 and the position of the lower surface of the interlayer insulating film 238 are the same.

[0120] Fig. 7b is an enlarged view of a region Z in Fig. 7a. As shown in Fig. 7b, the semiconductor device 150 of the comparative example does not include the protective insulating film 36.

[0121] The width Wsit is the width in the Y-axis direction from the end on the Y-axis direction positive side of the interlayer insulating film 238 provided above the gate trench portion 40 to the end on the Y-axis direction positive side of the gate conductive portion 44. In addition, the width Wsit is the width in the Y-axis direction from the end on the Y-axis direction negative side of the contact hole 254 provided on the Y-axis direction positive side of the gate trench portion 40 to the end on the Y-axis direction positive side of the gate conductive portion 44.

[0122] The width Wsit' is the width in the Y-axis direction from the end on the negative side in the Y-axis direction of the interlayer insulating film 238 provided above the gate trench portion 40 to the end on the negative side in the Y-axis direction of the gate conductive portion 44. Moreover, the width Wsit' is the width in the Y-axis direction from the end on the positive side in the Y-axis direction of the contact hole 254 provided on the negative side in the Y-axis direction of the gate trench portion 40 to the end on the positive side in the Y-axis direction of the gate conductive portion 44. The width Wsit and the width Wsit' are equal.

[0123] The width Wsit'' is the width in the Y-axis direction from the end on the Y-axis direction positive side of the interlayer insulating film 238 provided above the dummy trench portion 30 to the end on the Y-axis direction positive side of the dummy conductive portion 34. In addition, the width Wsit'' is the width in the Y-axis direction from the end on the Y-axis direction negative side of the contact hole 254 provided on the Y-axis direction positive side of the dummy trench portion 30 to the end on the Y-axis direction positive side of the dummy conductive portion 34.

[0124] The semiconductor device 150 of the comparative example is not provided with the protective insulating film 36. Therefore, if the interlayer insulating film 238 is shifted by more than the width Wsit' to the positive side in the Y-axis direction or by more than the width Wsit to the negative side in the Y-axis direction due to process variations, the contact provided in the contact hole 254 and the gate conductive portion 44 are shorted, causing a GE-to-GE short circuit. Therefore, it is difficult for the semiconductor device 150 of the comparative example to narrow the mesa width, increase the IE effect, and lower the on-voltage of the transistor portion 70 while preventing a GE-to-GE short circuit.

[0125] The thickness, i.e., width Wsiv', of the interlayer insulating film 238 is larger than the thickness, i.e., width Wiv, of the protective insulating film 36 in the semiconductor device 100 shown in Fig. 2b. For this reason, the interlayer insulating film 238 cannot be positioned with as high precision as the protective insulating film 36. For this reason, the interlayer insulating film 238 is more likely to shift in the Y-axis direction positive side by more than the width Wsit' or in the Y-axis direction negative side by more than the width Wsit than the protective insulating film 36, and a GE short circuit is more likely to occur.

[0126] Fig. 8a is a diagram showing another example of the a-a' cross section in Fig. 1. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 2a in that the side surface of the interlayer insulating film 38 in the semiconductor device 100 shown in Fig. 2a is tapered.

[0127] Fig. 8b is an enlarged view of region A4 in Fig. 8a. As shown in Fig. 8b, in the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered. In this example, the end F, the end F', and the end F''' may be the end portions of the tapered side surface of the interlayer insulating film 38 at positions that contact the protective insulating film 36 in the Z-axis direction.

[0128] Vertex P in this example is located on the more negative side in the Y-axis direction than vertex P in the example shown in Figure 2b. Vertex P' in this example is located on the more positive side in the Y-axis direction than vertex P' in the example shown in Figure 2b. Vertex P'' in this example is located on the more negative side in the Y-axis direction than vertex P'' in the example shown in Figure 2b.

[0129] In this example, the width Wss1' in the Y-axis direction from the vertex P' to the vertex P'' is the width in the Y-axis direction from the vertex P' of the interlayer insulating film 38 provided above the gate trench portion 40 to the vertex P'' of the interlayer insulating film 38 provided above the dummy trench portion 30. In this example, compared to the example shown in FIG. 2b, the vertex P' is provided on the positive side of the Y-axis direction and the vertex P'' is provided on the negative side of the Y-axis direction, so the width Wss1' is larger than the width Wss1 in the example shown in FIG. 2b.

[0130] In this example, the width Wsihu1' in the Y-axis direction from the vertex P to the vertex P' is the width in the Y-axis direction from the vertex P to the vertex P' of the interlayer insulating film 38 provided above the gate trench portion 40. In this example, compared to the example shown in FIG. 2b, the vertex P is provided on the negative side in the Y-axis direction and the vertex P' is provided on the positive side in the Y-axis direction, so the width Wsihu1' is smaller than the width Wsihd1.

[0131] In the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered, so that the contact provided in the contact hole 54 is more easily filled up to the bottom end of the contact hole 54 than in the semiconductor device 100 shown in FIG. 2b. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be further reduced than in the semiconductor device 100 shown in FIG. 2b. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be further reduced than in the semiconductor device 100 shown in FIG. 2b.

[0132] Fig. 9a is a diagram showing another example of the a-a' cross section in Fig. 1. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 3a in that the side surface of the interlayer insulating film 38 in the semiconductor device 100 shown in Fig. 3a is tapered.

[0133] Fig. 9b is an enlarged view of region A5 in Fig. 9a. As shown in Fig. 9b, in the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered. The positions in the Y-axis direction of the vertex P, vertex P', and vertex P'' in the semiconductor device 100 of this example are equal to the positions in the Y-axis direction of the vertex P, vertex P', and vertex P'' in the example shown in Fig. 8b, respectively.

[0134] In the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered, so that the contact provided in the contact hole 54 is more easily filled up to the bottom end of the contact hole 54 than in the semiconductor device 100 shown in FIG. 3b. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be further reduced than in the semiconductor device 100 shown in FIG. 3b. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be further reduced than in the semiconductor device 100 shown in FIG. 3b.

[0135] Fig. 10a is a diagram showing another example of the a-a' cross section in Fig. 1. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 4a in that the side surface of the interlayer insulating film 38 in the semiconductor device 100 shown in Fig. 4a is tapered.

[0136] Fig. 10b is an enlarged view of region A6 in Fig. 10a. As shown in Fig. 10b, in the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is provided in a tapered shape. The positions in the Y-axis direction of the vertex P, vertex P', and vertex P'' in the semiconductor device 100 of this example are equal to the positions in the Y-axis direction of the vertex P, vertex P', and vertex P'' in the examples shown in Figs. 8b and 9b, respectively.

[0137] In the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered, so that the contact provided in the contact hole 54 is more likely to be filled up to the bottom end of the contact hole 54 than in the semiconductor device 100 shown in FIG. 4b. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be further reduced than in the semiconductor device 100 shown in FIG. 4b. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be further reduced than in the semiconductor device 100 shown in FIG. 4b.

[0138] Fig. 11 is a diagram partially illustrating another example of the upper surface of the semiconductor device 100 according to this embodiment. The semiconductor device 100 illustrated in Fig. 11 is an example in which the width of the contact hole 54 in the Y-axis direction is smaller than that of the semiconductor device 100 illustrated in Fig. 1. The contact hole 54 may be provided spaced apart in the Y-axis direction from the gate trench portion 40 and the dummy trench portion 30 in the top view of Fig. 11.

[0139] Fig. 12a is a diagram showing an example of the b-b' cross section in Fig. 11. The semiconductor device 100 shown in Fig. 12a differs from the semiconductor device 100 shown in Fig. 2a in that the width in the Y-axis direction of the interlayer insulating film 38 is set equal to the width in the Y-axis direction of the protective insulating film 36 in the semiconductor device shown in Fig. 2a. The semiconductor device 100 shown in Fig. 12a also differs from the semiconductor device 100 shown in Fig. 2a in that the width in the Y-axis direction of the contact hole 54 is set smaller than that in the example shown in Fig. 2a.

[0140] Fig. 12b is an enlarged view of region B1 in Fig. 12a. In this example, width Wsihu2 is the width from vertex P to vertex P' of interlayer insulating film 38 in the Y-axis direction. Furthermore, width Wsihd2 is the width of interlayer insulating film 38 in the Y-axis direction at the position where interlayer insulating film 38 and protective insulating film 36 contact in the Z-axis direction. In this example, since the side surface of interlayer insulating film 38 is equal to the XZ plane, width Wsihu2 and width Wsihd2 are equal. Furthermore, width Wsihu2 and width Wsihd2 are equal to the width of the interlayer insulating film.

[0141] 12b, in the semiconductor device 100 of the present example, at the boundary between the interlayer insulating film 38 and the protective insulating film 36, the width Wsihd2 of the interlayer insulating film 38 in the Y-axis direction is equal to the width Wih of the protective insulating film 36 in the Y-axis direction. In addition, the width Wss2 in the Y-axis direction from the apex P' of the interlayer insulating film 38 provided above the gate trench portion 40 to the apex P'' of the interlayer insulating film 38 provided above the dummy trench portion 30 is equal to the width Wc of the contact hole 54.

[0142] In the semiconductor device 100 of this example, since the width Wiv is smaller than the width Wsiv, the protective insulating film 36 can be positioned more accurately in the direction parallel to the top surface 21 than the interlayer insulating film 38. Therefore, even if the first mesa portion 60 is further narrowed, a GE-to-GE short circuit can be prevented. Therefore, while preventing a GE-to-GE short circuit, the mesa width can be narrowed, and the on-voltage of the transistor portion 70 can be reduced by enhancing the IE effect.

[0143] In the semiconductor device 100 of this example, the protective insulating film 36 is in contact with the first mesa portion 60 and the width Wih is greater than the width Wt, so that it is possible to suppress a short circuit between the contact provided in the contact hole 54 and the gate conductive portion 44. That is, in the semiconductor device 100 of this example, the protective insulating film 36 protects the gate insulating film 42 and the gate conductive portion 44, so that it is possible to prevent a GE short circuit, i.e., a short circuit between the gate metal layer 50 and the emitter electrode 52.

[0144] Fig. 13a is a diagram showing another example of the b-b' cross section in Fig. 11. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 12a in that the protective insulating film 36 is not provided above the upper surface 21 in the semiconductor device 100 shown in Fig. 12a. In this example, the positions of the upper surfaces of the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64 are equal to the position of the upper surface of the protective insulating film 36 in the Z-axis direction.

[0145] Fig. 13b is an enlarged view of region B2 in Fig. 3a. As shown in Fig. 13b, in the semiconductor device 100 of this example, the position of the top surface of the first mesa portion 60 is equal to the position of the top surface of the protective insulating film 36 in the Z-axis direction. In this example, the width Wt, the width Wih' of the protective insulating film 36 in the Y-axis direction, and the width Wsihd2' of the interlayer insulating film 38 in the Y-axis direction at the position where the interlayer insulating film 38 and the protective insulating film 36 contact each other in the Z-axis direction are equal. In addition, the width Wsihu2 is greater than the width Wt, the width Wih', and the width Wsihd2'.

[0146] In the semiconductor device 100 of this example, since the width Wsihu2 is larger than the width Wt, it is possible to suppress a short circuit between the contact provided in the contact hole 54 and the gate conductive portion 44. That is, in the semiconductor device 100 of this example, since the protective insulating film 36 protects the gate insulating film 42 and the gate conductive portion 44, it is possible to prevent a GE short circuit, i.e., a short circuit between the gate metal layer 50 and the emitter electrode 52.

[0147] Fig. 14a is a diagram showing another example of the b-b' cross section in Fig. 11. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 12a in that the protective insulating film 36 is not provided below the upper surface 21 in the semiconductor device 100 shown in Fig. 12a. In this example, the positions of the upper surfaces of the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64 are equal to the position of the lower surface of the protective insulating film 36 in the Z-axis direction.

[0148] Fig. 14b is an enlarged view of a region B3 in Fig. 14a. In the semiconductor device 100 of this example, the position in the Z-axis direction of the upper surface of the gate conductive portion 44 and the position in the Z-axis direction of the upper surface of the gate insulating film 42 are equal to the position in the Z-axis direction of the upper surface 21. The protective insulating film 36 contacts the gate conductive portion 44 and the gate insulating film 42 at a position on the upper surface 21 in the Z-axis direction.

[0149] In the semiconductor device 100 of this example, the width Wsihd2 of the interlayer insulating film 38 in the Y-axis direction is equal to the width Wih of the protective insulating film 36 in the Y-axis direction at the boundary between the interlayer insulating film 38 and the protective insulating film 36. In addition, the width Wss2 in the Y-axis direction from the apex P' of the interlayer insulating film 38 provided above the gate trench portion 40 to the apex P'' of the interlayer insulating film 38 provided above the dummy trench portion 30 is equal to the width Wc of the contact hole 54.

[0150] In the semiconductor device 100 of this example, since the width Wiv is smaller than the width Wsiv, the protective insulating film 36 can be positioned more accurately in the direction parallel to the top surface 21 than the interlayer insulating film 38. Therefore, even if the first mesa portion 60 is further narrowed, a GE-to-GE short circuit can be prevented. Therefore, while preventing a GE-to-GE short circuit, the mesa width can be narrowed, and the on-voltage of the transistor portion 70 can be reduced by enhancing the IE effect.

[0151] Furthermore, in the semiconductor device 100 of this embodiment, the protective insulating film 36 is in contact with the first mesa portion 60 and has a width Wih larger than the width Wt, so that it is possible to suppress a short circuit between the contact provided in the contact hole 54 and the gate conductive portion 44. That is, in the semiconductor device 100 of this embodiment, the protective insulating film 36 protects the gate insulating film 42 and the gate conductive portion 44, so that it is possible to prevent a GE short circuit, i.e., a short circuit between the gate metal layer 50 and the emitter electrode 52.

[0152] Fig. 15a is a diagram showing another example of the b-b' cross section in Fig. 11. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 12a in that the side surface of the interlayer insulating film 38 in the semiconductor device 100 shown in Fig. 12a is tapered.

[0153] Fig. 15b is an enlarged view of a region B4 in Fig. 15a. As shown in Fig. 15b, in the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is provided in a tapered shape.

[0154] Vertex P in this example is located on the more negative side in the Y-axis direction than vertex P in the example shown in Fig. 12b. Vertex P' in this example is located on the more positive side in the Y-axis direction than vertex P' in the example shown in Fig. 12b. Vertex P'' in this example is located on the more negative side in the Y-axis direction than vertex P'' in the example shown in Fig. 12b.

[0155] In this example, the width Wss2' in the Y-axis direction from the vertex P' to the vertex P'' is the width in the Y-axis direction from the vertex P' of the interlayer insulating film 38 provided above the gate trench portion 40 to the vertex P'' of the interlayer insulating film 38 provided above the dummy trench portion 30. In this example, compared to the example shown in FIG. 12b, the vertex P' is provided on the positive side in the Y-axis direction and the vertex P'' is provided on the negative side in the Y-axis direction, so the width Wss2' is larger than the width Wss2 in the example shown in FIG. 12b. At the boundary where the interlayer insulating film 38 and the protective insulating film 36 contact each other, the width of the lower surface of the interlayer insulating film 38 in the Y-axis direction is equal to the width Wih of the protective insulating film 36 in the Y-axis direction.

[0156] In this example, the width Wsihu2' in the Y-axis direction from the vertex P to the vertex P' is the width in the Y-axis direction from the vertex P to the vertex P' of the interlayer insulating film 38 provided above the gate trench portion 40. In this example, compared to the example shown in FIG. 12b, the vertex P is provided on the negative side in the Y-axis direction and the vertex P' is provided on the positive side in the Y-axis direction, so the width Wsihu2' is smaller than the width Wsihd2.

[0157] In the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered, so that the contact provided in the contact hole 54 is more likely to be filled up to the bottom end of the contact hole 54 than in the semiconductor device 100 shown in FIG. 12b. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be further reduced than in the semiconductor device 100 shown in FIG. 12b. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be further reduced than in the semiconductor device 100 shown in FIG. 12b.

[0158] Fig. 16a is a diagram showing another example of the b-b' cross section in Fig. 11. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 13a in that the side surface of the interlayer insulating film 38 in the semiconductor device 100 shown in Fig. 13a is tapered.

[0159] Fig. 16b is an enlarged view of region B5 in Fig. 16a. As shown in Fig. 16b, in the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is provided in a tapered shape. The positions in the Y-axis direction of the vertex P, vertex P', and vertex P'' in the semiconductor device 100 of this example are equal to the positions in the Y-axis direction of the vertex P, vertex P', and vertex P'' in the example shown in Fig. 15b, respectively.

[0160] In the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered, so that the contact provided in the contact hole 54 is more likely to be filled up to the bottom end of the contact hole 54 than in the semiconductor device 100 shown in FIG. 13b. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be further reduced than in the semiconductor device 100 shown in FIG. 13b. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be further reduced than in the semiconductor device 100 shown in FIG. 13b.

[0161] Fig. 17a is a diagram showing another example of the b-b' cross section in Fig. 11. The semiconductor device 100 of this example differs from the semiconductor device 100 shown in Fig. 14a in that the side surface of the interlayer insulating film 38 in the semiconductor device 100 shown in Fig. 14a is tapered.

[0162] Fig. 17b is an enlarged view of a region B6 in Fig. 17a. As shown in Fig. 17b, in the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered. The positions in the Y-axis direction of the apex P, apex P', and apex P'' in the semiconductor device 100 of this example are equal to the positions in the Y-axis direction of the apex P, apex P', and apex P'' in the examples shown in Figs. 15b and 16b, respectively. In addition, at the boundary where the interlayer insulating film 38 and the protective insulating film 36 contact each other, the width of the lower surface of the interlayer insulating film 38 in the Y-axis direction is equal to the width Wih of the protective insulating film 36 in the Y-axis direction.

[0163] In the semiconductor device 100 of this example, the side surface of the interlayer insulating film 38 is tapered, so that the contact provided in the contact hole 54 is more likely to be filled up to the bottom end of the contact hole 54 than in the semiconductor device 100 shown in FIG. 14b. Therefore, in the first mesa portion 60, the contact resistance between the contact and the emitter region 12 can be further reduced than in the semiconductor device 100 shown in FIG. 14b. Also, in the first mesa portion 60, the contact resistance between the contact and the contact regions 15 provided on the positive and negative sides of the emitter region 12 in the X-axis direction can be further reduced than in the semiconductor device 100 shown in FIG. 14b.

[0164] Fig. 18a is a diagram showing an example of a method for manufacturing the semiconductor device 100 according to this embodiment. Fig. 18a is a diagram showing an example of a method for manufacturing the semiconductor device 100 shown in Fig. 2a and Fig. 2b.

[0165] In (a), the gate insulating film 42 and the gate conductive portion 44 in the upper portion of the gate trench portion 40 are formed below the upper surface 21, and a recess S is formed in the upper portion of the gate trench portion 40. Then, in (b) a first step, a protective insulating film 36 is formed on the semiconductor substrate 10. In this example, the protective insulating film 36 is formed so as to fill the recess S. Then, in (c) a second step, the protective insulating film 36 is patterned with a first mask 92 and etched to expose the upper surface 21 of the semiconductor substrate 10. Then, in (d) a third step, an interlayer insulating film 38 is formed on the protective insulating film 36. Then, in (e) a fourth step, the interlayer insulating film 38 is patterned with a second mask 94 and etched to expose the upper surface 21 of the semiconductor substrate 10 and the protective insulating film 36. The fourth step exposes a region of the protective insulating film 36 that is not covered by the interlayer insulating film 38 when viewed from above the semiconductor substrate 10. Next, in (f), the second mask 94 is removed, completing the semiconductor device 100 shown in FIGS. 2a and 2b.

[0166] In the manufacturing method of this example, the (c) second step and the (e) fourth step may be performed by dry etching. The etching gas in the dry etching may be CF4, SF6, or the like. When the (c) second step and the (e) fourth step are performed by dry etching, the etching gas in the (c) second step and the etching gas in the (e) fourth step may be different.

[0167] Fig. 18b is a diagram showing another example of the method for manufacturing the semiconductor device 100 according to this embodiment. Fig. 18b shows an example of the method for manufacturing the semiconductor device 100 shown in Figs. 8a and 8b.

[0168] In FIG. 18b, the fourth step (e) and the fourth step (f) are reprints of the fourth step (e) and the fourth step (f) in FIG. 18a. In the manufacturing method of the semiconductor device 100 of this example, after (f), in the fifth step (g), the side and upper surface of the interlayer insulating film 38 are etched by wet etching to make the side of the interlayer insulating film 38 tapered. The wet etching in the fifth step (g) may be performed using a hydrofluoric acid solution diluted to a predetermined concentration. Also, the wet etching in the fifth step (g) may be performed as a pretreatment before sputtering the emitter electrode 52.

[0169] Fig. 19 is a diagram showing another example of the manufacturing method of the semiconductor device 100 according to this embodiment. The manufacturing method of the semiconductor device 100 shown in Fig. 19 differs from the manufacturing method of the semiconductor device 100 shown in Fig. 18a in that CMP (Chemical Mechanical Polishing) is used instead of etching in the (b) second step in the example of the manufacturing method shown in Fig. 18a. Fig. 19 is an example of the manufacturing method for manufacturing the semiconductor device 100 shown in Fig. 3a and Fig. 3b.

[0170] In the manufacturing method of the semiconductor device 100 of this example, the protective insulating film 36 is polished by CMP in the (b') second step. By the (b') second step, the upper surface of the protective insulating film 36 becomes flush with the upper surface 21. Subsequently, the third and fourth steps are performed in the same manner as in FIG. 18a, and the semiconductor device 100 shown in FIG. 3a and FIG. 3b is completed.

[0171] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0172] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0173] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 16-1 accumulation region, 16-2 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 29 extension portion, 30 dummy trench portion, 31 connection portion, 32 dummy insulating film, 34 dummy conductive portion, 36 protective insulating film, 38 interlayer insulating film, 39 extension portion, 40 gate trench portion, 41 connection portion portion, 42 gate insulating film, 44 gate conductive portion, 48 gate runner, 49 contact hole, 50 gate metal layer, 52 emitter electrode, 54 contact hole, 56 contact hole, 58 barrier metal, 60 first mesa portion, 62 second mesa portion, 64 third mesa portion, 70 transistor portion, 80 diode portion, 82 cathode region, 90 boundary portion, 92 first mask, 94 second mask, 100 semiconductor device, 150 semiconductor device, 238 interlayer insulating film, 254 contact hole

Claims

1. A semiconductor device including a semiconductor substrate having a trench portion in which a conductive portion is provided, a first insulating film in contact with an upper surface of the trench portion and an upper surface of the semiconductor substrate; a second insulating film having a lower surface in contact with an upper surface of the first insulating film and made of a material different from that of the first insulating film; a metal electrode filled in a contact hole penetrating the first insulating film and the second insulating film; Equipped with In a cross section passing through the contact hole in the arrangement direction of the trench portion, The width of the lower surface of the second insulating film is smaller than the width of the upper surface of the first insulating film, and the metal electrode is in contact with the upper surface of the first insulating film. Semiconductor device.

2. The thickness of the first insulating film is smaller than the thickness of the second insulating film. The semiconductor device according to claim 1 .

3. The metal electrode has a barrier metal provided continuously on an upper surface and a side surface of the first insulating film and on an upper surface and a side surface of the second insulating film.

3. The semiconductor device according to claim 1 or 2.

4. The first insulating film is provided along a corner of the metal electrode. The semiconductor device according to claim 1 .

5. An upper surface of the conductive portion of the trench portion and an upper surface of the semiconductor substrate are provided parallel to each other. The semiconductor device according to claim 1 .

6. A semiconductor device including a semiconductor substrate having a trench portion in which a conductive portion is provided, a first insulating film in contact with an upper surface of the trench portion and an upper surface of the semiconductor substrate; a second insulating film having a lower surface in contact with an upper surface of the first insulating film and made of a material different from that of the first insulating film; a metal electrode filled in a contact hole penetrating the first insulating film and the second insulating film; Equipped with In a cross section passing through the contact hole in the arrangement direction of the trench portion, a width of a lower surface of the second insulating film is smaller than a width of an upper surface of the first insulating film, and the metal electrode is in contact with the upper surface of the first insulating film, The metal electrode has a barrier metal provided continuously on the upper surface and side surfaces of the first insulating film and on the upper surface and side surfaces of the second insulating film.

7. The metal electrode has a plug formed containing tungsten. The semiconductor device according to claim 1 .

8. The second insulating film has a tapered side surface formed in a tapered shape. The semiconductor device according to claim 1 .

9. The tapered side surface has a width in a depth direction that is greater than a width in the arrangement direction. The semiconductor device according to claim 8.

10. An upper surface of the first insulating film and an upper surface of the second insulating film are provided parallel to an upper surface of the conductive portion. The semiconductor device according to claim 1 .

11. An upper surface of the conductive portion is located at the same depth position as an upper surface of the semiconductor substrate. The semiconductor device according to claim 1 .

12. The trench portion has a third insulating film that insulates the conductive portion from the semiconductor substrate, The first insulating film has a lower oxygen content than the third insulating film. The semiconductor device according to claim 1 .

13. The first insulating film is made of SiN (silicon nitride), HfO ２ (Hafnium oxide), TiO ２ (Titanium oxide), Ta ２ O ５ (tantalum pentoxide), TiN (titanium nitride) and HfSiO (hafnium silicate). The semiconductor device according to claim 1 .

14. The second insulating film is PSG or BPSG. The semiconductor device according to claim 1 .

15. A semiconductor device comprising a semiconductor substrate having a trench portion, a metal electrode in contact with an upper surface side of the semiconductor substrate; a first insulating film made of silicon nitride (SiN), provided between the semiconductor substrate and the metal electrode, and in contact with the metal electrode; a second insulating film formed on an upper surface of the first insulating film and in contact with the metal electrode and the first insulating film; Equipped with The first insulating film is provided along a corner of the metal electrode. In a cross section in the arrangement direction, a width of a lower surface of the second insulating film is larger than a width of the conductive portion. The semiconductor device according to claim 1 .

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