Semiconductor memory device having contact plugs

Abstract

To provide a semiconductor memory element with a contact plug.SOLUTION: A semiconductor memory element includes: a substrate including a memory cell region where a plurality of active regions are defined and a peripheral circuit region where at least one logic active region is defined; a word line including a stack structure including a lower word line layer and an upper word line layer, crossing the active regions, and extending along a first horizontal direction, and an embedded insulating film on the word line; a bit line structure disposed on the active regions, extending in a second horizontal direction orthogonal to the first horizontal direction, including a bit line; and a word line contact plug penetrating the embedded insulating film, electrically connected to the word line, and including, on an upper part, a plug extension part having a larger horizontal width than a lower part.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a contact plug. [Background technology]

[0002] Due to the rapid development of the electronics industry and the demands of users, electronic devices are becoming smaller and lighter. Therefore, semiconductor memory devices used in electronic devices are also required to have a high degree of integration, and design rules related to the configuration of the semiconductor memory devices are becoming narrower. As a result, it is difficult to ensure the reliability of electrical connections between the components of the semiconductor memory devices. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS It is an object of the present invention to provide a semiconductor memory device having a contact plug capable of ensuring the reliability of electrical connection. [Means for solving the problem]

[0004] In order to achieve the above technical objectives, the present invention provides a semiconductor memory device as follows: The semiconductor memory device according to the present invention includes a substrate having a memory cell region in which a plurality of active regions are defined, and a peripheral circuit region in which at least one logic active region is defined; a word line having a stacked structure of a lower word line layer and an upper word line layer, crossing the plurality of active regions and extending along a first horizontal direction, and a buried insulating film on the word line; a bit line structure disposed on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug penetrating the buried insulating film and electrically connected to the word line, the upper portion of which has a plug extension portion having a horizontal width wider than that of a lower portion.

[0005] A semiconductor memory device according to the present invention includes a substrate having a memory cell region in which a plurality of active areas are defined, and a peripheral circuit region in which at least one logic active area is defined; a word line having a stacked structure of a lower word line layer and an upper word line layer, the word line extending along a first horizontal direction across the plurality of active areas, and a buried insulating film on the word line; a bit line structure disposed on the plurality of active areas, extending in a second horizontal direction perpendicular to the first horizontal direction, the bit line structure having a bit line; and a word line contact plug penetrating the buried insulating film and the upper word line layer to be electrically connected to the lower word line layer, the word line contact plug having an upper portion and a plug extension portion having a horizontal width wider than a lower portion; and a side surface of the word line contact plug is completely covered by the upper word line layer at a level between an upper surface and a lower surface of the upper word line layer.

[0006] A semiconductor memory device according to the present invention includes a substrate having a memory cell region in which a plurality of active regions are defined, and a peripheral circuit region in which at least one logic active region is defined; a plurality of word lines having a stacked structure of a lower word line layer and an upper word line layer, filling a plurality of word line trenches extending parallel to each other across the plurality of active regions in a first horizontal direction, and a plurality of buried insulating films on the plurality of word lines; a plurality of bit line structures disposed on the plurality of active regions, extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, each bit line having an insulating cap line covering the bit line; and a plurality of buried insulating films filling spaces between the plurality of bit line structures. a filled insulating layer having an upper portion and a plug extension portion having a horizontal width wider than a lower portion, the word line contact plug penetrating the filled insulating layer, the buried insulating film, and the upper word line layer to be connected to the lower word line layer, the word line contact plug having a side surface at a level between an upper surface and a lower surface of the upper word line layer completely covered by the upper word line layer; a plurality of buried contacts filling lower portions of spaces between the plurality of bit line structures and connected to the plurality of active regions; and a plurality of landing pads filling upper portions of spaces between the plurality of bit line structures and extending onto the plurality of bit line structures, the landing pads being made of the same material as the word line contact plug. Effect of the Invention

[0007] In the semiconductor memory device according to the present invention, since the word line contact plug has a plug extension portion at an upper portion having a horizontal width and horizontal area larger than that at a lower portion, the reliability of the electrical connection between the word line contact plug and the logic bit line is improved. Also, since the bottom surface of the word line contact hole may be lowered during the process of forming the hole extension portion to form the plug extension portion, a "not open" defect in which the word line is not exposed at the bottom of the word line contact hole can be prevented.

[0008] In addition, since the word line contact hole can be extended to the lower word line layer, the word line contact plug can be electrically connected to both the upper word line layer and the lower word line layer, thereby improving the reliability of the electrical connection between the word line contact plug and the word line. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic planar layout for explaining a main configuration of a semiconductor memory device according to an embodiment of the present invention; [Figure 2A] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 2B] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 2C] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 2D] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 2E] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 2F] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 2G] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 3A] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 3B] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 3C] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 3D] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 3E] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 3F] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 3G] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 4A] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 4B] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 4C] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 4D] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 4E] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 4F] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 4G] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 5A] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 5B] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 5C] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 5D] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 5E] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 5F]1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 5G] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 6A] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 6B] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 6C] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 6D] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 6E] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 6F] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 6G] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 7A] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 7B] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 7C] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 7D] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 7E] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 7F] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 7G]1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 8A] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 8B] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 8C] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 8D] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 8E] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 8F] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 8G] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 9A] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 9B] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 9C] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 9D] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 9E] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 9F] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 9G] 1A to 1C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor memory device according to an embodiment of the present invention. [Figure 10A]1A to 1C are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present invention in stages; [Figure 10B] 1A to 1C are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present invention in stages; [Figure 10C] 1A to 1C are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present invention in stages; [Figure 10D] 1A to 1C are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present invention in stages; [Figure 10E] 1A to 1C are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present invention in stages; [Figure 10F] 1A to 1C are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present invention in stages; [Figure 10G] 1A to 1C are cross-sectional views illustrating a semiconductor memory device according to an embodiment of the present invention in stages; [Figure 11] 1A and 1B are comparative views illustrating cross sections of contact plugs of semiconductor memory devices according to embodiments of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] FIG. 1 is a schematic planar layout for explaining a main configuration of a semiconductor memory device according to an embodiment of the present invention.

[0011] 1, a semiconductor memory device 1 includes a memory cell region CR and a peripheral circuit region PR. The semiconductor memory device 1 may include a plurality of active regions ACT formed in the memory cell region CR and a plurality of logic active regions ACTP formed in the peripheral circuit region PR.

[0012] In some embodiments, the active regions ACT arranged in the memory cell region CR are also arranged so as to have their major axes in a diagonal direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0013] A plurality of word lines WL may extend parallel to each other along a first horizontal direction (X direction) across a plurality of active regions ACT in the memory cell region CR. A plurality of bit lines BL may extend parallel to each other along a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction) on the plurality of word lines WL. The plurality of bit lines BL may be connected to the plurality of active regions ACT via direct contacts DC.

[0014] In some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines BL in the plurality of bit lines BL, and the plurality of buried contacts BC may be arranged in a line along each of a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0015] A plurality of landing pads LP may be formed on the plurality of buried contacts BC. The plurality of landing pads LP may be arranged to at least partially overlap the plurality of buried contacts BC. In some embodiments, each of the plurality of landing pads LP may extend onto one of two adjacent bit lines BL.

[0016] A plurality of storage nodes SN may be formed on the landing pads LP. The storage nodes SN may be formed above the bit lines BL. The storage nodes SN may be lower electrodes of a plurality of capacitors. The storage nodes SN may be connected to the active regions ACT via the landing pads LP and buried contacts BC.

[0017] The plurality of gate line patterns GLP may be disposed on the logic active region ACTP in the peripheral circuit region PR. In some embodiments, some of the plurality of gate line patterns GLP extend parallel to each other along a first horizontal direction (X direction) on the logic active region ACTP, and other parts of the plurality of gate line patterns GLP extend parallel to each other along a second horizontal direction (Y direction) on the logic active region ACTP, but are not limited thereto. For example, each of the plurality of gate line patterns GLP may have various widths, may have a bend, may have a varying width, and may extend in various horizontal directions.

[0018] In Fig. 1, components other than the logic active regions ACTP and the gate line patterns GLP in the peripheral circuit region PR are omitted for convenience of illustration. Also, in Fig. 1, the gate line patterns GLP are illustrated to be disposed only on the logic active regions ACTP, but are not limited thereto. For example, at least a portion of the gate line patterns GLP may be extended to the outside of the logic active regions ACTP, i.e., onto the logic element isolation film 115 (Figs. 2E to 2G).

[0019] The gate line patterns GLP may be formed at the same level as the bit lines BL. In some embodiments, the gate line patterns GLP and the bit lines BL may be made of the same material or at least a portion of the same material. For example, a process for forming all or a portion of the gate line patterns GLP and a process for forming all or a portion of the bit lines BL may be the same process.

[0020] Figures 2A to 2G, Figures 3A to 3G, Figures 4A to 4G, Figures 5A to 5G, Figures 6A to 6G, Figures 7A to 8G, and Figures 9A to 9G are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment of the present invention in stages, and Figures 10A to 10G are cross-sectional views showing a semiconductor memory device according to an embodiment of the present invention in stages. Specifically, FIGS. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A are cross-sectional views taken along a line A-A' in FIG. 1, FIGS. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are cross-sectional views taken along a line B-B' in FIG. 1, FIGS. 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, and 10C are cross-sectional views taken along a line C-C' in FIG. 1, and FIGS. 2D, 3D, 4D, 5D, 6D, 7D, 8D, 9D, and 10D are cross-sectional views cut at a position corresponding to line D-D' in Figure 1, Figures 2E, 3E, 4E, 5E, 6E, 7E, 8E, 9E and 10E are cross-sectional views cut at a position corresponding to line E-E' in Figure 1, Figures 2F, 3F, 4F, 5F, 6F, 7F, 8F, 9F and 10F are cross-sectional views cut at a position corresponding to line F-F' in Figure 1, and Figures 2G, 3G, 4G, 5G, 6G, 7G, 8G, 9G and 10G are cross-sectional views cut at a position corresponding to line G-G' in Figure 1.

[0021] 2A through 2G, an isolation trench 116T and a logic isolation trench 115T may be formed in a substrate 110, and an isolation layer 116 filling the isolation trench 116T and a logic isolation layer 115 filling the logic isolation trench 115T may be formed. In some embodiments, top surfaces of the substrate 110, the isolation layer 116, and the logic isolation layer 115 may be located at the same vertical level.

[0022] The substrate 110 may include, for example, silicon (Si), e.g., crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the substrate 110 may include at least one compound semiconductor selected from a semiconductor element such as germanium (Ge), SiGe, SiC, GaAs, InAs, and InP. Alternatively, the substrate 110 may have a silicon on insulator (SOI) structure. For example, the substrate 110 may include a buried oxide layer (BOX layer). The substrate 110 may include a conductive region, e.g., an impurity-doped well or an impurity-doped structure.

[0023] The device isolation film 116 and the logic device isolation film 115 may be made of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The device isolation film 116 may be a single layer made of one type of insulating film, a double layer made of two types of insulating films, or a multi-layer made of a combination of at least three types of insulating films. For example, the device isolation film 116 may be a double layer or a multi-layer made of an oxide film and a nitride film. However, according to the technical concept of the present invention, the configuration of the device isolation film 116 is not limited to the above. The device isolation film 116 may define a plurality of active regions 118 in the substrate 110 in the memory cell region CR (FIG. 1), and the logic device isolation film 115 may define a plurality of logic active regions 117 in the substrate 110 in the peripheral circuit region PR (FIG. 1).

[0024] In this specification, the portion of substrate 110 in which multiple active regions 118 are arranged and an adjacent portion thereof is referred to as a cell region CR, and the portion of substrate 110 in which multiple logic active regions 117 are arranged and an adjacent portion thereof is referred to as a peripheral circuit region PR.

[0025] In some embodiments, the isolation film 116 and the logic isolation film 115 may be formed together and may be referred to as an isolation structure. For example, the isolation film 116 and the logic isolation film 115 may be formed from the same material at the same time by the same process. The isolation film 116 may be a portion of the isolation structure that defines a plurality of active regions 118, and the logic isolation film 115 may be a portion of the isolation structure that defines a plurality of logic active regions 117. The portion of the isolation structure located at the boundary between the cell region CR and the peripheral circuit region PR may be the isolation film 116 or the logic isolation film 115, and the isolation film 116 and the logic isolation film 115 are not clearly distinguished from each other at the boundary between the cell region CR and the peripheral circuit region PR.

[0026] The active regions 118 may each have a relatively long island shape having a short axis and a long axis in a plan view, like the active region ACT illustrated in Fig. 1. The logic active regions 117 may each have a rectangular shape in a plan view, like the logic active region ACTP illustrated in Fig. 1, but this is merely an example and is not intended to be limiting, and the active regions 118 may have various planar shapes.

[0027] A plurality of word line trenches 120T may be formed in the substrate 110. The plurality of word line trenches 120T may have a line shape extending parallel to each other in a first horizontal direction (X direction), crossing the active region 118, and arranged at generally equal intervals along a second horizontal direction (Y direction). In some embodiments, a step may be formed on a bottom surface of the plurality of word line trenches 120T. In some embodiments, the plurality of word line trenches 120T may be formed by etching the device isolation film 116 and the substrate 110 in separate etching processes, so that the etching depth of the device isolation film 116 and the etching depth of the substrate 110 may be different from each other. In some embodiments, the plurality of word line trenches 120T may be formed by etching both the device isolation film 116 and the substrate 110, but due to a difference in etching rate between the device isolation film 116 and the substrate 110, the etching depth of the device isolation film 116 and the etching depth of the substrate 110 may be different from each other.

[0028] After cleaning the resultant structure in which the word line trenches 120T are formed, a plurality of gate dielectric layers 122, a plurality of word lines 120, and a plurality of buried insulating layers 124 may be sequentially formed inside the word line trenches 120T. The word lines 120 may constitute the word lines WL illustrated in FIG. 1. The word lines 120 may have a line shape extending in parallel in a first horizontal direction (X direction), crossing the active regions 118, and generally equally spaced apart along a second horizontal direction (Y direction). An upper surface of each of the word lines 120 may be located at a level lower than an upper surface of the substrate 110. A bottom surface of the word lines 120 may have an uneven shape, and a saddle fin structure transistor (saddle FinFET) may be formed in the active regions 118.

[0029] In this specification, the term "level" refers to a height in the vertical direction (Z direction) relative to the main surface or upper surface of the substrate 110. In other words, being located at the same level or at a constant level refers to a position having the same or constant height in the vertical direction (Z direction) relative to the main surface or upper surface of the substrate 110, and being located at a low / high level refers to a position having a low / high height in the vertical direction (Z direction) relative to the main surface of the substrate 110.

[0030] Each of the word lines 120 may have a stacked structure of a lower word line layer 120a and an upper word line layer 120b. For example, the lower word line layer 120a may be made of a metal material, a conductive metal nitride, or a combination thereof. In some embodiments, the lower word line layer 120a may be made of Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. For example, the upper word line layer 120b may be made of doped polysilicon. A lower surface of the upper word line layer 120b may contact an upper surface of the lower word line layer 120a. In some embodiments, the lower word line layer 120a may include a core layer and a barrier layer disposed between the core layer and the gate dielectric layer 122. For example, the core layer may be made of a metal material or a conductive metal nitride, such as W, WN, TiSiN, or WSiN, and the barrier layer may be made of a metal material or a conductive metal nitride, such as Ti, TiN, Ta, or TaN.

[0031] In some embodiments, before or after forming the word lines 120, impurity ions may be implanted into the active regions 118 of the substrate 110 on either side of the word lines 120 to form source and drain regions within the active regions 118.

[0032] The gate dielectric layer 122 may be at least one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO), and a high-k dielectric film having a higher dielectric constant than a silicon oxide layer. For example, the gate dielectric layer 122 may have a dielectric constant of about 10 to 25. In some embodiments, the gate dielectric 122 is made of at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO). For example, the gate dielectric 122 may be made of HfO. 2 , Al 2 O 3 , HfAlO 3 , Ta 2 O 3 or TiO 2 It may consist of.

[0033] The upper surfaces of the buried insulating layers 124 may be located at substantially the same level as the upper surface of the substrate 110. The buried insulating layers 124 may be made of at least one material layer selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. The lower surfaces of the buried insulating layers 124 may contact upper surfaces of the corresponding word lines 120.

[0034] 3A to 3G, insulating film patterns 112 and 114 are formed to cover an isolation film 116, a plurality of active regions 118, a plurality of buried insulating films 124, a logic isolation film 115, and a plurality of logic active regions 117. For example, the insulating film patterns 112 and 114 may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a metal-based dielectric film, or a combination thereof. In some embodiments, the insulating film patterns 112 and 114 may be formed by stacking a plurality of insulating films including a first insulating film pattern 112 and a second insulating film pattern 114. In some embodiments, the first insulating film pattern 112 may be formed of a silicon oxide film, and the second insulating film pattern 114 may be formed of a silicon oxynitride film.

[0035] In some embodiments, the first insulating film pattern 112 may be a non-metallic dielectric film, and the second insulating film pattern 114 may be a metallic dielectric film. For example, the first insulating film pattern 112 may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. For example, the second insulating film pattern 114 may be made of at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO).

[0036] Thereafter, a direct contact hole 134H is formed penetrating the insulating film patterns 112 and 114 to expose a source region in the active region 118. In some embodiments, the direct contact hole 134H may extend into the active region 118, i.e., into the source region. For example, the direct contact hole 134H may extend to a level lower than the top surface of the corresponding active region 118 and the device isolation layer 116.

[0037] 4A to 4G, a conductive layer for direct contact is formed on the active regions 118 and the isolation film 116 to fill the direct contact holes 134H and cover the insulating film patterns 112 and 114. The conductive layer for direct contact may be made of, for example, silicon (Si), germanium (Ge), tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or a combination thereof. In some embodiments, the conductive layer for direct contact may be made of an epitaxial silicon layer. In some embodiments, the conductive layer for direct contact may be made of doped polysilicon.

[0038] Thereafter, a metal-based conductive layer and an insulating capping layer are sequentially formed to cover the insulating film patterns 112 and 114 and the conductive layer for direct contact and to form a bit line structure 140.

[0039] In some embodiments, the metal-based conductive layer may have a laminated structure of a first metal-based conductive layer and a second metal-based conductive layer. The metal-based conductive layer may have a conductive layer laminated structure of a double layer structure, but this is merely an example and the technical concept of the present invention is not limited to the illustrated example. For example, the metal-based conductive layer may be formed as a single layer or a multi-layer structure of three or more layers.

[0040] The first metal conductive layer, the second metal conductive layer and the insulating capping layer are etched to form a plurality of bit lines 147 having a stacked structure of a line-shaped first metal conductive pattern 145 and a second metal conductive pattern 146, and a plurality of insulating capping lines 148.

[0041] In some embodiments, the first metal-based conductive pattern 145 is made of titanium nitride (TiN) or TSN (Ti-Si-N), and the second metal-based conductive pattern 146 is made of tungsten (W), or tungsten and tungsten silicide (WSi x In some embodiments, the first metal-based conductive pattern 145 may function as a diffusion barrier. In some embodiments, the plurality of insulating capping lines 148 may be made of a silicon nitride layer.

[0042] One bit line 147 and one insulating capping line 148 covering the bit line 147 may constitute one bit line structure 140. The bit lines 147 and the insulating capping lines 148 may extend parallel to each other in a second horizontal direction (Y direction) parallel to the main surface of the substrate 110. The bit lines 147 may constitute the bit lines BL illustrated in FIG. 1. In some embodiments, the bit line structure 140 may further include a conductive semiconductor pattern 132 disposed between the insulating film patterns 112 and 114 and the first metal-based conductive pattern 145. The conductive semiconductor pattern 132 may be made of doped polysilicon. In some embodiments, the conductive semiconductor pattern 132 may be omitted.

[0043] In an etching process for forming the plurality of bit lines 147, portions of the direct contact conductive layer that do not vertically overlap with the bit lines 147 may be removed to form a plurality of direct contact conductive patterns 134. At this time, the insulating film patterns 112 and 114 may function as an etch stop film in an etching process for forming the plurality of bit lines 147 and the plurality of direct contact conductive patterns 134. The plurality of direct contact conductive patterns 134 may constitute a plurality of direct contacts DC as exemplified in FIG. 1. The plurality of bit lines 147 may be electrically connected to the plurality of active regions 118 through the plurality of direct contact conductive patterns 134.

[0044] In some embodiments, a conductive semiconductor pattern 132 may be formed during the process of removing a portion of the conductive layer for direct contact to form the direct contact conductive pattern 134. For example, the conductive semiconductor pattern 132 may be a portion of the conductive layer for direct contact that vertically overlaps the bit line 147 but does not vertically overlap the direct contact hole 134H and is located on the insulating film patterns 112 and 114, and the direct contact conductive pattern 134 may be a portion of the conductive layer for direct contact that vertically overlaps the direct contact hole 134H and contacts the active region 118.

[0045] Both side walls of each of the plurality of bit line structures 140 may be covered with an insulating spacer structure 150. The plurality of insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may be made of a material having a lower dielectric constant than the first insulating spacer 152 and the third insulating spacer 156. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may be made of a nitride film, and the second insulating spacer 154 may be made of an oxide film. In some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may be made of a nitride film, and the second insulating spacer 154 may be made of a material having an etching selectivity with respect to the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 are made of a nitride film, the second insulating spacer 154 may be made of an oxide film, but may be removed in a subsequent process to become an air spacer.

[0046] A plurality of buried contact holes 170H may be formed between each of the plurality of bit lines 147. The internal space of the plurality of buried contact holes 170H may be defined between two adjacent bit lines 147 among the plurality of bit lines 147 by the insulating spacer structures 150 covering the sidewalls of each of the two adjacent bit lines 147 and the active region 118.

[0047] The buried contact holes 170H may be formed by removing portions of the insulating film patterns 112, 114 and the active region 118 using the insulating spacer structures 150 covering both sidewalls of the insulating capping lines 148 and the bit line structures 140 as an etching mask. In some embodiments, the buried contact holes 170H may be formed by first performing an anisotropic etching process to remove portions of the insulating film patterns 112, 114 and the active region 118 using the insulating spacer structures 150 covering both sidewalls of the insulating capping lines 148 and the bit line structures 140 as an etching mask, and then performing an isotropic etching process to further remove other portions of the active region 118, thereby expanding a space defined by the active region 118.

[0048] A plurality of gate line structures 140P may be formed on the logic active area 117. In some embodiments, at least one dummy bit line structure 140D may be disposed between the bit line structures 140 and the gate line structures 140P.

[0049] The gate line structure 140P may include a gate line 147P and an insulating capping line 148 covering the gate line 147P. The gate lines 147P included in the gate line structures 140P may be formed together with the bit lines 147. That is, the gate line 147P may have a stacked structure of a first metal-based conductive pattern 145 and a second metal-based conductive pattern 146. A gate insulating pattern 142 may be disposed between the gate line 147P and the logic active region 117. In some embodiments, the gate line structure 140P may further include a conductive semiconductor pattern 132 disposed between the gate insulating pattern 142 and the first metal-based conductive pattern 145. The gate lines 147P may constitute a gate line pattern GLP illustrated in FIG. 1.

[0050] The sidewalls of the gate line structures 140P may be covered with gate insulating spacers 150P. The gate insulating spacers 150P may be, for example, a nitride film. In some embodiments, the gate insulating spacers 150P may be formed of a single layer, but are not limited thereto, and may be formed of a multi-layer structure of two or more layers.

[0051] The dummy bitline structures 140D extend parallel to each other along the second horizontal direction (Y direction) together with the bitline structures 140. The dummy bitline structures 140D may have a structure generally similar to that of the bitline structures 140. The dummy bitline structures 140D may include a dummy bitline 147D including a first metal-based conductive pattern 145 and a second metal-based conductive pattern 146, and an insulating capping line 148. Sidewalls of the dummy bitline structures 140D may be covered by at least one of an insulating spacer structure 150 and a gate insulating spacer 150P.

[0052] In some embodiments, the horizontal width of the dummy bit line 147D in the first horizontal direction (X direction) may be greater than the horizontal width of the bit line 147. In other embodiments, the horizontal width of the dummy bit line 147D in the first horizontal direction (X direction) may be the same as the horizontal width of the bit line 147. In some embodiments, the dummy bit line structure 140D is a plurality of dummy bit line structures 140D, and the horizontal width of some of the dummy bit lines 147D in the first horizontal direction (X direction) may be greater than the horizontal width of the bit line 147, and the horizontal width of other of the dummy bit line structures 140D in the first horizontal direction (X direction) may be the same as the horizontal width of the bit line 147.

[0053] 5A to 5G, a plurality of buried contacts 170 and a plurality of insulating fences 180 are formed in spaces between a plurality of insulating spacer structures 150 covering both sidewalls of each of the plurality of bit line structures 140. The plurality of buried contacts 170 and the plurality of insulating fences 180 may be alternately arranged between a pair of insulating spacer structures 150 facing each other, i.e., along the second horizontal direction (Y direction), in the plurality of insulating spacer structures 150 covering both sidewalls of the plurality of bit line structures 140. For example, the plurality of buried contacts 170 may be made of polysilicon. For example, the plurality of insulating fences 180 may be made of a nitride film.

[0054] In some embodiments, the buried contacts 170 may be arranged in a line along a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the buried contacts 170 may extend in a vertical direction (Z direction) perpendicular to the substrate 110 on the active region 118. The buried contacts 170 may constitute the buried contacts BC illustrated in FIG.

[0055] The buried contacts 170 may be disposed in a space defined by the insulating fences 180 and the insulating spacer structures 150 covering both sidewalls of the bitline structures 140. The buried contacts 170 may fill a lower portion of the space between the insulating spacer structures 150 covering both sidewalls of each of the bitline structures 140.

[0056] The upper surface level of the plurality of buried contacts 170 can be located lower than the upper surface level of the plurality of insulating capping lines 148. The upper surfaces of the plurality of insulating fences 180 and the upper surfaces of the plurality of insulating capping lines 148 can be located at the same level in the vertical direction (Z direction).

[0057] A plurality of landing pad holes 190H may be defined by the plurality of insulating spacer structures 150 and the plurality of insulating fences 180. The plurality of landing pad holes 190H may overlap the plurality of buried contacts 170 in the vertical direction (Z direction). The plurality of buried contacts 170 may be exposed at the bottom surfaces of the plurality of landing pad holes 190H.

[0058] Filled insulating layers 172, 174 may be formed on the insulating film patterns 112, 114 around the plurality of gate line structures 140P. In some embodiments, the filled insulating layers 172, 174 may have a stacked structure of a first filled insulating layer 172 and a second filled insulating layer 174. In some embodiments, the first filled insulating layer 172 may be made of an oxide, and the second filled insulating layer 174 may be made of a nitride. The top surfaces of the filled insulating layers 172, 174, i.e., the top surface of the second filled insulating layer 174 and the top surface of the gate line structures 140P may have the same level.

[0059] In the process of forming the buried contacts 170 and / or the insulating fences 180, upper portions of the insulating capping lines 148, the insulating spacer structures 150, and the gate insulating spacers 150P included in the bit line structures 140, the dummy bit line structures 140D, and the gate line structures 140P may be removed, and the levels of the upper surfaces of the bit line structures 140, the dummy bit line structures 140D, and the gate line structures 140P may be lowered.

[0060] 6A to 6G, a plurality of contact holes CPHE, CPHF, CPHG are formed penetrating the filled insulating layers 172, 174 and the insulating film patterns 112, 114. The plurality of contact holes CPHE, CPHF, CPHG may include a first contact hole CPHE, a second contact hole CPHF, and a third contact hole CPHG. The third contact hole CPHG may include a gate line contact hole CPHG1 and a bit line contact hole CPHG2. The first contact hole CPHE and the second contact hole CPHF are also referred to as a word line contact hole CPHE and a logic active region contact hole CPHF, respectively.

[0061] The word line contact holes CPHE may extend through the filled insulating layers 172 and 174, the insulating film patterns 112 and 114, the buried insulating film 124, and the upper word line layer 120b to the lower word line layer 120a. In some embodiments, the word line contact holes CPHE may extend into the lower word line layer 120a.

[0062] The logic active area contact holes CPHF may extend through the filled insulating layers 172, 174 and the insulating film patterns 112, 114 to the logic active areas 117. In some embodiments, the logic active area contact holes CPHF may extend into the logic active areas 117.

[0063] In some embodiments, the third contact holes CPHG, i.e., the gate line contact hole CPHG1 and the bit line contact hole CPHG2, may pass through the insulating capping line 148 and the second metal-based conductive pattern 146 and extend to the first metal-based conductive pattern 145. In some embodiments, the third contact holes CPHG, i.e., the gate line contact hole CPHG1 and the bit line contact hole CPHG2, may extend into the first metal-based conductive pattern 145. In other embodiments, the third contact holes CPHG, i.e., the gate line contact hole CPHG1 and the bit line contact hole CPHG2, may pass through the insulating capping line 148 and extend to the second metal-based conductive pattern 146. In other embodiments, the third contact holes CPHG, i.e., the gate line contact hole CPHG1 and the bit line contact hole CPHG2, may extend into the second metal-based conductive pattern 146.

[0064] That is, the gate line contact hole CPHG1 may pass through the insulating capping line 148 and extend into the gate line 147P, and the bit line contact hole CPHG2 may pass through the insulating capping line 148 and extend into the bit line 147. In some embodiments, the gate line contact hole CPHG1 may pass through the insulating capping line 148 and extend into the gate line 147P, and the bit line contact hole CPHG2 may pass through the insulating capping line 148 and extend into the bit line 147.

[0065] In some embodiments, the first contact hole CPHE, the second contact hole CPHF, and the third contact hole CPHG may be simultaneously formed by the same etching process, while in other embodiments, at least one of the first contact hole CPHE, the second contact hole CPHF, and the third contact hole CPHG may be sequentially formed by separate etching processes.

[0066] 7A to 7G, an extension mask pattern MKE is formed having an extension opening MKEO exposing the first contact hole CPHE and a portion of the filled insulating layer 172, 174 adjacent to the first contact hole CPHE. The extension mask pattern MKE may cover remaining portions of the filled insulating layer 172, 174. The extension mask pattern MKE may fill the second contact hole CPHF and the third contact hole CPHG, and cover the bit line structure 140, the dummy bit line structure 140D, the gate line structure 140P, the buried contact 170, and the insulating fence 180.

[0067] Thereafter, the filled insulating layers 172 and 174 exposed by the extended openings MKEO may be removed using the extended mask pattern MKE as an etching mask to form hole extensions HE (FIG. 8E) in the upper portions of the first contact holes CPHE. After the hole extensions HE are formed, the extended mask pattern MKE may be removed. In the process of forming the hole extensions HE, the bottom vertical level of the first contact holes CPHE may be lowered.

[0068] Referring to Figures 8A to 8G together, after forming the hole extension portion HE, the landing pad holes 190H and the contact holes CPHE, CPHF, and CPHG are filled to form a landing pad material layer 190P covering the bit line structures 140, the gate line structures 140P, and at least one dummy bit line structure 140D.

[0069] The hole extension HE may be formed by removing a portion of the filled insulating layers 172 and 174. The hole extension HE may expand the horizontal width and horizontal cross-sectional area of ​​the upper portion of the first contact hole CPHE. The bottom surface of the hole extension HE may have a vertical level higher than the top surface of the bit line 147 or the gate line 147P, i.e., the first vertical level LV1 of the top surface of the second metal-based conductive pattern 146. That is, the vertical level of the bottom surface of the hole extension HE is higher than the first vertical level LV1 of the top surface of the second metal-based conductive pattern 146 and lower than the top surface of the insulating capping line 148 or the top surfaces of the filled insulating layers 172 and 174, i.e., the second vertical level LV2 of the top surface of the second filled insulating layer 174. In some embodiments, the bottom surface of the hole extension HE may have a vertical level lower than the top surface of the first filled insulating layer 172.

[0070] In some embodiments, the landing pad material layer 190P may be comprised of a conductive barrier layer and a conductive pad material layer on the conductive barrier layer. For example, the conductive barrier layer may be comprised of a metal, a conductive metal nitride, or a combination thereof. In some embodiments, the conductive barrier layer may be comprised of a Ti / TiN stack structure. In some embodiments, the conductive pad material layer may include tungsten (W).

[0071] In some embodiments, prior to forming the landing pad material layer 190P, a metal silicide layer may be formed on the buried contacts 170. The metal silicide layer may be disposed between the buried contacts 170 and the landing pad material layer 190P. The metal silicide layer may be comprised of, but is not limited to, cobalt silicide (CoSix), nickel silicide (NiSix), or manganese silicide (MnSix).

[0072] A plurality of hard mask patterns HMKC, HMKP are formed on the landing pad material layer 190P. In some embodiments, the plurality of hard mask patterns HMKC, HMKP may be formed through an extreme ultraviolet (EUV) lithography process. The plurality of hard mask patterns HMKC, HMKP may include a cell hard mask pattern HMKC disposed on the plurality of landing pad holes 190H and the surrounding portions of the landing pad material layer 190P, and a logic hard mask pattern HMKP disposed on the plurality of contact holes CPHE, CPHF, CPHG and the surrounding portions of the landing pad material layer 190P.

[0073] 9A to 9G, using the cell hard mask pattern HMKC as an etching mask, portions of the bit line structures 140 and portions of the landing pad material layer 190P (FIGS. 8A to 8G) are removed, and at least a portion of the landing pad holes 190H are filled to form a plurality of landing pads 190 extending over the bit line structures 140 and separated by recessed portions 190R. The landing pads 190 are spaced apart from one another with the recessed portions 190R interposed therebetween. Also, using the cell hard mask pattern HMKC as an etching mask, portions of each of the insulating fences 180 may be removed.

[0074] The landing pads 190 may be disposed on the buried contacts 170 and may extend over the bit line structures 140. In some embodiments, the landing pads 190 may extend over the bit lines 147. The landing pads 190 may be disposed on the buried contacts 170 and may be electrically coupled to the corresponding buried contacts 170. The landing pads 190 may be coupled to the active region 118 via the buried contacts 170. The landing pads 190 may constitute the landing pads LP illustrated in FIG. 1.

[0075] The buried contact 170 may be disposed between two adjacent bit line structures 140, and the landing pad 190 may extend from between the two adjacent bit line structures 140 across the buried contact 170 onto one of the bit line structures 140.

[0076] In addition, a portion of the landing pad material layer 190P is removed using the logic hard mask pattern HMKP as an etching mask to form a plurality of logic bit lines BLP and a plurality of contact plugs CPE, CPF, and CPG filling the plurality of contact holes CPHE, CPHF, and CPHG, respectively. The logic bit lines BLP may be a portion of the landing pad material layer 190P above the second vertical level LV2 on the plurality of contact plugs CPE, CPF, and CPG.

[0077] The contact plugs CPE, CPF, CPG may include a plurality of first contact plugs CPE, a plurality of second contact plugs CPF, and a plurality of third contact plugs CPG. The third contact plugs CPG may include a plurality of gate line contact plugs CPG1, and a plurality of bit line contact plugs CPG2. The first contact plugs CPE and the second contact plugs CPF are also referred to as word line contact plugs CPE and logic active region contact plugs CPF, respectively.

[0078] The word line contact plugs CPE may pass through the filled insulating layers 172 and 174 covering a portion of the upper surface of the word lines 120, the insulating film patterns 112 and 114, the buried insulating film 124, and the upper word line layer 120b, and may extend to the lower word line layer 120a.

[0079] The word line contact plug CPE may have a plug extension portion PE. The plug extension portion PE may be a portion of the word line contact plug CPE that fills the hole extension portion HE. The plug extension portion PE may expand the horizontal width and horizontal cross-sectional area of ​​an upper portion of the word line contact plug CPE. The bottom surface of the plug extension portion PE may have a vertical level higher than a first vertical level LV1 of the upper surface of the second metal-based conductive pattern 146. That is, the vertical level of the bottom surface of the plug extension portion PE is higher than the first vertical level LV1 of the upper surface of the second metal-based conductive pattern 146 and lower than a second vertical level LV2 of the upper surface of the insulating capping line 148.

[0080] The side of the word line contact plug CPE portion adjacent to the upper surface of the lower word line layer 120a may be surrounded by the upper word line layer 120b. That is, at a level corresponding to the upper word line layer 120b, i.e., a level between the upper surface and the lower surface of the upper word line layer 120b, the side of the word line contact plug CPE portion may be completely covered by the upper word line layer 120b.

[0081] The logic active region contact plugs CPF may extend to the logic active region 117 through the filled insulating layers 172 and 174 and the insulating film patterns 112 and 114 .

[0082] In some embodiments, the third contact plugs CPG, i.e., the gate line contact plugs CPG1 and the bit line contact plugs CPG2, may penetrate the insulating capping line 148 and the second metal-based conductive pattern 146 and extend to the first metal-based conductive pattern 145. In other embodiments, the third contact plugs CPG, i.e., the gate line contact plugs CPG1 and the bit line contact plugs CPG2, may penetrate the insulating capping line 148 and extend to the second metal-based conductive pattern 146. That is, the gate line contact plugs CPG1 may penetrate the insulating capping line 148 and extend to the gate line 147P, and the bit line contact plugs CPG2 may penetrate the insulating capping line 148 and extend to the bit line 147.

[0083] The plurality of landing pads 190, the plurality of logic bit lines BLP, the first contact plugs CPE, the second contact plugs CPF, and the third contact plugs CPG may be simultaneously formed by the same etching process using the cell hard mask pattern HMKC and the logic hard mask pattern HMKP as an etching mask.

[0084] 10A to 10G, a semiconductor memory device 1 including a plurality of capacitor structures 200 may be formed by sequentially forming a plurality of lower electrodes 210, a capacitor dielectric layer 220, and an upper electrode 230 on a plurality of landing pads 190. Each of the lower electrodes 210 may correspond to and be electrically connected to each of the landing pads 190. The capacitor dielectric layer 220 may conformally cover the lower electrodes 210. The upper electrode 230 may cover the capacitor dielectric layer 220. The upper electrode 230 may face the lower electrode 210 with the capacitor dielectric layer 220 interposed therebetween. The capacitor dielectric layer 220 and the upper electrode 230 may be integrally formed to cover the lower electrodes 210 together in a certain region, for example, in one memory cell region CR. The lower electrodes 210 may constitute a plurality of storage nodes SN illustrated in FIG. 1.

[0085] Each of the lower electrodes 210 may have a pillar shape, i.e., a shape filled with a circular horizontal cross section, but is not limited thereto. In some embodiments, each of the lower electrodes 210 may have a cylindrical shape with a closed bottom. In some embodiments, the lower electrodes 210 may be arranged in a honeycomb shape arranged in a zigzag pattern in a first horizontal direction (X direction) or a second horizontal direction (Y direction). In other embodiments, the lower electrodes 210 may be arranged in a matrix shape arranged in a line along each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). The lower electrodes 210 may be formed of, for example, silicon doped with impurities, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride. Although not separately illustrated, the semiconductor memory device 1 may further include at least one support pattern in contact with a sidewall of the lower electrodes 210.

[0086] The capacitor dielectric film 220 can be composed of, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0087] The top electrode 230 can be made of, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof.

[0088] Before forming the plurality of capacitor structures 200, an insulating structure 195 may be formed to fill the recessed portion 190R. In some embodiments, the insulating structure 195 may include an interlayer insulating layer and an etch stop layer. For example, the interlayer insulating layer may be an oxide layer, and the etch stop layer may be a nitride layer. In FIGS. 10A and 10C, the upper surface of the insulating structure 195 and the lower surface of the lower electrode 210 are illustrated to be at the same level, but are not limited thereto. For example, the upper surface level of the insulating structure 195 may be higher than the lower surface level of the lower electrode 210, and the lower electrode 210 may extend into the insulating structure 195 toward the substrate 110.

[0089] A buried insulating layer 250 may be filled on the logic bit lines BLP corresponding to the level where the capacitor structures 200 are located. The buried insulating layer 250 may be formed of, for example, an oxide layer or an ultra low K (ULK) layer. The oxide layer may be formed of borophosphosilicate (BPSG) or the like. glass) membrane, PSG (phosphosilicate glass) membrane, BSG (borosilicate glass) membrane, USG (un-doped silicate glass) membrane, TEOS (tetraethyl orthosilicate) membrane or HDP (high The ULK film may be formed of any one selected from a SiOC film and a SiCOH film having an ultra low dielectric constant K of, for example, 2.2 to 2.4.

[0090] The semiconductor memory device 1 includes a substrate 110 having a plurality of active regions 118 and a plurality of logic active regions 117; a plurality of gate dielectric films 122, a plurality of word lines 120, and a plurality of buried insulating films 124 sequentially formed within a plurality of word line trenches 120T crossing the plurality of active regions 118 in the substrate 110; insulating film patterns 112, 114 covering an isolation film 116, the plurality of active regions 118, and the plurality of buried insulating films 124; a plurality of bit line structures 140 and a plurality of insulating spacer structures 150 covering both side walls of the plurality of bit line structures 140 on the insulating film patterns 112, 114; On 117, there are included a plurality of gate line structures 140P, a plurality of gate insulating spacers 150P covering both side walls of the plurality of gate line structures 140P, a plurality of insulating fences 180, and a plurality of landing pads 190 filling a lower portion of a space defined by the plurality of insulating spacer structures 150, filling an upper portion and a plurality of buried contacts 170 connected to the plurality of active regions 118, and extending to an upper portion of the bit line structure 140; and a plurality of capacitor structures 200 consisting of a plurality of lower electrodes 210, a capacitor dielectric film 220, and an upper electrode 230 connected to the plurality of landing pads 190.

[0091] The insulating fences 180 may be disposed spaced apart from each other along a pair of opposing insulating spacer structures 150, i.e., along the second horizontal direction (Y direction), among the insulating spacer structures 150 covering both sidewalls of the bit line structures 140. Each of the insulating fences 180 may extend from between the buried contacts 170 to between the landing pads 190.

[0092] The semiconductor memory device 1 may further include word line contact plugs CPE, logic active region contact plugs CPF, gate line contact plugs CPG1, and bit line contact plugs CPG2. The word line contact plugs CPE, logic active region contact plugs CPF, gate line contact plugs CPG1, and bit line contact plugs CPG2 may be made of the same material.

[0093] 10A to 10G, one each of the word line contact plug CPE, the gate line contact plug CPG1, and the bit line contact plug CPG2 and two logic active region contact plugs CPF are illustrated, but are merely examples and are not limited thereto. For example, the semiconductor memory device 1 may include a plurality of word line contact plugs CPE, a plurality of gate line contact plugs CPG1, a plurality of bit line contact plugs CPG2, and a plurality of logic active region contact plugs CPF corresponding to a plurality of word lines 120, a plurality of gate lines 147P, a plurality of bit lines 147, and a plurality of logic active regions 117.

[0094] The word line contact plugs CPE may penetrate the filled insulating layers 172 and 174, the insulating film patterns 112 and 114, the buried insulating film 124, and the upper word line layer 120b, and may be connected to the lower word line layer 120a. The logic active region contact plugs CPF may penetrate the filled insulating layers 172 and 174 and the insulating film patterns 112 and 114, and may be connected to the logic active region 117.

[0095] The gate line contact plug CPG1 may penetrate the insulating capping line 148 and be connected to the gate line 147P, and the bit line contact plug CPG2 may penetrate the insulating capping line 148 and be connected to the bit line 147. In some embodiments, the word line contact plug CPG1 and the bit line contact plug CPG2 may penetrate the insulating capping line 148 and the second metal-based conductive pattern 146 and be connected to the first metal-based conductive pattern 145. In other embodiments, the gate line contact plug CPG1 and the bit line contact plug CPG2 may penetrate the insulating capping line 148 and be connected to the second metal-based conductive pattern 146.

[0096] A plurality of logic bitlines BLP may be disposed on the insulating capping line 148 and the filling insulating layers 172 and 174. Each of the word line contact plugs CPE, the logic active region contact plugs CPF, the gate line contact plugs CPG1, and the bit line contact plugs CPG2 may be connected to at least one of the plurality of logic bitlines BLP. In some embodiments, the word line contact plugs CPE, the logic active region contact plugs CPF, the gate line contact plugs CPG1, and the bit line contact plugs CPG2 may be made of the same material as the plurality of logic bitlines BLP and may be integrated with each other. In some embodiments, the word line contact plugs CPE, the logic active region contact plugs CPF, the gate line contact plugs CPG1, and the bit line contact plugs CPG2 may be made of the same material as the plurality of landing pads 190.

[0097] In the semiconductor memory device 1 according to the present invention, since the word line contact plug CPE has a plug extension part PE having a horizontal width and horizontal area at an upper part thereof larger than that at a lower part thereof, the reliability of the electrical connection between the word line contact plug CPE and the logic bit line BLP may be improved. Also, in the process of forming the hole extension part HE to form the plug extension part PE, the bottom surface of the word line contact hole CPHE becomes lower, thereby preventing a not-open defect in which the word line 120 is not exposed at the bottom surface of the word line contact hole CPHE.

[0098] In addition, the word line contact hole CPHE is extended to the lower word line layer 120a, and the word line contact plug CPE contacts both the upper word line layer 120b and the lower word line layer 120a and is electrically connected to both the upper word line layer 120b and the lower word line layer 120a. Therefore, the reliability of the electrical connection between the word line contact plug CPE and the word line 120 may be improved.

[0099] FIG. 11 is a comparative cross-sectional view illustrating cross sections of contact plugs of a semiconductor memory device according to an embodiment of the present invention.

[0100] 11 together with FIGS. 10A to 10G, the semiconductor memory device 1 may include a first contact plug CPE, a second contact plug CPF, and a third contact plug CPG. The first contact plug CPE and the second contact plug CPF may also be referred to as a word line contact plug CPE and a logic active region contact plug CPF, respectively. The third contact plug CPG may include a gate line contact plug CPG1 and a bit line contact plug CPG2. The gate line contact plug CPG1 and the bit line contact plug CPG2 have substantially the same shape except that they are connected to the gate line 147P and the bit line 147, respectively. Therefore, in FIG. 11, the third contact plug CPG will be described with reference to a cross section of a portion related to the bit line contact plug CPG2, and a description of the gate line contact plug CPG1 will be omitted.

[0101] The word line contact plug CPE may extend from the logic bit line BLP to the lower word line layer 120a by passing through the filled insulating layers 172 and 174 covering a portion of the upper surface of the word line 120, the insulating film patterns 112 and 114, the buried insulating film 124, and the upper word line layer 120b.

[0102] The word line contact plug CPE may have a plug extension portion PE. The plug extension portion PE may expand the horizontal width and horizontal cross-sectional area of ​​an upper portion of the word line contact plug CPE. The bottom surface of the plug extension portion PE may have a vertical level higher than a first vertical level LV1 of the upper surface of the second metal-based conductive pattern 146. That is, the vertical level of the bottom surface of the plug extension portion PE is higher than the first vertical level LV1 of the upper surface of the second metal-based conductive pattern 146 and lower than a second vertical level LV2 of the upper surface of the insulating capping line 148.

[0103] The side of the word line contact plug CPE portion adjacent to the upper surface of the lower word line layer 120a may be completely surrounded by the upper word line layer 120b. That is, at a level corresponding to the upper word line layer 120b, i.e., a level between the upper surface and the lower surface of the upper word line layer 120b, the side of the word line contact plug CPE portion may be entirely covered by the upper word line layer 120b.

[0104] The logic active region contact plugs CPF may extend from the logic bit lines BLP to the logic active regions 117 through the filled insulating layers 172 and 174 and the insulating film patterns 112 and 114 .

[0105] The third contact plugs CPG, i.e., the gate line contact plugs CPG1, may pass through the insulating capping lines 148 and extend to the gate lines 147P, and the bit line contact plugs CPG2 may pass through the insulating capping lines 148 and extend to the bit lines 147. In some embodiments, the third contact plugs CPG, i.e., the gate line contact plugs CPG1 and the bit line contact plugs CPG2, may pass through the insulating capping lines 148 and the second metal-based conductive pattern 146 and extend from the logic bit lines BLP to the first metal-based conductive pattern 145. In other embodiments, the third contact plugs CPG, i.e., the gate line contact plugs CPG1 and the bit line contact plugs CPG2, may pass through the insulating capping lines 148 and extend from the logic bit lines BLP to the second metal-based conductive pattern 146.

[0106] The ratio (WEH / WEL) of the horizontal width WEH at the second vertical level LV2 to the horizontal width WEL at the first vertical level LV1 of the word line contact plug CPE may be greater than the ratio (WFH / WFL) of the horizontal width WFH at the second vertical level LV2 to the horizontal width WFL at the first vertical level LV1 of the logic active area contact plug CPF, and the ratio (WGH / WGL) of the horizontal width WGH at the second vertical level LV2 to the horizontal width WGL at the first vertical level LV1 of the third contact plug CPG, i.e., the gate line contact plug CPG1 and the bit line contact plug CPG2.

[0107] In some embodiments, the extension length of the word line contact plug CPE from the logic bit line BLP toward the substrate 110 may be greater than the extension length of the logic active area contact plug CPF, which may be greater than the extension length of the third contact plug CPG, i.e., the gate line contact plug CPG1 and the bit line contact plug CPG2.

[0108] In some embodiments, the horizontal width WFL of the logic active area contact plug CPF at the first vertical level LV1 may have a value larger than the horizontal width WEL of the word line contact plug CPE at the first vertical level LV1, and the horizontal width WEL of the word line contact plug CPE at the first vertical level LV1 may have a value larger than the horizontal width WGL of the third contact plug CPG, i.e., the gate line contact plug CPG1 and the bit line contact plug CPG2, at the first vertical level LV1, but is not limited thereto.

[0109] The present invention has been described in detail above by giving preferred embodiments. However, the present invention is not limited to these embodiments, and various modifications and changes may be made by those skilled in the art within the technical spirit and scope of the present invention. [Explanation of symbols]

[0110] 1. Semiconductor memory element 110 Substrate 112 First insulating film pattern 114 Second insulating film pattern 115 Logic device isolation film 116 Element Isolation Film 117 Logic Active Areas 118 Active region 120,WL Word Line 120a Lower word line layer 120b Upper word line layer 120T Word Line Trench 122 Gate dielectric film 124 Buried insulating film 140 Bit Line Structure 147,BL bit line 140D Dummy bit line structure 140P Gate Line Structure 147P Gate Line 150 Insulating spacer structure 170,BC embedded contact 180 Insulation Fence 190,LP Landing Pad 200 Capacitor structure 210 Lower electrode 220 Capacitor Dielectric Film 230 Upper electrode CPE first contact plug, word line contact plug CPF second contact plug, logic active region contact plug CPG 3rd Contact Plug CPG1 Gate Line Contact Plug CPG2 bit line contact plug CR memory cell area DR Dam Area PR peripheral circuit area

Claims

1. a substrate having a memory cell region having a plurality of active areas defined therein and a peripheral circuit region having at least one logic active area defined therein; a word line having a stacked structure of a lower word line layer and an upper word line layer, the word line extending in a first horizontal direction across the active regions, and a buried insulating layer on the word line; a bit line structure disposed on the plurality of active regions and extending in a second horizontal direction perpendicular to the first horizontal direction, the bit line structure including a bit line and an insulating capping line covering the bit line, the bit line having a stacked structure of a first metal-based conductive pattern and a second metal-based conductive pattern; a gate line structure disposed on the at least one logic active region, the gate line having a stacked structure of the first metal-based conductive pattern and the second metal-based conductive pattern, and the insulating capping line covering the gate line; a fill insulating layer filling a space between the bit line structure and the gate line structure; a word line contact plug penetrating both the filled insulating layer and the buried insulating film, electrically connected to the word line, extending into the word line, and having an upper portion and a plug extension portion having a horizontal width greater than a lower portion.

2. 2. The semiconductor memory device of claim 1, wherein the word line contact plug penetrates the buried insulating layer and the upper word line layer and extends to the lower word line layer.

3. 3. The semiconductor memory device of claim 2, wherein a side of a portion of the word line contact plug adjacent to an upper surface of the lower word line layer is surrounded by the upper word line layer.

4. 2. The semiconductor memory device of claim 1, wherein the bit line structure further comprises a bit line contact plug passing through the insulating capping line and electrically connected to the bit line.

5. The semiconductor memory element of claim 4, further comprising a gate line contact plug penetrating the insulating capping line and electrically connected to the gate line.

6. 6. The semiconductor memory device of claim 5, further comprising a logic active region contact plug penetrating the filling insulating layer and electrically connected to the logic active region.

7. a plurality of logic bitlines disposed on the filled insulating layer and on the insulating capping line; 7. The semiconductor memory device of claim 6, wherein each of the word line contact plugs, the logic active region contact plugs, the bit line contact plugs and the gate line contact plugs is connected to at least one of the plurality of logic bit lines.

8. 8. The semiconductor memory device of claim 7, wherein each of the word line contact plugs, the logic active region contact plugs, the bit line contact plugs and the gate line contact plugs is integral with at least one of the plurality of logic bit lines to which it is connected.

9. 7. The semiconductor memory device of claim 6, wherein a vertical level of a bottom surface of the plug extension is higher than a first vertical level of an upper surface of the bit line and lower than a second vertical level of an upper surface of the insulating capping line.

10. 10. The semiconductor memory device of claim 9, wherein a ratio of a horizontal width at the second vertical level of the word line contact plug to a horizontal width at the first vertical level is greater than a ratio of a horizontal width at the second vertical level of each of the logic active region contact plugs, the bit line contact plugs, and the gate line contact plugs to their horizontal widths at the first vertical level.

11. a substrate having a memory cell region having a plurality of active areas defined therein and a peripheral circuit region having at least one logic active area defined therein; a word line having a stacked structure of a lower word line layer and an upper word line layer, the word line extending in a first horizontal direction across the active regions, and a buried insulating layer on the word line; a bit line structure disposed on the plurality of active regions and extending in a second horizontal direction perpendicular to the first horizontal direction, the bit line structure having a bit line; a gate line structure disposed on the at least one logic active area and having a gate line; a fill insulating layer filling a space between the bit line structure and the gate line structure; a word line contact plug extending into the lower word line layer, the word line contact plug extending through the filled insulating layer, the buried insulating film, and the upper word line layer, the word line contact plug being electrically connected to the lower word line layer, the word line contact plug having an upper portion and a plug extension portion having a horizontal width greater than a lower portion of the word line contact plug; A semiconductor memory device, wherein at the levels of the upper and lower surfaces of the upper word line layer, side surfaces of the word line contact plug are both covered by the upper word line layer.

12. The method according to claim 11, further comprising: a bit line contact plug and a gate line contact plug electrically connected to the bit line and the gate line, respectively; 12. The semiconductor memory device of claim 11, wherein each of the bit line structures and the gate line structures further comprises an insulating capping line covering the bit line and the gate line, and each of the bit line contact plugs and the gate line contact plugs penetrate the insulating capping line and are electrically connected to the bit line and the gate line.

13. The semiconductor memory device of claim 12, further comprising a logic active region contact plug penetrating the filled insulating layer and electrically connected to the logic active region.

14. 14. The semiconductor memory device of claim 13, wherein a ratio of a horizontal width of an upper surface of the insulating capping line at a second vertical level to a horizontal width of an upper surface of the bit line at a first vertical level of the word line contact plug is greater than a ratio of a horizontal width of the logic active region contact plug, the bit line contact plug, and the gate line contact plug at the second vertical level to their horizontal widths at the first vertical level.

15. a plurality of buried contacts connected to the plurality of active regions; and a plurality of landing pads extending onto a plurality of bit line structures on the plurality of buried contacts, 12. The semiconductor memory device of claim 11, wherein the word line contact plugs and the landing pads are made of the same material.

16. a substrate having a memory cell region having a plurality of active areas defined therein and a peripheral circuit region having at least one logic active area defined therein; a plurality of word lines each having a stacked structure of a lower word line layer and an upper word line layer, the word lines filling a plurality of word line trenches extending parallel to each other in a first horizontal direction across the plurality of active regions, and a plurality of buried insulating layers on the plurality of word lines; a plurality of bit line structures disposed on the plurality of active regions and extending parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, each bit line having a bit line and an insulating capping line covering the bit line; a fill insulating layer filling spaces between the plurality of bit line structures; a word line contact plug having an upper portion, a plug extension portion having a horizontal width larger than that of a lower portion, penetrating the filled insulating layer, the buried insulating film and the upper word line layer, connected to the lower word line layer, and having side surfaces at the levels of the upper surface and the lower surface of the upper word line layer all covered by the upper word line layer; a plurality of buried contacts filling lower portions of spaces between the bit line structures and coupled to the active regions; a plurality of landing pads, each of which is made of the same material as the word line contact plugs and which fill upper portions of spaces between the bit line structures and extend onto the bit line structures;

17. a gate line structure disposed on the at least one logic active region, the gate line being made of the same material as the bit line, and the insulating capping line covering the gate line; 17. The semiconductor memory device of claim 16, further comprising: a gate line contact plug passing through the insulating capping line and electrically connected to the gate line.

18. a bit line contact plug passing through the insulating capping line and electrically connected to the bit line; a logic active region contact plug penetrating the filled insulating layer and electrically connected to the at least one logic active region, 20. The semiconductor memory device of claim 17, wherein the word line contact plugs, the gate line contact plugs, the bit line contact plugs, and the logic active region contact plugs are made of the same material.

19. 17. The semiconductor memory device of claim 16, wherein the upper word line layer is made of doped polysilicon, and the lower word line layer is made of a metal material, a conductive metal nitride, or a combination thereof.

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