Two-bit magnetoresistive random access memory cell

Abstract

A magnetoresistive random access memory (MRAM) cell is provided. The MRAM cell includes a first heavy metal layer and a first magnetic tunnel junction (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further includes a second MTJ. The second MTJ is connected in series with the first MTJ, and the second MTJ has a second area different from the first area. The second MTJ shares a reference layer with the first MTJ. The MRAM cell further includes a second heavy metal layer coupled to the second MTJ.

Description

[Technical field]

[0001] The present disclosure relates to the electrical, electronic, and computer fields. In particular, the present disclosure relates to a two-bit magnetoresistive random access memory (MRAM) cell having three transistors and a method for fabricating the same. [Background technology]

[0002] MRAM is a type of non-volatile memory used to store data in computers and other electronic devices. Unlike traditional read-access memories (e.g., dynamic read-access memories (DRAMs)), which store data as electric charges or current flows (e.g., using capacitors), MRAM uses magnetic storage elements to store data in magnetic domains. The magnetic storage elements are made of two ferromagnetic plates, each capable of retaining magnetization, separated by an insulating layer. The magnetization of the plates can be changed to match that of an external field to store data. Summary of the Invention

[0003] An embodiment of the present disclosure includes a magnetoresistive random access memory (MRAM) cell. The MRAM cell includes a first heavy metal layer and a first magnetic tunnel junction (MTJ) coupled to the first heavy metal layer. The first MTJ has a first area. The MRAM cell further includes a second MTJ. The second MTJ is connected in series with the first MTJ. The second MTJ has a second area different from the first area. The second MTJ shares a reference layer with the first MTJ. The MRAM cell further includes a second heavy metal layer coupled to the second MTJ.

[0004] Further embodiments of the present disclosure include a method of forming a 2-bit MRAM cell. The method includes forming a second heavy metal layer. The method further includes forming an MTJ stack. The MTJ stack includes a first MTJ having a first area and a second MTJ having a second area different from the first area. The second MTJ is formed on the second heavy metal layer. The first and second MTJs share a reference layer. The method further includes forming a first heavy metal layer on the first MTJ.

[0005] Further embodiments of the present disclosure include methods, systems, and computer program products for programming a 2-bit MRAM cell. The method includes receiving a write command to program a first bit of the 2-bit MRAM cell. The MRAM cell includes a first MTJ and a second MTJ in series. An area of ​​the first MTJ is different from an area of ​​the second MTJ. The first MTJ is coupled to a first heavy metal layer. The first heavy metal layer is connected to a bit line using a first transistor. The first heavy metal layer is connected to a source line using a second transistor. The second MTJ is connected to a second heavy metal layer. The second heavy metal layer is connected to the bit line using a third transistor. The second heavy metal layer is directly connected to the source line. The method further includes determining that the first bit is stored in a particular MTJ. The particular MTJ is either the first MTJ or the second MTJ. The method further includes selectively activating one or more of the first, second and third transistors to pass a current through a heavy metal layer associated with a particular MTJ.

[0006] Further embodiments of the present disclosure include methods, systems, and computer program products for reading a two-bit MRAM cell. The method includes receiving a read command to read a two-bit MRAM cell including a first MTJ and a second MTJ in series. The area of ​​the first MTJ is different from the area of ​​the second MTJ. The method further includes driving a current through the MRAM cell. The method further includes determining a resistance of the MRAM cell. The method further includes determining a two-bit value of the MRAM cell based on the determined resistance.

[0007] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. [Brief description of the drawings]

[0008] The drawings contained in this disclosure are incorporated in and form a part of this specification. These drawings illustrate embodiments of the disclosure and, together with the description, explain the principles of the disclosure. The drawings are merely illustrative of typical embodiments and are not intended to limit the disclosure.

[0009] [Figure 1] 1 is a block diagram showing an example configuration of a 2-bit magnetoresistive random access memory (MRAM) cell according to an embodiment of the present disclosure. [Diagram 2] 2 illustrates an example truth table showing how the states of the two magnetic tunnel junctions (MTJs) of the MRAM cell of FIG. 1 correspond to bit value states of the MRAM cell, according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 illustrates a portion of an MRAM array consisting of 2-bit MRAM cells according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a block diagram of a second example configuration of a 2-bit MRAM cell according to an embodiment of the present disclosure. [Figure 5A] 1A-1C are cross-sectional views of a 2-bit MRAM cell at intermediate stages in the manufacturing process according to an embodiment of the present disclosure. [Figure 5B]FIG. 5B is a cross-sectional view of the 2-bit MRAM cell of FIG. 5A after additional fabrication steps according to an embodiment of the present disclosure. [Figure 5C] FIG. 5C is a cross-sectional view of the 2-bit MRAM cell of FIG. 5B after additional fabrication steps according to an embodiment of the present disclosure. [Figure 5D] FIG. 5D is a cross-sectional view of the 2-bit MRAM cell of FIG. 5C after additional fabrication steps according to an embodiment of the present disclosure. [Figure 5E] FIG. 5E is a cross-sectional view of the 2-bit MRAM cell of FIG. 5D after additional fabrication steps according to an embodiment of the present disclosure. [Figure 5F] FIG. 5F is a cross-sectional view of the 2-bit MRAM cell of FIG. 5E after additional fabrication steps according to an embodiment of the present disclosure. [Figure 5G] FIG. 5C is a cross-sectional view of the 2-bit MRAM cell of FIG. 5F after additional fabrication steps according to an embodiment of the present disclosure. [Figure 6] 1 is a flowchart of an exemplary method for programming a first bit of a two-bit MRAM cell according to an embodiment of the present disclosure. [Figure 7] 1 is a flowchart of an exemplary method for programming a second bit of a two-bit MRAM cell according to an embodiment of the present disclosure. [Figure 8] 1 is a flow chart of an exemplary method for reading data stored in a 2-bit MRAM cell according to an embodiment of the present disclosure. [Figure 9] FIG. 1 is a schematic block diagram of an example computer system that can be used to implement one or more of the methods, tools, modules, and associated functionality described herein, according to embodiments of the present disclosure.

[0010] While the embodiments described herein are susceptible to various modifications and alternative forms, specific details of the embodiments are shown by way of example in the drawings and will be described in detail. However, the specific embodiments described are not to be construed in a limiting sense. On the contrary, it is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Aspects of the present disclosure relate generally to the electrical, electronic, and computer fields, and more specifically to a three-transistor 2-bit magnetoresistive random access memory (MRAM) cell and a method for fabricating the same. The present disclosure is not necessarily limited to such applications, but various aspects of the present disclosure can be understood through the description of various examples in this context.

[0012] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Other embodiments may be devised without departing from the scope of the present disclosure. It should be noted that various connection and positional relationships (e.g., above, below, adjacent, etc.) between elements are defined in the following description and drawings. These connection and / or positional relationships may be direct or indirect unless otherwise stated, and the present disclosure is not intended to be limiting in this respect. Thus, the coupling of entities may refer to direct or indirect coupling, and the positional relationship between entities may be direct or indirect. As an example of an indirect positional relationship, when it is said herein to form a layer "A" over a layer "B," it includes a situation in which there are one or more intermediate layers (e.g., layer "C") between the layers "A" and "B," as long as the relevant properties and functions of the layers "A" and "B" are not substantially altered by the intermediate layers.

[0013] The following definitions and abbreviations shall be used for the interpretation of the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements, but can include other elements not expressly recited or inherent to such composition, mixture, process, method, article, or device.

[0014] In the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the structures and methods described as oriented in the drawings. The terms "overlying", "atop", "on top", "positioned on" or "positioned atop" mean that a first element, such as a first structure, is on top of a second element, such as a second structure, where there may be an intervening element, such as an interface structure, between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating or semiconducting layer at the interface between the two elements. It should be noted that the term "selective to," e.g., "a first element selective to a second element," means that the first element can be etched and the second element can act as an etch stop.

[0015] For the sake of brevity, conventional techniques for semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Also, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional steps are only briefly mentioned herein without showing details of the well-known processes or are omitted entirely.

[0016] Generally, the various processes used in forming the microchips that are packaged into ICs fall into four broad categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0017] Deposition is any process whereby material is grown, applied, or otherwise transferred onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), among others. Another deposition technique is plasma enhanced chemical vapor deposition (PECVD). PECVD is a process that uses energy in a plasma to create a reaction at the wafer surface that would require higher temperatures in conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0018] Removal / etching is any process that removes material from a wafer. Examples include etching processes (wet or dry etching), chemical-mechanical planarization (CMP), etc. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to dry plasma etching that utilizes a remote broad beam ion / plasma source to remove substrate material by physical inert gas means or chemically reactive gas means or both. Like other dry plasma etching techniques, IBE has advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal substrate damage. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses a chemically reactive plasma to remove material deposited on the wafer. In RIE, the plasma is generated under low pressure (vacuum) by an electromagnetic field. High energy ions from the RIE plasma bombard and react with the wafer surface to remove material.

[0019] Semiconductor doping is the modification of electrical properties, for example, by doping the source and drain of a transistor, typically by diffusion or ion implantation or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The anneal serves to activate the implanted dopants. Both conductor (e.g., polysilicon, aluminum, copper, etc.) and insulator (e.g., various forms of silicon dioxide, silicon nitride, etc.) films are used to connect and separate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be changed by the application of a voltage. By forming structures of these various components, millions of transistors can be fabricated and wired together to form the complex circuits of modern microelectronic devices.

[0020] Semiconductor lithography is the formation of a three-dimensional relief image or pattern on a semiconductor substrate for later transfer of the pattern to a substrate. In semiconductor lithography, the pattern is formed with a light-sensitive polymer called photoresist. The lithography and etch pattern transfer steps are repeated multiple times to create the complex structures that make up the transistors and the many interconnects that connect the millions of transistors in a circuit. Each pattern printed on the wafer is aligned with the one before it, and conductors, insulators and selectively doped regions are gradually built up to form the final device.

[0021] A summary of technology more specifically related to aspects of the present disclosure is now provided. In general, a 2-bit MRAM cell refers to any material or combination of materials that can store two values ​​(e.g., two bits of information) using magnetic storage elements. The value of an MRAM cell can be binary ("01" or "00") or analog (e.g., 0.65). And the value of an MRAM cell is stored in the memory cell according to the electrical resistance of the cell, similar to how values ​​are stored in a resistive random access memory (ReRAM or RRAM) cell and / or a memristor. In other words, the relative orientation of the magnetization of the plates in an MRAM cell can affect the electrical resistance of the MRAM cell. This electrical resistance can be measured by passing a current through the MRAM cell, and the measured electrical resistance can be converted into a value.

[0022] Some of the drawbacks of conventional two-terminal MRAM devices are oxide reliability and high write power. Three-terminal spin hall effect (SHE) or spin orbit torque (SOT) MRAM cells overcome these limitations by providing separate paths for read and write operations. However, conventional SOT MRAM cells require two transistors coupled to a magnetic tunnel junction (MTJ) to store one bit of information. This limits the bit density of MRAM devices.

[0023] Attempts to increase the low bit density of MRAM devices have focused on forming multi-bit MRAM cells by either (1) sharing heavy metals in different MTJ pillars and (2) using stacked MTJs, where one MTJ utilizes SHE and the other utilizes spin-transfer torque (STT). However, both of these solutions have significant drawbacks. When different MTJs share a heavy metal structure, each MTJ cannot be programmed independently. For stacked MTJs, where one MTJ operates with SHE and the other with STT, all the constraints of STT still exist, such as tunnel barrier reliability and high write energy.

[0024] The embodiments of the present disclosure may overcome these and other shortcomings in existing solutions by using a 2-bit SOT MRAM cell that uses three transistors and provides separate write paths for each bit. The 2-bit SOT MRAM cell disclosed herein uses two MTJs in a series configuration with a shared reference layer. Two heavy metals (Pt, Ta, W, etc.) are in contact with two free layers (which can be in-plane or perpendicular-to-plane ferromagnetic). The MTJ stack has two free layers and a shared reference layer. The areas of the two free layers are different. In this structure, the SOT effect can be used to program the two free layers independently by passing a current through the heavy metal. The structure of the present disclosure can achieve speed improvement (for iso-energy) and energy improvement (for iso-speed) compared to STT-based MRAM cells.

[0025] In some embodiments, a 2-bit SOT MRAM cell includes two ferromagnetic free layers (FL1 and FL2) of different areas in contact with two heavy metals (Pt, Ta, W, etc.). In some embodiments, the upper free layer is smaller in area than the lower free layer. The ferromagnetic material can have in-plane or perpendicular-to-plane magnetic anisotropy.

[0026] A common ferromagnetic reference layer is shared between the two free layers. The reference layer (RL) is separated from each free layer by a tunnel barrier (e.g., MgO). In this way, the MTJ stack is formed by FL1 / MgO / RL / MgO / FL2. Due to the presence of two heavy metal layers at both ends, in some embodiments, the entire stack is composed of HM1 / FL1 / MgO / RL / MgO / FL2 / HM2.

[0027] The two free layers can be programmed independently by passing a "write" current through each of the two heavy metals. That is, by selectively activating one or two of the transistors, a current can be passed through one of the heavy metal layers, thereby independently setting the magnetic orientation of the layers based on the current. This allows each bit to be written individually into the MRAM cell.

[0028] The state of an MRM cell is determined by passing a "read" current through the MTJ stack and measuring the associated resistance state of the MTJ stack. Each MTJ in the stack has a different area / size, and therefore a different impact on the total resistance of the MTJ stack. This allows the MTJ stack to effectively have four resistance states instead of just two. As a simplified example, a first MTJ may be programmed to have a resistance of 10 or 20 kilohms, and a second MTJ may be programmed to have a resistance of 1 or 5 kilohms. Because the MTJs are in series, the entire stack will have a resistance of either 11, 15, 21, or 25 kilohms, depending on the magnetic orientation of the two MTJ stacks. Each of these resistance values ​​can be translated into a state of a 2-bit MRAM cell. For example, an effective resistance of 11 kilohms can correspond to a 2-bit value of 00. Similarly, 15, 21, and 25 kilohms can correspond to 01, 10, and 11, respectively.

[0029] It should be noted that while this simplified example illustrates the process, in practice, the MTJ may not be able to be programmed to an exact resistance value. Thus, each resistance state may have a corresponding range of resistance. Following the example above and assuming that the MTJ stack can be programmed to within 1.5 kilohms of the intended value, a two-bit value of 00 may be associated with a resistance in the range of [9.5, 12.5] kilohms. Similarly, two-bit values ​​of 01, 10, and 11 may correspond to resistances in the ranges of [13.5, 16.5] kilohms, [19.5, 22.5] kilohms, and [23.5, 26.5] kilohms, respectively.

[0030] By separating the write paths, the MTJs can be written independently, rather than sequentially as in conventional stacked MTJs. This can result in a significant reduction in time when writing to an MRAM cell. Because reading from an MRAM cell involves reading both bits at once, the improvement in read speed compared to conventional MRAM cells is not as great as the improvement in write speed, but the read speed can still be about two or three times faster than conventional MRAM in some embodiments. Additionally, separating the write paths and using different sized MTJs allows for better separation of resistance states based on how the tunnel barriers are formed.

[0031] Further embodiments of the present disclosure include a method for forming a 2-bit SOT MRAM cell. HM1, FL1, and TB1 are etched using a hard mask by a time controlled IBE or RIE process. HM1, FL1, and TB1 are then encapsulated with a dielectric material along with the top electrode material. RL, TB2, and FL2 are etched by a time controlled IBE or RIE process. The etch stops on the bottom heavy metal. A dielectric material (low-k) is deposited and polished by CMP to expose the top surface of HM1. A heavy metal (HM1) is deposited on the patterned HM1 to contact the FL1 surface.

[0032] As used herein, "heavy metal" as in "heavy metal layer" refers to any metal that has spin-orbit coupling properties of suitable strength to switch the magnetic orientation of the free layer (e.g., from parallel to anti-parallel) by inducing a torque on the magnetization of the free layer. These metals are sometimes called spin Hall metals or spin orbit torque metals.

[0033] It should be noted that the above advantages are merely examples and should not be construed as limiting. The embodiments of the present disclosure may include all, some, or none of the above advantages within the spirit and scope of the present disclosure.

[0034] Referring now to the drawings, FIG. 1 is a block diagram illustrating an example of a configuration of a 2-bit magnetoresistive random access memory (MRAM) cell 100 according to an embodiment of the present disclosure. The MRAM cell 100 includes two MTJs 102, 104 in an MTJ stack. The first MTJ 102 includes a first free layer (FL1) 116, a first tunnel barrier (TB1) 118, and a reference layer (RL) 120. The second MTJ 104 includes a second free layer (FL2) 124, a second tunnel barrier (TB2) 122, and a RL 120. As shown in FIG. 1, the first and second MTJs 102, 104 share the RL 120.

[0035] FL1 (116) and FL2 (124) are separated from RL120 by TB1 (118) and TB2 (122), respectively. Each tunnel barrier acts as an insulator between the free layer and the reference layer. TB1 (118) and TB2 (122) may be formed of any suitable material. For example, in some embodiments, TB1 (118) and TB2 (122) are layers of epitaxial (crystalline) MgO. In other embodiments, other suitable materials (e.g., amorphous aluminum oxide) may be used as one or both of the tunnel barriers.

[0036] 1, the first MTJ 102 is much smaller in area than the second MTJ 104. Because the resistance of an MTJ is proportional to its area, by utilizing an MTJ stack in which one MTJ is smaller than the other, there are four unique resistance states in the MTJ stack.

[0037] The first MTJ 102 is coupled to the first heavy metal layer (HM1) 112 via FL1 (116). Similarly, the second MTJ 104 is coupled to the second heavy metal layer (HM2) 114 via FL2 (124). HM1 (112) and HM2 (114) may be one or more layers of any metal or alloy that exhibits spin-orbit torque interaction. For example, HM1 (112) and HM2 (114) may be one or more of platinum, tungsten, tantalum, or manganese, or combinations thereof. In some embodiments, HM1 (112) and HM2 (114) are the same material, while in other embodiments, HM1 (112) and HM2 (114) are different metals.

[0038] HM1 (112) is connected to the bit line and the first word line (word line 1) through a first transistor T1. HM1 (112) is also connected to the source line and the third word line (word line 3) through a third transistor T3. Similarly, HM2 (114) is connected to the bit line and the second word line (word line 2) through a second transistor T2. HM2 (114) is connected directly (i.e., without an intermediate transistor) to the source line.

[0039] FL1 (116) and FL2 (124) can be independently programmed to store different values. Each of FL1 (116) and FL2 (124) must be programmed at a different time to prevent current from leaking between the two layers (i.e., current from passing through the MTJ stack).

[0040] FL1 is programmed (e.g., written) simply by passing a current through HM1 (112). This is done by turning on the first and third transistors T1, T3 while keeping the second transistor T2 off. Activating the transistors in this manner allows current to pass from the bit line to the source line through HM1 (112) without passing through the stack. The current through HM1 (112) sets the magnetic orientation of FL1 (116) and can therefore be used to change the resistance of FL1 (116).

[0041] Similarly, FL2 is programmed (e.g., written) simply by passing a current through HM2 (114). This is done by turning on the second transistor T2 while the first transistor T1 and the third transistor T3 are in an off state. Activating the transistors in this manner allows current to pass from the bit line to the source line through HM2 (114) without passing through the stack. The current through HM2 (114) sets the magnetic orientation of FL2 (124) and can therefore be used to change the resistance of FL2 (124).

[0042] The state (i.e., bit value) of the MRAM cell 100 can be read by passing a current through the MTJ stack (i.e., through both the first MTJ 102 and the second MTJ 104). This is done by activating the first transistor T1 while the second transistor T2 and the third transistor T3 are in an off state. As shown in FIG. 1, activating the transistor in this manner induces a read current (Iread) 130. The read current 130 flows from the bit line, through the first transistor T1, to HM1 (112), through the MTJ stack, to HM2 (114), and finally to the source line. The resistance of the MRAM cell 100 can be determined using the read current 130. The determined resistance can then be converted to a two-bit value (e.g., using a truth table such as that shown in FIG. 2).

[0043] 2 illustrates an example truth table 200 showing the correspondence between the states of the two MTJs of the MRAM cell of FIG. 1 and the bit value states of the MRAM cell according to an embodiment of the present disclosure. As shown in FIG. 2, each MTJ can be programmed to a parallel state (P) or an anti-parallel state (AP). Each state will have a corresponding resistance value depending on the area of ​​the MTJ. For example, the first MTJ 102 has a first resistance value when in the parallel state and a second resistance value when in the anti-parallel state. Similarly, the second MTJ 104 has a third resistance value when in the parallel state and a fourth resistance value when in the anti-parallel state.

[0044] By controlling the relative size of each MTJ, the resistance of each MTJ in both states can be made sufficiently different that the effective resistance of the stack can determine the state of each MTJ independently. This can then be translated into a state (i.e., a 2-bit value) of the MRAM cell. In the example shown in FIG. 2, the parallel state corresponds to a value 0 and the antiparallel state corresponds to a bit value 1. Thus, when both MTJs are in the parallel state, it corresponds to a 2-bit value 00, and when both MTJs are in the antiparallel state, it corresponds to a 2-bit value 11. When the first MTJ 102 is in the parallel state and the second MTJ 104 is in the antiparallel state, the 2-bit value of the MRAM cell is 01. Similarly, when the first MTJ 102 is in the antiparallel state and the second MTJ 104 is in the parallel state, the 2-bit value of the MRAM cell is 10.

[0045] Next, FIG. 3 illustrates a portion of an MRAM array 300 consisting of a plurality of 2-bit MRAM cells according to an embodiment of the present disclosure. The portion of the MRAM array 300 illustrated in FIG. 3 includes four MRAM cells. The four MRAM cells are connected to six word lines 310-320, two bit lines (Bit Line 1, Bit Line 2), and a source line. Each MRAM cell includes two heavy metal layers, an MTJ stack, and three transistors.

[0046] For example, the first MRAM cell includes a first heavy metal layer 302A, a second heavy metal layer 304A, and a first MTJ stack 306A. The first heavy metal layer 302A is connected to a first bit line and a first word line 310 through a first transistor T1. The first heavy metal layer 302A is also connected to a source line and a third word line 314 through a third transistor. The first heavy metal layer 302A is also connected to a second heavy metal layer 304A through a first MTJ stack 306A. The second heavy metal layer 304A is also connected to a first bit line and a second word line 312 through a second transistor T2.

[0047] Similarly, the second MRAM cell includes two heavy metal layers 302B, 304B, an MTJ stack 306B, and three transistors. Like the first MRAM cell, the second MRAM cell is connected to the first, second, and third word lines 310-314 and a source line. However, unlike the first MRAM cell, the second MRAM cell is connected to a second bit line (bit line 2). This allows the second MRAM cell to be controlled separately from the first MRAM cell.

[0048] The third MRAM cell includes two heavy metal layers 302C, 304C, an MTJ stack 306C, and three transistors. Similar to the first MRAM cell, the third MRAM cell is connected to a first bit line (Bitline 1) and a source line. However, unlike the first MRAM cell, the third MRAM cell is connected to a fourth word line 316, a fifth word line 318, and a sixth word line 320. This allows the third MRAM cell to be controlled separately from the first and second MRAM cells.

[0049] The fourth MRAM cell includes two heavy metal layers 302D, 304D, an MTJ stack 306D, and three transistors. Similar to the second MRAM cell, the third MRAM cell is connected to a second bit line (bit line 2) and a source line. However, unlike the second MRAM cell, the third MRAM cell is connected to a fourth word line 316, a fifth word line 318, and a sixth word line 320. This allows the fourth MRAM cell to be controlled separately from the first, second, and third MRAM cells.

[0050] Although only four MRAM cells are shown in Figure 3, any number of MRAM cells may be included in an MRAM array. In other words, the illustrated pattern of MRAM cells may be extended to any number of word lines and / or bit lines to accommodate many more MRAM cells in a single array. The total number of MRAM cells (and their arrangement) may be limited by other aspects of the processor, such as the number of individually controllable elements it supports.

[0051] Next, FIG. 4 is a block diagram illustrating a second example configuration of a 2-bit MRAM cell 400 according to an embodiment of the present disclosure. The MRAM cell 400 illustrated in FIG. 4 may be substantially similar to the MRAM cell 100 illustrated in FIG. 1, except for the shape of the MTJ stack. Thus, the first heavy metal layer 412 may be substantially similar to or the same as the first heavy metal layer 112 illustrated in FIG. 1. Similarly, the second heavy metal layer 414 may be substantially similar to or the same as the second heavy metal layer 114 illustrated in FIG. 1.

[0052] 1, the first MTJ 402 in FIG. 4 may include a first free layer 416, a first tunnel barrier 418, and a reference layer 420. The first free layer 416, the first tunnel barrier 418, and the reference layer 420 may be substantially similar or the same as the first free layer 116, the first tunnel barrier 118, and the reference layer 120 described with reference to FIG. 1, except for the different shapes. Similarly, the second MTJ 404 may include The second layer of freedom 424, a second tunnel barrier 422, and a reference layer 420. The second layer of freedom 424 and second tunnel barrier 422 may be substantially similar or the same as second free layer 124 and second tunnel barrier 122 described with reference to FIG. 1, except for their different shapes.

[0053] Because the first MTJ 402 and the second MTJ 404 have different areas, the MRAM cell 400 will have four effective resistance states for the same reason that the MRAM cell 100 has four effective resistance states. Furthermore, the operation of the MRAM cell 400 is the same as that of the MRAM cell 100. For example, reading the two-bit value of the MRAM cell 400 can be done by activating the first transistor T1 while the second transistor T2 and the third transistor T3 are in the off state. Thus, the trapezoidal / pyramidal shape of the MTJ stack shown in FIG. 4 may be used as an alternative to the shape of the MTJ stack shown in FIG. 1. This may be adopted for reasons of ease of fabrication, total area of ​​the MTJ stack, or other considerations recognized by those skilled in the art.

[0054] It should be noted that the shapes / configurations shown in Figures 1 and 4 are only examples of shapes that can be used to create a 2-bit MRAM cell. As one of ordinary skill in the art will recognize, there are many other suitable shapes, and the present disclosure is not limited to these example embodiments.

[0055] In some embodiments, the heavy metal layer may be local to each cell (as shown in FIG. 4), although in some other embodiments, the heavy metal layer may be shared among multiple MRAM cells in the same row. These embodiments may add complexity and require additional write cycles.

[0056] 5A is a cross-sectional view of a two-bit MRAM cell 500 at an intermediate stage in the manufacturing process, according to an embodiment of the present disclosure. Figure 5A shows the MRAM cell 500 after the formation of the initial material stack and before the initial etching step. The MRAM cell 500 includes one or more dielectric layers 504, 506, 508 on a substrate 502, collectively referred to as dielectric layers 550.

[0057] A heavy metal layer 510 is provided on the dielectric layer 550, formed by any suitable fabrication process. The heavy metal layer 510 may be formed on the dielectric layer 550 by any suitable fabrication process for depositing a heavy metal (e.g., Pl) on a dielectric layer. A free layer 512 is formed on the heavy metal layer 510. The free layer 512 may be any suitable ferromagnetic material.

[0058] A tunnel barrier 514 is formed on the free layer 512 by any suitable fabrication process. The tunnel barrier 514 may be, for example, MgO. The tunnel barrier 514 may be formed by epitaxial growth or material deposition of MgO on the free layer 512.

[0059] A reference layer 516 is formed on the tunnel barrier 514 by any suitable fabrication process. A second tunnel barrier layer 518 may then be formed on the reference layer 516 by any suitable fabrication process. The second tunnel barrier layer 518 may be substantially similar or the same as the first tunnel barrier layer 514.

[0060] A free layer 520 is formed on the tunnel barrier 518 by any suitable fabrication process. The free layer 520 may be any suitable ferromagnetic material. In some embodiments, the free layer 520 is the same material as the free layer 512. However, in other embodiments, the two free layers 512, 520 are different materials.

[0061] A heavy metal layer 522 is formed on the free layer 520 by any suitable fabrication process. The heavy metal layer 522 may be any suitable heavy metal (e.g., any metal that exhibits spin-orbit torque properties). The heavy metal layer 522 may be substantially similar or the same as the heavy metal layer 510.

[0062] A top electrode 524 is formed on the heavy metal layer 522 by any suitable fabrication process. The top electrode 524 may be formed of any suitable electrode material, such as Cu. A dielectric hard mask 526 is formed on the top electrode 524. The dielectric hard mask 526 may be formed of any suitable material, as known to those skilled in the art. An optical planarization layer (OPL) 528 is formed on the dielectric hard mask 526.

[0063] A silicon anti-reflective coating (SiARC) 530 is formed on the OPL 528. Finally, a resist 532 is formed on the SiARC 530.

[0064] 5B, a hard mask etching process is performed to remove the dielectric hard mask 526 and a portion of the top electrode 524. The hard mask etching process etches down to the top of the heavy metal layer 522. The area of ​​the remaining portion of the dielectric hard mask 526 and the top electrode 524 is based on the area of ​​the first MTJ of the MRAM cell 500 at the end of the fabrication process.

[0065] 5C, a time-controlled etch of the heavy metal layer 522, the free layer 520, and the tunnel barrier 518 is performed. In some embodiments, the time-controlled etch utilizes an ion beam etching process. In other embodiments, the heavy metal layer 522, the free layer 520, and the tunnel barrier 518 are etched by RIE.

[0066] 5D, a dielectric encapsulation of the etched heavy metal layer 522, the free layer 520, and the tunnel barrier 518 is performed. The dielectric encapsulation includes forming a dielectric (e.g., low-k) material 534 along the sides of the etched heavy metal layer 522, the free layer 520, and the tunnel barrier 518.

[0067] 5E, the reference layer 516, the tunnel barrier 514, and the free layer 512 are then etched. The reference layer 516, the tunnel barrier 514, and the free layer 512 may be etched by time-controlled ion beam etching or RIE. The encapsulated top layer may act as a hard mask for the etch such that the sides of these etched layers are substantially flush with the dielectric encapsulation layer 534. The etch may be performed down to the top surface of the heavy metal layer 510.

[0068] 5F, a dielectric deposition and CMP of the remaining top electrode material is then performed to expose the top of the heavy metal layer 522. The dielectric deposition includes depositing a low-k material 536 over the exposed portions of the heavy metal layer 510. In some embodiments, this step can be preceded by a second dielectric encapsulation of the entire stack.

[0069] 5G, a heavy metal layer 538 is then deposited over the structure in contact with the patterned heavy metal layer 522, the dielectric encapsulation layer 534, and the deposited low-k layer 536. HM1 (522) and HM2 (510) in the resulting MRAM cell 500 may be located in two metal layers at the back end of the line (BEOL) and will run perpendicular to each other, although for purposes of illustration they are shown as parallel in this figure.

[0070] 6 is a flow chart of an example method 600 for programming a first bit of a 2-bit MRAM cell, according to an embodiment of the present disclosure. The method 600 may be performed by hardware, firmware, software, or any combination thereof running on a processor. For example, the method 600 may be performed by a memory controller (e.g., in a processor). With reference to FIGS. 1, 2, and 6, the method 600 begins at operation 602, when the memory controller receives a write command to program a first bit of the 2-bit MRAM cell 100.

[0071] In the example illustrated in FIG. 6, a first bit is stored in the first MTJ 102. The write command also indicates a value (e.g., 0 or 1) of the first bit. In response to receiving the write command, the memory controller determines an associated current required to program the value into the first MTJ 102. The associated current depends on whether the first MTJ 102 is set to a parallel state (e.g., associated with a 0 in the example illustrated in FIG. 2) or an anti-parallel state (e.g., associated with a 1 in the example illustrated in FIG. 2). Based on the current required to program the appropriate state into the first MTJ 102, a voltage is driven onto the bit line. The voltage may be a high voltage or a low voltage.

[0072] After charging the bit lines to the appropriate voltages, the first transistor T1 and the third transistor T3 are activated in operation 604. This is done by raising the voltages of the first word line and the third word line. The second transistor T2 is kept off. This causes a current to flow through the first heavy metal layer 112, thereby programming the first MTJ 102 to store the value contained in the write command. After programming the first MTJ 102 of the MRAM cell 100 based on the write command, the method 600 ends.

[0073] 7 is a flow chart of an example method 700 for programming a second bit of a 2-bit MRAM cell, according to an embodiment of the present disclosure. The method 700 may be performed by hardware, firmware, software, or any combination thereof running on a processor. For example, the method 700 may be performed by a memory controller (e.g., within a processor). With reference to FIGS. 1, 2, and 7, the method 700 begins at operation 702, where the memory controller receives a write command to program the second bit of the 2-bit MRAM cell 100.

[0074] In the example illustrated in FIG. 7, a second bit is stored in the second MTJ 104. The write command also indicates a value (e.g., 0 or 1) of the second bit. In response to receiving the write command, the memory controller determines an associated current required to program the value into the second MTJ 104. The associated current depends on whether the second MTJ 104 is set to a parallel state (e.g., associated with a 0 in the example illustrated in FIG. 2) or an anti-parallel state (e.g., associated with a 1 in the example illustrated in FIG. 2). Based on the current required to program the appropriate state into the second MTJ 104, a voltage is driven onto the bit line. The voltage may be a high voltage or a low voltage.

[0075] After charging the bit line to the appropriate voltage, the second transistor T2 is activated in operation 704. This is done by raising the voltage of the second word line. The first transistor T1 and the third transistor T3 are kept off. This allows current to flow through the second heavy metal layer 114, thereby programming the second MTJ 104 to store the value contained in the write command. After programming the second MTJ 104 of the MRAM cell 100 based on the write command, the method 700 ends.

[0076] 8 is a flow chart of an example method 800 for reading data stored in a 2-bit MRAM cell, according to an embodiment of the present disclosure. The method 800 may be performed by hardware, firmware, software, or any combination thereof running on a processor. For example, the method 800 may be performed by a memory controller (e.g., in a processor). With reference to FIGS. 1, 2, and 8, the method 800 begins at operation 802, where the memory controller receives a read command to read the 2-bit MRAM cell 100.

[0077] In operation 804, the first transistor T1 is activated. This may be done by raising the voltage of the first word line. Meanwhile, the second transistor T2 and the third transistor T3 are kept off during the read process. The activation of the first transistor T1 (the other two transistors are in the off state) causes a read current to flow through the transistor T1, the first heavy metal layer 112, the MTJs 102, 104, and the second heavy metal layer 114.

[0078] The resistance of the MTJ stack is determined in operation 806. The resistance may be determined by measuring the read current and applying Ohm's law to the measured current, using a known precharge voltage on the bit lines.

[0079] At operation 808, a bit value of the MRAM cell is determined based on the calculated resistance of the MTJ stack. Because the first MTJ and the second MTJ have different areas and each MTJ has two resistance states based on whether it is parallel or anti-parallel oriented, the MRAM cell as a whole effectively has four resistance states. Each of the four resistance states corresponds to a two-bit value (e.g., as shown in FIG. 2). Thus, the calculated resistance of the MRAM cell can be compared to the four resistance states to determine the two-bit value of the MRAM cell. After determining the two-bit value of the MRAM cell, the memory controller can return the two-bit value to the originator of the read request. Method 800 may then end.

[0080] 9 is now a schematic block diagram of an example computer system 901 that can be used to implement (e.g., with one or more processor circuits of a computer or computer processor) one or more of the methods, tools, modules, and any associated functionality described herein, according to embodiments of the present disclosure. In some embodiments, the major components of the computer system 901 can include one or more CPUs 902, a memory subsystem 904, a terminal interface 912, a storage interface 916, an I / O (input / output) device interface 914, and a network interface 918, all of which can be communicatively coupled directly or indirectly to facilitate communication between the components via a memory bus 903, an I / O bus 908, and an I / O bus interface unit 910.

[0081] Computer system 901 may include one or more general purpose programmable central processing units (CPUs) 902A, 902B, 902C, and 902D (collectively referred to herein as CPUs 902). In some embodiments, computer system 901 may include multiple processors, as is common in larger systems, although in other embodiments computer system 901 may instead be a single CPU based system. Each CPU 902 may execute instructions stored in memory subsystem 904. Each CPU 902 may also include one or more levels of on-board cache.

[0082] The system memory 904 may include computer system readable media such as volatile memory, such as random access memory (RAM) 922 and cache memory 924. The computer system 901 may further include other removable / non-removable volatile / non-volatile computer system storage media. By way of example only, the storage system 926 may be provided for reading and writing to a non-removable, non-volatile magnetic medium, such as a "hard drive." Although not shown, a magnetic disk drive may be provided for reading and writing to a removable, non-volatile magnetic disk (e.g., a floppy disk) and an optical disk drive may be provided for reading and writing to a removable, non-volatile optical disk (e.g., a CD-ROM, DVD-ROM or other optical media). In addition, the memory 904 may include a flash memory (e.g., a flash memory stick drive or a flash drive). The memory device may be connected to the memory bus 903 by one or more data media interfaces. The memory 904 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of various embodiments.

[0083] One or more programs / utilities 928, each having at least one set of program modules 930, can be stored in memory 904. The programs / utilities 928 can include a hypervisor (also called a virtual machine monitor), one or more operating systems, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or any combination thereof, can include an implementation of a network environment. The program modules 930 generally perform the functions or methods of the various embodiments.

[0084] Although the memory bus 903 is illustrated in FIG. 9 as a single bus structure providing a direct communication path between the CPU 902, the memory subsystem 904, and the I / O bus interface 910, the memory bus 903 may, in some embodiments, include multiple different buses or communication paths. These buses or communication paths may be arranged in any of a variety of configurations, such as point-to-point links in a hierarchical star or web configuration, multiple hierarchical buses, parallel and redundant paths, or any other suitable type of configuration. Additionally, while the I / O bus interface 910 and the I / O bus 908 are each illustrated as single units, the computer system 901 may, in some embodiments, include multiple I / O bus interface units 910, multiple I / O buses 908, or both. Additionally, although multiple I / O interface units are illustrated that separate the I / O bus 908 from the various communication paths leading to the various I / O devices, in other embodiments, some or all of the I / O devices may be directly connected to one or more system I / O buses.

[0085] In some embodiments, computer system 901 may be a multi-user mainframe computer system, a single-user system, or a server computer or similar device that has little or no direct user interface but receives requests from other computer systems (clients). Further, in some embodiments, computer system 901 may be implemented as a desktop computer, a portable computer, a laptop or notebook computer, a tablet computer, a pocket computer, a telephone, a smartphone, a network switch or router, or any other suitable type of electronic device.

[0086] It should be noted that FIG. 9 is intended to illustrate representative major components in an example computer system 901. In some embodiments, the individual components may be more complex or simpler than those depicted in FIG. 9. Also, there may be other components present than those depicted in FIG. 9 or in addition to those depicted in FIG. 9. The number, type, and configuration of such components may vary. Furthermore, the modules are enumerated and described as exemplary in accordance with one embodiment and are not intended to indicate that any particular module is required or to exclude other possible modules (or the functionality / purpose applied to any particular module).

[0087] The present invention may be a system, method or computer program product, or combination thereof, integrated at any possible level of technical detail. The computer program product may include a computer readable storage medium having stored thereon computer readable program instructions for causing a processor to carry out aspects of the present invention.

[0088] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or a suitable combination thereof. More specific examples of computer-readable storage media include portable computer diskettes, hard disks, RAM, ROM, EPROM (or flash memory), SRAM, CD-ROM, DVD, memory sticks, floppy disks, punch cards or mechanically encoded devices with instructions recorded on ridges in grooves, and the like, and suitable combinations thereof. As used herein, a computer-readable storage medium should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a wave guide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electric signal transmitted through a wire.

[0089] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing device / processing device. Alternatively, they can be downloaded to an external computer or external storage device via a network (e.g., the Internet, a LAN, a WAN, or a wireless network, or a combination thereof). The network can comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing device / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing device / processing device.

[0090] The computer readable program instructions for carrying out the operations of the present invention may be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object oriented programming languages ​​such as Smalltalk and C++, and procedural programming languages ​​such as the "C" programming language and similar programming languages. The computer readable program instructions may be executed entirely on the user's computer as a stand-alone software package, or partially on the user's computer, or partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a LAN or WAN, or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuitry, field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), can execute computer readable program instructions by utilizing state information of the computer readable program instructions to customize the electronic circuitry for carrying out aspects of the present invention.

[0091] Aspects of the present invention are described herein with reference to flowchart and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. Each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer readable program instructions.

[0092] These computer readable program instructions can be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, whereby the instructions executed via the processor of such computer or other programmable data processing apparatus create means for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions can further be stored on a computer readable storage medium capable of instructing a computer, programmable data processing apparatus or other device, or combination thereof, to function in a particular manner. The computer readable storage medium having instructions stored thereon thereby constitutes an article of manufacture including instructions for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0093] Also, computer-readable program instructions may be loaded into a computer, other programmable apparatus, or other device and a sequence of operational steps executed on the computer, other programmable apparatus, or other device to generate a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device perform the functions / operations identified in one or more blocks in the flowcharts and / or block diagrams.

[0094] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for performing a specific logical function. In some other implementations, the functions shown in the blocks may be performed in a different order than the order shown in the figures. For example, depending on the functions involved, two blocks shown in succession may actually be accomplished as one step, may be performed simultaneously or nearly simultaneously, may be performed in a partially or fully overlapping manner, or the blocks may be performed in reverse order in some cases. It should be noted that each block in the block diagrams and / or flowcharts, and combinations of multiple blocks in the block diagrams and / or flowcharts, may be executed by a dedicated hardware-based system that performs a specific function or operation or executes a combination of dedicated hardware and computer instructions.

[0095] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the various embodiments. In this specification, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. Furthermore, in this specification, the terms "includes" and / or "including" specify the presence of a stated feature, integer, step, operation, element, or component, or combination thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups or combinations thereof. In the above detailed description of exemplary embodiments of various embodiments, reference has been made to the accompanying drawings, in which like numerals represent like elements. The accompanying drawings, which form a part of this specification, illustrate specific example embodiments in which various embodiments may be practiced. These embodiments have been described in sufficient detail to enable one skilled in the art to practice the embodiments, but other embodiments may be used and logical, mechanical, electrical and other types of changes may be made without departing from the scope of the various embodiments. In the above description, numerous specific details have been set forth to provide a thorough understanding of the various embodiments. However, various embodiments may be practiced without these specific details, and in other instances, well-known circuits, structures and techniques have not been described in detail in order to avoid obscuring the embodiments.

[0096] As used herein, "a number of" with respect to an item means one or more of the item. For example, "a number of different types of networks" means one or more different types of networks.

[0097] Where different reference numbers consist of a common number followed by a different letter (e.g., 100a, 100b, 100c), or a common number followed by punctuation followed by a different number (e.g., 100-1, 100-2, or 100.1, 100.2), using only the reference number (e.g., 100) without the letters or subsequent numbers may refer to the entire group of elements, any subset within the group, or an illustrative example within the group.

[0098] Furthermore, when the phrase "at least one of" is used in conjunction with a list of items, it means that different combinations of one or more of the listed items can be used, and only one of each item in the list may be required. In other words, "at least one of" means that any combination and any number of the items in the list can be used, and not all items in the list are required. An item can be a particular object, thing, or category.

[0099] For example, "at least one of item A, item B, or item C" can include, but is not limited to, "item A," "item A and item B," or "item B." This example can further include "item A, item B, and item C," or "item B and item C." Of course, any combination of these items exists. To give some examples, "at least one" can be, for example, but is not limited to, "2 items A, 1 item B, and 10 items C," "4 items B, and 7 items C," or any other suitable combination.

[0100] In the above description, various embodiments have been referenced. However, the present disclosure is not limited to the specifically described embodiments. Any combination of the described features and elements, whether related to different embodiments or not, is contemplated in implementing and practicing the present disclosure. Numerous modifications, changes, and variations may be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. Furthermore, the embodiments of the present disclosure may achieve advantages over other possible solutions or prior art, but whether or not a particular advantage is achieved by a given embodiment does not limit the present disclosure. Thus, the described aspects, features, embodiments, and advantages are merely exemplary and should not be considered elements or limitations of the appended claims unless expressly recited in the claims. Moreover, it is intended that the following claims be construed to encompass all such modifications and variations that fall within the true spirit and scope of the present invention.

Claims

1. a first heavy metal layer; a first magnetic tunnel junction (MTJ) coupled to the first heavy metal layer and having a first area; a second MTJ connected in series with the first MTJ and having a second area different from the first area, the second MTJ sharing a reference layer with the first MTJ; a second heavy metal layer coupled to the second MTJ; Including, the first heavy metal layer is connected to a first word line and a bit line via a first transistor; the second heavy metal layer is connected to a second word line and the bit line via a second transistor; the first heavy metal layer is connected to a third word line and a source line via a third transistor; the second heavy metal layer is directly connected to the source line; A magnetoresistive random access memory (MRAM) cell.

2. The first MTJ comprises: a first free layer in direct contact with the first heavy metal layer; The reference layer; a first tunnel barrier disposed between the first free layer and the reference layer; The MRAM cell of claim 1 , comprising:

3. The second MTJ comprises: a second free layer in direct contact with the second heavy metal layer; The reference layer; a second tunnel barrier disposed between the second free layer and the reference layer; The MRAM cell of claim 2 , comprising:

4. The MRAM cell of claim 2 , wherein the first tunnel barrier is a layer of MgO.

5. The MRAM cell of claim 1 , wherein the first area is smaller than the second area.

6. The MRAM cell of claim 5, wherein the common reference layer has the same area as the second MTJ.

7. The MRAM cell of claim 1 , wherein the first heavy metal layer and the second heavy metal layer comprise one or more layers of a metal that exhibits spin-orbit torque properties.

8. 10. The MRAM cell of claim 1, wherein the first heavy metal layer and the second heavy metal layer comprise one or more layers of a metal selected from the group consisting of platinum, tungsten, tantalum, and manganese.

9. The MRAM cell of claim 1 , wherein the first MTJ is stacked above the second MTJ.

10. The MRAM cell of claim 1 , wherein the MRAM cell is part of a memory array that includes a plurality of 2-bit MRAM cells.

11. The MRAM cell of claim 1, wherein the first heavy metal layer and the second heavy metal layer both comprise one or more layers of a metal selected from the group consisting of platinum, tungsten, tantalum, and manganese, and the common reference layer comprises a ferromagnetic metal.

12. A method for programming a magnetoresistive random access memory (MRAM) cell comprising: a first heavy metal layer; a first magnetic tunnel junction (MTJ) coupled to the first heavy metal layer and having a first area; a second MTJ connected in series with the first MTJ and having a second area different from the first area, the second MTJ sharing a reference layer with the first MTJ; and a second heavy metal layer coupled to the second MTJ, the first heavy metal layer being connected to a first word line and a bit line via a first transistor, the second heavy metal layer being connected to a second word line and the bit line via a second transistor, the first heavy metal layer being connected to a third word line and a source line via a third transistor, and the second heavy metal layer being directly connected to the source line, the method comprising: receiving a write command to program a first bit of the MRAM cell; determining to store the first bit in a particular MTJ, the particular MTJ being either the first MTJ or the second MTJ; Selectively activating one or more of the first, second, and third transistors to pass current through a heavy metal layer associated with the particular MTJ; The method includes:

13. the particular MTJ is the first MTJ, and selectively activating one or more of the first, second, and third transistors includes: activating the first and third transistors to pass a current through the first heavy metal layer; the second transistor is not activated; The method of claim 12.

14. the particular MTJ is the second MTJ, and selectively activating one or more of the first, second, and third transistors includes: activating the second transistor to pass a current through the second heavy metal layer; the first and third transistors remain inactivated; The method of claim 12.

15. A system for programming a magnetoresistive random access memory (MRAM) cell, comprising: the MRAM cell and a processor; The MRAM cell comprises: a first heavy metal layer; a first magnetic tunnel junction (MTJ) coupled to the first heavy metal layer and having a first area; a second MTJ connected in series with the first MTJ and having a second area different from the first area, the second MTJ sharing a reference layer with the first MTJ; a second heavy metal layer coupled to the second MTJ; Including, the first heavy metal layer is connected to a first word line and a bit line via a first transistor; the second heavy metal layer is connected to a second word line and the bit line via a second transistor; the first heavy metal layer is connected to a third word line and a source line via a third transistor; the second heavy metal layer is directly connected to the source line; The processor, receiving a write command to program a first bit of the MRAM cell; determining to store the first bit in a particular MTJ, the particular MTJ being either the first MTJ or the second MTJ; selectively activating one or more of the first, second, and third transistors to pass a current through a heavy metal layer associated with the particular MTJ. system.

16. the particular MTJ is the first MTJ, and selectively activating one or more of the first, second, and third transistors includes: activating the first and third transistors to pass a current through the first heavy metal layer; the second transistor is not activated; The system of claim 15.

17. the particular MTJ is the second MTJ, and selectively activating one or more of the first, second, and third transistors includes: activating the second transistor to pass a current through the second heavy metal layer; the first and third transistors remain inactivated; The system of claim 15.

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