Wrap-around contacts with localized metal silicide

Abstract

The conformally deposited metal liner used to form the individual wrap-around contact structures is localized between pairs of gate structures and beneath the tops of the gate structures. Block mask patterning is used to remove portions of the metal liner between the active regions while protecting the transistors on the substrate active areas. A chamfering technique is used to selectively remove additional portions of the metal liner within the active areas. Metal silicide liners formed on the source / drain regions using the conformally deposited metal liner are electrically connected to the source / drain contact metal following deposition and patterning of a dielectric layer and subsequent metallization.

Description

[Technical field]

[0001] The present invention relates generally to electrical, electronic and computer technologies, and more particularly to field effect transistors (FETs) including wrap-around contacts and their fabrication. [Background technology]

[0002] As the dimensions of various integrated circuit components have decreased, transistors such as field effect transistors (FETs) have undergone dramatic improvements in both performance and power consumption. These improvements can be primarily attributed to the decrease in dimensions of the components used in the integrated circuits, which in turn can generally be attributed to the decrease in capacitance, resistance, and increase in the throughput current of the transistors. Metal-oxide-semiconductor field effect transistors (MOSFETs) are well suited for use in high density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of the device's source / drain regions, channel region, and gate electrode also decrease.

[0003] FinFETs, nanosheet and other FETs are under development for potential use in narrow pitch applications. Nanosheet FETs contain multiple channel layers, each separated by a gate stack that includes a layer of conductive gate material and a gate dielectric layer. The gate stack wraps around all sides of the channel layer, thereby forming a gate-all-around (GAA) structure. Epitaxial regions at the ends of the nanosheet channel layer form the source / drain regions of the nanosheet FET. Spacers are used to electrically insulate the gate from the source / drain regions of the nanosheet transistor. Fin-type field effect transistors (FinFETs) have a three-dimensional non-planar configuration that includes a fin-like structure that extends above a substrate. The substrate can include a semiconductor-on-insulator (SOI) substrate or a bulk semiconductor substrate. Silicon fins are formed in some FinFETs on the substrate via known techniques such as sidewall image transfer (SIT). FinFET structures that include SOI substrates can be formed in part by selective etching of a crystalline silicon layer down to an oxide or other insulating layer following photolithography. The height of the active fin is set by the SOI thickness when using an SOI substrate. In bulk FinFETs, the height of the active fin is typically set by the oxide thickness and the etched fin height.

[0004] Due to aggressive dimension scaling in advanced CMOS devices, the contribution of middle-of-line (MOL) contact resistance to the total parasitic resistance is increasing. The silicide / source-drain interface resistance can be a major contributor to the total extrinsic parasitic resistance. The overall contact resistance can be reduced by increasing the silicide contact length by wrapping around the entire source-drain surface. Covering the source-drain epitaxy with a trench silicide (TS) liner as a wrap-around contact (WAC) to reduce spreading resistance can be important for designing advanced semiconductor devices. Conformal metallization processes using chemical vapor deposition (CVD) or atomic layer deposition (ALD) are used to form the metal contacts. Summary of the Invention

[0005] According to one aspect of the invention, a method of forming a semiconductor structure including a wrap-around contact is provided. The method includes conformally depositing a metal liner on a monolithic structure, the monolithic structure including first and second active areas, and field effect transistors on the first and second active areas including gate structures and epitaxial source / drain regions. A metal silicide liner is formed from the metal liner on the epitaxial source / drain regions and wraps around these regions. The method further includes protecting the first and second active areas with a patterned block mask, selectively removing the metal liner from areas exposed by the patterned block mask between the first and second active areas, and removing the patterned block mask. The protective mask is formed on the monolithic structure such that the epitaxial source / drain regions are completely below a top surface of the protective mask and such that portions of the metal liner above the first and second active areas are exposed. The exposed portions of the metal liner over the first and second active areas are selectively removed, and then the protective mask is removed.

[0006] A further method of forming a semiconductor structure including a wrap-around contact includes obtaining a monolithic structure including first and second active regions, a field effect transistor on the first and second active regions including a gate structure, a gate cap above the gate structure, a gate sidewall spacer on the sidewall of the gate structure, and an epitaxial source / drain region between the pair of gate structures, and a continuous liner on the epitaxial source / drain region including a first liner portion covering the epitaxial source / drain region and a metal liner extending over the gate cap and gate sidewall spacer between the first and second active regions. The first and second active regions are protected with a patterned block mask. The metal liner is selectively removed from areas exposed by the patterned block mask between the first and second active regions, and the patterned block mask is then removed. A protective mask is formed over the monolithic structure such that the tops of the gate cap and gate sidewall spacers extend above a top surface of the protective mask and the epitaxial source / drain regions are below a top surface of the protective mask. The metal liner is selectively removed from the tops of the gate sidewall spacers and gate cap and the protective mask is removed.

[0007] In a further aspect of the invention, a semiconductor structure is provided that includes a semiconductor substrate including a first active region and a second active region, a shallow trench isolation region between the first active region and the second active region, and a plurality of gate structures on the first active region. A first field effect transistor on the first active region includes one of the gate structures on the first active region, a channel region, and a pair of epitaxial source / drain regions on either side of the channel region, each epitaxial source / drain region being located between the pair of gate structures on the first active region. A wrap-around metal silicide liner is adjacent to each epitaxial source / drain region. A dielectric layer extends over the semiconductor substrate and the first field effect transistor. The semiconductor structure further includes a metal liner portion contiguous with each metal silicide liner, each metal liner portion including a vertical extending portion located between the pair of gate structures on the first active region and extending above the source / drain regions, and a horizontal extending portion located below the source / drain regions of the first field effect transistor and disposed between the shallow trench isolation region and the dielectric layer, the horizontal extending portion of each metal liner portion extending laterally beyond one of the source / drain regions of the first field effect transistor.

[0008] A semiconductor structure according to a further aspect includes a semiconductor substrate including a first active region and a second active region, a plurality of parallel gate structures extending across the semiconductor substrate, and a first field effect transistor on the first active region, the first field effect transistor including one of the gate structures, a channel region, and a first pair of epitaxial source / drain regions on either side of the channel region, each epitaxial source / drain region being located between the first pair of gate structures. The semiconductor structure further includes a second field effect transistor on a second active region, the second field effect transistor including one of the gate structures, a channel region, and a second pair of epitaxial source / drain regions on either side of the channel region, each epitaxial source / drain region being located between the second pair of gate structures. A dielectric liner covers the first field effect transistor and the second field effect transistor. A metal silicide layer is wrapped around each of the source / drain regions of the first and second field effect transistors. A conformal metal liner extends from and is contiguous with each metal silicide liner. Each conformal metal layer is confined between a pair of gate structures and includes a vertically extending portion that extends vertically above one of the source / drain regions, the pair of gate structures extending vertically above the vertically extending portion of each conformal metal liner. A source / drain contact metal extends vertically through the dielectric layer and contacts the metal silicide liner.

[0009] The techniques and structures disclosed herein can provide substantial beneficial technical effects. By way of example only and not limitation, one or more embodiments can provide one or more of the following advantages: Robust and easily integrated individual wrap-around contacts. · Reducing the number of Extreme Ultraviolet Lithography (EUVL) levels. · Avoiding possible problems associated with inverse tone patterning.

[0010] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0011] The following drawings are presented by way of example only and not by way of limitation, and like reference numerals (where used) indicate corresponding elements throughout the several views. [Brief description of the drawings]

[0012] [Figure 1] 1 is a schematic plan view illustrating selected elements of a monolithic semiconductor structure. [Figure 1A] 2 is a schematic cross-sectional view taken along line X in FIG. 1, showing further elements of the monolithic semiconductor structure; [Figure 1B] 2 is a schematic cross-sectional view taken along line Y in FIG. 1, showing further elements of the monolithic semiconductor structure. [Figure 2A] FIG. 1B is a schematic cross-sectional view of the structure shown in FIG. 1A after selective oxide etching. [Figure 2B] FIG. 1C is a schematic cross-sectional view of the structure shown in FIG. 1B after selective oxide etching. [Figure 3A] FIG. 2B is a schematic cross-sectional view of the structure as shown in FIG. 2A after removal of the contact and etch stop layer (CESL). [Figure 3B] FIG. 2C is a schematic cross-sectional view of the structure as shown in FIG. 2B after removal of the contact and etch stop layer (CESL). [Figure 4A] FIG. 3B is a schematic cross-sectional view of the structure as shown in FIG. 3A after forming a silicide liner around the source / drain regions. [Figure 4B] FIG. 3C is a schematic cross-sectional view of the structure as shown in FIG. 3B after deposition of a metal liner. [Figure 5A] FIG. 4B is a schematic cross-sectional view of the structure after depositing and patterning a block mask onto the structure shown in FIG. 4A. [Figure 5B] FIG. 4B is a schematic cross-sectional view of the structure after depositing and patterning a block mask onto the structure. [Figure 6A] FIG. 5B is a schematic cross-sectional view of a structure as shown in FIG. 5A after selective removal of the metal liner between active areas of the structure. [Figure 6B] FIG. 5C is a schematic cross-sectional view of the structure after selective removal of the metal liner between the active areas of the structure as shown in FIG. 5B. [Figure 7A] FIG. 6B is a schematic cross-sectional view of the structure as shown in FIG. 6A after removal of the patterned block mask. [Figure 7B] FIG. 6C is a schematic cross-sectional view of the structure as shown in Figure 6B after removal of the patterned block mask. [Figure 8A] Schematic cross-section of the structure as shown in Figure 7A after deposition of an organic planarization layer (OPL) and its partial etch-back. [Figure 8B] Schematic cross-section of the structure as shown in Figure 7B after deposition of an organic planarization layer (OPL) and its partial etch-back. [Figure 9A] FIG. 8B is a schematic cross-sectional view of the structure as shown in FIG. 8A after selective chamfering of the metal liner on the gate. [Figure 9B] FIG. 8C is a schematic cross-sectional view of the structure as shown in FIG. 8B after selective chamfering of the metal liner on the gate. [Figure 10A] FIG. 9B is a schematic cross-sectional view of the structure as shown in FIG. 9A after removal of the OPL. [Figure 10B] FIG. 9C is a schematic cross-sectional view of the structure as shown in FIG. 9B after removal of the OPL. [Figure 11A] FIG. 10B is a schematic cross-sectional view of the structure as shown in FIG. 10A after deposition and planarization of an interlevel dielectric (ILD) layer. [Figure 11B] FIG. 10C is a schematic cross-sectional view of the structure as shown in FIG. 10B after deposition and planarization of an ILD layer. [Figure 12A] FIG. 11B is a schematic cross-sectional view of the structure as shown in FIG. 11A after forming contact trenches in the ILD layer. [Figure 12B] FIG. 11C is a schematic cross-sectional view of the structure as shown in FIG. 11B after forming contact trenches in the ILD layer. [Figure 13A]FIG. 12B is a schematic cross-sectional view of the structure as shown in FIG. 12A after contact metallization. [Figure 13B] FIG. 12C is a schematic cross-sectional view of the structure as shown in FIG. 12B after contact metallization. [Figure 14A] FIG. 13B is a schematic cross-sectional view of the structure as shown in FIG. 13A after planarization. [Figure 14B] FIG. 13C is a schematic cross-sectional view of the structure as shown in FIG. 13B after planarization. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] It should be understood that elements in the figures are illustrated for simplicity and clarity, and that common but well-understood elements that may be useful or necessary in a commercially feasible embodiment may not be shown so as not to obscure the view of the illustrated embodiment.

[0014] The principles of the present invention are described herein in the context of exemplary embodiments. It should be understood, however, that the specific embodiments and / or methods illustratively shown and described herein should be considered as exemplary and not limiting. Moreover, it will be apparent to those skilled in the art in light of the teachings herein that numerous modifications can be made to the illustrated embodiments that are within the scope of the claims. That is, no limitations with respect to the embodiments shown and described herein are intended or should be inferred.

[0015] An exemplary sequence of steps that can be used to form a wrap-around contact (WAC) is shown in the figure. Although the disclosed method and resulting structure are directed to a GAA nanosheet architecture, the principles of the invention can be applied to other FET architectures, such as FinFETs.

[0016] An exemplary monolithic structure 20, as shown in Figures 1, 1A and 1B, can be obtained during a manufacturing process that provides a GAA nanosheet architecture. Various techniques for manufacturing such and similar architectures are known in the art, and new techniques continue to be developed. The exemplary structure 20 includes a pFET and an nFET, each including a stack of alternating semiconductor channel layers 21 (shown in cross section in Figure 1B). The semiconductor channel layers 21 can be, for example, silicon nanosheets. The nanosheets can be formed on a semiconductor-on-insulator substrate or on a bulk semiconductor substrate, such as a bulk silicon substrate. Shallow trench isolation (STI) regions 26 formed in the substrate 24 provide electrical isolation of active regions including adjacent transistors or other devices that may be formed on the substrate. In an exemplary embodiment, the active region 24A of the substrate 24 includes a single crystal silicon fin, although impurities may be present in the crystal structure. Single crystal silicon wafers are commercially available and feature a diamond cubic lattice structure. As known in the art, the Miller indices of a substrate are determined from the reciprocals of the points where the crystal planes of silicon intersect with the major crystal axes. Exemplary embodiments described herein relate to structures that include doped or undoped (100) silicon as the substrate material.

[0017] In one or more exemplary embodiments, the semiconductor channel layers 21 each have a thickness in the range of four to ten nanometers (4-10 nm). The number of semiconductor (channel) layers in the semiconductor layer stack may vary depending on the desired application and capabilities of the nanosheet transistor being fabricated. The channel layers 21 may consist essentially of single crystal silicon layers, possibly including impurities, and in some embodiments are spaced apart by six to twenty nanometers (6-20 nm). The width of each semiconductor channel layer 21 is, in some embodiments, about twenty to fifty nanometers (20-50 nm), although this range should be considered exemplary and not limiting.

[0018] Fabrication of the structure 20 can include replacing sacrificial silicon-germanium layers (not shown) between the channel layers 21 by metal gates and gate dielectric materials forming a gate-all-around structure (gate stack) 28 as shown diagrammatically in FIG. 1 and FIG. 1B. Alternating silicon and silicon-germanium layers can be epitaxially grown to obtain a vertical stack with a desired number of silicon (channel) layers. The terms "epitaxially grown and / or deposited" and "epitaxially grown and / or deposited" refer to growing a semiconductor material on a deposition surface of a semiconductor material such that the grown semiconductor material has the same crystalline properties as the semiconductor material on the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled and system parameters are set such that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy, move around on the surface, and orient themselves in the crystalline arrangement of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline properties as the deposition surface on which it is formed.

[0019] The gate structure 28 can have a thickness in the range of six to twenty nanometers (6-20 nm). The dimensional ranges of the channel layer and gate structure should be considered exemplary, not limiting. The gate dielectric layer forms a portion of the gate stack 28 that replaces the sacrificial silicon germanium layer. The gate stack is adjacent to the silicon nanosheet channel layer 21 and extends to the bottom dielectric isolation (BDI) layer 36 and / or the STI region 26. Non-limiting examples of materials suitable for the gate dielectric layer include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k gate dielectric materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials can further include dopants such as, for example, lanthanum and aluminum.

[0020] The gate dielectric layer can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of the gate dielectric material may vary depending on the deposition process, as well as the composition and number of high-k dielectric materials used. In an exemplary embodiment, a high-k dielectric layer having a thickness of 2.5 nm is used. In some embodiments, the gate dielectric layer includes multiple layers.

[0021] Source / drain regions 32P, 32N may be epitaxially grown and merged on the exposed edges of silicon (channel) layer 21. The source / drain regions are electrically isolated from substrate 24 by bottom dielectric isolation (BDI) layer 36. Dopants in source / drain regions 32 may be incorporated in-situ using appropriate precursors, as known in the art. By "in-situ" it is meant that the dopants that determine the conductivity type of the doped layer are introduced during the process step that forms the doped layer, for example during epitaxial deposition. As used herein, the term "conductivity type" refers to a dopant region that is p-type or n-type. As used herein, "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing substrates, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of an impurity that provides free electrons to the intrinsic semiconductor. In silicon-containing substrates, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. Exemplary epitaxial growth processes suitable for use in forming the silicon and / or silicon germanium epitaxy include rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The nFET region includes transistors having n-type source / drain regions, while the pFET region includes p-type source / drain regions. The use of BDI layer 36 is optional for the fabrication of the nFET and pFET transistors described herein.

[0022] Following source / drain epitaxy, the monolithic structure 20 further includes a contact etch stop layer (CESL) formed thereon as a liner. The CESL liner 37 is formed in some embodiments by depositing a conformal layer of a low-k dielectric material, such as silicon nitride, silicon-carbon-boron-nitrogen (SiCBN), silicon-oxycarbide (SiOC), or silicon-carbon-oxynitride (SiCON), over and between the source-drain regions 32P, 32N.

[0023] Next, an interlayer dielectric (ILD) 38, e.g., silicon dioxide (SiO2) or any other material having similar functional properties, is formed over the source-drain regions and the CESL liner 37 by chemical vapor deposition (CVD) or any other suitable deposition technique. The structure 20 further includes a dielectric gate sidewall spacer 42 and a gate cap 44, as shown in FIG. 1B. Techniques for forming such spacers and gate caps are known in the art. The CESL liner 37 also extends over the gate sidewall spacer and the gate cap. Following planarization of the gate cap layer and deposition of an oxide fill, whereby the gate cap is formed, the elements described above are embedded in the ILD layer 38, as shown in FIGS. 1A and 1B.

[0024] 2A and 2B, the ILD layer 38 is selectively removed using, for example, a wet hydrofluoric (HF) acid etch or any other suitable etch. The CESL liner 37 is then selectively removed to yield the structure 30 as shown generally in cross-section in Figures 3A and 3B. In one or more embodiments, the CESL liner 37 may be selectively removed using a wet phosphoric acid etch or other suitable etch.

[0025] A TS liner covering the source / drain regions 32P, 32N may be formed by conformally depositing a titanium (Ti) liner 46 or other suitable metal liner using CVD. Following deposition of the liner 46, an annealing step may be performed at this stage of the process or later to form a titanium silicide and / or titanium-based germanosilicide layer on the source / drain regions. A conformal film is understood to have a substantially uniform thickness. In some exemplary structures including both nFET and pFET regions, the annealing results in the source / drain regions in the nFET region including a TiS2 layer and a titanium germanosilicide (Ti(SiGe)2) layer on the source / drain regions in the pFET region. The terms titanium silicide and metal silicide used hereinafter are intended to encompass silicides formed on either silicon or silicon germanium. The thickness of the Ti liner 46 may be in the range of, for example, two to five nanometers (2 nm to 5 nm). The liner extends further over the STI regions 26, gate sidewall spacers 42, and gate caps 44, as shown in Figures 4A and 4B, resulting in structure 40.

[0026] An organic planarization layer (OPL) 48 is deposited on the structure 40 and patterned to form a block mask. According to one embodiment of the present invention, the OPL 48 may be an organic polymer containing carbon, hydrogen, and nitrogen. Non-limiting examples of OPL materials include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL102, or other similar materials commercially available from vendors such as JSR, TOK, Sumitomo, and Rohm & Haas. The OPL 48 may be deposited, for example, by spin coating, and excess material is etched back. As shown in Figures 5A and 5B, the remaining portions of the OPL extend over the active area 24A of the substrate 24, forming a block mask that protects the active area 24A. The source / drain regions 32P, 32N, portions of the liner 46 covering the source / drain regions, and the gate structure over the active area are embedded within the patterned OPL and are therefore protected. The patterned OPL extends laterally over and beyond the source / drain regions, but leaves exposed the horizontal portions of titanium liner 46 between the pFET and nFET active areas, as shown in Figure 5A. The portions of titanium liner 46 extending over STI regions 26 and gate structures 28 located between the active areas are exposed following OPL patterning in the resulting structure 50.

[0027] The exposed portions of the titanium liner 46 between the active areas 24A are selectively removed. The selective removal of titanium-based materials can be achieved, for example, by a wet process using a sulfuric acid peroxide mixture (SPM) combining the use of sulfuric acid and hydrogen peroxide. As used herein, the term "selective" in relation to a material removal process (e.g., etching) means that, with the selection of an appropriate etchant, the material removal rate (i.e., the etch rate) of the material of interest exceeds, and preferably far exceeds, the removal rate of at least another material exposed to the material removal process. Accordingly, a structure 60 can be obtained as shown diagrammatically in cross section in Figures 6A and 6B. Removal of the OPL 48 from the structure 60 again exposes the titanium-coated source / drain regions 32P, 32N and other structures above the active area 24A of the substrate 24. A structure 70 can be obtained as shown diagrammatically in Figures 7A and 7B. As shown in FIG. 7A, metal liner 46 now includes a horizontal segment 46A that extends partially over STI region 26 and extends laterally beyond the lateral ends of the immediately overlying source / drain regions.

[0028] A further organic planarization layer 48' is deposited and etched back to obtain a structure 80 as shown diagrammatically in Figures 8A and 8B. The OPL 48' may, but need not, comprise the same material as the OPL 48 described above. The OPL 48' may be deposited in the same manner or using a different technique. As shown in Figures 8A and 8B, the thickness of the OPL 48' is sufficient so that the source / drain regions 32P, 32N, which include a titanium (silicide) layer 48 thereon, are embedded within the OPL and therefore protected. Portions of the gate structure 28 and the gate sidewall spacers 42 extend above the top surface of the OPL. The titanium-coated gate cap 44 formed over the active area 24A is fully exposed. By providing a sufficiently uniform recessed OPL 48' below the top surface of the gate cap 44 across the entire wafer on which the field effect transistors are formed, the portion of the titanium layer 46 on the gate cap 44 is completely exposed, but the titanium (or silicide) on the epitaxial source / drain regions 32P, 32N is not exposed.

[0029] The selective titanium chamfer removes the exposed portion of the titanium liner 46 above the top surface of the OPL 48'. As mentioned above, the selective removal of titanium-based material can be performed by a wet process using, for example, a sulfuric peroxide mixture (SPM). Accordingly, a structure 90 can be obtained as shown diagrammatically in cross section in Figures 9A and 9B. The remaining vertical portion 46B of the titanium liner is adjacent to the gate sidewall spacer 42 and terminates below the gate cap 44. The gate structure 28, the upper portion of which is adjacent to the gate cap 44, extends above the vertical portion 46B of the titanium layer 46.

[0030] The second OPL 48' may be removed by ashing or other suitable process to obtain a structure 100 as shown diagrammatically in cross section in Figures 10A and 10B. Here, the liner 46 includes a plurality of individual contiguous segments, each segment including a metal silicide portion and a metal portion extending from the silicide portion. As shown in Figure 10A, the titanium silicide portion of the liner 46 covers the source / drain regions 32P, 32N. The laterally extending metal (non-silicide) portion 46A of the liner 46 extends horizontally a limited distance from the sub-fin region below the bottom dielectric isolation layer 36 to over a portion of the STI region 26. As described above, the laterally extending portion 46A of the liner 46 segment extends further laterally beyond the source / drain regions 32P, 32N of the associated field effect transistor. The vertical portion 46B of the titanium liner 46 segment is localized between pairs of gate structures 28, as shown in Figure 10B. Each vertical portion 46B includes a pair of metal segments adjacent to the gate sidewall spacers 42. The vertical portions 46B are positioned completely below the top surface of the gate structure 28 and the gate cap 44.

[0031] An interlevel dielectric (ILD) layer 52 is deposited on the structure 90 and planarized. The ILD layer can be deposited using deposition techniques including, but not necessarily limited to, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), radio frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD) or liquid source mist chemical deposition (LSMCD) or combinations thereof, spin-on coating, sputtering or plating or combinations thereof. The ILD layer 52 can include, but is not limited to, low-k materials (e.g., k less than about 4.0), such as, for example, porous silicates, carbon doped oxides, silicon dioxide, silicon oxynitrides, carbon doped silicon oxides (SiCOH) and their porous variants, silsesquioxanes, siloxanes, or other dielectric materials having a dielectric constant, for example, in the range of about 2 to about 4.

[0032] An interlevel dielectric (ILD) layer 52 is conformally deposited on the structure 90, thereby filling the spaces between the elements including the nFETs and pFETs above the substrate 24. The interlevel dielectric layer may include a conformal oxide, such as, for example, ALD silicon dioxide in one exemplary embodiment. In one or more embodiments, a flowable ILD material may be used. A substantially carbon-free silicon oxide (SiO2) material may be deposited using, for example, FCVD. Flowable chemical vapor deposition (FCVD) provides a liquid-like film that flows freely into trench-like features, providing bottom-up, void-free, seamless filling. In some embodiments, other dielectric materials may be substituted, but etch selectivity between the ILD layer 52 and the gate sidewall spacers 42, gate cap 44, and metal silicide should be provided. The ILD layer 52 may be optionally cured using a variety of known curing techniques, including UV light assisted curing at less than 400° C. The resulting structure is then subjected to chemical mechanical planarization (CMP). Thereby, a structure 110 can be obtained, as shown diagrammatically in FIGS. 11A and 11B, in which the horizontal portion 46A of the metal liner 46 is localized between the ILD layer 52 and the STI region 26.

[0033] The trench openings are conventionally formed in the ILD layer 52, for example, by using known damascene techniques. The deposition of the ILD layer is followed by photolithography and etching steps. Specifically, a photoresist (not shown) is applied onto the ILD layer. The photoresist may be applied by any suitable technique, including, but not limited to, coating or spin-on techniques. A mask (not shown) patterned with shapes defining the trench openings and / or contact holes to be formed is provided over the photoresist, and the mask pattern is transferred to the photoresist using a photolithography process, creating recesses in the uncovered areas of the photoresist. The patterned photoresist is then used to create recesses of the same pattern in the ILD dielectric layer by conventional etching typically used to form trenches and contact holes. Such trenches and contact holes may be formed using a dry etch (e.g., reactive ion etching). The etch selectively removes portions of the ILD layer 52. After the formation of the trench openings 54, the photoresist may be stripped from the ILD layer by ashing or other suitable process. The resulting structure 120 may be subjected to a wet cleaning, as shown generally in Figures 12A and 12B.

[0034] After the resist is stripped, the trench (via) opening is cleaned and then lined, for example, with a thin PVD (e.g., sputtered) titanium (Ti) layer (not shown). The Ti film acts as an adhesion layer and also reduces the contact resistance to the underlying conductor by reducing the interfacial oxide. Subsequently, titanium nitride (TiN) (not shown) is deposited by either sputtering or CVD. A contact metal layer 56, for example tungsten (W) or cobalt (Co), is conformally deposited on the structure, filling the trenches 54 formed in the ILD layer 52 and directly contacting the metal silicide and / or metal germanosilicide layers formed on the source / drain regions 32N, 32P from the metal liner 46. As shown in FIG. 13B, the vertically extending portion 46B of the liner also contacts the metal contact layer 56. In some embodiments, the contact metal layer is a tungsten (W) layer deposited using a tungsten hexafluoride source with silane. Chemical vapor deposition performed using tungsten hexafluoride precursor chemicals at 300-400°C may be used to deposit the tungsten layer, for example. The contact material may alternatively include, for example, tantalum (Ta), aluminum (Al), platinum (Pt), gold (Au), titanium (Ti), palladium (Pd), or any combination thereof. The contact material may be deposited, for example, by CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A structure 130 as shown diagrammatically in Figures 13A and 13B may be obtained after trench silicide metallization as described above.

[0035] A planarization process such as CMP is performed to remove any conductive material (overburden) from the top surface of the structure. The thickness of the ILD layer 52 may also be reduced using CMP to obtain a structure 140 as shown diagrammatically in Figures 14A and 14B. As shown in Figure 14A, the metal silicide covers the source / drain regions 32P, 32N. As shown in Figure 14B, the metal silicide around the source / drain regions and the continuous portion 46B of the liner 46 that extends above the source / drain regions are localized between the gate structures 28. All remaining portions of the liner 46 are located below the top surface of the gate structures 28. A semiconductor structure 140 may be provided that includes a gate-all-around (GAA) architecture, wrap-around source / drain contacts, and localized metal / silicide. Furthermore, the combination of block mask patterning and chamfering to fabricate such a structure eliminates the need for reverse grayscale patterning.

[0036] The figures described above depict exemplary process steps / stages in the fabrication of an exemplary structure. While the overall fabrication method and structures formed thereby are entirely novel, the specific individual process steps required to carry out the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tools. These techniques and tools will be familiar to those of skill in the art in light of the teachings herein. Moreover, one or more of the process steps and tools used to fabricate semiconductor devices may be similar to those described in, for example, James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1999, Vol. 1, No. 1, pp. 111-115, 2002. st Edition, Prentice Hall, 2001. While certain individual process steps are described herein, it is emphasized that these steps are merely exemplary and that one of ordinary skill in the art may be familiar with several equally suitable alternatives that may be applicable.

[0037] It should be understood that the various layers and / or regions illustrated in the accompanying figures may not be drawn to scale. Additionally, one or more semiconductor layers of the type commonly used in such integrated circuit devices or other layers may not be explicitly shown in a given figure for ease of illustration. This does not imply that the semiconductor layers or other layers not explicitly shown are omitted in the actual integrated circuit device.

[0038] In view of the preceding discussion, it will be understood that, in general terms, an exemplary method for forming a semiconductor structure including a wrap-around contact includes conformally depositing a metal liner on a monolithic structure including first and second active regions 24A and field effect transistors (FETs) on the first and second active regions. FIGS. 3A and 3B show an exemplary monolithic structure 30 including a nanosheet FET. The FET includes a gate structure 28 and epitaxial source / drain regions 32P and / or 32N. A metal silicide liner is formed on the epitaxial source / drain regions from the metal liner, covering the source / drain regions. The first and second active regions are protected with a patterned block mask 48, as shown generally in FIGS. 5A and 5B. The metal liner is selectively removed from the areas exposed by the patterned block mask between the first and second active regions. After removing the patterned block mask 48, a structure 70 as shown in Figures 7A and 7B is obtained. A protective mask 48' is formed on the monolithic structure as shown in Figures 8A and 8B. The protective mask protects the epitaxial source / drain regions that are completely below the top surface of the protective mask. Portions of the metal liner 46 above the first and second active areas are exposed. The exposed portions of the metal liner 46 above the active areas are removed, followed by removal of the protective mask 48'. Accordingly, a monolithic semiconductor structure 100 as shown in Figures 10A and 10B can be obtained, it being understood that the exemplary method is applicable with respect to nanosheet transistors as shown, as well as other types of FETs, such as FinFETs.

[0039] In an exemplary embodiment, forming the protective mask includes depositing an organic planarization layer over the monolithic structure and etching back the organic planarization layer to expose the tops of the gate structures 28 and associated gate sidewall spacers 42 and gate caps 44. The method can include forming an interlevel dielectric layer 52 over the monolithic structure, patterning the interlevel dielectric layer to thereby expose the metal silicide liners over the epitaxial source / drain regions 32P, 32N as shown in Figures 12A and 12B, and forming metal contacts 56 in the interlevel dielectric layer that directly contact the metal silicide liners over the epitaxial source / drain regions. Figures 13A and 13B show an exemplary structure 130 after contact metallization. The monolithic structure 30 in one or more exemplary embodiments further includes a gate cap 44 and a gate sidewall spacer 42 adjacent the gate structure, and selectively removing the metal liner 46 over the top of the gate structure includes removing the metal liner from the gate cap and a portion of the gate sidewall spacer. The monolithic structure in one or more embodiments includes a shallow trench isolation region 26, and selectively removing the metal liner 46 from the region between the first active area and the second active area includes removing the metal liner from a top surface of the shallow trench isolation region 26.

[0040] A semiconductor structure provided according to one or more embodiments includes a semiconductor substrate 24 including a first active region 24A and a second active region 24A, and a shallow trench isolation region 26 between the first and second active regions. A first field effect transistor on the first active region includes a gate structure 28 on the first active region, a channel region (a region of layer 21 adjacent the gate structure), and a pair of epitaxial source / drain regions 32P or 32N on either side of the channel region. Each epitaxial source / drain region is located between the pair of gate structures on the first active region. A wrap-around metal silicide liner (a silicide portion of conformal metal layer 46) is adjacent to each epitaxial source / drain region of the first field effect transistor. A dielectric layer 52 extends over the semiconductor substrate and the first field effect transistor. A metal liner portion is contiguous with each metal silicide liner, respectively. Each metal liner portion is located between a pair of gate structures 28 on the first active region and includes a vertically extending portion 46B that extends above the source / drain regions. The gate structures 28 on the first active region extend vertically above the vertically extending portions 46B. The horizontally extending metal liner portion 46A extends below the source / drain regions of the first field effect transistor and is disposed between the shallow trench isolation region 26 and the dielectric layer 52. For example, as shown in FIG. 14A, the horizontally extending portion 46A of each metal liner portion extends laterally beyond one of the source / drain regions of the first field effect transistor directly above.

[0041] At least some of the techniques described above can be implemented in integrated circuits. In forming integrated circuits, identical dies are typically manufactured in a repeating pattern on the surface of a semiconductor wafer. Each die includes the devices described herein and may include other structures and / or circuits. The individual dies are cut or diced from the wafer and then packaged as integrated circuits. Those skilled in the art will know how to dice a wafer and package the dies to produce integrated circuits.

[0042] Those skilled in the art will appreciate that the exemplary structures described above may be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare die, in packaged form, or may be incorporated as part of an intermediate or final product that would benefit from having nanosheet or other FET devices with wrap-around contacts formed in accordance with one or more of the exemplary embodiments.

[0043] There are numerous techniques used by those skilled in the art to remove material at various stages in creating semiconductor structures. As used herein, these processes are generally referred to as "etching." For example, etching includes wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, all of which are known techniques for removing selective materials in forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid, and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art, and therefore a more detailed description of such processes is not presented herein.

[0044] The illustrations of the embodiments described herein are intended to provide a general understanding of the various embodiments, and are not intended to serve as a complete description of all elements and features of devices and systems that may utilize the circuits and techniques described herein. Many other embodiments will be apparent to those skilled in the art in view of the teachings herein. Other embodiments may be utilized and derived from the present teachings, such that structural and logical substitutions and changes may be made without departing from the scope of the present invention. It should also be noted that in some alternative implementations, some of the steps of the exemplary method may be performed out of the order shown in the figures. For example, two steps shown in succession may in fact be performed substantially simultaneously, or certain steps may sometimes be performed in the reverse order, depending on the functionality involved. Additionally, the drawings are merely representative and not drawn to scale. Accordingly, the specification and drawings should be considered in an illustrative and not restrictive sense.

[0045] The embodiments may be referred to herein by the term "embodiment" either individually or collectively or both for convenience only, and are not intended to limit the scope of the present application to any single embodiment or inventive concept when more than one embodiment is actually shown. Thus, while specific embodiments have been illustrated and described herein, it should be understood that configurations which achieve the same purpose may be substituted for the specific embodiments illustrated. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will be apparent to those of skill in the art in light of the teachings herein.

[0046] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", as used herein, specify the presence of stated features, steps, operations, elements, or components, or combinations thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, or groups thereof, or combinations thereof. Terms such as "above" and "below" as well as "vertical" are used to indicate the relative positions of elements or structures with respect to one another, rather than relative heights.

[0047] The corresponding structures, materials, acts, and equivalents of any means or step-plus-function elements in the following claims are intended to include any structures, materials, or acts for performing a function in combination with other claimed elements as specifically claimed. The description of the various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The embodiments have been chosen and described in order to best explain the principles and practical applications, and to enable others skilled in the art to appreciate the various embodiments with various modifications as suited to the particular use contemplated.

[0048] The Abstract is provided in accordance with 37 C.FR §1.72(b). This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above Detailed Description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the appended claims reflect, claimed subject matter may reside in less than all features of a single embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

[0049] Given the teachings provided herein, those skilled in the art will be able to envision other implementations and applications of the techniques and disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the exemplary embodiments are not limited to those precise embodiments, and that various other changes and modifications may be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. 1. A semiconductor structure comprising: a semiconductor substrate including a first active region and a second active region; a shallow trench isolation region between the first active area and the second active area; a plurality of gate structures on the first active area; a first field effect transistor on the first active region, the first field effect transistor comprising one of the gate structures on the first active region, a channel region, and a pair of epitaxial source / drain regions on either side of the channel region, each of the epitaxial source / drain regions being located between the pair of gate structures on the first active region; a wrap-around metal silicide liner adjacent each of the epitaxial source / drain regions of the first field effect transistor; a dielectric layer extending over the semiconductor substrate and the first field effect transistor; a metal liner portion contiguous with each of the metal silicide liners, the metal liner portion comprising: a vertical extending portion located between a pair of the gate structures on the first active region and extending above the source / drain region; and a horizontally extending portion disposed below the source / drain regions of the first field effect transistor and between the shallow trench isolation region and the dielectric layer, the horizontally extending portion of each metal liner portion extending laterally beyond one of the source / drain regions of the first field effect transistor; the metal liner portion comprising: Equipped with further comprising gate sidewall spacers on sidewalls of the gate structure, the vertically extending portions of the metal liner portions being adjacent to the gate sidewall spacers, and the gate structure over the first active area extending vertically above the vertically extending portions of the metal liner portions. Semiconductor structure.

2. a plurality of gate structures on the second active region; a second field effect transistor on the second active region, the second field effect transistor comprising one of the gate structures on the second active region, a channel region, and a pair of epitaxial source / drain regions on either side of the channel region, each of the epitaxial source / drain regions being located between a pair of the gate structures, and the dielectric layer extending over the second field effect transistor; a wrap-around metal silicide liner adjacent each of the epitaxial source / drain regions of the second field effect transistor; a metal liner portion contiguous with each metal silicide liner of the second field effect transistor, the metal liner portion comprising: a vertical extension portion located between a pair of the gate structures on the second active region and extending above the source / drain region of the second field effect transistor, the gate structure on the second active region extending vertically above the vertical extension portion; and a horizontally extending portion disposed below the source / drain regions of the second field effect transistor and between the shallow trench isolation region and the dielectric layer, the horizontally extending portion of each metal liner portion extending laterally beyond one of the source / drain regions of the second field effect transistor. the metal liner portion comprising: Equipped with the gate structure on the second active area extends vertically above the vertical extension of the metal liner portion.

10. The semiconductor structure of claim 1.

3. 3. The semiconductor structure of claim 2 further comprising a bottom dielectric isolation layer beneath said first field effect transistor and said second field effect transistor, said metal liner portion extending over an edge portion of said bottom dielectric isolation layer.

4. 1. A semiconductor structure comprising: a semiconductor substrate including a first active region and a second active region; a shallow trench isolation region between the first active area and the second active area; a plurality of gate structures on the first and second active areas; a first field effect transistor on the first active area, the first field effect transistor comprising one of the gate structures on the first active area, a channel region, and a first pair of epitaxial source / drain regions on either side of the channel region, each of the epitaxial source / drain regions being located between the first pair of gate structures on the first active area; a second field effect transistor on the second active region, the second field effect transistor comprising one of the gate structures on the second active region, a channel region, and a second pair of epitaxial source / drain regions on either side of the channel region, each of the epitaxial source / drain regions being located between the second pair of gate structures on the second active region; a dielectric layer covering the semiconductor substrate and the first and second field effect transistors; a metal silicide liner surrounding each of the first and second pairs of epitaxial source / drain regions; a metal liner portion contiguous with each of the metal silicide liners, the metal liner portion comprising: a vertically extending portion located between each pair of the gate structures of the first and second pairs and extending vertically above at least one of the first and second epitaxial source / drain regions; and a horizontally extending portion disposed below the epitaxial source / drain regions of the first and second field effect transistors and between the shallow trench isolation region and the dielectric layer, the horizontally extending portion extending laterally beyond at least one of the epitaxial source / drains; the metal liner comprising: Equipped with a bottom dielectric isolation layer beneath the first field effect transistor and the second field effect transistor, the metal liner portion extending over an edge portion of the bottom dielectric isolation layer. Semiconductor structure.

5. a plurality of vertically extending trenches in the dielectric layer; a contact metal in the trench, the contact metal contacting the metal silicide liner adjacent the epitaxial source / drain regions of the first and second field effect transistors; 5. The semiconductor structure of claim 2 further comprising:

6. 5. The semiconductor structure of any one of claims 2 to 4 wherein said first and second field effect transistors are nanosheet transistors and said epitaxial source / drain regions comprise doped facet structures.

7. 5. The semiconductor structure of claim 2 wherein said active region comprises a semiconductor fin.

8. 8. The semiconductor structure of claim 2 wherein said channel region of each of said first field effect transistor and said second field effect transistor comprises a plurality of vertically stacked channel layers.

9. 1. A method of forming a semiconductor structure including a wrap around contact, comprising: Conformally depositing a metal liner onto the monolithic structure, said monolithic structure comprising: first and second active regions; and a field effect transistor on said first and second active regions, said field effect transistor including a gate structure and an epitaxial source / drain region; depositing on said conformal form, forming a metal silicide liner from the metal liner on the epitaxial source / drain regions to cover the epitaxial source / drain regions; protecting the first and second active areas with a patterned block mask; selectively removing the metal liner from areas exposed by the patterned block mask between the first active area and the second active area; removing the patterned block mask; and forming a protective mask over the monolithic structure such that the epitaxial source / drain regions are completely below a top surface of the protective mask and such that portions of the metal liner above the first and second active areas are exposed; selectively removing exposed portions of the metal liner over the first and second active areas; removing the protective mask; A method comprising:

10. forming the protective mask depositing an organic planarization layer over the monolithic structure; etching back the organic planarization layer such that a portion of the gate structure extends above the top surface of the protective mask; 10. The method of claim 9, comprising:

11. forming an interlevel dielectric layer over the first and second active regions; patterning the interlevel dielectric layer thereby exposing the metal silicide liner on the epitaxial source / drain regions; forming metal contacts in the interlevel dielectric layer directly contacting the metal silicide liner on the epitaxial source / drain regions; The method of claim 9 or 10, further comprising:

12. 12. The method of claim 9, wherein the monolithic structure further comprises a gate cap and a gate sidewall spacer adjacent the gate structure, and further wherein selectively removing the exposed portions of the metal liner over the first and second active areas comprises removing the metal liner from a top of the gate cap and the gate sidewall spacers.

13. 13. The method of claim 9, wherein the monolithic structure includes a shallow trench isolation region between the first active area and the second active area, and further wherein selectively removing the metal liner from the region between the first active area and the second active area includes removing the metal liner from a top surface of the shallow trench isolation region.

14. the monolithic structure further includes a contact etch stop liner extending over the first and second active regions and the shallow trench isolation region; removing said contact etch stop liner and replacing said contact etch stop liner with said metal liner; The method of claim 13 further comprising:

15. 15. The method of any one of claims 9 to 14, wherein the field effect transistor comprises a nanosheet transistor or a FinFET transistor.

16. 15. The method of any one of claims 9 to 14, wherein the field effect transistor comprises a nanosheet transistor or a FinFET transistor, the epitaxial source / drain region comprises a doped facet semiconductor region, and further comprising conformally depositing the metal liner such that the metal liner covers the doped facet semiconductor region.

17. 17. The method of any one of claims 9 to 16, wherein the patterned block mask completely covers and extends laterally beyond the epitaxial source / drain regions.

18. the monolithic structure further comprising a gate cap and a gate sidewall spacer adjacent the gate structure; forming the protective mask includes depositing an organic planarization layer over the monolithic structure and etching back the organic planarization layer, thereby exposing the gate cap and a top of the gate sidewall spacer; selectively removing the exposed portions of the metal liner over the first and second active areas includes removing the metal liner from the gate cap and the top of the gate sidewall spacers.

18. The method according to any one of claims 9 to 17.

19. 1. A method of forming a semiconductor structure including a wrap around contact, comprising: first and second active regions; a field effect transistor on the first and second active areas, the field effect transistor including a gate structure, a gate cap above the gate structure, gate sidewall spacers on sidewalls of the gate structure, and epitaxial source / drain regions between the pair of gate structures; and a continuous liner including a first liner portion on the epitaxial source / drain region and encapsulating the epitaxial source / drain region, and a metal liner extending over the gate cap and gate sidewall spacers between the first active area and the second active area; Obtaining a monolithic structure comprising: protecting the first and second active areas with a patterned block mask; selectively removing the metal liner from areas exposed by the patterned block mask between the first active area and the second active area; removing the patterned block mask; and forming a protective mask over the monolithic structure such that tops of the gate cap and the gate sidewall spacers extend above a top surface of the protective mask and the epitaxial source / drain regions are below the top surface of the protective mask; selectively removing the metal liner from the tops of the gate sidewall spacers and from the gate cap; removing the protective mask; A method comprising:

20. the field effect transistor comprises a nanosheet transistor or a FinFET transistor; forming a metal silicide liner from the first liner portion; forming an interlevel dielectric layer over the first and second active regions; patterning the interlevel dielectric layer thereby exposing the metal silicide liner on the epitaxial source / drain regions; forming metal contacts in the interlevel dielectric layer directly contacting the metal silicide liner on the epitaxial source / drain regions; 20. The method of claim 19, further comprising:

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