3D Memory Device

Abstract

To provide three-dimensional memory devices and methods for forming the same.SOLUTION: A 3D memory device includes: a substrate; a peripheral circuit on the substrate; a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit; an N-type doped semiconductor layer above the memory stack; a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer; and a source contact above the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for fabricating the same. [Background technology]

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become more difficult and costly. As such, the memory density of planar memory cells is approaching an upper limit.

[0003] 3D memory architectures can address this density limitation of planar memory cells. 3D memory architectures include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention [Means for solving the problem]

[0004] SUMMARY OF THE DISCLOSURE Disclosed herein are embodiments of 3D memory devices and methods for forming the same.

[0005] In one example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including alternating conductive and dielectric layers on the peripheral circuit, an N-type doped semiconductor layer on the memory stack, a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer, and a source contact on the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is coplanar with or below a top surface of the N-type doped semiconductor layer.

[0006] In another example, a 3D memory device includes a substrate, a memory stack including alternating conductive and dielectric layers over the substrate, an N-type doped semiconductor layer over the memory stack, and a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer. Each of the plurality of channel structures includes a memory film and a semiconductor channel. An upper end of the memory film is below an upper end of the semiconductor channel. The N-type doped semiconductor layer includes a semiconductor plug surrounding and contacting a portion of the semiconductor channel. A doping concentration of the semiconductor plug is different from a doping concentration of a remainder of the N-type doped semiconductor layer.

[0007] In yet another example, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a junction interface between the first and second semiconductor structures. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a memory stack including alternating conductive and dielectric layers, an N-type doped semiconductor layer, and a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuit. The N-type doped semiconductor layer includes a semiconductor plug surrounding a portion of each of the plurality of channel structures penetrating into the N-type doped semiconductor layer. The doping concentration of the semiconductor plug is different from the doping concentration of the remaining portion of the N-type doped semiconductor layer.

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure. [Brief description of the drawings]

[0009] [Figure 1] 1 is a side view illustrating a cross-section of an example 3D memory device according to some embodiments of the present disclosure. [Diagram 2] 1 is a side view illustrating a cross section of another example 3D memory device according to some embodiments of the present disclosure. [Figure 3A]1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3B] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3C] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3D] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3E] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3F] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3G] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3H] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3I] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3J] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3K] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3L] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3M]1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 3N] 1A-1D illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4A] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4B] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4C] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4D] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4E] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4F] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4G] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4H] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4I] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4J] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4K]1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4L] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4M] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4N] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 4O] 1A-1C illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 5A] 1 is a flowchart of an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure. [Figure 5B] 1 is a flowchart of another method for forming an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 6A] 1 is a flowchart of a method for forming another exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 6B] 1 is a flowchart of another exemplary method for forming a 3D memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0011] While specific configurations and arrangements have been described, it will be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be employed in a variety of other applications.

[0012] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like, indicate that the embodiment being described may comprise a particular feature, structure, or characteristic, but that all embodiments may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in the context of one embodiment, it will be within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in the context of other embodiments, whether or not explicitly described.

[0013] Generally, terms may be understood, at least in part, from their usage in context. For example, the phrase "one or (or) more" as used herein may be used in a singular sense to describe a feature, structure, or characteristic, or in a plural sense to describe a combination of features, structures, or characteristics, depending at least in part on the context. Similarly, articles such as "a," "an," or "the" in English text may be understood as conveying singular use or conveying plural use, depending at least in part on the context. In addition, the phrase "based on" may be understood as not necessarily intended to convey an exclusive series of elements, but may instead permit the presence of additional elements not necessarily expressly described, again depending at least in part on the context.

[0014] It should be readily understood that the meanings of "on," "above," and "directly above" in this disclosure are to be interpreted in their broadest sense such that "on" not only means "directly above" something, but can also include the meaning "on top of" something with an intervening intermediate feature or layer, and "above" or "directly above" not only means "above" something or "directly above" something, but can also include the meaning "above" something or "directly above" something (i.e., directly above) without any intervening features or layers.

[0015] Spatially relative terms such as "below," "lower," "lower," "above," "upper," and similar terms may be used herein for ease of description in describing the relationship of one element or feature to another as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in some other way (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein similarly interpreted accordingly.

[0016] As used herein, the term "substrate" refers to a material onto which a subsequent layer of material is applied. The substrate itself can be patterned. The material applied onto the substrate can be patterned or left unpatterned. Additionally, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

[0017] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend throughout an underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be disposed between a top surface and a bottom surface of a continuous structure, or between a pair of horizontal surfaces at the top and bottom surfaces. A layer may extend along a horizontal, vertical, and / or tapered surface. A substrate may be a layer and may include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer may also include multiple layers. For example, an interconnect layer may include one or more conductor layers and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0018] As used herein, the phrase "nominal / nominal" refers to a desired or target value of a characteristic or parameter for a component or process operation that is set during the design phase of the product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or manufacturing tolerances. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND memory strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction with respect to the substrate. As used herein, the phrase "vertical" means nominally perpendicular to an outer surface of the substrate.

[0020] In some 3D memory devices, such as 3D NAND memory devices, slit structures (e.g., gate line slit (GLS)) are used to electrically connect to the source of the memory array, such as the array common source (ACS), from the front side of the device. However, the front side source contact can affect the electrical performance of the 3D memory device by introducing both leakage current and parasitic capacitance between the word line and the source contact, even with the presence of a spacer in between. The formation of the spacer also complicates the fabrication process. In addition to affecting the electrical performance, the slit structures usually contain wall-shaped polysilicon and / or build-up, which can introduce local stress and cause the wafer to bow or warp, thereby reducing production yields.

[0021] Furthermore, in some 3D NAND memory devices, the semiconductor plug is selectively grown, for example, to surround the sidewall of the channel structure, which is called sidewall selective epitaxial growth (SEG). Compared with another type of semiconductor plug formed at the lower end of the channel structure, for example, bottom SEG, the formation of sidewall SEG avoids etching of the memory film and semiconductor channel at the bottom of the channel hole (also called "SONO" punch), thereby increasing the process window, especially when fabricating 3D NAND memory devices with advanced technologies, such as having 96 or more levels in a multi-deck architecture. Sidewall SEG is usually formed by replacing a sacrificial layer between the substrate and the stack structure with sidewall SEG, which involves multiple deposition and etching processes through slit openings. However, as the levels of 3D NAND memory devices continue to increase, the aspect ratio of the slit openings through the stack structure becomes larger, making the deposition and etching process through the slit openings more difficult and undesirable to form sidewall SEGs using known approaches due to increased costs and reduced yields.

[0022] Various embodiments according to the present disclosure provide a 3D memory device with a backside source contact. By moving the source contact from the frontside to the backside, the effective memory cell array area is increased, and the cost per memory cell can be lowered since the spacer formation process can be skipped. Moreover, the device performance can be improved by avoiding the leakage current and parasitic capacitance between the word line and the source contact, and by reducing the local stress caused by the frontside slit structure (as the source contact). The sidewall SEG (e.g., semiconductor plug) is formed from the backside of the substrate, which can avoid the deposition or etching process through the opening penetrating the stack structure on the frontside of the substrate. As a result, the complexity and cost of the fabrication process can be reduced, and the product yield can be enhanced. Also, the scalability of the 3D memory device can be improved because the fabrication process of the sidewall SEG is no longer affected by the aspect ratio of the opening penetrating the stack structure, i.e., it is not limited to the level of the memory stack.

[0023] In some embodiments, the substrate on which the memory stack is formed is removed from the backside to expose the channel structure prior to the formation of the sidewall SEG. Thus, the choice of substrate can be extended to, for example, a dummy wafer to reduce cost, or a silicon-on-insulator (SOI) wafer to simplify the fabrication process. Removal of the substrate can also avoid the difficult problem of thickness uniformity control in known methods using a backside thinning process.

[0024] For example, various 3D memory device architectures and fabrication methods thereof having different erase operation mechanisms are disclosed in the present disclosure to accommodate different requirements and applications. In some embodiments, the sidewall SEG is part of an N-type doped semiconductor layer to enable gate-induced drain leakage (GIDL) erase by the 3D memory device. In some embodiments, the sidewall SEG is part of a P-type doped semiconductor layer to enable P-well bulk erase by the 3D memory device.

[0025] 1 is a side view illustrating a cross section of an exemplary 3D memory device 100 according to some embodiments of the present disclosure. In some embodiments, the 3D memory device 100 is a bonded chip comprising a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 are coupled at a bonded interface 106 therebetween according to some embodiments. As shown in FIG. 1, the first semiconductor structure 102 may include a substrate 101, which may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), SOI, or any other suitable material.

[0026] The first semiconductor structure 102 of the 3D memory device 100 may include a peripheral circuit 108 on the substrate 101. Note that x-axis and y-axis are included in FIG. 1 to further illustrate the spatial relationships of components in the 3D memory device 100 with the substrate 101. The substrate 101 includes two outer sides (e.g., top and bottom) that extend laterally (i.e., laterally) in the x-direction. As used herein, whether one component (e.g., a layer or device) is "on," "above," or "below" another component (e.g., a layer or device) of the semiconductor device (e.g., the 3D memory device 100) is determined with respect to the substrate (e.g., substrate 101) of the semiconductor device in the y-direction (i.e., vertical direction) when the substrate is positioned at the bottommost plane of the semiconductor device in the y-direction. The same concepts for describing spatial relationships are applied throughout this disclosure.

[0027] In some embodiments, the peripheral circuits 108 are configured to control and sense the 3D memory device 100. The peripheral circuits 108 may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to facilitate operation of the 3D memory device 100, including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits 108 may include transistors formed "on" the substrate 101, with all or a portion of the transistors formed in (e.g., below the top surface of) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) may also be formed in the substrate 101. The transistors are fast, according to some embodiments, using advanced logic processes (e.g., technology nodes such as 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.) It is understood that in some embodiments, the peripheral circuits 108 may further include any other circuitry compatible with advanced logic processes, including logic circuits such as processors and programmable logic devices (PLDs), or memory circuits such as static random access memories (SRAMs) and dynamic RAMs (DRAMs).

[0028] In some embodiments, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuitry 108 for communicating electrical signals to and from the peripheral circuitry 108. The interconnect layer may include a plurality of interconnects (also referred to herein as "contacts") including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term "interconnect" may be broadly defined to include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer may further include one or more interlayer dielectric (ILD) layers (also referred to as "intermetal dielectric (IMD) layers") in which the interconnect lines and VIA contacts may be formed. That is, the interconnect layer may include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers in the interconnect layer may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0029] As shown in FIG. 1, the first semiconductor structure 102 of the 3D memory device 100 may further include a bonding layer 110 at the bonding interface 106 and above the interconnect layer and the peripheral circuitry 108. The bonding layer 110 may include a plurality of bonding contacts 111 and a dielectric that electrically insulates the bonding contacts 111. The bonding contacts 111 may include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. The remaining regions of the bonding layer 110 may be formed by a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 111 and the surrounding dielectric in the bonding layer 110 may be used for hybrid bonding.

[0030] Similarly, as shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 may also include a bonding layer 112 at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 may include a plurality of bonding contacts 113 and a dielectric that electrically insulates the bonding contacts 113. The bonding contacts 113 may include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. The remaining regions of the bonding layer 112 may be formed by a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 113 and the surrounding dielectric in the bonding layer 112 may be used for a hybrid bond. The bonding contacts 113 contact the bonding contacts 111 at the bonding interface 106 according to some embodiments.

[0031] As described in detail below, the second semiconductor structure 104 may be bonded on the first semiconductor structure 102 face-to-face at the bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 110 and 112 as a result of a hybrid bond (also called a "metal / dielectric hybrid bond"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as a solder or adhesive) that can simultaneously obtain a metal-metal bond and a dielectric-dielectric bond. In some embodiments, the bonding interface 106 is where the bonding layers 112 and 110 come into contact and are bonded. In practice, the bonding interface 106 may be a layer having a certain thickness that includes the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0032] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 to transfer electrical signals. The interconnect layer can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which interconnect lines and VIA contacts can be formed. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0033] In some embodiments, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can include an array of channel structures 124 that function as an array of NAND memory strings. As shown in FIG. 1, each channel structure 124 can vertically penetrate multiple pairs, each including a conductive layer 116 and a dielectric layer 118. The interleaved conductive layers 116 and dielectric layers 118 are part of a memory stack 114. The number of pairs of conductive layers 116 and dielectric layers 118 in the memory stack 114 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in the 3D memory device 100. It is understood that in some embodiments, the memory stack 114 can have a multi-deck architecture (not shown) that includes multiple memory decks stacked on top of each other. The number of pairs of conductive layers 116 and dielectric layers 118 in each memory deck may be the same or different.

[0034] The memory stack 114 may include multiple interleaved conductive layers 116 and dielectric layers 118. The conductive layers 116 and dielectric layers 118 in the memory stack 114 may alternate vertically. In other words, each conductive layer 116, except for the one at the top or bottom of the memory stack 114, may be adjacent to two dielectric layers 118 on either side, and each dielectric layer 118 may be adjacent to two conductive layers 116 on either side. The conductive layers 116 may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 116 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer 116 may extend laterally as a word line and terminate at one or more staircase structures of the memory stack 114. The dielectric layer 118 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0035] As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 can also include an N-type doped semiconductor layer 120 above the memory stack 114. The N-type doped semiconductor layer 120 can be an example of a "sidewall SEG" as described above. The N-type doped semiconductor layer 120 can include a semiconductor material, such as silicon. In some embodiments, the N-type doped semiconductor layer 120 includes polysilicon formed by deposition techniques, as described in more detail below. In some embodiments, the N-type doped semiconductor layer 120 includes single crystal silicon, such as a device layer of an SOI wafer, as described in more detail below. The N-type doped semiconductor layer 120 can be doped with any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contributes to providing free electrons and increasing the conductivity of the intrinsic semiconductor. For example, the N-type doped semiconductor layer 120 can be a polysilicon layer doped with an N-type dopant, such as P, Ar, or Sb. In some embodiments, N-type doped semiconductor layer 120 is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having multiple polysilicon sublayers with non-uniform doping concentrations at their interfaces (e.g., an abrupt doping concentration change at the interface between the two sublayers). It is understood that the doping concentration of the N-type dopant in N-type doped semiconductor layer 120 can still vary gradually in the vertical direction, so long as there is no abrupt doping concentration change that allows two or more sublayers to be distinguished by the change in doping concentration.

[0036] In some embodiments, each channel structure 124 includes a channel hole filled with a semiconductor layer (e.g., as the semiconductor channel 128) and a composite dielectric layer (e.g., as the memory film 126). In some embodiments, the semiconductor channel 128 includes silicon, such as amorphous silicon, polysilicon, or single crystal silicon. In some embodiments, the memory film 126 is a composite layer including a tunnel layer, a storage layer (also referred to as a "charge trapping layer"), and a blocking layer. The remaining space of the channel structure 124 may be partially or completely filled with a capping layer including a dielectric material, such as silicon oxide, and / or voids. The channel structure 124 may have a cylindrical shape (e.g., a pillar shape). The capping layer, the semiconductor channel 128, the tunnel layer, the storage layer, and the blocking layer of the memory film 126 are radially arranged in this order from the center toward the outer surface of the pillar according to some embodiments. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 126 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0037] In some embodiments, the channel structure 124 further includes a channel plug 129 at a bottom (e.g., lower end) of the channel structure 124. As used herein, the "upper end" of a component (e.g., channel structure 124) is the end that is farther from the substrate 101 in the y-direction, and the "lower end" of a component (e.g., channel structure 124) is the end that is closer to the substrate 101 in the y-direction when the substrate 101 is positioned in the bottom-most plane of the 3D memory device 100. The channel plug 129 can include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 129 functions as a drain of a NAND memory string.

[0038] As shown in FIG. 1, each channel structure 124 may penetrate vertically through the alternating conductor layers 116 and dielectric layers 118 of the memory stack 114 into the N-type doped semiconductor layer 120. The upper end of each channel structure 124 may be flush with or below the top surface of the N-type doped semiconductor layer 120. That is, the channel structure 124 does not extend beyond the top surface of the N-type doped semiconductor layer 120 according to some embodiments. In some embodiments, as shown in FIG. 1, the upper end of the memory film 126 is below the upper end of the semiconductor channel 128 of the channel structure 124. In some embodiments, the upper end of the memory film 126 is below the top surface of the N-type doped semiconductor layer 120 and the upper end of the semiconductor channel 128 is flush with or below the top surface of the N-type doped semiconductor layer 120. 1, the memory film 126 may terminate at a bottom surface of the N-type doped semiconductor layer 120 and the semiconductor channel 128 may extend above the bottom surface of the N-type doped semiconductor layer 120 such that the N-type doped semiconductor layer 120 surrounds and contacts a top portion 127 of the semiconductor channel 128 that penetrates into the N-type doped semiconductor layer 120. In some embodiments, the doping concentration of the top portion 127 of the semiconductor channel 128 that penetrates into the N-type doped semiconductor layer 120 is different from the doping concentration of the remainder of the semiconductor channel 128. For example, the semiconductor channel 128 may include undoped polysilicon except for the top portion 127, which may include doped polysilicon to enhance conductivity in forming an electrical connection with the surrounding N-type doped semiconductor layer 120.

[0039] In some embodiments, the N-type doped semiconductor layer 120 includes semiconductor plugs 122 each surrounding and contacting a top 127 of a respective semiconductor channel 128 of a channel structure 124 penetrating into the N-type doped semiconductor layer 120. The semiconductor plugs 122, according to some embodiments, include doped polysilicon, e.g., N-type doped polysilicon. The semiconductor plugs 122 may be formed in a later process after the formation of the remaining portion of the N-type doped semiconductor layer 120, as described in detail below, so that the doping concentration of the semiconductor plugs 122 may be different from the doping concentration of the remaining portion of the N-type doped semiconductor layer 120. In some embodiments, the semiconductor plugs 122 include polysilicon (e.g., N-type doped polysilicon), and the remaining portion of the N-type doped semiconductor layer 120 includes single crystal silicon (e.g., N-type doped single crystal silicon). In some embodiments, the semiconductor plug 122 comprises polysilicon (e.g., N-type doped polysilicon) and the remainder of the N-type doped semiconductor layer 120 comprises polysilicon (e.g., N-type doped polysilicon) but with a different doping concentration than that of the semiconductor plug 122.

[0040] Each semiconductor plug 122 may surround and contact a sidewall of a top 127 of a respective semiconductor channel 128. As a result, the semiconductor plugs 122 of the N-type doped semiconductor layer 120 may serve as a "sidewall SEG (e.g., semiconductor plug)" of the channel structure 124 and replace a "bottom SEG (e.g., semiconductor plug)". Furthermore, as described in detail below, the formation of the semiconductor plugs 122 is performed on the opposite side of the memory stack 114, which may avoid any deposition or etching process through an opening through the memory stack 114, thereby reducing the complexity and cost of fabrication and improving yield and vertical scalability. Depending on the relative location of the upper end of the semiconductor channel 128 of each channel structure 124 with respect to the top surface of the N-type doped semiconductor layer 120, the semiconductor plug 122 may be formed above and in contact with the upper end of the semiconductor channel 128 as well when the upper end of the semiconductor channel 128 is below the top surface of the N-type doped semiconductor layer 120, for example, as shown in Figure 1. It will be appreciated that in other examples where the upper end of the semiconductor channel 128 is flush with the top surface of the N-type doped semiconductor layer 120, the semiconductor plug 122 may be formed surrounding and in contact with only the sidewalls of the top 127 of the semiconductor channel 128.

[0041] Nevertheless, the N-type doped semiconductor layer 120 surrounding the top 127 of the semiconductor channel 128 of the channel structure 124 together with the semiconductor plug 122 (e.g., as a sidewall SEG) can enable GIDL-assisted body biasing for an erase operation of the 3D memory device 100. The GIDL around the source select gate of the NAND memory string can generate a hole current in the NAND memory string and raise the body potential for an erase operation.

[0042] As shown in FIG. 1, the second semiconductor structure 104 of the 3D memory device 100 may further include an insulating structure 130 that vertically penetrates the interleaved conductive layers 116 and dielectric layers 118 of the memory stack 114, respectively. Unlike the channel structure 124 that penetrates further into the N-type doped semiconductor layer 120, the insulating structure 130 may stop at the bottom surface of the N-type doped semiconductor layer 120, i.e., not extend vertically into the N-type doped semiconductor layer 120, according to some embodiments. That is, the top surface of the insulating structure 130 may be flush with the bottom surface of the N-type doped semiconductor layer 120. Each insulating structure 130 may also extend laterally to separate the channel structure 124 into multiple blocks. That is, the memory stack 114 may be divided into multiple memory blocks by the insulating structure 130, thereby separating the array of channel structures 124 into each memory block. Unlike the slit structures of existing 3D NAND memory devices described above, which include front-side ACS contacts, the insulating structures 130 do not include contacts therein (i.e., do not function as source contacts) and therefore do not introduce parasitic capacitance and leakage current due to the conductive layers 116 (including wordlines) according to some embodiments. In some embodiments, each insulating structure 130 comprises an opening (e.g., a slit) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 can be filled with silicon oxide.

[0043] Furthermore, as described in more detail below, because the openings for forming the insulating structures 130 are not used (e.g., as sidewall SEGs) for forming the N-type doped semiconductor layers 120 and the semiconductor plugs 122 therein, increasing the aspect ratio of the openings as the number of interleaved conductive layers 116 and dielectric layers 118 increases does not affect the formation of the N-type doped semiconductor layers 120 and the semiconductor plugs 122 therein.

[0044] Instead of a front-side source contact, the 3D memory device 100 may include a back-side source contact 132 above the memory stack 114 and in contact with the N-type doped semiconductor layer 120, as shown in FIG. 1. The source contact 132 and the memory stack 114 (and the insulating structure 130 therethrough) may be disposed on opposite sides of the N-type doped semiconductor layer 120 and may therefore be considered a "back-side" source contact. In some embodiments, the source contact 132 is electrically connected to the semiconductor channel 128 of the channel structure 124 through the semiconductor plug 122 of the N-type doped semiconductor layer 120. In some embodiments, the source contact 132 is not laterally aligned with the insulating structure 130, but is adjacent to the channel structure 124 to reduce the resistance of the electrical connection therebetween. For example, the source contact 132 may be laterally between the insulating structure 130 and the channel structure 124 (e.g., in the x-direction of FIG. 1). The source contact 132 may include any suitable type of contact. In some embodiments, the source contact 132 includes a VIA contact. In some embodiments, the source contact 132 includes a laterally extending wall-shaped contact. The source contact 132 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0045] 1, the 3D memory device 100 may further include a BEOL interconnect layer 133 overlying and electrically connected to the source contacts 132 for pad-out, e.g., for transferring electrical signals between the 3D memory device 100 and an external circuit. In some embodiments, the interconnect layer 133 includes one or more ILD layers 134 over the N-type doped semiconductor layer 120 and a redistribution layer 136 over the ILD layer 134. The upper end of the source contacts 132 is flush with the top surface of the ILD layer 134 and the bottom surface of the redistribution layer 136, according to some embodiments, and the source contacts 132 penetrate vertically through the ILD layer 134 into the N-type doped semiconductor layer 120. The ILD layer 134 in the interconnect layer 133 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layer 136 in the interconnect layer 133 may include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the redistribution layer 136 includes Al. In some embodiments, the interconnect layer 133 further includes a passivation layer 138 as an outermost layer for passivation and protection of the 3D memory device 100. A portion of the redistribution layer 136 may be exposed from the passivation layer 138 as a contact pad 140. That is, the interconnect layer 133 of the 3D memory device 100 may also include contact pads 140 for wire bonding and / or bonding with an interposer.

[0046] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 through the N-type doped semiconductor layer 120. Since the N-type doped semiconductor layer 120 may be a device layer of a thinned substrate, e.g., an SOI wafer, in some embodiments the contacts 142 and 144 are through silicon contacts (TSCs). In some embodiments, the contact 142 penetrates the N-type doped semiconductor layer 120 and the ILD layer 134 to contact the redistribution layer 136, thereby electrically connecting the N-type doped semiconductor layer 120 to the contact 142 through the source contact 132 of the interconnect layer 133 and the redistribution layer 136. In some embodiments, the contact 144 penetrates the N-type doped semiconductor layer 120 and the ILD layer 134 to contact the contact pad 140. The contacts 142 and 144 may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least the contact 144 further includes a spacer (e.g., a dielectric layer) to electrically isolate the contact 144 from the N-type doped semiconductor layer 120.

[0047] In some embodiments, the 3D memory device 100 further comprises peripheral contacts 146 and 148 each extending vertically outside the memory stack 114. Each peripheral contact 146 or 148 can have a depth greater than the depth of the memory stack 114 to extend vertically from the bonding layer 112 to the N-type doped semiconductor layer 120 in a peripheral region outside the memory stack 114. In some embodiments, the peripheral contact 146 is below and in contact with the contact 142 such that the N-type doped semiconductor layer 120 is electrically connected to the peripheral circuitry 108 in the first semiconductor structure 102 through at least the source contact 132, the interconnect layer 133, the contact 142, and the peripheral contact 146. In some embodiments, the peripheral contact 148 is below and in contact with the contact 144 such that the peripheral circuitry 108 in the first semiconductor structure 102 is electrically connected to the pad-out contact pad 140 through at least the contact 144 and the peripheral contact 148. The peripheral contacts 146 and 148 may each include one or more conductive layers, such as a metal layer (eg, W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (eg, TiN).

[0048] As shown in FIG. 1, the 3D memory device 100 also includes various local contacts (also referred to as “C1”) as part of the interconnect structure, which are in direct contact with structures in the memory stack 114. In some embodiments, the local contacts include channel local contacts 150 each below and in contact with a lower end of a respective channel structure 124. Each channel local contact 150 may be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts 152 each below and in contact with a respective conductive layer 116 (including word lines) in the staircase structure of the memory stack 114 for word line fan-out. The local contacts, such as the channel local contacts 150 and the word line local contacts 152, may be electrically connected to the peripheral circuitry 108 of the first semiconductor structure 102 through at least the bonding layers 112 and 110. Local contacts, such as the channel local contact 150 and the word line local contact 152, may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0049] 2 is a side view illustrating a cross section of another exemplary 3D memory device 200 according to some embodiments of the present disclosure. In some embodiments, the 3D memory device 200 is a bonded chip comprising a first semiconductor structure 202 and a second semiconductor structure 204 stacked on the first semiconductor structure 202. The first semiconductor structure 202 and the second semiconductor structure 204 are coupled at a bonded interface 206 therebetween according to some embodiments. As shown in FIG. 2, the first semiconductor structure 202 may include a substrate 201, which may include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0050] The first semiconductor structure 202 of the 3D memory device 200 may include peripheral circuits 208 on the substrate 201. In some embodiments, the peripheral circuits 208 are configured to control and sense the 3D memory device 200. The peripheral circuits 208 may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to facilitate operation of the 3D memory device 200, including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits 208 may include transistors formed "on" the substrate 201, where the transistors are formed in whole or in part in the substrate 201 (e.g., below a top surface of the substrate 201) and / or directly on the substrate 201. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of transistors) may also be formed in substrate 201. The transistors, according to some embodiments, are high speed using advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.). It is understood that in some embodiments, peripheral circuitry 208 may further include any other circuitry compatible with advanced logic processes, including logic circuits such as processors and PLDs, or memory circuits such as SRAMs and DRAMs.

[0051] In some embodiments, the first semiconductor structure 202 of the 3D memory device 200 further includes an interconnect layer (not shown) above the peripheral circuitry 208 for communicating electrical signals to and from the peripheral circuitry 208. The interconnect layer may include a plurality of interconnects (also referred to herein as "contacts") including lateral interconnect lines and VIA contacts. As used herein, the term "interconnect" may be broadly defined to include any suitable type of interconnect, such as MEOL interconnects and BEOL interconnects. The interconnect layer may further include one or more ILD layers (also referred to as "IMD layers") in which the interconnect lines and VIA contacts may be formed. That is, the interconnect layer may include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer may comprise dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0052] As shown in FIG. 2, the first semiconductor structure 202 of the 3D memory device 200 may further include a bonding layer 210 at the bonding interface 206 and above the interconnect layer and peripheral circuitry 208. The bonding layer 210 may include a plurality of bonding contacts 211 and a dielectric that electrically insulates the bonding contacts 211. The bonding contacts 211 may include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. The remaining regions of the bonding layer 210 may be formed by a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 211 and the surrounding dielectric in the bonding layer 210 may be used for hybrid bonding.

[0053] Similarly, as shown in FIG. 2, the second semiconductor structure 204 of the 3D memory device 200 may also include a bonding layer 212 at the bonding interface 206 and above the bonding layer 210 of the first semiconductor structure 202. The bonding layer 212 may include a plurality of bonding contacts 213 and a dielectric that electrically insulates the bonding contacts 213. The bonding contacts 213 may include a conductive material, including but not limited to W, Co, Cu, Al, a silicide, or any combination thereof. The remaining regions of the bonding layer 212 may be formed by a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 213 and the surrounding dielectric in the bonding layer 212 may be used for a hybrid bond. The bonding contacts 213 contact the bonding contacts 211 at the bonding interface 206 according to some embodiments.

[0054] As described in detail below, the second semiconductor structure 204 may be bonded on top of the first semiconductor structure 202 in a face-to-face manner at a bonding interface 206. In some embodiments, the bonding interface 206 is disposed between the bonding layers 210 and 212 as a result of a hybrid bond (also called a "metal / dielectric hybrid bond"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as a solder or adhesive) that can simultaneously obtain a metal-metal bond and a dielectric-dielectric bond. In some embodiments, the bonding interface 206 is where the bonding layers 212 and 210 come into contact and are bonded. In practice, the bonding interface 206 may be a layer having a certain thickness that includes the top surface of the bonding layer 210 of the first semiconductor structure 202 and the bottom surface of the bonding layer 212 of the second semiconductor structure 204.

[0055] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes an interconnect layer (not shown) above the bonding layer 212 to transfer electrical signals. The interconnect layer can include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which interconnect lines and VIA contacts can be formed. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0056] In some embodiments, the 3D memory device 200 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in FIG. 2, the second semiconductor structure 204 of the 3D memory device 200 can include an array of channel structures 224 that function as an array of NAND memory strings. As shown in FIG. 2, each channel structure 224 can vertically penetrate multiple pairs each including a conductive layer 216 and a dielectric layer 218. The interleaved conductive layers 216 and dielectric layers 218 are part of a memory stack 214. The number of pairs of conductive layers 216 and dielectric layers 218 in the memory stack 214 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in the 3D memory device 200. It is understood that in some embodiments, the memory stack 214 can have a multi-deck architecture (not shown) including multiple memory decks stacked on top of each other. The number of pairs of conductive layers 216 and dielectric layers 218 in each memory deck may be the same or different.

[0057] The memory stack 214 may include multiple interleaved conductive layers 216 and dielectric layers 218. The conductive layers 216 and dielectric layers 218 in the memory stack 214 may alternate vertically. In other words, each conductive layer 216, except for the one at the top or bottom of the memory stack 214, may be adjacent to two dielectric layers 218 on either side, and each dielectric layer 218 may be adjacent to two conductive layers 216 on either side. The conductive layers 216 may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 216 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer 216 may extend laterally as a word line and terminate at one or more staircase structures of the memory stack 214. The dielectric layer 218 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0058] As shown in FIG. 2, the second semiconductor structure 204 of the 3D memory device 200 can also include a P-type doped semiconductor layer 220 above the memory stack 114. The P-type doped semiconductor layer 220 can be an example of a "sidewall SEG" as described above. The P-type doped semiconductor layer 220 can include a semiconductor material, such as silicon. In some embodiments, the P-type doped semiconductor layer 220 includes polysilicon formed by deposition techniques, as described in more detail below. In some embodiments, the P-type doped semiconductor layer 220 includes single crystal silicon, such as a device layer of an SOI wafer, as described in more detail below. The P-type doped semiconductor layer 220 is doped with any suitable P-type dopant, such as boron (B), gallium (Ga), or aluminum (Al), such that the intrinsic semiconductor creates a deficiency of valence electrons, called "holes." For example, the P-type doped semiconductor layer 220 can be a polysilicon layer doped with a P-type dopant, such as P, Ar, or Sb. In some embodiments, P-type doped semiconductor layer 220 is a single polysilicon layer with a uniform doping concentration profile in the vertical direction, as opposed to having multiple polysilicon sublayers with non-uniform doping concentrations at their interfaces (e.g., an abrupt doping concentration change at the interface between the two sublayers). It is understood that the doping concentration of the P-type dopant in P-type doped semiconductor layer 220 can still vary gradually in the vertical direction, so long as there is no abrupt doping concentration change that allows two or more sublayers to be distinguished by the change in doping concentration.

[0059] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes an N-well 221 in the P-type doped semiconductor layer 220. The N-well 221 may be doped with any suitable N-type dopant, such as P, Ar, or Sb, which contributes to providing free electrons and enhances the conductivity of the intrinsic semiconductor. In some embodiments, the N-well 221 is doped from the bottom surface of the P-type doped semiconductor layer 220. It is understood that the N-well 221 may extend vertically through the entire thickness of the P-type doped semiconductor layer 220, i.e., to the top surface of the P-type doped semiconductor layer 220 or a portion of the entire thickness of the P-type doped semiconductor layer 220.

[0060] In some embodiments, each channel structure 224 includes a channel hole filled with a semiconductor layer (e.g., as the semiconductor channel 228) and a composite dielectric layer (e.g., as the memory film 226). In some embodiments, the semiconductor channel 228 includes silicon, such as amorphous silicon, polysilicon, or single crystal silicon. In some embodiments, the memory film 226 is a composite layer including a tunnel layer, a storage layer (also referred to as a "charge trapping layer"), and a blocking layer. The remaining space of the channel structure 224 may be partially or completely filled with a capping layer including a dielectric material, such as silicon oxide, and / or voids. The channel structure 224 may have a cylindrical shape (e.g., a pillar shape). The capping layer, the semiconductor channel 228, the tunnel layer, the storage layer, and the blocking layer of the memory film 226 are radially arranged in this order from the center toward the outer surface of the pillar according to some embodiments. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 226 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0061] In some embodiments, the channel structure 224 further includes a channel plug 227 at a bottom (e.g., lower end) of the channel structure 224. As used herein, the "upper end" of a component (e.g., channel structure 224) is the end that is farther from the substrate 201 in the y-direction, and the "lower end" of a component (e.g., channel structure 224) is the end that is closer to the substrate 201 in the y-direction when the substrate 201 is positioned in the bottom-most plane of the 3D memory device 200. The channel plug 227 can include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 227 functions as a drain of a NAND memory string.

[0062] As shown in FIG. 2, each channel structure 224 may penetrate vertically through the alternating conductor layers 216 and dielectric layers 218 of the memory stack 214 into the P-type doped semiconductor layer 220. The upper end of each channel structure 224 may be flush with or below the top surface of the P-type doped semiconductor layer 220. That is, the channel structure 224 does not extend beyond the top surface of the P-type doped semiconductor layer 220 according to some embodiments. In some embodiments, as shown in FIG. 2, the upper end of the memory film 226 is below the upper end of the semiconductor channel 228 of the channel structure 224. In some embodiments, the upper end of the memory film 226 is below the top surface of the P-type doped semiconductor layer 220 and the upper end of the semiconductor channel 228 is flush with or below the top surface of the P-type doped semiconductor layer 220. 2, the memory film 226 may terminate at a bottom surface of the P-type doped semiconductor layer 220 and the semiconductor channel 228 may extend above the bottom surface of the P-type doped semiconductor layer 220 such that the P-type doped semiconductor layer 220 surrounds and contacts a top 229 of the semiconductor channel 228 that penetrates into the P-type doped semiconductor layer 220. In some embodiments, the doping concentration of the top 229 of the semiconductor channel 228 that penetrates into the P-type doped semiconductor layer 220 is different from the doping concentration of the remainder of the semiconductor channel 228. For example, the semiconductor channel 228 may include undoped polysilicon except for the top 229, which may include doped polysilicon to enhance conductivity in forming an electrical connection with the surrounding P-type doped semiconductor layer 220.

[0063] In some embodiments, the P-type doped semiconductor layer 220 includes semiconductor plugs 222 each surrounding and contacting a top 229 of a respective semiconductor channel 228 of a channel structure 224 penetrating into the P-type doped semiconductor layer 220. The semiconductor plugs 222, according to some embodiments, include doped polysilicon, e.g., P-type doped polysilicon. The semiconductor plugs 222 may be formed in a later process after the formation of the remaining portion of the P-type doped semiconductor layer 220, as described in detail below, so that the doping concentration of the semiconductor plugs 222 may differ from the doping concentration of the remaining portion of the P-type doped semiconductor layer 220. In some embodiments, the semiconductor plugs 222 include polysilicon (e.g., P-type doped polysilicon), and the remaining portion of the P-type doped semiconductor layer 220 includes single crystal silicon (e.g., P-type doped single crystal silicon). In some embodiments, the semiconductor plug 222 comprises polysilicon (e.g., P-type doped polysilicon) and the remainder of the P-type doped semiconductor layer 220 comprises polysilicon (e.g., P-type doped polysilicon) but with a different doping concentration than that of the semiconductor plug 222.

[0064] Each semiconductor plug 222 may surround and contact a sidewall of a top 229 of a respective semiconductor channel 228. As a result, the semiconductor plugs 222 of the P-type doped semiconductor layer 220 may serve as a "sidewall SEG (e.g., semiconductor plug)" of the channel structure 224 and replace a "bottom SEG (e.g., semiconductor plug)." Furthermore, as described in detail below, the formation of the semiconductor plugs 222 is performed on the opposite side of the memory stack 214, which may avoid any deposition or etching process through an opening through the memory stack 214, thereby reducing the complexity and cost of fabrication and improving yield and vertical scalability. Depending on the relative location of the upper end of the semiconductor channel 228 of each channel structure 224 with respect to the top surface of the P-type doped semiconductor layer 220, the semiconductor plug 222 may be formed above and in contact with the upper end of the semiconductor channel 228 as well when the upper end of the semiconductor channel 228 is below the top surface of the P-type doped semiconductor layer 220, for example, as shown in Figure 2. It will be appreciated that in other examples where the upper end of the semiconductor channel 228 is flush with the top surface of the P-type doped semiconductor layer 220, the semiconductor plug 222 may be formed surrounding and in contact with only the sidewall of the top 229 of the semiconductor channel 228.

[0065] Nevertheless, the P-type doped semiconductor layer 220 surrounding the top 229 of the semiconductor channel 228 of the channel structure 224 together with the semiconductor plug 222 (e.g., as a sidewall SEG) can enable a P-well bulk erase operation for the 3D memory device 200. The design of the 3D memory device 200 disclosed herein can achieve the separation of hole current paths and electron current paths for forming erase and read operations, respectively. In some embodiments, the 3D memory device 200 is configured to form an electron current path between an electron source (e.g., N-well 221) and the semiconductor channel 228 of the channel structure 224 to supply electrons to the NAND memory string when performing a read operation, according to some embodiments. Conversely, the 3D memory device 200 is configured to form a hole current path between a hole source (e.g., P-type doped semiconductor layer 220) and the semiconductor channel 228 of the channel structure 224 to supply holes to the NAND memory string when performing a P-well bulk erase operation, according to some embodiments.

[0066] As shown in FIG. 2, the second semiconductor structure 204 of the 3D memory device 200 may further include insulating structures 230 that each penetrate vertically through the interleaved conductive layers 216 and dielectric layers 218 of the memory stack 214. Unlike the channel structures 224 that penetrate further into the P-type doped semiconductor layer 220, the insulating structures 230 may stop at the bottom surface of the P-type doped semiconductor layer 220, i.e., not extend vertically into the P-type doped semiconductor layer 220, according to some embodiments. That is, the top surface of the insulating structures 230 may be flush with the bottom surface of the P-type doped semiconductor layer 220. Each insulating structure 230 may also extend laterally to separate the channel structures 224 into multiple blocks. That is, the memory stack 214 may be divided into multiple memory blocks by the insulating structures 230, thereby separating the array of channel structures 224 into each memory block. Unlike the slit structures of existing 3D NAND memory devices described above that include front-side ACS contacts, the insulating structures 230 do not include contacts therein (i.e., do not function as source contacts) and therefore do not introduce parasitic capacitance and leakage current due to the conductive layers 216 (including wordlines) according to some embodiments. In some embodiments, each insulating structure 230 comprises an opening (e.g., a slit) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 230 can be filled with silicon oxide.

[0067] Furthermore, as described in more detail below, because the openings for forming the insulating structures 230 are not used (e.g., as sidewall SEGs) for forming the P-type doped semiconductor layers 220 and semiconductor plugs 222 therein, the increased aspect ratio of the openings as well as the increased number of interleaved conductive layers 216 and dielectric layers 218 do not affect the formation of the P-type doped semiconductor layers 220 and semiconductor plugs 222 therein.

[0068] Instead of a front-side source contact, the 3D memory device 100 may include back-side source contacts 231 and 232 above the memory stack 214 and in contact with the N-well 221 and the P-type doped semiconductor layer 220, as shown in FIG. 1. The source contacts 231 and 232 and the memory stack 214 (and the insulating structure 230 therethrough) may be disposed on opposite sides of the P-type doped semiconductor layer 220 and may therefore be considered "back-side" source contacts. In some embodiments, the source contact 220 in contact with the P-type doped semiconductor layer 220 is electrically connected to the semiconductor channel 228 of the channel structure 224 through the semiconductor plug 222 of the P-type doped semiconductor layer 220. In some embodiments, the source contact 231 in contact with the N-well 221 is electrically connected to the semiconductor channel 228 of the channel structure 224 through the semiconductor plug 222 of the P-type doped semiconductor layer 220. In some embodiments, the source contact 232 is not laterally aligned with the insulating structure 230 but is adjacent to the channel structure 224 to reduce the resistance of the electrical connection therebetween. As shown in FIG. 2, the source contact 231 is laterally aligned with the insulating structure 230, but it is understood that in some examples, the source contact 231 may not be laterally aligned with the insulating structure 230 but may be adjacent to the channel structure 224 (e.g., laterally between the insulating structure 230 and the channel structure 224) to reduce the resistance of the electrical connection therebetween as well. As described above, the source contacts 231 and 232 may be used to separately control the electron current and the hole current, respectively, during read and erase operations. The source contacts 231 and 232 may include any suitable type of contact. In some embodiments, the source contacts 231 and 232 include VIA contacts. In some embodiments, the source contacts 231 and 232 include laterally extending wall-shaped contacts.The source contacts 231 and 232 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0069] As shown in FIG. 2, the 3D memory device 100 can further include a BEOL interconnect layer 233 overlying and electrically connecting the source contacts 231 and 232 for pad-out, e.g., for transferring electrical signals between the 3D memory device 200 and an external circuit. In some embodiments, the interconnect layer 233 includes one or more ILD layers 234 over the P-type doped semiconductor layer 220 and a redistribution layer 236 over the ILD layer 234. The upper ends of the source contacts 231 or 232 are flush with the top surface of the ILD layer 234 and the bottom surface of the redistribution layer 236. The source contacts 231 and 232 can be electrically isolated over the ILD layer 234. In some embodiments, the source contact 232 penetrates vertically through the ILD layer 234 into the P-type doped semiconductor layer 220 and makes an electrical connection with the P-type doped semiconductor layer 220. In some embodiments, the source contact 231 penetrates vertically through the ILD layer 234 and the P-type doped semiconductor layer 220 into the N-well 221 to make an electrical connection to the N-well. The source contact 231 may include a spacer (e.g., a dielectric layer) surrounding its sidewalls such that it is electrically isolated from the P-type doped semiconductor layer 220. The redistribution layer 236 may include two electrically isolated interconnects: a first interconnect 236-1 in contact with the source contact 232 and a second interconnect 236-2 in contact with the source contact 231.

[0070] The ILD layer 234 in the interconnect layer 233 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The redistribution layer 236 in the interconnect layer 233 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the redistribution layer 236 includes Al. In some embodiments, the interconnect layer 233 further includes a passivation layer 238 as an outermost layer for passivation and protection of the 3D memory device 200. A portion of the redistribution layer 236 may be exposed from the passivation layer 238 as a contact pad 240. That is, the interconnect layer 233 of the 3D memory device 200 may also include a contact pad 240 for wire bonding and / or bonding with an interposer.

[0071] In some embodiments, the second semiconductor structure 204 of the 3D memory device 200 further includes contacts 242, 243, and 244 through the P-type doped semiconductor layer 220. Since the P-type doped semiconductor layer 220 may be a device layer of a thinned substrate, e.g., an SOI wafer, the contacts 242, 243, and 244 are TSCs according to some embodiments. In some embodiments, the contact 242 penetrates the P-type doped semiconductor layer 220 and the ILD layer 234 to contact the first interconnect 236-1 of the redistribution layer 236, thereby electrically connecting the P-type doped semiconductor layer 220 to the contact 242 through the source contact 232 and the first interconnect 236-1 of the interconnect layer 233. In some embodiments, the contact 243 penetrates the P-type doped semiconductor layer 220 and the ILD layer 234 to contact the second interconnect 236-2 of the redistribution layer 236, such that the N-well 221 is electrically connected to the contact 243 through the source contact 231 and the second interconnect 236-2 of the interconnect layer 233. In some embodiments, the contact 244 penetrates the P-type doped semiconductor layer 220 and the ILD layer 234 to contact the contact pad 240. The contacts 242, 243, and 244 may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least the contacts 243 and 244 each further include a spacer (e.g., a dielectric layer) to electrically isolate the contacts 243 and 244 from the P-type doped semiconductor layer 220.

[0072] In some embodiments, the 3D memory device 200 further comprises peripheral contacts 246, 247, and 248 each extending vertically outside the memory stack 214. Each peripheral contact 246, 247, or 248 can have a depth greater than a depth of the memory stack 214 such that it extends vertically from the bonding layer 212 to the P-type doped semiconductor layer 220 in a peripheral region outside the memory stack 214. In some embodiments, the peripheral contact 246 is below and in contact with the contact 242 such that the P-type doped semiconductor layer 220 is electrically connected to the peripheral circuitry 208 in the first semiconductor structure 202 through at least the source contact 232, the first interconnect 236-1 of the interconnect layer 233, the contact 242, and the peripheral contact 246. In some embodiments, the peripheral contact 247 is below and in contact with the contact 243, such that the N-well 221 is electrically connected to the peripheral circuitry 208 in the first semiconductor structure 202 through at least the source contact 231, the second interconnect 236-2 of the interconnect layer 233, the contact 243, and the peripheral contact 247. That is, the electron current and the hole current for the read operation and the erase operation can be separately controlled by the peripheral circuitry 208 through different electrical connections. In some embodiments, the peripheral contact 248 is below and in contact with the contact 244, such that the peripheral circuitry 208 in the first semiconductor structure 202 is electrically connected to the pad-out contact pad 240 through at least the contact 244 and the peripheral contact 248. Periphery contacts 246, 247, and 248 may each include one or more conductive layers, such as a metal layer (eg, W, Co, Cu, or Al) or a silicide layer surrounded by an adhesion layer (eg, TiN).

[0073] As shown in FIG. 2, the 3D memory device 200 also includes various local contacts (also referred to as “C1”) as part of the interconnect structure, which are in direct contact with structures in the memory stack 214. In some embodiments, the local contacts include channel local contacts 250 each below and in contact with a lower end of a respective channel structure 224. Each channel local contact 250 may be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts 252 each below and in contact with a respective conductive layer 216 (including word lines) in the staircase structure of the memory stack 214 for word line fan-out. The local contacts, such as the channel local contacts 250 and the word line local contacts 252, may be electrically connected to the peripheral circuitry 208 of the first semiconductor structure 202 through at least the bonding layers 212 and 210. Local contacts, such as the channel local contact 250 and the word line local contact 252, may each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0074] 3A-3N illustrate a fabrication process for forming an exemplary 3D memory device according to some embodiments of the present disclosure. FIG. 5A illustrates a flowchart of a method 500 for forming an exemplary 3D memory device according to some embodiments of the present disclosure. FIG. 5B illustrates a flowchart of another method 501 for forming an exemplary 3D memory device according to some embodiments of the present disclosure. An example of a 3D memory device illustrated in FIGS. 3A-3N, 5A, and 5B includes the 3D memory device 100 illustrated in FIG. 1. FIGS. 3A-3N, 5A, and 5B will be described collectively. It is understood that the operations illustrated in methods 500 and 501 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations as well. Additionally, some of these operations may be performed simultaneously or in a different order than illustrated in FIGS. 5A and 5B.

[0075] Referring to FIG. 5A, the method 500 begins with operation 502 where peripheral circuits are formed on a first substrate. The first substrate may be a silicon substrate. As illustrated in FIG. 3G, a plurality of transistors are formed on the silicon substrate 350 using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed in the silicon substrate 350 by ion implantation and / or thermal diffusion, which function, for example, as source and / or drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 350 by wet and / or dry etching and thin film deposition. The transistors may form a peripheral circuit 352 on the silicon substrate 350.

[0076] 3G, a bonding layer 348 is formed above the peripheral circuitry 352. The bonding layer 348 includes a bonding contact that is electrically connected to the peripheral circuitry 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and a bonding contact through the ILD layer is formed using wet and / or dry etching, e.g., reactive ion etching (RIE), and then formed using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0077] A channel structure vertically penetrating the memory stack and the N-type doped semiconductor layer may be formed above the second substrate. The method 500 proceeds to operation 504, as illustrated in FIG. 5A, where a sacrificial layer on the second substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. The second substrate may be a silicon substrate. It is understood that the second substrate may be a part of a dummy wafer, e.g., a carrier substrate, made of any suitable material, such as glass, sapphire, plastic, silicon, to name a few, to reduce the cost of the second substrate, since it is removed from the final product. In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the N-type doped semiconductor layer includes polysilicon, and the dielectric stack includes alternating stack dielectric layers and stack sacrificial layers. In some embodiments, the stack dielectric layers and stack sacrificial layers are alternately deposited on the N-type doped semiconductor layer to form the dielectric stack.

[0078] As shown in FIG. 3A, a sacrificial layer 304 is formed on a carrier substrate 302, and an N-type doped semiconductor layer 306 is formed on the sacrificial layer 304. The N-type doped semiconductor layer 306 may include polysilicon doped with an N-type dopant, such as P, As, or Sb. The sacrificial layer 304 may include any suitable sacrificial material that may be subsequently selectively removed and that is different from the material of the N-type doped semiconductor layer 306. In some embodiments, the sacrificial layer 304 includes a dielectric material, such as silicon oxide or silicon nitride. To form the sacrificial layer 304, the silicon oxide or silicon nitride is deposited on the carrier substrate 302 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, according to some embodiments. In some embodiments, to form the N-type doped semiconductor layer 306, polysilicon is deposited on the sacrificial layer 304 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, and then the deposited polysilicon is doped with an N-type dopant, such as P, As, or Sb, using ion implantation and / or thermal diffusion. In some embodiments, in-situ doping of an N-type dopant, such as P, As, or Sb, is performed when depositing polysilicon on the sacrificial layer 304 to form the N-type doped semiconductor layer 306.

[0079] As illustrated in FIG. 3B , a dielectric stack 308 including multiple pairs of a first dielectric layer (referred to herein as a “stack sacrificial layer” 312) and a second dielectric layer (referred to herein as a “stack dielectric layer” 310, collectively referred to herein as a “dielectric layer pair”) is formed on the N-type doped semiconductor layer 306. The dielectric stack 308 includes alternating stack sacrificial layers 312 and stack dielectric layers 310 according to some embodiments. The stack dielectric layers 310 and stack sacrificial layers 312 can be alternately deposited on the N-type doped semiconductor layer 306 above the carrier substrate 302 to form the dielectric stack 308. In some embodiments, each stack dielectric layer 310 includes a layer of silicon oxide and each stack sacrificial layer 312 includes a layer of silicon nitride. The dielectric stack 308 can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. As illustrated in FIG. 3B, a staircase structure can be formed at the edge of the dielectric stack 308. The staircase structure can be formed by performing multiple so-called "trim etch" cycles on the dielectric layer pairs of the dielectric stack 308 toward the carrier substrate 302. With repeated trim etch cycles applied to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more slanted edges and a top dielectric layer pair that is shorter than the bottom dielectric layer pair, as shown in FIG. 3B.

[0080] The method 500 proceeds to operation 506, where a channel structure is formed vertically through the dielectric stack and the N-type doped semiconductor layer, as illustrated in Figure 5A. In some embodiments, to form the channel structure, a channel hole is etched vertically through the dielectric stack and the N-type doped semiconductor layer, stopping at the sacrificial layer, and then a memory film and a semiconductor channel are deposited along the sidewalls of the channel hole.

[0081] As illustrated in FIG. 3B, the channel holes are openings that vertically penetrate the dielectric stack 308 and the N-type doped semiconductor layer 306. In some embodiments, multiple openings are formed, each opening being a location for growing an individual channel structure 314 in a later process. In some embodiments, the fabrication process for forming the channel holes of the channel structures 314 includes wet etching and / or dry etching, such as deep recessive ion etching (DRIE). The sacrificial layer 304 can act as an etch stop layer to control the variance in the penetration between different channel holes. For example, the etching of the channel holes can be stopped by the sacrificial layer 304 without penetrating further into the carrier substrate 302. That is, according to some embodiments, the lower end of each channel hole (and corresponding channel structure 314) is between the top and bottom surfaces of the sacrificial layer 304.

[0082] As illustrated in FIG. 3B, a memory film including a blocking layer 317, a storage layer 316, and a tunnel layer 315, and a semiconductor channel 318 are then formed in this order along the sidewall and bottom surface of the channel hole. In some embodiments, the blocking layer 317, the storage layer 316, and the tunnel layer 315 are first deposited in this order along the sidewall and bottom surface of the channel hole using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form a memory film. The semiconductor channel 318 can then be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), on the tunnel layer 315 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are then deposited to form a blocking layer 317, a storage layer 316, and a tunnel layer 315 of the memory membrane and semiconductor channel 318.

[0083] As illustrated in FIG. 3B , a capping layer is formed in the channel hole and over the semiconductor channel 318 to completely or partially fill the channel hole (e.g., without or with voids). The capping layer may be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A channel plug may then be formed at the top of the channel hole. In some embodiments, the memory film, the semiconductor channel 318, and a portion of the capping layer on the top surface of the dielectric stack 308 are removed and planarized by CMP, wet etching, and / or dry etching. A recess may then be formed at the top of the channel hole by wet etching and / or dry etching the portion of the semiconductor channel 318 and the capping layer at the top of the channel hole. A channel plug may then be formed by depositing a semiconductor material, such as polysilicon, in the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Thereby, a channel structure 314 is formed through the dielectric stack 308 and the N-type doped semiconductor layer 306. Depending on the depth at which the etching of each channel hole is stopped by the sacrificial layer 304, the channel structure 314 may penetrate further into the sacrificial layer 304 or may stop at the interface between the sacrificial layer 304 and the N-type doped semiconductor layer 306. Nevertheless, the channel structure 314 may not penetrate further into the carrier substrate 302.

[0084] 5A, the method 500 proceeds to operation 508, where the dielectric stack is replaced with a memory stack, for example, using a so-called "gate replacement" process, whereby a channel structure vertically penetrates the memory stack and the N-type doped semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening is etched vertically through the dielectric stack and stopping at the N-type doped semiconductor layer, and the stack sacrificial layer is replaced with a stack conductor layer through the opening, forming a memory stack including alternating stack dielectric layers and stack conductive layers.

[0085] As illustrated in FIG. 3C, the slit 320 is an opening that passes vertically through the dielectric stack 308 and stops at the N-type doped semiconductor layer 306. In some embodiments, the fabrication process for forming the slit 320 includes wet etching and / or dry etching, such as DRIE. A gate exchange can then be performed through the slit 320 to replace the dielectric stack 308 with a memory stack 330 (shown in FIG. 3E).

[0086] As illustrated in Figure 3D, the outer recesses 322 are formed by first removing the stack sacrificial layers 312 (shown in Figure 3C) through the slits 320. In some embodiments, the stack sacrificial layers 312 are removed by applying an etchant through the slits 320 to form the outer recesses 322 interleaved between the stack dielectric layers 310. The etchant may include any suitable etchant that selectively etches the stack sacrificial layers 312 relative to the stack dielectric layers 310.

[0087] As illustrated in FIG. 3E, a stack conductive layer 328 (including a gate electrode and an adhesive layer) is deposited in the outer recess 322 (shown in FIG. 3D) through the slit 320. In some embodiments, a gate dielectric layer 332 is deposited in the outer recess 322 in front of the stack conductive layer 328, and the stack conductive layer 328 is deposited on the gate dielectric layer 332. The stack conductive layer 328, such as a metal layer, may be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a gate dielectric layer 332, such as a high-k dielectric layer, is formed along the sidewalls and also at the bottom of the slit 320. A memory stack 330 including the interleaved stack conductive layer 328 and stack dielectric layer 310 is thereby formed replacing the dielectric stack 308 (shown in FIG. 3D) according to some embodiments.

[0088] The method 500 proceeds to operation 510, as illustrated in FIG. 5A, where an insulating structure is formed vertically through the memory stack. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited in the openings to fill the openings. As illustrated in FIG. 3E, an insulating structure 336 is formed vertically through the memory stack 330, stopping on the top surface of the N-type doped semiconductor layer 306. The insulating structure 336 can be formed by depositing one or more dielectric materials, such as silicon oxide, into the slits 320 to completely or partially fill the slits 320 (with or without voids) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the insulating structure 336 includes a gate dielectric layer 332 (e.g., including a high-k dielectric) and a dielectric capping layer 334 (e.g., including silicon oxide).

[0089] 3F, after the formation of the insulating structure 336, the local contacts, including the channel local contact 344 and the word line local contact 342, and the peripheral contacts 338 and 340, are formed. The local dielectric layer may be formed on the memory stack 330 by depositing a dielectric material, such as silicon oxide or silicon nitride, on the memory stack 330 using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. The channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340 may be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet etching and / or dry etching, e.g., RIE, and then filling the contact openings with a conductive material using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0090] 3F, a bonding layer 346 is formed over the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. The bonding layer 346 includes a bonding contact that is electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and a bonding contact is formed through the ILD layer using wet etching and / or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0091] The method 500 proceeds to operation 512, as illustrated in FIG. 5A, where the first substrate and the second substrate are bonded face-to-face, with the memory stack above the peripheral circuitry. The bonding can include hybrid bonding. As illustrated in FIG. 3G, the carrier substrate 302 and the components formed thereon (e.g., the memory stack 330 and the channel structure 314 formed therethrough) are flipped upside-down. The downward bonding layer 346 is bonded with the upward bonding layer 348, i.e., bonded face-to-face, thereby forming a bonding interface 354 between the carrier substrate 302 and the silicon substrate 350, according to some embodiments. In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and / or a heat treatment, is applied to the bonding surfaces prior to bonding. After bonding, the bond contacts in bonding layer 346 and the bond contacts in bonding layer 348 may be aligned and contact each other, thereby electrically connecting memory stack 330 and the channel structure 314 formed therethrough to, and above, the peripheral circuitry 352.

[0092] The method 500 proceeds to operation 514, as illustrated in FIG. 5A, where the second substrate and the sacrificial layer are removed to expose the ends of the channel structures. The removal can be performed from the backside of the second substrate. As illustrated in FIG. 3H, the carrier substrate 302 and the sacrificial layer 304 (shown in FIG. 3G) are removed from the backside to expose the upper ends of the channel structures 314. The carrier substrate 302 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some embodiments, the carrier substrate 302 is peeled off. The removal of the carrier substrate 302 can be stopped by the underlying sacrificial layer 304 due to their different materials to ensure thickness uniformity. In some embodiments where the carrier substrate 302 comprises silicon and the sacrificial layer 304 comprises silicon oxide, the carrier substrate 302 can be removed using CMP, automatically stopping at the interface between the carrier substrate 302 and the sacrificial layer 304.

[0093] The sacrificial layer 304 may then be selectively removed using a wet etch with a suitable etchant, such as hydrofluoric acid, without etching the underlying N-type doped semiconductor layer 306. As explained above, the channel structure 314 does not extend beyond the sacrificial layer 304 into the carrier substrate 302, so removal of the carrier substrate 302 does not affect the channel structure 314. Removal of the sacrificial layer 304 may expose the upper end of the channel structure 314. In some embodiments in which the channel structure 314 extends into the sacrificial layer 304, selective etching of the sacrificial layer 304 comprising silicon oxide also removes a portion of the blocking layer 317 comprising silicon oxide above the top surface of the N-type doped semiconductor layer 306, but leaves the storage layer 316 comprising silicon nitride and other layers (e.g., the tunnel layer 315) surrounded by the storage layer 316 intact.

[0094] 5A, the method 500 proceeds to operation 516, where a portion of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug. In some embodiments, to replace a portion of the channel structure abutting the N-type doped semiconductor layer with a semiconductor plug, a portion of the memory film abutting the N-type doped semiconductor layer is removed, thereby forming a recess surrounding a portion of the semiconductor channel, the portion of the semiconductor channel is doped, and polysilicon is deposited within the recess to form a semiconductor plug surrounding and contacting a portion of the doped semiconductor channel.

[0095] As shown in FIG. 3I, a portion of the storage layer 316 (shown in FIG. 3H) abutting the N-type doped semiconductor layer 306 is removed. In some embodiments, the silicon nitride-containing storage layer 316 is selectively removed using a wet etch with a suitable etchant, such as phosphoric acid, without etching the polysilicon-containing N-type doped semiconductor layer 306. The etching of the storage layer 316 can be controlled by controlling the etching time and / or the etching rate, so that the etching does not continue to affect the remaining portions of the storage layer 316 that are surrounded by the memory stack 330.

[0096] 3J, the portions of the blocking layer 317 and the tunnel layer 315 abutting the N-type doped semiconductor layer 306 are removed, thereby forming a recess 357 surrounding the top of the semiconductor channel 318 abutting the N-type doped semiconductor layer 306. In some embodiments, the blocking layer 317 and the tunnel layer 315 comprising silicon oxide are selectively removed using a wet etch with a suitable etchant, such as hydrofluoric acid, without etching the N-type doped semiconductor layer 306 and the semiconductor channel 318 comprising polysilicon. The etching of the blocking layer 317 and the tunnel layer 315 can be controlled by controlling the etching time and / or the etching rate, so that the etching does not continue to affect the remaining portions of the blocking layer 317 and the tunnel layer 315 that are surrounded by the memory stack 330. As a result, according to some embodiments, a top portion of the memory film (including blocking layer 317, storage layer 316, and tunnel layer 315) of channel structure 314 abutting N-type doped semiconductor layer 306 is removed, thereby forming a recess 357 and exposing a top portion of semiconductor channel 318. In some embodiments, the top portion of semiconductor channel 318 exposed by recess 357 is doped to increase its conductivity. For example, an angled ion implantation process may be performed to dope the top portion of semiconductor channel 318 exposed by recess 357 (including, for example, polysilicon) with any suitable dopant to a desired doping concentration.

[0097] As illustrated in FIG. 3K, a semiconductor plug 359 is formed in the recess 357 (shown in FIG. 3J) to surround and contact the doped top of the semiconductor channel 318. As a result, according to some embodiments, the top of the channel structure 314 (shown in FIG. 3H) abutting the N-type doped semiconductor layer 306 is thereby replaced by the semiconductor plug 359. In some embodiments, to form the semiconductor plug 359, polysilicon is deposited in the recess 357 to fill the recess 357 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, followed by a CMP process to remove any excess polysilicon above the top surface of the N-type doped semiconductor layer 306. In some embodiments, to dope the semiconductor plug 359, in-situ doping of an N-type dopant, such as P, As, or Sb, is performed when depositing the polysilicon in the recess 357. Because the semiconductor plug 359 and the N-type doped semiconductor layer 306 may comprise the same material, such as polysilicon, and have the same thickness (after a CMP process), the semiconductor plug 359 may be considered to be part of the N-type doped semiconductor layer 306. Nevertheless, because the semiconductor plug 359 is formed in a process subsequent to the formation of the remainder of the N-type doped semiconductor layer 306 (e.g., as shown in FIG. 3A ), according to some embodiments, the doping concentration of the semiconductor plug 359 is different from the doping concentration of the remainder of the N-type doped semiconductor layer 306, regardless of whether the semiconductor plug 359 is doped in-situ.

[0098] As described above, the semiconductor plug 359 in the N-type doped semiconductor layer 306 can function as a sidewall SEG of the channel structure 314. Unlike the known method of forming the sidewall SEG by an etching and deposition process through the slit 320 (e.g., as shown in FIG. 3D ) that penetrates the dielectric stack 308 from end to end with a high aspect ratio, the semiconductor plug 359 may be formed from the opposite side of the dielectric stack 308 / memory stack 330 after the carrier substrate 302 is removed, which is not affected by the level of the dielectric stack 308 / memory stack 330 and the aspect ratio of the slit 320. By avoiding the problems also introduced by the high aspect ratio of the slit 320, the fabrication complexity and cost can be reduced and the yield can be increased. Moreover, the vertical scalability (e.g., higher levels of the dielectric stack 308 / memory stack 330) can be improved as well.

[0099] The method 500 proceeds to operation 518, as illustrated in FIG. 5A, where a source contact is formed above the memory stack and in contact with the N-type doped semiconductor layer. As illustrated in FIG. 3L, one or more ILD layers 356 are formed on the N-type doped semiconductor layer 306. The ILD layer 356 may be formed by depositing a dielectric material on the top surface of the N-type doped semiconductor layer 306 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A source contact opening 358 may be formed in the N-type doped semiconductor layer 306 through the ILD layer 356. In some embodiments, the source contact opening 358 is formed using a wet etch and / or a dry etch, such as RIE. In some embodiments, the source contact opening 358 penetrates further into the top of the N-type doped semiconductor layer 306. The etching process through the ILD layer 356 may continue to etch a portion of the N-type doped semiconductor layer 306. In some embodiments, a separate etching process is used to etch a portion of the N-type doped semiconductor layer 306 after etching through the ILD layer 356 .

[0100] As illustrated in FIG. 3M, a source contact 364 is formed in a source contact opening 358 (shown in FIG. 3L) on the backside of the N-type doped semiconductor layer 306. The source contact 364 is above the memory stack 330 and in contact with the N-type doped semiconductor layer 306 according to some embodiments. In some embodiments, one or more conductive materials are deposited in the source contact opening 358 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill the source contact opening 358 with an adhesion layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove excess conductive material and make the top surface of the source contact 364 flush with the top surface of the ILD layer 356.

[0101] 5A, the method 500 proceeds to operation 520, where an interconnect layer is formed over and in contact with the source contact. In some embodiments, the contact is formed through the N-type doped semiconductor layer and in contact with the interconnect layer, such that the N-type doped semiconductor layer is electrically connected to the contact through the source contact and the interconnect layer.

[0102] As illustrated in FIG. 3N , the redistribution layer 370 is formed above and in contact with the source contact 364. In some embodiments, the redistribution layer 370 is formed by depositing a conductive material, such as Al, on top of the ILD layer 356 and the source contact 364 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A passivation layer 372 may be formed on the redistribution layer 370. In some embodiments, the passivation layer 372 is formed by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Thereby, an interconnect layer 376 including the ILD layer 356, the redistribution layer 370, and the passivation layer 372 is formed according to some embodiments.

[0103] As illustrated in FIG. 3L, contact openings 360 and 361 are formed through the ILD layer 356 and the N-type doped semiconductor layer 306, respectively. In some embodiments, the contact openings 360 and 361 are formed using a wet etch, such as RIE, and / or a dry etch, through the ILD layer 356 and the N-type doped semiconductor layer 306. In some embodiments, the contact openings 360 and 361 are patterned using lithography to be aligned with the peripheral contacts 338 and 340, respectively. The etching of the contact openings 360 and 361 may stop at the top ends of the peripheral contacts 338 and 340, exposing the peripheral contacts 338 and 340. As illustrated in FIG. 3L, spacers 362 are formed along the sidewalls of the contact openings 360 and 361 to electrically isolate the N-type doped semiconductor layer 306 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, etching of the source contact opening 358 is performed after the formation of the spacers 362, so that the spacers 362 are not formed along the sidewalls of the source contact opening 358, increasing the contact area between the source contact 364 and the N-type doped semiconductor layer 306.

[0104] As illustrated in FIG. 3M, contacts 366 and 368 are formed in contact openings 360 and 361 (shown in FIG. 3L) on the backside of N-type doped semiconductor layer 306, respectively. Contacts 366 and 368 vertically penetrate ILD layer 356 and N-type doped semiconductor layer 306, according to some embodiments. Contacts 366 and 368 and source contact 364 are formed using the same deposition process, which can reduce the number of deposition processes. In some embodiments, one or more conductive materials are deposited in contact openings 360 and 361 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill contact openings 360 and 361 with an adhesive layer (e.g., TiN) and a conductive layer (e.g., W). A planarization process, such as CMP, may then be performed to remove excess conductive material so that the top surfaces of contacts 366 and 368 (and the top surface of source contact 364) are flush with the top surface of ILD layer 356. In some embodiments, contact openings 360 and 361 are aligned with peripheral contacts 338 and 340, respectively, so that contacts 366 and 368 likewise overlie and contact peripheral contacts 338 and 340, respectively.

[0105] 3N , a redistribution layer 370 is also formed above and in contact with the contact 366. As a result, the N-type doped semiconductor layer 306 may be electrically connected to the peripheral contact 338 through the source contact 364, the redistribution layer 370 of the interconnect layer 376, and the contact 366. In some embodiments, the N-type doped semiconductor layer 306 is electrically connected to the peripheral circuit 352 through the source contact 364, the interconnect layer 376, the contact 366, the peripheral contact 338, and the bonding layers 346 and 348.

[0106] 3N , the contact pad 374 is formed above and in contact with the contact 368. In some embodiments, a portion of the passivation layer 372 covering the contact 368 is removed by wet and / or dry etching, thereby exposing a portion of the underlying redistribution layer 370 to form the contact pad 374. As a result, the pad-out contact pad 374 can be electrically connected to the peripheral circuitry 352 through the contact 368, the peripheral contact 340, and the bonding layers 346 and 348.

[0107] It is understood that the second substrate, sacrificial layer, and N-type doped semiconductor layer described above in method 500 may be replaced with an SOI wafer including a handling layer, a buried oxide layer (also referred to as a "BOX" layer), and a device layer, as described below with respect to method 501. Details of similar operations between methods 500 and 501 may not be repeated for ease of explanation. With reference to FIG. 5B, method 501 begins with operation 502, where peripheral circuitry is formed on a first substrate. The first substrate may be a silicon substrate.

[0108] Method 501 proceeds to operation 503, as illustrated in FIG. 5B, where a device layer of an SOI wafer is doped with an N-type dopant. The SOI wafer may include a handling layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide and the device layer includes single crystal silicon. As illustrated in FIG. 3A, SOI wafer 301 includes handling layer 302 (corresponding to carrier substrate 302 described above in describing method 500), buried oxide layer 304 (corresponding to sacrificial layer 304), and device layer 306 (corresponding to N-type doped semiconductor layer 306). Device layer 306 may be doped with an N-type dopant, such as P, As, or Sb, using ion implantation and / or thermal diffusion, resulting in N-type doped device layer 306. It will be understood that the above description relating to the carrier substrate 302, the sacrificial layer 304, and the N-type doped semiconductor layer 306 may equally apply to the handling layer 302, the buried oxide layer 304, and the doped device layer 306 of the SOI wafer 301, respectively, so as to better understand the method 501 below, and therefore will not be repeated for ease of explanation.

[0109] Method 501 proceeds to operation 505, as illustrated in FIG. 5B, where a dielectric stack is formed on the doped device layer of the SOI wafer. The dielectric stack can include alternating stack dielectric layers and stack sacrificial layers. Method 501 proceeds to operation 507, as illustrated in FIG. 5B, where a channel structure is formed vertically through the dielectric stack and the doped device layer. In some embodiments, to form the channel structure, a channel hole is formed vertically through the dielectric stack and the doped device layer, stopping at the buried oxide layer, and then a memory film and a semiconductor channel are deposited along the sidewall of the channel hole. Method 501 proceeds to operation 508, as illustrated in FIG. 5B, where the dielectric stack is replaced with the memory stack, such that the channel structure vertically penetrates the memory stack and the doped device layer. In some embodiments, to replace the dielectric stack with a memory stack, openings are etched vertically through the dielectric stack stopping at the doped device layers, and the stack sacrificial layers are replaced with stack conductor layers through the openings to form a memory stack including alternating stack dielectric layers and stack conductor layers. The method 501 proceeds to operation 510, as illustrated in FIG. 5B, where an insulating structure is formed vertically through the memory stack. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited in the openings to fill the openings.

[0110] The method 501 proceeds to operation 513, as illustrated in FIG. 5B, where the first substrate and the SOI wafer are bonded face-to-face, with the memory stack above the peripheral circuitry. The bonding can include a hybrid bond. The method 501 proceeds to operation 515, as illustrated in FIG. 5B, where the handle layer and the buried oxide layer of the SOI wafer are removed to expose an end of the channel structure. The method 501 proceeds to operation 517, as illustrated in FIG. 5B, where a portion of the channel structure abutting the doped device layer is replaced with a semiconductor plug. In some embodiments, to replace a portion of the channel structure abutting the doped device layer with a semiconductor plug, a portion of the memory film abutting the doped device layer is etched to form a recess surrounding a portion of the semiconductor channel, the portion of the semiconductor channel is doped, and polysilicon is deposited within the recess to form a semiconductor plug surrounding and contacting a portion of the doped semiconductor channel.

[0111] The method 501 proceeds to operation 519, as illustrated in Figure 5B, where a source contact is formed above the memory stack and in contact with the doped device layer. The method 501 proceeds to operation 520, as illustrated in Figure 5B, where an interconnect layer is formed above the source contact and in contact with the source contact. In some embodiments, the contact is formed through the doped device layer and in contact with the interconnect layer, such that the doped device layer is electrically connected to the contact through the source contact and the interconnect layer.

[0112] 4A-4O illustrate a fabrication process for forming another exemplary 3D memory device according to some embodiments of the present disclosure. FIG. 6A illustrates a flowchart of a method 600 for forming another exemplary 3D memory device according to some embodiments of the present disclosure. FIG. 6B illustrates a flowchart of another method 601 for forming another exemplary 3D memory device according to some embodiments of the present disclosure. An example of a 3D memory device illustrated in FIGS. 4A-4O, 6A, and 6B includes the 3D memory device 200 illustrated in FIG. 2. FIGS. 4A-4O, 6A, and 6B will be described collectively. It is understood that the acts illustrated in methods 600 and 601 are not exhaustive, and that other acts may be performed before, after, or between any of the illustrated acts as well. Additionally, some of these acts may be performed simultaneously or in a different order than illustrated in FIGS. 6A and 6B.

[0113] Referring to FIG. 6A, the method 600 begins with operation 602 where peripheral circuits are formed on a first substrate. The first substrate may be a silicon substrate. As illustrated in FIG. 4G, a plurality of transistors are formed on the silicon substrate 450 using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. In some embodiments, doped regions (not shown) are formed in the silicon substrate 450 by ion implantation and / or thermal diffusion, which function, for example, as source and / or drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 450 by wet and / or dry etching and thin film deposition. The transistors may form the peripheral circuits 452 on the silicon substrate 450.

[0114] 4G, a bonding layer 448 is formed above the peripheral circuitry 452. The bonding layer 448 includes a bonding contact that is electrically connected to the peripheral circuitry 452. To form the bonding layer 448, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and a bonding contact is formed through the ILD layer using wet and / or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0115] A channel structure vertically penetrating the memory stack and the P-type doped semiconductor layer with the N-well may be formed above the second substrate. The method 600 proceeds to operation 604, as illustrated in FIG. 6A, where a sacrificial layer on the second substrate, a P-type doped semiconductor layer with an N-well on the sacrificial layer, and a dielectric stack on the P-type doped semiconductor layer are subsequently formed. The second substrate may be a silicon substrate. It is understood that the second substrate may be a part of a dummy wafer, e.g., a carrier substrate, made of any suitable material, such as glass, sapphire, plastic, silicon, to name a few, to reduce the cost of the second substrate, since it is removed from the final product. In some embodiments, the substrate is a carrier substrate, the sacrificial layer includes a dielectric material, the P-type doped semiconductor layer includes polysilicon, and the dielectric stack includes alternating stack dielectric layers and stack sacrificial layers. In some embodiments, the stack dielectric layers and stack sacrificial layers are alternately deposited on the P-type doped semiconductor layer to form the dielectric stack. In some embodiments, prior to forming the dielectric stack, a portion of the P-type doped semiconductor layer is doped with an N-type dopant to form an N-well.

[0116] As illustrated in FIG. 4A, a sacrificial layer 404 is formed on a carrier substrate 402, and a P-type doped semiconductor layer 406 is formed on the sacrificial layer 404. The P-type doped semiconductor layer 406 can include polysilicon doped with a P-type dopant, such as B, Ga, or Al. The sacrificial layer 404 can include any suitable sacrificial material that can be selectively removed later and that is different from the material of the P-type doped semiconductor layer 406. In some embodiments, the sacrificial layer 404 includes a dielectric material, such as silicon oxide or silicon nitride. To form the sacrificial layer 404, the silicon oxide or silicon nitride is deposited on the carrier substrate 402 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, according to some embodiments. In some embodiments, to form the P-type doped semiconductor layer 406, polysilicon is deposited on the sacrificial layer 404 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, and then the deposited polysilicon is doped with a P-type dopant, such as B, Ga, or Al, using ion implantation and / or thermal diffusion. In some embodiments, in-situ doping of a P-type dopant, such as B, Ga, or Al, is performed when depositing the polysilicon on the sacrificial layer 404 to form the P-type doped semiconductor layer 406.

[0117] 4A, a portion of the P-type doped semiconductor layer 406 is doped with an N-type dopant, such as P, As, or Sb, to form an N-well 407 within the P-type doped semiconductor layer 406. In some embodiments, the N-well 407 is formed using ion implantation and / or thermal diffusion. The ion implantation and / or thermal diffusion process can be controlled to control the thickness of the N-well 407 through either the entire thickness of the P-type doped semiconductor layer 406 or a portion thereof.

[0118] As illustrated in FIG. 4B , a dielectric stack 410 including multiple pairs of a first dielectric layer (referred to herein as a “stack sacrificial layer” 412) and a second dielectric layer (referred to herein as a “stack dielectric layer” 410, collectively referred to herein as a “dielectric layer pair”) is formed on the P-type doped semiconductor layer 406. The dielectric stack 408 includes alternating stack sacrificial layers 412 and stack dielectric layers 410 according to some embodiments. The stack dielectric layers 410 and stack sacrificial layers 412 can be alternately deposited on the P-type doped semiconductor layer 406 above the carrier substrate 402 to form the dielectric stack 408. In some embodiments, each stack dielectric layer 410 includes a layer of silicon oxide and each stack sacrificial layer 412 includes a layer of silicon nitride. The dielectric stack 408 can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. As illustrated in FIG. 4B, a staircase structure can be formed at the edge of the dielectric stack 408. The staircase structure can be formed by performing multiple so-called "trim etch" cycles on the dielectric layer pairs of the dielectric stack 408 toward the carrier substrate 402. With repeated trim etch cycles applied to the dielectric layer pairs of the dielectric stack 408, the dielectric stack 408 can have one or more slanted edges and a top dielectric layer pair that is shorter than the bottom dielectric layer pair, as shown in FIG. 4B.

[0119] The method 600 proceeds to operation 606, where a channel structure is formed vertically through the dielectric stack and the P-type doped semiconductor layer, as illustrated in Figure 6A. In some embodiments, to form the channel structure, a channel hole is etched vertically through the dielectric stack and the P-type doped semiconductor layer, stopping at the sacrificial layer, and then a memory film and a semiconductor channel are deposited along the sidewalls of the channel hole.

[0120] As illustrated in FIG. 4B, the channel holes are openings that vertically penetrate the dielectric stack 408 and the P-type doped semiconductor layer 406. In some embodiments, multiple openings are formed, each opening being a location for growing an individual channel structure 414 in a later process. In some embodiments, the fabrication process for forming the channel holes of the channel structures 414 includes wet etching and / or dry etching, such as DRIE. The sacrificial layer 404 can act as an etch stop layer to control the variance in the penetration between different channel holes. For example, the etching of the channel holes can be stopped by the sacrificial layer 404 without penetrating further into the carrier substrate 402. That is, according to some embodiments, the lower end of each channel hole (and corresponding channel structure 414) is between the top and bottom surfaces of the sacrificial layer 404.

[0121] As illustrated in FIG. 4B, a memory film including a blocking layer 417, a storage layer 416, and a tunnel layer 415, and a semiconductor channel 418 are then formed in this order along the sidewall and bottom surface of the channel hole. In some embodiments, the blocking layer 417, the storage layer 416, and the tunnel layer 415 are first deposited in this order along the sidewall and bottom surface of the channel hole using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form a memory film. The semiconductor channel 418 can then be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), on the tunnel layer 415 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are then deposited to form a blocking layer 417, a storage layer 416, and a tunnel layer 415 of the memory membrane and semiconductor channel 418.

[0122] As illustrated in FIG. 4B , a capping layer is formed in the channel hole and over the semiconductor channel 418 to completely or partially fill the channel hole (e.g., without or with voids). The capping layer may be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A channel plug may then be formed at the top of the channel hole. In some embodiments, the memory film, the semiconductor channel 418, and a portion of the capping layer on the top surface of the dielectric stack 408 are removed and planarized by CMP, wet etching, and / or dry etching. A recess may then be formed at the top of the channel hole by wet etching and / or dry etching the portion of the semiconductor channel 418 and the capping layer at the top of the channel hole. A channel plug may then be formed by depositing a semiconductor material, such as polysilicon, in the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Thereby, a channel structure 414 is formed through the dielectric stack 408 and the P-type doped semiconductor layer 406. Depending on the depth at which the etching of each channel hole stops through the sacrificial layer 404, the channel structure 414 may penetrate further into the sacrificial layer 404 or may stop at the interface between the sacrificial layer 404 and the P-type doped semiconductor layer 406. Nevertheless, the channel structure 414 may not penetrate further into the carrier substrate 402.

[0123] 6A, the method 600 proceeds to operation 608, where the dielectric stack is replaced with a memory stack, for example using a so-called "gate replacement" process, whereby a channel structure vertically penetrates the memory stack and the P-type doped semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, an opening is etched vertically through the dielectric stack and stopping at the P-type doped semiconductor layer, and the stack sacrificial layer is replaced with a stack conductor layer through the opening, forming a memory stack including alternating stack dielectric layers and stack conductor layers.

[0124] As illustrated in FIG. 4C, the slit 420 is an opening that penetrates vertically through the dielectric stack 408 and stops at the P-type doped semiconductor layer 406. In some embodiments, the fabrication process for forming the slit 420 includes wet etching and / or dry etching, such as DRIE. The slit 420 is laterally aligned with the N-well 407 as shown in FIG. 4C, although it is understood that in other examples, the slit 420 may not be laterally aligned with the N-well 407. A gate exchange can then be performed through the slit 420 to exchange the dielectric stack 408 with a memory stack 430 (shown in FIG. 4E).

[0125] 4D, the outer recesses 422 are formed by first removing the stack sacrificial layers 412 (shown in FIG. 4C) through the slits 420. In some embodiments, the stack sacrificial layers 412 are removed by applying an etchant through the slits 420 to form the outer recesses 422 interleaved between the stack dielectric layers 410. The etchant can include any suitable etchant that selectively etches the stack sacrificial layers 412 relative to the stack dielectric layers 410.

[0126] As illustrated in FIG. 4E, a stack conductor layer 428 (including a gate electrode and an adhesive layer) is deposited in the outer recess 422 (shown in FIG. 4D) through the slit 420. In some embodiments, a gate dielectric layer 432 is deposited in the outer recess 422 in front of the stack conductor layer 428, and the stack conductor layer 428 is deposited on the gate dielectric layer 432. The stack conductor layer 428, such as a metal layer, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a gate dielectric layer 432, such as a high-k dielectric layer, is formed along the sidewalls and also at the bottom of the slit 420. A memory stack 430 including the interleaved stack conductor layer 428 and stack dielectric layer 410 is thereby formed, according to some embodiments, replacing the dielectric stack 408 (shown in FIG. 4D).

[0127] The method 600 proceeds to operation 610, as illustrated in FIG. 6A, where an insulating structure is formed vertically through the memory stack. In some embodiments, to form the insulating structure, after forming the memory stack, one or more dielectric materials are deposited in the openings to fill the openings. As illustrated in FIG. 4E, an insulating structure 436 is formed vertically through the memory stack 430, stopping on the top surface of the P-type doped semiconductor layer 406. The insulating structure 436 may be formed by depositing one or more dielectric materials, such as silicon oxide, into the slits 420 to completely or partially fill the slits 420 (with or without voids) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the insulating structure 436 includes a gate dielectric layer 432 (e.g., including a high-k dielectric) and a dielectric capping layer 434 (e.g., including silicon oxide).

[0128] 4F, after the formation of the insulating structure 436, the local contacts including the channel local contact 444 and the word line local contact 442, as well as the peripheral contacts 438, 439, and 440 are formed. The local dielectric layer may be formed on the memory stack 430 by depositing a dielectric material, such as silicon oxide or silicon nitride, on the memory stack 430 using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. The channel local contact 444, the word line local contact 442, and the peripheral contacts 438, 439, and 440 may be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet etching and / or dry etching, e.g., RIE, and then filling the contact openings with a conductive material using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0129] 4F, a bonding layer 446 is formed over the channel local contact 444, the word line local contact 442, and the peripheral contacts 438, 439, and 440. The bonding layer 446 includes a bonding contact that is electrically connected to the channel local contact 444, the word line local contact 442, and the peripheral contacts 438, 439, and 440. To form the bonding layer 446, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and a bonding contact is formed through the ILD layer using wet and / or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0130] The method 600 proceeds to operation 612, as illustrated in FIG. 6A, where the first substrate and the second substrate are bonded face-to-face, with the memory stack above the peripheral circuitry. The bonding can include hybrid bonding. As illustrated in FIG. 4G, the carrier substrate 402 and the components formed thereon (e.g., the memory stack 430 and the channel structure 414 formed therein) are flipped upside-down. The downward bonding layer 446 is bonded with the upward bonding layer 448, i.e., bonded face-to-face, thereby forming a bonding interface 454 between the carrier substrate 402 and the silicon substrate 450, according to some embodiments. In some embodiments, a treatment process, such as a plasma treatment, a wet treatment, and / or a heat treatment, is applied to the bonding surfaces prior to bonding. After bonding, the bonding contacts in bonding layer 446 and the bonding contacts in bonding layer 448 may be aligned and contact each other, thereby electrically connecting memory stack 430 and the channel structure 414 formed therethrough to, and above, the peripheral circuitry 452.

[0131] The method 600 proceeds to operation 614, as illustrated in FIG. 6A, where the second substrate and the sacrificial layer are removed to expose the ends of the channel structures. The removal can be performed from the backside of the second substrate. As illustrated in FIG. 4H, the carrier substrate 402 and the sacrificial layer 404 (shown in FIG. 4G) are removed from the backside to expose the upper ends of the channel structures 414. The carrier substrate 402 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some embodiments, the carrier substrate 402 is peeled off. The removal of the carrier substrate 402 can be stopped by the underlying sacrificial layer 404 due to their different materials to ensure thickness uniformity. In some embodiments where the carrier substrate 402 comprises silicon and the sacrificial layer 304 comprises silicon oxide, the carrier substrate 402 can be removed using CMP, automatically stopping at the interface between the carrier substrate 402 and the sacrificial layer 404.

[0132] The sacrificial layer 404 may then be selectively removed using a wet etch with a suitable etchant, such as hydrofluoric acid, without etching the underlying P-type doped semiconductor layer 406. As explained above, the channel structure 414 does not extend beyond the sacrificial layer 404 into the carrier substrate 402, so removal of the carrier substrate 402 does not affect the channel structure 414. Removal of the sacrificial layer 404 may expose the upper end of the channel structure 414. In some embodiments in which the channel structure 414 extends into the sacrificial layer 404, selective etching of the sacrificial layer 404 comprising silicon oxide also removes a portion of the blocking layer 417 comprising silicon oxide above the top surface of the P-type doped semiconductor layer 406, but leaves the storage layer 416 comprising silicon nitride and other layers (e.g., the tunnel layer 415) surrounded by the storage layer 416 intact.

[0133] 6A, the method 600 proceeds to operation 616, where a portion of the channel structure abutting the P-type doped semiconductor layer is replaced with a semiconductor plug. In some embodiments, to replace a portion of the channel structure abutting the P-type doped semiconductor layer with a semiconductor plug, a portion of the memory film abutting the P-type doped semiconductor layer is removed, thereby forming a recess surrounding a portion of the semiconductor channel, the portion of the semiconductor channel is doped, and polysilicon is deposited within the recess to form a semiconductor plug surrounding and contacting a portion of the doped semiconductor channel.

[0134] As illustrated in FIG. 4I, a portion of the storage layer 416 (shown in FIG. 4H) abutting the P-type doped semiconductor layer 406 is removed. In some embodiments, the silicon nitride-containing storage layer 416 is selectively removed using a wet etch with a suitable etchant, such as phosphoric acid, without etching the polysilicon-containing P-type doped semiconductor layer 406. The etching of the storage layer 416 is controlled by controlling the etching time and / or the etching rate, so that the etching does not continue to affect the remaining portions of the storage layer 416 that are surrounded by the memory stack 430.

[0135] 4J, the portions of the blocking layer 417 and the tunnel layer 415 abutting the P-type doped semiconductor layer 406 are removed, thereby forming a recess 457 surrounding the top of the semiconductor channel 418 abutting the P-type doped semiconductor layer 406. In some embodiments, the blocking layer 417 and the tunnel layer 415 comprising silicon oxide are selectively removed using a wet etch with a suitable etchant, such as hydrofluoric acid, without etching the P-type doped semiconductor layer 406 and the semiconductor channel 418 comprising polysilicon. The etching of the blocking layer 417 and the tunnel layer 415 can be controlled by controlling the etching time and / or the etching rate, so that the etching does not continue to affect the remaining portions of the blocking layer 417 and the tunnel layer 415 that are surrounded by the memory stack 430. As a result, according to some embodiments, a top portion of the memory film (including blocking layer 417, storage layer 416, and tunnel layer 415) of channel structure 414 abutting P-type doped semiconductor layer 406 is removed, thereby forming a recess 457 and exposing a top portion of semiconductor channel 418. In some embodiments, the top portion of semiconductor channel 418 exposed by recess 457 is doped to increase its electrical conductivity. For example, an angled ion implantation process may be performed to dope the top portion of semiconductor channel 418 exposed by recess 457 (including, for example, polysilicon) with any suitable dopant to a desired doping concentration.

[0136] As illustrated in FIG. 4K, a semiconductor plug 459 is formed in the recess 457 (shown in FIG. 4J) surrounding and contacting the doped top of the semiconductor channel 418. As a result, according to some embodiments, the top of the channel structure 414 (shown in FIG. 4H) abutting the P-type doped semiconductor layer 406 is thereby replaced by the semiconductor plug 459. In some embodiments, to form the semiconductor plug 459, polysilicon is deposited in the recess 457 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill the recess 457, followed by a CMP process to remove any excess polysilicon above the top surface of the P-type doped semiconductor layer 406. In some embodiments, to dope the semiconductor plug 459, in-situ doping of a P-type dopant, such as B, Ga, or Al, is performed when depositing the polysilicon in the recess 457. Because semiconductor plug 459 and P-type doped semiconductor layer 406 may comprise the same material, such as polysilicon, and have the same thickness (after a CMP process), semiconductor plug 459 may be considered a part of P-type doped semiconductor layer 406. Nevertheless, because semiconductor plug 459 is formed in a process subsequent to the formation of the remainder of P-type doped semiconductor layer 406 (e.g., as shown in FIG. 4A ), according to some embodiments, the doping concentration of semiconductor plug 459 is different from the doping concentration of the remainder of P-type doped semiconductor layer 406, regardless of whether semiconductor plug 459 is doped in-situ.

[0137] As described above, the semiconductor plug 459 in the P-type doped semiconductor layer 406 can function as a sidewall SEG of the channel structure 414. Unlike the known method of forming the sidewall SEG by an etching and deposition process through the slit 420 (e.g., as shown in FIG. 4D ) that penetrates the dielectric stack 408 end-to-end with a high aspect ratio, the semiconductor plug 459 may be formed from the other side of the dielectric stack 408 / memory stack 430 after the carrier substrate 402 is removed, which is not affected by the level of the dielectric stack 408 / memory stack 430 and the aspect ratio of the slit 420. By avoiding the problems also introduced by the high aspect ratio of the slit 420, the fabrication complexity and cost can be reduced and the yield can be increased. Moreover, the vertical scalability (e.g., higher levels of the dielectric stack 408 / memory stack 430) can be improved as well.

[0138] The method 600 proceeds to operation 618, as illustrated in Figure 6A, where a first source contact is formed above the memory stack and contacts the P-type doped semiconductor layer, and a second source contact is formed above the memory stack and contacts the N-well. As illustrated in Figure 4L, one or more ILD layers 456 are formed on the P-type doped semiconductor layer 406. The ILD layer 456 may be formed by depositing a dielectric material on a top surface of the P-type doped semiconductor layer 406 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0139] As illustrated in FIG. 4M , a source contact opening 458 may be formed through the ILD layer 456 and into the P-type doped semiconductor layer 406. In some embodiments, the source contact opening 458 is formed using a wet etch and / or a dry etch, such as RIE. In some embodiments, the source contact opening 458 penetrates further into the top of the P-type doped semiconductor layer 406. The etching process through the ILD layer 456 may continue to etch a portion of the P-type doped semiconductor layer 406. In some embodiments, a separate etching process is used to etch a portion of the P-type doped semiconductor layer 406 after etching through the ILD layer 456.

[0140] As illustrated in FIG. 4M , source contact opening 465 may be formed through ILD layer 456 and into N-well 407. In some embodiments, source contact opening 465 is formed using a wet etch and / or a dry etch, such as RIE. In some embodiments, source contact opening 465 penetrates further into the top of N-well 407. The etch process through ILD layer 456 may continue to etch a portion of N-well 407. In some embodiments, a separate etch process is used to etch a portion of N-well 407 after etching through ILD layer 456. The etch of source contact opening 458 may be performed after the etch of source contact opening 465, or vice versa. In some examples, source contact openings 458 and 465 are etched by the same etch process, which may reduce the number of etch processes.

[0141] As illustrated in FIG. 4N, source contacts 464 and 478 are formed in source contact openings 458 and 465 (shown in FIG. 4M) on the backside of P-type doped semiconductor layer 406, respectively. Source contact 464 is above memory stack 430 and in contact with P-type doped semiconductor layer 406, according to some embodiments. Source contact 478 is above memory stack 430 and in contact with N-well 407, according to some embodiments. In some embodiments, one or more conductive materials are deposited in source contact openings 458 and 465 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill source contact openings 458 and 465 with an adhesion layer (e.g., TiN) and a conductive layer (e.g., W). A planarization process, such as CMP, may then be performed to remove excess conductive material so that the top surfaces of source contacts 464 and 478 are coplanar with each other and with the top surface of ILD layer 456. In some examples, source contacts 464 and 478 are formed by the same deposition and CMP process, which may reduce the number of fabrication processes.

[0142] The method 600 continues at operation 620, where an interconnect layer is formed over and in contact with the first and second source contacts, as illustrated in Figure 6A. In some embodiments, the interconnect layer includes first and second interconnects over and in contact with the first and second source contacts, respectively.

[0143] As illustrated in FIG. 4O, the redistribution layer 470 is formed above and in contact with the source contacts 464 and 478. In some embodiments, the redistribution layer 470 is formed by depositing a conductive material, such as Al, on the top surface of the ILD layer 456 and the source contacts 364 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the redistribution layer 470 is patterned by lithography and etching processes to form a first interconnect 470-1 above and in contact with the source contact 464 and a second interconnect 470-2 above and in contact with the source contact 478. The first and second interconnects 470-1 and 470-2 may be electrically isolated from each other. A passivation layer 472 may be formed on the redistribution layer 470. In some embodiments, the passivation layer 472 is formed by depositing a dielectric material, such as silicon nitride, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, whereby the ILD layer 456, the redistribution layer 470, and the interconnect layer 476, including the passivation layer 472, are formed, according to some embodiments.

[0144] As illustrated in FIG. 4L, contact openings 460, 461, and 463 are formed through ILD layer 456 and P-type doped semiconductor layer 406, respectively. In some embodiments, contact openings 460, 461, and 463 are formed using a wet etch, such as RIE, and / or a dry etch through ILD layer 456 and P-type doped semiconductor layer 406. In some embodiments, contact openings 460, 461, and 463 are patterned using lithography to be aligned with peripheral contacts 438, 440, and 439, respectively. Etching of contact openings 460, 461, and 463 may stop at the top ends of peripheral contacts 438, 439, and 440, exposing peripheral contacts 438, 439, and 440. Etching of contact openings 460, 461, and 463 may be performed by the same etch process, thereby reducing the number of etch steps. It will be understood that due to different etch depths, the etching of contact openings 460, 461, and 463 may be performed before the etching of source contact opening 465, or vice versa, but not at the same time.

[0145] 4M, spacers 462 are formed along the sidewalls of contact openings 460, 461, and 463 as well as source contact opening 465 to electrically isolate P-type doped semiconductor layer 406 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, spacers 462 are formed along the sidewalls of contact openings 460, 461, and 463 as well as source contact opening 465 by the same deposition process, thereby reducing the number of fabrication processes. In some embodiments, etching of source contact opening 458 is performed after formation of spacers 362, such that spacers 362 are not formed along the sidewalls of source contact opening 358, increasing the contact area between source contact 364 and N-type doped semiconductor layer 306.

[0146] As illustrated in FIG. 4N, contacts 466, 468, and 469 are formed in contact openings 460, 461, and 463 (shown in FIG. 4M) on the backside of P-type doped semiconductor layer 406, respectively. Contacts 466, 468, and 469 vertically penetrate ILD layer 456 and P-type doped semiconductor layer 406, according to some embodiments. Contacts 466, 468, and 469 as well as source contacts 464 and 478 are formed using the same deposition process, thereby reducing the number of deposition processes. In some embodiments, one or more conductive materials are deposited in contact openings 460, 461, and 463 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill contact openings 460, 461, and 463 with an adhesive layer (e.g., TiN) and a conductive layer (e.g., W). A planarization process, such as CMP, can then be performed to remove excess conductive material so that the top surfaces of contacts 466, 468, and 469 (and the top surfaces of source contacts 464 and 478) are flush with the top surface of ILD layer 456. In some embodiments, contact openings 460, 461, and 463 are aligned with peripheral contacts 438, 440, and 439, respectively, so that contacts 466, 468, and 469 likewise overlie and contact peripheral contacts 438, 440, and 439, respectively.

[0147] 4O, the first interconnect 470-1 of the redistribution layer 470 is formed above and in contact with the contact 466. As a result, the P-type doped semiconductor layer 406 can be electrically connected to the peripheral contact 438 through the source contact 464, the first interconnect 470-1 of the interconnect layer 476, and the contact 466. In some embodiments, the P-type doped semiconductor layer 406 is electrically connected to the peripheral circuit 452 through the source contact 464, the first interconnect 470-1 of the interconnect layer 476, the contact 466, the peripheral contact 438, and the bonding layers 446 and 448. Similarly, the second interconnect 470-2 of the redistribution layer 470 is formed above and in contact with the contact 469. As a result, the N-well 407 may be electrically connected to the peripheral contact 438 through the source contact 478, the second interconnect 470-2 of the interconnect layer 476, and the contact 469. In some embodiments, the N-well 407 is electrically connected to the peripheral circuitry 452 through the source contact 478, the second interconnect 470-2 of the interconnect layer 476, the contact 469, the peripheral contact 439, and the bonding layers 446 and 448.

[0148] 4O, the contact pad 474 is formed above and in contact with the contact 468. In some embodiments, a portion of the passivation layer 472 covering the contact 468 is removed by wet and / or dry etching, thereby exposing a portion of the underlying redistribution layer 470 to form the contact pad 474. As a result, the pad-out contact pad 474 can be electrically connected to the peripheral circuitry 452 through the contact 468, the peripheral contact 440, and the bonding layers 446 and 448.

[0149] It is understood that the second substrate, sacrificial layer, and P-type doped semiconductor layer described above in method 600 may be replaced with an SOI wafer including a handling layer, a buried oxide layer (also referred to as a "BOX" layer), and a device layer, as described below with respect to method 601. Details of similar operations between methods 600 and 601 may not be repeated for ease of explanation. With reference to FIG. 6B, method 601 begins with operation 602 where peripheral circuitry is formed on a first substrate. The first substrate may be a silicon substrate.

[0150] The method 601 proceeds to operation 603, as illustrated in FIG. 6B, where a device layer of the SOI wafer is doped with a P-type dopant. The SOI wafer may include a handling layer, a buried oxide layer, and a device layer. In some embodiments, the buried oxide layer includes silicon oxide and the device layer includes single crystal silicon. The method 601 proceeds to operation 605, as illustrated in FIG. 6B, where a portion of the doped device layer is doped with an N-type dopant to form an N-well in the doped device layer.

[0151] 4A, SOI wafer 401 includes a handling layer 402 (corresponding to carrier substrate 402 described above in describing method 600), a buried oxide layer 404 (corresponding to sacrificial layer 404), and a device layer 406 (corresponding to P-type doped semiconductor layer 406). Device layer 406 may be doped with a P-type dopant, such as P, As, or Sb, using ion implantation and / or thermal diffusion, thereby becoming a P-type doped device layer 406. A portion of doped device layer 406 may be further doped with an N-type dopant, such as B, Ga, or Al, using ion implantation and / or thermal diffusion, thereby forming an N-well 407. It will be understood that the above description relating to the carrier substrate 402, the sacrificial layer 404, and the P-type doped semiconductor layer 406 may equally apply to the handling layer 402, the buried oxide layer 404, and the doped device layer 406 of the SOI wafer 401, respectively, so as to better understand the method 601 below, and therefore will not be repeated for ease of explanation.

[0152] Method 601 proceeds to operation 607, as illustrated in FIG. 6B, where a dielectric stack is formed on the doped device layer of the SOI wafer. The dielectric stack can include alternating stack dielectric layers and stack sacrificial layers. Method 601 proceeds to operation 609, as illustrated in FIG. 6B, where a channel structure is formed vertically through the dielectric stack and the doped device layer. In some embodiments, to form the channel structure, a channel hole is formed vertically through the dielectric stack and the doped device layer, stopping at the buried oxide layer, and then a memory film and a semiconductor channel are deposited along the sidewall of the channel hole. Method 601 proceeds to operation 608, as illustrated in FIG. 6B, where the dielectric stack is replaced with the memory stack, such that the channel structure vertically penetrates the memory stack and the doped device layer. In some embodiments, to replace the dielectric stack with a memory stack, openings are etched vertically through the dielectric stack stopping at the doped device layers, and the stack sacrificial layers are replaced with stack conductor layers through the openings to form a memory stack including alternating stack dielectric layers and stack conductor layers. The method 601 proceeds to operation 610, as illustrated in FIG. 6B, where an insulating structure method is formed vertically through the memory stack. In some embodiments, after forming the memory stack to form an insulating structure, one or more dielectric materials are deposited in the openings to fill the openings.

[0153] The method 601 proceeds to operation 613, as illustrated in FIG. 6B, where the first substrate and the SOI wafer are bonded face-to-face, with the memory stack above the peripheral circuitry. The bonding can include a hybrid bond. The method 601 proceeds to operation 615, as illustrated in FIG. 6B, where the handle layer and the buried oxide layer of the SOI wafer are removed to expose an end of the channel structure. The method 601 proceeds to operation 617, as illustrated in FIG. 6B, where a portion of the channel structure abutting the doped device layer is replaced with a semiconductor plug. In some embodiments, to replace a portion of the channel structure abutting the doped device layer with a semiconductor plug, a portion of the memory film abutting the doped device layer is etched to form a recess surrounding a portion of the semiconductor channel, the portion of the semiconductor channel is doped, and polysilicon is deposited within the recess to form a semiconductor plug surrounding and contacting a portion of the doped semiconductor channel.

[0154] The method 601 proceeds to operation 619, as illustrated in FIG. 6B, where a first source contact is formed above the memory stack and in contact with the doped device layer, and a second source contact is formed above the memory stack and in contact with the N-well. The method 601 proceeds to operation 621, as illustrated in FIG. 6B, where an interconnect layer is formed above and in contact with the first and second source contacts. In some embodiments, the interconnect layer includes a first interconnect above and in contact with the first source contact and a second interconnect above and in contact with the second source contact. In some embodiments, the first contact is formed through the doped device layer and in contact with the first interconnect layer, such that the doped device layer is electrically connected to the first contact through the first source contact and the first interconnect layer. In some embodiments, a second contact is formed through the doped device layer and contacts the second interconnect layer, such that the doped device layer is electrically connected to the second contact through the second source contact and the second interconnect layer.

[0155] According to one aspect of the disclosure, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including alternating conductive and dielectric layers on the peripheral circuit, an N-type doped semiconductor layer on the memory stack, a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer, and a source contact on the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.

[0156] In some embodiments, the N-type doped semiconductor layer comprises polysilicon.

[0157] In some embodiments, the N-type doped semiconductor layer comprises single crystal silicon.

[0158] In some embodiments, each of the channel structures includes a memory film and a semiconducting channel, with an upper edge of the memory film below an upper edge of the semiconducting channel.

[0159] In some embodiments, an upper end of the memory film is below a top surface of the N-type doped semiconductor layer and an upper end of the semiconductor channel is flush with or below the top surface of the N-type doped semiconductor layer.

[0160] In some embodiments, the portion of the semiconductor channel that penetrates into the N-type doped semiconductor layer comprises doped polysilicon.

[0161] In some embodiments, the N-type doped semiconductor layer includes a semiconductor plug surrounding and in contact with a portion of the semiconductor channel, the doping concentration of the semiconductor plug being different from the doping concentration of the remainder of the N-type doped semiconductor layer.

[0162] In some embodiments, the 3D memory device further includes an interconnect layer above and electrically connected to the source contacts.

[0163] In some embodiments, the 3D memory device further includes a first contact through the N-type doped semiconductor layer. According to some embodiments, the N-type doped semiconductor layer is electrically connected to peripheral circuitry through at least the source contact, the interconnect layer, and the first contact.

[0164] In some embodiments, the 3D memory device further includes a second contact through the N-type doped semiconductor layer. The interconnect layer includes a contact pad electrically connected to the second contact, according to some embodiments.

[0165] In some embodiments, the 3D memory device further includes an insulating structure that extends vertically through the memory stack and laterally to separate the multiple channel structures into multiple blocks.

[0166] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0167] In some embodiments, the top surface of the insulating structure is coplanar with the bottom surface of the N-type doped semiconductor layer.

[0168] In some embodiments, the 3D memory device further comprises a bonding interface between the peripheral circuitry and the memory stack.

[0169] According to another aspect of the disclosure, a 3D memory device includes a substrate, a memory stack including alternating conductive and dielectric layers over the substrate, an N-type doped semiconductor layer over the memory stack, and a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer. Each of the plurality of channel structures includes a memory film and a semiconductor channel. An upper end of the memory film is below an upper end of the semiconductor channel. The N-type doped semiconductor layer includes a semiconductor plug surrounding and contacting a portion of the semiconductor channel. The doping concentration of the semiconductor plug is different from the doping concentration of the remainder of the N-type doped semiconductor layer.

[0170] In some embodiments, the semiconductor plug comprises polysilicon and the remainder of the N-type doped semiconductor layer comprises polysilicon.

[0171] In some embodiments, the semiconductor plug comprises polysilicon and the remainder of the N-type doped semiconductor layer comprises single crystal silicon.

[0172] In some embodiments, the 3D memory device further includes an insulating structure that extends vertically through the memory stack and laterally to separate the multiple channel structures into multiple blocks.

[0173] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0174] In some embodiments, the top surface of the insulating structure is coplanar with the bottom surface of the N-type doped semiconductor layer.

[0175] In some embodiments, the 3D memory device further includes a source contact above the memory stack and in contact with the N-type doped semiconductor layer.

[0176] In some embodiments, the 3D memory device further includes peripheral circuitry above the substrate and a bonding interface between the peripheral circuitry and the memory stack.

[0177] In some embodiments, the 3D memory device further includes an interconnect layer above and electrically connected to the source contacts.

[0178] In some embodiments, the N-type doped semiconductor layer is electrically connected to peripheral circuitry through at least the source contact and the interconnect layer.

[0179] According to yet another aspect of the present disclosure, a 3D memory device includes a first semiconductor structure, a second semiconductor structure, and a junction interface between the first and second semiconductor structures. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a memory stack including alternating conductive and dielectric layers, an N-type doped semiconductor layer, and a plurality of channel structures each penetrating vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuit. The N-type doped semiconductor layer includes a semiconductor plug surrounding a portion of each of the plurality of channel structures penetrating into the N-type doped semiconductor layer. The doping concentration of the semiconductor plug is different from the doping concentration of the remaining portion of the N-type doped semiconductor layer.

[0180] In some embodiments, the second semiconductor structure further includes an insulating structure that extends vertically through the memory stack and laterally to separate the plurality of channel structures into a plurality of blocks.

[0181] In some embodiments, the insulating structure is filled with one or more dielectric materials.

[0182] In some embodiments, the insulating structures do not penetrate vertically into the N-type doped semiconductor layer.

[0183] In some embodiments, the second semiconductor structure further includes a source contact in contact with the N-type doped semiconductor layer.

[0184] In some embodiments, the second semiconductor structure further includes an interconnect layer, and each of the channel structures does not extend beyond the N-type doped semiconductor layer.

[0185] In some embodiments, the semiconductor plug comprises polysilicon and the remainder of the N-type doped semiconductor layer comprises polysilicon.

[0186] In some embodiments, the semiconductor plug comprises polysilicon and the remainder of the N-type doped semiconductor layer comprises single crystal silicon.

[0187] The foregoing description of specific embodiments will clarify the general nature of the disclosure so that those skilled in the art can easily modify and / or adapt such specific embodiments to various applications without departing from the general concept of the disclosure and without undue experimentation by applying knowledge within the art. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It will be understood that the phrases or terms used herein are for the purpose of explanation, and thus should be interpreted by those skilled in the art in light of the teaching and guidance.

[0188] The embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating implementation forms of specified functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the specified functions and their relationships are appropriately performed.

[0189] The Summary and Abstract sections may define one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and thus are not intended to limit the disclosure and the appended claims in any way.

[0190] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0191] 100 3D Memory Devices 101 Substrate 102 First semiconductor structure 104 Second Semiconductor Structure 106 Joint interface 108 Peripheral Circuits 110 Bonding layer 111 Bonding Contact 112 Bonding layer 113 Bonding Contact 114 Memory Stack 116 Conductive Layer 118 Dielectric Layer 120 N-type doped semiconductor layer 122 Semiconductor plug 124 channel structure 126 Memory Film 127 Top 128 Semiconductor Channels 129 Channel Plug 130 Insulation structure 132 Backside Source Contact 133 BEOL Interconnect Layers 134 ILD layer 136 Redistribution layer 138 Passivation Layer 140 Contact Pad 142, 144 Contact 146, 148 Peripheral Contacts 150 Channel Local Contacts 152 Word Line Local Contact 200 3D memory devices 201 Substrate 202 First Semiconductor Structure 204 Second Semiconductor Structure 206 Joint interface 208 Peripheral Circuits 210 Bonding layer 211 Bonding Contact 212 Bonding layer 213 Bonding Contact 216 Conductive Layer 218 Dielectric Layer 220 P-type doped semiconductor layer 221 N-well 222 Semiconductor plug 224 Channel Structure 226 Memory Film 227 Channel Plug 228 Semiconductor Channels 229 Top 230 Insulation Structure 231, 232 Backside source contact 233 BEOL Interconnect Layers 234 ILD layer 236 Redistribution layer 236-1 First Interconnection 236-2 Second Interconnection 238 Passivation Layer 240 Contact Pad 242, 243, 244 Contact 246, 247, 248 Peripheral Contacts 250 Channel Local Contacts 252 word line local contact 302 Carrier Board 304 Sacrificial Layer 306 N-type doped semiconductor layer 308 Dielectric Stack 310 stack dielectric layers 312 stack sacrificial layer 314 Channel Structure 315 Tunnel Layer 316 Storage Tier 317 Blocking Layer 318 Semiconductor Channel 320 Slit 322 Outer recess 328 stacked conductive layers 330 Memory Stack 332 Gate dielectric layer 334 Dielectric Capping Layer 336 Insulation Structure 338, 340 Peripheral Contact 342 Word Line Local Contact 344 Channel Local Contacts 346 Bonding layer 348 Bonding layer 350 Silicon substrate 352 Peripheral Circuits 354 Joint interface 356 ILD layer 357 Depression 358 Source Contact Opening 359 Semiconductor plug 360, 361 Contact opening 362 Spacer 364 Source Contacts 366, 368 Contact 370 Redistribution layer 372 Passivation Layer 374 Contact Pad 376 Interconnection Layer 402 Carrier Board 404 Sacrificial Layer 406 P-type doped semiconductor layer 407 N-well 408 Dielectric Stack 410 stack dielectric layers 412 stack sacrificial layer 414 Channel Structure 415 Tunnel Layer 416 Storage Tier 417 Blocking Layer 418 Semiconductor Channel 420 Slit 422 Outer recess 428 stacked conductive layers 430 Memory Stack 432 Gate Dielectric Layer 434 Dielectric Capping Layer 436 Insulation Structure 438, 439, 440 Peripheral Contacts 442 Word Line Local Contact 444 Channel Local Contact 446 Bonding layer 448 Bonding layer 450 Silicon substrate 452 Peripheral Circuit 454 Joint interface 456 ILD layer 457 Depression 458 Source Contact Opening 459 Semiconductor plug 460, 461, and 463 Contact Openings 464 and 478 Source Contact 465 Source Contact Opening 466, 468, and 469 Contacts 470 Redistribution layer 470-1 First Interconnection 470-2 Second Interconnection 472 Passivation Layer 474 Contact Pad 476 Interconnection Layer

Claims

1. 1. A three-dimensional (3D) memory device, comprising: a memory stack including alternating conductive and dielectric layers; a semiconductor layer above the memory stack; a plurality of channel structures each penetrating vertically through the memory stack and into the semiconductor layer, each channel structure including a semiconductor channel, the semiconductor layer surrounding the semiconductor channel, the semiconductor channel penetrating into a portion of the semiconductor layer and contacting the semiconductor layer; a source contact above the memory stack and in contact with the semiconductor layer.

2. 2. The 3D memory device of claim 1, wherein the semiconductor layer comprises an N-type doped semiconductor layer or a P-type doped semiconductor layer.

3. 3. The 3D memory device of claim 2, further comprising a source contact above the memory stack, the source contact and the memory stack being disposed on opposite sides of the N-type doped semiconductor layer.

4. 3. The 3D memory device of claim 2, further comprising two source contacts, both of the two source contacts being above the memory stack, each of the two source contacts and the memory stack being disposed on opposite sides of the P-type doped semiconductor layer, and one of the two source contacts contacting an N-well in the P-type doped semiconductor layer.

5. 5. The 3D memory device of claim 4, wherein the other of the two source contacts contacts the P-type doped semiconductor layer.

6. 3. The 3D memory device of claim 2, wherein the N-type doped semiconductor layer comprises polysilicon.

7. 3. The 3D memory device of claim 2, wherein the N-type doped semiconductor layer comprises single crystal silicon.

8. 8. The 3D memory device of claim 1, wherein each of the channel structures further comprises a memory film, an upper end of the memory film being below an upper end of the semiconductor channel.

9. 9. The 3D memory device of claim 8, wherein the upper end of the memory film is below a top surface of the semiconductor layer and the upper end of the semiconductor channel is flush with or below the top surface of the semiconductor layer.

10. 10. The 3D memory device of claim 1, wherein the portion of the semiconductor channel that penetrates into the semiconductor layer comprises doped polysilicon.

11. 11. The 3D memory device of claim 10, wherein the semiconductor layer includes a semiconductor plug surrounding and contacting a portion of the semiconductor channel, the semiconductor plug having a doping concentration different from a doping concentration of a remainder of the semiconductor layer.

12. 10. The 3D memory device of claim 1, further comprising an interconnect layer above and electrically connected to said source contacts.

13. Further including peripheral circuitry; 13. The 3D memory device of claim 12, further comprising a first contact through the semiconductor layer, the semiconductor layer being electrically connected to the peripheral circuitry through at least the source contact, the interconnect layer, and the first contact.

14. 13. The 3D memory device of claim 12, further comprising a second contact through the semiconductor layer, the interconnect layer including a contact pad electrically connected to the second contact.

15. 10. The 3D memory device of claim 1, further comprising an insulating structure that extends vertically through the memory stack and laterally to separate the plurality of channel structures into a plurality of blocks.

16. 16. The 3D memory device of claim 15, wherein the insulating structures are filled with one or more dielectric materials.

17. 17. The 3D memory device of claim 15 or 16, wherein a top surface of the insulating structure is coplanar with a bottom surface of the semiconductor layer.

18. 18. The 3D memory device of claim 15, wherein the source contact is located on the insulating structure.

19. 19. The 3D memory device of claim 15, wherein projections of the source contact and the insulating structure at least partially overlap.

20. 14. The 3D memory device of claim 13, further comprising a bonding interface between the peripheral circuitry and the memory stack.

21. 10. The 3D memory device of claim 1, wherein the semiconductor layer is an N-type doped semiconductor layer, the N-type doped semiconductor layer configured to supply holes for gate induced drain leakage (GIDL) erase.

22. 1. A three-dimensional (3D) memory device, comprising: Peripheral circuitry; a memory stack including alternating conductive and dielectric layers above the peripheral circuitry; a semiconductor layer above the memory stack; a plurality of channel structures each penetrating vertically through the memory stack and into the semiconductor layer, each channel structure including a semiconductor channel, the semiconductor layer surrounding the semiconductor channel, the semiconductor channel penetrating into a portion of the semiconductor layer and contacting the semiconductor layer; a source contact above the memory stack and in contact with the semiconductor layer; a laterally extending isolation structure that vertically penetrates the memory stack and separates the plurality of channel structures into a plurality of blocks; the peripheral circuit is connected to the memory stack by bonding; A three dimensional (3D) memory device, wherein the source contact is located above the insulating structure.

23. 23. The 3D memory device of claim 22, wherein projections of the source contact and the insulating structure at least partially overlap.

24. 23. The 3D memory device of claim 22, wherein the semiconductor layer comprises an N-type doped semiconductor layer or a P-type doped semiconductor layer.

25. 25. The 3D memory device of claim 24, further comprising two source contacts, both of the two source contacts being above the memory stack, each of the two source contacts and the memory stack being disposed on opposite sides of the P-type doped semiconductor layer, and one of the two source contacts contacting an N-well in the P-type doped semiconductor layer.

26. 26. The 3D memory device of claim 25, wherein the other of the two source contacts contacts the P-type doped semiconductor layer.

27. 23. The 3D memory device of claim 22, wherein the semiconductor layer is an N-type doped semiconductor layer, the N-type doped semiconductor layer configured to provide holes for gate induced drain leakage (GIDL) erase.

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