Thin film transistor and display device including same

Abstract

To provide a thin film transistor in which the conduction penetration depth can be controlled.SOLUTION: In one example, a thin film transistor includes an active layer, and a gate electrode at least partially overlapping with the active layer apart from the active layer. The active layer includes a channel region overlapping with the gate electrode in a plan view, a source region not overlapping with the gate electrode in a plan view and coupled to one side of the channel region, and a drain region not overlapping with the gate electrode in a plan view and coupled to the other side of the channel region. The source region and the drain region are apart from each other with the channel region held therebetween. The active layer includes a first source conduction adjustment region and a first drain conduction adjustment region that are apart from each other. At least a part of the first source conduction adjustment region overlaps with at least a part of the gate electrode. At least a part of the first drain conduction adjustment region overlaps with at least a part of the gate electrode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present specification relates to a transistor and a display device including the transistor. [Background technology]

[0002] Transistors are widely used as switching devices and driving devices in the field of electronic devices. In particular, thin film transistors can be manufactured on glass or plastic substrates, and are therefore widely used as switching devices in display devices such as liquid crystal display devices and organic light emitting devices.

[0003] Based on the material constituting the active layer, thin film transistors can be divided into amorphous silicon thin film transistors in which amorphous silicon is used as an active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as an active layer, and oxide semiconductor thin film transistors in which an oxide semiconductor is used as an active layer.

[0004] Amorphous silicon thin film transistors (a-Si TFTs) have the advantage of being able to form an active layer by depositing amorphous silicon in a short time, resulting in a short manufacturing process time and low production costs. However, they have the disadvantage of being limited in use in active matrix organic light emitting diodes (AMOLEDs) due to their low mobility, poor current driving capability, and threshold voltage changes.

[0005] Polycrystalline silicon thin film transistors (poly-Si TFTs) are made by depositing amorphous silicon and then crystallizing the amorphous silicon. The manufacturing process of polycrystalline silicon thin film transistors requires a process to crystallize the amorphous silicon, which increases the number of processes and increases manufacturing costs, and the crystallization process is performed at a high process temperature, making it difficult to apply polycrystalline silicon thin film transistors to large area devices. In addition, due to the polycrystalline characteristics, it is difficult to ensure the uniformity of polycrystalline silicon thin film transistors.

[0006] In oxide semiconductor thin film transistors (TFTs), the oxide constituting the active layer can be formed at a relatively low temperature, and the film has high mobility and a large change in resistance depending on the oxygen content, so that the desired physical properties can be easily obtained. In addition, because of the characteristics of oxides, oxide semiconductors are transparent, so they are also advantageous for realizing transparent displays.

[0007] In the case of an oxide semiconductor thin film transistor, selective conductorization of the oxide semiconductor layer may be required, and in this case, control of the conductorized region formed in the oxide semiconductor layer and the conductorized penetration depth is very important. Therefore, techniques for controlling the conductorized region and the conductorized penetration depth are being studied. Summary of the Invention [Problem to be solved by the invention]

[0008] One embodiment of the present invention provides a thin film transistor in which the active layer contains a pattern and the conductor penetration depth can be controlled even when the channel region has a large width.

[0009] One embodiment of the present invention provides a thin film transistor in which the active layer includes a pattern and the channel region has a large width, preventing or suppressing a negative (-) shift in threshold voltage (Vth).

[0010] One embodiment of the present invention provides a thin film transistor in which the active layer includes a pattern, resulting in improved reliability.

[0011] Another embodiment of the present invention provides a display device including a transistor as described above. [Means for solving the problem]

[0012] In order to achieve the above-mentioned technical object, one embodiment of the present invention provides a thin film transistor including: an active layer; and a gate electrode spaced from the active layer and at least partially overlapping the active layer, the active layer including a channel region overlapping with the gate electrode in a planar view; a source region not overlapping with the gate electrode in a planar view and connected to one side of the channel region; and a drain region not overlapping with the gate electrode in a planar view and connected to the other side of the channel region, the source region and the drain region being spaced apart from each other with the channel region interposed therebetween; the active layer including a first source conductor adjustment region and a first drain conductor adjustment region spaced apart from each other, at least a portion of the first source conductor adjustment region overlapping with at least a portion of the gate electrode, and at least a portion of the first drain conductor adjustment region overlapping with at least a portion of the gate electrode. Effect of the Invention

[0013] A thin film transistor according to an embodiment of the present invention has an active layer that includes a pattern, allowing the conductor penetration depth to be controlled even when the channel region has a large width.

[0014] In a thin film transistor according to an embodiment of the present invention, even if an active layer includes a pattern and a channel region has a large width, the threshold voltage (Vth) can be controlled to shift in the negative (-) direction.

[0015] According to an embodiment of the present invention, the thin film transistor may have stability and excellent reliability since the active layer includes a pattern.

[0016] In addition to the above-mentioned effects, other features and advantages of the present invention will be described below or will become apparent to those having ordinary skill in the art to which the present invention pertains from such techniques and descriptions. [Brief description of the drawings]

[0017] [Figure 1] FIG. 2 is a plan view of a thin film transistor according to an embodiment of the present invention. [Figure 2A] 2 is a cross-sectional view taken along II' in FIG. 1. [Figure 2B] FIG. 2 is a cross-sectional view taken along line II-II' in FIG. [Diagram 3] 4 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention. [Figure 4A] 3A and 3B are a plan view and a cross-sectional view taken along line III-III' of the plan view of a thin film transistor according to still another embodiment of the present invention; [Figure 4B] 3A and 3B are a plan view and a cross-sectional view taken along line III-III' of the plan view of a thin film transistor according to still another embodiment of the present invention; [Diagram 5] 4A and 4B are a plan view and a cross-sectional view taken along line IV-IV' of the plan view of a thin film transistor according to still another embodiment of the present invention; [Figure 6] 11A and 11B are a plan view and a cross-sectional view taken along line V-V' of the plan view of a thin film transistor according to still another embodiment of the present invention; [Figure 7] 4 is a cross-sectional view of a thin film transistor according to still another embodiment of the present invention. [Figure 8] FIG. 4 is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 9] FIG. 4 is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 10] FIG. 4 is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 11A] FIG. 4 is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 11B]FIG. 11B is a cross-sectional view taken along line VI-VI' of FIG. 11A. [Figure 11C] FIG. 11B is a cross-sectional view taken along line VII-VII' in FIG. 11A. [Figure 12A] 11B is a cross-sectional view taken along line VI-VI' of a thin film transistor according to another embodiment of FIG. 11A. [Figure 12B] 11B is a cross-sectional view taken along line VII-VII' of a thin film transistor according to another embodiment of FIG. 11A; [Figure 13] FIG. 4 is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 14] FIG. 4 is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 15] FIG. 4 is a plan view of a thin film transistor according to still another embodiment of the present invention. [Figure 16A] 1 is a graph showing measurement of threshold voltage (Vth) of thin film transistors according to an example and a comparative example. [Figure 16B] FIG. 16B is a plan view of a thin film transistor according to a comparative example of FIG. 16A. [Figure 17] 1 is a graph showing carrier concentrations in various regions of an active layer. [Figure 18] 1 is a graph showing carrier concentrations in various regions of an active layer. [Figure 19] 1 is a schematic diagram of a display device according to an embodiment of the present invention; [Figure 20] FIG. 2 is a schematic diagram of a shift register. [Figure 21] FIG. 20 is a circuit diagram of one of the pixels in FIG. 19. [Figure 22] FIG. 11 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention. [Diagram 23] FIG. 11 is a circuit diagram of one pixel of a display device according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The advantages and features of the present invention, as well as the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be configured in various different forms. The embodiments are provided solely for the purpose of making the disclosure of the present invention complete, and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains.

[0019] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely illustrative, and the present invention is not limited to the matters shown in the drawings. The same reference numbers may refer to the same components throughout the specification. In addition, in the description of the present invention, if a detailed description of related known technology is deemed to unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0020] When the terms "comprise", "have", "consist of", etc. are used in the present invention, other parts may be added unless "only" is used. When an element is expressed in the singular, it includes the plural unless otherwise expressly stated.

[0021] When interpreting elements, they are interpreted as including a margin of error unless otherwise expressly stated.

[0022] For example, when the location of two parts is described using "on," "at the top," "at the bottom," "beside," etc., one or more other parts can be located between the two parts, unless the word "immediately" or "directly" is used.

[0023] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like, may be used to facilitate the description of the relationship of one element or component to another element or component, as shown in the figures. Spatially relative terms should be understood as terms that include different orientations of elements in use or operation in addition to the orientation shown in the figures. For example, if elements shown in the figures are inverted, an element described as "below" or "below" the other element may be placed "above" the other element. Thus, the exemplary term "below" can include both an orientation below and above. Similarly, the exemplary terms "above" or "upper" can include both an orientation above and below.

[0024] When describing a temporal relationship, for example, when the temporal precedence / subsequence relationship is described using "after," "following," "next to," "before," etc., it can also include cases where the relationship is not consecutive, unless the words "immediately" or "directly" are used.

[0025] Although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical spirit of the present invention.

[0026] The term "at least one" should be understood to include all combinations that can be presented from one or more of the associated items. For example, the meaning of "at least one of the first item, the second item, and the third item" can mean not only each of the first item, the second item, or the third item, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0027] The features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and may be technically linked and driven in various ways, and each embodiment may be implemented independently of the others, or may be implemented together in a linked relationship.

[0028] When adding reference numbers to components in each figure illustrating an embodiment of the present invention, identical components may have the same numbers whenever possible, even if they appear in different figures.

[0029] In the embodiments of the present invention, the source electrode and the drain electrode are distinguished only for convenience of explanation, and the source electrode and the drain electrode may be interchangeable. A source electrode may be a drain electrode, and a drain electrode may be a source electrode. Also, a source electrode in any one embodiment may be a drain electrode in another embodiment, and a drain electrode in any one embodiment may be a source electrode in another embodiment.

[0030] In some embodiments of the present invention, for convenience of explanation, the source region and the source electrode may be distinguished, and the drain region and the drain electrode may be distinguished, but the embodiments of the present invention are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Also, the source region may be the drain electrode, and the drain region may be the source electrode.

[0031] Fig. 1 is a plan view of a thin film transistor 100 according to an embodiment of the present invention. Fig. 2A is a cross-sectional view taken along line II' in Fig. 1. Fig. 2B is a cross-sectional view taken along line II' in Fig. 1.

[0032] 1, 2A, and 2B, a transistor 100 according to one embodiment of the present invention can include an active layer 130 and a gate electrode 150.

[0033] In detail, referring to FIGS. 1, 2A and 2B, the semiconductor device may include an active layer 130 and a gate electrode 150 spaced apart from the active layer 130 and at least partially overlapping the active layer 130.

[0034] According to an embodiment of the present invention, the thin film transistor 100 may further include a base substrate 110. Referring to Figures 2A and 2B, the active layer 130 is disposed on the base substrate 110.

[0035] According to an embodiment of the present invention, the thin film transistor 100 may further include a buffer layer 120. Referring to Figures 2A and 2B, the active layer 130 is disposed on the buffer layer 120. In particular, the buffer layer 120 is disposed between the base substrate 110 and the active layer 130.

[0036] According to an embodiment of the present invention, the thin film transistor 100 may further include a gate insulating layer 140. Referring to Figures 2A and 2B, the gate insulating layer 140 is disposed on the active layer 130. In particular, the gate insulating layer 140 is disposed between the active layer 130 and the gate electrode 150.

[0037] According to an embodiment of the present invention, the thin film transistor 100 may further include an interlayer insulating film 160. Referring to FIG 2A, the interlayer insulating film 160 is disposed on the gate electrode 150. In particular, the gate electrode 150 is disposed between the gate insulating film 140 and the interlayer insulating film 160.

[0038] According to an embodiment of the present invention, the thin film transistor 100 may further include a source electrode 171 and a drain electrode 172. Referring to Fig. 2A, the source electrode 171 and the drain electrode 172 are disposed on the interlayer insulating film 160. In particular, the interlayer insulating film 160 is disposed between the gate electrode 150 and the source electrode 171 and the drain electrode 172.

[0039] The components of the thin film transistor 100 according to an embodiment of the present invention will now be described in more detail.

[0040] Glass or plastic can be used for the base substrate 110. As the plastic, a transparent plastic having a flexible property, such as polyimide, can be used.

[0041] When polyimide is used as the base substrate 110, a heat-resistant polyimide that can withstand high temperatures can be used, considering that a high-temperature deposition process is performed on the base substrate 110. In this case, in order to form a thin film transistor, processes such as deposition and etching can be performed in a state where the polyimide substrate is placed on a carrier substrate made of a highly durable material such as glass.

[0042] With reference to FIGS. 2A and 2B, a buffer layer 120 may be disposed on a base substrate 110 .

[0043] The buffer layer 120 is formed on the base substrate 110 and may be made of an inorganic or organic material, for example, an insulating oxide such as silicon oxide (SiOx) or aluminum oxide (Al2O3).

[0044] The buffer layer 120 protects the active layer 130 by blocking impurities such as moisture and oxygen that may flow in from the base substrate 110, and serves to planarize the upper surface of the base substrate 110. The buffer layer 120 may be formed as a single layer or multiple layers.

[0045] 2A and 2B, an active layer 130 may be disposed on the buffer layer 120. As shown in FIG.

[0046] The active layer 130 may include a channel region 130a, a source region 130b, and a drain region 130c.

[0047] In detail, the active layer 130 may include a channel region 130a overlapping with the gate electrode 150 in a planar view, a source region 130b not overlapping with the gate electrode 150 in a planar view and connected to one side of the channel region 130a, and a drain region 130c not overlapping with the gate electrode 150 in a planar view and connected to the other side of the channel region 130a.

[0048] According to one embodiment of the present invention, source region 130b and drain region 130c are spaced apart from each other across channel region 130a.

[0049] According to an embodiment of the present invention, the active layer 130 may be formed of a semiconductor material, and may include an oxide semiconductor material.

[0050] The oxide semiconductor material may include at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and an FIZO (FeInZnO)-based oxide semiconductor material. However, an embodiment of the present invention is not limited thereto, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

[0051] The source region 130b and the drain region 130c may be formed by selectively conducting the active layer 130 made of a semiconductor material. According to an embodiment of the present invention, selectively conducting refers to imparting electrical conductivity to a specific portion of the active layer 130 so that it can function as a conductor.

[0052] For example, the active layer 130 may be selectively made conductive by ion doping, thereby forming the source region 130b and the drain region 130c. However, an embodiment of the present invention is not limited thereto, and the active layer 130 may be selectively made conductive by other methods known in the art.

[0053] The source region 130b and the drain region 130c do not overlap with the gate electrode 150. The source region 130b and the drain region 130c have superior conductivity and high mobility compared to the channel region 130a. Therefore, the source region 130b and the drain region 130c can each serve as wiring.

[0054] 1, the channel region 130a has a channel length (L) and a channel width (W). Here, the channel length (L) of the channel region 130a means the length in the direction of the source region 130b and the drain region 130c. Also, the channel width (W) of the channel region 130a means the length of the channel region 130a in the vertical direction.

[0055] According to an embodiment of the present invention, the active layer 130 may include a first source conductive adjustment region 135a and a first drain conductive adjustment region 136a. The first source conductive adjustment region 135a and the first drain conductive adjustment region 136a are separated from each other. In particular, they are separated from each other with at least a part of the channel region 130a in between.

[0056] 1 and 2B, the first source conductor adjustment region 135a can overlap at least a part of the channel region 130a. FIG. 1 shows a configuration in which the first source conductor adjustment region 135a overlaps at least a part of the channel region 130a. In particular, at least a part of the first source conductor adjustment region 135a can overlap at least a part of the gate electrode 150. FIG. 1 shows a configuration in which at least a part of the first source conductor adjustment region 135a overlaps at least a part of the gate electrode 150. However, an embodiment of the present invention is not limited thereto, and the first source conductor adjustment region 135a can overlap with the channel region 130a and the source region 130b at the same time. In particular, at least a part of the first source conductor adjustment region 135a may overlap with the gate electrode 150, while another part of the first source conductor adjustment region 135a may not overlap with the gate electrode 150. Here, the overlap of the first source conductor adjusting region 135a with at least a part of the channel region 130a can be regarded as the same structural expression as the overlap of the first source conductor adjusting region 135a with at least a part of the gate electrode 150. The same applies to the first source conductor adjusting region 136a below.

[0057] Also, the first drain conductor adjustment region 136a can overlap at least a part of the channel region 130a. FIG. 1 shows a configuration in which the first drain conductor adjustment region 136a overlaps at least a part of the channel region 130a. More specifically, at least a part of the first drain conductor adjustment region 136a can overlap at least a part of the gate electrode 150. FIG. 1 shows a configuration in which at least a part of the first drain conductor adjustment region 136a overlaps at least a part of the gate electrode 150. However, one embodiment of the present invention is not limited thereto, and referring to FIG. 1, the first drain conductor adjustment region 136a can overlap with the channel region 130a and the drain region 130c at the same time. More specifically, at least a part of the first drain conductor adjustment region 136a may overlap with the gate electrode 150, while another part of the first drain conductor adjustment region 136a may not overlap with the gate electrode 150.

[0058] According to an embodiment of the present invention, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a can be formed by patterning the active layer 130. In particular, the first source conductor adjustment region 135a can be said to be a region that overlaps with at least a part of the channel region 130a and is surrounded by the active layer 130. In particular, the first source conductor adjustment region 135a can be said to be a region that overlaps with at least a part of the gate electrode 150 and is surrounded by the active layer 130. For example, the first source conductor adjustment region 135a can be said to be a portion where the active layer 130 is partially patterned and removed.

[0059] The first drain conductor adjustment region 136a can be said to be a region that overlaps with at least a part of the channel region 130a and is surrounded by the active layer 130. In detail, the first drain conductor adjustment region 136a can be said to be a region that overlaps with at least a part of the gate electrode 150 and is surrounded by the active layer 130. For example, the first drain conductor adjustment region 136a can be said to be a portion where the active layer 130 has been partially patterned and removed.

[0060] Referring to FIG. 1, according to one embodiment of the present invention, the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a have a width (D) and a length (S), where the width (D) may be in the range of 0.5 to 5 μm.

[0061] 1, according to one embodiment of the present invention, when the length of the region where the first source conductor adjustment region 135a and the gate electrode 150 overlap is S1, S1 may be in the range of 0.5 to 1.5 μm. The same is true for the first drain conductor adjustment region 136a, when the length of the region where the first drain conductor adjustment region 136a and the gate electrode 150 overlap is S2, S2 may be in the range of 0.5 to 1.5 μm.

[0062] According to an embodiment of the present invention, the first source conductor adjustment region 135a can overlap with the source region 130b. In particular, the first source conductor adjustment region 135a can protrude from the gate electrode 150 toward the source region 130b in a plan view. If the length of the region where the first source conductor adjustment region 135a and the source region 130b overlap is S3, S3 can be in the range of 0.5 to 5 μm. In particular, if the length of the region where the first source conductor adjustment region 135a protrudes from the gate electrode 150 in a plan view is S3, S3 can be in the range of 0.5 to 5 μm. This is also true for the first drain conductor adjustment region 136a, and if the length of the region where the first drain conductor adjustment region 136a and the drain region 130c overlap is S4, S4 can be in the range of 0.5 to 5 μm. In particular, if the length of the region where the first drain conductor adjustment region 136a protrudes from the gate electrode 150 in a plan view is taken as S4, S4 can be in the range of 0.5 to 5 μm.

[0063] 13, according to an embodiment of the present invention, the first source conductor adjustment region 135a may not overlap the boundary between the channel region 130a and the source region 130b. In particular, the first source conductor adjustment region 135a may be disposed apart from the boundary between the gate electrode 150 and the source region 130b. More particularly, the first source conductor adjustment region 135a may be disposed within the gate electrode 150 apart from the boundary between the gate electrode 150 and the source region 130b. If the shortest distance between the first source conductor adjustment region 135a and the boundary between the channel region 130a and the source region 130b is S5, S5 may be in the range of 0.5 to 1.5 μm. The same is true for the first drain conductor adjusting region 136a. If the shortest distance between the first drain conductor adjusting region 136a and the boundary between the channel region 130a and the drain region 130c is S6, S6 can be in the range of 0.5 to 1.5 μm.

[0064] According to an embodiment of the present invention, the channel region 130a can be partially conductorized. In particular, since the channel region 130a overlaps with the gate electrode 150, it is not a direct target for conductorization in the conductorization process. However, the boundary between the channel region 130a and the source region 130b and the boundary between the channel region 130a and the drain region 130c can be partially conductorized during the conductorization process due to the diffusion of dopants such as metal ions, the diffusion of hydrogen, and the indirect effect of plasma. As a result, the boundary between the channel region 130a and the source region 130b and the boundary between the channel region 130a and the drain region 130c can each have a carrier concentration gradient. The carrier concentration gradient will be described in detail with reference to FIG. 17 and FIG. 18.

[0065] In general, when the channel region 130a of the active layer 130 has a large channel width (W), the conductive diffusion may progress significantly in the boundary region between the channel region 130a and the source region and the drain region 130b, 130c. When the conductive diffusion progresses, the threshold voltage (Vth) of the thin film transistor 100 may shift in the negative (-) direction, and the driving stability of the thin film transistor 100 may decrease.

[0066] When the channel region 130a of the active layer 130 has a small channel width (W), the diffusion of conductor may be reduced in the boundary region between the channel region 130a and the source region and the drain region 130b, 130c. On the other hand, when the channel region 130a of the active layer 130 has a small channel width (W), the total amount of carriers passing through the channel region 130a of the thin film transistor 100 may be reduced, and the ON current characteristics may be deteriorated. As a result, if a large current is allowed to flow through the thin film transistor 100 having a small channel width (W) of the channel region 130a, the thin film transistor 100 may be damaged and the driving stability may be deteriorated. Therefore, it is necessary to control the diffusion of conductor even when the active layer 130 has a large channel width (W).

[0067] 3, 4A and 4B, according to an embodiment of the present invention, the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a are formed by patterning the first active layer 131, and the first active layer 131 may not be stacked on the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a, or the thickness of the first active layer 130 may be thin. As a result, the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a may have a low or almost no dopant concentration, and dopant diffusion can be prevented or suppressed around the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a. Therefore, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a can play the same role as forming multiple channel regions 130a with small channel widths (W) in the active layer 130, and can control conductor penetration even if the channel region 130a has a large width.

[0068] 1, when the active layer 130 includes the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, the conductorization can be suppressed on the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. Therefore, the conductorization progresses in the region of the channel region 130a of the active layer 130 excluding the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. As a result, even if the channel region 130a of the active layer 130 has a large channel width (W), the width of the region where the conductorization progresses is narrowed, and the conductorization penetration into the channel region 130a can be prevented or controlled.

[0069] According to an embodiment of the present invention, the first drain conductive adjustment region 136a may be disposed on the first line (LN), which is the shortest line connecting the source region 130b and the drain region 130c across the first source conductive adjustment region 135a. In detail, referring to FIG. 1, the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a may be disposed on the first line (LN). However, the embodiment of the present invention is not limited thereto, and the first drain conductive adjustment region 136a may be disposed on the first line (LN), which is the shortest line connecting the source region 130b and the drain region 130c across the first source conductive adjustment region 135a.

[0070] According to an embodiment of the present invention, the active layer 130 may include a first active layer 131. In particular, the first active layer 131 may be disposed in at least a part of the channel region 130a, at least a part of the source region 130b, and at least a part of the drain region 130c. Also, the first active layer 131 may not be disposed in at least a part of the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a.

[0071] When the first active layer 131 is disposed in the first source conductor adjustment region 135a, the thickness of the first active layer 131 disposed in the first source conductor adjustment region 135a may be thinner than the thickness of the first active layer 131 disposed in the channel region 130a excluding the first source conductor adjustment region 135a (see FIG. 4B).

[0072] Furthermore, when the first active layer 131 is disposed in the first drain conductor adjustment region 136a, the thickness of the first active layer 131 disposed in the first drain conductor adjustment region 136a may be thinner than the thickness of the first active layer 131 disposed in the channel region 130a excluding the first drain conductor adjustment region 136a (see FIG. 4B).

[0073] According to an embodiment of the present invention, the first source conductor adjustment region 135a can overlap the boundary between the channel region 130a and the source region 130b and can overlap at least a part of the source region 130b. In detail, the first source conductor adjustment region 135a can protrude from the gate electrode 150 toward the source region 130b in a plan view. FIG. 1 shows a configuration in which the first source conductor adjustment region 135a overlaps the boundary between the channel region 130a and the source region 130b and overlaps with the source region 130b. FIG. 1 also shows a configuration in which the first source conductor adjustment region 135a protrudes from the gate electrode 150 toward the source region 130b in a plan view. However, an embodiment of the present invention is not limited thereto, and the first source conductor adjustment region 135a may overlap the boundary between the channel region 130a and the source region 130b but may not overlap with the source region 130b. In detail, at least a part of the end of the first source conductor adjusting region 135a may be disposed at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductor adjusting region 135a may not protrude from the gate electrode 150 toward the source region 130b in a plan view (see FIG. 9). Also, the first source conductor adjusting region 135a may not overlap the boundary between the channel region 130a and the source region 130b. In detail, the first source conductor adjusting region 135a may be disposed apart from the boundary between the gate electrode 150 and the source region 130b in a plan view (see FIG. 13).

[0074] According to an embodiment of the present invention, the first drain conductor adjustment region 136a can overlap the boundary between the channel region 130a and the drain region 130c and can overlap at least a part of the drain region 130c. In detail, the first drain conductor adjustment region 136a can protrude from the gate electrode 150 toward the drain region 130c in a plan view. FIG. 1 shows a configuration in which the first drain conductor adjustment region 136a overlaps the boundary between the channel region 130a and the drain region 130c and overlaps with the drain region 130c. FIG. 1 also shows a configuration in which the first drain conductor adjustment region 136a protrudes from the gate electrode 150 toward the drain region 130c in a plan view. However, an embodiment of the present invention is not limited to this, and the first drain conductor adjustment region 136a may overlap the boundary between the channel region 130a and the drain region 130c and may not overlap with the drain region 130c. In detail, at least a part of the edge of the first drain conductor adjustment region 136a may be disposed at the boundary between the gate electrode 150 and the drain region 130c in a plan view, and the first drain conductor adjustment region 136a may not protrude from the gate electrode 150 toward the drain region 130c in a plan view (see FIG. 9). Also, the first drain conductor adjustment region 136a may not overlap the boundary between the channel region 130a and the drain region 130c. In detail, the first drain conductor adjustment region 136a may be disposed apart from the boundary between the gate electrode 150 and the drain region 130c in a plan view (see FIG. 13).

[0075] 1 or 9, the channel region 130a may have a first diffusion region (A1) and a second diffusion region (A2). Specifically, according to one embodiment of the present invention, the first diffusion region (A1) and the second diffusion region (A2) are spaced apart from each other.

[0076] According to one embodiment of the present invention, a first diffusion region (A1) is disposed on the channel region 130a and can contact the source region 130b. A second diffusion region (A2) is disposed on the channel region 130a and can contact the drain region 130c.

[0077] More specifically, the first diffusion region (A1) and the second diffusion region (A2) do not overlap with the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a.

[0078] The first diffusion region (A1) and the second diffusion region (A2) are regions that are partially conductive, and the first diffusion region (A1) and the second diffusion region (A2) refer to regions that are partially conductive in the channel region 130a. In detail, the first diffusion region (A1) and the second diffusion region (A2) overlap with the gate electrode 150, and therefore are not directly subject to the conductive process. However, the first diffusion region (A1) and the second diffusion region (A2) may be partially conductive due to the indirect influence of dopant diffusion, hydrogen diffusion, and plasma during the conductive process. Therefore, the first diffusion region (A1) and the second diffusion region (A2) each have a carrier concentration gradient. The carrier concentration gradient will be described in detail with reference to FIG. 17 and FIG. 18.

[0079] Also, referring to FIG. 1, the first diffusion region (A1) and the second diffusion region (A2) are regions in which the channel region 130a is partially conductorized, and the length or distance over which the channel region 130a is conductorized is called the conductor penetration depth (ΔL).

[0080] According to one embodiment of the present invention, when the length of the first diffusion region (A1) and the second diffusion region (A2) is defined as the conductor penetration depth (ΔL), the conductor penetration depth (ΔL) may be in the range of 0 to 1 μm.

[0081] In detail, a part of the channel region 130a is conductorized during the process of selectively conductorizing the active layer 130, and the conductorized region cannot function as a channel. In FIG. 1, the conductorization penetration depth, which is the length of the first diffusion region (A1) and the second diffusion region (A2) in the channel region 130a, is indicated by "ΔL". In addition, the region of the channel region 130a that is not conductorized and can effectively function as a channel is called the effective channel. As the conductorization penetration depth (ΔL) increases, the length of the effective channel decreases.

[0082] In order for a thin film transistor to perform its switching function, it is preferable to maintain the effective channel length at a predetermined value or more, and it is preferable to adjust the conductor penetration depth (ΔL) to ensure the predetermined effective channel length. Therefore, it is preferable that the conductor penetration depth (ΔL) is in the range of 0 to 1 μm.

[0083] A gate insulating film 140 may be disposed on the active layer 130. Referring specifically to Figure 2A, the gate insulating film 140 is disposed between the active layer 130 and the gate electrode 150.

[0084] The gate insulating film 140 may include at least one of silicon oxide, silicon nitride, and metal oxide, and may have a single film structure or a multi-layer structure.

[0085] A gate electrode 150 may be disposed on the gate insulating film 140. The gate electrode 150 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). Although not shown in the figure, the gate electrode 150 may have a multilayer structure including two conductive films with different physical properties.

[0086] The gate electrode 150 serves as a hydrogen barrier film that prevents hydrogen from entering from above the gate electrode 150 .

[0087] The thin film transistor 100 according to an embodiment of the present invention may further include an interlayer insulating layer 160. The interlayer insulating layer 160 is disposed on the gate electrode 150. The interlayer insulating layer 160 is an insulating layer made of an insulating material. The interlayer insulating layer 160 may be made of an organic material, an inorganic material, or a laminate of an organic layer and an inorganic layer.

[0088] According to an embodiment of the present invention, the thin film transistor 100 may include a source electrode 171 and a drain electrode 172. The source electrode 171 and the drain electrode 172 may be disposed on the interlayer insulating film 160, for example, as shown in FIG.

[0089] The source electrode 171 and the drain electrode 172 may be spaced apart from each other and connected to the active layer 130. Referring to Fig. 2A, the source electrode 171 and the drain electrode 172 may be connected to the active layer 130 through contact holes. More specifically, the source electrode 171 and the drain electrode 172 may be connected to the source region 130b and the drain region 130c of the active layer 130 through contact holes, respectively.

[0090] The source electrode 171 and the drain electrode 172 may each include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0091] In the embodiment and drawings of the present invention, the source electrode 171 and the drain electrode 172 are distinguished only for the convenience of explanation, and the source electrode 171 and the drain electrode 172 are not limited by the drawings and the above explanation. The source electrode 171 and the drain electrode 172 can be replaced with each other. The source region 130b and the drain region 130c are also distinguished only for the convenience of explanation, and the source region 130b and the drain region 130c can be replaced with each other.

[0092] FIG. 3 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention.

[0093] According to an embodiment of the present invention, the first active layer 131 may further include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b. Referring to FIG 3, the second oxide semiconductor layer 131b may be disposed on the first oxide semiconductor layer 131a.

[0094] FIG. 4A is a plan view and a cross-sectional view taken along line III-III' of a thin film transistor 300 according to another embodiment of the present invention, and FIG. 4B is a plan view and a cross-sectional view taken along line III-III' of a thin film transistor according to another embodiment of the present invention.

[0095] According to FIG. 4A, compared with FIG. 1, according to one embodiment of the present invention, the active layer 130 may further include a first active layer 131 and a second active layer 132 on the first active layer 131 .

[0096] According to an embodiment of the present invention, the second active layer 132 may be formed of a semiconductor material, and may include an oxide semiconductor material.

[0097] The second active layer 132 may be made of the same oxide semiconductor material as the first active layer 131 or may be made of a different oxide semiconductor material than the first active layer 131 .

[0098] According to an embodiment of the present invention, the second active layer 132 can be disposed over the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. In particular, the second active layer 132 can be disposed in the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a. FIG. 4 shows a configuration in which the second active layer 132 is disposed in the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a. More particularly, at least a portion of the second active layer 132 can contact the side of the first active layer 131 in the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a.

[0099] 4A shows a configuration in which the first active layer 131 is not disposed in at least a part of the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a, and the second active layer 132 is disposed in the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a. Also, referring to FIG. 4A, the second active layer 132 can contact the buffer layer 120 in the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a.

[0100] 4B shows a configuration in which the first active layer 131 is disposed in the first source conductor adjusting region 135a, as compared with FIG. 4A. In detail, when the first active layer 131 is disposed in the first source conductor adjusting region 135a, the thickness of the first active layer 131 disposed in the first source conductor adjusting region 135a may be thinner than the thickness of the first active layer 131 disposed in the channel region 130a excluding the first source conductor adjusting region 135a. Here, the second active layer 132 does not contact the buffer layer 120 in the first source conductor adjusting region 135a.

[0101] Also, the first active layer 131 may be disposed in the first drain conductor adjustment region 136a. In particular, when the first active layer 131 is disposed in the first drain conductor adjustment region 136a, the thickness of the first active layer 131 disposed in the first drain conductor adjustment region 136a may be thinner than the thickness of the first active layer 131 disposed in the channel region 130a excluding the first drain conductor adjustment region 136a. Here, the second active layer 132 does not contact the buffer layer 120 in the first drain conductor adjustment region 136a.

[0102] According to one embodiment of the present invention, even when the active layer 130 has a multi-layer structure, the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a are thinner than the regions of the active layer 130 other than the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, so that the conductor penetration depth (ΔL) into the channel region 130a can be controlled.

[0103] FIG. 5 is a plan view and a cross-sectional view taken along line IV-IV' of a thin film transistor 400 according to still another embodiment of the present invention.

[0104] According to FIG. 5, compared with FIG. 4, the first active layer 131 can include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b. Referring to FIG. 5, the first active layer 131 can include a first oxide semiconductor layer 131a and a second oxide semiconductor layer 131b on the first oxide semiconductor layer 131a. In detail, the first active layer 131 is patterned to form a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a, and the second active layer 132 can be disposed over the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. More specifically, the second active layer 132 can be disposed over the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a. At least a portion of the second active layer 132 may be in contact with any one of the first oxide semiconductor layer 131a and the second oxide semiconductor layer 131b in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a.

[0105] FIG. 6 is a plan view and a cross-sectional view taken along line VV' of a thin film transistor 500 according to still another embodiment of the present invention.

[0106] 6, compared with FIG. 4, the second active layer 132 can include a third oxide semiconductor layer 132a and a fourth oxide semiconductor layer 132b. Referring to FIG. 6, the second active layer 132 can include a third oxide semiconductor layer 132a and a fourth oxide semiconductor layer 132b on the third oxide semiconductor layer 132a. In detail, the first active layer 131 is patterned to form a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a, and the second active layer 132 can be disposed over the entire channel region 130a, the entire source region 130b, and the entire drain region 130c. More specifically, at least a portion of the second active layer 132 can contact at least a portion of the third oxide semiconductor layer 132a in the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a.

[0107] FIG. 7 is a cross-sectional view of a thin film transistor 600 according to another embodiment of the present invention.

[0108] Referring to FIG. 7, according to one embodiment of the present invention, the gate insulating film 140 may be patterned in various forms to cover the upper surface of the channel region 130a of the active layer 130 and expose the upper surfaces of the source region 130b and the drain region 130b.

[0109] 7 shows a configuration in which the gate insulating film 140 covers the entire upper surface of the active layer 130. However, an embodiment of the present invention is not limited to this, and the gate insulating film 140 may expose the upper surfaces of the source region 130b and the drain region 130b (see FIG. 2A).

[0110] FIG. 8 is a plan view of a thin film transistor 700 according to another embodiment of the present invention.

[0111] According to FIG. 8, compared with FIG. 1, a second source conductive adjustment region 135b and a second drain conductive adjustment region 136b can be further included.

[0112] According to an embodiment of the present invention, the active layer 130 includes a second source conductive adjustment region 135b and a second drain conductive adjustment region 136b spaced apart from each other, and the second source conductive adjustment region 135b can overlap at least a portion of the channel region 130a. In particular, at least a portion of the second source conductive adjustment region 135b can overlap at least a portion of the gate electrode 150.

[0113] The second drain conductive adjustment region 136b can overlap at least a portion of the channel region 130a. In particular, at least a portion of the second drain conductive adjustment region 136b can overlap at least a portion of the gate electrode 150.

[0114] As shown in FIG. 8, the first source conductor adjustment region 135a, the second source conductor adjustment region 135b, the first drain conductor adjustment region 136a, and the second drain conductor adjustment region 136b are shown to be the same size, but one embodiment of the present invention is not limited to this, and the first source conductor adjustment region 135a, the second source conductor adjustment region 135b, the first drain conductor adjustment region 136a, and the second drain conductor adjustment region 136b may not be the same size.

[0115] 8, the first source conductor adjustment region 135a is shown disposed above the second source conductor adjustment region 135b in a plan view, but the embodiment of the present invention is not limited to this, and the positions of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b can be interchanged. This also applies to the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b.

[0116] The second source conductor adjustment region 135b can overlap the boundary between the channel region 130a and the source region 130b and can overlap at least a part of the source region 130b. In detail, the second source conductor adjustment region 135b can protrude from the gate electrode 150 toward the source region 130b in a plan view. FIG. 8 shows a configuration in which the second source conductor adjustment region 135b overlaps the boundary between the channel region 130a and the source region 130b and can overlap at least a part of the source region 130b. FIG. 8 also shows a configuration in which the second source conductor adjustment region 135b protrudes from the gate electrode 150 toward the source region 130b in a plan view. However, an embodiment of the present invention is not limited to this, and the second source conductor adjustment region 135b may not overlap the source region 130b or may not overlap the boundary between the channel region 130a and the source region 130b. In detail, at least a portion of the end of the second source conductor adjustment region 135b is arranged at the boundary between the gate electrode 150 and the source region 130b in a planar view, the second source conductor adjustment region 135b may not protrude from the gate electrode 150 toward the source region 130b in a planar view, and the second source conductor adjustment region 135b can be arranged away from the boundary between the gate electrode 150 and the source region 130b in a planar view.

[0117] The second drain conductor adjustment region 136b can overlap the boundary between the channel region 130a and the drain region 130c and can overlap at least a part of the drain region 130c. In detail, the second drain conductor adjustment region 136b can protrude from the gate electrode 150 toward the drain region 130c in a plan view. FIG. 8 shows a configuration in which the second drain conductor adjustment region 136b overlaps the boundary between the channel region 130a and the drain region 130c and can overlap at least a part of the drain region 130c. FIG. 8 also shows a configuration in which the second drain conductor adjustment region 136b protrudes from the gate electrode 150 toward the drain region 130c in a plan view. However, an embodiment of the present invention is not limited to this, and the second drain conductor adjustment region 136b may not overlap the drain region 130b, and may not overlap the boundary between the channel region 130a and the drain region 130c. In detail, at least a portion of the end of the second drain conductor adjustment region 136b is arranged at the boundary between the gate electrode 150 and the drain region 130c in a planar view, the second drain conductor adjustment region 136b may not protrude from the gate electrode 150 toward the drain region 130c in a planar view, and the second drain conductor adjustment region 136b can be arranged away from the boundary between the gate electrode 150 and the drain region 130c in a planar view.

[0118] 8, the first diffusion region (A1) may be disposed between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b, where the first diffusion region (A1) does not overlap with the first source conductor adjustment region 135a and the second source conductor adjustment region 135b.

[0119] 8, the second diffusion region (A2) may be disposed between the first drain conductive adjustment region 136a and the second drain conductive adjustment region 136b, where the second diffusion region (A2) does not overlap with the first drain conductive adjustment region 136a and the second drain conductive adjustment region 136b.

[0120] According to an embodiment of the present invention, when the active layer 130 includes the second source conductor adjustment region 135b, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are separated from each other. When the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are separated from each other, the first diffusion region (A1) can be disposed between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b.

[0121] When the active layer 130 includes the first drain conductive adjustment region 136a and the second drain conductive adjustment region 136b, the first drain conductive adjustment region 136a and the second drain conductive adjustment region 136b are separated from each other. When the first drain conductive adjustment region 136a and the second drain conductive adjustment region 136b are separated from each other, the second diffusion region (A2) can be disposed between the first drain conductive adjustment region 136a and the second drain conductive adjustment region 136b.

[0122] According to an embodiment of the present invention, the first source conductor adjusting region 135a and the second source conductor adjusting region 135b can be arranged at intervals of 0.5 to 20 μm.

[0123] The first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b can be arranged at intervals of 0.5 to 20 μm. Here, the interval between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b and the interval between the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b may be the same as or different from each other.

[0124] If the distance between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b exceeds 20 μm, the width of the region where conductorization progresses in the channel region 130a becomes wider, and conductorization to the channel region 130a may not be prevented or controlled. As a result, the conductorization penetration depth (ΔL) of the diffusion regions (A1, A2) becomes longer, resulting in a relatively short effective channel length. In addition, the threshold voltage (Vth) of the thin film transistor may shift in the negative (-) direction, decreasing the driving stability of the thin film transistor. This also applies to the case where the distance between the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b exceeds 20 μm.

[0125] When the distance between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b is in the range of 0.5 to 20 μm, the width of the region in which the conductorization progresses in the channel region 130a becomes narrow, and the conductorization to the channel region 130a can be prevented or controlled. On the other hand, when the distance between the first source conductor adjustment region 135a and the second source conductor adjustment region 135b is less than 0.5 μm, the width of the region in which the conductorization progresses is too narrow, so that the total amount of carriers passing through the channel region 130a of the thin film transistor 100 decreases, and the ON current can be suppressed. As a result, if a large current flows through the thin film transistor 100 having a narrow width of the region in which the conductorization progresses, the thin film transistor 100 can be damaged and the driving stability can be reduced. This is also true when the distance between the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b is less than 0.5 μm.

[0126] According to an embodiment of the present invention, the active layer 130 may further include a third source conductive adjustment region and a third drain conductive adjustment region. Although Fig. 8 shows only the first source conductive adjustment region 135a, the second source conductive adjustment region 135b, the first drain conductive adjustment region 136a, and the second drain conductive adjustment region 136b, the present invention is not limited thereto, and although not shown in the figure, the number of source homes and drain homes may be three or more.

[0127] FIG. 9 is a plan view of a thin film transistor 800 according to yet another embodiment of the present invention.

[0128] 9, compared to FIG. 8, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b may overlap the boundary between the channel region 130a and the source region 130b, but may not overlap the source region 130b. Also, the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b may overlap the boundary between the channel region 130a and the drain region 130c, but may not overlap the drain region 130c. In detail, at least a part of the end of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b may be disposed at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductor adjustment region 135a and the second source conductor adjustment region 135b may not protrude from the gate electrode 150 toward the source region 130b in a plan view. The same is true for the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b.

[0129] According to an embodiment of the present invention, even when the first source conductor adjustment region 135a, the second source conductor adjustment region 135b, the first drain conductor adjustment region 136a, and the second drain conductor adjustment region 136b do not overlap with the source region 130b and the drain region 130c, respectively, it is possible to prevent or control the conductor diffusion into the channel region 130a. In detail, even when the first source conductor adjustment region 135a and the second source conductor adjustment region 135b do not protrude from the gate electrode 150 toward the source region 130b in a plan view, and the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b do not protrude from the gate electrode 150 toward the drain region 130c in a plan view, it is possible to prevent or control the conductor diffusion into the channel region 130a.

[0130] FIG. 10 is a plan view of a thin film transistor 900 according to yet another embodiment of the present invention.

[0131] 10, in comparison with FIG 9, at least one of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b can overlap with the source region 130b. In detail, at least one of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b can protrude from the gate electrode 150 toward the source region 130b in a plan view.

[0132] 10 shows a configuration in which the first source conductor adjustment region 135a overlaps with the source region 130b, and the second source conductor adjustment region 135b does not overlap with the source region 130b. In detail, FIG. 10 shows a configuration in which the first source conductor adjustment region 135a protrudes from the gate electrode 150 toward the source region 130b in a plan view, and the second source conductor adjustment region 135b does not protrude toward the source region 130b. However, an embodiment of the present invention is not limited to this, and the first source conductor adjustment region 135a may not overlap with the source region 130b, and the second source conductor adjustment region 135b may overlap with the source region 130b.

[0133] According to an embodiment of the present invention, at least one of the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b can overlap with the drain region 130c. In detail, at least one of the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b can protrude from the gate electrode 150 toward the drain region 130c in a plan view. FIG. 10 shows a configuration in which the first drain conductor adjustment region 136a overlaps with the drain region 130c, and the second drain conductor adjustment region 136b does not overlap with the drain region 130c. In detail, FIG. 10 shows a configuration in which the first drain conductor adjustment region 136a protrudes from the gate electrode 150 toward the drain region 130c in a plan view, and the second drain conductor adjustment region 136b does not protrude toward the drain region 130c. However, one embodiment of the present invention is not limited thereto. The first drain conductor adjustment region 136a may not overlap with the drain region 130c, and the second drain conductor adjustment region 136b may overlap with the drain region 130c.

[0134] FIG. 11A is a plan view of a thin film transistor according to still another embodiment of the present invention.

[0135] FIG. 11B is a cross-sectional view taken along line VI-VI' in FIG. 11A.

[0136] FIG. 11C is a cross-sectional view taken along line VII-VII' in FIG. 11A.

[0137] According to an embodiment of the present invention, the first source conductor adjustment region 135a overlaps with the longitudinal edge (R) of the channel region 130a, and more specifically, the first source conductor adjustment region 135a can be disposed on the longitudinal edge (R) of the channel region 130a in a plan view. Here, the longitudinal direction of the channel region 130a is the direction connecting the source region 130b and the drain region 130c.

[0138] 11A, 11B and 11C, an active layer 130 of a thin film transistor 1000 according to an embodiment of the present invention includes a first active layer 131 and a second active layer 132. As shown in FIG.

[0139] In detail, the active layer 130 includes a first source conductor adjustment region 135a and a second source conductor adjustment region 135b, and the first source conductor adjustment region 135a and the second source conductor adjustment region 135b overlap with the longitudinal edge (R) of the channel region 130a. More specifically, referring to Fig. 8, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are shown not overlapping with the longitudinal edge (R) of the channel region 130a. For example, in Fig. 8, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are arranged apart from the longitudinal edge (R) of the channel region 130a.

[0140] According to an embodiment of the present invention, the first drain conductor adjustment region 136a can overlap with the longitudinal edge (R) of the channel region 130a. In particular, the first drain conductor adjustment region 136a can be disposed at the longitudinal edge (R) of the channel region 130a in a plan view.

[0141] 11A, 11B and 11C, the active layer 130 includes a first drain conductive adjustment region 136a and a second drain conductive adjustment region 136b, which overlap with the longitudinal edge (R) of the channel region 130a. The contents overlapping with the first source conductive adjustment region 135a and the second source conductive adjustment region 135b are omitted.

[0142] 11B and 11C show a configuration including a first active layer 131 and a second active layer 132. However, an embodiment of the present invention is not limited thereto, and the second active layer 132 may not be included.

[0143] FIG. 12A is a cross-sectional view taken along line VI-VI' of a thin film transistor according to another embodiment of FIG. 11A.

[0144] FIG. 12B is a cross-sectional view taken along line VII-VII' of a thin film transistor according to another embodiment of FIG. 11A.

[0145] 12A and 12B show a configuration that does not include the second active layer 132, as compared to FIGS. 11B and 11C.

[0146] FIG. 13 is a plan view of a thin film transistor 1100 according to yet another embodiment of the present invention.

[0147] According to an embodiment of the present invention, the first source conductor adjustment region 135a may not overlap the boundary between the channel region 130a and the source region 130b. Also, the first drain conductor adjustment region 136a may not overlap the boundary between the channel region 130a and the drain region 130c. In detail, the first source conductor adjustment region 135a may be arranged apart from the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first drain conductor adjustment region 136a may be arranged apart from the boundary between the gate electrode 150 and the drain region 130c in a plan view.

[0148] 13, compared to FIG. 8, the first source conductor adjustment region 135a and the second source conductor adjustment region 135b may not overlap with the source region 130b and may not overlap with the boundary between the source region 130b and the channel region 130a.

[0149] According to an embodiment of the present invention, even if the first source conductor adjustment region 135a and the second source conductor adjustment region 135b do not overlap the boundary between the source region 130b and the channel region 130a, the conductor diffusion into the channel region 130a can be prevented or controlled. In particular, even if the first source conductor adjustment region 135a and the second source conductor adjustment region 135b are arranged apart from the boundary between the gate electrode 150 and the source region 130b in a plan view, the conductor diffusion into the channel region 130a can be prevented or controlled. In the case of the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b, even if they do not overlap the boundary between the drain region 130c and the channel region 130a, the conductor diffusion into the channel region 130a can be prevented or controlled. In detail, even when the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b are arranged away from the boundary between the gate electrode 150 and the drain region 130c in a planar view, conductor diffusion into the channel region 130a can be prevented or controlled.

[0150] FIG. 14 is a plan view of a thin film transistor 1200 according to yet another embodiment of the present invention.

[0151] 14 shows a configuration in which the first source conductor adjustment region 135a and the second source conductor adjustment region 135b overlap the boundary between the source region 130b and the channel region 130a, but do not overlap the source region 130b, as compared with FIG. 13. In detail, FIG. 14 shows a configuration in which at least a part of the end of the first source conductor adjustment region 135a and the second source conductor adjustment region 135b is disposed at the boundary between the gate electrode 150 and the source region 130b in a plan view, and the first source conductor adjustment region 135a and the second source conductor adjustment region 135b do not protrude from the gate electrode 150 toward the source region 130b in a plan view. On the other hand, an embodiment of the present invention is not limited thereto, and it is possible that only the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b overlap the boundary between the drain region 130c and the channel region 130a, but do not overlap the drain region 130c. In this case as well, the diffusion of conductive material into the channel region 130a can be controlled or prevented.

[0152] FIG. 15 is a plan view of a thin film transistor 1300 according to yet another embodiment of the present invention.

[0153] 15 shows a configuration in which the first source conductor adjustment region 135a and the second source conductor adjustment region 135b overlap with the source region 130b, as compared with FIG. 13. In detail, FIG. 15 shows a configuration in which the first source conductor adjustment region 135a and the second source conductor adjustment region 135b protrude from the gate electrode 150 toward the source region 130b in a plan view. However, an embodiment of the present invention is not limited to this, and only the first drain conductor adjustment region 136a and the second drain conductor adjustment region 136b may overlap with the drain region 130c. In either case, conductor diffusion into the channel region 130a can be controlled or prevented.

[0154] FIG. 16A is a graph showing the measurement of threshold voltage (Vth) of thin film transistors according to an example and a comparative example.

[0155] FIG. 16B is a plan view of a thin film transistor according to a comparative example of FIG. 16A.

[0156] Referring to FIG. 16A, graph a shows the measurement results of the threshold voltage (Vth) of the thin film transistor according to the embodiment, and graph b shows the measurement results of the threshold voltage (Vth) of the thin film transistor according to the comparative example.

[0157] In the graph of FIG. 16A, the horizontal axis is the gate voltage (V G ), and the vertical axis represents the drain-source current (I DS )

[0158] The thin film transistor according to the embodiment includes a first source conductor adjustment region 135a and a first drain conductor adjustment region 136a. Meanwhile, the thin film transistor according to the comparative example does not include the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a (see FIG. 16B). The thin film transistor according to the embodiment may further include a second source conductor adjustment region 135b and a second drain conductor adjustment region 136b.

[0159] In the case of an embodiment including the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, conductor penetration can be prevented or controlled at the boundary between the channel region 130a and the source region 130b, and at the boundary between the channel region 130a and the drain region 130c. As a result, even if the channel region 130a of the active layer 130 has a large channel width (W), the channel width (W) of the region where conductorization progresses becomes narrow, and conductorization into the channel region 130a can be suppressed or controlled.

[0160] Therefore, when the conductivization of the channel region 130a is suppressed or controlled, the conductivization penetration depth (ΔL) is shortened, and the effective channel length is relatively large. Also, when the conductivization of the channel region 130a is suppressed or controlled, the shift of the threshold voltage (Vth) of the thin film transistor in the negative (-) direction can be controlled, thereby improving the driving stability of the thin film transistor.

[0161] Referring to FIG. 16B, in the comparative example that does not include the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, conductor progression may occur at the boundary between the channel region 130a and the source region 130b and at the boundary between the channel region 130a and the drain region 130c.

[0162] Therefore, when the conductive layer is formed in the channel region 130a, the conductive penetration depth (ΔL) is increased, resulting in a relatively short effective channel length. Also, when the conductive layer is formed in the channel region 130a, the threshold voltage (Vth) of the thin film transistor may shift in the negative (-) direction, resulting in a decrease in the driving stability of the thin film transistor.

[0163] When comparing a thin film transistor according to an embodiment of the present invention having an active layer 130 including the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a with a thin film transistor according to a comparative example of the present invention having an active layer 130 not including the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a, it can be confirmed that at the same ON current, the threshold voltage (Vth) of the thin film transistor according to the comparative example of the present invention shifts in the negative (-) direction.

[0164] Fig. 17 is a graph of carrier concentration in each region of the active layer 130. In particular, Fig. 17 is a graph of carrier concentration according to VII-VII' of the active layer 130. Here, the active layer 130 may be made of an oxide semiconductor material.

[0165] The horizontal axis of the graph in Fig. 17 represents the source region 130b, the channel region 130a, and the drain region 130c, respectively, with the first source conductor adjustment region 135a overlapping the source region 130b and the channel region 130a, and the first drain conductor adjustment region 136a overlapping the channel region 130a and the drain region 130c. The horizontal axis of Fig. 17 may correspond to the distance measured from the left edge of the active layer 130 shown in Fig. 17.

[0166] The vertical axis of the graph in FIG. 17 represents the carrier concentration (au).

[0167] 17, the first active layer 131 may not be stacked on the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a, or the thickness of the first active layer 130 may be thin. As a result, the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a may have a low or almost no dopant concentration. Therefore, the carrier concentration of the first source conductive adjustment region 135a and the first drain conductive adjustment region 136a may be zero or very low. On the other hand, the thickness of the first active layer 131 arranged in the channel region 130a excluding the first source conductor adjusting region 135a and the first drain conductor adjusting region 136a is thicker than the thickness of the first active layer 131 arranged in the first source conductor adjusting region 135a and the first drain conductor adjusting region 136a, and the carrier concentration of the channel region 130a excluding the first source conductor adjusting region 135a and the first drain conductor adjusting region 136a is higher than the carrier concentration of the first source conductor adjusting region 135a and the first drain conductor adjusting region 136a. The source region 130b and the drain region 130c are regions formed by conductorization and have high carrier concentrations.

[0168] Fig. 18 is a graph showing carrier concentration in each region of the active layer 130. In particular, Fig. 18 is a graph showing carrier concentration according to IX-IX' of the active layer 130. Here, the active layer 130 may be made of an oxide semiconductor material.

[0169] The vertical axis of the graph in FIG. 18 is the same as that in FIG. 17 and is therefore omitted.

[0170] The horizontal axis of the graph in Figure 18 represents the source region 130b, the channel region 130a, and the drain region 130c, respectively, and the channel region 130a includes a first diffusion region (A1) and a second diffusion region (A2). The horizontal axis of Figure 18 may correspond to the distance measured from the left edge of the active layer 130 shown in Figure 18.

[0171] 18, the channel region 130a except for the first source conductor adjustment region 135a and the first drain conductor adjustment region 136a has a high carrier concentration, and the source region 130b and the drain region 130c are regions formed by conductorization and have a high carrier concentration. In addition, a carrier concentration gradient is formed in the first diffusion region (A1) and the second diffusion region (A2).

[0172] According to one embodiment of the present invention, the first diffusion region (A1) has a carrier concentration gradient that decreases in a direction away from the source region 130b. In particular, referring to the graph of Fig. 18, the carrier concentration is highest in the source region 130b, the carrier concentration of the first diffusion region (A1) decreases gradually as it moves away from the source region 130b, and the carrier concentration is lowest in the region of the channel region 130a other than the first diffusion region (A1) and the second diffusion region (A2).

[0173] According to one embodiment of the present invention, the second diffusion region (A2) has a carrier concentration gradient that decreases in a direction away from the drain region 130c. In particular, referring to the graph of Fig. 18, the carrier concentration is highest in the drain region 130c, the carrier concentration of the second diffusion region (A2) decreases gradually as it moves away from the drain region 130c, and the carrier concentration is lowest in the region of the channel region 130a other than the first diffusion region (A1) and the second diffusion region (A2).

[0174] FIG. 19 is a schematic diagram of a display device 1500 according to yet another embodiment of the present invention.

[0175] A display device 1500 according to another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340, as shown in FIG.

[0176] The display panel 310 includes gate lines (GL) and data lines (DL), and pixels (P) are arranged at the intersections of the gate lines (GL) and the data lines (DL). Images are displayed by driving the pixels (P). The gate lines (GL), data lines (DL) and pixels (P) may be arranged on a base substrate 110.

[0177] The control unit 340 controls the gate driver 320 and the data driver 330 .

[0178] The controller 340 uses a signal provided from an external system (not shown) to output a gate control signal (GCS) for controlling the gate driver 320 and a data control signal (DCS) for controlling the data driver 330. In addition, the controller 340 samples input image data provided from the external system, realigns the input image data, and provides the realigned digital image data (RGB) to the data driver 330.

[0179] The gate control signal (GCS) includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), a gate clock (GCLK), etc. The gate control signal (GCS) may also include a control signal for controlling a shift register.

[0180] The data control signal (DCS) includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like.

[0181] The data driver 330 supplies a data voltage to the data lines (DL) of the display panel 310. In particular, the data driver 330 converts the image data (RGB) input from the control unit 340 into an analog data voltage, and supplies the data voltage to the data lines (DL).

[0182] According to an embodiment of the present invention, the gate driver 320 may be mounted on the display panel 310. Such a structure in which the gate driver 320 is directly mounted on the display panel 310 is called a Gate In Panel (GIP) structure. In detail, in the Gate In Panel (GIP) structure, the gate driver 320 may be disposed on the base substrate 110.

[0183] The display device 1500 according to an embodiment of the present invention may include the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300. According to an embodiment of the present invention, the gate driver 320 may include the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300.

[0184] The gate driver 320 may include a shift register 350 .

[0185] The shift register 350 sequentially supplies gate pulses to the gate lines (GL) for one frame using a start signal, a gate clock, etc. transmitted from the control unit 340. Here, one frame refers to a period during which one image is output through the display panel 310. The gate pulse has a turn-on voltage that can turn on a switching element (thin film transistor) arranged in the pixel (P).

[0186] In addition, the shift register 350 supplies a gate-off signal capable of turning off the switching element to the gate line (GL) during the remaining period during one frame in which the gate pulse is not supplied. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a scan signal (SS or Scan).

[0187] The shift register 350 may include the thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 described above.

[0188] FIG. 20 is a schematic diagram of a shift register 350.

[0189] Referring to FIG. 20, a shift register 350 can include g stages 351 (ST1 to STg).

[0190] The shift register 350 transmits one scan signal (SS) to a pixel (P) connected to one gate line (GL) via one gate line (GL). Each of the stages 351 can be connected to one gate line (GL). When g gate lines (GL) are formed on the display panel 110, the shift register 350 can include g stages 351 (ST1 to STg) and generate g scan signals (SS1 to SSg).

[0191] In general, each stage 351 outputs a gate pulse (GP) once during one frame, and the gate pulse (GP) is output in sequence by each stage 351.

[0192] FIG. 21 is a circuit diagram of any one of the pixels (P) in FIG.

[0193] The circuit diagram of FIG. 21 is an equivalent circuit diagram for a pixel (P) of a display device 1500 that includes an organic light emitting diode (OLED) as the display element 710.

[0194] 21, a pixel (P) includes a display element 710 and a pixel driving circuit (PDC) that drives the display element 710. In particular, a display device 1500 according to an embodiment of the present invention may include a pixel driving circuit (PDC) on a base substrate 110.

[0195] The pixel driving circuit (PDC) of Fig. 21 includes a first thin film transistor (TR1) which is a switching transistor and a second thin film transistor (TR2) which is a driving transistor. A display device 1500 according to another embodiment of the present invention may include at least one of the thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300.

[0196] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off according to a scan signal SS provided through the gate line GL.

[0197] The data line (DL) provides a data voltage (Vdata) to the pixel driving circuit (PDC), and the first thin film transistor (TR1) controls the application of the data voltage (Vdata).

[0198] The driving power line (PL) provides a driving voltage (Vdd) to the display element 710, and the first thin film transistor (TR1) controls the driving voltage (Vdd). The driving voltage (Vdd) is a pixel driving voltage for driving the organic light emitting diode (OLED) which is the display element 710.

[0199] When the first thin film transistor (TR1) is turned on by the scan signal (SS) applied from the gate driver 320 through the gate line (GL), the data voltage (Vdata) supplied through the data line (DL) is supplied to the gate electrode of the second thin film transistor (TR2) connected to the display element 710. The data voltage (Vdata) is charged in the storage capacitor (Cst) formed between the gate electrode and source electrode of the second thin film transistor (TR2).

[0200] The amount of current supplied to the organic light emitting diode (OLED), which is the display element 710, through the second thin film transistor (TR2) is controlled by the data voltage (Vdata), thereby controlling the gray scale of the light output from the display element 710.

[0201] FIG. 22 is a circuit diagram of one pixel (P) of a display device 1600 according to still another embodiment of the present invention.

[0202] FIG. 22 is an equivalent circuit diagram of a pixel (P) of an organic light emitting display device.

[0203] 22 includes an organic light emitting diode (OLED) as a display element 710, and a pixel driving circuit (PDC) for driving the display element 710. The display element 710 is coupled to the pixel driving circuit (PDC).

[0204] Signal lines (DL, GL, PL, RL, SCL) that supply signals to a pixel drive circuit (PDC) are arranged in the pixels (P).

[0205] A data voltage (Vdata) is supplied to the data line (DL), a scan signal (SS) is supplied to the gate line (GL), a drive voltage (Vdd) for driving the pixels is supplied to the drive power line (PL), a reference voltage (Vref) is supplied to the reference line (RL), and a sensing control signal (SCS) is supplied to the sensing control line (SCL).

[0206] The pixel driving circuit (PDC) includes, for example, a first thin film transistor (TR1) (switching transistor) connected to the gate line (GL) and the data line (DL), a second thin film transistor (TR2) (driving transistor) that controls the amount of current output to the display element 710 according to the data voltage (Vdata) transmitted through the first thin film transistor (TR1), and a third thin film transistor (TR3) (sensing transistor) for sensing the characteristics of the second thin film transistor (TR2).

[0207] The first thin film transistor (TR1) is turned on by a scan signal (SS) supplied to the gate line (GL) and transmits a data voltage (Vdata) supplied to the data line (DL) to the gate electrode of the second thin film transistor (TR2).

[0208] The third thin film transistor (TR3) is connected to the first node (n1) between the second thin film transistor (TR2) and the display element 710 and the reference line (RL), and is turned on or off according to the sensing control signal (SCS) to sense the characteristics of the second thin film transistor (TR2), which is a driving transistor, during the sensing period.

[0209] A second node (n2) connected to the gate electrode of the second thin film transistor (TR2) may be connected to the first thin film transistor (TR1). A storage capacitor (Cst) is formed between the second node (n2) and the first node (n1).

[0210] When the first thin film transistor (TR1) is turned on, the data voltage (Vdata) supplied through the data line (DL) is supplied to the gate electrode of the second thin film transistor (TR2). The data voltage (Vdata) is charged in the storage capacitor (Cst) formed between the gate electrode and source electrode of the second thin film transistor (TR2).

[0211] When the second thin film transistor (TR2) is turned on, a current is supplied to the display element 710 via the second thin film transistor (TR2) by the driving voltage (Vdd) that drives the pixel, and the display element 710 outputs light.

[0212] A display device 1600 according to another embodiment of the present invention may include at least one of the thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300.

[0213] FIG. 23 is a circuit diagram of one pixel (P) of a display device 1700 according to still another embodiment of the present invention.

[0214] A pixel (P) of the display device 1700 shown in Figure 23 includes an organic light emitting diode (OLED) as a display element 710, and a pixel drive circuit (PDC) that drives the display element 710. The display element 710 is coupled to the pixel drive circuit (PDC).

[0215] The pixel driving circuit (PDC) includes thin film transistors (TR1, TR2, TR3, TR4).

[0216] Signal lines (DL, EL, GL, PL, SCL, RL) that supply drive signals to a pixel drive circuit (PDC) are arranged in the pixels (P).

[0217] The pixel (P) of Figure 23 further includes an emission control line (EL) compared to the pixel (P) of Figure 22. The emission control signal (EM) is supplied to the emission control line (EL). Also, the pixel driving circuit (PDC) of Figure 23 further includes a fourth thin film transistor (TR4) which is an emission control transistor for controlling the emission time point of the second thin film transistor (TR2) compared to the pixel driving circuit (PDC) of Figure 22.

[0218] The first thin film transistor (TR1) is turned on by a scan signal (SS) supplied to the gate line (GL) and transmits a data voltage (Vdata) supplied to the data line (DL) to the gate electrode of the second thin film transistor (TR2).

[0219] Between the gate electrode of the second thin film transistor TR2 and the display element 710, a storage capacitor Cst is located.

[0220] The third thin film transistor TR3 is connected to the reference line RL and is turned on or off according to the sensing control signal SCS to sense the characteristics of the second thin film transistor TR2, which is a driving transistor, during a sensing period.

[0221] The fourth thin film transistor (TR4) transmits the driving voltage (Vdd) to the second thin film transistor (TR2) or blocks the driving voltage (Vdd) according to the light emission control signal (EM). When the fourth thin film transistor (TR4) is turned on, a current is supplied to the second thin film transistor (TR2), and light is output from the display element 710.

[0222] The pixel driving circuit (PDC) according to other embodiments of the present invention may be formed in various other structures than those described above. For example, the pixel driving circuit (PDC) may include five or more thin film transistors.

[0223] The present invention described above is not limited by the above-mentioned embodiments and the attached drawings, and various substitutions, modifications and changes are possible within the scope of the technical subject of the present invention, which will be apparent to those skilled in the art to which the present invention pertains. Therefore, the scope of the present invention is shown by the claims below, and all modifications or alterations derived from the meaning, scope and equivalent concept of the claims should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0224] 110: Base substrate 120: Buffer layer 130: Active layer 130a: Channel region 130b: Source area 130c: Drain region 131: First active layer 132: Second active layer 131a: first oxide semiconductor layer 131b: second oxide semiconductor layer 132a: third oxide semiconductor layer 132b: fourth oxide semiconductor layer 135a: First source conductive adjustment region 135b: second source conductive adjustment region 136a: First drain conductive adjustment region 136b: second drain conductive adjustment region 140: Gate insulating film 150: Gate electrode 160: Interlayer insulating film 171: Source electrode 172: Drain electrode

Claims

1. The active layer, a gate electrode spaced apart from the active layer and at least partially overlapping the active layer; The active layer is a channel region overlapping the gate electrode in a plan view; a source region that does not overlap the gate electrode in a plan view and is connected to one side of the channel region; a drain region that does not overlap the gate electrode in a plan view and is connected to the other side of the channel region, the source region and the drain region are spaced apart from each other with the channel region therebetween; the active layer includes a first source conductive adjustment region and a first drain conductive adjustment region spaced apart from each other; At least a portion of the first source conductor adjustment region overlaps with at least a portion of the gate electrode; At least a portion of the first drain conductor adjustment region overlaps with at least a portion of the gate electrode, the active layer includes a first active layer and a second active layer on the first active layer; the first active layer is disposed on at least a portion of the channel region, at least a portion of the source region, and at least a portion of the drain region; the second active layer is disposed in the first source conductive adjustment region and the first drain conductive adjustment region; A thin film transistor, wherein at least a portion of the second active layer contacts sides of the first active layer within the first source conductive adjustment region and the first drain conductive adjustment region.

2. 2. The thin film transistor according to claim 1, wherein the first drain conductor adjustment region is disposed on a first line that is the shortest line that crosses the first source conductor adjustment region and connects the source region and the drain region.

3. The thin film transistor of claim 1 , wherein the active layer is absent from at least a portion of the first source conductive adjustment region and the first drain conductive adjustment region.

4. 2. The thin film transistor of claim 1, wherein a thickness of the first active layer disposed in the first source conductor adjustment region is thinner than a thickness of the first active layer disposed in the channel region excluding the first source conductor adjustment region.

5. 2. The thin film transistor according to claim 1, wherein the thickness of the first active layer disposed in the first drain conductor adjustment region is thinner than the thickness of the first active layer disposed in the channel region excluding the first drain conductor adjustment region.

6. The thin film transistor according to claim 1 , wherein the first active layer is not disposed in at least a portion of the first source conductive adjustment region and the first drain conductive adjustment region.

7. The thin film transistor of claim 1 , wherein the second active layer is disposed over the channel region, the source region, and the drain region.

8. The thin film transistor of claim 1 , wherein the first active layer comprises a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer.

9. The thin film transistor of claim 1 , wherein the second active layer comprises a third oxide semiconductor layer and a fourth oxide semiconductor layer on the third oxide semiconductor layer.

10. A thin film transistor as described in claim 8, wherein at least a portion of the second active layer contacts one of the first oxide semiconductor layer and the second oxide semiconductor layer within the first source conductor adjustment region and the first drain conductor adjustment region.

11. 10. The thin film transistor of claim 9, wherein at least a portion of the first active layer contacts at least a portion of the third oxide semiconductor layer in the first source conductive adjustment region and the first drain conductive adjustment region.

12. at least a part of an end of the first source conductor adjustment region is disposed at a boundary between the gate electrode and the source region in a plan view; The thin film transistor according to claim 1 , wherein the first source conductor adjustment region does not protrude from the gate electrode toward the source region in a plan view.

13. At least a part of an end of the first drain conductor adjustment region is disposed at a boundary between the gate electrode and the drain region in a plan view, The thin film transistor according to claim 1 , wherein the first drain conductor adjustment region does not protrude from the gate electrode toward the drain region in a plan view.

14. The thin film transistor according to claim 1 , wherein the first source conductor adjustment region protrudes from the gate electrode toward the source region in a plan view.

15. The thin film transistor according to claim 1 , wherein the first drain conductor adjustment region protrudes from the gate electrode toward the drain region in a plan view.

16. The thin film transistor according to claim 1 , wherein the first source conductor adjustment region is disposed apart from a boundary between the gate electrode and the source region in a plan view.

17. The thin film transistor according to claim 1 , wherein the first drain conductor adjustment region is disposed apart from a boundary between the gate electrode and the drain region in a plan view.

18. the active layer includes a second source conductive adjustment region and a second drain conductive adjustment region spaced apart from each other; At least a portion of the second source conductor adjustment region overlaps with at least a portion of the gate electrode; The thin film transistor according to claim 1 , wherein at least a portion of the second drain conductor adjustment region overlaps at least a portion of the gate electrode.

19. the first source conductor adjustment region and the second source conductor adjustment region are spaced apart from each other; The thin film transistor of claim 18 , wherein the first drain conductor adjustment region and the second drain conductor adjustment region are spaced apart from each other.

20. 20. The thin film transistor according to claim 19, wherein the first source conductor adjustment region and the second source conductor adjustment region are arranged at intervals of 0.5 to 20 μm.

21. 20. The thin film transistor according to claim 19, wherein the first drain conductor adjustment region and the second drain conductor adjustment region are arranged at an interval in the range of 0.5 to 20 μm.

22. The first source conductive adjustment region and the first drain conductive adjustment region have a width (D) and a length (S), 2. The thin film transistor of claim 1, wherein the width (D) is in the range of 0.5 to 5 μm.

23. 2. The thin film transistor according to claim 1, wherein when a length of a region where said gate electrode overlaps said first source conductor adjustment region is taken as S1, said S1 is in a range of 0.5 to 1.5 μm.

24. 2. The thin film transistor according to claim 1, wherein when a length of a region where said gate electrode overlaps said first drain conductor adjustment region is taken as S2, said S2 is in a range of 0.5 to 1.5 μm.

25. 15. The thin film transistor according to claim 14, wherein when a length S3 of a region of the first source conductor adjustment region that protrudes from the gate electrode toward the source region in a plan view is taken as a length S3, the length S3 is in the range of 0.5 to 5 μm.

26. 16. The thin film transistor according to claim 15, wherein when the length S4 of the region of the first drain conductor adjustment region that protrudes from the gate electrode toward the drain region in a plan view is in the range of 0.5 to 5 μm.

27. 17. The thin film transistor according to claim 16, wherein S5 is a shortest distance between said first source conductor adjustment region and a boundary between said channel region and said source region, and said S5 is in the range of 0.5 to 1.5 μm.

28. 18. The thin film transistor according to claim 17, wherein when the shortest distance between said first drain conductor adjustment region and the boundary between said channel region and said drain region is S6, said S6 is in the range of 0.5 to 1.5 μm.

29. 20. The thin film transistor according to claim 18, wherein at least one of the first source conductor adjustment region and the second source conductor adjustment region protrudes from the gate electrode toward the source region in a plan view.

30. The thin film transistor according to claim 18 , wherein at least one of the first drain conductor adjustment region and the second drain conductor adjustment region protrudes from the gate electrode toward the drain region in a plan view.

31. The first source conductor adjustment region is disposed on an edge (R) of the channel region in a longitudinal direction in a plan view, The thin film transistor according to claim 1 , wherein the longitudinal direction of the channel region is a direction connecting the source region and the drain region.

32. The first drain conductor adjustment region is disposed at an edge (R) in a longitudinal direction of the channel region in a plan view, The thin film transistor according to claim 1 , wherein the longitudinal direction of the channel region is a direction connecting the source region and the drain region.

33. the channel region having a first diffusion region and a second diffusion region spaced apart from each other; the first diffusion region is disposed on the channel region and in contact with the source region; the second diffusion region is disposed on the channel region and in contact with the drain region; The thin film transistor of claim 1 , wherein the first diffusion region and the second diffusion region do not overlap the first source conductor adjustment region and the first drain conductor adjustment region.

34. 34. The thin film transistor of claim 33, wherein the first diffusion region and the second diffusion region are partially conductive.

35. 34. The thin film transistor of claim 33, wherein the first diffusion region has a decreasing carrier concentration gradient along a direction away from the source region.

36. 34. The thin film transistor of claim 33, wherein the second diffusion region has a decreasing carrier concentration gradient along a direction away from the drain region.

37. A display device comprising the thin film transistor according to any one of claims 1 to 36.

Images