Display device

Abstract

One object is to suppress deterioration of characteristics of a transistor in a driver circuit. The potential state of an output signal is controlled by turning on or off in response to a first input signal. a first switch that controls whether to set the power supply voltage to the power supply voltage, and a second switch that controls whether to set the power supply voltage to the power supply voltage, a second switch that controls whether or not to set the potential state of the output signal by being turned on; When the first switch or the second switch is turned on or off, the first wiring and The second wiring is in a conductive state or a non-conductive state.

Description

[Technical field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device and a display device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a liquid crystal display device or a driving method thereof, or to the semiconductor device, the display device, The present invention also relates to an electronic device having the liquid crystal display device. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single crystal semiconductors are used to form a pixel region. The technology of configuring driving circuits such as gate drivers on a substrate is expected to contribute greatly to reducing costs and improving reliability. Development is underway actively to contribute significantly to the

[0003] A transistor formed of a non-single crystal semiconductor has a tendency to have a fluctuation in threshold voltage or a decrease in mobility. As this transistor degradation progresses, the driver circuit becomes less operable. Therefore, there is a problem that the image cannot be displayed. In Patent Document 1, the output signal of a flip-flop is lowered to an L level (also called a low level). In order to suppress deterioration of a transistor having a function of pulling down a These documents disclose a shift register that can be used to The two pull-down transistors are used in the flip-flop. It is connected between the output terminal and the wiring that supplies VSS (hereinafter referred to as the negative power supply). The pull-down transistor of the first transistor and the other pull-down transistor are alternately turned on (on state) This causes each pull-down transistor to turn on. Since the time during which the pull-down transistor is turned on is shortened, deterioration of the characteristics of the pull-down transistor can be suppressed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-50502 A [Patent Document 2] JP 2006-24350 A [Non-patent literature]

[0005] [Non-Patent Document 1] Yong Ho Jang, et al., “Integrated Gate Driver Circuit Using a-Si TFT with Dual Pull-down Structure”, Proceedings of The 11th International Display Workshops 2004, pp.333-336 Summary of the Invention [Problem to be solved by the invention]

[0006] In the configuration of the conventional technology, a transistor for controlling an output signal to a high level (hereinafter The gate potential of the pull-up transistor is a positive power supply voltage or a clock signal. This can cause the potential of the pull-up transistor to be higher than the high level of the A large voltage may be applied to the gate of the pull-up transistor. A large voltage may be applied to the transistor being used, or the transistor may become degraded. The transistors that make up the shift register are designed so that the shift register can still function even if the The channel width may be large. Or, if the channel width of the transistor is large, the transistor The gate of the transistor may be easily shorted to the source or drain. As the channel width of the transistors increases, the number of transistors that make up the shift register increases. The parasitic capacitance of the

[0007] An object of one embodiment of the present invention is to suppress deterioration of transistor characteristics. An object of one embodiment of the present invention is to reduce the channel width of a transistor. One aspect is to suppress deterioration of the characteristics of the pull-up transistor or to reduce the channel width. Another object of one embodiment of the present invention is to increase the amplitude of an output signal. Another object of one embodiment of the present invention is to increase the on-time of a transistor included in a pixel. Another object of one embodiment of the present invention is to improve insufficient writing to a pixel. Another object of one embodiment of the present invention is to shorten the fall time of an output signal. An object of one embodiment of the present invention is to shorten the rise time of an output signal. In one aspect of the invention, a video signal for pixels in one row is written to a pixel in another row. Alternatively, the object of the present invention is to prevent the fall time of the output signal from the drive circuit from being extended. The objective is to reduce the variation in the feedthrough effect on each pixel. Another object of the present invention is to reduce crosstalk. An object of one embodiment of the present invention is to reduce a layout area. Another object of the present invention is to narrow the frame of a display device. Another object of one embodiment of the present invention is to increase the yield. Another object of one embodiment of the present invention is to reduce manufacturing costs. An object of one embodiment of the present invention is to reduce the distortion of an output signal. Another object of the present invention is to reduce a delay in an output signal. Another object of one embodiment of the present invention is to reduce the current supply capability of an external circuit. Another object of one embodiment of the present invention is to provide a semiconductor device having an external circuit. The object of the present invention is to reduce the size of the display device. However, this does not prevent the existence of problems. Note that one embodiment of the present invention aims to solve all of these problems. It is not necessary to [Means for solving the problem]

[0008] One aspect of the present invention is a digital signal processing apparatus for detecting a first input signal, a second input signal, and a third input signal; A driving circuit that outputs an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in response to the output signal. and a pixel in which a voltage is set to a voltage corresponding to the pixel voltage, and the driving circuit is turned on or off in response to a third input signal. A first switch and a second switch that are turned on and off, and the first switch being turned on or off Whether the first input signal is input or not is controlled by the above, and the ON / OFF switch is turned on or off depending on the first input signal. a third switch that controls whether to set the potential state of the output signal by being turned on or off; and a second switch is turned on or off to determine whether a second input signal is input. The potential of the output signal is controlled by turning on or off according to the second input signal. and a fourth switch that controls whether or not to set the state.

[0009] One aspect of the present invention is a digital signal processing apparatus for detecting a first input signal, a second input signal, and a third input signal; A driving circuit that outputs an output signal and a liquid crystal element are provided, and a voltage is applied to the liquid crystal element in response to the output signal. and a pixel to which a voltage is set, the driving circuit having a gate, a source, and a drain. A third input signal is input to the gate, and a first input signal is input to one of the source and the drain. a first transistor having a gate, a source, and a drain, and a third transistor connected to the gate A second transistor to which an input signal is input and to which a second input signal is input to one of the source and the drain. a gate, a source, and a drain, the gate being connected to the source of the first transistor; The other of the source and drain is electrically connected to the output terminal, and the output signal is generated by turning the output terminal on or off. a third transistor for controlling whether or not to set the potential state of the the gate is electrically connected to the other of the source and drain of the second transistor. By being turned on or off, it controls whether or not to set the potential state of the output signal. and a fourth transistor.

[0010] One aspect of the present invention is a method for detecting a first input signal, a second input signal, a third input signal, and a fourth input signal. A liquid crystal display device includes a driving circuit to which a signal is input and which outputs an output signal, and a liquid crystal element, and the liquid crystal element changes in response to the output signal. A pixel in which a voltage applied to a liquid crystal element is set, and the driving circuit receives a first input signal. A first wiring to which a second input signal is input, a second wiring to which a second input signal is input, and a third wiring to which a third input signal is input. a third wiring to which a fourth input signal is input; a fourth wiring to which a fourth input signal is input; The gate is electrically connected to a third wiring, and one of the source and drain is a first transistor electrically connected to a first wiring; and a gate, a source, and a drain. The gate is electrically connected to the third wiring, and one of the source and the drain is connected to the second wiring. A second transistor electrically connected to the wiring and having a gate, a source, and a drain. The gate is electrically connected to the other of the source and drain of the first transistor, and the source a third transistor, one of whose drains is electrically connected to a fourth wiring; a gate connected to the other of the source and drain of the second transistor; a fourth line having a source and a drain electrically connected to the fourth line; the other of the source and drain of the third transistor and the fourth transistor The other of the source and drain of the transistor is electrically connected to the potential of the output signal. and a fifth wiring that serves as a second wiring.

[0011] One aspect of the present invention is a method for detecting a first input signal, a second input signal, a third input signal, and a fourth input signal. A liquid crystal display device includes a driving circuit that receives an input signal and outputs an output signal, and a liquid crystal element that changes the liquid crystal according to the output signal. A pixel in which a voltage applied to a liquid crystal element is set, and the driving circuit receives a first input signal. A first wiring to which a second input signal is input, a second wiring to which a second input signal is input, and a third wiring to which a third input signal is input. a third wiring to which a fourth input signal is input; a fourth wiring to which a fourth input signal is input; and a drain, and one of the gate and the source and drain is electrically connected to the first wiring. a first transistor having a gate, a source, and a drain, a second transistor, one of a gate and a drain of which is electrically connected to a second wiring; a gate connected to the source and drain of the first transistor, a second wiring, one of the source and drain of which is electrically connected to the second wiring; a first transistor having a gate, a source, and a drain, the gate being connected to a second transistor; the other of the source and drain of the fourth A fourth transistor electrically connected to the wiring and a source and a drain of the third transistor the other of the input terminals of the first transistor and the other of the source and drain terminals of the fourth transistor; and a fifth wiring to which a potential applied becomes a potential of an output signal.

[0012] According to one aspect of the present invention, a first input signal and a second input signal are input, and an output signal is output. The liquid crystal display has a driving circuit and a liquid crystal element, and the voltage applied to the liquid crystal element is set according to the output signal. The pixel includes a first wiring to which a first input signal is input, and a second input signal is input to the driving circuit. The gate and the source are connected to a second wiring to which a signal is input. a first transistor, one of a gate and a drain of which is electrically connected to a first wiring; , a source, and a drain, and the gate and one of the source and the drain are connected to a second wiring. a second transistor electrically connected to the gate electrode; and one of the source and drain of the first transistor is connected to the other of the source and drain of the second transistor. a third transistor electrically connected to the gate electrode; and one of the source and drain of the second transistor is connected to the other of the source and drain of the second transistor. A fourth transistor electrically connected to the source and drain of the third transistor. The other of the source and drain of the fourth transistor is electrically connected to the other of the source and drain of the fourth transistor. and a third wiring whose applied potential becomes the potential of an output signal.

[0013] In one embodiment of the present invention, the channel width of the third transistor is set to be equal to that of the fourth transistor. It can also be made equal to the channel width of the

[0014] In one embodiment of the present invention, the channel width of the first transistor is the channel width of the second transistor is made smaller than that of the fourth transistor; It can also be made smaller than the channel width.

[0015] According to one aspect of the present invention, a first input signal and a second input signal are input, and an output signal is output. The liquid crystal display has a driving circuit and a liquid crystal element, and the voltage applied to the liquid crystal element is set according to the output signal. The pixel includes a first wiring to which a first input signal is input, and a second input signal is input to the driving circuit. The gate and the source are connected to a second wiring to which a signal is input. a first transistor, one of a gate and a drain of which is electrically connected to a first wiring; , a source, and a drain, and the gate and one of the source and the drain are connected to a second wiring. a second transistor electrically connected to the first transistor, the second transistor having a positive electrode and a negative electrode, the positive electrode being connected to the first transistor; a first diode electrically connected to the other of the source and drain of the transistor; The positive electrode is electrically connected to the other of the source and drain of the second transistor. A second diode is connected to the negative terminal of the first diode and the negative terminal of the second diode. a third wiring electrically connected to the liquid crystal display device and a potential applied thereto becomes a potential of an output signal; It is a display device.

[0016] In one embodiment of the present invention, the channel width of the first transistor is It can also be made equal to the channel width of the

[0017] One embodiment of the present invention is a liquid crystal display device according to any one of the above, and a device for controlling the operation of the liquid crystal display device. and an operation switch for controlling the operation of the electronic device.

[0018] In addition, various types of switches can be used. For this purpose, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific one as long as it can control the current.

[0019] An example of a switch is a transistor (e.g., a bipolar transistor, a MOS transistor, transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky -Diode, MIM (Metal Insulator Metal) diode, M IS (Metal Insulator Semiconductor) Diode, These include transistors with diode connections, or logic circuits that combine these. An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has a mechanically movable electrode, and the movement of the electrode causes a conductive It operates by controlling conduction and non-conduction.

[0020] In addition, both N-channel and P-channel transistors are used as switches. Alternatively, a CMOS type switch may be used.

[0021] Note that a display element, a display device which is a device having a display element, a light-emitting element, and a A light-emitting device, which is a device that emits light, can have a variety of forms or elements. An example of a display element, a display device, a light-emitting element, or a light-emitting device is an electroluminescent (EL) device. EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (current transistors that emit light in response to light), electron emission elements, liquid crystal elements, electronic ink, electrophoretic elements , Grating Light Valve (GLV), Digital Micromirror Device (DMD) , carbon nanotubes, etc., due to electromagnetic effects, contrast, brightness, reflectance, Some display devices have a display medium whose transmittance changes. The display device using the EL element may be a piezoelectric or piezoelectric ceramic display. An example of a display device using electron-emitting devices is an EL display. For this purpose, a Field Emission Display (FED) or a Surface-emitting Display (SED) (onduction Electron-emitter Display) type flat type An example of a display device using liquid crystal elements is a liquid crystal display. (Transmissive LCD, Semi-transmissive LCD, Reflective LCD, Direct-view LCD LCDs (e.g., liquid crystal displays, projection LCDs, etc.) An example of a display device using such a device is electronic paper.

[0022] An example of a liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. The element can be composed of a pair of electrodes and a liquid crystal layer. The optical modulation of liquid crystals is achieved by applying an electric field (horizontal electric field, vertical electric field, or diagonal electric field) to the liquid crystal. Specifically, a liquid crystal element is a nematic liquid crystal element. tic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal Pyc liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDL C), Ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma address liquid Crystal (PALC), banana type LCD, TN (Twisted Nematic) mode, ST N (Super Twisted Nematic) mode, IPS (In-Plane -Switching) mode, FFS (Fringe Field Switchin) g) Mode, MVA (Multi-domain Vertical Alignmen) t) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Micro-cell mode, OCB (Opt ical Compensated Birefringence mode, ECB (E Controlled Birefringence) mode , FLC (Ferroelectric Liquid Crystal) mode, AF LC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Dispersed Liquid Crystal) mode Some of them use the guest-host mode, the Blue Phase mode, etc. However, the present invention is not limited to this, and various liquid crystal elements can be used.

[0023] Note that transistors having various structures can be used as the transistors. There is no limitation on the type of transistor. Examples of transistors include amorphous silicon, polycrystalline silicon, and Crystalline silicon, microcrystalline (also called microcrystalline, nanocrystalline, semi-amorphous) ) Thin film transistors (TFTs) that have non-single crystal semiconductor films, such as silicon can be used.

[0024] Examples of transistors include ZnO, a-InGaZnO, SiGe, and GaAs. , IZO (indium zinc oxide), ITO (indium tin oxide), SnO, TiO, Transistors containing compound semiconductors or oxide semiconductors such as AlZnSnO(AZTO) or a thin film transistor formed by thinning these compound semiconductors or oxide semiconductors. It is possible.

[0025] As an example of a transistor, a transistor formed by an ink-jet method or a printing method is used. A transistor or the like can be used.

[0026] An example of a transistor is a transistor having an organic semiconductor or a carbon nanotube. A resistor such as a resistor 14 can be used.

[0027] In addition, as the transistor, transistors having various other structures can be used. For example, transistors include MOS transistors, junction transistors, and bipolar transistors. A transistor or the like can be used.

[0028] An example of a transistor is a multi-gate transistor having two or more gate electrodes. A register can be used.

[0029] One example of a transistor is a structure in which gate electrodes are arranged above and below a channel. The transistors can be applied.

[0030] An example of a transistor is a transistor having a structure in which a gate electrode is disposed above a channel region. a structure in which the gate electrode is disposed under the channel region; a positive staggered structure; and a reverse staggered structure. , a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or A transistor having a structure in which channel regions are connected in series can be used.

[0031] In addition, as an example of a transistor, a source electrode or A transistor having an overlapping drain electrode structure can be used.

[0032] An example of a transistor is a lightly doped drain (LDD). A transistor having a structure in which a .DELTA..sub.3.sup.x region is provided can be applied.

[0033] In addition, the type of substrate on which the transistors are formed is not limited to a specific one, and various A transistor can be formed using a substrate such as a semiconductor substrate. Solid substrates, single crystal substrates (e.g. silicon substrates), SOI substrates, glass substrates, quartz substrates, Includes stick substrate, metal substrate, stainless steel substrate, stainless steel foil Substrates with tungsten foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated substrates Examples of the substrate include a glass substrate, a paper containing a fibrous material, or a base film. Examples of glass include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of flexible substrates include polyethylene terephthalate (PET), polystyrene (PS), and polystyrene (PS). Polyethylene naphthalate (PEN) and polyethersulfone (PES) are typical examples of The materials used for the adhesive include flexible plastics, acrylics, and other synthetic resins with flexibility. Examples of the polypropylene, polyester, vinyl, polyvinyl fluoride, or chlorine Examples of the base film include polyester, polyamide, polyimide, etc. In particular, semiconductor substrates, single crystal substrates, and SO By manufacturing transistors using I substrates, etc., the characteristics, size, shape, etc. This makes it possible to manufacture small-sized transistors with low variation in temperature and high current capability. When a circuit is constructed using such transistors, the power consumption of the circuit can be reduced or It is possible to achieve high integration of the circuits.

[0034] Note that a transistor is formed using a certain substrate and then transferred to another substrate. However, the transistor may be disposed on another substrate. In addition to the substrate on which the above-mentioned transistors can be formed, the substrates include paper substrates, cellophane substrates, and the like. substrates made of natural fibers (silk, cotton, hemp), synthetic fibers (nylon, Polyurethane, polyester) or regenerated fiber (acetate, cupra, rayon, regenerated The substrates used are made of synthetic polyester, leather, or rubber. This improves the electrical characteristics of the transistor and reduces the power consumption of the transistor. Furthermore, it is possible to improve the reliability, heat resistance, and lightness of devices using transistors. It is possible to achieve a reduction in weight or thickness.

[0035] All of the circuits required to realize a given function are mounted on the same substrate (e.g., glass It can be formed on a substrate, a plastic substrate, a single crystal substrate, an SOI substrate, etc. This reduces the number of components, thereby reducing costs, and reduces the number of connections to circuit components. This can improve reliability.

[0036] It is possible that all of the circuits required to realize a given function are not formed on the same substrate. In other words, part of the circuitry required to realize a given function is formed on a certain substrate. Another part of the circuitry required to realize a given function is formed on a different substrate. For example, some of the circuits required to realize a certain function can be made of glass. Another part of the circuitry required to realize a given function is formed on the single crystal substrate. It is possible to form the semiconductor device on a substrate (or an SOI substrate). The single crystal substrate on which another part of the circuit required for the semiconductor device is formed is called COG (Chip On Glass). The glass substrate is connected to the glass substrate by a solder joint, and the circuit is provided on the substrate. It is possible to place an IC chip on the TAB. (Tape Automated Bonding), COF (Chip On Fil) m), SMT (Surface Mount Technology), or printed circuit board It is possible to connect the pixel to the glass substrate using a plate or the like. Since the main body is formed on the same board as the main body, the number of parts is reduced, resulting in cost reduction and The number of connection points with the circuit components can be reduced, improving reliability. Circuits with high power consumption or circuits with high drive frequencies tend to consume a lot of power. Therefore, such circuits are often mounted on a substrate (such as a single crystal substrate) separate from the pixel section. By using this IC chip, the power consumption is reduced. This can prevent the increase in

[0037] In addition, the transistor may have at least three elements including a gate, a drain, and a source. The device may have a terminal between the drain region and the source region. The transistor has a channel region and allows a current to flow through the drain region, the channel region, and the source region. Here, the source and drain are determined by the structure or operating conditions of the transistor. It is difficult to determine which is the source or drain because Therefore, the region functioning as a source and the region functioning as a drain are called a source or In some cases, the drain is not called the source. In that case, for example, One is referred to as a first terminal, a first electrode, or a first region, and the other is referred to as a second terminal, a second electrode, or a The gate is sometimes referred to as the third terminal or the third electrode. There is.

[0038] A transistor has at least three terminals including a base, an emitter, and a collector. In this case, the element may be, for example, an element having one of an emitter and a collector. The first terminal, the first electrode, or the first region is referred to as the first terminal, the first electrode, or the first region, and the other of the emitter and the collector is referred to as the second terminal. It may be written as a terminal, a second electrode, or a second region. When a polarized transistor is used, the term "gate" can be replaced with "base." It is.

[0039] In addition, when it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits, etc.). , wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, a given connection relationship, For example, the present invention is not limited to the connection relationships shown in the drawings or text, and may be applied to connections other than those shown in the drawings or text. This also includes other things.

[0040] An example of a case where A and B are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more resistors (e.g., diodes) can be connected between A and B.

[0041] An example of a case where A and B are functionally connected is a case where a functional connection between A and B is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc., level shifters that change the potential level of signals, etc.), Pressure source, current source, switching circuit, amplifier circuit (circuit that can increase the signal amplitude or current amount, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, One or more memory circuits, control circuits, etc. can be connected between A and B. For example, even if there is another circuit between A and B, the signal output from A will be transmitted to B. If there is a transmission, A and B are considered to be functionally connected.

[0042] In addition, when it is explicitly stated that A and B are electrically connected, it means that A and B are electrically When A and B are directly connected (i.e., when another element or circuit is placed between A and B) A and B are functionally connected (i.e., there is no connection between A and B) and B is functionally connected (i.e., there is no connection between A and B). When A and B are connected directly ( In other words, A and B are connected without any other element or circuit between them. In other words, when it is explicitly stated that something is electrically connected, it should simply be "" is the same as if it were expressly stated that the

[0043] In addition, it is not necessary to explicitly say that B is formed on A, or that B is formed on A. In the case of describing, it is not limited to forming B directly on A. This also includes cases where there is no object between A and B, that is, cases where there is another object between A and B. A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.) (etc.).

[0044] Therefore, for example, it is not necessary to explicitly state that layer B is formed on layer A (or on layer A). In the case of a laminated structure, layer B may be formed directly on layer A, or layer A may be formed directly on layer B. Another layer (such as layer C or layer D) is formed adjacent to it, and layer B is formed directly on top of it. In addition, other layers (such as layers C and D) may be formed separately. It may be a layer or multiple layers.

[0045] Furthermore, the same applies when it is explicitly stated that B is formed above A. This is not limited to B being directly on A, but includes the case where there is another object between A and B. For example, if a layer B is formed above a layer A, In this case, layer B is formed directly on layer A, and layer B is formed directly on layer A. Another layer (such as layer C or layer D) is formed, and layer B is formed directly on top of it. In addition, the other layers (e.g., layers C and D) may be single layers. Alternatively, it may be multi-layered.

[0046] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that B is formed, this also includes the case where B is formed diagonally above. In addition, when B is formed under A, or when B is formed under A, The same applies to the case.

[0047] In addition, where something is explicitly stated as singular, it is preferable to use the singular. However, this is not limited to this, and plurals are also possible. It is preferable that the items described are plural. However, this is not limited to this. , it is also possible that it is singular.

[0048] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0049] Note that the diagram is a schematic representation of an ideal example, and is not limited to the shapes or values ​​shown in the diagram. For example, the drawings may show variations in shape due to manufacturing techniques, variations in shape due to errors, Variations in signals, voltages, or currents due to noise, or timing differences This can include variations in voltage or current, etc.

[0050] In addition, technical terms may be used for the purpose of describing a specific embodiment or example. However, one aspect of the invention should not be interpreted as being limited by technical terms.

[0051] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It is possible to use the term as meaning equivalent to the general meaning understood by a person skilled in the art. Any words defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0052] In addition, the terms first, second, third, etc., refer to various elements, members, regions, layers, or sections from one another. Therefore, the words first, second, third, etc. are used to distinguish between elements, parts, etc. The number of materials, regions, layers, areas, etc. is not limited. It is possible to replace "second" or "third" etc.

[0053] In addition, "up," "upward," "down," "downward," "sideways," "right," "left," Spatial arrangement such as "diagonally," "in the back," "in front," "inside," "outside," or "inside" The location phrases should be used to easily illustrate the relationship of one element or feature to another. However, it is not limited to this and is often used to indicate these spatial arrangements. The term can include other directions in addition to the direction depicted in the figure. For example, when explicitly shown as B above A, it is not limited to B being above A. Since the device in the figure can be inverted or rotated 180°, it is possible to include B being below A. Thus, the term "above" can include the direction of "below" in addition to the direction of "above". However, it is not limited to this, and since the device in the figure can be rotated in various directions, the term "above" can include other directions such as "horizontally", "to the right", "to the left", "diagonally", "towards the back", "towards the front", "inwards", "outwards" or "into" in addition to the directions of "above" and "below". That is, it can be interpreted appropriately according to the situation.

[0054] One aspect of the present invention has a first switch connected between a first wiring and a second wiring, and a second switch connected between the first wiring and the second wiring. In a first period, the first switch is turned on and the second switch is turned off. In a second period, the first switch is turned off and the second switch is turned off. In a third period, the first switch is turned off and the second switch is turned on. In a fourth period, the first switch is turned off and the second switch is turned off.

[0055] One aspect of the present invention has a first path and a second path between a first wiring and a second wiring. In a first period, the first wiring and the second wiring are in a conductive state via the first path. In a second period, the first wiring and the second wiring are in a non-conductive state. In a third period, ​​​​​In the fourth period, the first wiring and the second wiring are brought into a conductive state via the second path. In this case, the first wiring and the second wiring are in a non-conductive state.

[0056] One embodiment of the present invention includes a first transistor and a second transistor. A first terminal of the first transistor is connected to the first wiring, and a second terminal of the first transistor is connected to the second wiring. the gate of the first transistor is connected to a third wiring, and the gate of the second transistor is connected to a third wiring. A first terminal of the first transistor is connected to the first wiring, and a second terminal of the second transistor is connected to the second wiring. and the gate of the second transistor is connected to a fourth wiring.

[0057] One embodiment of the present invention includes a first transistor and a second transistor, In this case, the first transistor is turned on and the second transistor is turned off, and the second During the period, the first transistor is turned off and the second transistor is turned on. In the third period, the first transistor is turned off and the second transistor is turned on. In the fourth period, the first transistor is turned off and the second transistor is turned on. The start is what turns on.

[0058] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a first terminal of the first transistor is connected to a first wiring; The second terminal is connected to the second wiring, and the gate of the first transistor is connected to the third wiring. A first terminal of the second transistor is connected to the first wiring, and a second terminal of the second transistor is connected to the first wiring. The second terminal of the second transistor is connected to the second wiring, and the gate of the second transistor is connected to the fourth wiring. The first terminal of the third transistor is connected to the fifth wiring. The second terminal is connected to the second wiring, and the gate of the third transistor is connected to the sixth wiring. It is something that will be done. Effect of the Invention

[0059] According to one embodiment of the present invention, deterioration of the characteristics of a transistor can be suppressed. The embodiment allows the channel width of the transistor to be reduced. It is possible to suppress the deterioration of the characteristics of the transistor and to reduce the channel width. According to one embodiment of the present invention, a layout area can be reduced. Alternatively, one embodiment of the present invention can provide a display device with high resolution. Alternatively, one embodiment of the present invention can increase the yield. According to one embodiment of the present invention, manufacturing costs can be reduced. Alternatively, one embodiment of the present invention can reduce the current supply capability of an external circuit. Alternatively, one aspect of the present invention is to provide a method for manufacturing a semiconductor device having an external circuit. The size of the display device can be reduced. [Brief description of the drawings]

[0060] [Figure 1] 1A to 1C are an example of a circuit diagram of a semiconductor device according to a first embodiment and an example of a schematic diagram for explaining the operation of the semiconductor device; [Diagram 2] 1A to 1C are an example of a circuit diagram of a semiconductor device according to a first embodiment, an example of a schematic diagram for explaining an operation of the semiconductor device according to the first embodiment, and an example of a timing chart for explaining the operation of the semiconductor device according to the first embodiment. [Diagram 3] 5 is an example of a timing chart illustrating an operation of the semiconductor device in the first embodiment. [Figure 4] 11A and 11B are an example of a circuit diagram of a semiconductor device according to a second embodiment and an example of a timing chart illustrating the operation of the semiconductor device; [Diagram 5] 11A and 11B are an example of a schematic diagram for explaining an operation of the semiconductor device according to the second embodiment and an example of a circuit diagram of the semiconductor device according to the second embodiment. [Figure 6] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device in the second embodiment. [Figure 7] 11 is an example of a timing chart illustrating an operation of the semiconductor device in the second embodiment. [Figure 8] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 9] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is an example of a schematic diagram for explaining the operation of the semiconductor device in the second embodiment. [Figure 11] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 12] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a second embodiment. [Figure 13] 11A and 11B are an example of a circuit diagram of a semiconductor device according to a second embodiment and an example of a timing chart illustrating the operation of the semiconductor device; [Figure 14] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 15] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 16] FIG. 13 is an example of a schematic diagram for explaining the operation of the semiconductor device in the third embodiment. [Figure 17] FIG. 13 is an example of a schematic diagram for explaining the operation of the semiconductor device in the third embodiment. [Figure 18] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 19] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 20] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 21]FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 22] FIG. 11 is a circuit diagram of a semiconductor device according to a third embodiment. [Figure 23] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 24] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Diagram 25] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Figure 26] FIG. 13 is an example of a circuit diagram of a shift register according to the fourth embodiment. [Figure 27] 13 is an example of a timing chart illustrating the operation of a shift register in the fourth embodiment. [Figure 28] 13 is an example of a timing chart illustrating the operation of a shift register in the fourth embodiment. [Figure 29] FIG. 13 is an example of a circuit diagram of a shift register according to the fourth embodiment. [Diagram 30] FIG. 13 is an example of a block diagram of a display device according to a fifth embodiment. [Diagram 31] FIG. 13 is an example of a block diagram of a display device according to a fifth embodiment. [Diagram 32] 13A and 13B are an example of a circuit diagram of a signal line driver circuit in accordance with a sixth embodiment and an example of a timing chart for explaining the operation of the signal line driver circuit; [Diagram 33] 21A and 21B are an example of a circuit diagram of a pixel according to the seventh embodiment and an example of a timing chart for explaining the operation of the pixel; [Diagram 34] FIG. 23 is an example of a circuit diagram of a pixel according to the seventh embodiment. [Diagram 35] 13A and 13B are examples of a top view and a cross-sectional view of a display device in Embodiment 8. [Diagram 36] FIG. 13 is an example of a cross-sectional view of a transistor in an embodiment 9. [Figure 37] 11A to 11C are examples of cross-sectional views illustrating a manufacturing process of a transistor in Embodiment 10. [Figure 38] FIG. 23 is an example of a layout diagram of a semiconductor device in an eleventh embodiment. [Figure 39]12A to 12C are diagrams illustrating examples of electronic devices according to embodiment 12. [Diagram 40] 12A to 12C are diagrams illustrating examples of electronic devices according to embodiment 12. [Diagram 41] FIG. 11 is an example of a circuit diagram of a semiconductor device according to a third embodiment. [Diagram 42] FIG. 13 is a diagram showing a verification result of the semiconductor device in the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiment may be different from the embodiment. The present invention can be implemented in any manner without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the present invention may be modified in various ways. In addition, in the configuration described below, Reference numerals indicating similar objects are used in different drawings, and the same parts or similar functions are shown. A detailed description of the portion having the symbol will be omitted.

[0062] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in the embodiment, and / or one or more other embodiments The application, combination, or replacement of the contents (or part of the contents) described in the form etc. can be carried out.

[0063] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to the content that is stated or stated using the text in the specification.

[0064] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part of it) described in another embodiment of the present invention , more diagrams can be constructed.

[0065] In addition, in a drawing or text described in a certain embodiment, a part of it may be taken out and Therefore, the drawings or text describing a certain part may be used to constitute an embodiment of the invention. When a chapter is described, the contents of a part of the figure or text are also considered as an aspect of the invention. and is disclosed as an embodiment of the invention. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitors, etc.) elements, resistor elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, parts, substrates, The term "module," "device," "solid," "liquid," "gas," "method of operation," "method of manufacture," etc. may be used in singular or plural form. Drawings (sections, plan views, circuit diagrams, block diagrams, flow charts, process diagrams, perspective views, elevation views) Diagrams, layout diagrams, timing charts, structural diagrams, schematic diagrams, graphs, tables, optical path diagrams, vector diagrams, A part of a state diagram, waveform diagram, photograph, chemical formula, etc. or text is taken out and used as an invention. It is possible to constitute one aspect of the present invention.

[0066] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. As an example, various driving circuits such as a shift register, a gate driver, or a source driver Note that the semiconductor device of this embodiment mode can be used as a driver circuit or a circuit. It is possible to show.

[0067] First, a semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device includes a plurality of switches 11_1 to 11_2. 11_1 to 11_2 are connected between the wiring 111 and the wiring 112. However, this is not limited to this. The number of switches is not limited to one, and the semiconductor device may have three or more switches.

[0068] Next, signals or voltages input to or output from each wiring will be described.

[0069] As an example, a signal OUT is output from the wiring 111. For example, the signal O may be a signal having a first potential state and a second potential state. UT is a digital signal that has two states: H level (also called high level) and L level. In many cases, the wiring 111 is a signal, and can function as an output signal. In particular, the wiring 111 is arranged to extend to the pixel portion. The wiring 111 can be connected to a pixel. For example, in the case of a liquid crystal display device, the wiring 111 is connected to a pixel having a liquid crystal element. The voltage applied to the liquid crystal element can be set according to the potential of the liquid crystal display. The line 111 is connected to a transistor (e.g., a selection transistor or a switching transistor) included in the pixel. In this case, the signal OUT can be connected to the gate of the , as a selection signal, transfer signal, start signal, reset signal, gate signal, or scan signal Therefore, the wiring 111 can function as a gate signal line (gate line) or a running It is possible to function as a scanning line.

[0070] As an example, a signal CK1 is input to the wiring 112. For example, the signal CK 1 is often a digital signal that alternates between H and L levels, Therefore, the wiring 112 can function as a signal line or a clock signal. However, the present invention is not limited to this, and the wiring 111, Alternatively, various other signals, various voltages, or various currents may be input to the wiring 112. For example, a voltage is supplied to the wiring 111 or the wiring 112, and these wirings are connected to the power supply. It is capable of functioning as a source line.

[0071] As an example, the first potential state, that is, the potential of the L level signal is V1, and the second potential state is V2. The potential state, that is, the potential of the H level signal is V2. And, V2>V1. However, the present invention is not limited to this, and the potential of the L level signal can be lower than V1. It is possible to set the potential of the H-level signal higher than V2. It can be lower than V2 or higher than V3. For example, depending on the circuit configuration, In some cases, even if a signal is described as being at H level, its potential may be lower than V2, or V 2. Or, depending on the circuit configuration, it may be described as an L level signal. However, the potential may be lower than V1 or higher than V1.

[0072] In addition, "generally" refers to errors due to noise, errors due to process variations, and errors due to the manufacturing process of the element. This includes various errors such as errors due to variations in manufacturing process and / or measurement errors.

[0073] Generally speaking, voltage refers to the difference in electric potential between two points (also called the potential difference). Potential is the electrostatic energy (electrical potential) of a unit charge in a static electric field at a certain point. However, in an electronic circuit, even if there is only one point, The potential difference between the potential at a point and a reference potential (also called the reference potential) is sometimes used as the value. In addition, voltage and potential values ​​are often expressed in volts (V) in circuit diagrams, etc. Therefore, in the documents of this application (specification and claims), Unless otherwise specified, voltage may be used as a value even at only one point.

[0074] Note that the signal CK1 can be balanced or unbalanced. Equilibrium is the period during which the signal is at the H level and the period during which the signal is at the L level in one cycle. Non-equilibrium means that the periods when the blood is at the H level and the periods when the blood is at the L level are roughly equal. In this case, "different" does not include the case where the two are roughly the same. This shall not be tolerated.

[0075] Next, the functions of the switches 11_1 to 11_2 will be described. 2 has a function of controlling the electrical continuity between the wiring 111 and the wiring 112. As shown in FIG. 1, a plurality of paths 21_1 to 21_2 are provided between the wiring 111 and the wiring 112. Alternatively, the switches 11_1 and 11_2 may be connected to the power supply of the signal OUT. However, this is not limited to this, and the switch 11_1 to 11_2 can have various other functions.

[0076] In addition, the path between the wiring A (for example, the wiring 111) and the wiring B (for example, the wiring 112) is described as In this case, a switch can be connected between the wiring A and the wiring B. However, However, various elements (e.g., transistors, diodes, resistors, or capacitors, or various circuits (e.g., A buffer circuit, an inverter circuit, a shift register circuit, etc. can be connected. Therefore, for example, a resistor or a transistor may be connected in series or in parallel with the switch 11_1. Elements such as transistors can be connected.

[0077] Next, an example of the operation of the semiconductor device in FIG. 1A will be described with reference to a timing chart in FIG. However, the semiconductor device of FIG. 1A may be used in various types of The time can be controlled by timing.

[0078] In the timing chart of FIG. 2(A), the signal CK1, the state of the switch 11_1 (on or 11_1, the state of the switch 11_2 (on or off), and the waveform of the signal OUT. The timing chart in FIG. 2(A) has multiple periods, and each period is divided into multiple subperiods. For example, the timing chart in FIG. 2A includes a period T1 and a period T2. Period T1 includes a plurality of periods (hereinafter, a period is also referred to as a frame period). 1. There are several sub-periods, namely, period B1, period C1, period D1, and period E1 (hereinafter, the sub-periods The period T2 is also called one gate selection period, and the period T2 includes the periods A2, B2, and C2. , period D2, and period E2. However, the present invention is not limited to this, and the present invention can be applied to the following sub-periods. The timing chart of (A) may have a period other than the period T1 and the period T2. It is possible to omit one of the periods T1 and T2. It is possible to have various periods other than the periods A1 to E1, and the periods A1 to E1 It is possible to omit any of the periods. Alternatively, the period T2 may include various periods other than the periods A2 to E2. It is possible to have a period other than the period A2, and it is possible to omit any of the periods A2 to E2. be.

[0079] Note that, for example, the semiconductor device in FIG. 1A alternates between operation in the period T1 and operation in the period T2. However, the semiconductor device of FIG. 1A may be formed in various orders. It is possible to perform the operations in the periods T1 and T2.

[0080] Note that, as an example, in the period T1, in the semiconductor device in FIG. The operation in period D1 and the operation in period E1 are repeated until the switch is turned on. In the semiconductor device of FIG. 1A, when the switch 11_1 is turned on, The operation in the period B1, the operation in the period C1, and the operation in the period C2 are performed in this order. After that, the semiconductor device of FIG. 1A continues to operate in a period D1 until the switch 11_1 is turned on again. The operation in the period E1 and the operation in the period E2 are repeated. However, the present invention is not limited to this. In the semiconductor device of FIG. 1A, operations in the periods A1 to E1 can be performed in various orders. It is Noh.

[0081] Note that in the period T2, for example, in the semiconductor device in FIG. The operation in period D2 and the operation in period E2 are repeated until the power supply is turned on. In the semiconductor device of FIG. 1A, when the switch 11_2 is turned on, The operation in period B1, the operation in period B2, and the operation in period C2 are performed in this order. After that, the semiconductor device of FIG. 1A continues to operate in a period D2 until the switch 11_2 is turned on again. The operation in period E1 and the operation in period E2 are repeated. However, this is not limited to this. In the semiconductor device of FIG. 1A, operations in the periods A2 to E2 can be performed in various orders. It is possible.

[0082] The operation of the period T1 will be described. In the period T1, the switch 11_1 is turned on or off. Therefore, the switch 11_2 is turned off.

[0083] During period A1 of period T1, as shown in FIG. 2(D), switch 11_1 is turned on. Therefore, as shown in FIG. 2(E), the path 21_1 is conductive. The signal input to the wiring 112 is turned on, and the path 21_2 is turned off. (For example, a signal CK1 at a low level) is supplied to the wiring 111 via the switch 11_1. Therefore, the signal OUT becomes L level.

[0084] During the period B1 of the period T1, as shown in FIG. 2(D), the switch 11_1 remains on. Therefore, as shown in FIG. 2(E), the path The path 21_1 remains conductive, and the path 21_2 remains non-conductive. A signal input to the line 112 (for example, a signal CK1 at a high level) is input via the switch 11_1. This is then supplied to the wiring 111. As a result, the signal OUT becomes H level.

[0085] During a period C1 of the period T1, as shown in FIG. 2(B), the switch 11_1 is turned off. Therefore, as shown in FIG. 2C, the switch 11_2 remains off. 1 becomes non-conductive, and the path 21_2 remains non-conductive. Since the wiring 112 is in a non-conductive state, the signal (for example, the L level The signal CK1) is no longer supplied to the wiring 111.

[0086] In the period C1 of the period T1, the switch 11_1 is turned off at a timing when the signal This is often later than the timing when CK1 becomes L level. Therefore, switch 11_1 Before the switch is turned off, a signal (for example, a signal CK1 at a low level) input to the wiring 112 is In many cases, the signal OUT is supplied to the wiring 111 via the switch 11_1. However, the present invention is not limited to this. For example, when a signal or voltage V1 of an L level is supplied to the wiring 111, It is possible for the funds to be provided.

[0087] During the period D1 and the period E1 of the period T1, as shown in FIG. 2B, the switch 11_1 And the switch 11_2 remains off. Therefore, as shown in FIG. Therefore, the wiring 111 and the wiring 11_1 and the path 21_2 remain in a non-conductive state. 2 is not electrically connected to the wiring 111. Therefore, the signal OUT remains at the L level.

[0088] Next, the operation during the period T2 will be described. During the period T2, the switch 11_1 is turned off. , the switch 11_2 is turned on or off.

[0089] During a period A2 of the period T2, as shown in FIG. 2(F), the switch 11_1 is turned off. Therefore, as shown in FIG. 2(G), the path 21_1 is not Then, the signal input to the wiring 112 becomes (For example, the signal CK1 at the L level is supplied to the wiring 111 via the switch 11_2. Therefore, the signal OUT becomes L level.

[0090] During a period B2 of the period T2, as shown in FIG. 2(F), the switch 11_1 remains off. Therefore, as shown in FIG. 2(G), the path The path 21_1 remains in a non-conductive state, and the path 21_2 remains in a conductive state. A signal input to the line 112 (for example, a signal CK1 at a high level) is input via the switch 11_2. This is then supplied to the wiring 111. As a result, the signal OUT becomes H level.

[0091] During a period C2 of the period T2, as shown in FIG. 2(B), the switch 11_1 remains off. 2C, the switch 11_2 is turned off. 1 remains non-conductive, and the path 21_2 becomes non-conductive. Then, the wiring 111 and Since the wiring 112 is in a non-conductive state, the signal (for example, the L level The signal CK1) is no longer supplied to the wiring 111.

[0092] In the period C2 of the period T2, the switch 11_2 is turned off at a timing when the signal This is often later than the timing when CK1 becomes L level. Therefore, switch 11_2 Before the switch is turned off, a signal (for example, a signal CK1 at a low level) input to the wiring 112 is In many cases, the signal OUT is supplied to the wiring 111 via the switch 11_2. However, this is not limited to this, and the wiring 111 may be supplied with a signal or voltage V1 of L level. It is possible to do so.

[0093] In the period D2 and the period E2 of the period T2, as shown in FIG. 2B, the switch 11_1 And the switch 11_2 remains off. Therefore, as shown in FIG. Therefore, the wiring 111 and the wiring 11_1 and the path 21_2 remain in a non-conductive state. 2 is not electrically connected to the wiring 111. Therefore, the signal OUT remains at the L level.

[0094] As described above, by changing the period during which each switch is on, This can reduce the number of times the switch is turned on or shorten the time the switch is turned on. As a result, deterioration of the characteristics of the element or circuit used as the switch can be suppressed.

[0095] Alternatively, deterioration of the characteristics of an element or circuit used as a switch can be suppressed. For example, the wiring 111 may be a gate signal line or When the wiring 111 has a function as a scanning line or is connected to a pixel, the pixel is protected. The video signal stored in the OUT signal may be affected by the waveform of the OUT signal. If the potential of the transistor (e.g., a selection transistor) of the pixel does not rise to V2, The time that the switching transistor (or transistor) is on is shortened. This may cause insufficient writing of the video signal, resulting in a deterioration in display quality. When the fall time and rise time of T become longer, the pixels belonging to the selected row In this case, the video signal may be written to a pixel belonging to another row. The quality will be degraded. Or, if the fall time of the signal OUT varies, the pixel may not be held. The feedthrough effect on the video signal being displayed can vary. This results in uneven display.

[0096] However, the semiconductor device of the present embodiment is not limited to an element or circuit used as a switch. Therefore, the potential of the signal OUT is increased to V2. Therefore, the time during which the transistor in the pixel is turned on can be extended. This allows the video signal to be written to the pixels in sufficient time, improving display quality. Or, the fall time and rise time of the signal OUT can be shortened. Therefore, the pixels belonging to the selected row can receive the same video signal as the pixels belonging to another row. As a result, the display quality is improved. Or, the variation in the fall time of the signal OUT can be suppressed. This reduces the variation in the effect of feedthrough on the video signal held by the pixel. Therefore, display unevenness can be suppressed.

[0097] In the period T1, the period B1 is called the selection period, and the periods A1, C1, D1, and period E1 can be called a non-selection period. Similarly, in period T2, period B 2 is called a selection period, and periods A2, C2, D2, and E2 are called non-selection periods. It is possible.

[0098] In the period T1, the switch 11_1 is turned on (periods A1 and A2). The period in which the switch 11_1 is turned off (period C1, period D1, and period Similarly, in the period T2, the periods A2 and E3 can be called the second period. Periods C2, D2, and E2 are referred to as the fourth period. It is possible.

[0099] The periods T1 and T2 are called frame periods, and the periods A1 to E1 and A2 to E2 can be called a sub-period, or one gate selection period.

[0100] Note that a period or subperiod may be replaced with a step, process, or operation. It is.

[0101] In the period T1, the period D1 and the period E1 are arranged in sequence before the period A1. Similarly, in the period T2, before the period A2, the period D2 and the period E2 can be arranged in sequence. In such a case, the start of the period T1 The time from the time to the start time of period A1, and the time from the start time of period T2 to the start time of period A2 It is preferable that the time until the end of the period is approximately equal to the time until the end of the period, but this is not limited thereto.

[0102] As shown in FIG. 1C, the switch 11_1 and the switch 11_2 are turned on for the same period. In this case, as shown in FIG. 1(D), the path 21_1 and The path 21_1 and the path 21_2 are in a conductive state for the same period. , is supplied to the wiring 111 via the switch 11_1 and the switch 11_2. This is not limited to the above.

[0103] As shown in FIG. 1E, the semiconductor device includes switches 11_1 to 11_N (N is 2 or more). It is possible to have multiple switches, each of which is a natural number above. _N is connected between the wiring 111 and the wiring 112. The switches 11_1 to 11_N are It has the same function as the switch 11_1 or the switch 11_2. As shown in FIG. 1, there are paths 21_1 to 21_N between the wiring 111 and the wiring 112. There is.

[0104] In addition, when the semiconductor device has N switches, as shown in FIG. For example, in the timing chart of FIG. The intervals T1 to TN are arranged in order. However, this is not limited to this. In this embodiment, It is possible to arrange the periods T1 to TN in various orders. It is possible to omit any of the periods T1 to TN. For example, the period Ti (i is any one of 1 to N) is divided into periods Ai to Ei. Each of the periods Ai to Ei can have a plurality of sub-periods. In the same manner as in the periods A2 to E2, the switches 11_1 to 11_N (for example, For example, switches 11_1 to 11_i-1 and switches 11_i+1 to 11_N are turned off. Then, in periods Ai and Bi of period Ti, switch 11_i is turned on. , during periods Ci, Di, and Ei of period Ti, the switch 11_i is turned off.

[0105] Note that by making N large, the number of times each switch is turned on, or the number of times each The time that the switch is on can be reduced. However, if N is too large, the switch If the number of ,is too large, the circuit size will become large. Therefore, N is 6 or less. It is preferable that the number of the 3-way junction is 4 or less. It is more preferable that the number of the 3-way junction is 4 or less. is preferably 2, but is not limited to this.

[0106] As shown in FIG. 1G, the wiring 112 may be divided into a plurality of wirings 112A to 112B. The switch 11_1 can be divided into the wiring 111 and the wiring 112A. and the switch 11_1 is connected between the wiring 111 and the wiring 112B. The wirings 112A to 112B are connected to various other wirings or various elements. It is possible to do so.

[0107] As in FIG. 1G, the wiring 112 is divided into a plurality of wirings in FIG. It is possible.

[0108] (Embodiment 2) In this embodiment, an example of a semiconductor device will be described. In particular, the semiconductor device according to the first embodiment may include the semiconductor device according to the first embodiment. A configuration in which, for example, a transistor is used as a switch of the device will be described. However, the present invention is not limited to this, and various elements or circuits may be used as the switch. It is possible to do so. The contents described in the first embodiment will not be described here. The contents of this embodiment mode can be appropriately combined with the contents of Embodiment Mode 1. do.

[0109] First, the semiconductor device of this embodiment will be described with reference to FIG. The semiconductor device includes a circuit 100. The circuit 100 has a structure described in Embodiment 1. In this case, the structure is the same as that in the case where a transistor is used as a switch. A transistor 101_1 is used as the switch 11_1 of the switch 11_ 2. The transistor 101_2 is used as the transistor The transistor 101_1 has a function similar to that of the switch 11_1, and the transistor 101_2 has a function similar to that of the switch 11_1. However, the present invention is not limited to this and may have the same functions as those described in the first embodiment. In the configuration, a transistor can be used as the switch. A CMOS switch or the like can be used as the gate driver.

[0110] Note that the transistors 101_1 and 101_2 are N-channel transistors. In an N-channel transistor, the potential difference (Vgs) between the gate and source is When the threshold voltage (Vth) is exceeded, the transistor is turned on. However, the present invention is not limited to this. The transistor 101_1 and / or the transistor 101_2 are P-channel type. It is possible to make a P-channel transistor operate with a gate-source voltage difference (Vg s) falls below the threshold voltage (Vth).

[0111] Next, the connection relationship of the semiconductor device in FIG. The first terminal of the transistor 101_1 is connected to the wiring 112, and the second terminal of the transistor 101_1 is connected to the wiring 111. A first terminal of the transistor 101_2 is connected to a wiring 112. A second terminal of the first terminal 101_2 is connected to the wiring 111.

[0112] Note that a connection point between the gate of the transistor 101_1 and the circuit 10 is indicated as a node n1. The connection point between the gate of the transistor 101_2 and the circuit 10 is indicated as a node n2. The node n1 and the node n2 can be called wiring.

[0113] Next, functions of the transistor 101_1 and the transistor 101_2 will be described. do.

[0114] The transistor 101_1 changes the potential of the wiring 112 to the potential of the wiring 111 in response to the potential of the node n1. For example, the wiring 112 has a function of controlling the timing of supplying a voltage (for example, a voltage When a voltage V1 or V2 is supplied, the transistor 101_1 is connected to the potential of the node n1. A function of controlling the timing of supplying the voltage supplied to the wiring 112 to the wiring 111 in response to the As another example, when a signal (for example, a signal CK1) is input to the wiring 112, The transistor 101_1 transmits a signal input to the wiring 112 in response to the potential of the node n1. In this case, the signal CK1 has a function of controlling the timing of supplying the signal to the line 111. When the signal CK1 is at the L level, the transistor 101_1 supplies the signal CK1 at the L level to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing of supplying a signal OU T goes to the L level. Then, the transistor 101_1 supplies a signal CK1 of H level to the wiring 111. Alternatively, the transistor 101_1 has a function of controlling the timing when the signal OUT is at the H level. At this time, node n1 is in a floating state. In this case, the transistor 101_1 can be connected to the potential of the wiring 111. The transistor 101 has a function of increasing the potential of the node n1 in response to a rise in the potential of the transistor 101. The transistor 101_1 has a function of performing a bootstrap operation. The potential state of the signal OUT is set by turning it on or off according to the signal input to the port. It has the function of controlling whether or not to set the

[0115] The transistor 101_2 changes the potential of the wiring 112 to the potential of the wiring 111 in response to the potential of the node n2. For example, the wiring 112 has a function of controlling the timing of supplying a voltage (for example, a voltage When a voltage V1 or a voltage V2 is supplied, the transistor 101_2 is connected to the potential of the node n2. A function of controlling the timing of supplying the voltage supplied to the wiring 112 to the wiring 111 in response to the As another example, when a signal (for example, a signal CK1) is input to the wiring 112, The transistor 101_2 transmits a signal input to the wiring 112 in response to the potential of the node n2. In this case, the signal CK1 has a function of controlling the timing of supplying the signal to the line 111. When the signal CK1 is at the L level, the transistor 101_2 supplies the signal CK1 at the L level to the wiring 111. Alternatively, the transistor 101_2 has a function of controlling the timing of supplying the signal OU T goes to the L level. Then, the transistor 101_2 supplies the signal CK1 of H level to the wiring 111. Alternatively, the transistor 101_2 has a function of controlling the switching when the signal OUT is at the H level. At this time, node n2 is in a floating state. In this case, the transistor 101_2 may be connected to the potential of the wiring 111. The transistor 101 has a function of increasing the potential of the node n2 in response to a rise in the potential of the transistor 101. The transistor 101_1 has a function of performing a bootstrap operation. The potential state of the signal OUT is set by turning it on or off according to the signal input to the port. It has the function of controlling whether or not to set the

[0116] As shown in FIG. 4B, the semiconductor device of this embodiment mode includes a circuit 10. For example, the circuit 10 includes a wiring 113, a wiring 114, a wiring 115_1, a wiring 11 5_2, wiring 116, wiring 117, the gate of transistor 101_1, transistor 10 1_2 and / or the wiring 111. However, the present invention is not limited to this. Depending on the configuration of circuit 10, circuit 10 may be connected to other wires or other nodes. Alternatively, the circuit 10 includes the wiring 113, the wiring 114, the wiring 115_1, and the wiring 115_2. , a wiring 116, a wiring 117, a gate of the transistor 101_1, a gate of the transistor 101_2 It is possible that the gate of the transistor 111 is not connected to the wiring 111 .

[0117] Circuit 10 often includes one or more transistors. The polarity of the N-channel transistor is often the same as that of the transistors 101_1 and 101_2. However, the circuit 10 is not limited to this, and may be a P-channel transistor. Alternatively, the circuit 10 may include an N-channel transistor and a P-channel transistor. In other words, the circuit 10 may be a CMOS circuit. It is possible that it is a path.

[0118] As in the first embodiment, the signal OUT is output from the wiring 111. As in the first embodiment, the signal CK1 is input to the CK 12. When the signal CK2 is written as 2, the signal CK2 is an inverted signal of the signal CK1, or the phase is 1 phase from the signal CK1. In many cases, the signal is shifted by 80 degrees. The wiring 113 is supplied with a voltage V2. Voltage V2 can function as a power supply voltage, a reference voltage, or a positive power supply voltage. Therefore, the wiring 113 can function as a power supply line. The signal SP is input. The signal SP can function as a start signal. Therefore, the wiring 114 can function as a signal line. In the configuration, the wiring 114 is connected to the wiring 11 of the semiconductor device in another stage (for example, the previous stage). When connected to 1, the signal SP is a selection signal, a transfer signal, a start signal, a reset signal, The wiring 114 can function as a gate signal or a scanning signal. The wiring 115_1 can function as a gate signal line or a scanning line. The signal SEL1 is input every certain period (for example, every frame period). ) by repeating H and L levels as a clock signal, selection signal, or control signal. Therefore, the wiring 115_1 can function as a signal line. It is assumed that a signal SEL2 is input to the wiring 115_2. The signal SEL2 is , an inverted signal of signal SEL1, or a signal whose phase is shifted by 180° from signal SEL1. Therefore, the wiring 115_2 can function as a signal line. A signal RE is input to the input terminal 6. The signal RE functions as a reset signal. Therefore, the wiring 116 can function as a signal line. In this case, the wiring 116 is connected to another stage (for example, the next stage). ) is connected to the wiring 111 of the semiconductor device, the signal RE is a selection signal, a transfer signal, It can function as a start signal, a reset signal, a gate signal, or a scan signal. In this case, the wiring 116 can function as a gate signal line or a scanning line. It is assumed that a voltage V1 is supplied to the wiring 117. The voltage V1 is a power supply voltage, a reference voltage The line 11 can function as a voltage, a ground voltage, or a negative power supply voltage. The wiring 111 can function as a power supply line. , wiring 112, wiring 113, wiring 114, wiring 115_1, wiring 115_2, wiring 116 Various signals, various voltages, or various currents can be supplied to the wiring 117. It is.

[0119] Note that the signal CK1 or the signal CK2 can be balanced or unbalanced. Similarly, the signal SEL1 or the signal SEL2 can be a balanced It is possible for the state to be in equilibrium, or it is possible for the state to be non-equilibrium (also called disequilibrium).

[0120] The circuit 10 includes a voltage V1, a signal CK2, a signal SP, a signal SEL1, a signal SEL2, and a signal RE. , the potential of node n1, the potential of node n2, and / or the signal OUT. , the timing of supplying a signal or a voltage to the node n2 and / or the wiring 111. Alternatively, the circuit 10 has a function of supplying a voltage V1, a signal CK2, a signal SP, a signal SEL1, , signal SEL2, signal RE, voltage V1, the potential of node n1, the potential of node n2, and / or In response to the signal OUT, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring 11 For example, the circuit 10 has a function of controlling the potential of the H-level signal or voltage V2. The circuit 10 has a function of supplying a signal to the node n1 and / or the node n2. A signal or voltage V1 of the bell is supplied to the node n1, the node n2, and / or the wiring 111. Alternatively, the circuit 10 may output a signal or a voltage to the node n1 and / or the node Alternatively, the circuit 10 has a function of not supplying a potential to the node n1 and / or The circuit 10 has a function of increasing the potential of the node n1, The potential of the node n2 and / or the potential of the wiring 111 is reduced or maintained. The circuit 10 has a function of putting the node n1 and / or the node n2 in a floating state. However, the circuit 10 may have a variety of other functions, without being limited thereto. However, circuit 10 need not have all of the above functions.

[0121] Next, an example of the operation of this embodiment will be described. Here, as an example, The operation of the semiconductor device will be described with reference to the timing chart of FIG. The timing chart of FIG. 4(C) will be described with reference to FIG. 4(E) and FIG. 6(A) to FIG. 6(E). The port includes signals CK1, CK2, SP, RE, and the potential of node n1 (Va1). , the potential of the node n2 (Va2), and the signal OUT. The explanation of the parts common to the chart will be omitted. The operation can be applied to the contents described in this embodiment or the contents described in other embodiments. It is Noh.

[0122] First, in a period A1, as shown in FIG. 5A, the signal SP goes to H level, and the signal S EL1 goes to H level and signal SEL2 goes to L level. The circuit 10 supplies the signal SP or the voltage V2 of the line to the node n1. The potential of the node n1 is then increased to V1+Vth101_1 (Vth10 1_1: Threshold voltage of transistor 101_1) + Vx, transistor 1 At this time, Vx is greater than 0. Therefore, the wiring 112 and the wiring The line 111 is in a conductive state via the transistor 101_1, so that the L-level signal C K1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_1. As a result, the signal OUT goes to the L level. After that, the potential of the node n1 further rises. Therefore, the supply of voltage or signal from the circuit 10 to the node n1 is stopped, and the circuit 10 and the node As a result, node n1 is in a floating state, and the voltage of node n1 is The voltage is maintained at V1+Vth101_1+Vx.

[0123] In addition, during the period A1, the circuit 10 supplies an L-level signal or a voltage V2 to the node n2. It is possible to provide

[0124] Note that in the period A1, the circuit 10 supplies an L-level signal or a voltage V2 to the wiring 111. It is possible to provide

[0125] Next, in a period B1, as shown in FIG. 5B, the signal SP goes to the L level, and the signal S EL1 remains at the H level, and the signal SEL2 remains at the L level. 0 remains without supplying any voltage or signal to node n1. Therefore, node n1 is It remains in a floating state, and the potential of the node n1 remains V1 + Vth101_1 + Vx. In other words, the transistor 101_1 remains on, so that the wiring 112 and the wiring 111 At this time, the signal CK1 is in a low level. Since the potential of the wiring 111 rises from the low level to the H level, the potential of the node Since n1 remains floating, the potential of the node n1 is It rises due to the parasitic capacitance between the first terminal and the second terminal. This is known as bootstrap operation. In this way, the potential of the node n1 rises to V2+Vth101_1+Vx. In this way, the potential of the wiring 111 can be increased to V2. T becomes H level.

[0126] In the period B1, the circuit 10 supplies an L-level signal or a voltage V2 to the node n2. It is possible to provide

[0127] In addition, during the period B1, the circuit 10 does not supply a signal or a voltage to the wiring 111. It is possible.

[0128] Next, during a period C1, as shown in FIG. 5C, the signal RE goes to H level. The circuit 10 outputs a low-level signal or voltage V1 to the node n1, the node n2, and / or the Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring The potential of the transistor 101_1 and the transistor 101_2 is V1. Since the signal 1_2 is turned off, the wiring 112 and the wiring 111 are not electrically connected to each other. OUT becomes L level.

[0129] In the period C1, the potential of the node n1 decreases to the L level. It is possible to set the timing when CK1 drops to L level earlier. Then, as shown in FIG. 5(E), the signal CK1 at L level is output from the wiring 112 to the transistor. The potential can be supplied to the wiring 111 through the transistor 101_1. The channel width of 1_1 is, for example, a transistor other than the transistor 101_1. In some cases, the channel width of the wiring 111 is often larger than that of other transistors. In other words, the fall time of the signal OUT can be shortened. Therefore, in order to reduce the potential of the wiring 111, the circuit 10 needs to output an L-level signal or When the voltage V1 is supplied to the wiring 111, and when the signal CK1 at the L level is supplied to the transistor When the signal is supplied to the wiring 111 through the first input 101_1, or when the signal is supplied to the circuit 10 through the first input 101_2, the signal is at an L level. A voltage V1 is supplied to the wiring 111, and a signal CK1 of L level is supplied to the transistor from the wiring 112. There are three patterns: one in which the power is supplied to the wiring 111 via the power supply 101_1; and one in which the power is supplied to the wiring 111 via the power supply 101_2.

[0130] Next, in periods D1 and E1, as shown in FIG. 5(D), the circuit 10 outputs a voltage V A signal of 1 or L level is supplied to the node n1, the node n2, and / or the wiring 111. Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring 111 are V1 Therefore, the transistor 101_1 and the transistor 101_2 remain off. Therefore, the wiring 112 and the wiring 111 remain in a non-conductive state. UT remains at the L level.

[0131] Next, in a period A2, as shown in FIG. 6A, the signal SP goes to H level, and the signal S EL1 goes to the L level, and the signal SEL2 goes to the H level. The circuit 10 supplies the signal SP or voltage V2 of the line to the node n2. The potential of the node n2 is then increased to V1+Vth101_2 (Vth10 1_2: The threshold voltage of transistor 101_2) + Vx, At this time, Vx is greater than 0. Therefore, the wiring 112 and The line 111 is in a conductive state via the transistor 101_2, so that the L-level signal C K1 is supplied from the wiring 112 to the wiring 111 via the transistor 101_2. As a result, the signal OUT goes low. After that, the potential of the node n2 further rises. Therefore, the supply of voltage or signal from the circuit 10 to the node n2 is stopped, and the circuit 10 and the node As a result, node n2 is in a floating state, and the voltage of node n2 is The voltage is maintained at V1+Vth101_2+Vx.

[0132] In addition, during the period A2, the circuit 10 supplies an L-level signal or a voltage V2 to the node n1. It is possible to provide

[0133] Note that in the period A2, the circuit 10 supplies an L-level signal or a voltage V2 to the wiring 111. It is possible to provide

[0134] Next, in a period B2, as shown in FIG. 6B, the signal SP goes to the L level, and the signal S The signal EL1 remains at the L level, and the signal SEL2 remains at the H level. 0 remains without supplying any voltage or signal to node n2. Therefore, node n2 is It remains in a floating state, and the potential of node n2 remains V1 + Vth101_2 + Vx. In other words, the transistor 101_2 remains on, so that the wiring 112 and the wiring 111 At this time, the signal CK1 is in a low level. Since the potential of the wiring 111 rises from the low level to the H level, the potential of the node Since n2 remains floating, the potential of the node n2 is It rises due to the parasitic capacitance between the first terminal and the second terminal. This is known as bootstrap operation. In this way, the potential of the node n2 rises to V2+Vth101_2+Vx. Thus, the potential of the wiring 111 can rise to V2. T becomes H level.

[0135] In addition, in the period B2, the circuit 10 supplies an L-level signal or a voltage V2 to the node n1. It is possible to provide

[0136] Note that the circuit 10 does not supply a signal or a voltage to the wiring 111 during the period B2. It is possible.

[0137] Next, during a period C2, the signal RE goes to H level as shown in FIG. The circuit 10 outputs a low-level signal or voltage V2 to the node n1, the node n2, and / or the Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring The potential of the transistor 101_1 and the transistor 101_2 is V1. Since the signal 1_2 is turned off, the wiring 112 and the wiring 111 are not electrically connected to each other. OUT becomes L level.

[0138] In the period C2, the signal CK1 becomes higher than the timing at which the potential of the node n2 decreases. It is possible to set the timing for the signal to decrease to the L level earlier. As shown in FIG. 6E, the signal CK1 at the L level is supplied from the wiring 112 to the transistor 10. The signal can be supplied to the wiring 111 through the transistor 101_2. For example, when other transistors are included, the channel width is set to be smaller than the channel width of the other transistors. Since the potential of the wiring 111 is often large, the potential of the wiring 111 can be quickly reduced. The fall time of OUT can be shortened. Therefore, the potential of the wiring 111 is reduced. In order to achieve this, for example, when the circuit 10 supplies a signal or voltage V1 of L level to the wiring 111, , the L-level signal CK1 is input from the wiring 112 to the wiring 111 via the transistor 101_2. When the signal V1 is supplied to the wiring 111, or when the circuit 10 supplies a signal or voltage V1 of L level to the wiring 111, Furthermore, the signal CK1 at the L level is input from the wiring 112 to the wiring 111 via the transistor 101_2. In some cases, they are supplied to

[0139] Next, in periods D2 and E2, as shown in FIG. 6(D), the circuit 10 supplies a voltage V A signal of 1 or L level is supplied to the node n1, the node n2, and / or the wiring 111. Then, the potential of the node n1, the potential of the node n2, and / or the potential of the wiring 111 are V1 Therefore, the transistor 101_1 and the transistor 101_2 remain off. Therefore, the wiring 112 and the wiring 111 remain in a non-conductive state. UT remains at the L level.

[0140] As described above, in the period T1, the transistor 101_2 is turned off, and in the period T2, Since the transistor 101_1 is turned off, the transistor 101_1 and the transistor The number of times each of the transistors 101_1 and 101_2 is turned on, or the number of times each of the transistors 101_1 and 101_2 is turned on Therefore, the time that each of the transistors 101_2 and 101_3 is turned on is reduced. This can suppress deterioration of the characteristics of the transistors 01_1 and 101_2.

[0141] As described above, the semiconductor device of the present embodiment can suppress the deterioration of the transistor characteristics. In addition, the potential of the H level of the signal OUT can be raised to V2, This allows the transistors in the pixel to remain on for a longer period of time. This allows the video signal to be written in a short time, improving the display quality. Or, the fall time and rise time of the signal OUT can be shortened. Therefore, the video signal for the pixels in another row is written to the pixels in the selected row. As a result, the display quality can be improved. Since the variation in the fall time of the signal OUT can be suppressed, the pixel can hold This reduces the variation in the effect of feedthrough on the video signal being displayed. It is possible to suppress unevenness.

[0142] In the semiconductor device of this embodiment, the polarity of all the transistors is set to an N-channel type or Therefore, the number of steps can be reduced compared to CMOS circuits. In particular, it is possible to reduce the number of pixels, improve the yield, improve the reliability, or reduce the cost. When all transistors, including the junctions, are N-channel, the semiconductor layer of the transistor and For example, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. However, transistors using these semiconductors are prone to degradation. However, the semiconductor device of this embodiment can suppress the deterioration of the transistor. .

[0143] Alternatively, the transistor may be designed to operate so that the semiconductor device can function even if the transistor characteristics are deteriorated. Therefore, it is not necessary to increase the channel width of the transistor. This is because the semiconductor device of the present embodiment can suppress the deterioration of the transistor. Because it can be controlled.

[0144] The circuit 10 includes periods C1, D1, E1, A2, B2, C2, and During the period D2 and / or E2, a signal or voltage V1 of the L level is provided to the node n1. It is possible to supply a voltage or signal to node n1, or not to supply a voltage or signal to node n1. However, this is not limited to this.

[0145] The circuit 10 includes periods A1, B1, C1, D1, E1, C2, and During the period D2 and / or E2, a signal or voltage V1 of the L level is provided to the node n2. It is possible to supply a voltage or signal to node n2, or not to supply a voltage or signal to node n2. However, this is not limited to this.

[0146] The circuit 10 includes periods A1, C1, D1, E1, A2, C2, and During the period D2 and / or the period E2, a signal or voltage V1 of the L level is supplied to the wiring 111. It is possible to supply a voltage or a signal to the wiring 111, or not to supply a voltage or a signal to the wiring 111. However, this is not limited to this.

[0147] Note that the signals CK1 and CK2 can be unbalanced. For example, if the period during which the signal is at the H level is shorter than the period during which the signal is at the L level in one cycle, In this way, in the period C1 or the period C2, Since the L-level signal CK1 is supplied to the wiring 111, the falling edge time of the signal OUT is Alternatively, when the wiring 111 is arranged to extend to the pixel portion, the length of the wiring 111 to the pixel portion can be shortened. It is possible to prevent unauthorized video signals from being written. However, this is not limited to this. During the period, it is possible for the period to be at the H level to be longer than the period to be at the L level.

[0148] Note that a polyphase clock signal can be used in the semiconductor device of this embodiment mode. For example, if n (n is a natural number) is used, then a clock signal with n+1 phases has a period of 1 A clock signal is a set of n+1 clock signals, each of which is shifted by n+1 periods. Any two of the signals can be input to the wiring 112 and the wiring 113, respectively. 7(B) shows an example of a timing diagram for a semiconductor device using a three-phase clock signal. Charts include, but are not limited to:

[0149] In addition, the larger n is, the smaller the clock frequency is, which reduces power consumption. However, if n is too large, the number of signals increases, which increases the layout area. Or the external circuit may become large. Therefore, n<8 is recommended. It is preferable that n is less than 6. It is even more preferable that n is 4. Alternatively, n=3 is preferred, but is not limited thereto.

[0150] Since the transistors 101_1 and 101_2 have the same function, The channel width of the transistor 101_1 and the channel width of the transistor 101_2 are It is preferable that the transistor sizes are roughly equal. By this, the current supply capabilities of the transistors can be made roughly equal. The degree of deterioration of the transistors can be made roughly equal. Even if the capacitor is switched, the waveform of the signal OUT can be made roughly the same. , but is not limited to this, the channel width of the transistor 101_1 and the channel width of the transistor 101_2 The channel width of the first channel may be different from that of the second channel.

[0151] When describing the channel width of a transistor, this is the W / L (W: channel This can be expressed as the ratio of the channel width to the channel length (L:channel width, L:channel length).

[0152] The transistors 101_1 and 101_2 are turned on during the same period. For example, in the period B1 or the period B2, the transistor 101_ When transistor 101_1 and transistor 101_2 are turned on, only one of the transistors is turned on. Therefore, the potential of the wiring 111 can be increased more quickly than when the signal OU The rise time of T can be shortened.

[0153] As shown in FIG. 8A, the wiring 112 may be divided into a plurality of wirings 112A to 112B. The first terminal of the transistor 101_1 can be connected to the wiring 112. A, and a first terminal of the transistor 101_2 can be connected to the wiring 112B. In addition, the wirings 112A to 112B can be connected to other wirings or nodes. It is possible.

[0154] As in FIG. 8A, in FIGS. 4A to 4B, the wiring 112 is divided into a plurality of wirings ( For example, it is possible to divide the wiring into wirings 112A to 112B.

[0155] As shown in FIG. 8B, a capacitance is provided between the gate and the second terminal of the transistor 101_1. A capacitance element 121_1 is connected between the gate of the transistor 101_2 and the second terminal of the transistor 101_2. It is possible to connect element 121_2. By doing so, the bootstrap During operation, the potential of the node n1 or the potential of the node n2 tends to rise. Since the Vgs of the transistors 101_1 and 101_2 can be increased, Therefore, the channel width of these transistors can be reduced. The fall time or rise time can be shortened, but is not limited to this. It is possible to omit either the capacitor 121_1 or the capacitor 121_2. The capacitance element is connected to the gate of the transistor (node ​​n1, node n2) and the second terminal (wire 1). 12) can be connected between the capacitor and the MIS capacitor. It is possible to use.

[0156] Note that the material of one electrode of each of the capacitors 121_1 and 121_2 is, for example, a transistor. The gate of the transistor 101_1 and the gate of the transistor 101_2 are preferably made of the same material. The other electrodes of the capacitors 121_1 and 121_2 are preferably made of a material similar to that of a transistor. The material is the same as that of the source or drain of the transistor 101_1 and the transistor 101_2. This is preferable. By doing so, the layout area can be reduced. However, the capacitance value of the capacitor 121_1 can be increased. As the materials of one electrode and the other electrode of the capacitor 121_2, various It is possible to use materials.

[0157] The capacitance value of the capacitor 121_1 and the capacitance value of the capacitor 121_2 are approximately equal. Alternatively, it is preferable that the area where one electrode and the other electrode of the capacitor 121_1 overlap with each other is The area where one electrode of the capacitor 121_2 overlaps with the other electrode is approximately equal to the area where the other electrode of the capacitor 121_2 overlaps with the other electrode of the capacitor 121_2. By doing so, even if the transistors are switched, the transistor It is possible to make the Vgs of the transistor 101_1 and the Vgs of the transistor 101_2 approximately equal. Therefore, the waveform of the signal OUT can be made roughly the same. However, this is not limited to this. The capacitance value of the capacitance element 121_1 and the capacitance value of the capacitance element 121_2 are different from each other. Alternatively, the area where one electrode and the other electrode of the capacitor 121_1 overlap with each other and The area where one electrode and the other electrode of the capacitor 121_2 overlap may be different. be.

[0158] As in FIG. 8(B), the transistors in FIGS. 4(A) to 4(B) and FIG. A capacitance element 121_1 can be connected between the gate and the second terminal of the transistor 101_1. Alternatively, a capacitor 121_2 is provided between the gate and the second terminal of the transistor 101_2. It is possible to connect.

[0159] As shown in FIG. 8C, the circuit 100 includes transistors 101_1 to 101_N. It is possible to have a plurality of transistors such as the transistors 101_1 to 101_ The first terminals of the transistors 101_1 to 101_N are connected to the wiring 112, and the second terminals of the transistors 101_1 to 101_N are connected to the wiring 112. The terminal is connected to the wiring 111. The gates of the transistors 101_1 to 101_N are nodes n1 to nN, respectively. The configuration of FIG. 8(C) is the same as that of the first embodiment. This corresponds to a configuration in which a transistor is used as a switch. 1_1 to 101_N have the same functions as the switches 11_1 to 11_N.

[0160] Note that the larger N, the more times each transistor is turned on, or The time that the transistor is on is shortened, so the deterioration of the transistor characteristics can be suppressed. However, if N is too large, the number of transistors increases, and the circuit scale becomes large. Therefore, it is preferable that N<6. More preferably, N<4. More preferably, N=3 or N=2.

[0161] As in FIG. 8(C), in FIGS. 4(A) to 4(B) and 8(A) to 8(B), The circuit 100 includes a plurality of transistors 101_1 to 101_N. In particular, in FIG. 8A, the circuit 100 includes transistors 101_1 to When a plurality of transistors 101_N are included, the wiring 112 is divided into N wirings. In particular, in FIG. 8B, the circuit 100 includes transistors 101_1 to In the case where a plurality of transistors, 101_1 to 101_N, are provided, A capacitance element is provided between the gate of N and the second terminal of each of the transistors 101_1 to 101_N. It is possible to connect

[0162] As shown in FIG. 8D, the transistor 101_1 is connected to one terminal (hereinafter, referred to as the positive terminal). The negative terminal of the positive terminal of the positive electrode 111 is connected to the node n1, and the negative terminal of the negative electrode 111 is connected to the wiring 111. It is possible to replace the diode 101a_1 connected to the transistor 101_2, one terminal (hereinafter also referred to as the positive terminal) is connected to the node n2, and the other terminal (hereinafter, also referred to as the negative electrode) is replaced with the diode 101a_2 connected to the wiring 111. However, the present invention is not limited to this. As shown in FIG. 8E, The first terminal of the transistor 101_1 is connected to the node n1. Similarly, the transistor 101_2 can be configured as a diode. By connecting the first terminal to the node n2, the transistor 101_2 is in diode connection. It is possible to have a continuous configuration.

[0163] As in Figs. 8(D) to (E), Figs. 4(A) to (B) and Figs. 8(A) to (C) Even if the transistor is a diode, it is possible to replace the transistor. It is possible to configure the inputs in a diode-connected configuration.

[0164] As shown in FIG. 8(F), the output signal can be divided into two. Additionally, the semiconductor device may include a circuit 120. The circuit 120 may include a transistor The circuit 120 includes a plurality of transistors 122_1 to 122_2. The transistors 122_1 and 122_2 each have the same function as the transistor 1. The first terminal of the transistor 122_1 is a wiring A first terminal of the transistor 122_1 is connected to the line 112, and a second terminal of the transistor 122_2 is connected to the line 211. The gate of the transistor 122_1 is connected to the node n1. The first terminal of the transistor 122_2 is connected to the wiring 112, and the second terminal of the transistor 122_2 is connected to the wiring 211. and the gate of the transistor 122_2 is connected to the node n2. The transistors 101_1 and 122_1 are controlled at the same timing. The transistor 101_2 and the transistor 122_2 are controlled at the same timing. Therefore, the signal output from the wiring 211 has a timing approximately equal to that of the signal OUT. Timing will result in either H or L level.

[0165] When the signal output from the wiring 111 functions as a gate signal or a selection signal, The signal output from the wiring 211 is a transfer signal, a reset signal, a gate signal, etc. In such a case, the load of the wiring 111 is the load of the wiring 211. Since the channel width of the transistor 101_1 is often larger than the load, The channel width of the transistor 102 is preferably larger than that of the transistor 122_1. The channel width of the transistor 122_2 is preferably larger than the channel width of the transistor 122_2. However, this is not limited to this.

[0166] As in FIG. 8(F), in FIGS. 4(A) to 4(B) and 8(A) to 8(E), The semiconductor device can split the output signal into two by including the circuit 120. The circuit 120 includes a plurality of transistors 122_1 to 122_2. In particular, in FIG. 8C, the circuit 100 may include a transistor. In the case where the circuit 120 has a plurality of transistors 101_1 to 101_N, the circuit It is possible to have transistors.

[0167] Next, a specific example of the circuit 10 will be described. First, referring to FIG. 9A, the circuit 10 is A configuration including a circuit 200 will be described. The circuit 200 is a part of the circuit 10. The circuit 200 includes the wiring 114, the wiring 115_1, the wiring 115_2, the node n1, and / or , and the node n2. However, this is not limited to this. The circuit 200 may be connected to other wirings or It is possible for it to be connected to other nodes.

[0168] Circuit 200 often includes one or more transistors. The polarity of the transistors 101_1 and 101_2 is often the same as that of the N-channel transistors 101_1 and 101_2. However, the circuit 200 is not limited to a P-channel transistor. Alternatively, the circuit 200 may include an N-channel transistor. and a P-channel transistor. It may be a MOS circuit.

[0169] The circuit 200 receives the signal SP, the signal SEL1, the signal SEL2, the potential of the node n1, and / or Depending on the potential of the node n2, a signal or voltage is provided to the node n1 and / or the node n2. In this way, the circuit 200 has a function of controlling the timing at which the potential of the node n1 is supplied. For example, the circuit 200 has a function of controlling the potential of the H level and / or the potential of the node n2. The function of the input terminal 11 is to supply a signal or voltage V2 to the node n1 and / or the node n2. Alternatively, the circuit 200 may apply a signal or voltage V1 at an L level to the node n1 and / or the node Alternatively, the circuit 200 has a function of supplying a signal or a voltage to the nodes n1 and n2. The circuit 200 has a function of not supplying the voltage of the node n1 to the node n2. The circuit 200 has a function of increasing the potential of the node n1 and / or the potential of the node n2. The potential of the node n1 and / or the potential of the node n2 are reduced or maintained. The circuit 200 has a function of putting the node n1 and / or the node n2 in a floating state.

[0170] Here, an example of the circuit 200 will be described with reference to FIG. The transistor 2 has a plurality of transistors 201_1 to 201_2. A first terminal of the transistor 01_1 is connected to the wiring 115_1, and a second terminal of the transistor 201_1 is connected to the wiring 115_1. is connected to the gate of the transistor 101_1, and the gate of the transistor 201_1 is A first terminal of the transistor 201_2 is connected to a wiring 114. A first terminal of the transistor 201_2 is connected to a wiring 115_2. The second terminal of the transistor 201_2 is connected to the gate of the transistor 101_2. The gate of the transistor 201_2 is connected to the wiring 114. However, various configurations can be used for the circuit 200.

[0171] The transistor 201_1 and the transistor 201_2 are It is preferable that the polarity of the transistor 101_1 is the same as that of the transistor 101_2, and the transistor 101_2 is an N-channel type. However, the transistor 201_1 and / or the transistor 201_2 may be can be of the P-channel type.

[0172] The transistor 201_1 is connected to the wiring 115_1 and the node n1 in response to the potential of the wiring 114. Alternatively, the transistor 201_1 has a function of controlling the conduction state of the wiring 114. The potential of the wiring 115_1 is supplied to the node n1 in accordance with the potential of the transistor 115_2. The transistor 201_1 has a function of being turned on or off in response to the signal SP, or The resistor 201_1 controls whether or not the signal SEL1 is input to the transistor 101_1. Alternatively, the transistor 201_1 has a function of outputting a signal by being turned on or off. The transistor 201_2 has a function of controlling whether or not to set the potential state of OUT. A function of controlling electrical continuity between the wiring 115_2 and the node n2 in response to the potential of the wiring 114. Alternatively, the transistor 201_2 may be connected to the wiring 115_ The transistor 201_2 has a function of supplying a potential of the signal The transistor 201_2 has a function of being turned on or off depending on the SP. It has a function of controlling whether or not the signal SEL2 is input to the transistor 101_2. The transistor 201_2 sets the potential state of the signal OUT by being turned on or off. It has the function of controlling whether or not

[0173] The operation of the semiconductor device in FIG. 9A will be described. Here, the circuit of the circuit 200 will be taken as an example. A case where the circuit configuration is the circuit configuration shown in FIG. As shown in FIG. 10(A), the signal SP goes to H level, so that the transistors 201_1 and Therefore, the signal SEL1 at the H level is applied to the wiring 11. 5_1 to the node n1 via the transistor 201_1, and a signal SE L2 is supplied from the wiring 115_2 through the transistor 201_2 to the node n2. Thus, the potential of the node n1 starts to rise and becomes V2. The potential of the node n1 is changed from the potential of the wiring 114 (V2) to the threshold voltage (V When the voltage rises to the value (V2-Vth201_1) obtained by subtracting The transistor 201_1 is turned off. Therefore, the potential of the node n1 is V2-Vth201_1. The player becomes levitating while maintaining their current position.

[0174] During the period B1 to E1, the signal SP is at the L level, so that the transistors 201_1 and Therefore, the wiring 115_1 and the node n1 are not electrically connected to each other. In the period B1, the wiring 115_2 and the node n2 are brought out of electrical continuity. FIG. 10B is a schematic diagram of the semiconductor device in the period C1. FIG. 10C is a schematic diagram of the semiconductor device in the periods D1 and E1. As shown in.

[0175] Next, in period A2, as shown in FIG. 10(E), the signal SP goes to H level, The transistor 201_1 and the transistor 201_2 are turned on. Therefore, the L level The signal SEL1 is supplied from the wiring 115_1 to the node n1 through the transistor 201_1. The signal SEL2 at H level is supplied from the wiring 115_2 to the transistor 201_2. Thus, the potential of node n1 becomes V1, and the potential of node n2 becomes V2. After that, the potential of the node n2 changes from the potential (V2) of the wiring 114 to the potential (V3) of the transistor The value obtained by subtracting the threshold voltage (Vth201_2) of the first gate 201_2 (V2-Vth201_2) When the potential of the node n2 rises to The potential is maintained at V2-Vth201_2 and is in a floating state.

[0176] During the period B2 to E2, the signal SP is at the L level, so that the transistors 201_1 and Therefore, the wiring 115_1 and the node n1 are not electrically connected to each other. In the period B2, the wiring 115_2 and the node n2 are brought out of electrical continuity. FIG. 10F is a schematic diagram of the semiconductor device in the period C1. 10G, and a schematic diagram of the semiconductor device in the periods D2 and E2 is shown in FIG. As shown in.

[0177] As described above, by configuring the circuit 10, any of the transistors in the circuit 100 The transistors in the circuit 100 can be selectively turned on or off. Even when the transistor is turned off, a potential is applied to the gate of the transistor to be turned off from the circuit 10. It is possible to prevent the device from becoming idle.

[0178] Since the transistors 201_1 and 201_2 have the same function, The channel width of the transistor 201_1 and the channel width of the transistor 201_2 are It is preferable that the transistor sizes are roughly equal. By this, the current supply capacity can be made roughly equal. Therefore, the degree of polarization can be roughly equalized by switching transistors. In addition, the potential of the node n1 and the potential of the node n2 can be made approximately equal, so that the signal The waveform of the signal OUT can be roughly the same. However, this is not limited to this. The channel width of the transistor 201_1 and the channel width of the transistor 201_2 are different. It is possible.

[0179] The load of the transistor 201_1 (for example, node n1) is the transistor 101_1 Since the load of the transistor 201_1 is smaller than the load of the other transistor (for example, the wiring 111), The channel width is preferably smaller than the channel width of the transistor 101_1. The load of the transistor 201_2 (for example, node n2) is the load of the transistor 101_2. Since the load (e.g., the wiring 111) is often smaller than the channel of the transistor 201_2, The width of the channel is preferably smaller than the channel width of the transistor 101_2. However, the channel width of the transistor 201_1 is not limited to the above. Alternatively, the channel width of the transistor 201_2 can be larger than , may be larger than the channel width of transistor 101_2.

[0180] As shown in FIG. 9C, the circuit 100 includes transistors 101, 1 to 101_N, the circuit 200 includes transistors 2 It is possible to have multiple transistors 01_1 to 201_N. The first terminals of the capacitors 201_1 to 201_N are connected to the wirings 115_1 to 115_N, respectively. The second terminals of the transistors 201_1 to 201_N are connected to the nodes n1 to nN. The gates of the transistors 201_1 to 201_N are connected to the wiring 114.

[0181] As shown in FIG. 9D, the wiring 114 may be divided into a plurality of wirings 114A to 114B. Therefore, the wirings 114A to 114B can be divided into the same The gate of the transistor 201_1 is connected to the wiring 114A. The gate of the transistor 201_2 is connected to the wiring 114B. Signals having approximately the same waveform are input to the line 114A and the line 114B. and separate signals can be input.

[0182] As in FIG. 9D, the wiring 114 is divided into a plurality of wirings in FIG. 9C. It is possible.

[0183] As shown in FIG. 9E, the first terminal of the transistor 201_1 and the The first terminal of the first terminal of the second ... second terminal of the first terminal of the first terminal of the second terminal of the first terminal of the second terminal of the first terminal of the first terminal of the second terminal of the first terminal of the second terminal of the first terminal of the first terminal of the second terminal of the First terminals of the transistors 201_1 and 201_2 are connected to the wiring 115_1. However, the present invention is not limited to this. The first terminals of the transistors 201_1 to 201_2 may also be It is possible to connect to various wirings. For example, the transistors 201_1 to 201_ The first terminal of the second transistor is connected to the wiring 113 or a wiring to which a signal CK2 is input. It is possible.

[0184] As in FIG. 9E, in FIGS. 9C to 9D, the transistors 201_1 to The first terminal of 201_2 can be connected to the same wiring. In this case, the first terminals of the transistors 201_1 to 201_N are connected to the same wiring. is possible.

[0185] As shown in FIG. 9F, the first terminal of the transistor 201_1 is connected to the wiring 114. The second terminal of the transistor 201_1 is connected to the node n1, and the second terminal of the transistor 201_2 is connected to the node n2. The gate of the transistor 201_1 can be connected to the wiring 115_1. A first terminal of the transistor 201_1 is connected to the wiring 114, and a second terminal of the transistor 201_2 is connected to the node n2. The gate of the transistor 201_2 can be connected to the wiring 115_2. In this case, during the period T1, the signal SEL1 is at the H level and the signal SEL2 is at the L level. If the level is 0, the transistor 201_1 is turned on and the transistor 201_2 is turned on. Therefore, in the period A1, the signal SP at the H level is transmitted from the wiring 114 to the transistor 116. Since the potential is supplied to the node n1 through the transistor 201_1, the potential of the node n1 rises. On the other hand, during the period T2, the signal SEL1 is at the L level and the signal SEL2 is at the H level. If so, the transistor 201_1 is turned off and the transistor 201_2 is turned on. Therefore, in the period A2, the signal SP at the H level is transmitted from the wiring 114 to the transistor. Since the potential is supplied to the node n2 via the capacitor 201_2, the potential of the node n2 increases.

[0186] As shown in FIG. 11A, the second terminal of the transistor 201_1 and the node n1 A transistor 202_1 in a diode-connected configuration may be connected between the Similarly, a diode is provided between the second terminal of the transistor 201_2 and the node n2. The transistor 202_2 may be connected in a connected configuration. A first terminal of the transistor 202_1 is connected to a second terminal of the transistor 201_1. A second terminal of the transistor 202_1 is connected to the node n1, and a gate of the transistor 202_1 is The first terminal of the transistor 202_2 is connected to the second terminal of the transistor 201_1. , is connected to the second terminal of the transistor 201_2, and the second terminal of the transistor 202_2 is , and the gate of the transistor 202_2 is connected to the node n2. The transistor 201_1 and the transistor 201_2 are connected to the second terminal of the The transistor 201_1 can function as a diode. By this, a decrease in the potential of the node n1 is prevented. 01_2 has a function of preventing a decrease in the potential of the node n2 by being in a non-conductive state. However, the present invention is not limited to this, and the second terminal of the transistor 201_1 and the node n1 may be , and / or various elements between the second terminal of the transistor 201_2 and the node n2 Alternatively, the first terminal of the transistor 201_1 and the Between the first terminal of the transistor 201_2 and the line 115_1 and / or between the first terminal of the transistor 201_2 and the line 115_2 It is possible to connect various elements or circuits between the As shown in FIG. 1, the transistor 202_1 is connected between the first terminal of the transistor 201_1 and the wiring 1 15_1. Alternatively, the transistor 202_2 may be connected between the transistor It can be connected between the first terminal of the transistor 201_2 and the wiring 115_2.

[0187] As in the case of FIGS. 11(A) to 11(B), in FIGS. 9(C) to 9(F), the transistor 2 between the second terminal of the transistor 201_1 and the node n1, between the second terminal of the transistor 201_2 and the node n 2, between the first terminal of the transistor 201_1 and the wiring 115_1, and / or between the first terminal of the transistor 201_2 and the wiring 115_1. Various elements or circuits are provided between the first terminal of the transistor 201_2 and the wiring 115_2. FIG. 11C shows an example of a traverse in FIG. 9F. A transistor having a diode-connected configuration is connected between the second terminal of the transistor 201_1 and the node n1. A transistor 202_1 is connected between the second terminal of the transistor 201_2 and the node n2. 2 shows a configuration in which a transistor 202_2 in a diode-connected configuration is connected. FIG. 11D shows an example of the first transistor 201_1 in FIG. A diode-connected transistor 202_1 is connected between the terminal and the wiring 114. A diode-connected transistor is provided between the first terminal of the transistor 201_2 and the wiring 114. 2 shows a configuration in which a transistor 202_1 of the above configuration is connected.

[0188] As shown in FIG. 11E, the circuit 200 includes transistors 203_1 to 203_2. It is possible to have a plurality of transistors such as the transistors 203_1 to 203_3. It is preferable that the polarity of the N-channel transistors 201_1 to 201_2 is the same as that of the N-channel transistors 201_2. However, the present invention is not limited to this, and the transistors 203_1 to 203_3 are of the same type. The first terminal of the transistor 203_1 may be a P-channel type. a second terminal of the transistor 203_1 connected to the wiring 117, and a second terminal of the transistor 203_1 connected to the node n1. The gate of the transistor 203_1 is connected to the wiring 115_2. A first terminal of the transistor 203_2 is connected to the wiring 117, and a second terminal of the transistor 203_2 is connected to the The gate of the transistor 203_2 is connected to the wiring 115_1. However, this is not limited to this. For example, the second terminal of the transistor 203_1 is connected to the node n 2. Alternatively, the second terminal of the transistor 203_2 may be connected to node n1.

[0189] In response to a signal SEL2, the transistor 203_1 switches between the wiring 117 and the node n1. By controlling the conduction state, the timing at which voltage V1 is supplied to node n1 is controlled. The transistor 203_2 has a function of switching the input voltage Vpp and can function as a switch. In response to the signal SEL1, the conduction state between the wiring 117 and the node n2 is controlled. , the function of controlling the timing at which the voltage V1 is supplied to the node n2, Thus, in the period T1, the transistor 203_2 Therefore, the voltage V1 is supplied to the node n2. Therefore, the transistor 201_2 is off. Similarly, in the period T2, the potential of the transistor The voltage V1 is supplied to the node n1 by the transistor 203_1. Even if 201_1 is off, the potential of the node n1 can be fixed. Therefore, a semiconductor device that is resistant to noise can be obtained.

[0190] As shown in FIG. 11(F), the wiring 117 may be divided into a plurality of wirings 117A to 117B. The first terminal of the transistor 203_1 and the second terminal of the transistor The first terminals of 203_2 can be connected to the wiring 117A and the wiring 117B, respectively. The wirings 117A to 117B are connected to various wirings, various elements, or various nodes. It is possible to do so.

[0191] As shown in FIG. 12A, the second terminal of the transistor 203_1 is connected to the wiring 115_ 1, and a second terminal of the transistor 203_2 is connected to the wiring 115_2. By doing so, the period during which the transistor 203_1 is turned off (for example, For example, during a period T1, an H-level signal is input to the first terminal of the transistor 203_1. Therefore, a reverse bias is applied to the transistor 203_1, which suppresses deterioration. Similarly, during the period when the transistor 203_2 is turned off (for example, the period T2), In this case, an H-level signal is input to the first terminal of the transistor 203_2. Since a reverse bias is applied to the transistor 203_2, deterioration can be suppressed. .

[0192] As shown in FIG. 12B, the transistor 203_1 and the transistor 203_ 2 may be in a diode-connected configuration. For example, transistor 203 A first terminal of the transistor 203_1 is connected to the wiring 115_1, and a second terminal of the transistor 203_1 is connected to the wiring 115_1. The gate of the transistor 203_1 is connected to the node n1, and the gate of the transistor 203_1 is connected to the node n1. Similarly, a first terminal of the transistor 203_2 is connected to the wiring 115_2. A second terminal of the transistor 203_2 is connected to the node n2, and a gate of the transistor 203_2 is In this case, during the period T1, the signal SEL2 goes to the L level. Then, the signal SEL2 at the L level is output from the wiring 115_2 through the transistor 203_2. The potential of the node n2 is fixed to approximately V1. On the other hand, in the period T2, when the signal SEL1 becomes the L level, The signal SEL1 of the line 115_1 is supplied to the node n1 through the transistor 203_1. Therefore, the potential of the node n1 can be fixed to approximately V1. However, the present invention is not limited to this. For example, the gate of the transistor 203_1 is connected to the wiring 1. 15_1. Alternatively, the gate of the transistor 203_2 can be connected to the It can be connected to the line 115_2.

[0193] 11(E) to (F) and 12(A) to (B), as well as FIGS. 9(C) to (F), 11A to 11D, the circuit 200 includes transistors 203_1 to 203_2. For example, in FIG. 12(C), the circuit shown in FIG. 9(F) can be FIG. 12(D) shows a configuration in which the circuit 200 has transistors 203_1 to 203_2. 11A to 11E, the circuit 200 includes transistors 203_1 to 203_2. FIG. 12F shows a configuration in which the circuit 200 in FIG. 2 shows a configuration in which the semiconductor device has transistors 203_1 and 203_2.

[0194] The second terminal of the transistor 203_1 and the second terminal of the transistor 203_2 are It is possible to connect to various wirings or nodes. For example, as shown in FIG. Furthermore, the second terminal of the transistor 203_1 is connected to the second terminal of the transistor 201_1. Similarly, the second terminal of the transistor 203_2 can be connected to the transistor 2 12(F), A second terminal of the transistor 203_1 is connected to a first terminal of the transistor 201_1. Similarly, the second terminal of the transistor 203_2 is connected to the second terminal of the transistor 201 It is possible to connect it to the first terminal of _2.

[0195] As shown in FIG. 5F, the circuit 200 includes transistors 201_1 and 201_2. In addition, it is possible to have a plurality of transistors 203_1 to 203_2. The transistors 203_1 to 203_2 are the same as the transistors 201_1 to 201_ It is preferable that the polarity is the same as that of 2 and that the transistor is an N-channel type. However, the transistors 203_1 to 203_2 may be of a P-channel type. A first terminal of the transistor 203_1 is connected to the wiring 114. A second terminal of the transistor 203_1 is connected to the node n1. A gate of the transistor 203_1 is connected to the wiring A first terminal of the transistor 203_2 is connected to the wiring 114. The second terminal of the transistor 203_2 is connected to the node n2. The port is connected to a wiring 118. A signal CK2 is input to the wiring 118. Therefore, the wiring 118 can function as a signal line or a clock signal line. However, the present invention is not limited to this, and various signals, various voltages, or various currents may be applied to the wiring 118. The transistor 203_1 is connected in response to the potential of the wiring 118. The transistor 203 has a function of controlling the conduction state between the line 114 and the node n1. The potential of the wiring 114 is supplied to the node n1 in response to the potential of the wiring 118. The transistor 203_2 is connected between the wiring 114 and the node n2 in response to the potential of the wiring 118. Alternatively, the transistor 203_2 has a function of controlling electrical continuity between the wiring 118 and the The potential of the wiring 114 is supplied to the node n2 in response to the potential. The transistors 203_1 to 203_2 may have various other functions. It is possible.

[0196] The first terminal of the transistor 203_1 and the first terminal of the transistor 203_2 are separate. The gate and the gate of the transistor 203_1 can be connected to each other. The gate of the transistor 203_2 can be connected to a separate wiring.

[0197] As in FIG. 5(F), FIGS. 9(C) to (F), 11(A) to (F), and FIG. In A) to F), transistors having the same functions as the transistors 203_1 to 203_2 are used. It is possible to add new transistors.

[0198] As shown in FIG. 13A, the transistors 101_1 and 101_2, P-channel transistors can be used as 201_1 and 201_2. The transistors 101p_1 and 101p_2 correspond to the transistors 101_1 and 101_2. The transistors 102p_1 and 102p_2 are of the P-channel type. 102_1 to 102_2, which are P-channel type. In this way, when the polarity of the transistor is a P-channel type, a voltage V1 is supplied to the wiring 113, and A voltage V2 is supplied to the line 117, and the potentials of the signals CK1, SP, RE, and node n1 are 4B, the potential of the node n2 and the signal OUT are inversely related to the timing chart of FIG. Please note that it is rotating.

[0199] As in FIG. 13(A), FIGS. 9(C) to (F), 11(A) to (F), and FIG. 12 In (A) to (F), a P-channel transistor is used as the transistor. It is possible.

[0200] (Embodiment 3) In this embodiment, an example of a configuration different from that of the circuit 10 described in the second embodiment will be described. The contents described in the first and second embodiments will not be described. The contents described in the embodiment may be appropriately combined with the contents described in the first and second embodiments. It is possible.

[0201] First, a specific example of the circuit 10 different from that in the second embodiment will be described with reference to FIG. The circuit 10 in FIG. 14 includes a circuit 300 in addition to the circuit 200. The circuit 300 includes the same components as the circuit 10. In addition, a part of the circuit 300 can be shared with the circuit 200. 0 can be shared with the circuit 300. The circuit 300 includes the wiring 113, the wiring 116, a wiring 117, a node n1, a node n2, and / or a wiring 111. However, the present invention is not limited to this, and the circuit 200 may be connected to other wirings or other nodes. is possible.

[0202] Circuit 300 often includes one or more transistors. The polarity of the transistors 101_1 and 101_2 is often the same as that of the N-channel transistors 101_1 and 101_2. However, the circuit 300 is not limited to a P-channel transistor. Alternatively, the circuit 300 may include an N-channel transistor. and a P-channel transistor. It may be a MOS circuit.

[0203] The circuit 300 receives the signal RE, the potential of the node n1, the potential of the node n2, and / or the signal OU Depending on the fall time of T, a signal is applied to the node n1, the node n2, and / or the wiring 111. In this way, the circuit 200 has a function of controlling the timing of supplying the voltage. The potential of the node n1, the potential of the node n2, and / or the potential of the wiring 111. For example, the circuit 200 supplies a signal or voltage V1 at an L level to the nodes n1, n2, and and / or the wiring 111.

[0204] Next, an example of the circuit 300 will be described with reference to FIG. In the example, the circuit 300 includes a plurality of transistors 301_1 to 301_2. , a transistor 302, and a plurality of transistors 303_1 to 303_2. , a transistor 304, a plurality of circuits 310_1 to 310_2, and a circuit 320 has.

[0205] In addition, the transistors 301_1 to 301_2, the transistor 302, and the transistor 303 The transistors _1 to 303_2 and the transistor 304 are, for example, N-channel types. However, the present invention is not limited to this, and the transistors 301_1 to 301_2 and the transistor 3 02, the transistors 303_1 to 303_2, and / or the transistor 304 are P-channel The optical fiber may be of the channel type.

[0206] As an example, as shown in FIG. 15B, circuits 310_1 to 310_2 and An inverter circuit can be used as 320. However, the present invention is not limited to this. As the circuits 310_1 to 310_2 and the circuit 320, various other circuits may be used. It is possible.

[0207] Next, the connections of the circuit 300 in FIG. 15A will be described. A first terminal of the transistor 301_1 is connected to the wiring 117, and a second terminal of the transistor 301_1 is connected to the node n A first terminal of the transistor 301_2 is connected to the wiring 117. A second terminal of the transistor 301_2 is connected to the node n2. The second terminal of the transistor 302 is connected to the wiring 117, and the second terminal of the transistor 303 is connected to the wiring 111. A first terminal of the transistor 303_1 is connected to the wiring 117. A second terminal of the transistor 303_1 is connected to the node n1. A gate of the transistor 303_1 is connected to the wiring A first terminal of the transistor 303_2 is connected to the wiring 117. The second terminal of the transistor 303_2 is connected to the node n2. The first terminal of the transistor 304 is connected to the wiring 117. The second terminal of the transistor 304 is connected to the wiring 111. The gate is connected to the wiring 116. The circuit 310_1 includes a wiring 113, a node n1, a wiring The circuit 310_2 is connected to the wiring 117 and the gate of the transistor 301_1. 13, the node n2, the wiring 117, and the gate of the transistor 301_2. The path 320 is connected to the wiring 113, the wiring 111, the wiring 117, and the gate of the transistor 302. Connected.

[0208] Next, functions of the circuits 310_1 and 310_2 and the circuit 320 will be described. The path 310_1 changes the potential of the gate of the transistor 301_1 in response to the potential of the node n1. By controlling the control, the conductive state of the transistor 301_1 is controlled. The circuit 310_2 can function as a circuit in response to the potential of the node n2. By controlling the potential of the gate of the transistor 301_2, the transistor 301_ Circuit 3 has a function of controlling the conductive state of circuit 2 and can function as a control circuit. 20 controls the potential of the gate of the transistor 302 in response to the potential of the wiring 111. This has a function of controlling the conduction state of the transistor 302 and functions as a control circuit. However, the present invention is not limited to this, and the circuits 310_1 to 310_2 and Path 320 can have a variety of other functions.

[0209] Next, the transistors 301_1 to 301_2, the transistor 302, and the transistor 303 The functions of the transistors _1 to 303_2 and the transistor 304 will be described. The transistor 301_1 changes the electrical continuity between the wiring 117 and the node n1 in response to an output signal of the circuit 310_1. By controlling the state, the timing of supplying voltage V1 to node n1 can be controlled. The transistor 301_2 has a function of switching the input voltage Vcc to the ground potential Vcc and can function as a switch. The conduction state between the wiring 117 and the node n2 is controlled in response to the output signal of 310_2. Therefore, the switch has a function of controlling the timing of supplying the voltage V1 to the node n2. The transistor 302 can function as a By controlling the conduction state between the wiring 117 and the wiring 111, the voltage V1 is applied to the wiring 111. and can function as a switch. The transistor 303_1 turns on or off the wiring 117 and the node n1 in response to a signal RE. By controlling the timing of supplying voltage V1 to node n1, The transistor 303_2 is connected to a signal RE In response to this, the conduction state between the wiring 117 and the node n2 is controlled, thereby controlling the voltage V1. It has a function to control the timing of supplying to node n2, and can function as a switch. The transistor 304 turns on and off the wiring 117 and the wiring 111 in response to a signal RE. By controlling the state, the timing of supplying the voltage V1 to the wiring 111 can be controlled. It can function as a switch. However, it is not limited to this. Transistors 301_1 to 301_2, transistor 302, transistors 303_1 to 30 3_2 and the transistor 304 can have various other functions.

[0210] Next, an example of the operation of the circuit 300 in FIG. The operation of the semiconductor device is common to that of the semiconductor device shown in FIG. The following description will be given with reference to the timing chart of FIG. Where applicable, explanations will be omitted.

[0211] First, in a period A1, as shown in FIG. 16(A), the signal RE goes to the L level. The transistors 303_1 to 303_2 and the transistor 304 are turned off. The output signal 0_1 is generated because the potential of node n1 becomes, for example, V2+Vth101_1+Vx. Therefore, the transistor 301_1 is turned off. The output signal becomes H level because the potential of the node n2 is approximately V1. The transistor 301_2 is turned on. The output signal of the circuit 320 is This voltage becomes V1, which is at the H level. Therefore, the transistor 302 is turned on. As a result, the wiring 117 and the node n1 are in a non-conducting state, and the wiring 117 and the node n2 are in a non-conducting state. The wiring 117 and the wiring 111 are connected to each other through the transistor 301_2. Therefore, the voltage V1 is applied from the wiring 117 to the transistor 30 The voltage V1 is supplied to the node n2 through the wiring 117 and the transistor 30 2 to the wiring 111.

[0212] On the other hand, in the period A2, as shown in FIG. 16(B), the output signal of the circuit 310_1 is The potential of the node n1 becomes approximately V1, so that the potential becomes H level, and the output signal of the circuit 310_2 becomes , the potential of node n2 becomes, for example, V2+Vth101_2+Vx, so that it becomes L level. However, this is different from the period A1. Therefore, the transistor 301_1 is turned on, and the transistor As a result, the wiring 117 and the node n1 are connected to the transistor 301_2. Conduction is established through 01_1, and conduction is eliminated between the wiring 117 and the node n2. The voltage V1 is supplied to the node n1 via the wiring 117.

[0213] Next, during period B1, as shown in FIG. 16(C), the signal RE remains at the L level. , the transistors 303_1 to 303_2 and the transistor 304 remain off. The output signal of the circuit 310_1 is, for example, V2+Vth101_1+Vx Therefore, the transistor 301_1 remains off. The output signal of the circuit 310_2 is H because the potential of the node n2 remains at approximately V1. Therefore, the transistor 301_2 remains on. Since the potential of the wiring 111 is approximately V2, the output signal of The transistor 302 is turned off. As a result, the wiring 117 and the node n1 are not in electrical continuity. Therefore, electrical continuity between the wiring 117 and the node n2 remains through the transistor 301_2. Therefore, the voltage V1 is applied to the line 117 and the line 111. 17 to the node n2 via the transistor 301_2.

[0214] On the other hand, in the period B2, as shown in FIG. 17(A), the output signal of the circuit 310_1 is Since the potential of the node n1 remains at approximately V1, it remains at the L level, and the output of the circuit 310_2 The output signal is, for example, the potential of node n2 remains approximately V2 + Vth101_2 + Vx. The difference from the period B1 is that the transistor 301 remains at the L level. _1 remains on and transistor 301_2 remains off. 117 and the node n1 remain in a conductive state through the transistor 301_1, and the wiring 1 Therefore, the voltage V1 is applied to the node n1 through the wiring 117. and supplied to node n1.

[0215] Next, during periods C1 and C2, as shown in FIG. 17B, the signal RE is at H level. Therefore, the transistors 303_1 to 303_2 and the transistor 304 are turned on. The output signal of the circuit 310_1 is at the H level because the potential of the node n1 is approximately V1. Therefore, the transistor 301_1 is turned on. Since the potential of node n2 is approximately V1, it becomes H level. The potential of the wiring 111 is approximately V1. This causes the output to go to H level, and the transistor 302 is turned on. The line 117 and the node n1 are connected via the transistors 301_1 and 303_1. The wiring 117 and the node n2 are electrically connected to the transistor 301_2 and the transistor The wiring 117 and the wiring 111 are electrically connected to the transistor 302 through 303_2. Therefore, the voltage V1 is applied from the wiring 117 to the transistor 304. The voltage is supplied to a node n1 via a transistor 301_1 and a transistor 303_1. The voltage V1 is input from the wiring 117 through the transistors 301_2 and 303_2. The voltage V1 is supplied to the node n2 from the wiring 117 to the transistor 302 and the transistor The signal is supplied to the wiring 111 via the star 304.

[0216] Next, in periods D1, D2, E1, and E2, as shown in FIG. 17(C), Since the signal RE becomes L level, the transistors 303_1 to 303_2 and the transistor The potential of the node n1 is approximately V1. Therefore, the transistor 301_1 remains on. The output signal of the circuit 310_2 is H because the potential of the node n2 remains at approximately V1. Therefore, the transistor 301_2 remains on. Since the potential of the wiring 111 remains at approximately V1, the output signal of remains at the H level. Therefore, the transistor 302 remains on. As a result, the wiring 117 and the node n1 remains in a conductive state through the transistor 301_1, and the wiring 117 and the node n2 The transistor 301_2 remains in a conductive state, and the wiring 117 and the wiring 111 are connected to each other. Therefore, the voltage V1 is applied from the wiring 117 to the transistor 302. The voltage V1 is supplied to the node n1 through the transistor 301_1. The voltage V1 is supplied to the node n2 through the transistor 301_2. The signal is supplied to the wiring 111 through the transistor 302 .

[0217] Since the transistors 301_1 and 301_2 have the same functions, It is preferable that the channel widths of the transistors 303_1 to 303_3 are approximately equal. 3_2 have similar functions, so it is preferable that their channel widths are approximately equal. However, the present invention is not limited to this, and the transistors 301_1 and 301_2 may be connected to each other via channels. Alternatively, the transistors 303_1 to 303_2 may have different widths. may have a structure in which the channel widths are different from each other.

[0218] The transistors 301_1 and 301_2 supply a voltage V1 to the nodes n1 and n2. The transistor 302 has a function of controlling timing and supplies a voltage V1 to the wiring 111. The load of the nodes n1 to n2 is the load of the wiring 111. Therefore, the channel width of the transistors 301_1 to 301_2 is It is preferable that the channel width of the transistor 302 is smaller than that of the transistor 302. The channel width of the transistors 303_1 and 303_2 is smaller than the channel width of the transistor 304. However, it is preferable that the transistors 301_1 to 301_2 are The channel width is greater than or approximately equal to the channel width of transistor 302. Alternatively, the channel width of the transistors 303_1 to 303_2 can be The width of the channel of the input 304 may be greater than or approximately equal to the channel width of the input 304 .

[0219] As shown in FIG. 18A, similarly to the first and second embodiments, the wiring 117 It is possible to divide the wiring 117C into a plurality of wirings 117C to 117K. Wiring 117D, wiring 117E, wiring 117F, wiring 117G, wiring 117H, wiring 117 I, a wiring 117J, and a wiring 117K are respectively connected to a first terminal of the transistor 303_1, A first terminal of the transistor 303_2, a first terminal of the transistor 304, a circuit 310_1, A first terminal of the transistor 301_1, a circuit 310_2, and a first terminal of the transistor 301_2 , the circuit 320, and the first terminal of the transistor 302. 7C to 117K are the wiring 111, the wiring 112, the wiring 113, the wiring 114, the wiring 115_1 Various wirings such as 115_2, wiring 116, wiring 118, or wiring 211, or It is possible to connect to various nodes such as nodes n1 to n2. However, this is not limited to this. Similarly, the wiring 113 can be divided into a plurality of wirings.

[0220] As shown in FIG. 18B, the first terminal of the transistor 303_1 and the A first terminal of the transistor 303_2 and a first terminal of the transistor 304 are connected to the wiring 118. It is possible.

[0221] As shown in FIG. 18C, the transistor 304 can be omitted. However, the present invention is not limited to this, and the transistor 303_1 and / or the transistor 303_ It is possible to omit 2.

[0222] As in FIG. 18C, in FIGS. 18A to 18B, the transistor 303 1, transistor 303_2, and / or transistor 304 may be omitted. be.

[0223] As shown in FIG. 19A, the circuit 320 and the transistor 302 can be omitted. However, the present invention is not limited to this. 1 can be omitted, and the circuit 310_1 and the transistor 301_2 can be omitted. It is possible to do so.

[0224] As in FIG. 19A, in FIGS. 18A to 18C, the circuit 310_1 and The transistor 301_1 can be omitted, and the circuit 310_1 and the transistor The transistor 301_2 can be omitted, and the circuit 320 and the transistor 302 can be omitted. It is possible to omit it.

[0225] As shown in FIG. 19B, the transistor 301_1 is connected to one terminal (hereinafter, the positive terminal The other terminal (hereinafter also referred to as a negative terminal) is connected to the node n1, and the other terminal (hereinafter also referred to as a negative terminal) is connected to the circuit 310_ It is possible to replace the diode 301a_1 connected to the output terminal of the first input. One terminal (hereinafter also referred to as a positive terminal) of the transistor 301_2 is connected to the node n2. The other terminal (hereinafter, also referred to as the negative terminal) of the diode is connected to the output terminal of the circuit 310_2. Alternatively, the transistor 302 can be replaced with one of the A terminal (hereinafter also referred to as a positive electrode) is connected to the wiring 111, and the other terminal (hereinafter also referred to as a negative electrode) ) can be substituted for the diode 302a connected to the output terminal of the circuit 320. Alternatively, one terminal (hereinafter also referred to as a positive terminal) of the transistor 303_1 is connected to the node n1. and the other terminal (hereinafter also referred to as the negative electrode) of the diode 3 is connected to the wiring 116. Alternatively, the transistor 303_2 can be replaced with the transistor 303a_1. The terminal (hereinafter also referred to as the positive terminal) is connected to node n2, and the other terminal (hereinafter also referred to as the negative terminal) can be replaced with the diode 303a_2 connected to the wiring 116. One terminal (hereinafter also referred to as a positive electrode) of the transistor 304 is connected to the wiring 111. The other terminal (hereinafter, also referred to as the negative terminal) of the diode 304a is connected to the wiring 116. However, the present invention is not limited to this, and the gate of each transistor and the second By connecting this pin, it is possible to configure the transistor as a diode. Alternatively, the gate of each transistor can be connected to the first terminal. It is possible to configure the resistor in a diode-connected configuration.

[0226] As in FIG. 19(B), in FIGS. 18(A) to 18(C) and FIG. 19(A), Transistors 301_1 to 301_2, transistor 302, transistors 303_1 to 3 03_2 and / or transistor 304 can be replaced with a diode. Alternatively, the transistors can be in a diode-connected configuration.

[0227] As shown in FIG. 19C, the transistors 301_1 and 301_2 and the transistor A circuit for controlling the conductive state of the transistor 302 is made up of transistors 301_1 to 301_2, and The circuit 330 can be shared by the transistors 302 and 303. The gates of the transistors 301_1 to 301_2 and the transistor 302 are By controlling the potential of the transistors 301_1 to 301_2 and the transistor The input terminal 304 has a function of controlling the conductive state of the capacitor 302 and can function as a control circuit. In the periods A1, A2, B1, and B2 shown in FIG. 4C, the output of the circuit 330 The signal is at the L level because the potential of the node n1 or the potential of the node n2 is higher than V1. Therefore, the transistors 301_1 to 301_2 and the transistor 302 are turned off. In the periods C1, C2, D1, D2, E1, and E2, the circuit The output signal of 330 is H because the potential of node n1 or the potential of node n2 is approximately V1. Therefore, the transistors 301_1 to 301_2 and the transistor 302 will be turned on.

[0228] As in FIG. 19(C), in FIGS. 18(A) to (C) and 19(A) to (B), Even if the transistors 301_1 to 301_2 and the transistor 302 are turned on, the conduction state of the transistors 301_1 to 301_2 and the transistor 302 is controlled. It is possible to share a circuit for performing the above operations.

[0229] As shown in FIG. 20A, the circuit 100 includes the transistor 10 as shown in FIG. When the circuit 300 has a plurality of transistors 1_1 to 101_N, the transistors A plurality of transistors 301_1 to 301_N, transistors 303_1 to 303 310_1 to 310_N, and a plurality of circuits 310_1 to 310_N. The transistors 301_1 to 301_N are 1 or 301_2 and have the same function. 303_N corresponds to the transistor 303_1 or the transistor 303_2, The circuits 310_1 to 310_N have the functions of The first terminals of the transistors 301_1 to 301_N are connected to the wiring 1. 17. The second terminals of the transistors 301_1 to 301_N are connected to the node n The gates of the transistors 301_1 to 301_N are connected to the respective The transistors 303_1 to 303_N are connected to the output terminals of the transistors 303_1 to 303_N. The first terminal is connected to the wiring 117. The gates of the transistors 303_1 to 303_N are connected to the nodes n1 to nN, respectively. The port is connected to wiring 116 .

[0230] As in FIG. 20(A), in FIGS. 18(A) to (C) and 19(A) to (C), However, the circuit 300 includes a plurality of transistors 301_1 to 301_N. A plurality of transistors 303_1 to 303_N and / or a circuit 31 It is possible to have multiple circuits numbered 0_1 through 310_N.

[0231] In addition, when the semiconductor device has the circuit 120 as shown in FIG. 8F, As such, the circuit 300 may include a transistor 342 and a transistor 344. The transistor 342 corresponds to the transistor 302 and has a similar function. The transistor 344 corresponds to the transistor 304 and has a similar function. A first terminal of the transistor 342 is connected to the wiring 117, and a second terminal of the transistor 342 is connected to the wiring 2. 11, and the gate of transistor 342 is connected to the gate of transistor 302. A first terminal of the transistor 344 is connected to the wiring 117. The second terminal is connected to the wiring 211, and the gate of the transistor 344 is connected to the wiring 116. will be done.

[0232] As in FIG. 20(B), FIGS. 18(A) to (C), 19(A) to (C), and FIG. In FIG. 2(A), the circuit 300 also includes the transistor 342 and / or the transistor 3 It is possible to have 44.

[0233] As shown in FIG. 21, the transistors 301_1 to 301_2 and the transistor 302 The transistors 303_1 to 303_2 and the transistor 304 are P-channel It is possible to use transistors. The transistor 302p, the transistors 303p_1 to 303p_2, and the transistor 30 4p are transistors 301_1 to 301_2, transistor 302, The transistors 303_1 to 303_2 and the transistor 304 are of the P-channel type. In the case where the polarity of the transistor is a P-channel type, a voltage V1 is supplied to the wiring 113, and A voltage V2 is supplied to 117, and the output signal of the circuit 310_1 and the output signal of the circuit 310_2 are The output signal of the circuit 320, the potential of the node n1, the potential of the node n2, and the signal OUT are It should be noted that the polarity of the transistor is reversed compared to the N-channel type.

[0234] As in FIG. 21, FIGS. 18(A) to (C), 19(A) to (C), and 20(A) In the above-mentioned embodiments (1) to (B), a P-channel transistor may be used as the transistor. It is possible.

[0235] Next, specific examples of the circuits 310_1 and 310_2 and the circuit 320 will be described.

[0236] First, FIG. 22A illustrates an example of a circuit 310_1. The circuit 310_1 is a transistor. The first terminal of the transistor 311_1 and the second terminal of the transistor 312_1 are connected to the first terminal of the transistor 311_2. The second terminal of the transistor 311_1 is connected to the wiring 113, and the second terminal of the transistor 311_2 is connected to the wiring 113. The gate of the transistor 311_1 is connected to the wiring 113. A first terminal of the transistor 312_1 is connected to the wiring 117. The second terminal of the transistor 301_2 is connected to the gate of the transistor 301_1. The gates of the transistors 311_1 and 311_2 are connected to the node n1. The transistor 12_1 is an N-channel type. However, it is not limited to this. 311_1 and / or transistor 312_1 may be of the P-channel type. The transistor 311_1 is connected to the transistor 301_1 when the gate potential of the transistor 301_1 is approximately V When the potential of the transistor 301_1 becomes 1, the potential of the gate of the transistor 301_1 is increased. The transistor 312_1 can function as a potential regulator of the node n1. By controlling the electrical continuity between the wiring 117 and the transistor 301_1 in response to The function of controlling the timing of supplying the voltage V1 to the gate of the transistor 301_1 is , it can function as a switch.

[0237] The operation of the circuit 310_1 shown in FIG. 22A will be described. In this case, the potential of the node n1 becomes higher than the threshold voltage of the transistor 312_1. The transistor 312_1 is turned on. Therefore, the channel width of the transistor 312_1 is By making the channel width of the transistor 311_1 larger than that of the transistor 30 The potential of the gate of transistor 301_1 is approximately V1. The potential of the wiring 117 (V1) and the threshold voltage of the transistor 301_1 (Vth30 1_1) is smaller than the sum of period A2, period B2, period C1, period C2, period In the periods D1, D2, E1, and E2, the potential of the node n1 is approximately V1. Therefore, the transistor 312_1 is turned off. The potential of the terminal is changed from the potential of the wiring 113 (V2) to the threshold voltage of the transistor 311_1 (Vt h311_1) is subtracted from the value (V2-Vth311_1).

[0238] The channel width of the transistor 312_1 is It is preferably 2 times or more, and more preferably 4 times or more. Preferably, the ratio is 8 times or more, but is not limited thereto.

[0239] Note that the gate and the first terminal of the transistor 311_1 may be connected to various wirings. For example, the gate and the first terminal of the transistor 311_1 may be connected to the wiring 112 or It is possible to connect to the wiring 118. However, this is not a limitation.

[0240] The first terminal of the transistor 312_1 can be connected to various wirings. For example, the first wiring of the transistor 312_1 may be connected to the wiring 115_2. It is possible, but not limited to this.

[0241] As shown in FIG. 22B, the circuit 310_1 includes a transistor 311_1 and a transistor In addition to the transistor 312_1, a transistor 313_1 and a transistor 314_1 are provided. A first terminal of the transistor 313_1 is connected to the wiring 113. A second terminal of the transistor 313_1 is connected to the gate of the transistor 301_1. The gate of the transistor 313_1 is connected to the second terminal of the transistor 311_1 and the The transistor 311_1 and the transistor 312_1 are connected to a second terminal of the transistor 311_1 and a second terminal of the transistor 312_1. The transistor 31 is an N-channel type. However, this is not limited to this. 1_1 and / or transistor 312_1 may be of P-channel type. The transistor 313_1 supplies the voltage supplied to the wiring 113 to the transistor 301_1. It has a function to control the timing of supplying the bootstrap transistor or switch. The first terminal of the transistor 314_1 can function as a , and the second terminal of the transistor 314_1 is connected to the second terminal of the transistor 313_1. The gate of the transistor 314_1 is connected to a node n1. The transistor 314_1 changes the connection between the wiring 117 and the transistor 301_1 in response to the potential of the node n1. By controlling the conductive state, the voltage V1 is supplied to the gate of the transistor 301_1. The input / output terminal has a function of controlling the timing at which the input / output terminal is turned on and can function as a switch.

[0242] The first terminal of the transistor 313_1 can be connected to various wirings. For example, the first terminal of the transistor 313_1 is connected to the wiring 112 or the wiring 118. However, the present invention is not limited to this.

[0243] The first terminal of the transistor 314_1 can be connected to various wirings. For example, the first wiring of the transistor 314_1 may be connected to the wiring 115_2. It is possible, but not limited to this.

[0244] In FIG. 22B, as shown in FIG. 22C, A capacitive element 315_1 can be connected between the port and the second terminal.

[0245] As shown in FIG. 22D, the circuit 300 includes a transistor 316_1. A first terminal of the transistor 316_1 is connected to the wiring 117. The second terminal of the transistor 316_1 is connected to the gate of the transistor 301_1. The gate of the transistor 316_1 is connected to the wiring 114. However, the transistor 316_1 is not limited to a P-channel type. The transistor 316_1 can be a channel type. By controlling the conduction state between 117 and the gate of transistor 301_1, The output of the output of the transistor 301_1 is supplied to the transistor 301_2.

[0246] As in FIG. 22D, the first terminal is also connected to the wiring 117 in FIGS. 22B to 22C. The second terminal is connected to the gate of the transistor 301_1, and the gate is connected to the wiring 11. It is possible to newly add a transistor 316_1 connected to 4.

[0247] Next, an example of a circuit 310_2 is shown in FIG. The first terminal of the transistor 311_2 is , the second terminal of the transistor 311_2 is connected to the wiring 113, The gate of the transistor 311_2 is connected to the wiring 113. A first terminal of the transistor 312_2 is connected to the wiring 117. The second terminal of the transistor 301_2 is connected to the gate of the transistor 312_2. The gate of the transistor 311_2 is connected to the node n2. The transistor 31 is an N-channel type. However, this is not limited to this. 1_2 and / or transistor 312_2 may be P-channel type. The transistor 311_2 is connected to the transistor 301_2 when the gate potential of the transistor 301_2 is approximately equal to V1. When the potential of the gate of the transistor 301_2 is increased, the diode The transistor 312_2 can function as a transistor in response to the potential of the node n2. By controlling the conduction state between the wiring 117 and the transistor 301_2, the voltage The timing of supplying V1 to the gate of the transistor 301_2 is controlled. It is possible for the cascade to function as a switch.

[0248] The operation of the circuit 310_2 shown in FIG. 23A will be described. In this case, the potential of the node n2 becomes higher than the threshold voltage of the transistor 312_2. The transistor 312_2 is turned on. By making the channel width of the transistor 301 larger than that of the transistor 311_2, The potential of the gate of transistor 301_2 is approximately V1. The potential is the potential of the wiring 117 (V1) and the threshold voltage of the transistor 301_2 (Vth301 _2) is smaller than the sum of period A2, period B2, period C1, period C2, period D In the periods D1, D2, E1, and E2, the potential of the node n2 is approximately V1. Therefore, the transistor 312_2 is turned off. The potential of the transistor 311_2 is changed from the potential of the wiring 113 (V2) to the threshold voltage of the transistor 311_2 (Vth 311_2), the value is (V2-Vth311_2).

[0249] The channel width of the transistor 312_2 is It is preferably 2 times or more, and more preferably 4 times or more. Preferably, the ratio is 8 times or more, but is not limited thereto.

[0250] Note that the gate and the first terminal of the transistor 311_2 may be connected to various wirings. For example, the gate and the first terminal of the transistor 311_2 may be connected to the wiring 112 or It is possible to connect to the wiring 118. However, this is not a limitation.

[0251] The first terminal of the transistor 312_2 can be connected to various wirings. For example, the first terminal of the transistor 312_2 may be connected to the wiring 115_1. It is possible, but not limited to this.

[0252] As shown in FIG. 23B, the circuit 310_2 includes a transistor 311_2 and a transistor In addition to the transistor 312_2, a transistor 313_2 and a transistor 314_2 are provided. A first terminal of the transistor 313_2 is connected to the wiring 113. A second terminal of the transistor 313_2 is connected to the gate of the transistor 301_2. The gate of the transistor 313_2 is connected to the second terminal of the transistor 311_2 and the The transistor 311_2 and the transistor 312_2 are connected to a second terminal of the transistor 311_3 and a second terminal of the transistor 312_4. The transistor 31 is an N-channel type. However, this is not limited to this. 1_2 and / or transistor 312_2 may be of P-channel type. The transistor 313_2 supplies the voltage supplied to the wiring 113 to the transistor 301_2. It has a function to control the timing of supplying the bootstrap transistor or switch. The transistor 314_2 can function as a By controlling the conduction state between the wiring 117 and the transistor 301_2, the voltage The timing of supplying V1 to the gate of the transistor 301_2 is controlled. It is possible for the cascade to function as a switch.

[0253] The first terminal of the transistor 313_2 can be connected to various wirings. For example, the first terminal of the transistor 313_2 is connected to the wiring 112 or the wiring 118. However, the present invention is not limited to this.

[0254] The first terminal of the transistor 314_2 can be connected to various wirings. For example, the first wiring of the transistor 314_2 may be connected to the wiring 115_1. It is possible, but not limited to this.

[0255] As shown in FIG. 23C, a transistor 313_2 is provided between the gate and the second terminal thereof. , the capacitive element 315_2 can be connected.

[0256] As shown in FIG. 23D, the circuit 300 includes a transistor 316_2. A first terminal of the transistor 316_2 is connected to the wiring 117. The second terminal of the transistor 316_2 is connected to the gate of the transistor 301_2. The gate of the transistor 316_2 is connected to the wiring 114. However, the transistor 316_2 is not limited to a P-channel type. The transistor 316_2 can be a channel type. By controlling the conduction state between 117 and the gate of transistor 301_2, The output of the output of the transistor 301_2 is supplied to the transistor 301_3.

[0257] As in FIG. 23D, the first terminal is also connected to the wiring 117 in FIGS. 23B to 23C. The second terminal is connected to the gate of the transistor 301_2, and the gate is connected to the wiring 11. It is possible to newly add a transistor 316_2 connected to 4.

[0258] Next, an example of a circuit 320 is shown in FIG. A first terminal of the transistor 321 is connected to the wiring 113. The second terminal of the transistor 321 is connected to the gate of the transistor 302. A gate of the transistor 321 is connected to the wiring 113. A first terminal of the transistor 322 is The second terminal of the transistor 322 is connected to the wiring 117. The gate of the transistor 322 is connected to the wiring 111. The transistor 21 and the transistor 322 are assumed to be N-channel type. However, this is not limiting. and the transistor 321 and / or the transistor 322 are P-channel type. The transistor 321 is connected to the transistor 302 when the potential of the gate of the transistor 302 is approximately equal to the potential of the gate of the transistor 321. When the potential of the gate of the transistor 302 becomes V1, the potential of the gate of the transistor 302 is increased. The transistor 322 can function as a transistor in response to the potential of the wiring 111. Therefore, by controlling the conduction state between the wiring 117 and the transistor 302, the voltage V1 The switch 302 has a function of controlling the timing at which the input of the transistor 302 is supplied with the It is possible for the system to function as such.

[0259] The operation of the circuit 320 shown in FIG. 24A will be described. In the period B2, the potential of the wiring 111 becomes higher than the threshold voltage of the transistor 322. Therefore, the transistor 322 is turned on. By making the channel width of the transistor 321 larger than that of the transistor 302, The gate potential is approximately V1. For example, the gate potential of transistor 302 is The sum of the potential of the line 117 (V1) and the threshold voltage of the transistor 302 (Vth302) is The value becomes small. Period A1, Period A2, Period C1, Period C2, Period D1, Period D2, Period In the periods E1 and E2, the potential of the wiring 111 is approximately V1. Therefore, the potential of the gate of the transistor 302 is equal to the potential of the wiring 113. The value obtained by subtracting the threshold voltage (Vth321) of the transistor 321 from the h321).

[0260] The channel width of the transistor 322 is at least twice as large as that of the transistor 321. It is preferable that the ratio is 4 times or more. It is even more preferable that the ratio is 4 times or more. Preferably, the ratio is 8 times or more, but is not limited to this.

[0261] The gate and the first terminal of the transistor 321 can be connected to various wirings. For example, the gate and the first terminal of the transistor 321 are connected to the wiring 112 or the wiring 11 8, but is not limited to this.

[0262] The first terminal of the transistor 322 can be connected to various wirings. For example, a first wiring of the transistor 322 can be connected to the wiring 112. However, this is not limited to this.

[0263] As shown in FIG. 24B, the circuit 320 includes a transistor 321 and a transistor In addition to transistor 322, transistor 323 and transistor 324 may be included. A first terminal of the transistor 323 is connected to the wiring 113. The terminal is connected to the gate of the transistor 302, and the gate of the transistor 323 is connected to the The second terminal of the transistor 321 is connected to the second terminal of the transistor 322. A first terminal of the transistor 324 is connected to a second terminal of the transistor 323. The second terminal of the transistor 324 is connected to the wiring 117, and the gate of the transistor 324 is connected to the wiring 111. The transistor 323 and the transistor 324 are assumed to be N-channel types. However, the present invention is not limited to this. The transistor 323 can be a P-channel type. The timing of supplying the voltage to the transistor 302 is controlled by the bootstrap circuit. It can function as a trap transistor or a switch. Transistor 3 24 indicates a line 117 and a gate of a transistor 302 that are electrically connected to each other depending on the potential of the line 111. By controlling the state, the timing of supplying voltage V1 to the gate of transistor 302 is determined. The MOSFET has a function of controlling the switching of the MOSFET and can function as a switch.

[0264] The first terminal of the transistor 323 can be connected to various wirings. For example, the first wiring of the transistor 323 may be connected to the wiring 112 and the wiring 118. It is possible, but not limited to this.

[0265] The first terminal of the transistor 324 can be connected to various wirings. For example, a first terminal of the transistor 324 can be connected to the wiring 118 .

[0266] As shown in FIG. 24C, in addition to the configuration shown in FIG. 24B, a transistor 323 A capacitive element 325 may be connected between the gate and the second terminal.

[0267] As shown in FIG. 24D, the circuit 320 may include a transistor 326. The first terminal of the transistor 326 is connected to the wiring 117. The second terminal of the sixth input terminal is connected to the gate of the transistor 302 and to the gate of the transistor 326. is connected to the wiring 114. The transistor 326 is an N-channel type. However, without being limited thereto, the transistor 326 can be a P-channel type. The transistor 326 is connected to the gate of the wiring 117 and the transistor 302 in response to the signal SP. Voltage V1 is supplied to transistor 302 by controlling the conduction state between It has the function of controlling the timing of

[0268] As in FIG. 24(D), the first terminal is also connected to the wiring 117 in FIGS. 24(B) to (C). The second terminal is connected to the gate of the transistor 302, and the gate is connected to the wiring 114. It is possible to add a new connected transistor 326 .

[0269] Next, FIG. 25A illustrates an example of a circuit 330. The circuit 330 includes a transistor 331. , a transistor 332, and a transistor 333. The first terminal of the transistor 331 is , the second terminal of the transistor 331 is connected to the wiring 113, A gate of the transistor 301_2 and a gate of the transistor 302 are connected to the gate of the transistor 301_3. The gate of the transistor 331 is connected to the wiring 113. The first terminal of the transistor 332 is connected to the wiring 117, and the second terminal of the transistor 331 The gate of the transistor 332 is connected to the second terminal of the transistor 333 and the gate of the transistor 334 is connected to the node n1. A first terminal of the transistor 333 is connected to the wiring 117, and a second terminal of the transistor 333 is , the second terminal of the transistor 331, and the gate of the transistor 333 is connected to a node n 2. The transistors 331, 332, and 333 are The transistor 331 is an N-channel type. However, the present invention is not limited to this. The transistor 332 and the transistor 333 may be of the P-channel type.

[0270] The operation of the circuit 330 shown in FIG. 25A will be described. In the periods A2, B1, and B2, the potential of the node n1 or the potential of the node n2 is Since the threshold voltage of the transistor 332 or the transistor 333 is higher than that of the transistor 332 or the transistor 333, At this time, the transistor 332 or the transistor 333 is turned on. The channel width of the transistor 333 is made larger than the channel width of the transistor 331. As a result, the gate of the transistor 301_1, the gate of the transistor 301_2, and the The potential of the gate of the transistor 302 becomes approximately V1. In the periods D2, E1, and E2, the potential of the node n1 and the potential of the node n2 becomes approximately V1, so that transistors 332 and 333 are turned off. Therefore, the gate of the transistor 301_1, the gate of the transistor 301_2, and the The potential of the gate of the transistor 302 is changed from the potential of the wiring 113 (V2) to the potential of the transistor 331 The threshold voltage (Vth331) of the In this case, Vx is greater than 0.

[0271] Note that the channel width of the transistor 332 or the channel width of the transistor 333 is It is preferable that the width of the channel of the transistor 331 is two times or more. More preferably, it is four times or more. More preferably, it is 8 times or more. However, This is not limited to the above.

[0272] The gate and the first terminal of the transistor 331 can be connected to various wirings. For example, the gate and the first terminal of the transistor 331 are connected to the wiring 112 or the wiring 11 8, but is not limited to this.

[0273] Note that the gates of the transistors 332 and 333 are connected to various wirings. For example, the gate of the transistor 332 can be connected to the wiring 114. The gate of the transistor 333 can be connected to the wiring 111. , but is not limited to this.

[0274] The first terminal of the transistor 332 and the first terminal of the transistor 333 are connected to separate wirings. For example, the first terminal of the transistor 332 can be connected to the wiring 11. A first terminal of the transistor 333 is connected to the wiring 115_1. However, the present invention is not limited to the above.

[0275] As shown in FIG. 25B, the circuit 330 includes a transistor 331, a transistor 3 In addition to transistor 32 and transistor 333, transistor 334, transistor 335, and A first terminal of the transistor 334 may be connected to the line 113, and the second terminal of the transistor 334 is connected to the gate of the transistor 301_1. , a gate of the transistor 301_2 and a gate of the transistor 302 are connected to the transistor The gate of the transistor 334 is connected to the second terminal of the transistor 331. A first terminal of the transistor 335 is connected to the wiring 117, and a second terminal of the transistor 335 is connected to the The gate of the transistor 335 is connected to the second terminal of the transistor 334, and the gate of the transistor 335 is connected to the node n1. The first terminal of the transistor 336 is connected to the wiring 117. The second terminal of the transistor 334 is connected to the gate of the transistor 336. The transistor 334, the transistor 335, and the transistor The transistor 336 is assumed to be an N-channel type. However, it is not limited to this. The transistors 334, 335, and 336 are P-channel types. It is possible.

[0276] Note that a capacitance element can be connected between the gate and the second terminal of the transistor 334. It is.

[0277] The first terminal of the transistor 334 can be connected to various wirings. For example, the first terminal of the transistor 334 may be connected to the wiring 112 or the wiring 118. It is possible, but not limited to this.

[0278] Note that the gates of the transistors 335 and 336 are connected to various wirings. For example, the gate of the transistor 335 can be connected to the wiring 114. The gate of the transistor 336 can be connected to the wiring 111. However, the present invention is not limited to this.

[0279] The first terminal of the transistor 335 and the first terminal of the transistor 336 are connected to separate wirings. For example, the first terminal of the transistor 335 can be connected to the wiring 11. A first terminal of the transistor 336 is connected to the wiring 115_1. However, the present invention is not limited to the above.

[0280] Here, an example of a semiconductor device in which the contents described in the first to third embodiments are appropriately combined is shown in FIG. 41. However, the present invention is not limited to this, and may be applied to other embodiments described in the first to third embodiments. The semiconductor device can be configured in various ways by combining the components.

[0281] The semiconductor device of FIG. 41 includes a circuit 100 and a circuit 10. The circuit 10 includes a circuit 200 and The semiconductor device in FIG. 41 includes a circuit 300, which includes a circuit 330. The circuit 100 has the configuration shown in FIG. 4A, and the circuit 200 has the configuration shown in FIG. The circuit 300 has a configuration shown in FIG. 19C. The circuit 330 has a configuration shown in FIG. For this purpose, the configuration shown in FIG.

[0282] Furthermore, the operation of the semiconductor device shown in Fig. 41 was verified. The verification results are shown in Fig. 42. 42 is a diagram showing the verification result of the semiconductor device of this embodiment. The test was performed using an E simulator. As a comparative example, the transistor of the semiconductor device shown in FIG. transistor 101_2, transistor 201_2, transistor 203_1, transistor 20 3_2, transistor 301_2, transistor 303_2, transistor 333, and The operation of a semiconductor device having a circuit configuration without the transistor 336 was also verified. The verification was performed with Vdd = 30V, Vss = 0V, and clock frequency = 25kHz (1 cycle = 20 μsec), mobility of each transistor = 1cm 2 / VS, threshold voltage of each transistor = 5 The test was performed with V and output capacitance set to 50 pF.

[0283] FIG. 42A is a timing chart showing the verification results for the semiconductor device of the comparative example. As shown in FIG. 42(A), in the semiconductor device of the comparative example, the node n The transistor 101_1 is turned on in response to the potential of the line 1, and the wiring 112 and the wiring 111 are connected to each other. The transistor 101_1 is turned on, and the signal CK1 is supplied from the wiring 112 to the transistor The signal is supplied to the wiring 111 via the star 101_1.

[0284] FIG. 42B is a timing chart showing the verification results of the semiconductor device shown in FIG. As shown in FIG. 42B, in the semiconductor device shown in FIG. 41, in the period T1, The transistor 101_1 is turned on in response to the potential of the transistor The transistor 101_1 is turned on, and the signal CK1 is input from the wiring 112 to the transistor is supplied to the wiring 111 through the capacitor 101_1, and in the period T2, The transistor 101_1 is turned on, and the wiring 112 and the wiring 111 are connected to the transistor 10 1_1, the signal CK1 is applied from the wiring 112 to the transistor 101_1. 42, the semiconductor device of this embodiment is In this case, by turning on different transistors in each period, each transistor It can be seen that the number of turns on and the time for which they are turned on can be reduced.

[0285] (Embodiment 4) In this embodiment, an example of a shift register will be described. The system can include the semiconductor device according to the first to third embodiments. The soft resistor may refer to a semiconductor device or a gate driver. The contents described in the first to third embodiments will not be described. The contents described in the third embodiment can be appropriately combined with the contents described in this embodiment. .

[0286] First, an example of a shift register will be described with reference to FIG. 0 has a plurality of flip-flops called flip-flops 501_1 to 501_N. .

[0287] The flip-flops 501_1 to 501_N are the same as those in the first to third embodiments, respectively. The semiconductor device in FIG. 26 corresponds to the semiconductor device described in the section 1. 1_N, the semiconductor device of FIG. 4A is used. The flip-flops 501_1 to 501_N are not limited to this, and may be, for example, The semiconductor device or circuit described in the first to third embodiments can be used.

[0288] Next, the connection relationship of the shift register will be described. 1_1 to 511_N, wiring 512, wiring 513, wiring 514, wiring 515_1 to 515_ 2, the wiring 516, the wiring 517, and the wiring 518. In 501_i (where i is any one of 2 to N), the wiring 111, the wiring 112, the wiring 113 , the wiring 114, the wiring 115_1, the wiring 115_2, the wiring 116, and the wiring 117 are , wiring 511_i, wiring 512, wiring 514, wiring 511_i-1, wiring 515_1, The line 515_2 is connected to the wiring 511_i+1 and the wiring 516. In many cases, the connection destination of the wiring 112 is different between the flip-flop and the even-numbered flip-flops. For example, in the flip-flop in the i-th stage, when the wiring 112 is connected to the wiring 512, In this case, the flip-flop in the (i+1)th stage or the flip-flop in the (i-1)th stage has a The line 112 is connected to the wiring 513 .

[0289] In addition, in the flip-flop 501_1, when the wiring 114 is connected to the wiring 517, In the flip-flop 501_N, the wiring 116 and the wiring 518 In many cases, however, it is not limited to this.

[0290] Next, an example of a signal or voltage input to or output from each wiring will be described. For example, signals GOUT_1 to GOUT_N are output from the inputs 1 to 511_N, respectively. The signals GOUT_1 to GOUT_N are respectively output from flip-flops 501_1 The signals GOUT_1 to GOUT_N are output signals of the signals OU Corresponding to T, output signal, selection signal, transfer signal, start signal, reset signal, gate signal The wiring 512 can function as a signal GCK1 or a scanning signal. The signal GCK1 corresponds to the signal CK1 and functions as a clock signal. It is possible to input a signal GCK2 to the wiring 513, for example. Signal GCK2 corresponds to signal CK2 and can function as an inverted clock signal. As an example, a voltage V2 is supplied to the wiring 514. As an example, signals SEL1 to SEL2 are input to 515_1 to 515_2, respectively. For example, a voltage V1 is supplied to the wiring 516. As an example, assume that a signal GSP is input. The signal GSP corresponds to the signal SP, and The wiring 518 may function as a clock signal, a vertical synchronization signal, or a vertical sync signal. The signal GRE corresponds to the signal RE and is a reset signal. These wirings can function as signals, but are not limited to these. It is also possible to input various other signals, various voltages, or various currents.

[0291] The wirings 511_1 to 511_N function as signal lines, gate signal lines, or scanning lines. The wiring 512 and the wiring 513 can be used as a signal line or a clock signal line. The wiring 514 can function as a power supply line. The wirings 515_1 to 515_2 can function as signal lines. The wiring 517 can function as a power supply line or a ground line. The wiring 518 can function as a signal line. However, this is not a limitation and these wirings can function as various other types of wiring. is possible.

[0292] In addition, the wiring 512, the wiring 513, the wiring 514, the wirings 515_1 to 515_2, and the wiring 516 A signal or a voltage is input from the circuit 520 to the wiring 517 and the wiring 518. The circuit 520 supplies a signal or voltage to the shift register to The device has a function to control the input register and functions as a control circuit or controller. is possible.

[0293] Note that the circuit 520 includes, for example, a circuit 521 and a circuit 522. The circuit 521 generates power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, and a reference voltage. The circuit 52 has a function of supplying a power to the power supply circuit or a regulator. 2 is a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a It has the function of generating various signals such as video signals and functions as a timing generator. However, the present invention is not limited to this. The circuit 520 may be a circuit 521 or a circuit 522. In addition to the circuit 22, various circuits or elements may be included. For example, the circuit 52 0 is an oscillator, a level shifter circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, AD conversion circuit, operational amplifier, shift register, look-up table, coil, transistor The input may include a resistor, a capacitance element, a resistance element, and / or a frequency divider.

[0294] Next, the operation of the shift register of FIG. 26 will be described with reference to FIG. 27. FIG. 27 is an example of a timing chart for explaining the operation of a shift register. Signal GSP, Signal GRE, Signal GCK1, Signal GCK2, Signal SEL1, Signal SEL2, Signal GOUT_1, Signal GOUT_i-1, Signal GOUT_i, Signal GOUT_i+1, and a signal GOUT_N are shown. The description of the operations common to those of the first embodiment will be omitted.

[0295] The operation of the flip-flop 501_i in the kth frame (k is a natural number) will be described. First, the signal GOUT_i-1 goes to H level. Then, the flip-flop 501_ i starts operation in period A1, and the signal GOUT_i becomes L level. Then, the flip-flop 501_ i starts the operation in period B1, and the signal GOUT_i becomes H level. _i is input to the flip-flop 501_i-1 as a reset signal, and The start signal is input to the flip-flop 501_i+1. 01_i-1 starts operation in period C1, and flip-flop 501_i+1 The operation in the period A1 starts. After that, the signals GCK1 and GCK2 are inverted again. Then, the flip-flop 501_i+1 starts its operation in the period B1, and the signal The signal GOUT_i+1 goes to H level. _i as a reset signal. Therefore, the flip-flop 501_i is Since the operation of C1 starts, the signal GOUT_i becomes L level. Then, the signal Until the signal GOUT_i-1 becomes H level, the flip-flop 501_i receives the signal GC Every time K1 and the signal GCK2 are inverted, the operation in the period D1 and the operation in the period E1 are This process is repeated.

[0296] The operation of the flip-flop 501_i in the (k+1)th frame will be described. First, The signal GOUT_i-1 becomes H level. Then, the flip-flop 501_i is in the high-level state for a period A2 starts, and the signal GOUT_i goes to the L level. Then, the signal GCK1 Then, the flip-flop 501_i is inverted in the period B2. The signal GOUT_i goes to the H level. The reset signal is input to the flip-flop 501_i-1 and the flip-flop 501_i +1 as a start signal. Therefore, the flip-flop 501_i-1 The flip-flop 501_i+1 starts its operation in the period C2, and the flip-flop 501_i+1 starts its operation in the period A2. After that, the signals GCK1 and GCK2 are inverted again. The flip-flop 501_i+1 starts its operation in period B1, and the signal GOUT_i+1 The signal GOUT_i+1 is a reset signal to the flip-flop 501_i. Therefore, the flip-flop 501_i operates in the period C2 as follows: Then, the signal GOUT_i becomes L level. Then, the signal GOUT_i-1 Until the signal GCK1 and the signal GCK Each time 2 is inverted, the operation in period D2 and the operation in period E2 are repeated.

[0297] In addition, in the flip-flop 501_1, instead of the output signal of the previous stage flip-flop, In addition, the signal GSP is input from the circuit 520 through the wiring 517. When the flip-flop 501_1 becomes the H level, the operation in the period A1 or the period A2 is Start.

[0298] In addition, in the flip-flop 501_N, instead of the output signal of the next stage flip-flop, The signal GRE is input from the circuit 520 through the wiring 518. When the flip-flop 501_N becomes the H level, the operation in the period C1 or the period C2 is Start.

[0299] As described above, the shift register of the present embodiment is the semiconductor By using the device, it is possible to obtain the same advantages as those of the semiconductor device.

[0300] It is possible to make the relationship between the signals GCK1 and GCK2 unbalanced. For example, As shown in the timing chart of FIG. 28(A), in the signals GCK1 and GCK2, It is possible to make the period during which the signal is at the H level shorter than the period during which the signal is at the L level. By this, even if delay or distortion occurs in the signals GOUT_1 to GOUT_N, It is possible to prevent the period during which these signals are at H level. When the shift register is used in a display device, it is necessary to prevent multiple rows from being selected at the same time. However, the present invention is not limited to this, and the signal GCK1 and / or the signal GCK2 may be used. In this case, the period during which the signal is at the H level can be longer than the period during which the signal is at the L level.

[0301] It is possible to input multi-phase clock signals to the shift register. For example, see Figure 2. As shown in the timing chart of 8(B), a clock signal with M phases (M is a natural number of 3 or more) is In this case, in the signals GOUT_1 to GOUT_N, The period when the signal is at the H level in one stage overlaps with the period when the signal is at the H level in the previous and next stages. Therefore, when the present embodiment is used in a display device, a plurality of rows This allows the precharging of the video signals to the pixels in the other rows. It becomes possible to use it as a voltage.

[0302] In FIG. 28(B), it is preferable that M≦8. More preferably, M≦6. It is more preferable that M≦4. When the register is used in a scanning line driving circuit of a display device, if M is too large, the pixels may be overlapped. This is because several kinds of video signals are written to the pixel. This is because the period during which the signal is input becomes longer, which may result in a decrease in display quality.

[0303] As in FIG. 28(B), the timing chart in FIG. 28(A) also shows the multi-phase clock. A lock signal may be used.

[0304] In addition, the wiring 518 and other wirings (for example, the wiring 512, the wiring 513, the wiring 515_1, the wiring 515_2, wiring 516, or wiring 517) are configured as one common wiring, and wiring 518 In this case, the wiring 116 in the flip-flop 501_N can be omitted. is the wiring 512, the wiring 513, the wiring 515_1, the wiring 515_2, the wiring 516, or the wiring 5 It is preferable that the wiring 518 is connected to the wiring 517. In addition, the wiring 518 may be omitted by using other configurations. In this case, in the flip-flop 501_N, the transistors 303_1 to It is also possible to omit 303_2 and the transistor 304.

[0305] It is possible to divide the output signal as shown in Fig. 29. In the example of Fig. 29, The flip-flops 501_1 to 501_N are each implemented by the semiconductor device shown in FIG. In the flip-flop 501_i (i is any one of 2 to N), Wiring 111, wiring 112, wiring 113, wiring 114, wiring 115_1, wiring 115_2, The wiring 116 and the wiring 117 are respectively a wiring 511_i, a wiring 512, a wiring 514, and a wiring 518_i-1, wiring 515_1, wiring 515_2, wiring 511_i+1, wiring 516, By doing so, pixel or gate signals are connected to the wirings 511_1 to 511_N. Even if a load such as a power line is connected, the transfer There is no distortion or delay in the signal. Therefore, the effect of delay in the shift register is eliminated. However, the present invention is not limited to this, and the wiring 114 can be reduced by the wiring 511_i-1 Alternatively, the wiring 116 can be connected to the wiring 517_i+1. It is possible.

[0306] (Embodiment 5) In this embodiment, an example of a display device will be described.

[0307] First, with reference to FIG. 30(A), an example of a system block of a liquid crystal display device will be described. The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_2, 2, a pixel portion 5364 having a pixel, a circuit 5365, and a lighting device 5366. In the portion 5364, a plurality of wirings 5371 are arranged extending from the circuit 5362. 5372 is disposed extending from the circuit 5363_1 and the circuit 5363_2. In addition, in the intersecting regions of the plurality of wirings 5371 and the plurality of wirings 5372, liquid crystal elements, etc. are provided. Pixels 5367 each having a display element are arranged in a matrix.

[0308] In response to a video signal 5360, a circuit 5361 outputs a signal to a circuit 5362, a circuit 5363_1, a circuit 5363_2 and the circuit 5365 have a function of supplying a signal, a voltage, a current, or the like, Controller, control circuit, timing generator, power supply circuit, regulator, etc. In this embodiment, as an example, the circuit 5361 can function as a circuit 5362, the start signal for the signal line driver circuit (SSP), the clock signal for the signal line driver circuit (SCK), inverted clock signal for signal line driver circuit (SCKB), data for video signal (D ATA) and a latch signal (LAT). Then, a start signal for the scanning line driver circuit (G SP), clock signal for the scanning line driving circuit (GCK), and clock signal for the inversion scanning line driving circuit Alternatively, the circuit 5361 may supply a buffer signal (GCKB) to the circuit 5365. However, the present invention is not limited to this, and may be applied to the circuit 5. 361 also transmits various signals, various voltages, or various currents to a circuit 5362, a circuit It is possible to supply the signal to the circuits 5363_1, 5363_2, and 5365.

[0309] The circuit 5362 receives signals (e.g., SSP, SCK, SCKB , DATA, LAT) to output video signals to a plurality of wirings 5371. The circuit 5363_1 and the circuit 536 3_2 runs according to the signals (GSP, GCK, GCKB) supplied from the circuit 5361. It has a function of outputting scanning signals to a plurality of wirings 5372 and functions as a scanning line driver circuit. In response to a signal (BLC) supplied from the circuit 5361, the circuit 5365 By controlling the amount or time of power supplied to the lighting device 5366, the lighting device It has the function of controlling the brightness (or average brightness) of the 5366 and can function as a power supply circuit. It is possible.

[0310] When video signals are input to the multiple wirings 5371, the multiple wirings 5371 The wiring can function as a line, a video signal line, a source signal line, or the like. When scanning signals are input to 5372, the multiple wirings 5372 are signal lines, scanning lines, or gate lines. It is possible for the signal line to function as a port signal line, etc. However, the present invention is not limited to this.

[0311] Note that the same signal is input to the circuit 5363_1 and the circuit 5363_2. When the input is from the line 5372, the circuit 5363_1 outputs a scanning signal to the wirings 5372. The scanning signals output from the line 5363_2 to the wirings 5372 are approximately equal in timing. Therefore, the circuit 5363_1 and the circuit 5363_2 are driven. The load can be reduced. Therefore, the display device can be made larger. The display device can have high resolution. Since the channel width of the transistor can be reduced, a display device with a narrow frame can be manufactured. However, the present invention is not limited to this, and the circuit 5361 may be connected to the circuit 5363_1. It is possible to provide separate signals to the paths 5363_1 and 5363_2.

[0312] Note that either the circuit 5363_1 or the circuit 5363_2 can be omitted. do.

[0313] In addition, in the pixel portion 5364, wiring such as a capacitance line, a power supply line, and a scanning line can be newly arranged. It is possible. The circuit 5361 can output a signal or a voltage to these wirings. Alternatively, a circuit similar to the circuit 5363_1 or the circuit 5363_2 may be newly added. This newly added circuit can transmit signals such as scanning signals to the newly added wiring. It is possible to output the following.

[0314] Note that the pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 30B, the display element can emit light, so that the circuit 5 365 and the lighting device 5366 may be omitted. In order to supply power, a plurality of wirings 5373 capable of functioning as power supply lines are provided in the pixel portion 53 64. The circuit 5361 supplies a power supply voltage (also called a voltage ANO) The wiring 5373 can be connected to each color element of the pixel. It is possible for one pixel to be connected to the other pixel, or it is possible for one pixel to be connected in common to all pixels.

[0315] Note that in FIG. 30B, as an example, the circuit 5361 includes a circuit 5363_1 and a circuit 536 3_2 is supplied with separate signals. Start signal (GSP1), clock signal for scanning line driving circuit (GCK1), and inversion scanning A signal such as a clock signal (GCKB1) for the line driving circuit is supplied to the circuit 5363_1. The circuit 5361 outputs a start signal (GSP2) for the scanning line driver circuit, Clock signal (GCK2), and inversion scan line driver clock signal (GCKB2), etc. The circuit 5363_1 supplies the signal to the circuit 5363_2. 72, and the circuit 5363_2 scans only the odd-numbered wirings of the plurality of wirings 5372. That is, only the wirings in the even rows can be scanned. Since the driving frequency of the circuit 5363_2 can be reduced, the power consumption can be reduced. Or, it is possible to increase the area in which one stage of flip-flops can be laid out. Therefore, the display device can be made high-definition. However, the present invention is not limited to this. As in FIG. 30A, the circuit 5361 can be It is possible to output the same signal to the circuit 5363_1 and the circuit 5363_2.

[0316] 30B, the circuit 5361 in FIG. 30A is the same as the circuit 5363 in FIG. It is possible to supply separate signals to circuit 5363_1 and circuit 5363_2.

[0317] The above is a description of an example of the system block of the display device.

[0318] Next, an example of the configuration of the display device will be described with reference to FIGS. This will be explained with reference to E).

[0319] In FIG. 31A, a circuit having a function of outputting a signal to a pixel portion 5364 (for example, a circuit 5 362, a circuit 5363_1, and a circuit 5363_2, etc.) are formed on the same substrate as the pixel portion 5364. The circuit 5361 is formed on a substrate different from the pixel portion 5364. This reduces the number of external parts, which can reduce costs. Since the number of signals or voltages input to the board 5380 is reduced, the connections between the board 5380 and external components are reduced. This reduces the number of connections, thereby improving reliability and yield. Cut.

[0320] In addition, when the circuit is formed on a substrate different from the pixel portion 5364, the substrate is a TAB (Ta PE Automated Bonding (FPC) method Alternatively, the substrate may be implemented in a 3D printed circuit board (PCB). The COG (Chip on Glass) method is used to mount the pixel part 5364 on the same substrate 5380. It is possible to implement it in

[0321] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is preferably made of a single crystal semiconductor. Therefore, a transistor formed on the substrate can be formed. The circuit can set the drive frequency over a wide range. For example, by increasing the drive frequency, This makes it possible to increase the number of pixels arranged in the pixel portion 5364 (by increasing the resolution). By reducing the driving voltage, power consumption can be reduced. The circuit formed on the substrate can increase the driving voltage, so that it can be used as a display element. In addition, the circuit formed on the substrate can be used as a display element having a high driving voltage. Therefore, the variation in the output signal can be reduced.

[0322] In addition, a signal, voltage, or current is input from an external circuit via an input terminal 5381. This is often the case.

[0323] In FIG. 31B, the driving frequencies of the circuit 5363_1 and the circuit 5363_2 are 1 or the driving frequency of the circuit 5362, and the transistor formed in the pixel portion A transistor formed in the same process as the transistor is used for the circuit 5363_1 and the circuit 5363_2. Therefore, the circuit 5363_1 and the circuit 5363_2 can be connected to the pixel portion 5364. The circuit 5361 and the circuit 5362 are formed on the same substrate 5380. The transistors with low mobility are formed on a different substrate from the substrate 364. This allows the circuitry to be formed on the plate 5380. The semiconductor layer is made of an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. Therefore, it is possible to increase the size of the display device, reduce the number of steps, reduce costs, or It is possible to improve yields, etc.

[0324] As shown in FIG. 31C, a part of the circuit 5362 (a circuit 5362a) is 5380, and the remaining portion of the circuit 5362 (circuit 5362b) is formed on the same substrate 5380 as the circuit 5364. The circuit 5362a can be formed on a substrate separate from the element portion 5364. Circuits that can be constructed using low-power transistors (e.g., shift registers, select In addition, the circuit 5362b has high mobility and It is preferable that the circuit is constructed of transistors having small characteristic variations (e.g., (including soft registers, latch circuits, buffer circuits, DA conversion circuits, AD conversion circuits, etc.) In this way, the semiconductor layer of the transistor and For example, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used. This makes it possible to further reduce the number of external parts.

[0325] In FIG. 31D, a circuit having a function of outputting a signal to the pixel portion 5364 (for example, the circuit 5 362, circuit 5363_1, and circuit 5363_2, etc.), and controlling these circuits A circuit having a function (for example, a circuit 5361) is formed on a substrate different from the pixel portion 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. Therefore, the yield can be improved.

[0326] As in FIG. 31D, in FIGS. 31A to 31C, the circuit 5363_1 and The circuit 5363_2 can be formed on a substrate different from that of the pixel portion 5364.

[0327] In FIG. 31E, a part of the circuit 5361 (circuit 5361a) is formed on the same substrate as the pixel portion 5364. 5380, and the remaining circuit 5361 (circuit 5361b) is formed separately from the pixel portion 5364. The circuit 5361a is formed on a substrate. They often have circuits (e.g., switches, selectors, level shifters, etc.) that can The circuit 5361b is constructed using transistors with high mobility and small variation. It is preferable to construct a circuit (e.g., a shift register, a timing generator, an oscillator, etc.) The input often has a built-in power supply, a regulator, or an analog buffer.

[0328] In addition, in FIG. 31(A) to (D), the circuit 5361a and the pixel portion 5364 are mounted on the same substrate. In addition, the circuit 5361b can be formed on a substrate different from that of the pixel portion 5364.

[0329] Here, the circuits 5363_1 and 5363_2 are the circuits according to the first to fourth embodiments. In this case, the semiconductor device or shift register of the circuit 5363_ 1, the circuit 5363_2 and the pixel portion are formed on the same substrate, All transistors formed can be of either N-channel or P-channel type. Therefore, the number of steps can be reduced, the yield can be improved, the reliability can be improved, or the cost can be reduced. In particular, when all the transistors are N-channel type, The semiconductor layer of the transistor is formed of an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide. This makes it possible to use semiconductors, etc., which leads to the enlargement of the display device, the reduction of the cost, or It is possible to improve yields, etc.

[0330] Alternatively, the semiconductor device or the shift register according to the first to fourth embodiments may include a transistor Therefore, the layout area can be reduced. This allows the frame to be smaller, or the layout area to be smaller. Therefore, the resolution can be increased.

[0331] Alternatively, the semiconductor device or shift register according to the first to fourth embodiments may reduce parasitic capacitance. Therefore, the power consumption can be reduced. The flow capacity can be reduced. Alternatively, the size of the external circuit or the The size of the display device can be reduced.

[0332] Note that an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used as the semiconductor layer. The transistors used in this case may experience degradation in characteristics, such as an increase in threshold voltage or a decrease in mobility. However, the semiconductor device or shift register according to the first to fourth embodiments This can suppress deterioration of transistor characteristics, thereby extending the life of display devices. Cut.

[0333] As a part of the circuit 5362, the semiconductor device of any one of the first to fourth embodiments or For example, the circuit 5362a may be implemented by using a register similar to that described in the first to third embodiments. The semiconductor device of the fourth aspect may have a shift register.

[0334] (Embodiment 6) In this embodiment, an example of a signal line driver circuit will be described. It may be referred to as a conductor device or a signal generating circuit.

[0335] An example of a signal line driver circuit will be described with reference to FIG. The circuit includes a plurality of circuits 602_1 to 602_N, a circuit 600, and a circuit 601. The circuits 602_1 to 602_N include transistors 603_1 to 603_k, respectively. (k is a natural number of 2 or more) The transistor 603_k is an N-channel type, but is not limited to this. The transistors 603_1 to 603_k can be of P-channel type, or of CMOS type. It is possible to use a switch.

[0336] The connection relationship of the signal line driver circuit will be described using the circuit 602_1 as an example. The first terminals of the transistors 603_1 to 603_k are connected to the wiring 605_1. The second terminals of the transistors 6_1 to 603_k are connected to the wirings S1 to Sk, respectively. The gates of the transistors 603_1 to 603_k are connected to the wirings 604_1 to 604_k, respectively. For example, a first terminal of the transistor 603_1 is connected to a wiring 605_1. A second terminal of the transistor 603_1 is connected to the wiring S1. It is connected to the line 604_1.

[0337] The circuit 600 transmits signals to the circuits 602_1 to 602_k via the wirings 604_1 to 604_k. N, and can function as a shift register, decoder, etc. The signal is often a digital signal and can function as a selection signal. The wirings 604_1 to 604_k can function as signal lines. be.

[0338] The circuit 601 has a function of outputting signals to circuits 602_1 to 602_N, and generates a video signal. For example, the circuit 601 can function as a At the same time, a signal is supplied to the circuit 602_1 via the wiring 605_2. The signal is often an analog signal and functions as a video signal. The wirings 605_1 to 605_N can function as signal lines. It is possible.

[0339] The circuits 602_1 to 602_N select which wiring the output signal of the circuit 601 is to be output to. For example, the circuit 602 has a function of selecting an input signal from the input signal. _1 indicates which of the wirings S1 to Sk the signal output from the circuit 601 to the wiring 605_1 is to be transmitted to It has the function of selecting whether to output to

[0340] The transistors 603_1 to 603_N are connected to the wiring 6 in response to the output signal of the circuit 600. 05_1 and the wiring S1 to Sk, and functions as a switch. do.

[0341] Next, the operation of the signal line driver circuit of FIG. 32(A) will be described with reference to the timing chart of FIG. 32(B). FIG. 32B shows a signal 614_1 input to a wiring 604_1. , a signal 614_2 input to the wiring 604_2, a signal 614 input to the wiring 604_k _k, a signal 615_1 input to a wiring 605_1, and a signal 615_2 input to a wiring 605_2. An example of number 615_2 is shown below.

[0342] Note that one operation period of the signal line driver circuit corresponds to one gate selection period in the display device. A gate selection period is a period during which pixels in a certain row are selected and a video signal is written to the selected pixels. This refers to the period during which it is possible to

[0343] One gate selection period is divided into a period T0 and periods T1 to Tk. is a period for simultaneously applying a precharge voltage to the pixels in the selected row. The periods T1 to Tk can function as a precharge period. This is a period for writing video signals to pixels belonging to a row that has been selected, and functions as a write period. It is possible to do this.

[0344] For convenience, the operation of the signal line driver circuit will be described using the operation of the circuit 602_1 as an example.

[0345] First, in a period T0, the circuit 600 applies an H-level signal to the wirings 604_1 to 604_k. Then, the transistors 603_1 to 603_k are turned on, so that the wiring 605 At this time, the circuit 601 is in a conductive state with the wiring 605_1 Since the precharge voltage Vp is supplied to the transistor 6, the precharge voltage Vp is The signals are output to the wirings S1 to Sk via the pre-transmitted signals 03_1 to 603_k. The charge voltage Vp is written to the pixels in the selected row, so that the charge voltage Vp is The pixels that correspond to the pixel are precharged.

[0346] Next, in a period T1, the circuit 600 outputs an H-level signal to the wiring 604_1. Then, the transistor 603_1 is turned on, so that the wiring 605_1 and the wiring S1 are in a conductive state. Then, the wiring 605_1 and the wirings S2 to Sk are in a non-conductive state. If the circuit 601 outputs a signal Data (S1) to the wiring 605_1, then the signal D The ata (S1) is output to the wiring S1 through the transistor 603_1. The signal Data(S1) is supplied to the pixels in the selected row among the pixels connected to the wiring S1. It is written in simple terms.

[0347] Next, in a period T2, the circuit 600 outputs an H-level signal to the wiring 604_2. Then, the transistor 603_2 is turned on, so that the wiring 605_2 and the wiring S2 are in a conductive state. Then, the wiring 605_1 and the wiring S1 are brought into a non-conductive state. The wirings S3 to Sk remain in a non-conductive state. At this time, the circuit 601 outputs the signal Data( S2) is output to the wiring 605_1, the signal Data (S2) is The signal Data (S1) is output to the wiring S2 via the input terminal 603_2. Of the pixels connected to line S1, those belonging to the selected row are written.

[0348] After that, until the period Tk, the circuit 600 outputs a high-level signal to the wirings 604_1 to 604_k. Since the signals are output in sequence, the signals are output in sequence from the period T3 to the period Tk in the same manner as in the periods T1 and T2. 00 outputs H-level signals to the wirings 604_3 to 604_k in sequence. Since the resistors 603_3 to 603_k are turned on in sequence, the signal output from the circuit 601 is In this way, the signals are sequentially output to the wirings S3 to Sk. It becomes possible to write.

[0349] An example of the signal line driver circuit has been described above. Since the semiconductor memory device has a circuit that functions as a connector, the number of signals or the number of wirings can be reduced. Or, before writing a video signal to the pixel (period T0), a voltage for precharging is set to Since the video signal is written to the pixel, the time required for writing the video signal can be shortened. It is possible to increase the size of the display device and to increase the resolution of the display device. However, the present invention is not limited to this. , it is possible to omit period T0 and not precharge the pixel.

[0350] If k is too large, the time it takes to write to the pixel becomes too short, so the time it takes to write to the pixel of the video signal becomes too short. Writing may not finish in time, so k≦6 is preferred. More preferably, k≦3. Further preferably, k=2. It is.

[0351] In particular, if the pixel color components are divided into n, it is possible to make k=n. For example, If the color components of a pixel are divided into three, red (R), green (G), and blue (B), then k=3. In this case, one gate selection period is made up of a period T0, a period T1, a period T2, and a period T3. In the periods T1, T2, and T3, the red (R) image is It is possible to write video signals to the green (G) pixels and blue (B) pixels. However, the order of the periods T1, T2, and T3 can be set arbitrarily. It is.

[0352] In particular, a pixel has n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or sub-pixels). For example, if a pixel is divided into two sub-pixels, k=n. In this case, one gate selection period is a period T In the period T1, one of the two sub-pixels In the period T1, a video signal is written to the other of the two sub-pixels. It is possible.

[0353] The driving frequencies of the circuit 600 and the circuits 602_1 to 602_N are compared with the circuit 601. Therefore, the circuit 600 and the circuits 602_1 to 602_N are the same as the pixel section. In this way, the substrate on which the pixel portion is formed and the substrate on which the external circuit is formed can be formed on the same substrate. Since the number of connections can be reduced, it is possible to improve yield and reliability. Furthermore, as shown in FIG. 31(A) to (E), the scanning line driver circuit is also formed on the same substrate as the pixel section. By forming it on a plate, the number of connections to external circuits can be further reduced.

[0354] The circuit 600 may be a semiconductor device or a shift register according to any one of the first to fourth embodiments. In this case, the polarity of all the transistors in the circuit 600 can be changed to It can be made into either an N-channel type or a P-channel type. Therefore, the number of processes can be reduced. The yield can be improved or the cost can be reduced.

[0355] In addition to the circuit 600, all the transistors included in the circuits 602_1 to 602_N are The polarity of the transistor can be either N-channel or P-channel. 00, and when the circuits 602_1 to 602_N are formed on the same substrate as the pixel portion, the number of steps In particular, it is possible to reduce the number of transistors, improve the yield, and reduce the cost. By making the polarity of the transistor N-channel type, the semiconductor layer of the transistor can be made of, for example, An amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. .

[0356] (Embodiment 7) In this embodiment, a pixel configuration and pixel operation that can be applied to a liquid crystal display device will be described. explain.

[0357] 33A shows an example of a pixel. The pixel 3020 includes a transistor 3021, a liquid crystal element The first terminal of the transistor 3021 is The second terminal of the transistor 3021 is connected to a wiring 3031. and one electrode of the capacitor 3023; and The other electrode of the liquid crystal element 3022 is connected to the electrode 3034. The other electrode of the capacitor 3023 is connected to a wiring 3033 .

[0358] For example, a video signal can be input to the wiring 3031. For example, a scan signal, a selection signal, or a gate signal may be input to the input terminal 2. For example, a constant voltage can be supplied to the wiring 3033. As an example, the 034 may be supplied with a constant voltage. The line 3031 is not fixed, and a precharge voltage is supplied to the line 3031, thereby It is possible to shorten the writing time. Alternatively, a signal is input to the wiring 3033. By this, it is possible to control the voltage applied to the liquid crystal element 3022. By inputting a signal to electrode 3034, frame inversion driving can be realized. be.

[0359] The wiring 3031 can function as a signal line, a video signal line, or a source signal line. The wiring 3032 can function as a signal line, a scanning line, or a gate signal line. The wiring 3033 can function as a power supply line or a capacitance line. The electrode 3034 can function as a common electrode or a counter electrode. When a voltage is supplied to the wiring 3031 and the wiring 3032, these wirings are not limited to the above. 3033. Alternatively, when a signal is input to the wiring 3033, The wiring 3033 can function as a signal line.

[0360] The transistor 3021 controls the electrical continuity between the wiring 3031 and one electrode of the liquid crystal element 3022. By controlling the timing of writing a video signal to the pixel, The capacitor element 3023 can function as a switch. A potential difference is maintained between the electrode on the other side and the wiring 3033, and the voltage applied to the liquid crystal element 3022 is The capacitance C has a function of keeping the capacitance C constant and functions as a storage capacitor. However, the present invention is not limited to this.

[0361] FIG. 33B is a timing chart for explaining the operation of the pixel of FIG. 33A. FIG. 33B shows an example of a signal 3042_j (j is a natural number), a signal 3042_j+1 , signal 3041_i, signal 3041_i+1, and voltage 3043. In (B), the kth (k is a natural number) frame and the k+1th frame are shown. 42_j, ​​signal 3042_j+1, signal 3041_i, signal 3041_i+1, and voltage 3043 indicates a signal input to the jth line 3032, and 3044 indicates a signal input to the jth line 3032. a signal input to the wiring 3031 in the i-th column, a signal input to the wiring 3031 in the i+1-th column, 30 is an example of a signal to be input to the line 3032 and a voltage to be supplied to the line 3033.

[0362] The operation of the pixel 3020 in the jth row and the ith column will be described. When this occurs, the transistor 3021 is turned on. Since the signal 3041_j is connected to one electrode of the transistor 3022, The signal is input to one electrode of the liquid crystal element 3022 through a capacitor 3023. At this time, the potential difference between the potential of one electrode of the liquid crystal element 3022 and the potential of the wiring 3033 is maintained. Therefore, the liquid crystal element 302 is maintained at the H level until the signal 3042_j becomes H level again. The voltage applied to the liquid crystal element 3022 is constant. It expresses a gradation of tones.

[0363] In FIG. 33B, a positive polarity signal and a negative polarity signal are alternately arranged for each row selection period. This shows an example of a case where a signal is input to a line 3031. A positive signal is a signal whose potential is equal to or greater than a reference value (for example, A signal with a negative polarity is a signal with a potential higher than the reference potential (the potential of the electrode 3034). (for example, the potential of electrode 3034). However, this is not limited to this. The signal input to the wiring 3031 can have the same polarity during one frame period. do.

[0364] In addition, in FIG. 33(B), the polarity of the signal 3041_i and the polarity of the signal 3041_i+1 are different. The following shows an example of a case where the polarity and the phase of the signal 3041_i are different from each other. However, the present invention is not limited to this. The polarity of signal 3041_i+1 may be the same.

[0365] In addition, in FIG. 33B, there are periods when the signal 3042_j is at H level and periods when the signal 3042_j This is an example of a case where the period when +1 is at H level does not overlap. However, this is not limited to this. As shown in FIG. 33C, the signal 3042_j is at the H level and the signal 30 It is possible for the period during which the line 303_j+1 is at the H level to overlap with the period during which the line 303_j+1 is at the H level. It is preferable that signals of the same polarity are supplied to all of the inputs during one frame. The pixel in the j+1th row is written to the pixel in the jth row using the signal 3041_j written to the pixel in the jth row. This allows the time it takes to write a video signal to the pixel to be shortened. Therefore, the display device can have high resolution. Alternatively, the wiring 3031 may be connected to the same polarity in one frame period. Since the signal is input, power consumption can be reduced.

[0366] In addition, when the pixel configuration of FIG. 34(A) and the timing chart of FIG. 33(C) are combined, In this way, dot inversion driving can be realized. The pixel 3020(i, j) is connected to the wiring 3031_i. j+1) is connected to the wiring 3031_i+1. In this way, the i-th row is connected to the wiring 3031_i and the wiring 3031_i+1 alternately. The pixels belonging to each eye are written with positive and negative polarity signals alternately, row by row. In this case, dot inversion driving can be realized. However, this is not limited to this. The pixels are arranged in a plurality of rows (for example, two or three rows) alternately with the wiring 3031_i and the wiring 3031 _i+1.

[0367] As a pixel configuration, a sub-pixel structure can be used. 34(C) shows a configuration in which a pixel is divided into two sub-pixels. B) is 1S+2G (for example, one signal line and two scan lines are used per subpixel) FIG. 34(C) shows a subpixel structure called 2S+1G (e.g., 1 subpixel). A subpixel structure called a 3D pixel (using two signal lines and one scan line per pixel) The sub-pixel 3020A and the sub-pixel 3020B correspond to the pixel 3020. The transistor 3021A and the transistor 3021B correspond to the transistor 3021. The liquid crystal element 3022A and the liquid crystal element 3022B correspond to the liquid crystal element 3022. The wiring 3031A and the capacitance element 3023B correspond to the capacitance element 3023. The wiring 3031A and the wiring 3031B correspond to the wiring 3031. The wiring 3032A and the wiring 3032B correspond to the wiring 3031. Corresponding to wiring 3032.

[0368] Here, the pixel of the present embodiment, the semiconductor device of the first to sixth embodiments, and the shift register By combining it with a display, a display device, or a signal line driver circuit, various advantages are obtained. For example, when a subpixel structure is used as a pixel, the display device is driven This increases the number of gate signal lines or the number of source The number of signal lines increases. As a result, the number of connections between the substrate on which the pixel unit is formed and the external circuitry increases. However, even if the number of gate signal lines increases, As shown in FIG. 1, the scanning line driver circuit can be formed on the same substrate as the pixel portion. This allows the sub-pixels to be connected without significantly increasing the number of connections between the substrate on which the pixel part is formed and the external circuits. A pixel having a cell structure can be used. By using the signal line driver circuit of FIG. 6, the number of source signal lines can be reduced. Therefore, the number of connections between the substrate on which the pixel unit is formed and the external circuitry can be reduced significantly. A pixel having a sub-pixel structure can be used.

[0369] Or, when inputting a signal to a capacitance line, the number of connections between the substrate on which the pixel unit is formed and the external circuit is Therefore, the semiconductor of the first to fifth embodiments is used for the capacitance line. The signals can be provided using a logic device or a shift register. The semiconductor device or the shift register of the first to fifth embodiments may be formed on the same substrate as the pixel section. Therefore, the number of connections between the substrate on which the pixel unit is formed and the external circuit can be greatly reduced. A signal can be input to the capacitance line without increasing the capacitance.

[0370] Alternatively, when AC driving is used, the time required for writing a video signal to a pixel becomes short. As a result, there may not be enough time to write the video signal to the pixels. In addition, when using pixels with a subpixel structure, the time required to write a video signal to the pixel is shortened. As a result, there may be insufficient time to write the video signal to the pixels. Therefore, it is possible to write a video signal to the pixel by using the signal line driver circuit of the sixth embodiment. In this case, a precharge voltage is applied to the pixel before the video signal is written to the pixel. Since the video signal is written to the pixel in a short time, the video signal can be written to the pixel in a short time. ), the period in which one row is selected can be overlapped with the period in which another row is selected. Therefore, it is possible to use a video signal of another row as a precharge voltage.

[0371] (Embodiment 8) In this embodiment, an example of a display device will be described with reference to FIGS. In this case, a liquid crystal display device will be described as an example.

[0372] FIG. 35A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. For example, in the case of a liquid crystal display device, the pixel portion 5393 includes a pixel. The pixel has a voltage applied to the liquid crystal element set in response to an output signal from a driver circuit 5392. can be.

[0373] FIG. 35(B) shows an example of a cross section taken along line AB of FIG. 35(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. A conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and on the conductive layer 5404; A conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; A liquid crystal layer 5407 is formed on the insulating layer 5408. 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0374] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a dielectric film, a planarizing film, or a wiring. The insulating layer 5408 can function as a polarizer or a reflector. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0375] Here, parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. Or, the power consumption becomes large. However, as shown in FIG. An insulating layer 5408 capable of functioning as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance between the driving circuit 5392 and the conductive layer 5409 is reduced. This is because the dielectric constant of the sealant is often lower than that of the liquid crystal layer. Therefore, the output signal of the driver circuit 5392 or the potential of each node may become dull. Alternatively, the delay can be reduced. Alternatively, the power consumption of the driver circuit 5392 can be reduced. can.

[0376] As shown in FIG. 35C, a sealing material is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. Parasitic capacitance occurring between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the potential of each node. However, the present invention is not limited to this. It is possible that the insulating layer 5408 is not formed.

[0377] The display element is not limited to a liquid crystal element, and may be any of various display elements such as an EL element or an electrophoretic element. It is possible to use a display element.

[0378] In the above, an example of the cross-sectional structure of the display device has been described in the present embodiment. and a semiconductor device or shift register according to any one of the first to fourth embodiments. For example, a semiconductor layer of a transistor can be formed using an amorphous semiconductor, a microcrystalline semiconductor, When an organic semiconductor or an oxide semiconductor is used, the channel width of the transistor becomes large. However, if the parasitic capacitance of the drive circuit can be reduced as in this embodiment, The channel width of the transistor can be reduced, which reduces the layout area. Since the size of the frame of the display device can be reduced, the display device can be made high-precision. It can be thinned.

[0379] (Embodiment 9) In this embodiment, examples of the structure of a transistor will be described with reference to FIGS. ) will be referred to for explanation.

[0380] FIG. 36(A) is a diagram showing an example of the structure of a display device, and shows a top-gate transistor. FIG. 36(B) is a diagram showing an example of the structure of a display device. Also, an example of a structure of a bottom-gate transistor or an example of a structure of a display device is shown. FIG. 36(C) shows one structure of a transistor manufactured using a semiconductor substrate. FIG.

[0381] An example of a transistor in FIG. 36(A) is formed on a substrate 5260 with an insulating layer 5261 interposed therebetween. 5262a, 5262b, 5262c, 5262d, and 526 A semiconductor layer 5262 having a thickness of 2e and an insulating layer 52 formed to cover the semiconductor layer 5262. 63, a conductive layer 5264 formed on the semiconductor layer 5262 and the insulating layer 5263, and an insulating An insulating layer 5265 having an opening formed on the layer 5263 and the conductive layer 5264; and a conductive layer 5266 formed over the layer 5265 and in the opening of the insulating layer 5265.

[0382] An example of a transistor in FIG. 36B is a transistor including a conductive layer 5301 formed over a substrate 5300 and a 5302 formed to cover the conductive layer 5301; A semiconductor layer 5303a formed on the semiconductor layer 5302 and a A semiconductor layer 5303b and a conductive layer formed on the semiconductor layer 5303b and on the insulating layer 5302. A conductive layer 5304 and a conductive film 5305 having an opening are formed on the insulating layer 5302 and the conductive layer 5304. and a conductive layer 5305 formed on the insulating layer 5305 and in the opening of the insulating layer 5305. A layer 5306.

[0383] An example of the transistor in FIG. 36C is a semiconductor substrate having a region 5353 and a region 5355. A plate 5352, an insulating layer 5356 formed on the semiconductor substrate 5352, and a semiconductor substrate 53 An insulating layer 5354 is formed on the insulating layer 5356, and a conductive layer 535 is formed on the insulating layer 5356. 7, an insulating layer 5354, an insulating layer 5356, and a conductive layer 5357 are formed on the insulating layer 5354, the insulating layer 5356, and the conductive layer 5357, and an opening is formed. and an insulating layer 5358 having a first insulating layer 5358 and a second insulating layer 5358 formed on the first insulating layer 5358 and in the opening of the first insulating layer 5358. Thus, the region 5350 and the region 5351 each have a conductive layer 5359. A zygote is created.

[0384] When a display device is configured using the transistor in this embodiment, for example, 6(A), an opening is formed on the conductive layer 5266 and on the insulating layer 5265. and an insulating layer 5267 having an insulating layer 5268 formed on the insulating layer 5267 and in an opening of the insulating layer 5267. A conductive layer 5268 having an opening is formed on the insulating layer 5267 and the conductive layer 5268. An insulating layer 5269 having a first insulating layer 5269 and a second insulating layer 5269 formed on the first insulating layer 5269 and in an opening of the first insulating layer 5269. A light-emitting layer 5270 and a conductive layer 52 formed on the insulating layer 5269 and on the light-emitting layer 5270. 71 and it is possible to form

[0385] As shown in FIG. 36B, a conductive layer 5306 is disposed over the insulating layer 5305. A liquid crystal layer 5307 is formed on the liquid crystal layer 5307, and a conductive layer 5308 is formed on the liquid crystal layer 5307. It is possible.

[0386] The insulating layer 5261 can function as a base film. The insulating layer 5263 serves as an isolation layer (e.g., a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as a gate electrode. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are an interlayer film or a flat The conductive layer 5266, the conductive layer 5304, and the conductive layer 5 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a partition. The conductive layer 5271 and the conductive layer 5308 function as a counter electrode, a common electrode, or the like. It is possible.

[0387] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, a semiconductor substrate ( For example, a single crystal substrate (e.g., a silicon substrate), a SOI substrate, a plastic substrate, metal substrate, stainless steel substrate, substrate with stainless steel foil, tongue There are tin substrates, substrates with tungsten foil, and flexible substrates. Glass substrates Examples of such glass include barium borosilicate glass and aluminoborosilicate glass. Examples of flexible substrates include polyethylene terephthalate (PET), polyethylene naphtha Plastics such as polyether ether (PEN) and polyethersulfone (PES), or Acrylic and other flexible synthetic resins are also used. propylene, polyester, vinyl, polyvinyl fluoride, polyvinyl chloride, etc.), fibrous materials Including paper, base film (polyester, polyamide, polyimide, inorganic deposition film, Paper, etc.

[0388] The semiconductor substrate 5352 is, for example, a single crystal Si substrate having n-type or p-type conductivity. The region 5353 may be, for example, a semiconductor substrate 5352 having impurities. For example, if the semiconductor substrate 5352 is a p-type When the region 5353 has a conductivity type of n-type and functions as an n-well, On the other hand, if the semiconductor substrate 5352 has an n-type conductivity, the region 5353 has a p-type conductivity. The region 5355 has a conductivity type and functions as a p-well. It is a region doped in the plate 5352 and functions as a source region or a drain region. In the semiconductor substrate 5352, an LDD region can be formed.

[0389] Examples of the insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and oxynitride. Silicon nitride (SiOxNy) (x>y>0), silicon oxide nitride (SiNxOy) (x>y>0) The insulating layer 5261 may be a film containing oxygen or nitrogen, or a laminate structure thereof. In one example of a two-layer structure, a silicon nitride film is provided as the first insulating layer, A silicon oxide film can be provided as the second insulating layer. The insulating layer 5261 has a three-layer structure. In one example, a silicon oxide film is provided as the first insulating layer, and a silicon oxide film is provided as the second insulating layer. It is possible to provide a silicon nitride film as an insulating layer and a silicon oxide film as a third insulating layer. do.

[0390] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is a non-single Crystalline semiconductors (e.g., amorphous silicon, polycrystalline silicon, microcrystalline silicon) Semiconductors such as ZnO, InG aZnO, SiGe, GaAs, IZO, ITO, SnO, AZTO, organic semiconductors, or Carbon nanotubes, etc.

[0391] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, when impurities are added to the region 5262a, the region 5262a functions as a channel region. The impurity added to the region 5262a may be added to the region 5262b, 2c, region 5262d, or region 5262e. It is preferable that the region 5262b and the region 5262d are not included in the region 5262c or the region 5262e. The region is doped with impurities at a lower concentration than the region A and functions as an LDD region. The regions 5262b and 5262d may be omitted. The region 5262e is a region where impurities are added to the semiconductor layer 5262 at a high concentration. The gate electrode functions as a drain region.

[0392] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0393] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0394] An example of the insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 is silicon oxide (Si Ox), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y>0), nitriding acid A film containing oxygen or nitrogen, such as silicon carbide (SiNxOy) (x>y>0), or and laminated structures.

[0395] A conductive layer 5264, a conductive layer 5266, a conductive layer 5268, a conductive layer 5271, a conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 The conductive film 9 may have a single-layer structure or a multi-layer structure. Examples of these include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum (Mo). Mo, Tungsten (W), Neodymium (Nd), Chromium (Cr), Nickel (Ni ), platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt (Co), Niobium (Nb), Silicon (Si), Iron (Fe), Palladium (Pd), Carbon (C), Scandium (Sc), Zinc (Zn), Gallium (Ga), Indium (In) , tin (Sn), zirconium (Zr), and cerium (Ce). A single film of one of the elements selected from the group, or a compound containing one or more elements selected from the group, etc. The single film or compound is phosphorus (P), boron (B), arsenic (As), and and / or oxygen (O). Examples of such compounds include the above-mentioned An alloy containing one or more elements selected from a plurality of elements (e.g., ITO, IZO, Indium tin oxide with silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO ), Cadmium Tin Oxide (CTO), Aluminum Neodymium (Al-Nd), Aluminum Tungsten (Al-W), Aluminum Zirconium (Al-Zr), Aluminum Titanium Titanium (Al-Ti), Aluminum Cerium (Al-Ce), Magnesium Silver (Mg-A g), Molybdenum-niobium (Mo-Nb), Molybdenum-tungsten (Mo-W), Molyb (Mo-tantalum (Mo-Ta) and other alloy materials), or compounds of nitrogen with multiple elements (e.g. titanium nitride, tantalum nitride, molybdenum nitride, etc.) or a nitride film of one or more elements selected from the above elements and a silicide film. Compounds with silicon (e.g., tungsten silicide, titanium silicide, nickel silicide) side, aluminum silicon, molybdenum silicon silicide film, etc. Other examples include carbon nanotubes, organic nanotubes, inorganic nanotubes, and gold nanotubes. Nanotube materials include nanotubes of the genus Nanotubes.

[0396] An insulating layer 5265, an insulating layer 5267, an insulating layer 5269, an insulating layer 5305, and an insulating layer 535 An example of the insulating layer 8 is a single-layer insulating layer or a laminated structure thereof. As an example, silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride ( Oxygen such as SiOxNy (x>y>0) and silicon oxynitride (SiNxOy) (x>y>0) or a film containing nitrogen, a film containing carbon such as DLC (diamond-like carbon), or , siloxane resin, epoxy, polyimide, polyamide, polyvinylphenol, benzo Examples of the material include cyclobutene and organic materials such as acrylic.

[0397] An example of the light-emitting layer 5270 is an organic EL element or an inorganic EL element. An example of the element includes a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, and a hole transport layer made of a hole transport material. a light-emitting layer made of a light-emitting material; an electron transport layer made of an electron transport material; A single layer structure of an electron injection layer, etc., or a layer in which a plurality of these materials are mixed, or Often these include laminated structures.

[0398] An example of the liquid crystal layer 5307, an example of a liquid crystal material applicable to the liquid crystal layer 5307, or the liquid crystal layer 530 Examples of liquid crystal modes that can be applied to liquid crystal elements including 7 include nematic liquid crystal, cholesteric liquid crystal, and the like. Liquid crystals, smectic liquid crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals Clyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), Ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal, side chain polymer liquid crystal, plasma addressed liquid crystal (P ALC), banana type LCD, TN (Twisted Nematic) mode, STN (S upper Twisted Nematic mode, IPS (In-Plane-Sw fringe field switching mode, FFS (Fringe Field Switching) mode mode, MVA (Multi-domain Vertical Alignment) mode code, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Sym metric aligned Micro-cell) mode, OCB (Optica) l Compensated Birefringence mode, ECB (Electronic (Frequently Controlled Birefringence) mode, FL C (Ferroelectric Liquid Crystal) mode, AFLC ( AntiFerroelectric Liquid Crystal) mode, PDL C (Polymer Dispersed Liquid Crystal) mode, These include Stormhost mode and Blue Phase mode.

[0399] Note that an insulating layer functioning as an alignment film was provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0400] Note that a color filter, a black matrix, or a protrusion is provided on the conductive layer 5308. An insulating layer or the like that functions as a conductive layer can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0401] The transistor of this embodiment can be applied to the first to eighth embodiments. In particular, in FIG. 36(B), the semiconductor layer is made of an amorphous semiconductor, a microcrystalline semiconductor, an organic When a semiconductor or an oxide semiconductor is used, the transistor may deteriorate. Therefore, the transistor of this embodiment can be used in a semiconductor device, a shift register, or a display device. However, the semiconductor devices according to the first to eighth embodiments have a shorter life span. In a semiconductor device, a shift register, or a display device, deterioration of a transistor can be suppressed. Therefore, the transistor of this embodiment can be used as the semiconductor device of the first to eighth embodiments. By applying it to a device, a shift register, or a display device, the life of these devices can be increased. It is possible.

[0402] (Embodiment 10) In this embodiment, an example of a manufacturing process of a transistor and a capacitor will be described. A manufacturing process in the case where an oxide semiconductor is used for the layer will be described.

[0403] Referring to FIGS. 37A to 37C, an example of a manufacturing process of a transistor and a capacitor will be described. 37A to 37C show a transistor 5441 and a capacitor 5442. The transistor 5441 is an example of an inverted staggered thin film transistor. a wiring is provided over the oxide semiconductor layer with a source electrode or a drain electrode interposed therebetween, This is an example of a transistor.

[0404] First, a first conductive layer is formed on the entire surface of the substrate 5420 by sputtering. A resist mask formed by a photolithography process using a first photomask is used. Then, the first conductive layer is selectively etched to form a conductive layer 5421 and a conductive layer 5422. The conductive layer 5421 can function as a gate electrode, and the conductive layer 542 2 can function as one electrode of a capacitor element. However, this is not limited to this. The conductive layer 5421 and the conductive layer 5422 are used as a wiring, a gate electrode, or an electrode of a capacitor. After that, the resist mask is removed.

[0405] Next, an insulating layer 5423 is formed on the entire surface by plasma CVD or sputtering. The insulating layer 5423 can function as a gate insulating layer, and the conductive layer 5421, The insulating layer 5423 is formed so as to cover the conductive layer 5422. Often ~250 nm.

[0406] Next, a resist mask formed by a photolithography process using a second photomask 5423 to selectively etch the insulating layer 5423 to form a contact that reaches the conductive layer 5421. A hole 5424 is formed. After that, the resist mask is removed. However, the present invention is not limited to this. Therefore, the contact hole 5424 can be omitted. After the formation, a contact hole 5424 can be formed. The cross-sectional view corresponds to FIG.

[0407] Next, an oxide semiconductor layer is formed on the entire surface by a sputtering method. The oxide semiconductor layer is formed by sputtering, and a buffer layer (e.g. For example + The oxide semiconductor layer can be formed with a thickness of 5 nm to 2 00nm in most cases.

[0408] Next, a resist mask formed by a photolithography process using a third photomask The oxide semiconductor layer is selectively etched using the resist mask. After that, the resist mask is removed. do.

[0409] Next, a second conductive layer is formed on the entire surface by sputtering. Next, a fourth photomask is The second conductive layer is selectively formed using a resist mask formed by the photolithography process. The conductive layer 5429, the conductive layer 5430, and the conductive layer 5431 are formed by etching the layers. The conductive layer 5429 is connected to the conductive layer 5421 through a contact hole 5424. The conductive layer 5429 and the conductive layer 5430 function as a source electrode and a drain electrode. The conductive layer 5431 can function as the other electrode of the capacitor. However, the conductive layer 5429, the conductive layer 5430, and the conductive layer 54 31 is a part that functions as a wiring, a source or drain electrode, or an electrode of a capacitor element. It is possible to include

[0410] In addition, if a heat treatment (for example, at 200°C to 600°C) is to be performed after this, It is preferable that the second conductive layer has heat resistance that can be obtained by the above-mentioned method. Highly heat conductive materials (e.g., Ti, Ta, W, Mo, Cr, Nd, Sc, Zr, Ce Elements such as these, alloys combining these elements, or nitrides containing these elements However, it is not limited to this, and the second conductive material may be used. By forming the second conductive layer into a laminated structure, it is possible to provide the second conductive layer with high heat resistance. For example, it is possible to provide a conductive material with high heat resistance, such as Ti or Mo, above and below the Al. It is Noh.

[0411] When etching the second conductive layer, a part of the oxide semiconductor layer is also etched. By this etching, an oxide semiconductor layer 5425 overlapping with the conductive layer 5421 is formed. The oxide semiconductor layer 5425 in the portion where the second conductive layer is not formed or the oxide semiconductor layer 5425 in the portion where the second conductive layer is not formed is The oxide semiconductor layer 5425 is often thinned by being etched. Therefore, the oxide semiconductor layer 5425 may not be etched. On the n-type semiconductor layer 5425 + In the case where a layer is formed, the oxide semiconductor layer 5425 is After this, the resist mask is removed. At this stage, the transistor 5441 and the capacitor 5442 are completed. The surface view corresponds to FIG. 37(B).

[0412] Next, a heat treatment is performed at 200° C. to 600° C. in an air atmosphere or a nitrogen atmosphere. As a result, rearrangement at the atomic level occurs in the oxide semiconductor layer 5425. This heating (including photo-annealing) releases the distortion that inhibits carrier movement. The timing of the treatment is not limited, and may be any timing after the formation of the oxide semiconductor layer. This can be done in a group.

[0413] Next, an insulating layer 5432 is formed over the entire surface. The insulating layer 5432 may have a single-layer structure. For example, the insulating layer 5432 may be an organic insulating layer. In the case of using the above-mentioned method, a composition which is a material for the organic insulating layer is applied, and then the composition is heated under an air atmosphere or a nitrogen atmosphere. Then, a heat treatment is performed at 200°C to 600°C to form an organic insulating layer. By forming an organic insulating layer in contact with the semiconductor layer 5425, a highly reliable thin-film transistor can be obtained. When an organic insulating layer is used as the insulating layer 5432, A silicon nitride film or a silicon oxide film may be provided under the insulating layer.

[0414] In FIG. 37C, the insulating layer 5432 is formed using a non-photosensitive resin. For illustration, in the cross section of the region in which the contact hole is to be formed, the end of the insulating layer 5432 is However, when the insulating layer 5432 is formed using a photosensitive resin, the contact In the cross section of the region where the cut hole is formed, the end of the insulating layer 5432 may be curved. As a result, the coverage of the third conductive layer or pixel electrode to be formed later is improved.

[0415] Instead of applying the composition, a dip method, a spray application method, or an ink application method may be used depending on the material. Ink jet method, printing method, doctor knife, roll coater, curtain coater, or nail It is possible to use an IF coater or the like.

[0416] In addition, the composition which is the material of the organic insulating layer is not subjected to heat treatment after the oxide semiconductor layer is formed. The heat treatment can also serve as heat treatment for the oxide semiconductor layer 5425.

[0417] The thickness of the insulating layer 5432 is 200 nm to 5 μm, preferably 300 nm to 1 μm. It is possible to do so.

[0418] Next, a third conductive layer is formed on the entire surface. Next, a fifth photomask is used to perform photolithography. The third conductive layer is selectively etched using the resist mask formed by the etching process. A conductive layer 5433 and a conductive layer 5434 are formed. A cross-sectional view of the above stage is shown in FIG. The conductive layer 5433 and the conductive layer 5434 correspond to a wiring, a pixel electrode, a reflective electrode, a transparent electrode, The conductive layer 5434 can function as a photo-transistor or an electrode of a capacitor. Since the conductive layer 5422 is connected to the conductive layer 5422, the conductive layer 5422 can function as an electrode of the capacitor 5442. However, the present invention is not limited to this, and may be applied to a conductive layer formed using a first conductive layer and a second conductive layer. It is possible to provide a function of connecting a conductive layer formed using a conductive layer. By connecting the layer 5433 and the conductive layer 5434, the conductive layer 5422 and the conductive layer 543 0 through the third conductive layer (conductive layer 5433 and conductive layer 5434). become.

[0419] Note that the capacitor 5442 is formed by the conductive layer 5422 and the conductive layer 5434. Since the capacitor 5442 has a structure in which the capacitor 5442 is sandwiched, the capacitance of the capacitor 5442 can be increased. However, the present invention is not limited thereto, and one of the conductive layer 5422 and the conductive layer 5434 may be omitted. It is Noh.

[0420] After removing the resist mask by wet etching, the substrate is etched in air or nitrogen. It is possible to carry out a heat treatment at 200°C to 600°C under the above-mentioned conditions.

[0421] Through the above steps, the transistor 5441 and the capacitor 5442 can be manufactured. .

[0422] As shown in FIG. 37D, an insulating layer 5435 is formed over the oxide semiconductor layer 5425. The insulating layer 5435 can be used to prevent oxidation when the second conductive layer is patterned. It has a function of preventing the nitride semiconductor layer 5425 from being scraped off, and functions as a stop film. Therefore, the thickness of the oxide semiconductor layer 5425 can be reduced. Reduction of drive voltage, reduction of off-current, improvement of on-off ratio of drain current, improvement of S value, etc. Note that the insulating layer 5435 is formed by continuously forming the oxide semiconductor layer and the insulating layer. A photoresist is formed on the entire surface, and then a photolithography process is performed using a photomask. The insulating layer is selectively patterned using a resist mask to form a Thereafter, a second conductive layer is formed on the entire surface, and an oxide semiconductor layer is formed simultaneously with the second conductive layer. That is, the oxide semiconductor layer and the second In this case, the oxide layer must be formed under the second conductive layer. Thus, the insulating layer 543 is formed without increasing the number of steps. In such a manufacturing process, an oxide semiconductor layer is formed under the second conductive layer. However, the present invention is not limited to this, and may be applied to patterning an oxide semiconductor layer. After that, an insulating layer is formed on the entire surface, and the insulating layer is patterned to form an insulating film. A layer 5435 can be formed.

[0423] In FIG. 37D, the capacitor 5442 includes a conductive layer 5422 and a conductive layer 5431. The insulating layer 5423 and the oxide semiconductor layer 5436 are sandwiched between the insulating layer 5423 and the oxide semiconductor layer 5436. The oxide semiconductor layer 5436 can be omitted. The third conductive layer is patterned to form a conductive layer 5437, which is connected to the third conductive layer 5431. Such a structure can be used, for example, in the pixels of a liquid crystal display device. For example, the transistor 5441 functions as a switching transistor and has a capacitance The element 5442 can function as a storage capacitor. The conductive layer 5422, the conductive layer 5429, and the conductive layer 5437 are a gate line, a capacitance line, and a source line, respectively. 3, it can function as a pixel electrode. However, it is not limited to this. 37(D), the conductive layer 5430 and the conductive layer 5431 are also connected to the third The connection can be made via a conductive layer.

[0424] As shown in FIG. 37(E), after the second conductive layer is patterned, the oxide semiconductor layer 5425. By doing so, the second conductive layer can be patterned. In this case, the oxide semiconductor layer 5425 is not formed. Therefore, the oxide semiconductor layer 5425 can be thin. Therefore, it is possible to reduce the driving voltage of the transistor, reduce the off-current, and improve the on-off ratio of the drain current. Note that the oxide semiconductor layer 5425 can be formed by After the conductive layer is patterned, an oxide semiconductor layer 5425 is formed on the entire surface. A resist mask formed by a photolithography process using a photomask is used to select The oxide semiconductor layer 5425 can be patterned in a patterning manner.

[0425] In FIG. 37E, the capacitor 5442 is formed by connecting the conductive layer 5422 and the third conductive layer. The insulating layer 5423 and the insulating layer 5432 are formed by the conductive layer 5439 formed by turning. The conductive layer 5422 and the conductive layer 5430 are sandwiched between the third conductive layer. The connection is made via a conductive layer 5438 that is formed by patterning. 9 is connected to a conductive layer 5440 formed by patterning the second conductive layer. 37(E), in FIGS. 37(C) and (D), the conductive layer 5430 and the conductive layer 54 22 can be connected via conductive layer 5438.

[0426] The thickness of the oxide semiconductor layer (or the channel layer) is determined by the thickness of the depletion layer when the transistor is off. By making the thickness of the gate electrode less than this, it is possible to create a fully depleted state. In order to achieve this, the off-state current of the oxide semiconductor layer 5425 can be reduced. The film thickness is preferably 20 nm or less, and more preferably 10 nm or less. It is especially preferable that the thickness is 6 nm or less.

[0427] In addition, the operating voltage of transistors is reduced, the off-current is reduced, and the on / off ratio of the drain current is improved. In order to improve the S value, the thickness of the oxide semiconductor layer is set to be equal to the thickness of the layers constituting the transistor. For example, the oxide semiconductor layer is preferably thinner than the insulating layer 5423. The thickness of the oxide semiconductor layer is preferably thinner than that of the insulating layer 5423. It is preferably 1 / 2 or less, and more preferably 1 / 5 or less. More preferably, it is 1 / 10 or less. However, it is not limited to this. In order to improve reliability, the oxide semiconductor layer may be thicker than the insulating layer 5423. In particular, when the oxide semiconductor layer is removed as shown in FIG. Since the conductor layer is preferably thick, the oxide semiconductor layer is preferably thicker than the insulating layer 5423. It is possible to make the thickness of the film thicker.

[0428] In order to increase the dielectric strength of the transistor, the thickness of the insulating layer 5423 is set to be equal to or larger than that of the first conductive layer. It is preferable that the thickness of the insulating layer 5423 is thicker than that of the first conductive layer. It is preferable that the thickness is 5 / 4 or more of the layer. More preferably, it is preferable that the thickness is 4 / 3 or more. However, the present invention is not limited to this, and the insulating layer 54 may be used to increase the mobility of the transistor. The thickness of 23 can be thinner than that of the first conductive layer.

[0429] The substrate, insulating layer, conductive layer, and semiconductor layer of this embodiment may be the same as those of the other embodiments. Materials as described or similar to those described herein can be used.

[0430] The transistor of this embodiment may be used in the semiconductor device of the first to eighth embodiments, or in the shift register. By using it in a computer or display device, the display area can be enlarged. The part can be made highly detailed.

[0431] (Embodiment 11) In this embodiment mode, a layout diagram (hereinafter also referred to as a top view) of a shift register will be described. In this embodiment, as an example, the layout of the shift register described in the fourth embodiment is The contents of the present embodiment are the same as those of the fourth embodiment. In addition to the shift register described above, the semiconductor device and the shift register according to the first to seventh embodiments are The present embodiment can be applied to a display device or a monitor. It should be noted that this is merely an example and is not limiting.

[0432] The layout diagram of this embodiment will be described with reference to FIG. 38. FIG. 38 shows an example of a layout diagram. The layout diagram of FIG. 5(A) is shown as an example. Note that the hatching pattern shown on the right side of FIG. The hatching patterns of the components of the symbols attached to each hatching pattern are This shows that.

[0433] The transistor or wiring shown in FIG. 38 includes a conductive layer 701, a semiconductor layer 702, a conductive layer 7 703, a conductive layer 704, and a contact hole 705. It is not limited, and another conductive layer, an insulating film, or another contact hole can be formed. For example, a contact hole for connecting the conductive layer 701 and the conductive layer 703 is added. It is possible.

[0434] The conductive layer 701 can include a portion that functions as a gate electrode or a wiring. The conductor layer 702 may include a portion that functions as a semiconductor layer of a transistor. The conductive layer 703 may include a portion functioning as a wiring, a source electrode, or a drain electrode. The conductive layer 704 functions as a light-transmitting electrode, a pixel electrode, or a wiring. The contact hole 705 can include a conductive layer 701 and a conductive layer 704. or a function of connecting the conductive layer 703 and the conductive layer 704 .

[0435] In this embodiment, the transistor 101_1, the transistor 101_2, and the transistor 2 01_1 and / or the transistor 202_2, which functions as a second terminal The area where the conductive layer 703 overlaps with the conductive layer 701 is a conductive layer having a function as a first terminal. It is preferable that the area of ​​the conductive layer 701 is smaller than the area of ​​the conductive layer 703. This makes it possible to suppress the concentration of the electric field on the second terminal, thereby preventing the deterioration of the transistor or However, the second terminal can be used to suppress the breakdown of the transistor. The area of ​​the conductive layer 703 having the function as the first terminal and the conductive layer 701 overlap each other is The area of ​​the conductive layer 703 having the function and the conductive layer 701 can be larger than the overlapping area of ​​the conductive layer 703 having the function. .

[0436] Note that a semiconductor layer 702 is formed in a portion where the conductive layer 701 and the conductive layer 703 overlap each other. By doing so, the parasitic capacitance between the conductive layer 701 and the conductive layer 703 can be reduced. For the same reason, the conductive layer A semiconductor layer 702 can be formed in the area where the conductive layer 704 overlaps with the conductive layer 703. .

[0437] A conductive layer 704 is formed on a part of the conductive layer 701. It is possible to connect to the conductive layer 704 through the through hole 705. By this, the wiring resistance can be reduced. and a conductive layer 704 are formed. The conductive layer 701 is connected to the The conductive layer 703 is connected to the conductive layer 704 through another contact hole 705. It is possible to connect with the conductive layer 704. By doing so, the wiring resistance is reduced. It is possible.

[0438] Note that the conductive layer 704 is formed on a part of the conductive layer 703. It is possible to connect to the conductive layer 704 through the through hole 705. This makes it possible to reduce the wiring resistance.

[0439] Note that the conductive layer 701 or the conductive layer 703 is formed under a part of the conductive layer 704. 704 is connected to the conductive layer 701 or the conductive layer 703 through a contact hole 705. By doing so, the wiring resistance can be reduced. .

[0440] As described above, the parasitic capacitance between the gate and the second terminal of the transistor 101_1 can be made larger than the parasitic capacitance between the gate and the first terminal of the transistor 101_1. As shown in FIG. 38, the width of the conductive layer 703 that can function as the first terminal of the transistor 101_1 is set to 1 / 2. Width 732 and the width of the conductive layer 703 that can function as the second terminal of the transistor 101_1 is represented as Width 731 The width 731 can be greater than the width 732. This allows the parasitic capacitance between the gate and the second terminal of the transistor 101_1 to be greater than the parasitic capacitance between the gate and the first terminal of the transistor 101_1. However, this is not limiting.

[0441] As described above, the parasitic capacitance between the gate and the second terminal of the transistor 101_2 can be made larger than the parasitic capacitance between the gate and the first terminal of the transistor 101_2. As shown in FIG. 38, the width of the conductive layer 703 that can function as the first terminal of the transistor 101_2 is set to 1 / 2. Width 742 and the width of the conductive layer 703 that can function as the second terminal of the transistor 101_2 is Width 741 The width 741 can be greater than the width 742. This allows the parasitic capacitance between the gate and the second terminal of the transistor 101_2 to be greater than the parasitic capacitance between the gate and the first terminal of the transistor 101_2. However, this is not limiting.

[0442] (Embodiment 12) In this embodiment, an example of an electronic device will be described.

[0443] 39(A) to 39(H) and 40(A) to 40(D) ​​are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, and an LED. Lamp 5004, operation key 5005 (operation switch for controlling the operation of the display device, or power switch), connection terminal 5006, sensor 5007 (force, displacement, position, speed, acceleration , angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric The function of measuring current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays 5008, etc.

[0444] FIG. 39(A) shows a mobile computer, which includes, in addition to the above, a switch 5009, The portable terminal 5010 may have an infrared port 5010. FIG. A type of image reproducing device (for example, a DVD reproducing device) that, in addition to the above, also has a second display 39C shows a goog In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. FIG. 39(D) shows a portable game machine. In addition to the above, the device may have a recording medium reading unit 5011, etc. In addition to the above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 39(F) shows a portable gaming machine, which, in addition to the above, has a second display unit. 5002, a recording medium reading unit 5011, etc. In addition to the above, the image sensor may also include a tuner, an image processor, etc. 39(H) is a portable television receiver, capable of transmitting and receiving signals in addition to the above. FIG. 40(A) shows a display, and the above-mentioned In addition to the above, a support stand 5018 and the like can be provided. FIG. 40(B) shows a camera. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 40(C) is a computer, In addition, there is a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 40(D) ​​shows a mobile phone, which, in addition to the above, In addition, an antenna 5014, a 1-segment partial reception service tuner for mobile phones and mobile terminals It may have a nozzle, etc.

[0445] The electronic devices shown in FIGS. 39(A) to 39(H) and 40(A) to 40(D) ​​are For example, various information (still images, videos, text images, etc.) Function to display on the display unit, touch panel function, calendar, date or time display, etc. Functions, functions to control processing by various software (programs), wireless communication functions, A function to connect to various computer networks using wireless communication functions, A function to transmit or receive various data using a program recorded on a recording medium The data can be read out and displayed on the display unit. In electronic devices with displays, one display unit is used primarily to display image information, and another A function that mainly displays text information on one display unit, or a function that displays images with consideration for parallax on multiple displays. By displaying the image, it is possible to have a function of displaying a three-dimensional image. In electronic devices having an image unit, the functions of taking still images, taking videos, and taking pictures are available. The function to automatically or manually correct the captured image, and to store the captured image in a recording medium (external or built-in to the camera) ) and display the captured image on the display unit. The electronic devices shown in FIGS. 39(A) to 39(H) and 40(A) to 40(D) ​​are usable. The functions that can be performed are not limited to these, and various other functions can be performed.

[0446] The electronic device described in this embodiment has a display unit for displaying some information. The electronic device of the present embodiment and the semiconductor device of the first to ninth embodiments are By combining it with a semiconductor memory device, a shift register, or a display device, the reliability and yield can be improved. This allows for improved resolution, reduced costs, and a larger, more precise display. .

[0447] Next, application examples of the semiconductor device will be described.

[0448] FIG. 40(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. The semiconductor device is a wall-mounted type that is integrated with the building and requires a large space to install. It can be installed without requiring a large space.

[0449] FIG. 40(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 and is The display panel 5026 becomes viewable.

[0450] In this embodiment, a wall and a unit bath are used as examples of structures. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various structures.

[0451] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0452] FIG. 40G is a diagram showing an example in which the semiconductor device is provided in an automobile. 5028 is attached to a vehicle body 5029 of a vehicle, and is configured to detect the movement of the vehicle body or the inside and outside of the vehicle. The information entered can be displayed on demand. It is okay to do so.

[0453] FIG. 40(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 40(H) shows a passenger plane with a display panel 5031 mounted on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge portion 5032. This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0454] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorail, etc.) They can be installed on a variety of things, including buildings, railways, ships, etc. [Explanation of symbols]

[0455] 10 Circuit 11_1 Switch 11_2 Switch 11 Switch 21 Routes 100 circuits 101 Transistor 101p transistor 101a Diode 102 Transistor 102p transistor 111 Wiring 112 Wiring 111A Wiring 112A Wiring 112B Wiring 114A Wiring 114B Wiring 117A wiring 117B Wiring 117C Wiring 117D Wiring 117E Wiring 117F Wiring 117G Wiring 117H Wiring 117I Wiring 117J Wiring 117K wiring 301a Diode 301p transistor 3020 pixels 3021 Transistor 3022 Liquid crystal element 3023 Capacitive element 302a Diode 302p transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 120 circuits 121 Capacitive element 122 Transistor 200 circuits 201 Transistor 202 Transistor 203 Transistor 211 Wiring 300 circuits 301 Transistor 302 Transistor 303 Transistor 303a Diode 303p transistor 304 Transistor 304a Diode 304p transistor 310 Circuit 311 Transistor 312 Transistor 313 Transistor 314 Transistor 315 Capacitive element 316 Transistor 320 Circuit 321 Transistor 322 Transistor 323 Transistor 324 Transistor 325 Capacitive element 326 Transistor 330 circuits 331 Transistor 332 Transistor 333 Transistor 334 Transistor 335 Transistor 336 Transistor 342 Transistor 344 Transistor 500 Shift Registers 501 Flip-flop 511 Wiring 512 Wiring 513 Wiring 514 Wiring 515 Wiring 516 Wiring 517 Wiring 518 Wiring 520 Circuit 521 Circuit 522 circuits 600 circuits 601 Circuit 602 Circuit 603 Transistor 604 Wiring 605 Wiring 614 signal 615 Signal 701 Conductive layer 702 Semiconductor layer 703 Conductive layer 704 Conductive layer 705 Contact Hole 731 Width 732 Width 741 Width 742 Width 3031 Wiring 3032 Wiring 3033 Wiring 3034 Electrode 3041 Signal 3042 signal 3043 Voltage 5000 cabinet 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Reader / Writer 5022 Case 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit Bath 5028 Display Panel 5029 Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection Lens 5260 PCB 5261 Insulation layer 5262 Semiconductor layer 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5266 Conductive layer 5267 Insulating layer 5268 Conductive layer 5269 Insulation layer 5270 Light-emitting layer 5271 Conductive layer 5273 Insulation layer 5300 Board 5301 Conductive layer 5302 Insulating layer 5304 Conductive layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5360 Video Signal 5361 Circuit 5362 Circuit 5363 Circuit 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 PCB 5381 Input terminal 5391 Substrate 5392 Drive circuit 5393 Pixel section 5400 Board 5401 Conductive layer 5402 Insulating layer 5404 Conductive layer 5405 Insulating layer 5406 Conductive layer 5407 Liquid crystal layer 5408 Insulating layer 5409 Conductive layer 5410 Substrate 5420 PCB 5421 Conductive layer 5422 Conductive layer 5423 Insulating layer 5424 Contact Hole 5425 Oxide semiconductor layer 5429 Conductive layer 5430 Conductive layer 5431 Conductive layer 5432 Insulating layer 5433 Conductive layer 5434 Conductive layer 5435 Insulation Layer 5436 Oxide Semiconductor Layer 5437 Conductive layer 5438 Conductive layer 5439 Conductive layer 5440 Conductive layer 5441 Transistor 5442 Capacitor 3020A Subpixel 3020B Subpixel 3021A Transistor 3021B Transistor 3022A Liquid crystal element 3022B Liquid crystal element 3023A Capacitive Element 3023B Capacitive Element 3031A Wiring 3031B Wiring 3032A Wiring 3032B Wiring 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a Circuit 5361b circuit 5362a Circuit 5362b circuit 5403a Semiconductor layer 5403b Semiconductor layer

Claims

1. A gate driver is provided. The gate driver is a display device having a first transistor and a second transistor, a first conductive layer that functions as a gate of the first transistor; a second conductive layer that functions as a gate of the second transistor; a first semiconductor layer disposed above the first conductive layer and having a channel formation region of the first transistor; a second semiconductor layer disposed above the second conductive layer and having a channel formation region of the second transistor; a third conductive layer disposed above the first semiconductor layer and above the second semiconductor layer; a fourth conductive layer disposed above the first semiconductor layer and above the second semiconductor layer; the third conductive layer functions as one of a source and a drain of the first transistor and also functions as one of a source and a drain of the second transistor; the fourth conductive layer functions as the other of the source and the drain of the first transistor and also functions as the other of the source and the drain of the second transistor; the fourth conductive layer has an opening; the opening has a region overlapping with the first semiconductor layer and a region not overlapping with the first semiconductor layer, the opening has a region overlapping the first conductive layer and a region not overlapping the first conductive layer, A display device, wherein an overlapping area between the third conductive layer and the first conductive layer is smaller than an overlapping area between the fourth conductive layer and the first conductive layer.

2. A gate driver is provided. The gate driver is a display device having a first transistor and a second transistor, a first conductive layer that functions as a gate of the first transistor; a second conductive layer that functions as a gate of the second transistor; a first semiconductor layer disposed above the first conductive layer and having a channel formation region of the first transistor; a second semiconductor layer disposed above the second conductive layer and having a channel formation region of the second transistor; a third conductive layer disposed above the first semiconductor layer and above the second semiconductor layer; a fourth conductive layer disposed above the first semiconductor layer and above the second semiconductor layer; the third conductive layer functions as one of a source and a drain of the first transistor and also functions as one of a source and a drain of the second transistor; the fourth conductive layer functions as the other of the source and the drain of the first transistor and also functions as the other of the source and the drain of the second transistor; the fourth conductive layer has an opening; the opening has a region overlapping with the first semiconductor layer and a region not overlapping with the first semiconductor layer, the opening has a region overlapping the first conductive layer and a region not overlapping the first conductive layer, an overlapping area between the third conductive layer and the first conductive layer is smaller than an overlapping area between the fourth conductive layer and the first conductive layer; The display device, wherein the third conductive layer is electrically connected to a gate signal line.

3. A gate driver is provided. The gate driver is a display device having a first transistor and a second transistor, a first conductive layer that functions as a gate of the first transistor; a second conductive layer that functions as a gate of the second transistor; a first semiconductor layer disposed above the first conductive layer and having a channel formation region of the first transistor; a second semiconductor layer disposed above the second conductive layer and having a channel formation region of the second transistor; a third conductive layer disposed above the first semiconductor layer and above the second semiconductor layer; a fourth conductive layer disposed above the first semiconductor layer and above the second semiconductor layer; the third conductive layer functions as one of a source and a drain of the first transistor and also functions as one of a source and a drain of the second transistor; the fourth conductive layer functions as the other of the source and the drain of the first transistor and also functions as the other of the source and the drain of the second transistor; the fourth conductive layer has an opening; the opening has a region overlapping with the first semiconductor layer and a region not overlapping with the first semiconductor layer, the opening has a region overlapping the first conductive layer and a region not overlapping the first conductive layer, an overlapping area between the third conductive layer and the first conductive layer is smaller than an overlapping area between the fourth conductive layer and the first conductive layer; A display device, wherein an overlapping area between the third conductive layer and the second conductive layer is smaller than an overlapping area between the fourth conductive layer and the second conductive layer.

4. A gate driver is provided. The gate driver is a display device having a first transistor and a second transistor, a first conductive layer that functions as a gate of the first transistor; a second conductive layer that functions as a gate of the second transistor; a first semiconductor layer disposed above the first conductive layer and having a channel formation region of the first transistor; a second semiconductor layer disposed above the second conductive layer and having a channel formation region of the second transistor; a third conductive layer disposed above the first semiconductor layer and above the second semiconductor layer; a fourth conductive layer disposed above the first semiconductor layer and above the second semiconductor layer; the third conductive layer functions as one of a source and a drain of the first transistor and also functions as one of a source and a drain of the second transistor; the fourth conductive layer functions as the other of the source and the drain of the first transistor and also functions as the other of the source and the drain of the second transistor; the fourth conductive layer has an opening; the opening has a region overlapping with the first semiconductor layer and a region not overlapping with the first semiconductor layer, the opening has a region overlapping the first conductive layer and a region not overlapping the first conductive layer, an overlapping area between the third conductive layer and the first conductive layer is smaller than an overlapping area between the fourth conductive layer and the first conductive layer; an overlapping area between the third conductive layer and the second conductive layer is smaller than an overlapping area between the fourth conductive layer and the second conductive layer; The display device, wherein the third conductive layer is electrically connected to a gate signal line.

5. In any one of claims 1 to 4, A display device in which the third conductive layer is electrically connected to a gate of a transistor included in a pixel.

6. In any one of claims 1 to 5, A display device, wherein, in a plan view, the opening is a region that is completely surrounded by the fourth conductive layer.

Images