Semiconductor Device

Abstract

To provide a semiconductor device in which parasitic capacitance is reduced.SOLUTION: A transistor 10 comprises: a first insulation layer 110; a first insulator 121 on the first insulation layer; a semiconductor layer 122 on the first insulator; a source electrode layer 130 and a drain electrode layer 140 on the semiconductor layer; a second insulation layer 173 on the first insulation layer; a third insulation layer 175 on a second insulator, the source electrode layer, and the drain electrode layer; the second insulator 123 on the semiconductor layer; a gate insulation layer 150 on the second insulator; a gate electrode layer 160 on the gate insulation layer; and a fourth insulation layer 170 on the third insulation layer, the second insulation layer, the gate insulation layer, and the gate electrode layer. The second insulation layer has a region that is in contact with a first oxide layer, the semiconductor layer, the source electrode layer, and the drain electrode layer on a side surface. A top surface of the second insulation layer is positioned on the same plane as the source electrode layer and the drain electrode layer. The second insulator has a region that is in contact with side surfaces of the first oxide layer, the source electrode layer, the drain electrode layer, the second insulation layer, and the third insulation layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. , manufacture, or composition of matter. The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, In particular, one embodiment of the present invention relates to a semiconductor device or a driving method thereof. or a method for producing the same.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device or an electronic device may include a semiconductor device. [Background technology]

[0003] The technology of constructing transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. The transistor is expected to be used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention as other materials. There are.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 11-505377 Summary of the Invention [Problem to be solved by the invention]

[0006] As semiconductor elements become smaller, parasitic capacitance near transistors becomes a major problem.

[0007] In transistor operation, the area near the channel (for example, between the source electrode and the drain electrode) If parasitic capacitance is present, it takes time for the parasitic capacitance to charge, which slows down the transistor response. This reduces the performance and thus the response of the semiconductor device.

[0008] In addition, the various processes for forming transistors (especially film formation, processing, etc.) It is becoming increasingly difficult to control this, and variations in the manufacturing process can affect transistor characteristics, and even has a significant impact on reliability.

[0009] In addition, with miniaturization, the precision required for processing is becoming stricter, and the difficulty of processing is increasing. It's coming soon.

[0010] Therefore, one aspect of the present invention has an object to reduce parasitic capacitance in the vicinity of a transistor. Another object is to provide a semiconductor device having good electrical characteristics. Another object of the present invention is to provide a highly reliable semiconductor device. One of the objectives of the present invention is to reduce the variation in characteristics of a semiconductor device or a semiconductor device caused by the manufacturing process. Another object is to stabilize the manufacturing process of a transistor. An object of the present invention is to provide a semiconductor device including an oxide semiconductor layer with few oxygen vacancies. Another object of the present invention is to provide a semiconductor device that can be formed in a simple process. Alternatively, a semiconductor having a structure capable of reducing an interface state in the vicinity of an oxide semiconductor layer may be used. Another object of the present invention is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a novel semiconductor device. Another object is to provide a method for manufacturing the above semiconductor device.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device comprising a first insulating layer, a first oxide layer on the first insulating layer, and a first oxide layer. a semiconductor layer on the first insulating layer; a source electrode layer and a drain electrode layer on the semiconductor layer; a second insulating layer, a third insulating layer on the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer on the semiconductor layer; a gate insulating layer on the second oxide layer; and a gate insulating layer. a gate electrode layer on the layer, a third insulating layer, a second oxide layer, a gate insulating layer, and a gate and a fourth insulating layer on the electrode layer. The second insulating layer is a first oxide layer, a semiconductor layer, a silicon The top surface of the second insulating layer is in contact with the side surfaces of the source electrode layer and the drain electrode layer. , the source electrode layer, and the drain electrode layer, and the second oxide layer is side surfaces of the oxide layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer; The semiconductor device has a region in contact with the

[0013] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising the steps of: forming a first insulating layer; and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, a first conductive film is formed on the semiconductor film, and a first A first mask is formed on the conductive film, and a part of the first conductive film is etched using the first mask. The first conductive layer is formed in an island shape, and a first mask and the first conductive layer are used as a mask. The first oxide film and the semiconductor film are etched using a A second insulating layer is formed on the first insulating layer and the first conductive layer. and performing a chemical mechanical polishing process on the second insulating film until the first conductive layer is exposed. Thus, a second insulating layer is formed, and a third insulating film is formed on the first conductive layer and the second insulating layer. forming a second mask on the third insulating film; and forming a second mask on the third insulating film using the second mask. By partially etching, the source electrode layer, the drain electrode layer, and the third insulating layer are A third insulating layer is formed on the semiconductor layer, and a second oxide film is formed on the semiconductor layer. A fourth insulating film is formed on the first insulating film, a second conductive film is formed on the fourth insulating film, and the second conductive film and the first The insulating film of 4 and the second oxide film are subjected to a chemical mechanical polishing process to form the second oxide layer. A method for manufacturing a semiconductor device, comprising forming a gate insulating layer and a gate electrode layer. .

[0014] In addition, after the semiconductor film is formed, a first heat treatment is performed to form a third insulating layer, a second oxide layer, a gate A fourth insulating layer containing oxygen is formed over the insulating layer and the gate electrode layer. During the formation of the fourth insulating layer, A mixed layer of the third insulating layer and the fourth insulating layer is formed, and at the same time, the mixed layer or the first insulating layer is It is preferable to add oxygen to the semiconductor layer and then perform a second heat treatment to diffuse the oxygen into the semiconductor layer. stomach.

[0015] The third insulating film is an insulating film containing oxygen, and the fourth insulating layer is formed by using oxygen gas. It is preferable to form the insulating film by a sputtering method.

[0016] The third insulating film is a silicon oxide film, and the fourth insulating layer is formed by immersing 50 volumes of oxygen gas. % or more and formed by sputtering using an aluminum oxide target. It is preferable to do so.

[0017] The second heat treatment is preferably performed at a temperature of 300° C. or higher and 450° C. or lower.

[0018] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising the steps of: forming a first insulating layer; and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, a first conductive film is formed on the semiconductor film, and a first A second insulating film is formed on the conductive film, a first mask is formed on the second insulating film, and the first mask is The second insulating film and a part of the first conductive film are etched using a dummy mask to leave the first conductive layer and and a second insulating layer is formed, a second mask is formed on the second insulating layer and the semiconductor film, and The second insulating layer, the first conductive layer, the first oxide film, and the semiconductor film are then removed using the second mask. By partially etching, the first oxide layer, the semiconductor layer, the source electrode layer, the drain electrode layer, and the An electrode layer and a third insulating layer are formed on the first insulating layer, the third insulating layer, and the semiconductor layer. A second oxide film is formed on the second oxide film, a third insulating film is formed on the second oxide film, and the third insulating film is A second conductive film is formed on the first conductive film, a third mask is formed on the second conductive film, and a third mask is used to form a and etching a part of the second oxide film, the third insulating film, and the second conductive film. A semiconductor device comprising: a gate insulating layer and a gate electrode layer formed by A method for manufacturing a body device.

[0019] In addition, a first heat treatment is performed after the semiconductor film is formed, and the first insulating layer, the third insulating layer, and the gate electrode are formed. A fourth insulating layer having oxygen is formed on the electrode layer, and the first insulating layer and the fourth insulating layer are interposed between the fourth insulating layer and the electrode layer. A first mixed layer made of the first insulating layer and the fourth insulating layer, and a second mixed layer made of the third insulating layer and the fourth insulating layer. At the same time, an oxygen is introduced into the first mixed layer, the second mixed layer, the first insulating layer, or the second insulating layer. It is preferable to add oxygen to the semiconductor layer and then perform a second heat treatment to diffuse oxygen into the semiconductor layer.

[0020] The first insulating film and the second insulating film are insulating films containing oxygen, and the fourth insulating layer It is preferable that the insulating film is formed by a sputtering method using oxygen gas.

[0021] The first insulating film and the second insulating film are silicon oxide films, and the fourth insulating layer is an oxide film. The sputtering was performed using 50% or more of nitrogen gas and an aluminum oxide target. It is preferable to form the film by a coating method.

[0022] The second heat treatment is preferably performed at a temperature of 300° C. or higher and 450° C. or lower.

[0023] Another aspect of the present invention is a method for manufacturing a semiconductor device comprising the steps of: forming a first insulating layer; and forming a first oxide film on the first insulating layer. Then, a semiconductor film is formed on the first oxide film, a first conductive film is formed on the semiconductor film, and a first A second insulating film is formed on the conductive film, a third insulating film is formed on the second insulating film, and the third insulating film is formed on the conductive film. A first mask is formed on the film, and a third insulating film and a second insulating film are formed by using the first mask. a first conductive film, a semiconductor film, and a first oxide film are partially etched; Thus, the first oxide layer, the semiconductor layer, the second insulating layer, and the third insulating layer are formed in an island shape, A fourth insulating film is formed on the first insulating layer and the third insulating layer until the third insulating layer is exposed. The fourth insulating film is subjected to a chemical mechanical polishing process to form a fourth insulating layer. A second mask is formed on the third insulating layer, and a source electrode layer, a drain electrode layer, and a gate electrode layer are formed on the second mask. A rain electrode layer, a fifth insulating layer, and a sixth insulating layer are formed, and the fourth insulating layer and the sixth insulating layer are formed. forming a second oxide film on the edge layer and on the semiconductor layer; and forming a fifth insulating film on the second oxide film. a second conductive film is formed on the fifth insulating film, and the second conductive film, the fifth insulating film, and the first insulating film are formed on the second conductive film, the fifth insulating film, and the second insulating film. The second oxide layer, the gate insulating layer, and the gate insulating layer are formed by subjecting the oxide film of the second oxide layer to a chemical mechanical polishing process. The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device, comprising the steps of: forming a gate electrode layer;

[0024] In addition, the first heat treatment is performed after the semiconductor film is formed, and the second insulating film and the third insulating film are formed. A mixed layer with the third insulating film is formed, and oxygen is added to the mixed layer or the second insulating film at the same time. Then, a fourth insulating layer, a sixth insulating layer, a second oxide layer, a gate insulating layer, and a gate electrode layer are formed on the fourth insulating layer, the sixth insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer. During the formation of the seventh insulating layer, a mixed layer of the fourth insulating layer and the seventh insulating layer is formed. At the same time, oxygen is added to the mixed layer or the fourth insulating layer, and a second heat treatment is performed. It is preferable to diffuse oxygen into the semiconductor layer.

[0025] The second insulating film and the fourth insulating film are insulating films containing oxygen, and the third insulating film and The seventh insulating layer is preferably formed by a sputtering method using oxygen gas.

[0026] The second insulating film and the fourth insulating film are silicon oxide films, and the third insulating film and the fourth insulating film are silicon oxide films. The insulating layer of 7 is formed by using oxygen gas of 50% by volume or more and an aluminum oxide target. In particular, it is preferable to form the insulating film by a sputtering method.

[0027] The second heat treatment is preferably performed at a temperature of 300° C. or higher and 450° C. or lower.

[0028] Moreover, a configuration can be provided in which a semiconductor device, a microphone, a speaker, and a housing are used. Effect of the Invention

[0029] By using one embodiment of the present invention, parasitic capacitance near a transistor can be reduced. Alternatively, a semiconductor device having good electrical characteristics can be provided. Alternatively, a semiconductor device having a low resistance can be provided. It is possible to reduce the variation in characteristics caused by the manufacturing process of a transistor. Alternatively, a semiconductor having an oxide semiconductor layer with few oxygen vacancies can be obtained. Alternatively, a semiconductor device that can be formed by a simple process can be provided. Alternatively, the interface state in the vicinity of the oxide semiconductor layer can be reduced. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device or the like can be provided. A method for fabricating a semiconductor device may be provided.

[0030] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0031] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 2] 1 is a cross-sectional view illustrating a transistor. [Diagram 3] Enlarged cross-sectional view and band diagram of a transistor. [Figure 4] Schematic diagram showing the principle of ALD film formation. [Diagram 5] Schematic diagram of the ALD equipment. [Figure 6] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 7] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 8] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 10] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 11] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 12] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 13] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 14] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 15]1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 18] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 19] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor. [Figure 23] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 24] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 25] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 26] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 27] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 28] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 29] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Diagram 30] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Diagram 31] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Diagram 32] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Diagram 33] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Diagram 34]Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Diagram 35] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 36] Electron diffraction pattern of CAAC-OS. [Figure 37] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 38] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device. [Figure 39] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device. [Diagram 40] FIG. [Diagram 41] FIG. 2 is a plan view showing pixels of the imaging device. [Diagram 42] FIG. [Diagram 43] FIG. [Diagram 44] FIG. 2 is a diagram for explaining an example of the configuration of an RF tag. [Diagram 45] FIG. 2 is a diagram for explaining an example of the configuration of a CPU. [Figure 46] FIG. [Figure 47] 1A and 1B are diagrams illustrating a configuration example of a display device and a circuit diagram of a pixel. [Figure 48] 1A and 1B are a top view and a cross-sectional view illustrating a display device. [Figure 49] 1A and 1B are a top view and a cross-sectional view illustrating a display device. [Figure 50] FIG. 2 is a diagram illustrating a display module. [Figure 51] 1A and 1B are a perspective view showing a cross-sectional structure of a package using a lead frame type interposer and a diagram showing a module configuration. [Figure 52] 1A to 1C are diagrams illustrating electronic devices. [Figure 53] 1A to 1C are diagrams illustrating electronic devices. [Figure 54] 1A to 1C are diagrams illustrating electronic devices. [Figure 55] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0033] For example, in the present specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in the present specification. Therefore, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence. Any connections other than those shown in the drawings or text shall be deemed to be included in the drawings or text. do.

[0034] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0035] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When a resistor (such as an electrode, display element, light-emitting element, or load) is not connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors, etc.) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0036] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0037] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. and the case where they are electrically connected to each other.

[0038] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) When X and Y are functionally connected (i.e., when X and Y are connected), (When there is a functional connection between X and Y via another circuit in between) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is deemed to be disclosed in the present specification. If it is explicitly stated that it is connected, The same contents are deemed to be disclosed in the present specification and the like.

[0039] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0040] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined based on the above.

[0041] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path is connected to the source (or a path between the drain (or second terminal, etc.) of the transistor and the The first connection path is a path through Z1, and is connected to the drain (or the second The terminal of the third terminal (such as the terminal of the third terminal) is electrically connected to Y through at least a third connection path, The connection path does not include the second connection path, and the third connection path is via Z2. Or, it can be expressed as "the source (or the first The terminal of the first connection path is electrically connected to X through Z1. The first connection path does not have a second connection path, and the second connection path is A connection path through the transistor, the drain (or second terminal, etc.) of the transistor is electrically connected to Y through Z2 by at least a third connection path, The third connection path does not have the second connection path. "The source (or first terminal, etc.) of the transistor is connected to at least a first electrical path. Therefore, the first electrical path is electrically connected to X through Z1, and the second electrical path is The second electrical path is a path from the source (or the first terminal) of the transistor to the (e.g., the drain of the transistor) to the second terminal of the transistor. The drain (or second terminal, etc.) of the transistor is connected to the drain (or second terminal, etc.) by at least a third electrical path. The third electrical path is electrically connected to Y through Z2, and has a fourth electrical path. The fourth electrical path is a drain (or a second terminal, etc.) of the transistor. to the source (or first terminal, etc.) of the transistor. Using the same representation as these examples, the connection paths in the circuit configuration can be expressed as By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal.

[0042] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0043] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The electrode functions as both components. The term "electrochemically connected" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0044] <Notes regarding the description of the drawings> In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. The above is used for convenience in describing the drawings. The meaning of the term varies depending on the direction in which the configuration is depicted. It is not limited to this and can be rephrased appropriately depending on the situation.

[0045] In addition, the terms "above" and "below" refer to the positional relationship of components directly above or below each other and directly adjacent to each other. For example, if the expression is "electrode B on insulating layer A," It is not necessary for electrode B to be formed directly on insulating layer A. This does not exclude the inclusion of other components.

[0046] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0047] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0048] In addition, in the drawings, the size, layer thickness, and area are shown arbitrarily for convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for illustrative purposes only, and are not limited to the shapes or values ​​shown in the drawings.

[0049] In addition, in the drawings, in top views (also called plan views or layout views) and perspective views, In order to clarify the drawings, some components may be omitted.

[0050] In addition, the term "same" means that the substrate has the same area or shape. The same height may be used as the same plane in the vertical direction from the plate surface. Also, due to the manufacturing process, the shapes, planes, and heights may not be completely the same. Therefore, "almost identical" can be rephrased as "identical."

[0051] <Notes on possible alternative descriptions> In the present specification and the like, when describing the connection relationship of a transistor, is expressed as "one of the source and drain" (or the first electrode, or the first terminal), and The other side of the drain is referred to as the "other side of the source or drain" (or the second electrode, or the second terminal). This is because the source and drain of a transistor are This is because it changes depending on the conditions. Regarding the names of the source and drain of a transistor, can be appropriately rephrased as source (drain) terminal, source (drain) electrode, etc., depending on the situation. It is possible to do so.

[0052] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0053] In this specification, a transistor includes a gate, a drain, and a source. It is an element that has at least three terminals. And the drain (drain terminal, drain A channel is formed between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode). The transistor has a channel region and allows current to flow through the drain, the channel region, and the source. It is possible.

[0054] Here, the source and drain vary depending on the transistor structure or operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called a source or a drain. One of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. It may be indicated.

[0055] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of the elements. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0056] In the present specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Integrated Circuits) or TCP (Tape Carrier Packa ge) or COG (Chip On Glass) on the board Devices in which ICs (integrated circuits) are directly mounted using this method are sometimes called display devices.

[0057] In addition, the words "membrane" and "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" can be used interchangeably with the term "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0058] <Notes on definitions of terms> The following provides an explanation of the definitions of each term used in this specification.

[0059] In this specification, the term "trench" or "groove" refers to a thin, band-shaped recess. This refers to only that.

[0060] In this specification, when a film is represented by, for example, silicon oxynitride, it is represented by SiOxNy. In this case, x and y may be natural numbers or numbers with decimal points. Good too.

[0061] <About connection> In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to the above, it also includes those that are electrically connected. Here, A and B are electrically connected. Being connected means that there is an object between A and B that has some electrical effect. A communication line is a line that enables the transmission of electrical signals between A and B.

[0062] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another subject matter (or a part of the subject matter) described in the above and / or one or more other embodiments The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. It is possible to do things like drawing.

[0063] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to the content that is stated or stated using the text in the specification.

[0064] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part of them) described in the other embodiments of the present invention, This allows even more diagrams to be constructed.

[0065] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to the drawings. explain.

[0066] 1A, 1B, and 1C are top views and diagrams of a transistor 10 according to one embodiment of the present invention. 1(A) is a top view, and FIG. 1(B) is a cross-sectional view of the structure shown in FIG. 1(A). FIG. 1(A) is a cross-sectional view of the A1-A2 section, and FIG. 1(C) is a cross-sectional view of the A3-A4 section. For clarity, some elements are illustrated enlarged, reduced, or omitted. The A1-A2 direction is called the channel length direction, and the dashed line A3-A4 direction is called the channel width direction. There are cases.

[0067] The transistor 10 includes a substrate 100, an insulating layer 110, an insulator 121, and a semiconductor layer 122. , an insulator 123, a source electrode layer 130, a drain electrode layer 140, and a gate insulating layer 1 50, a gate electrode layer 160, an insulating layer 175, an insulating layer 173, and an insulating layer 170. The transistor 10 has an insulating layer 110 on a substrate 100. The transistor 10 has an insulator 121 on the insulating layer 110. The transistor 10 has a semiconductor layer 122 on which a source electrode layer 130 and The transistor 1 has a drain electrode layer 140 and is electrically connected to the semiconductor layer 122. 0 has an insulating layer 173, which is made up of an insulator 121, a semiconductor layer 122, and an insulator 12 3, the source electrode layer 130 and the drain electrode layer 140 are in contact with each other. The gate 10 has an insulating layer 173, a source electrode layer 130, and a drain electrode layer 140 on which an insulating layer 17 is formed. 5, and the insulating layer 175 has a region in contact with the side surface of the insulator 123. The semiconductor layer 122 has an insulator 123 over it. The insulator 123 is insulator 1 as shown in FIG. 21, and has an area in contact with the side surfaces of the insulating layer 173 and the insulating layer 175. 1B, the lower surface of the insulating layer 170, the insulating layer 175, the source electrode layer 130, and The transistor 10 has an insulator 12 and a region in contact with the side of the drain electrode layer 140. The transistor 10 has a gate insulating layer 150 on the gate insulating layer 150. It has a top electrode layer 160.

[0068] <About insulators> In addition, the insulator (for example, the insulator 121 and the insulator 123) basically has insulating properties and is a gate. When the inlet or drain electric field becomes strong, current flows near the interface with the semiconductor layer. This refers to a layer that can

[0069] In addition, the above-described structure is such that the semiconductor layer 122 is connected to the source electrode layer 130 and the drain electrode The insulator 123 is in contact with the source electrode layer 130 and the drain electrode layer 140. Since the insulator 121 and the electrode layer 140 are in contact with each other during operation of the transistor 10, The semiconductor layer 122 and the insulator 123 have a high heat dissipation effect against heat generated in the semiconductor layer 122 and the insulator 123. do.

[0070] In addition, when the insulating layer 170 is formed, the transistor 10 has an insulating layer at the interface with the insulating layer 175. The material of the insulating layer 175 and the material of the insulating layer 170, or the gas used in forming the insulating layer 170, etc. A mixed layer is formed, and oxygen (referred to as excess oxygen, exO) is added to the mixed layer or insulating layer 175. Further, by performing heat treatment, the oxygen is diffused to the semiconductor layer 122 and becomes an insulating layer. The oxygen vacancies present in the body 121 and the semiconductor layer 122 can be compensated for by the oxygen. This makes it possible to improve transistor characteristics (e.g., threshold voltage, reliability, etc.). Cut.

[0071] The excess oxygen added during the formation of the insulating layer 170 is, for example, formed by sputtering. The oxygen radiance may change due to the voltage, power, plasma, or substrate temperature applied during film formation. The excess oxygen exists in various forms, such as oxygen ions, oxygen atoms, etc. is a state that has more energy than the stable state and penetrates into the insulating layer 175. It is possible.

[0072] The method of adding oxygen is not limited to the above method. It may have oxygen or may be modified by other methods after deposition (e.g., ion implantation, ion plasma immersion, etc.). Methods such as the above may also be used.

[0073] As shown in the cross-sectional view of the dashed line A3-A4 in FIG. 1(C), the transistor 10 has a channel In the width direction of the gate electrode layer 160, the gate insulating layer 150 is interposed between the insulator 121 and the semiconductor The conductor layer 122 faces the side of the insulator 123. That is, when a voltage is applied to the gate electrode layer 160, Then, the insulator 121, the semiconductor layer 122, and the insulator 123 are gated in the channel width direction. The semiconductor layer 122 is surrounded by the electric field of the gate electrode layer 160. The structure of the transistor is called the surrounded channel (s-channel The transistor 10 is also called a self-aligned gate electrode layer using a trench. Since the source electrode layer and the drain electrode layer can be formed on the semiconductor substrate, the alignment accuracy is relaxed. This makes it possible to easily manufacture a miniaturized transistor. This structure is called a self-aligned s-channel FET (Self Aligned S-channel FET). s-channel FET, SA s-channel FET) structure, or Trench gate s-channel FET FET) structure, or TGSA s-channel FET (Trench Gate e Self Align FET) structure, or GLSA s-channel FE This is called the T (Gate Last Self Align FET) structure.

[0074] Here, the insulator 121, the semiconductor layer 122, and the insulator 123 are collectively called the semiconductor layer 120. In this case, in a transistor having a TGSA structure, the entire semiconductor layer 120 ( In the off state, a channel is formed in the semiconductor bulk, increasing the on-state current. Since the entire channel region formed in the conductor layer 120 can be depleted, The flow can be further reduced.

[0075] In addition, since the transistor 10 has a TGSA structure, or reducing the parasitic capacitance occurring between the gate electrode and the drain electrode, thereby improving the cutoff frequency of the transistor 10. This allows the transistor 10 to have high-speed response, for example by improving wave number characteristics.

[0076] In this embodiment, the second insulating film that will become the insulating layer 175 is formed on the source electrode layer as described later. 130, a flattening process is performed until the drain electrode layer 140 is exposed, and then an insulating layer 173 and When forming the third insulating film, the upper surface of the insulating layer 173, the source electrode layer 130 and the drain electrode layer 131 are in contact with each other. It is preferable that the upper surface of the drain electrode layer 140 is flush with the substrate surface. The insulating layer 173 on the source electrode layer 130 and the drain electrode layer 140 is formed uniformly within the substrate surface. This allows the process of forming the groove 174 (for example, the etching process time) to be stable. As a result, the transistor 10 can be stably manufactured. This makes it possible to stabilize the shape of the transistor and reduce the variation in transistor characteristics. It can be suppressed.

[0077] The position of the top surface of the source electrode layer 130 or the drain electrode layer 140 is the same as that of the gate electrode layer It may be lower than the position of the bottom surface of 160, may be the same as, or may be higher.

[0078] In addition, the upper surface of the gate electrode layer 160 of the transistor 10 is located below the upper surface of the insulating layer 175. The transistor 10 may also include a source electrode layer 130 and a drain electrode layer 14. 0 may have a shape shorter than the semiconductor layer 122 in the channel length direction, or may have a shape longer than the semiconductor layer 122 in the channel length direction. may have the following structure:

[0079] <Channel length> Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor through which current flows when the transistor is in the on-state). or a source (source region or source electrode) in the region where the channel is formed This refers to the distance between the drain (drain region or drain electrode) and the transistor. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is a value, a maximum value, or a minimum value in the region where the channel is formed. Or the average value.

[0080] <About channel width> The channel width is the width of the semiconductor (or transistor) when it is in the on state. This refers to the length of the area where the gate electrode overlaps with the current-carrying part of a transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is a value that can be any one of the values, the maximum value, the minimum value, or the like in the region where the channel is formed. or the average value.

[0081] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in transistors that contain small, three-dimensional channels, In some cases, the proportion of the channel region formed on the surface is large. In such cases, The effective channel width is smaller than the apparent channel width shown by the The width will be larger.

[0082] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0083] <SCWについて> Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel width in the region is called the Surrounding Channel Width (SCW). In this specification, it is simply called When channel width is mentioned, it refers to enclosed channel width or apparent channel width. In this specification, when the term "channel width" is used, it means an effective channel width. In addition, channel length, channel width, effective channel width, apparent channel width, The width of the upper channel and the width of the enclosed channel are obtained by taking a cross-sectional TEM image. The value can be determined, such as by analysis.

[0084] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0085] <Improvement of characteristics through miniaturization> In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the ON current is reduced, the ON current decreases.

[0086] However, in the transistor according to one embodiment of the present invention shown in FIG. An insulator 123 is formed so as to cover the semiconductor layer 122 in which the channel is formed. The channel formation layer and the gate insulating layer are not in contact with each other. This suppresses the scattering of carriers at the interface with the insulating layer, thereby increasing the on-state current of the transistor. It can be heard.

[0087] In the transistor of one embodiment of the present invention, the channel width of the semiconductor layer 122 serving as the channel is Since the gate electrode layer 160 is formed so as to electrically surround the semiconductor layer 12 in the direction For 2, a gate electric field is applied from the side in addition to the vertical gate electric field. That is, a gate electric field is applied to the entire semiconductor layer 122, and the current flows through the semiconductor layer 122. Since the on-current flows through the entire layer 122, the on-current can be further increased.

[0088] In the transistor of one embodiment of the present invention, the insulator 123 is formed by dividing the insulator 121 and the semiconductor layer 122. By forming the semiconductor layer 122 on the upper side, it becomes difficult to form an interface state. By forming the layer as a barrier, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to improving the on-state current of the transistor as mentioned above, the threshold voltage is stabilized and the S Therefore, the Icut (gate This reduces the input current (the current when the output voltage VG is 0V) and reduces power consumption. In addition, the threshold voltage of the transistor is stabilized, improving the long-term reliability of the semiconductor device. It can be raised.

[0089] In this embodiment, the semiconductor layer 120 (the semiconductor layer 122) ) is used as an example, but one aspect of the embodiment of the present invention is not limited to this. For example, the channel or its vicinity, the source region, the drain region, etc., may be Or, depending on the situation, silicon (including strained silicon), germanium, silicon germanium, etc. Silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride The insulating layer 11 may be formed of a material having lithium, an organic semiconductor, or the like.

[0090] <Transistor structure> The structure of a transistor in this embodiment will be described below.

[0091] <<Substrate 100>> The substrate 100 may be, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a multi-crystal Semiconductor substrates, compound semiconductor substrates made of silicon germanium, SOI (Silicon on Insulator) It is also possible to use a silicon on insulator (SiC) substrate, and on these substrates The substrate 100 may be a substrate on which a semiconductor element is provided. It may be a substrate on which other devices such as transistors are formed. At least one of the gate electrode layer 160, the source electrode layer 130, and the drain electrode layer 140 of the transistor At least one of the devices may be electrically connected to the other devices described above.

[0092] A flexible substrate may be used as the substrate 100. As a method for providing the transistor, a transistor is formed on a non-flexible substrate, and then the transistor is Alternatively, the substrate 100 may be peeled off and transferred to a flexible substrate 100. A peeling layer may be provided between the substrate and the transistor. Alternatively, a sheet, film, or foil having a stretchable structure may be used. In addition, the substrate 100 has the property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate 100 may have a property of not returning to its original shape. For example, the thickness is 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and more preferably 10 μm or more and 500 μm or less. The thickness of the substrate 100 is preferably 15 μm or more and 300 μm or less. In addition, by making the substrate 100 thinner, it is possible to reduce the weight of the substrate. It has the ability to stretch even when bent or pulled, and to return to its original shape when bending or pulling is stopped. Therefore, the semiconductor device on the substrate 100 may be subjected to a shock due to being dropped or the like. In other words, a robust semiconductor device can be provided.

[0093] The substrate 100, which is a flexible substrate, may be, for example, a metal, an alloy, a resin, or a glass. The substrate 100, which is a flexible substrate, has a linear expansion coefficient of The lower the temperature, the more preferable it is since deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 The resin may be, for example, polyester or polyolefin. Polyimide, polycarbonate, acrylic Aramid, in particular, has a linear expansion coefficient of Since the resistance is low, it is suitable for the substrate 100 which is a flexible substrate.

[0094] Insulating layer 110 The insulating layer 110 serves to prevent the diffusion of impurities from the substrate 100 and also serves to prevent the semiconductor layer 120 (semiconductor layer 122). The layer 110 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. It is more preferable that the insulating film is an insulating film. For example, the oxygen emission in terms of oxygen atoms by the TDS method is Output is 1.0 x 10 19 The film is assumed to have a density of at least atoms / cm3. The surface temperature of the film at this time is 100°C to 700°C or 100°C to 500°C. As described above, the substrate 100 may be a substrate on which other devices are formed. In the case where the insulating layer 110 is a plate, the insulating layer 110 also functions as an interlayer insulating film. CMP (Chemical Mechanical Polishing) is used to make the surface flat. It is preferable to perform a flattening treatment by method (g) or the like.

[0095] Insulators 121, 123, semiconductor layer 122 Oxides that can be used as the insulator 121, the semiconductor layer 122, and the insulator 123 are It is preferable that the alloy contains at least indium (In) or zinc (Zn). It is preferable that the oxide contains both In and Zn. To reduce the variation in the electrical properties of the stators, it is preferable to include a stabilizer therewith. Representative examples include In-Ga oxide, In-Zn oxide, In-Mg oxide, and Zn- Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, C e, Mg, or Nd).

[0096] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, with other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0097] When the insulator 123 is an In-M-Zn oxide, the sum of In and M is 100 at The atomic ratio of In and M in terms of omic percentage is preferably 25 atomic percent In. c% or more, M is less than 75 atomic %, and more preferably In is 34 atomic % In the above, M is less than 66 atomic%.

[0098] The indium and gallium contents of the insulator 123 were determined using time-of-flight secondary ion mass spectrometry. (TOF-SIMS), X-ray electron spectroscopy (XPS), ICP mass spectrometry (ICP-MS) ) for comparison.

[0099] The semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more. Since the potential is preferably 3 eV or more, the off-state current of the transistor 10 can be reduced. .

[0100] The thickness of the semiconductor layer 122 is 3 nm to 200 nm, preferably 3 nm to 100 nm. Further, the thickness is more preferably 3 nm or more and 50 nm or less.

[0101] The insulator 121 and the insulator 123 are composed of one or more elements that constitute the semiconductor layer 122. Therefore, the semiconductor layer 122, the insulator 121, and the insulator 12 At the interface with 3, interfacial scattering is unlikely to occur. Since electron transport is not impeded, the field effect mobility of transistor 10 is increased.

[0102] The insulators 121 and 123 are typically made of In-Ga oxide, In-Zn oxide, or In n-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Zn oxide (M is A l, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd) and a semiconductor The energy level of the conduction band minimum is closer to the vacuum level than that of the layer 122, and is typically an insulator 12 1. The energy level of the conduction band minimum of the insulator 123 and the energy level of the conduction band minimum of the semiconductor layer 122 The difference between the energy level and the .2 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less That is, the electron affinity of the insulator 121 and the insulator 123 and the electron affinity with the semiconductor layer 122 The difference between the force is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Electron affinity indicates the energy difference between the vacuum level and the bottom of the conduction band.

[0103] The insulators 121 and 123 are made of Al, Ti, Ga, Y, Zr, Sn, La, Ce, By having Mg or Nd in a higher atomic ratio than In, the following effects can be obtained. (1) The energy gap of the insulator 121, the semiconductor layer 122, and the insulator 123 is (2) The electron affinity of the insulators 121 and 123 is decreased. (3) The external (4) It has higher insulating properties than the semiconductor layer 122. (5) Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd has a bonding strength with oxygen. Since these elements have strong metal properties, Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, By having Nd in a higher atomic ratio than In, oxygen vacancies are less likely to occur.

[0104] The insulators 121 and 123 have higher insulating properties than the semiconductor layer 122. It has the same function as the gate insulating layer.

[0105] When the insulators 121 and 123 are In-M-Zn oxides, excluding Zn and O, The atomic ratio of In and M is preferably less than 50 atomic % for In and less than 50 atomic % for M. atomic % or more, more preferably, In is less than 25 atomic % and M is 75 atomic % or more. omic% or higher.

[0106] The insulators 121 and 123 are made of In-M-Zn oxide (wherein M is Al, Ti, Ga, Y). , Zr, Sn, La, Ce, Mg, or Nd), the insulating layer 122 is M (Al, Ti, Ga, Y, Zr, Sn, La, C) contained in the insulator 121 and the insulator 123 The atomic ratio of ZnO (Mg, Mg, or Nd) is high, and typically, the above-mentioned The atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher than that of the atomic ratio. The element M mentioned above bonds more strongly with oxygen than indium, so oxygen The insulator 121 and the insulator 123 have a function of suppressing the occurrence of defects. The semiconductor layer 121 and the insulator 123 are oxide films in which oxygen vacancies are less likely to occur than in the semiconductor layer 122 .

[0107] The semiconductor layer 122 contains more indium than the insulators 121 and 123. In semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, By increasing the In content, more s orbitals overlap, so In is more abundant than M. The oxides with a composition with a lower In content have a higher mobility than the oxides with a composition with an equal or lower In content than M. Therefore, by using an oxide having a high indium content for the semiconductor layer 122, Thus, a transistor with high field effect mobility can be realized.

[0108] The semiconductor layer 122 is an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, S In the case of n, La, Ce, Mg, or Nd), the temperature used to deposit the semiconductor layer 122 is In the target, if the atomic ratio of metal elements is In:M:Zn=x1:y1:z1, x1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z1 / y1 is 1 / It is preferably 3 or more and 6 or less, more preferably 1 or more and 6 or less. 6 or less, the semiconductor layer 122 can be formed using CAAC-OS (C Axis Aligned-Oxide Synthetic Alignment System). ed Crystalline Oxide Semiconductor) film is formed. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn=1. :1:1, 1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1:3, 3:1:2 , 4:2:3, 4:2:4.1, etc.

[0109] The insulators 121 and 123 are made of In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd), insulator 121, insulator 123 In the target used to deposit the film, the atomic ratio of metal elements is In:M:Zn=x Assuming 2:y2:z2, x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more 6 or less, more preferably 1 or more and 6 or less. Note that by setting z2 / y2 to 1 or more and 6 or less it becomes easier to form CAAC-OS films as the insulator 121 and the insulator 123. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:4, 1:4:5, 1:4:6, 1:4: 7, 1:4:8, 1:5:5, 1:5:6, 1:5:7, 1:5:8, 1:6:8, 1: 6:4, 1:9:6, etc. Note that the atomic ratios of the insulator 121 and the insulator 123 each include a variation of plus or minus 40% of the above atomic ratio as an error.

[0110] Moreover, the insulator 123 can be replaced with a metal oxide, such as aluminum oxide (AlOx), gallium oxide (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), germanium oxide (GeOx), or zirconia (ZrOx), or the insulator 123 can have the metal oxide on it.

[0111] Note that the atomic ratio is not limited to these, and an appropriate atomic ratio can be used according to the required semiconductor characteristics.

[0112]

[0113]

[0114] Also, the insulator 121 and the insulator 123 may have the same composition. For example, as the insulator 121 and the insulator 123, an In-Ga-Zn oxide having an atomic ratio of In:Ga :Zn = 1:3:2, 1:3:4, or 1:4:5 used in the sputtering method may be used.

[0114]

[0114] Alternatively, the insulators 121 and 123 may have different compositions. The atomic ratio of the metal elements in the target used in the sputtering method is In:Ga:Zn= The In-Ga-Zn oxide of 1:3:4 was used as the insulator 123, and the target metal element Alternatively, an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2 may be used.

[0115] The thickness of the insulator 121, the semiconductor layer 122, and the insulator 123 is 3 nm or more and 100 nm or less. It is preferable that the thickness is 3 nm or less and 50 nm or less.

[0116] Here, the thickness of the semiconductor layer 122 may be formed thinner than that of the insulator 121. For example, the semiconductor layer 122 may be thickened. In this case, the on-state current of the transistor can be increased. It is sufficient if the thickness is such that the effect of suppressing the generation of interface states of the layer 122 is not lost. For example, The thickness of the semiconductor layer 122 is greater than or equal to 2 times the thickness of the insulator 121. The on-resistance of the transistor can be 100 times or more, 4 times or more, or 6 times or more. When it is not necessary to increase the on-current, the thickness of the insulator 121 is set to be equal to or greater than the thickness of the semiconductor layer 122. For example, the insulating layer 110, the insulating layer 170, the insulating layer 173, or the insulating layer 175 may be When the semiconductor layer 122 contains excess oxygen, the oxygen diffuses and is contained in the semiconductor layer 122 by heat treatment. This can reduce the amount of oxygen vacancies and stabilize the electrical characteristics of the semiconductor device.

[0117] In addition, the insulator 123, like the insulator 121, also serves to suppress the generation of an interface state of the semiconductor layer 122. For example, the thickness may be equal to or greater than that of the insulator 121. If the insulator 123 is thick, the electric field generated by the gate electrode layer 160 becomes thicker than that of the semiconductor. It is preferable to form the insulator 123 thinly, since it may be difficult to reach the layer 122. In addition, oxygen contained in the insulator 123 diffuses into the source electrode layer 130 and the drain electrode layer 140. In order to prevent the source electrode layer 130 and the drain electrode layer 140 from being oxidized, the insulator 12 is For example, the thickness of the insulator 123 is thinner than the thickness of the semiconductor layer 122. However, the thickness of the insulator 123 is not limited to this, and may be determined based on the withstand voltage of the gate insulating layer 150. Taking this into consideration, it is preferable to set it appropriately according to the voltage at which the transistor is driven.

[0118] When the insulator 121, the semiconductor layer 122, and the insulator 123 have different compositions, The surface was observed using a scanning transmission electron microscope (STEM). In some cases, it may be possible to observe the structure using a 3D Electron Microscope.

[0119] <About hydrogen concentration> Hydrogen contained in the insulator 121, the semiconductor layer 122, and the insulator 123 bonds with metal atoms. The lattice from which oxygen has been removed (or the part from which oxygen has been removed) reacts with the oxygen present to form water. When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, forming carriers. Therefore, oxides containing hydrogen can be used as semiconductors. The transistor used tends to have normally-on characteristics.

[0120] Therefore, in the insulator 121, the semiconductor layer 122, the insulator 123, and their interfaces, In addition to oxygen vacancies, it is preferable that hydrogen is reduced as much as possible. 121, the semiconductor layer 122, the insulator 123, and the secondary ion mass at their respective interfaces. Analysis method (SIMS: Secondary Ion Mass Spectrometry) The hydrogen concentration obtained by 16 atoms / cm 3 More than 2×10 20 ato ms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 5×10 or more 19 ato ms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 More than 1×10 19 a toms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 As a result, the transistor 10 The threshold voltage is positive (also called normally-off characteristic). Cut.

[0121] <Carbon and silicon concentrations> In addition, in the insulator 121, the semiconductor layer 122, the insulator 123, and their interfaces, When silicon or carbon, which is one of the group 14 elements, is included, the insulator 121 and the semiconductor layer 122 In addition, oxygen vacancies increase in the insulator 123, and an n-type region is formed. Therefore, the insulator 121, the semiconductor layer 122, the insulator 123, and the silicon at their interfaces are For example, the insulator 121, the semiconductor layer 1, and the carbon concentration are preferably reduced. 22, insulator 123, and silicon and The concentration of carbon is 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below Lower, preferably 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 Below or less, and more preferably 1×10 16 atoms / cm 3 More than 2×10 18 atoms / c m 3 As a result, the transistor 10 has a threshold voltage of + The device has electrical characteristics (also called normally-off characteristics).

[0122] <About the concentration of alkali metals or alkaline earth metals> In addition, alkali metals and alkaline earth metals generate carriers when combined with oxides. In some cases, the off-state current of the transistor may increase. 21, the semiconductor layer 122, the insulator 123, and the alkali metal or It is preferable to reduce the concentration of alkaline earth metals. For example, the insulator 121, the semiconductor The Al obtained by SIMS at the layer 122, the insulator 123, and their respective interfaces. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm 3 The following are the preferred Or 2×10 16 atoms / cm 3 As a result, the transistor The transistor 10 has electrical characteristics in which the threshold voltage is positive (also called normally-off characteristics). Yes.

[0123] <Nitrogen concentration> In addition, nitrogen is contained in the insulator 121, the semiconductor layer 122, the insulator 123, and the interfaces therebetween. When the n-type region is formed, electrons that act as carriers are generated, the carrier density increases, and an n-type region is formed. As a result, transistors using oxides containing nitrogen are normally-on. Therefore, the insulator 121, the semiconductor layer 122, the insulator 123, and At the interface, it is preferable that the nitrogen is reduced as much as possible. For example, 21, the semiconductor layer 122, the insulator 123, and the interfaces between them obtained by SIMS. The nitrogen concentration is 1×10 15 atoms / cm 3 5×10 or more 19 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 5×10 or more 18 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 Less than 1×10, more preferably 15 atoms / cm 3 5×10 or more 17 ato ms / cm 3 As a result, the transistor 10 has a threshold voltage of is positive (also called normally-off characteristic).

[0124] <About carrier density> By reducing impurities in the insulator 121, the semiconductor layer 122, and the insulator 123, the insulator The carrier density of the insulating layer 121, the semiconductor layer 122, and the insulator 123 can be reduced. Therefore, the insulator 121, the semiconductor layer 122, and the insulator 123 have a carrier density of 1× 10 15 pieces / cm 3 Less than or equal to 1×10 13 pieces / cm 3 More preferably, 8 or less ×10 11 pieces / cm 3 less than 1×10 11 pieces / cm 3 Less than, most preferably is 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 That is all.

[0125] The insulator 121, the semiconductor layer 122, and the insulator 123 are each formed of a material having a low impurity concentration and a defect level. By using an oxide film with a low potential density, it is possible to fabricate transistors with superior electrical characteristics. Here, the impurity concentration is low and the defect level density is low (there is little oxygen vacancy). High purity authentic or substantially high purity authentic means that the Intrinsic oxides have fewer carrier sources, so they can reduce carrier density. Therefore, a transistor in which a channel region is formed in the oxide film may be The threshold voltage tends to be a positive electrical characteristic (also called a normally-off characteristic). In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide film has a low density of defect states. In addition, the trap level density may be lower. The transistor using the oxide film has a significantly small off-state current and When the voltage between the drain electrodes (drain voltage) is in the range of 1 V to 10 V, the off-state current is Below the measurement limit of the body parameter analyzer, i.e., 1 × 10 -13 Achieved a characteristic of A or lower Therefore, a transistor in which a channel region is formed in the oxide film can be In some cases, the variation in electrical characteristics is small, resulting in a highly reliable transistor.

[0126] In addition, the transistor using the highly purified oxide film as described above for the channel formation region The off-state current is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V, or When the voltage is set to about 10 V, the off-state current normalized by the channel width of the transistor is several y It is possible to reduce the distortion to a level of A / μm to several zA / μm.

[0127] The insulator 121, the semiconductor layer 122, and the insulator 123 may, for example, have a non-single crystal structure. The non-single crystal structure may be, for example, a CAAC-OS, a polycrystalline structure, a microcrystalline structure, or a non-crystalline structure, which will be described later. Among non-single crystal structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0128] The insulator 121, the semiconductor layer 122, and the insulator 123 may have a microcrystalline structure, for example. The crystalline insulator 121, the semiconductor layer 122, and the insulator 123 are each, for example, 1 nm or more. The oxide film contains crystallites of less than 10 nm in size. Alternatively, the oxide film having a crystallite structure is, for example, It has a mixed phase structure with crystalline parts of 1 nm or more and less than 10 nm in the amorphous phase.

[0129] The insulator 121, the semiconductor layer 122, and the insulator 123 may be, for example, amorphous structures. The insulator 121, the semiconductor layer 122, and the insulator 123, which have an amorphous structure, are, for example, The oxide film is disordered and has no crystalline components. Alternatively, the oxide film with an amorphous structure is, for example, completely It has an amorphous structure and does not have any crystalline parts.

[0130] The insulator 121, the semiconductor layer 122, and the insulator 123 are CAAC-OS, microcrystalline The film may be a mixed film having regions of two or more structures, i.e., an amorphous structure and an amorphous structure. For example, a region having an amorphous structure, a region having a microcrystalline structure, and a CAAC-OS region are Alternatively, a mixed film may have a single layer structure, for example, a region of an amorphous structure and a region of a microcrystalline structure. The structure is layered with a region of SiO2 and a region of CAAC-OS.

[0131] The insulator 121, the semiconductor layer 122, and the insulator 123 each have a single crystal structure, for example. You may do so.

[0132] The oxide film, which is less likely to cause oxygen deficiency than the semiconductor layer 122, is in contact with the upper and lower sides of the semiconductor layer 122. By providing the second insulating layer 122, oxygen vacancies in the semiconductor layer 122 can be reduced. The semiconductor layer 122 is made of an insulator 121 having one or more metal elements constituting the semiconductor layer 122, an insulating Since the semiconductor layer 122 is in contact with the insulator 123, the interface between the insulator 121 and the semiconductor layer 122 and the interface between the semiconductor layer 122 and the insulator The interface state density at the interface with the substrate 123 is extremely low. After the oxygen is introduced, a heat treatment is performed to transfer the oxygen to the semiconductor layer 122 via the insulator 121. However, oxygen is not easily captured by the interface state at this time, and the insulator 12 is efficiently transferred to the interface state. The oxygen contained in the semiconductor layer 122 can be transferred to the semiconductor layer 122. In addition, oxygen vacancies in the insulator 121 can be reduced. Since oxygen is added, it is possible to reduce oxygen vacancies in the insulator 121. Furthermore, the localized state density of the semiconductor layer 122 can be reduced.

[0133] In addition, the semiconductor layer 122 may be an insulating film having a different constituent element (for example, a gate insulating film including a silicon oxide film). When the semiconductor comes into contact with a semiconductor insulating layer, an interface state is formed, and the interface state can form a channel. In such a case, a second transistor with a different threshold voltage appears, However, the semiconductor layer 122 may have a large apparent threshold voltage. The insulator 121 and the insulator 123 each containing one or more metal elements are in contact with the semiconductor layer 122. Therefore, the interface between the insulator 121 and the semiconductor layer 122 and the interface between the insulator 123 and the semiconductor layer 122 are The interface state is less likely to be formed at the interface.

[0134] The insulators 121 and 123 are components of the insulating layer 110 and the gate insulating layer 150, respectively. In order to prevent the formation of impurity levels due to the incorporation of a composition element into the semiconductor layer 122, It also functions as a barrier film for

[0135] For example, the insulating layer 110 or the gate insulating layer 150 may be an insulating film containing silicon. In this case, the silicon in the gate insulating layer 150 or the insulating layer 110 and the gate insulating layer 150 Carbon that may be mixed into the insulator 121 or the insulator 123 penetrates into the insulator 121 or 123 up to a depth of several nm from the interface. When impurities such as silicon and carbon enter the semiconductor layer 122, the impurity level In some cases, the impurity level acts as a donor and generates electrons, making the material n-type.

[0136] However, if the thickness of the insulators 121 and 123 is greater than a few nm, the mixed Since impurities such as silicon and carbon do not reach the semiconductor layer 122, the influence of the impurity level is small. is reduced.

[0137] Therefore, by providing the insulators 121 and 123, the threshold voltage of the transistor It is possible to reduce the variation in electrical characteristics such as the above.

[0138] Furthermore, the gate insulating layer 150 and the semiconductor layer 122 come into contact with each other, and a channel is formed at the interface between them. In this case, interface scattering occurs at the interface, and the field effect mobility of the transistor decreases. On the other hand, the insulators 121 and 123 each containing one or more metal elements constituting the semiconductor layer 122 are Since the insulating layer 121 is provided in contact with the semiconductor layer 122, the insulating layer 121 and the insulating layer 123 At the interface with the semiconductor, carrier scattering is less likely to occur, increasing the field-effect mobility of the transistor. It is possible.

[0139] In this embodiment, the amount of oxygen vacancies in the semiconductor layer 122 and the amount of oxygen vacancies in the semiconductor layer 122 It is possible to reduce the amount of oxygen vacancies in the insulators 121 and 123, which are formed by the semiconductor layer 12. The density of localized states of the transistor 2 can be reduced. The semiconductor device 10 has a high reliability and exhibits a small variation in threshold voltage. The transistor 10 described in this embodiment has excellent electrical characteristics.

[0140] Note that an insulating film containing silicon is often used as a gate insulating layer of a transistor. For the above reasons, the region of the oxide layer that serves as a channel of the transistor of one embodiment of the present invention In this way, it is preferable that the gate insulating layer is not in contact with the semiconductor layer. When a channel is formed at the interface between the silicon and the oxide layer, carrier scattering occurs at the interface, and the From this viewpoint, the oxide layer It is preferable to separate the region that becomes the channel from the gate insulating layer.

[0141] Therefore, the semiconductor layer 120 is a laminated structure of an insulator 121, a semiconductor layer 122, and an insulator 123. In this way, a channel can be formed in the semiconductor layer 122, and high field effect mobility and Moreover, a transistor having stable electrical characteristics can be formed.

[0142] The semiconductor layer does not necessarily have to be three layers, but may be a single layer, two layers, four layers, or even five or more layers. In the case of a single layer, the semiconductor layer 122 shown in this embodiment may have a structure as follows. A layer may be used.

[0143] <Band diagram> Here, a band diagram will be described. In the band diagram, the insulating layer 110, The conduction band minimums of the insulator 121, the semiconductor layer 122, the insulator 123, and the gate insulating layer 150 The energy (Ec) of

[0144] As shown in FIG. 3(A) and FIG. 3(B), an insulator 121, a semiconductor layer 122, and an insulator 123 are In this case, the energy of the conduction band minimum changes continuously. Since the elements constituting the insulator 122 and the insulator 123 are the same, oxygen easily diffuses between them. Therefore, the insulator 121, the semiconductor layer 122, and the insulator 123 have the following composition: Although it is a laminate of films with different thicknesses, it can also be said that it is physically continuous.

[0145] The oxide films that are laminated with the same main component are not simply laminated, but are continuously bonded ( In particular, the energy of the conduction band edge changes continuously between layers in a U-shaped well (US In other words, a transistor well structure is formed at the interface of each layer. The stacking is done so that there are no impurities that would form defect levels such as drop centers or recombination centers. If impurities are present between the layers of the laminated multilayer film, the energy The band continuity is lost, and carriers are trapped or recombined at the interface, resulting in annihilation. cormorant.

[0146] In FIG. 3B, the insulator 121 and the insulator 123 have the same Ec. However, they may be different.

[0147] As shown in FIG. 3B, the semiconductor layer 122 serves as a well in the transistor 10. It can be seen that a channel is formed in the semiconductor layer 122. Note that the semiconductor layer 122 is taken as the bottom. A buried-channel MOSFET with a U-shaped well structure in which the conduction band edge energy changes continuously is used. It can also be called Nell.

[0148] In addition, in the vicinity of the interface between the insulator 121 and the insulator 123 and an insulating film such as a silicon oxide film, In the insulator 121 and the insulator 123, trap levels due to impurities or defects may be formed. By providing the semiconductor layer 122 with the above-mentioned trap level, the semiconductor layer 122 can be separated from the trap level. The energy difference between Ec of the insulator 121 or the insulator 123 and Ec of the semiconductor layer 122 is When the difference is small, electrons in the semiconductor layer 122 exceed the energy difference and reach the trap level. When negatively charged electrons are captured in the trap level, A negative fixed charge is generated in the transistor, and the threshold voltage of the transistor shifts in the positive direction. Furthermore, in long-term storage tests of transistors, the traps were not fixed and did not affect the characteristics. There is concern that this could cause fluctuations in the

[0149] Therefore, to reduce the variation in the threshold voltage of the transistor, the insulator 121, and It is necessary to provide an energy difference between Ec of the insulator 123 and Ec of the semiconductor layer 122. The respective energy differences are preferably 0.1 eV or more, and 0.2 eV or more. More preferred.

[0150] It is preferable that the insulator 121, the semiconductor layer 122, and the insulator 123 each contain a crystalline portion. In particular, the use of crystals oriented along the c-axis provides stable electrical characteristics to transistors. It is possible.

[0151] In addition, in the band diagram shown in FIG. 3B, the insulator 123 is not provided and the semiconductor layer 12 2 and the gate insulating layer 150. Alternatively, gallium oxide (In-Ga oxide:93) may be provided. In addition, in the state where the insulator 123 is present, an In-Ga An oxide may be provided, or gallium oxide may be provided.

[0152] The semiconductor layer 122 is an oxide having a higher electron affinity than the insulators 121 and 123. For example, the semiconductor layer 122 is made of a material having a higher electron density than the insulators 121 and 123. The affinity is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, More preferably, an oxide having a larger molecular weight than the oxide having a molecular weight of 0.2 eV or more and 0.4 eV or less can be used.

[0153] The transistor described in this embodiment includes one or more metal elements forming the semiconductor layer 122. Since the semiconductor layer 122 and the insulator 121 are connected to each other, the insulator 121 and the insulator 123 are connected to each other. As a result, interface states are less likely to be formed at the interface between the insulator 123 and the semiconductor layer 122 . Therefore, by providing the insulators 121 and 123, the threshold voltage of the transistor, etc. This can reduce the variation and fluctuation in electrical characteristics.

[0154] Source Electrode Layer 130, Drain Electrode Layer 140 The source electrode layer 130 and the drain electrode layer 140 are made of copper (Cu), tungsten (W), molybdenum (Mo), and the like. Ribide (Mo), Gold (Au), Aluminum (Al), Manganese (Mn), Titanium (T i), Tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn) , Iron (Fe), Cobalt (Co), Ruthenium (Ru), Platinum (Pt), Iridium (I r), strontium (Sr), or other elements, or alloys, or A single or multilayer conductive layer containing compounds such as oxygen, nitrogen, fluorine, silicon, etc. as the main components. For example, when stacking, the lower conductive layer that contacts the semiconductor layer 122 is preferably The conductive layer has a material that easily bonds with oxygen, and the upper conductive layer has a material that is highly resistant to oxidation. In addition, high melting point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a low-resistance conductive material such as aluminum or copper. Furthermore, when a Cu-Mn alloy is used, oxidation occurs at the interface with an insulator containing oxygen. This is preferable because it forms manganese oxide, which has the function of suppressing the diffusion of Cu. When tantalum nitride is used, it has the effect of suppressing the diffusion of hydrogen and oxygen (barrier properties), and Tantalum nitride is preferable because it is resistant to oxidation.

[0155] In addition, when a conductive material that easily bonds with oxygen is brought into contact with an oxide semiconductor layer, The oxygen in the oxide semiconductor layer diffuses to the conductive material side, which is more likely to bond with oxygen. Oxygen vacancies occur in the area near the source electrode layer or the drain electrode layer, and a small amount of oxygen is The hydrogen contained in the region enters the oxygen vacancy, causing the region to become significantly n-type. Therefore, the n-type region can function as the source or drain of a transistor. This can be done.

[0156] For example, a laminated structure using W as the lower conductive layer and Pt as the upper conductive layer may be used. By this, the oxide semiconductor in contact is made n-type, and the conductive layer in contact with the insulating layer 175 is made n-type. This can suppress oxidation of the conductive layer.

[0157] Gate insulating layer 150 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), Yttrium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd) , hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon oxide nitride (SiNxOy) , silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide ( The gate insulating layer 150 may be an insulating film containing one or more of TaOx. The gate insulating layer 150 may be a laminate of the above materials. It may contain impurities such as zirconium (Zr).

[0158] Next, an example of a laminated structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0159] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the thickness of the gate insulating layer 150 can be made larger than that of the case where silicon oxide is used. In other words, the off-current is small. Furthermore, hafnium oxide, which has a crystalline structure, can be used to realize an amorphous transistor. It has a higher dielectric constant than hafnium oxide, which has a porous structure. To make a small transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic crystals. The above is not a limitation of one aspect.

[0160] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface states may function as trap centers. When hafnium oxide is placed adjacent to the channel region of a transistor, the interface states This may cause degradation of the electrical characteristics of the transistor. To achieve this, another film is placed between the channel region of the transistor and the hafnium oxide. It may be preferable to separate the membranes from each other by using a The film having the buffer function may be a film included in the gate insulating layer 150, or may be an oxide semiconductor. The film may be a film included in the conductor film. That is, the film having a buffer function may be silicon oxide. Silicon oxynitride, an oxide semiconductor, or the like can be used. The film may include a semiconductor having a larger energy gap than the semiconductor that is to be the channel region. Alternatively, an insulator is used. Alternatively, the film having a buffer function may be, for example, a material that is a channel region. Use a semiconductor or insulator that has a smaller electron affinity than the semiconductor that is being used. The film to be formed may be a semiconductor having a higher ionization energy than the semiconductor in the channel region. Conductors or insulators are used.

[0161] On the other hand, the interface states (trap By trapping charge in the charge center, it may be possible to control the threshold voltage of a transistor. In order to make the charge exist stably, for example, the channel region and hafnium oxide If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium Alternatively, if a semiconductor or insulator with a smaller electron affinity than hafnium oxide is placed, Alternatively, the film with a buffer function may have a higher ionization energy than hafnium oxide. By using such an insulator, the interface state This makes it difficult for the trapped charge to be released, and the charge can be retained for a long period of time. can.

[0162] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges at the interface state in the gate insulating layer 150, the gate potential must be increased from the oxide semiconductor film. Electrons can be moved toward the pole layer 160. As a specific example, a high temperature (e.g. 125°C to 450°C, typically 150°C to 300°C) The potential of the electrode layer 160 is set higher than the potential of the source electrode layer 130 and the drain electrode layer 140. It is sufficient to maintain the state for at least one second, typically at least one minute.

[0163] In this way, a transistor is formed in which a desired amount of electrons are trapped in the interface state of the gate insulating layer 150, etc. The threshold voltage of the gate electrode layer 160 and the voltage applied to the gate electrode layer 160 are shifted to the positive side. By adjusting the time for which the gate is turned on, the amount of electrons captured (the amount of change in the threshold voltage) can be controlled. If the charge can be trapped, it can be trapped in the gate insulating layer 150. A laminated film having a similar structure may be used for the other insulating layers.

[0164] <Gate electrode layer 160> The gate electrode layer 160 may include, for example, aluminum (Al), titanium (Ti), chromium (C r), Cobalt (Co), Nickel (Ni), Copper (Cu), Yttrium (Y), Zirconia (ZrO2) Zr, Molybdenum (Mo), Ruthenium (Ru), Silver (Ag), Tantalum (T A conductive film such as a tungsten (W) film and the like can be used. The electrode layer 160 can be a laminate. It can also be made of a conductive material containing nitrogen, such as the nitrides of the above materials. In addition, when tantalum nitride is used, it has the effect of suppressing the diffusion of hydrogen and oxygen. In addition, tantalum nitride itself is preferably used since it has a barrier property and is resistant to oxidation.

[0165] Insulating layer 170 The insulating layer 170 may contain oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), ma, and the like. Magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), In Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Hafnium (Hf) For example, the metals may include hafnium (Hf), tantalum (Ta), titanium (Ti), etc. , Aluminum oxide (AlOx), Magnesium oxide (MgOx), Silicon oxide (Si Ox), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), nitride Silicon (SiNx), Gallium oxide (GaOx), Germanium oxide (GeOx), Acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) , neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaO The insulating layer 170 may be a laminate of the above materials. may be also possible.

[0166] The insulating layer 170 may be made of an oxide containing In or Zn. In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd ) is available.

[0167] The insulating layer 170 preferably includes an aluminum oxide film. The aluminum oxide film is Has a barrier effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane Therefore, the aluminum oxide film can be used during and after the manufacturing process of the transistor. After manufacturing, the insulation of impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of transistors Preventing contamination of the semiconductor layer 122 with oxygen, which is the main component material, The insulating layer 110 is provided with a protective layer 122 to prevent unnecessary release of oxygen. It is suitable for use as a protective film.

[0168] In addition, the insulating layer 170 is preferably a film having an oxygen supplying ability. When the insulating film 170a is formed, a mixed layer of the insulating layer 170 and the insulating layer 175 is formed. The mixed layer or insulating layer 175 is doped with oxygen, and the oxygen is then converted into The oxygen diffuses into the oxide semiconductor and can compensate for oxygen vacancies in the oxide semiconductor. This makes it possible to improve the transistor characteristics (eg, threshold value, reliability, etc.).

[0169] In addition, another insulating layer may be provided above or below the insulating layer 170. For example, an oxide Magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulating film containing one or more of neodymium oxide, hafnium oxide, and tantalum oxide may be used. Oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), magnesium (Mg), Silicon (Si), Gallium (Ga), Germanium (Ge), Yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (H f), tantalum (Ta), titanium (Ti), etc. For example, aluminum oxide Aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), Silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), silicon nitride ( SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide Umium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide NdOx, hafnium oxide (HfOx) and tantalum oxide (TaOx) The insulating layer may be a laminate of the above materials. The insulating layer preferably has more oxygen than the stoichiometric composition. The released oxygen diffuses through the gate insulating layer 150 into the channel forming region of the semiconductor layer 120. Since the oxygen can be dispersed, oxygen can be compensated for the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained.

[0170] Insulating Layer 173 and Insulating Layer 175 The insulating layer 173 and the insulating layer 175 are formed of oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and the like. Al, Mg, Si, Ga, and Germanium Ge, Yttrium, Zirconium, Lanthanum, Neo It contains Nd, Hf, Ta, Ti, etc. For example, magnesium oxide (MgOx), silicon oxide (SiOx), Silicon nitride (SiOxNx), silicon oxynitride (SiNxOx), silicon nitride (S iNx), gallium oxide (GaOx), germanium oxide (GeOx), yttrium oxide Aluminum oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide Niobium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (TaOx), aluminum oxide An insulating film containing one or more kinds of aluminum (AlOx) can be used. 3 and insulating layer 175 may be a stack of the above materials. It is preferred that the fluorine-containing amine has more oxygen than the fluorine-containing amine.

[0171] Alternatively, the insulating layer 173 and the insulating layer 175 may be made of a low dielectric constant material (low-k material). For example, silicon oxide (SiOF) containing a few percent of fluorine (F) Carbon (C)-doped silicon oxide (SiOC), fluorinated silicate glass (FSG) , organic silicate glass (OSG), hydrogen silsesquioxane (HSQ), methylsil Sesquioxane (MSQ), organic polymer, polyimide, fluororesin (polytetrafluoro It can be formed using amorphous carbon with added fluorine, etc. By using a low-k material for the insulating layer 173 and the insulating layer 175, This allows the capacitance associated with the turbine 10 to be further reduced.

[0172] <Conductive layer 165> As shown in FIG. 2, the transistor 10 has a conductive layer 165 under the insulating layer 110. The conductive layer 165 can function as a bottom gate. 2B, the same potential as that of the gate electrode layer 160 can be applied. The conductive layer 165 can be made of, for example, copper (C u), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), Manganese (Mn), Titanium (Ti), Tantalum (Ta), Nickel (Ni), Chromium (C r), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), Platinum (Pt), iridium (Ir), strontium (Sr), and other elements. Or alloys, or compounds with oxygen, nitrogen, fluorine, silicon, etc. as their main components For example, the conductive layer 166 may include a resistant The conductive layer 167 may have a material that is highly oxidizable. It is preferable to use a high melting point material such as tungsten or molybdenum. It is preferable to form the insulating layer from a low resistance conductive material such as aluminum or copper.

[0173] <Transistor manufacturing method> Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. Note that the parts that overlap with those described in the above transistor configuration will be omitted. The A1-A2 direction shown in FIG. 6 to FIG. 14 corresponds to the channel shown in FIG. 1(A) and FIG. 1(B). The A3-A4 direction shown in FIG. 6 to FIG. 14 is also referred to as the A3-A4 direction. ) and the channel width direction shown in FIG. 1(C).

[0174] In this embodiment, each layer constituting a transistor (insulating layer, oxide semiconductor layer, conductive layer The deposition methods include sputtering, chemical vapor deposition (CVD), vacuum deposition, and pulsed laser deposition. It can be formed by using a PLD method. Alternatively, it can be formed by a coating method or a printing method. The deposition method includes sputtering, plasma enhanced chemical vapor deposition (PECVD), ) Although the [method] is representative, the thermal CVD method may also be used. As an example of the thermal CVD method, MOCVD (organic metal chemical vapor deposition) method or ALD (atomic layer deposition) method may be used.

[0175] <Thermal CVD method> Since the thermal CVD method is a film-forming method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0176] Also, in the thermal CVD method, a source gas and an oxidizing agent are simultaneously fed into the chamber, and the inside of the chamber is under atmospheric pressure or reduced pressure, and the reaction is carried out near or on the substrate to deposit on the substrate, thereby forming a film.

[0177] Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an In -Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In (CH3)3. Also, the chemical formula of trimethylgallium is Ga(CH3)3 . Also, the chemical formula of dimethylzinc is Zn(CH3)2. Also, these combinations are not limited, and triethylgallium (chemical formula Ga(C2H5 )3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5 )2) can be used instead of dimethylzinc.

[0178] <ALD method> A film-forming apparatus using a conventional CVD method, during film formation, a source gas (precursor) for the reaction One or more of the above are simultaneously supplied to the chamber. Precursors for the reaction are introduced into the chamber in sequence, and the sequence of gas introduction is repeated. For example, each switching valve (also called a high-speed valve) is turned on and off. Two or more precursors are supplied to the chamber in sequence by switching between them, and multiple precursors are mixed. To avoid dust, an inert gas (such as argon or nitrogen) is placed after the first precursor. In addition, instead of introducing an inert gas, the first precursor is introduced. Thus, after the first precursor is evacuated, the second precursor can be introduced.

[0179] Figure 4 (A), (B), (C), and (D) show the film formation process by the ALD method. 01 is adsorbed onto the surface of the substrate (see FIG. 4(A)), and a first monolayer is formed (FIG. 4(B)). In this case, metal atoms contained in the precursor bond with hydroxyl groups present on the substrate surface. Metal atoms can be bonded to alkyl groups such as methyl and ethyl groups. The first precursor 601 may be evacuated and then reacted with the second precursor 602 introduced. In response (see FIG. 4(C)), a second monolayer is deposited on the first monolayer to form a thin film. (See FIG. 4(D)). For example, if an oxidizing agent is included as the second precursor, A metal atom or an alkyl group bonded to the metal atom present in the first precursor and an acid A chemical reaction occurs between the first precursor and the second precursor, forming an oxide film. If a gas containing hydrogen is used as the catalyst, a metal film can be formed by a reduction reaction. do.

[0180] The ALD method is a film formation method based on surface chemical reactions, in which precursors are adsorbed onto the film surface, A self-limiting mechanism is in place, allowing the formation of more. For example, trimethylaluminum Such precursors react with the hydroxyl groups (OH groups) present on the surface of the film to be formed. Since only surface reactions occur due to the precursor coming into contact with the target surface and transferring thermal energy, Metal atoms in the precursor can be adsorbed on the surface to be film-formed through the precursor. Casa has a high vapor pressure, is thermally stable before deposition, does not self-decompose, and is highly soluble in water. It has the characteristics of rapid chemical adsorption. In addition, the precursor is introduced as a gas, so the exchange rate is low. If the precursors introduced into each other have enough time to diffuse, high aspect ratios can be achieved. Even in an area having irregularities, a film can be formed with good coverage.

[0181] In addition, in the ALD method, the gas introduction order is controlled and repeated multiple times until the desired thickness is achieved. By repeating the process, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the nozzle is turned on. By increasing the pressure, the deposition rate can be increased and the impurity concentration in the film can be reduced. can be done.

[0182] In addition, there are two types of ALD: ALD using heat (thermal ALD) and ALD using plasma ( In the thermal ALD method, thermal energy is used to induce the reaction of the precursor. In the plasma ALD method, the precursor reaction is carried out in the radical state. do.

[0183] The ALD method can deposit extremely thin films with high precision. Surface coating can be achieved even on uneven surfaces. The rate is high and the film density is high.

[0184] <Plasma ALD> In addition, by forming a film by the plasma ALD method, compared with the ALD method using heat (thermal ALD method) it is possible to form a film at a lower temperature. The plasma ALD method can, for example, form a film even at 100 °C or lower without reducing the film formation rate. Also, in the plasma ALD method, N2 can be radicalized by plasma, so it is possible to form not only oxides but also nitrides.

[0185] Also, in plasma ALD, the oxidizing power of the oxidant can be increased. As a result, when film formation is performed by ALD, the precursors remaining in the film or the organic components desorbed from the precursors can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced, and a film with a low impurity concentration can be obtained.

[0186] Also, when performing plasma ALD, radical species can be generated, and plasma can be generated in a state separated from the substrate, such as ICP (Inductively Coupled Plasma), and plasma damage to the substrate or the film on which the protective film is to be formed can be suppressed.

[0187] From the above, by using the plasma ALD method, compared with other film formation methods, the process temperature can be lowered, the surface coverage rate can be increased, and the film can be formed. As a result, the intrusion of water and hydrogen from the outside can be suppressed. Therefore, the reliability of transistor characteristics can be improved.

[0188] <Explanation of the ALD apparatus> FIG. 5(A) shows an example of a film formation apparatus using the ALD method. A film forming chamber (chamber 1701), a raw material supply unit 1711a, a raw material supply unit 1711b, High-speed valves 1712a and 1712b, which are flow rate controllers, and a raw material inlet 1713 a, a raw material inlet 1713b, a raw material outlet 1714, and an exhaust device 1715. The raw material inlets 1713a and 1713b are provided in the chamber 1701 and are connected to the feed pipes and valves. The raw material supply units 1711a and 1711b are connected to the raw material discharge port 1714. is connected to an exhaust device 1715 via an exhaust pipe, a valve, and a pressure regulator.

[0189] Inside the chamber is a substrate holder 1716 equipped with a heater. A membrane substrate 1700 is placed.

[0190] In the raw material supply units 1711a and 1711b, solid A raw material gas is formed from a raw material of a solid or liquid. The unit 1711b may be configured to supply a source gas.

[0191] In addition, an example in which two raw material supply units 1711a and 1711b are provided is shown. There is no particular limitation, and three or more valves may be provided. 12b can be precisely controlled by time and supplies either the source gas or the inert gas. The high-speed valves 1712a and 1712b are flow rate controllers for the source gas. It can also be said to be a flow rate controller for inert gas.

[0192] In the film formation apparatus shown in FIG. 5A, a film formation substrate 1700 is carried onto a substrate holder 1716. After the chamber 1701 is sealed, the substrate holder 1716 is heated by a heater to form a film. The substrate 1700 is heated to a desired temperature (for example, 100° C. or higher or 150° C. or higher), and a source gas supply of inert gas, exhaust by exhaust device 1715, and exhaust by exhaust device 1715. By repeating this process, a thin film is formed on the surface of the substrate.

[0193] In the film forming apparatus shown in FIG. 5(A), the raw material supply units 1711a and 1711b are provided with By appropriately selecting the raw materials (volatile organometallic compounds, etc.), One selected from aluminum (Al), tantalum (Ta), zirconium (Zr), etc. Depositing an insulating layer containing an oxide (including a composite oxide) containing the above elements. Specifically, an insulating layer containing hafnium oxide and an insulating layer containing aluminum oxide can be formed. an insulating layer including hafnium silicate; In addition, the insulating layer containing tungsten silicate can be formed. The raw materials (volatile organometallic compounds, etc.) are provided in the raw material supply unit 1711a and raw material supply unit 1711b. By appropriately selecting the layer, a metal layer such as a tungsten layer or a titanium layer, or a titanium nitride layer, etc. It is also possible to deposit thin films such as nitride layers.

[0194] For example, when a hafnium oxide layer is formed using a deposition apparatus that uses the ALD method, a solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is made by vaporizing hafnium amide (such as TDMAH) and acid. In this case, two types of gases are used: The first source gas supplied from the source supply unit 1711b is TDMAH, and the second source gas supplied from the source supply unit 1711c is TDMAH. The raw gas becomes ozone. The chemical formula for tetrakisdimethylamidohafnium is Hf [N(CH3)2]4. Other materials include tetrakis(ethylmethylamine). Nitrogen has the function of eliminating the charge trapping level. Therefore, by including nitrogen in the source gas, a hafnium oxide film having a low charge trap level density can be formed. It is possible.

[0195] For example, when forming an aluminum oxide layer using a deposition apparatus that uses the ALD method, A liquid containing a catalyst and an aluminum precursor compound (such as TMA) is vaporized into a raw gas, and the oxidizer is In this case, two types of gases are used, one for the reagent and the other for H2O. The first source gas is TMA, and the second source gas supplied from the source supply unit 1711b is H 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include:

[0196] For example, when forming a silicon oxide film using a deposition system that uses ALD, The chlorine contained in the adsorbed material is removed, and the oxidizing gas (O2 , nitrous oxide) radicals are supplied to react with the adsorbate.

[0197] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing B2H6 gas and WF6 The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. Alternatively, SiH4 gas may be used.

[0198] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- Then, Ga(CH3)3 gas and O3 gas are repeatedly introduced to form a GaO Then, Zn(CH3)2 gas and O3 gas are repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. By forming mixed compound layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers, It is also possible to use H2O obtained by bubbling an inert gas such as Ar instead of O3 gas. However, it is preferable to use O3 gas that does not contain H. In(CH 3) Instead of gas In(C2H5)3, gas Ga(CH3)3 may be used. Instead of the gas, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used. You may use it.

[0199] <Multi-chamber deposition equipment> Also, a multi-chamber manufacturing apparatus having at least one film forming apparatus shown in FIG. An example is shown in Figure 5(B).

[0200] The manufacturing equipment shown in FIG. 5(B) can continuously form a laminated film without exposing it to the air. The aim is to prevent impurities from being mixed in and improve throughput.

[0201] The manufacturing apparatus shown in FIG. 5(B) includes a load chamber 1702, a transfer chamber 1720, a pretreatment chamber 1703, The apparatus includes at least a chamber 1701, which is a film-forming chamber, and an unloading chamber 1706. The chambers of the manufacturing equipment (including the load chamber, processing chamber, transfer chamber, deposition chamber, unload chamber, etc.) In order to prevent moisture from adhering, the container is filled with an inert gas (such as nitrogen gas) with a controlled dew point. It is preferable to keep the pressure reduced, and desirably maintain the reduced pressure.

[0202] Additionally, chambers 1704 and 1705 utilize the same ALD method as chamber 1701. It may be a film forming apparatus, a film forming apparatus using a plasma CVD method, or a sp The deposition apparatus may be a deposition apparatus using a deposition method, or a metal organic chemical vapor deposition (MOCVD) method. Organic Chemical Vapor Deposition (TCCVD) method The deposition apparatus may be a deposition apparatus that uses the same.

[0203] For example, the chamber 1704 may be a film forming device that uses a plasma CVD method. The following is an example of a deposition system using the MOCVD method to deposit a multilayer film. show.

[0204] In FIG. 5B, the top view of the transfer chamber 1720 is shown as an example of a hexagon. If necessary, a manufacturing device having a polygonal shape or more and connected to more chambers may be used. In addition, in FIG. 5B, the top surface shape of the substrate is shown as a rectangle, but this is not particularly limited. Although FIG. 5B shows an example of a single-wafer type, a batch type deposition method in which a film is deposited on multiple substrates at once may also be used. It may also be a device.

[0205] <Formation of Insulating Layer 110> First, the insulating layer 110 is formed on the substrate 100. The insulating layer 110 is formed by a plasma CVD method, a thermal For example, aluminum oxide is deposited by CVD (MOCVD, ALD) or sputtering. nium, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, gallium oxide Al, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, halide oxide Oxide insulating films such as tantalum oxide and tantalum oxide, silicon nitride, silicon nitride oxide, and nitride aluminium oxide, aluminium nitride, or a mixture of these materials. Alternatively, the insulating layer 121 may be formed by laminating the above materials. The upper layer of the stack in contact with the first insulating film can be a source of oxygen to the semiconductor layer 122. It is preferably formed from a material that contains excess oxygen.

[0206] For example, the insulating layer 110 is formed of silicon oxynitride having a thickness of 100 nm by plasma CVD. A membrane may be used.

[0207] Next, a first heat treatment may be performed to remove water, hydrogen, and the like contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110. The heat treatment reduces the amount of diffusion of water, hydrogen, and the like into the first oxide semiconductor film to be formed later. It is possible.

[0208] <Formation of the first insulating film and the semiconductor film> Next, a first insulating film, which will later become an insulator 121, and a semiconductor layer 122 are formed on the insulating layer 110. The first insulating film and the semiconductor film are formed by sputtering, MOCVD, It can be formed by a PLD method or the like, and is more preferably formed by a sputtering method. The sputtering method used is RF sputtering, DC sputtering, AC sputtering, etc. In addition, in the sputtering method, the opposing target method (opposing electrode method, gas phase sputtering method) Sputtering method, VDSP (Vapor Deposition Spattering) method By forming the film by the method described above, plasma damage during film formation can be reduced. Cut.

[0209] For example, when the first insulating film is formed by a sputtering method, each channel in the sputtering device The members are using cryopreservation to remove as much water and other impurities as possible from oxide semiconductors. A high vacuum (5×10 -7 Pa~1×10 -4 The substrate on which the film is to be formed must be heated to 100° C. or higher, preferably 40 It is preferable to be able to heat the system to 0°C or higher. Alternatively, a turbomolecular pump and a cold trap can be used. In combination, this prevents gas containing carbon components and moisture from flowing back into the chamber from the exhaust system. It is also preferable to use a combination of a turbo molecular pump and a cryopump. A system may also be used.

[0210] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is preferable to use a highly purified sputtering gas. The gas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using a gas that is highly purified up to 1000 ppm, moisture and the like can be taken into the oxide semiconductor film. It can be prevented as much as possible.

[0211] The sputtering gas is a rare gas (typically argon), oxygen gas, or a rare gas and oxygen gas. In the case of a mixture of rare gas and oxygen gas, the rare gas is It is preferable to increase the gas ratio of oxygen.

[0212] Note that when the oxide semiconductor film is formed by, for example, a sputtering method, the substrate temperature The temperature is 150° C. or higher and 750° C. or lower, preferably 150° C. or higher and 450° C. or lower, and more preferably The oxide semiconductor film is formed at a temperature of 200° C. or higher and 420° C. or lower. A film can be formed.

[0213] The material of the first insulating film is selected so as to have a smaller electron affinity than the semiconductor film. can.

[0214] The semiconductor film has a higher indium content than the first insulator film and the second insulator film. In oxide semiconductors, the s orbitals of heavy metals mainly contribute to carrier conduction, By increasing the In content, more s orbitals overlap, so In is more abundant than Ga. In oxides with a higher In content than Ga oxides with a lower In content or the same amount as Ga Therefore, by using an oxide having a high indium content for the semiconductor layer 122, In this way, a transistor with high mobility can be realized.

[0215] In addition, when the first insulating film and the semiconductor film are formed by, for example, a sputtering method, By using a sputtering device with a thin chamber, the first insulating film and the semiconductor film are not exposed to the atmosphere. In this case, the interface between the first insulating film and the semiconductor film is This can prevent unnecessary impurities from entering the interface, and can reduce the interface state density. As a result, the electrical characteristics of the transistors, especially the characteristics in reliability tests, can be stably verified. It can be stabilized.

[0216] In addition, if damage occurs in the semiconductor film, the presence of the first insulating film prevents the semiconductor film from being damaged. This allows the semiconductor film, which acts as a conductive path, to be kept away from the damaged area, resulting in a transistor. This can stabilize the electrical characteristics of the capacitor, especially the characteristics during reliability testing.

[0217] For example, the first insulating film is formed by sputtering a composition of In:Ga:Zn=1:3: The oxide semiconductor film was formed to a thickness of 20 nm using a target with an atomic ratio of 4. In addition, a semiconductor film of In:Ga:Zn=1:1 can be formed by sputtering. The oxide semiconductor film was formed to a thickness of 15 nm using a target with an atomic ratio of 1:1. This can be done.

[0218] In addition, it is preferable to perform a second heat treatment after forming the first insulating film and the semiconductor film. By performing the heat treatment, the amount of oxygen vacancies in the semiconductor film can be reduced.

[0219] The temperature of the second heat treatment is 250° C. or higher and lower than the substrate distortion point, preferably 300° C. or higher and 650° C. or higher. °C or less, and more preferably 350°C to 550°C.

[0220] The second heat treatment is performed using a rare gas such as helium, neon, argon, xenon, krypton, or the like. or in an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, Atmosphere or dry air (dew point below -80°C, preferably below -100°C, preferably below - Heating may be performed in an air atmosphere at 120°C or less, or under reduced pressure. In addition to the dry air, it is preferable that the inert gas and oxygen gas do not contain hydrogen, water, etc. Typically, the dew point is -80°C or less, preferably -100°C or less. Treatment times range from 3 minutes to 24 hours.

[0221] In the second heat treatment, the heat transfer from a heating element such as a resistance heating element is used instead of an electric furnace. A device that heats the workpiece by induction or thermal radiation may be used. For example, the GRTA ( Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Ra RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device uses halogen lamps, metal Halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps The workpiece is heated by the radiation of light (electromagnetic waves) emitted from a lamp such as a high-pressure mercury lamp. The GRTA device is a device that performs the second heat treatment using high-temperature gas. The hot gas is an inert gas, such as nitrogen or a noble gas, such as argon. .

[0222] Note that the second heat treatment is performed after etching to form an insulator 121 and a semiconductor layer 122, which will be described later. may be performed after

[0223] For example, after heat treatment at 450°C for 1 hour in a nitrogen atmosphere, Heat treatment can be performed at 450° C. for 1 hour.

[0224] The above steps reduce oxygen vacancies in the semiconductor film and impurities such as hydrogen and water. In addition, a semiconductor film with a reduced localized level density can be formed.

[0225] <Formation of the first conductive film> Next, a first conductive film that will become the source electrode layer 130 and the drain electrode layer 140 is formed on the semiconductor film. The first conductive film is formed by sputtering, chemical vapor deposition (CVD) (organometallic chemical vapor deposition), etc. deposition (MOCVD), metal chemical vapor deposition, atomic layer deposition (ALD) or plasma Chemical vapor deposition (PECVD), evaporation, pulsed laser deposition (PLD) etc. can be used.

[0226] The material of the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), gold (A), u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), Chromium (Cr), Lead (Pb), Tin (Sn), Iron (Fe), Cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S r) or other materials, or alloys, or compounds that contain these as their main components. It is preferable to use a single layer or a multilayer of conductive films. For example, when using a multilayer, the semiconductor layer 12 The lower conductive layer in contact with 2 has a material that easily bonds with oxygen, and the upper conductive layer has an oxidation-resistant In addition, tungsten (W), which has both heat resistance and electrical conductivity, can be used. It is preferable to use a high melting point material such as aluminum ( It is preferable to form the electrode from a low-resistance conductive material such as Al (Al) or copper (Cu). When a Mn alloy is used, a film containing manganese oxide is formed at the interface with the insulator containing oxygen, and oxidation Manganese is preferred because it has the function of suppressing the diffusion of Cu.

[0227] For example, a tungsten film having a thickness of 20 to 100 nm is formed on the first conductive layer by sputtering. It can be formed as a film.

[0228] In addition, the conductive layer 130b formed by processing the first conductive film in a later step will be In the present invention, the semiconductor device has a function as a hard mask and a function as a source electrode layer and a drain electrode layer. Since an additional film formation process is not required, the semiconductor manufacturing process can be shortened. .

[0229] <Formation of insulator 121 and semiconductor layer 122> Next, a resist mask is formed by a lithography process, and the resist mask is used to The first conductive film is selectively partially etched to form a conductive layer 130b. After removing the resist on the layer 130b, the semiconductor film and the first The oxide semiconductor film 1 is selectively etched to remove the semiconductor layer 122 and the insulator 121. The island shape can be formed (see FIG. 6). The etching method is dry etching. The conductive layer 130b can be used as a hard mask to form a semiconductor By etching the first insulating film and the second insulating film, the etching efficiency was improved compared to when only a resist mask was used. In comparison, the edge roughness of the oxide semiconductor layer after etching can be reduced.

[0230] For example, methane gas and argon gas are used as etching gas, and the resist mask and The first oxide semiconductor film and the semiconductor film are selectively etched using the hard mask. In this way, the insulator 121 and the semiconductor layer 122 can be formed. 10 may be partially etched.

[0231] <Deposition of insulating film> Next, an insulating film 173a that will become the insulating layer 173 is formed on the insulating layer 110 and the conductive layer 130b. (See FIG. 7). The insulating film 173a is formed by a plasma CVD method, a thermal CVD method (MOCVD method, AL D), sputtering, or spin coating, for example, (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), silicon oxynitride Silicon (SiOxNy), Gallium oxide (GaOx), Germanium oxide (GeOx), Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx ), neodymium oxide (NdOx), hafnium oxide (HfOx) and tantalum oxide (Ta Oxide insulating films such as silicon nitride (SiNx) and silicon oxynitride (SiNxO Nitride such as aluminum nitride (AlNx), aluminum oxide nitride (AlNxOy) The insulating film can be formed of a carbide insulating film, a carbide insulating film, or a mixture of these materials. It may be a laminate.

[0232] Alternatively, the insulating film 173a may be made of a material with a low dielectric constant (a low-k material). For example, silicon oxide (SiOF) containing a few percent of fluorine (F) and silicon dioxide containing a few percent of carbon (C) are Silicon oxide (SiOC), fluorinated silicate glass (FSG), organic silicates Glass (OSG), Hydrogenated Silsesquioxane (HSQ), Methylsilsesquioxane ( MSQ), organic polymers, fluororesins (polytetrafluoroethylene), polyimides, It can be formed by using amorphous carbon doped with fluorine or the like.

[0233] Note that the second heat treatment may be performed after the insulating film 173a is formed.

[0234] <Planarization of the second insulating film> Next, the insulating film 173a is planarized until the conductive layer 130b is exposed, and the insulating layer 173 (See FIG. 8.) The planarization process is performed by CMP (Chemical Mechanical This can be done by using the Al Polishing method, etc. The thickness of the insulating film 175a on the conductive layer 130b within the plate surface can be made uniform.

[0235] Note that the second heat treatment may be performed after the insulating film 173a is planarized.

[0236] <Deposition of insulating film> Next, a third insulating film 175a which will become the insulating layer 175 is formed on the insulating layer 173 and the conductive layer 130b. (See Figure 9.)

[0237] The insulating film 175a can be formed using the same material and method as the insulating film 173a.

[0238] <Formation of grooves> Next, a resist mask 176 is formed on the insulating film 175a by a lithography process (FIG. 10). Note that after applying an organic film onto the insulating film 175a, or after applying a resist The lithography process may be performed after applying an organic film. It contains cholesteryl monomethyl ether, ethyl lactate, etc., and acts as an anti-reflective coating (BA) during exposure. RC (Bottom Anti Reflective Coating) function In addition, it is possible to improve the adhesion between the resist and the film and to improve the resolution.

[0239] In addition, when forming a transistor with an extremely short channel length, at least the source electrode layer 130, in the region dividing the conductive layer 130b which becomes the drain electrode layer 140, an electron beam is exposure, immersion exposure, and EUV (Extreme Ultraviolet) exposure. A resist mask is processed using a method suitable for fine line processing such as light, and then the etching process is The region can be etched by forming a resist mask by electron beam exposure. In this case, if a positive resist is used as the resist mask, the exposed area can be minimized. This makes it possible to improve the throughput. To form transistors with channel lengths of 100 nm or less, and even 30 nm or less. Alternatively, microfabrication may be performed by exposure technology using X-rays or the like.

[0240] Using the resist mask, the insulating film 175a is partially etched by dry etching. As a result, the insulating layer 175 is formed and the groove portion 174 is formed. is formed.

[0241] Next, the exposed conductive layer 130b is partially etched to separate the source electrode layer 13 0, the drain electrode layer 140 can be formed (see FIG. 11).

[0242] After the source electrode layer 130 and the drain electrode layer 140 are formed, etching residues are removed. In order to prevent this, a cleaning process may be performed. This can prevent short circuits in the drain electrode layer 140. Alkaline solutions such as tetramethylammonium hydroxide This can be done using an acidic solution such as diluted hydrofluoric acid, oxalic acid, or phosphoric acid. Note that the cleaning process etches a part of the semiconductor layer 122, and the semiconductor layer 122 is left untreated. A recess is formed.

[0243] For example, after the silicon oxynitride film formed as the insulating film 173a is planarized, the silicon oxynitride film is A resist mask is formed on the silicon film by lithography, and the resist mask and carbon are The silicon oxynitride is formed by dry etching using a gas containing nitrogen and fluorine. An opening process is performed, and the conductive layer 130b is dry-etched using a chlorine or fluorine-based gas. In this way, the source electrode layer 130 and the drain electrode layer 140 can be formed.

[0244] <Formation of second insulating film 123a> Next, a second insulating film to be used as an insulator 123 is formed on the semiconductor layer 122 and the insulating layer 175. The second insulating film 123a is formed in the same manner as the first insulating film. The second insulating film 123a can be made to have a smaller electron affinity than the semiconductor film. The material can be selected.

[0245] For example, the second insulating film 123a is formed by sputtering In:Ga:Zn= Using a target with an atomic ratio of 1:3:2, a 5 nm thick oxide semiconductor film was formed. It is possible.

[0246] <Formation of insulating film 150a> Next, an insulating film 150a that will become the gate insulating layer 150 is formed on the second insulating film 123a. The insulating film 150a may be made of, for example, aluminum oxide (AlOx), magnesium oxide (M Silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride oxide Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. The insulating film 150a may be a laminate of the above materials. 0a is the method of sputtering, CVD (plasma CVD, MOCVD, ALD, etc.), M The insulating film 150a can be formed by using the BE method or the like. An insulating film can be formed by appropriately using a similar method.

[0247] For example, a silicon oxynitride film having a thickness of 10 nm is formed as the insulating film 150a by the plasma CVD method. It is possible.

[0248] <Formation of Conductive Film 160a> Next, a conductive film 160a that will become a gate electrode layer 160 is formed on the insulating film 150a (FIG. 1 The conductive film 160a may be made of, for example, aluminum (Al), titanium (Ti), Chromium (Cr), Cobalt (Co), Nickel (Ni), Copper (Cu), Yttrium (Y ), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), tungsten (W), or a combination of these The conductive film 160a can be formed by a sputtering method or a CVD method. Plasma CVD, MOCVD, ALD, etc.), MBE, vapor deposition, plating, etc. The conductive film 160a can be formed by using a conductive film containing nitrogen. Alternatively, a laminate of the conductive film and a conductive film containing nitrogen may be used. It may be a single layer or a multilayer.

[0249] For example, titanium nitride is formed to a thickness of 10 nm by the ALD method, and tungsten is deposited by metal CVD. A laminated structure formed to a thickness of 150 nm by a method can be used.

[0250] <Flattening process> Next, a planarization process is performed. The planarization process is performed using a method such as CMP or dry etching. The planarization process may be terminated when the insulating film 150a is exposed, or may be terminated after the first step. The step may be terminated when the insulating film 123a of the second insulating film 123 is exposed, or when the insulating layer 175 is exposed. This may result in the gate electrode layer 160, the gate insulating layer 150, and the insulating layer 12. 3 can be formed (see FIG. 13).

[0251] The second insulating film 123a or the insulating film 150a is formed on the planarized insulating layer 175. If the second insulating film 1 has a resist mask, it may be processed using a new resist mask. A resist mask is formed on the insulating film 23a or the insulating film 150a by a lithography process. The mask has an area larger than the upper surface of the gate electrode layer 160. The insulating film 150a and the second insulating film 123a are selectively etched to form a gate insulating layer. 150, an insulator 123 may be formed.

[0252] In the transistor 10, by providing the insulator 123 in which oxygen vacancies are unlikely to occur, The desorption of oxygen from the side surface of the insulator 123 in the channel width direction is suppressed, and the occurrence of oxygen vacancies is prevented. This results in improved electrical characteristics and a highly reliable transistor. This can be realized.

[0253] <Deposition of Insulating Layer 170> Next, the insulating layer 173, the insulator 123, the gate insulating layer 150, and the gate electrode layer 160 are An insulating layer 170 is then formed.

[0254] The insulating layer 170 is formed by a plasma CVD method, a thermal CVD method (MOCVD method, ALD method), or a sintered body. For example, aluminum oxide (AlOx), magnesium oxide (MgO x), silicon oxide (SiOx), silicon oxynitride (SiOxNy), gallium oxide ( GaOx), germanium oxide (GeOx), yttrium oxide (YOx), zirconium oxide Zirconium oxide (ZrOx), lanthanum oxide (LaOx), neodymium oxide (NdOx), hafnium oxide Insulating oxides such as hafnium (HfOx) and tantalum oxide (TaOx), silicon nitride (SiNx), silicon oxide nitride (SiNxOy), aluminum nitride (AlNx), The insulating film is made of a nitride such as aluminum oxide (AlNxOy), or a mixture of these materials. The insulating layer 170 may be formed of a laminate of the above materials. For the insulating layer, an oxide containing In or Zn may be used. Representative examples include In-Ga oxide, In-Zn oxide, In-Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, or Nd).

[0255] The insulating layer 170 is formed by depositing an aluminum oxide film by a sputtering method. It is also preferable to use aluminum oxide as a sputtering target. It is also preferable that the gas used during film formation contains oxygen gas.

[0256] When the aluminum oxide film is formed, a mixed layer 171 is formed at the interface with the insulating layer 173. do.

[0257] For example, the oxygen gas used in forming the insulating layer 170 is applied when the film is formed by sputtering. Due to the influence of the applied voltage, power, plasma, and substrate temperature, oxygen radicals, oxygen ions, Oxygen atoms exist in various states and have higher energy states than the stable state. At this time, oxygen (excess oxygen, exO) 172 forms an insulating layer 173 or a mixture. It is added in layer 171 .

[0258] <Oxygen addition> In addition, the method for manufacturing the transistor 10 is not limited to the above method. The oxygen addition treatment may be performed on the insulating layer 110 or on the first insulating layer 110. This may be performed on the oxide semiconductor film or the second insulating film 123a. As the oxygen radical, oxygen atom, oxygen atomic ion, oxygen molecular ion, or the like, The oxygen doping method includes ion doping, ion implantation, and proton implantation. Plasma immersion ion implantation is one example.

[0259] When ion implantation is used as a method for adding oxygen, oxygen atomic ions can be used. Alternatively, oxygen molecular ions may be used. When oxygen molecular ions are used, the amount of oxygen added to the film increases. The oxygen molecular ions are capable of reducing damage to the film surface to which the oxygen is added. The oxygen molecules are separated into oxygen atoms and then added. Energy is used to add oxygen molecular ions to the membrane to which the oxygen is added. The energy per oxygen atom ion in This is lower than the case where oxygen is added to the film. Therefore, damage to the film to which the oxygen is added is reduced. It can be reduced.

[0260] In addition, when oxygen molecular ions are implanted, the oxygen is more easily absorbed than when oxygen atomic ions are implanted. The energy per atomic ion is low. Therefore, it is possible to implant oxygen molecular ions. This allows the acceleration voltage to be increased, and the throughput to be improved. In addition, by using oxygen molecular ions, compared to the case of using oxygen atomic ions, It is possible to halve the dose to add the same amount of oxygen atomic ions. As a result, the throughput of the manufacturing process can be increased.

[0261] In addition, when oxygen is added to the film to which the oxygen is added, oxygen atoms are added to the film to which the oxygen is added. The oxygen is added under conditions such that the peak of the concentration profile of the molecular ions is located. It is preferable to add oxygen to the film to be etched. As a result, the film is more resistant to oxygen ion implantation than when oxygen atomic ions are implanted. In addition, the acceleration voltage during implantation can be lowered, reducing damage to the film to which the oxygen is added. That is, the amount of defects in the film to which oxygen is added can be reduced. It is possible to suppress the change in the electrical characteristics of the transistor. This reduces damage to the film that is being processed, and suppresses fluctuations in the electrical characteristics of the transistor. It can be controlled.

[0262] Also, a plasma method is used in which a film to which oxygen is added is exposed to plasma generated in an atmosphere containing oxygen. By plasma immersion ion implantation (PIA), oxygen is added to the film to which the oxygen is added. The oxygen-containing atmosphere may be oxygen, ozone, nitrous oxide, nitrogen dioxide, or the like. The atmosphere contains a chemical gas. By exposing the film to which oxygen is to be added to the plasma, oxygen is added to the film to which oxygen is to be added. It is possible and preferable to increase the amount of the plasma. As an example, there is an ashing device.

[0263] For example, the acceleration voltage is 5 kV and the dose is 1×10 16 / cm 2 The oxygen molecule ions of The first oxide semiconductor film can be doped by an on-implantation method.

[0264] The above steps and the subsequent heat treatment are combined to form an oxygen deficiency in the semiconductor layer 122. The film to which oxygen has been added is different from the film before oxygen was added. In comparison, the film density is low.

[0265] Next, a third heat treatment may be performed. The third heat treatment is typically performed at a temperature of 150° C. or higher. Less than the plate strain point, preferably 250°C to 500°C, more preferably 300°C to 45°C The heat treatment can be performed at a temperature of 0° C. or lower. The added oxygen 172 diffuses and The oxygen migrates to the conductor layer 122 and compensates for the oxygen vacancies present in the semiconductor layer 122. This is possible (see Figure 14).

[0266] For example, by sputtering, using an aluminum oxide (AlOx) target, The insulating layer 170 is formed using a sputtering gas containing 50% by volume of oxygen. The thickness can be 20 nm to 40 nm. As a practical example, it can be heat-treated at 400° C. for 1 hour in an oxygen atmosphere.

[0267] Through the above steps, the localized level density of the semiconductor film is reduced, and a transistor having excellent electrical properties is obtained. It is also possible to produce a resistor that can be used to measure the electrical characteristics of the device. It is possible to manufacture highly reliable transistors with fewer defects.

[0268] (Embodiment 2) In this embodiment, a transistor having a structure different from that of the transistor 10 described in the first embodiment is used. A method for manufacturing the transistor 11 and the transistor 12 will be described.

[0269] <Modification 1 of Transistor 10: Transistor 11> Regarding the transistor 11 having a different shape from the transistor 10 shown in FIG. 1, FIG. explain.

[0270] 15A, 15B, and 15C are a top view and a cross-sectional view of a transistor 11. FIG. 15(A) is a top view of the transistor 11, and FIG. 15(B) is a top view of the transistor 11. 15(A) is a cross-sectional view taken along dashed line A1-A2, and FIG. 15(C) is a cross-sectional view taken along dashed line A3-A4.

[0271] In the transistor 11, the insulating layer 170 is formed on the insulator 121, the semiconductor layer 122, and the source electrode layer 13. 0, the transistor has an area in contact with the side surfaces of the drain electrode layer 140 and the insulating layer 175. Different from Sta. 10.

[0272] As described later, the transistor 11 includes an insulator 121, a semiconductor layer 122, a source electrode The layer 130, the drain electrode layer 140, and the insulating layer 175 are formed in the same process. This method differs from the method for manufacturing the transistor 10 in that no planarization process is performed during the manufacturing process.

[0273] <Method of manufacturing transistor 11> A method for manufacturing the transistor 11 will be described with reference to FIGS. For steps similar to those for the transistor 10 described above, the description therefor is incorporated herein by reference.

[0274] As shown in FIG. 16(A) and FIG. 16(B), a first insulating layer 110 and an insulator 121 are formed. The insulating film 121a, the semiconductor film 122a which becomes the semiconductor layer 122, the source electrode layer 130, and the drain electrode layer 130 are The conductive film 130a which becomes the rain electrode layer 140 and the insulating film 175a which becomes the insulating layer 175 are formed. A resist mask 176 is formed on the insulating film 175a by using a lithography method.

[0275] Next, the insulating film 175a and the conductive film 130a are partially etched using the resist mask 176. Then, the groove 174, the insulating layer 175b, and the conductive layer 130b are formed (see FIG. 17).

[0276] Next, the insulating layer 175b, the conductive layer 130b, the semiconductor film 122a, and the The insulating film 121a of the first insulating film 121 is partially etched to remove the insulating film 121, the semiconductor layer 122, and the source electrode 123. The layer 130, the drain electrode layer 140, and the insulating layer 175 are formed (see FIG. 18).

[0277] Next, a second insulating film 123a which becomes the insulator 123 and an insulating film 1 which becomes the gate insulating layer 150 are formed. 50a, and a conductive film 160a which will become a gate electrode layer 160 are sequentially formed (see FIG. 19).

[0278] Next, a conductive film 160a and an insulating film 160b are formed using a resist mask formed by lithography. The insulating film 150a and the second insulating film 123a are partially etched to leave the insulating film 123 and the A gate insulating layer 150 and a gate electrode layer 160 are formed (see FIG. 20).

[0279] The insulator 123, the gate insulating layer 150, and the gate electrode layer 160 do not have to be formed at the same time. As shown in FIGS. 21 and 22, the insulating film 150a may be etched without etching the insulator 123. A gate electrode layer 160 may be formed. The end portions of the gate electrode layer 50 and the gate electrode layer 160 may be formed so as not to overlap each other.

[0280] Next, an insulating layer 170 is formed and heat treatment is performed to diffuse oxygen 172 into the semiconductor layer 122. This can reduce oxygen vacancies in the semiconductor layer 122 (see FIG. 23).

[0281] Through the above steps, the transistor 11 can be manufactured.

[0282] In the method for producing the transistor 11, the insulating film 175a which becomes the insulating layer 175 is formed on the source electrode layer 1 30, the conductive film 130a that will become the drain electrode layer 140 can be formed before processing. Therefore, the thickness of the insulating film 175a can be made uniform within the substrate surface, and the etching process for forming the grooves 174 can be performed with ease. This allows the etching process time to be stabilized. Therefore, the shape of the transistor can be stabilized. The transistor characteristics can be stabilized.

[0283] <Modification 2 of Transistor 10: Transistor 12> Regarding the transistor 12 having a different shape from the transistor 10 shown in FIG. 1, explain.

[0284] 24A, 24B, and 24C are a top view and a cross-sectional view of a transistor 12. FIG. 24(A) is a top view of the transistor 12, and FIG. 24(B) is a top view of the transistor 12. 24(A) is a cross-sectional view taken along dashed line A1-A2, and FIG. 24(C) is a cross-sectional view taken along dashed line A3-A4.

[0285] Transistor 12 differs from transistor 10 in that it has an insulating layer 177 .

[0286] As described later, the first insulating film 121a which becomes the insulator 121, the semiconductor layer 122, the conductive film 110 which is to become the source electrode layer 130 and the drain electrode layer 140; 30a, an insulating film 175a which becomes the insulating layer 175, and an insulating film 177a which becomes the insulating layer 177. This method differs from the method for manufacturing the transistor 10 in that the above films are formed before processing each of the above films.

[0287] <Method of manufacturing transistor 12> A method for manufacturing the transistor 12 will be described with reference to FIGS. For steps similar to those for the transistor 10 described above, the description therefor is incorporated herein by reference.

[0288] A first insulating film 121a which becomes the insulator 121 and a semiconductor layer 122 are formed on the insulating layer 110. Conductive film 122a, conductive film 130a which will become source electrode layer 130 and drain electrode layer 140 , an insulating film 175a which becomes the insulating layer 175, and an insulating film 177a which becomes the insulating layer 177. Before processing, films are formed in sequence (see FIG. 25).

[0289] The insulating layer 177 can be formed of the same material and by the same method as the insulating layer 170. Cut.

[0290] Next, the insulating film 177a, the insulating film 175a, the conductive film 130a, and the semiconductor The insulating film 122a and the first insulating film 121a are partially etched to leave the insulator 121 and the semiconductor layer 122, a conductive layer 130b, an insulating layer 175b, and an insulating layer 171b are formed (see FIG. 26). At this time, the insulating layer 110 may be partially etched.

[0291] Next, an insulating film 173a that will become the insulating layer 173 is formed (see FIG. 27). , plasma CVD method, thermal CVD method (MOCVD method, ALD method), sputtering method, or The film can be formed by a coating method or the like.

[0292] Next, the insulating film 173a is planarized by CMP until the insulating layer 171b is exposed. The insulating layer 171b is then removed to form the insulating layer 173 (see FIG. 28). The polishing rate is low under the same CMP processing conditions as that of the SiO2 film. It is preferable that the ion exchange reaction has a function of

[0293] Next, a resist mask is formed on the insulating layer 173 and the insulating layer 171b by lithography. Then, the insulating layer 171b is used as a hard mask until the semiconductor layer 122 is exposed. This selectively etches a portion of the conductive layer 130b. The drain electrode layer 140 and the insulating layer 175 are formed (see FIG. 29).

[0294] Next, a second insulating film 123a, an insulating film 150a, and a conductive film 160a are formed in this order (FIG. 3). 0).

[0295] Next, the conductive film 160a, the insulating film 150a, and the second insulating film 123a are subjected to a planarization process. 31. (see).

[0296] Next, an insulating layer 170 is formed and heat treatment is performed to remove oxygen 172 up to the semiconductor layer 122. This allows the oxygen vacancies in the semiconductor layer 122 to be reduced (see FIG. 32).

[0297] Through the above steps, the transistor 12 can be manufactured.

[0298] In the method for producing the transistor 12, the insulating film 175a which becomes the insulating layer 175 is formed on the source electrode layer 1 30, the conductive film 130a that will become the drain electrode layer 140 can be formed before processing. Therefore, the thickness of the insulating film 175a can be made uniform within the substrate surface, and the etching process for forming the grooves 174 can be performed with ease. This allows the etching process time to be stabilized. Therefore, the shape of the transistor can be stabilized. The transistor characteristics (eg, threshold value, reliability, etc.) can also be stabilized.

[0299] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0300] (Embodiment 3) <Structure of oxide semiconductor> In this embodiment, a structure of an oxide semiconductor will be described.

[0301] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline Oxide Semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li ke oxide semiconductor), and amorphous oxide semiconductor.

[0302] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, and nc-OS.

[0303] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angles are flexible and the bond length is short. In other words, it is a structure that has order but does not have long-range order.

[0304] On the other hand, in the case of an essentially stable oxide semiconductor, It cannot be called an oxide semiconductor. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is transformed into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a periodic Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0305] <caac-os> First, let me explain about CAAC-OS.

[0306] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a conductor.

[0307] Transmission Electron Microscope (TEM) A composite analysis image (high resolution) of the bright-field image and the diffraction pattern of CAAC-OS was obtained by using a scope. When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between the pellets, i.e., grain boundaries, are not clearly visible. Therefore, it is not possible to clearly confirm the presence of the CAAC-OS. Therefore, it can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0308] The following describes the CAAC-OS observed by TEM. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration corrector function was used. In particular, it is called a Cs-corrected high-resolution TEM image. This was carried out using an atomic resolution analytical electron microscope, such as the JEM-ARM200F manufactured by Nippon Denki Co., Ltd. This can be done.

[0309] FIG. 33(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 33(A). From FIG. 33(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is the same as that of the surface on which the CAAC-OS film is formed (also called the surface on which the film is formed). The surface on which the CAAC-OS is formed or the top surface of the CAAC-OS reflects the unevenness of the surface on which the CAAC-OS is formed or the top surface of the CAAC-OS.

[0310] As shown in Figure 33(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 33(B) and Figure 33(C). Therefore, the size of each pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the tilt between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). In addition, CAAC-OS is also used as a C-Axis Aligned Nanocry The semiconductor may also be referred to as an oxide semiconductor having a stals structure.

[0311] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 33(D)). The inclination between the pellets observed in FIG. 33(C) The location where the crack occurs corresponds to an area 5161 shown in FIG.

[0312] FIG. 34(A) shows the Cs Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in FIG. 34(A). The enlarged Cs-corrected high-resolution TEM images are shown in Fig. 34(B), Fig. 34(C) and Fig. 34(D), respectively. 34(D). From Fig. 34(B), Fig. 34(C) and Fig. 34(D), the pellet is It can be seen that the metal atoms are arranged in triangular, tetragonal or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0313] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When the structure is analyzed using the out-of-plane method, the result is as shown in Figure 35(A). A peak may appear at a diffraction angle (2θ) of about 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0314] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31° In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the c-axis indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0315] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is In the case of scanning, as shown in FIG. 35(C), the peaks belonging to the crystal plane equivalent to the (110) plane Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0316] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe with a diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 36(A) is obtained. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, even with electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately aligned on the surface to be formed or the upper surface. On the other hand, the same sample was probed perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in FIG. (B) shows a ring-shaped diffraction pattern. Therefore, by electron diffraction, It is seen that the a-axis and b-axis of the pellets contained in the CAAC-OS have no orientation. In addition, the first ring in FIG. 36(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and other factors. The second ring in Figure 36(B) This is thought to be due to the (110) plane, etc.

[0317] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so the opposite view is taken. CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0318] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0319] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0320] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than a career Such an oxide semiconductor can be a high-purity intrinsic or It is essentially a high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and In other words, it can be said that the oxide semiconductor has stable characteristics.

[0321] <nc-os> Next, we will explain nc-OS.

[0322] In the high-resolution TEM image, the nc-OS is divided into two groups: one where the crystals can be confirmed, and the other where the crystals can be clearly confirmed. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. An oxide semiconductor having a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, nc-OS shows grain boundaries. In addition, the nanocrystals are different from the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is called pellets. There may be cases where this happens.

[0323] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be considered to be a-like OS or amorphous oxide semiconductor. For example, for nc-OS, the X-shaped pellets with a diameter larger than that of the pellets may not be distinguishable. When using the line, the peaks showing the crystal planes were not detected by the out-of-plane method. In addition, for nc-OS, a probe diameter larger than the pellet (e.g. 50n When electron diffraction is performed using an electron beam of 1000 nm or more, a halo-like diffraction pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than that of the pellet. When performing nanobeam electron diffraction using an electron beam with a diameter of n When nanobeam electron diffraction is performed on c-OS, bright spots appear in a circular (ring-like) pattern. In some cases, a ring-shaped area may be observed. In addition, multiple spots may be observed within the ring-shaped area. There are cases.

[0324] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0325] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0326] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0327] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0328] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0329] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Sample B) and CAAC-OS (sample C) are prepared. The sample in is also an In-Ga-Zn oxide.

[0330] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0331] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0332] Figure 37 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It can be seen that the crystal part of eOS becomes larger according to the cumulative dose of electron irradiation. As shown by (1) in Figure 37, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus) was 4.2×10 in size, but the cumulative irradiation dose was 4.2×10 8 e - / nm 2 On the other hand, in the nc-OS, the size of the nanoparticles grows to about 2.6 nm. For CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in 37, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are about 1.4 nm and 2.1 nm, respectively. I realize something.

[0333] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. In other words, a-like OS is not seen in nc-OS and CAAC-OS. It can be seen that compared with S, it has a less stable structure.

[0334] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0335] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0336] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, we estimate the density equivalent to a single crystal of the desired composition. The density corresponding to a single crystal of a desired composition can be determined by combining single crystals of different compositions. The weighted average of the proportion of It is preferable to estimate by combining different types of single crystals.

[0337] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds.

[0338] (Embodiment 4) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. Please refer to the following for explanation.

[0339] <Cross-sectional structure> FIG. 38A is a cross-sectional view of a semiconductor device of one embodiment of the present invention. In FIG. The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The semiconductor device shown in FIG. 2 has a transistor 2200 using a first semiconductor material in the lower part and In FIG. 38A, a transistor 2100 using a second semiconductor material is provided in the first region. As the transistor 2100 using the second semiconductor material, the transistor 2100 shown in the above embodiment may be used. The left side of the dashed line is the channel of the transistor. The left side is a cross section in the longitudinal direction, and the right side is a cross section in the channel width direction.

[0340] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide) The second semiconductor is a The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can operate at high speed. The transistor can be an excellent substrate by applying the transistor exemplified in the above embodiment. It is possible to obtain threshold characteristics and make a fine transistor. The fast switching speed allows for high-speed operation, and the low off-state current reduces leakage current.

[0341] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors may be used, and an appropriate transistor may be used depending on the circuit. In addition to using a transistor according to one embodiment of the present invention using a nitride semiconductor, other materials and structures are not required. For example, the specific configuration of the semiconductor device is not necessarily limited to that shown here.

[0342] In the structure shown in FIG. 38A, an insulator 2201 and an insulator The transistor 2100 is connected via the transistor 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the substrate are used to connect the wiring provided in the upper and lower layers. The electrodes are electrically connected to an insulator 2204 that covers the transistor 2100. A wiring 2205 is provided on the insulator 2204 .

[0343] In this way, by stacking two types of transistors, the area occupied by the circuit is reduced, Multiple circuits can be arranged at higher density.

[0344] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor film of the transistor 2200 is a silicon dung. This has the effect of terminating the ring bond and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 21 Hydrogen in the insulator provided near the semiconductor film of 00 generates carriers in the oxide semiconductor. This may be one of the factors that reduces the reliability of the transistor 2100. Therefore, the upper layer of the transistor 2200 using a silicon-based semiconductor material is oxidized. When the transistor 2100 using a semiconductor is stacked, hydrogen diffusion between the transistors may occur. It is particularly effective to provide an insulator 2207 having a function of preventing the above-mentioned. 7, the reliability of the transistor 2200 is improved by confining hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the transistor 2100 At the same time, reliability can be improved.

[0345] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0346] In addition, a transistor 2100 including an oxide semiconductor film is formed so as to cover the transistor 2100. It is preferable to form a blocking film having a function of preventing hydrogen diffusion on the substrate 2100. The blocking film can be made of the same material as the insulator 2207, and in particular, It is preferable to use an aluminum oxide film. The aluminum oxide film is resistant to hydrogen, moisture, etc. It has a high blocking effect that prevents both impurities and oxygen from passing through the membrane. Therefore, an aluminum oxide film is used as the blocking film covering the transistor 2100. This prevents oxygen from being released from the oxide semiconductor film included in the transistor 2100. At the same time, water and hydrogen can be prevented from entering the oxide semiconductor film. The blocking film may be used by laminating the insulator 2204 or by forming a blocking film under the insulator 2204. It may be provided on the side.

[0347] It should be noted that the transistor 2200 is not limited to a planar type transistor, but may be of various types. It can be a transistor. For example, it can be a transistor such as a FIN (fin) type, a TRI-GATE (tri-gate) type, etc. An example of a cross-sectional view in that case is shown in FIG. 38(D). An insulator 2212 is provided on a semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at the tip. Note that an insulator may be provided on the convex portion. The insulator functions as a mask for preventing the semiconductor substrate 2 211 from being etched when forming the convex portion. Note that the convex portion does not necessarily have a thin tip. For example, it may be a substantially rectangular parallelepiped convex portion or a convex portion with a thick tip. A gate insulator 2214 is provided on the convex portion of the semiconductor substrate 2211, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2215 are formed in the semiconductor substrate 2211. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0348] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0349] <CMOS inverter circuit> The circuit diagram shown in FIG. 38(B) is a so-called CMO in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their gates are connected. 4 shows the configuration of an S inverter.

[0350] <CMOSアナログスイッチ> In addition, the circuit diagram shown in FIG. 38C shows the transistors 2100 and 2200. The figure shows a configuration in which the source and drain of each are connected. It can function as a so-called CMOS analog switch.

[0351] <Example of storage device> By using a transistor according to one embodiment of the present invention, it is possible to preserve memory contents even in a state where power is not supplied. FIG. 39 shows an example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written. As shown in.

[0352] The semiconductor device shown in FIG. 39A includes a transistor 3200 using a first semiconductor material and a The semiconductor device includes a transistor 3300 using the semiconductor material of the second embodiment, and a capacitor element 3400 . Note that the transistor described in Embodiments 1 and 2 is used as the transistor 3300. There can be.

[0353] 39B is a cross-sectional view of the semiconductor device shown in FIG. In the example shown, a back gate is provided in the transistor 3300. It is also possible to adopt a configuration in which no.

[0354] The transistor 3300 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the off-state current of the transistor 3300 is small, This means that the memory contents can be retained for a long period of time without requiring a refresh operation. Alternatively, the frequency of refresh operations can be extremely low. This makes it possible to sufficiently reduce power consumption.

[0355] In FIG. 39A, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the transistor The other of the source electrode and the drain electrode of the transistor 3300 and the capacitor 3400 The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. are electrically connected.

[0356] In the semiconductor device shown in FIG. 39A, the potential of the gate electrode of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0357] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is provided with A given charge is applied (write). Here, the charge is applied to two different potential levels. (hereinafter referred to as low-level charge and high-level charge) After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, the gate of the transistor 3200 is turned on. The charge applied to the port electrode is retained (retained).

[0358] Since the off-state current of the transistor 3300 is extremely small, the gate The charge is retained for a long period of time.

[0359] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the transistor Depending on the amount of charge held in the gate electrode of the capacitor 3200, the second wiring 3002 is at a different potential. In general, if the transistor 3200 is an n-channel type, then the transistor 3200 The apparent threshold voltage V when a high-level charge is applied to the gate electrode of th_H This is seen when a low-level charge is applied to the gate electrode of transistor 3200. Threshold V th_L Here, the apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between By setting the potential V0, the charge applied to the gate electrode of the transistor 3200 is determined. For example, if a high level charge is applied during writing, The potential of the wiring 3005 of 5 is V0 (> V th_H ), then transistor 3200 is "ON" When a low-level charge is applied, the voltage of the fifth wiring 3005 is The digit is V0( <V th_L ), transistor 3200 remains in the "off state." Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be put out.

[0360] When memory cells are arranged in an array, only the information in a desired memory cell can be read. For example, in a memory cell from which information is not read, the gate voltage A potential at which transistor 3200 is in the “off state” regardless of the polarity state, i.e. V th_H By applying a smaller potential to the fifth wiring 3005, the information of the desired memory cell is Alternatively, in a memory cell from which information is not read, , a potential at which transistor 3200 is "on" regardless of the state of its gate electrode. , that is, V th_L By applying a larger potential to the fifth wiring 3005, a desired memory It is only necessary to have a configuration in which only the information in the cells can be read out.

[0361] The semiconductor device shown in FIG. 39(C) is different from the semiconductor device shown in FIG. 39(A) in that the transistor 3200 is not provided. In this case, the writing and holding of information is performed in the same manner as above. It is possible.

[0362] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in the free state and the capacitor element 3400 are electrically connected to each other. Charge is redistributed among the capacitor elements 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is the potential of one of the electrodes of the capacitor 3400 ( Alternatively, it takes a different value depending on the charge stored in the capacitor element 3400.

[0363] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 is in two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=(C B×VB0+C×V0) / (CB+C)).

[0364] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0365] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be laminated on the driver circuit.

[0366] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0367] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0368] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of devices (capacitive elements, resistive elements, etc.), the connection destination is not specified. However, a person skilled in the art may be able to configure one aspect of the invention. Even if the destination is not specified, one aspect of the invention is clear. When the contents are described in this specification, etc., one aspect of the invention that does not specify a connection destination is the same as the embodiment of the present specification. In particular, if the terminal is connected to multiple If multiple cases are possible, there is no need to limit the connection of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitors, resistors, etc.) By specifying the connection destinations of only some of the terminals of a device (such as a semiconductor device), This may constitute an aspect of the invention.

[0369] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art that If you are a person who has experience in the field of electronics, you may be able to identify the invention. In some cases, a person skilled in the art can identify an invention by at least specifying the function. In other words, if a function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, if the connection destination is specified, it can be considered as an embodiment of the invention. and can constitute one embodiment of the invention. For a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an embodiment of the invention.

[0370] In this specification, etc., in a drawing or text described in a certain embodiment, It is possible to extract a part of the invention and use it as an embodiment of the invention. If a figure or text describing a certain part is included, the figure or text of that part is taken out. The above-mentioned contents are disclosed as one aspect of the invention and constitute one aspect of the invention. Therefore, for example, active elements (transistors, diodes, etc.) etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic Drawings showing one or more of the following: materials, inorganic materials, parts, devices, operating methods, manufacturing methods, etc. Or, in a sentence, a part of it can be taken out and used to constitute one aspect of the invention. It is assumed that, for example, it has N (N is an integer) circuit elements (transistors, capacitor elements, etc.). From a circuit diagram composed of M (M is an integer, M < N) circuit elements (transistors, capacitor elements, etc.) extracted from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to constitute one aspect of the invention. As another example, From a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer, M < N) layers and constitute one aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer, M < N) elements and constitute one aspect of the invention. Furthermore, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer, M < N ) elements and constitute one aspect of the invention.

[0371] <Imaging device> Hereinafter, an imaging device according to one aspect of the present invention will be described.

[0372] FIG. 40(A) is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel unit 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. In this specification, etc., all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be referred to as "peripheral circuit" or "driving circuit". For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit.

[0373] The imaging device 200 preferably also includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0374] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel portion 210 is formed. Also, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuits. The peripheral circuits are a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. Any one or more of these may be omitted.

[0375] As shown in FIG. 40B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel size in the row direction and the pixel size in the pixel area can be increased. The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the captured images.

[0376] <Pixel configuration example 1> The imaging device 200 has a pixel 211 that is composed of a plurality of sub-pixels 212. The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By this, it is possible to obtain information for realizing a color image display.

[0377] FIG. 41A is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 41(A) is provided with a color filter that transmits light in the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") receives light in the green (G) wavelength band. A subpixel 212 (hereinafter, also referred to as “subpixel 212G”) is provided with a color filter that transmits A subpixel 212 is provided with a color filter that transmits light in the blue (B) and blue (C) wavelength bands. (hereinafter, also referred to as "subpixel 212B"). The subpixel 212 has a photo sensor. It can be made to function.

[0378] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, in the nth line (n is an integer of 1 to p), The wiring 248 and the wiring 249 connected to the pixel 211 of and wiring 249[n]. For example, in the m-th column (m is an integer between 1 and q), The wiring 253 connected to the pixel 211 is described as wiring 253[m]. ), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the mth column is 53[m]R, the wiring 253 connected to the subpixel 212G is the wiring 253[m]G, and The wiring 253 connected to the subpixel 212B is indicated as wiring 253[m]B. , and are electrically connected to the peripheral circuits via the wiring.

[0379] In addition, the imaging device 200 detects color filters of adjacent pixels 211 that transmit light of the same wavelength band. The sub-pixels 212 provided with filters are electrically connected to each other via switches. FIG. 41B shows a pixel 211 arranged in n rows and m columns, and a sub-pixel 212 of the pixel 211. 11 shows an example of a connection of a sub-pixel 212 of a pixel 211 arranged in the (n+1)th row and the (m)th column adjacent to the pixel 11. In FIG. 41B, the subpixel 212R arranged in the nth row and the mth column and the subpixel 212R arranged in the n+1th row and the mth column are The sub-pixels 212R arranged in the nth row and the mth column are connected via the switches 201. The subpixel 212G arranged in the n+1th row and the mth column is connected to the switch 202. In addition, the sub-pixel 212B arranged in the nth row and the mth column is connected via The sub-pixel 212B arranged in the second direction is connected via the switch 203.

[0380] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). The color filters transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have three sub-pixels for detecting light of different wavelength bands. By providing 212, a full color image can be obtained.

[0381] Alternatively, color filters that transmit red (R), green (G) and blue (B) light are provided. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Alternatively, pixel 211 may be used with pixel 212, or with cyan (C), yellow (Y In addition to the subpixel 212 provided with a color filter that transmits light of red (A) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. A single pixel 211 may include sub-pixels 211 for detecting light of four different wavelength bands. By providing the second filter 12, the color reproducibility of the captured image can be further improved.

[0382] Also, for example, in FIG. 41A, a sub-pixel 212 detects the red wavelength band, The ratio of the number of sub-pixels 212 that detect the blue wavelength band and the number of sub-pixels 212 that detect the blue wavelength band ( or light receiving area ratio) does not have to be 1:1:1. For example, The Bayer array may be used with red:green:blue=1:2:1. The light area ratio may be red:green:blue=1:6:1.

[0383] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that the number is two or more. By providing two or more sub-pixels 212 that detect the same wavelength band, redundancy is increased, and the imaging device This can improve the reliability of the device 200.

[0384] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0385] In addition, ND (Neutral Density) filters are used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows the dynamic range of the device to be increased.

[0386] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described with reference to a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 42A, a lens 255 and a filter 25 formed in a pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0387] However, as shown in the area surrounded by the dashed line, a part of the light 256 indicated by the arrow is Therefore, as shown in Figure 42(B), A lens 255 and a filter 254 are disposed on the conversion element 220 side. It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, the imaging device 200 with high detection sensitivity is provided. can be done.

[0388] As the photoelectric conversion element 220 shown in FIG. 42, a pn-type junction or a pin-type junction is formed. A photoelectric conversion element may also be used.

[0389] In addition, the photoelectric conversion element 220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating electric charges may be a sintered material. Iron, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0390] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0391] Here, one pixel 211 included in the imaging device 200 has a sub-pixel 212 shown in FIG. 2, may include a subpixel 212 having a first filter.

[0392] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of forming a pixel using the above will be described.

[0393] 43(A) and 43(B) are cross-sectional views of elements constituting the imaging device.

[0394] The imaging device shown in FIG. 43(A) is a silicon-based transistor provided on a silicon substrate 300. A transistor using an oxide semiconductor that is stacked on the transistor 351. A transistor 352 and a transistor 353, and a transistor 354 provided on the silicon substrate 300. Each transistor includes a photodiode 360 ​​having an anode 361 and a cathode 362. The photodiodes 360 are electrically connected to various plugs 370 and wiring 371. The anode 361 of the photodiode 360 ​​has a low resistance region 363. 3 and has an electrical connection with plug 370 via.

[0395] The imaging device includes a transistor 351 and a photodiode 352 disposed on a silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20 and in contact with layer 320, and includes transistors 352 and 353. A layer 330 is provided in contact with the layer 330 and has wiring 372 and wiring 373. It has 40.

[0396] In the example of the cross-sectional view of FIG. 43(A), the transistor 3 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is disposed on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. Alternatively, the light receiving surface of the gate 360 ​​may be the same as the surface on which the transistor 351 is formed.

[0397] In addition, when a pixel is configured using only transistors using an oxide semiconductor, the layer 31 Alternatively, the layer 310 may be omitted. Alternatively, a pixel may be formed using only a transistor including an oxide semiconductor.

[0398] In the cross-sectional view of FIG. 43(A), a photodiode 360 ​​provided in the layer 310 and a The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0399] FIG. 43B shows an imaging device in which a photodiode 365 is provided on the layer 340 side as a transistor. In FIG. 43B, for example, the layer 310 may have a structure in which The layer 320 includes a transistor 351 and a transistor 352 using silicon. 71, and the layer 330 includes a transistor 352 using an oxide semiconductor and a transistor 35 3, and layer 340 includes a photodiode 365, which is It is composed of semiconductor layers 366, 367, and 368, and has wiring 373 and a pro It is electrically connected to wiring 374 via lug 370 .

[0400] By using the element configuration shown in FIG. 43B, the aperture ratio can be increased.

[0401] In addition, the photodiode 365 is made of an amorphous silicon film or a microcrystalline silicon film. A pin-type diode element or the like may be used. The photodiode 365 is an n-type semiconductor A layer 368, an i-type semiconductor layer 367, and a p-type semiconductor layer 366 are laminated in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer 367. The p-type semiconductor layer 366 and the n-type semiconductor layer 368 are provided with dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon containing a dopant can be used. The photodiode 365, which uses silicon as a photoelectric conversion layer, has high sensitivity in the visible light wavelength range. It is highly sensitive to weak visible light.

[0402] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0403] (Embodiment 5) <RFタグ> In this embodiment, an RF device including a transistor or a memory device described in the previous embodiment is The tag will be described with reference to FIG.

[0404] The RF tag in this embodiment has a memory circuit therein and stores necessary information in the memory circuit. In addition, information is exchanged with the outside world using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems, etc. Therefore, extremely high reliability is required.

[0405] The structure of an RF tag will be described with reference to FIG. 44. FIG. 44 is a block diagram showing an example of the structure of an RF tag. FIG.

[0406] As shown in FIG. 44, an RF tag 800 includes a communicator 801 (also called an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 804. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor having the rectification effect included in the demodulation circuit 807 is sufficiently suppressed. A material capable of being used for the insulating layer 11 may be, for example, an oxide semiconductor. This suppresses the deterioration of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and communication is carried out by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment can be used with any of these methods. It is also possible to use it for.

[0407] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 is a rectifier for an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side of the rectifier circuit 805. A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent a certain amount of power from being input to the downstream circuit. This is a circuit for controlling the

[0408] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may include a reset signal generating circuit. The reset signal generating circuit uses the stable rise of the power supply voltage to reset the logic circuit 80. This is a circuit for generating a reset signal for 9.

[0409] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the

[0410] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. This is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 also stores a unique number (ID) and outputs it according to the processing. This is a circuit for this purpose.

[0411] The above-mentioned circuits can be selected or omitted as appropriate.

[0412] Here, the transistor described in the above embodiment can be used for the memory circuit 810. The transistor according to one embodiment of the present invention can retain data even when the power supply is cut off. Therefore, the memory circuit according to one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required to write data is significantly smaller than that of conventional non-volatile memory. It is also possible to eliminate the difference in maximum communication distance when reading and writing data. In addition, it prevents malfunctions or erroneous writing caused by insufficient power when writing data. It is possible.

[0413] In addition, the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must input the data to ROM811. A separate command is provided to write data, so that users cannot freely rewrite it. It is preferable for the manufacturer to write the unique number before shipping the product. Instead of assigning unique numbers to all RF tags produced, we will assign numbers only to good products that are shipped. It is now possible to assign unique numbers, and the unique numbers of products after shipment will no longer be consecutive. This makes it easier to manage customers' accounts after products are shipped.

[0414] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0415] (Embodiment 6) In this embodiment, a CPU including the storage device described in the previous embodiment will be described.

[0416] FIG. 45 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 1 is a block diagram showing a configuration of an example.

[0417] <cpu> The CPU shown in FIG. 45 includes an ALU 1191 (ALU: Arithmetic logic unit) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction A timing decoder 1193, an interrupt controller 1194, and a timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on a separate chip. The CPU shown in Figure 45 is merely an example showing a simplified configuration. There are many different configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 45 A configuration including the above is considered as one core, and multiple such cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is as follows: For example, it can be 8-bit, 16-bit, 32-bit, 64-bit, etc.

[0418] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, the interface Rupture Controller 1194, Register Controller 1197, Timing Controller Entered into 1195.

[0419] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are processed according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes to register 1196 according to the CPU state.

[0420] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0421] In the CPU shown in FIG. 45, a register 1196 is provided with a memory cell. The transistors described in any of the embodiments 1 to 3 can be used as the memory cells of the 1196. can.

[0422] In the CPU shown in FIG. 45, the register controller 1197 receives the According to the instruction, the holding operation is selected in the register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, a power supply voltage is applied to the memory cells in the register 1196. If data retention is selected in the capacitive element, rewriting data to the capacitive element This allows the supply of the power supply voltage to the memory cells in the register 1196 to be stopped. .

[0423] <Recording circuit> FIG. 46 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. The semiconductor device may further include other elements such as a capacitor.

[0424] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to the first gate of the transistor 1209 via a load such as a resistor. The configuration is such that the terminal block is grounded.

[0425] The switch 1203 uses a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured as a transistor of the opposite conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The transistor 1213 corresponds to one of the source and drain electrodes of the switch 120. The second terminal of the third terminal corresponds to the other of the source electrode and the drain electrode of the transistor 1213. The first switch 1203 is turned on by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the first terminal and the second terminal (i.e., the on-state of the transistor 1213) The first terminal of the switch 1204 is connected to the transistor 121. 4, and the second terminal of the switch 1204 corresponds to one of the source and drain electrodes of the transistor 1202. The switch 1204 corresponds to the other of the source and drain electrodes of the transistor 1214. A control signal RD input to the gate of the resistor 1214 controls the first and second terminals The conduction or non-conduction between the two (i.e., the on or off state of the transistor 1214) is selected. It is selected.

[0426] One of the source electrode and the drain electrode of the transistor 1209 is connected to a pair of The transistor 1210 is electrically connected to one of the electrodes and the gate of the transistor 1210. The connection point is a node M2. The other side is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line), The other terminal is connected to the first terminal of the switch 1203 (the source electrode and drain electrode of the transistor 1213). The second terminal of the switch 1203 (one of the electrodes of the transistor 12 The other of the source electrode and drain electrode of 13) is connected to a first terminal of the switch 1204 (transistor The switch 120 is electrically connected to the source electrode or the drain electrode of the transistor 1214. The second terminal of the transistor 1214 (the other of the source and drain electrodes of the transistor 1214) is connected to a power supply potential The second terminal of the switch 1203 is electrically connected to a wiring that can supply VDD. (the other of the source electrode and drain electrode of the transistor 1213) and A first terminal (one of the source electrode and the drain electrode of the transistor 1214) and a logic element 1 The input terminal of the capacitor 1206 is electrically connected to one of a pair of electrodes of the capacitor 1207. Here, the connection point is a node M1. For example, a low power supply potential (GND, etc.) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitance element 120. The other of the pair of electrodes 7 is connected to a wiring capable of supplying a low power supply potential (e.g., GND The other of the pair of electrodes of the capacitor 1208 is electrically connected to a For example, a low power supply potential (GND, etc.) or a high power supply potential can be input. A voltage (such as VDD) can be input to the pair of electrodes of the capacitor 1208. The other one is electrically connected to a wiring that can supply a low power supply potential (for example, a GND line). To be continued.

[0427] The capacitors 1207 and 1208 are used to reduce parasitic capacitance of transistors and wirings. It is possible to omit it by making active use of it.

[0428] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the There is no continuity between the two terminals.

[0429] In addition, in the transistor 1209 in FIG. 46, the second gate (second gate electrode: back The first gate is connected to a control signal WE, and the second gate is connected to a control signal WE. A control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, a ground potential GND or the solenoid potential of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the potential of the source electrode. This is a potential signal for controlling the threshold voltage of the transistor 1209. The gate voltage VG is 0V. In addition, the control signal WE2 has the same current as the control signal WE. The transistor 1209 may be a transistor that does not have a second gate. A transistor may also be used.

[0430] The other of the source electrode and the drain electrode of the transistor 1209 is connected to a In FIG. 46, the signal output from the circuit 1201 is In this example, the signal is input to the other of the source electrode and the drain electrode of the transistor 1209. The second terminal of the transistor 1203 (the other of the source electrode and drain electrode of the transistor 1213) The signal output from the logic element 1206 is an inverted signal whose logical value is inverted by the logic element 1206. This is input to the circuit 1201 via the circuit 1220.

[0431] In FIG. 46, the second terminal of the switch 1203 (the source electrode of the transistor 1213) The signal output from the drain electrode (the other of the drain electrodes) controls the logic element 1206 and the circuit 1220. However, the present invention is not limited to this example. The signal output from terminal 2 (the other of the source electrode and drain electrode of transistor 1213) The signal may be input to the circuit 1201 without having its logic value inverted. A node in which a signal with the logical value of the signal input from the input terminal is inverted is held in the circuit 1201. When a diode is present, the second terminal of the switch 1203 (the source voltage of the transistor 1213) A signal output from one of the gate electrodes (the drain electrode and the other of the gate electrodes) can be input to the node.

[0432] In addition, in FIG. 46, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. 0. For example, a silicon layer or The transistor may have a channel formed in a silicon substrate. All the transistors used in 1200 are transistors whose channels are formed in an oxide semiconductor layer. Alternatively, the memory element 1200 may include any other element other than the transistor 1209. The other transistors may include a transistor in which a channel is formed using an oxide semiconductor layer. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be a transistor that is connected to the gate of the transistor.

[0433] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0434] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0435] Further, a transistor in which a channel is formed in an oxide semiconductor layer has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is The off-state current is significantly lower than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 1 Even when the power supply voltage is not supplied to 200, the signal held in the capacitance element 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents (data) even when the supply of the power supply voltage is stopped. It is possible to hold the data.

[0436] In addition, by providing the switches 1203 and 1204, the precharge operation Since the circuit 1201 is a memory element that performs the above-mentioned operation after the power supply voltage is restarted, This shortens the time it takes to restore the original data.

[0437] In the circuit 1202, the signal held by the capacitor 1208 is The power supply voltage to the memory element 1200 is then restarted. After that, the signal held by the capacitance element 1208 is converted into the state of the transistor 1210 ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal can be read out accurately.

[0438] Such a memory element 1200 may be a register or a cache memory of a processor. By using it in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, Since the power supply can be stopped for a short period of time in multiple logic circuits, power consumption can be reduced. It can be suppressed.

[0439] In this embodiment, the memory element 1200 is used as a CPU. The 200 is equipped with a DSP (Digital Signal Processor), custom L SI, PLD (Programmable Logic Device) and other LSIs, R It can also be applied to F (Radio Frequency) tags.

[0440] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0441] (Embodiment 7) In this embodiment, a structural example of a display device using a transistor according to one embodiment of the present invention will be described. explain.

[0442] <Display device circuit configuration example> FIG. 47A is a top view of a display device according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display device of one embodiment will be described. FIG 47C is a circuit diagram showing a pixel of a display device according to one embodiment of the present invention. FIG. 1 is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied. .

[0443] The transistor disposed in the pixel portion can be formed according to any one of the first to third embodiments. In addition, since the transistor can be easily made into an n-channel type, the driver circuit can be made of n-channel A part of the driver circuit that can be configured with a channel transistor is connected to the transistor of the pixel portion. In this manner, the transistor shown in the above embodiment is formed in the pixel portion and the driver circuit. By using the photodiode, a highly reliable display device can be provided.

[0444] An example of a top view of an active matrix display device is shown in FIG. On the display 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 70 3, a signal line driver circuit 704. A plurality of signal lines are connected to the pixel portion 701. 704, and a plurality of scanning lines are connected to the first scanning line driving circuit 702 and the second scanning line driving circuit 703. The scanning line driving circuit 703 is extended from the scanning line driving circuit 703. In each of the display devices, pixels each having a display element are arranged in a matrix. The substrate 700 is a connection part for FPC (Flexible Printed Circuit) etc. It is connected to a timing control circuit (also called a controller or control IC) via

[0445] In FIG. 47A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal line The driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. The number of components, such as the drive circuits, that are required can be reduced, leading to cost reduction. If a driver circuit is provided outside the 00, the wiring must be extended, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve the reliability or the yield. Any one of the circuit 702, the second scanning line driver circuit 703, and the signal line driver circuit 704 is connected to the substrate 70. 0 or provided outside the substrate 700.

[0446] <Liquid crystal display device> An example of the circuit configuration of a pixel is shown in FIG. 47(B). 4 shows a pixel circuit that can be applied to a pixel of a display device.

[0447] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of a multi-domain pixel to be The signals applied to the electrode layers can be controlled independently.

[0448] The scan line 712 of the transistor 716 and the scan line 713 of the transistor 717 have different On the other hand, the signal line 714 is separated so that a gate signal can be applied. The transistor 716 and the transistor 717 share the same The transistor 717 can be any of the transistors described in any of the embodiments 1 to 3. This makes it possible to provide a highly reliable liquid crystal display device.

[0449] In addition, the first pixel electrode layer is electrically connected to the transistor 716. The second pixel electrode layer is electrically connected to the first pixel electrode layer 17. The first pixel electrode layer and the second pixel electrode layer are separated from each other. For example, the first pixel electrode layer may be V-shaped.

[0450] The gate electrode of the transistor 716 is connected to the scanning line 712, and the gate The gate electrode is connected to a scanning line 713. Different gate signals are applied to the scanning lines 712 and 713. By applying a signal to the transistor 716 and the transistor 717, the operation timing is made different. The orientation of the molecule can be controlled.

[0451] In addition, the capacitance wiring 710, the gate insulating layer functioning as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0452] In the multi-domain design, one pixel has a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0453] Note that the pixel circuit shown in FIG. 47(B) is not limited to this. The pixel circuit is newly equipped with switches, resistors, capacitors, transistors, sensors, or logic Circuits etc. may be added.

[0454] 48(A) and 48(B) are an example of a top view and a cross-sectional view of a liquid crystal display device. In FIG. 48A, a display device 20, a display area 21, a peripheral circuit 22, and an FPC (flexible printed circuit board). A representative configuration having a flexible printed circuit board 42 is shown.

[0455] FIG. 48(B) shows cross-sectional views of broken lines A-A', B-B', and C-C' in FIG. 48(A). Between A-A' is the peripheral circuit section, between B-B' is the display area, and between C-C' is the FPC and The connection part is shown.

[0456] In addition to the transistor 11, the display device 20 includes a conductive layer 190, a conductive layer 195, an insulating layer 420, A liquid crystal layer 490, a liquid crystal element 80, a capacitance element 60, an insulating layer 430, a spacer 440, and a colored layer 4 60, adhesive layer 470, conductive layer 480, light shielding layer 418, substrate 400, adhesive layer 473, adhesive layer 474, adhesive layer 475, adhesive layer 476, polarizing plate 103, polarizing plate 403, protective substrate 105, A protective substrate 402 has an anisotropic conductive layer 510 .

[0457] <Organic EL display device> Another example of the circuit configuration of a pixel is shown in FIG. 47(C). 3 shows the pixel structure of the device.

[0458] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, which When the excited state of the electron returns to the ground state, light is emitted. The element is called a current-excited light-emitting element.

[0459] FIG. 47C is a diagram showing an example of an applicable pixel circuit. This example shows how two transistors are used in one pixel. The pixel circuit is a digital time scale. A tonal drive can be applied.

[0460] Regarding the configuration of an applicable pixel circuit and the operation of pixels when digital time gray scale driving is applied, I will explain it below.

[0461] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light-emitting element The switching transistor 721 has a gate electrode 724 and a capacitor element 723. The gate electrode layer is connected to the scanning line 726, and the first electrode (the source electrode layer and the drain electrode layer) One of the electrodes (the source electrode layer and the drain electrode layer) is connected to a signal line 725, and the second electrode (the other of the source electrode layer and the drain electrode layer) is connected to a signal line 725. ) is connected to the gate electrode layer of the driving transistor 722. In the semiconductor device 22, the gate electrode layer is connected to a power supply line 727 through a capacitor element 723, and the first electrode is The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light emitting element 724 corresponds to a common electrode 728. It is electrically connected to a common potential line formed on the substrate.

[0462] The switching transistor 721 and the driving transistor 722 are the same as those in the first embodiment. The transistors described in the sections 1 to 3 can be appropriately used. An EL display device can be provided.

[0463] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, for example, GND , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and must be at least the forward threshold. Includes low-value voltages.

[0464] The capacitance element 723 can be omitted by substituting the gate capacitance of the driving transistor 722. It can be omitted.

[0465] Next, a signal input to the driving transistor 722 will be described. In this case, the driving transistor 722 is in two states: fully on or fully off. A video signal such as the above is input to the driving transistor 722. In order to operate the driving transistor 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the driving transistor 722. A signal line 725 is connected to the gate electrode layer of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the input transistor 722 is applied.

[0466] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 72 A voltage equal to or greater than the forward voltage of the driving transistor 722 plus the threshold voltage Vth of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in the saturation region. A current flows through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is applied to the light emitting element 724. It is possible to perform analog gray scale driving.

[0467] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. A switch, a resistor, a capacitor, a sensor, a transistor or a logic A logic circuit or the like may be added.

[0468] When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like. A potential lower than that applied to the source electrode is applied to the second gate electrode through a wiring (not shown). It is sufficient to have a configuration in which the potentials exemplified above can be input, for example by applying a potential.

[0469] 49(A) and 49(B) are a top view and a cross-sectional view of an example of a light-emitting device. In FIG. 49A, a light emitting device 24, a display area 21, a peripheral circuit 22, and an FPC (flexible printed circuit board). A representative configuration having a flexible printed circuit board (42) is shown.

[0470] FIG. 49(B) shows cross-sectional views of the dashed lines A-A', B-B', and C-C' in FIG. 49(A). Between A-A' is the peripheral circuit section, between B-B' is the display area, and between C-C' is the FPC and The connection part is shown.

[0471] The light emitting device 24 includes a transistor 11, a conductive layer 190, a conductive layer 195, a conductive layer 410, Optical adjustment layer 530, EL layer 450, light emitting element 70, capacitance element 60, spacer 440, coloring layer 460, adhesive layer 470, conductive layer 480, light-shielding layer 418, substrate 400, anisotropic conductive layer 51 0.

[0472] For example, in this specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element, or the light-emitting device may include, for example, For example, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) etc.), transistors (transistors that emit light according to electric current), electron-emitting devices, liquid crystal devices , electronic ink, electrophoretic element, grating light valve (GLV), plasma display Display (PDP), MEMS (Micro Electro Mechanical Systems), Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), M IRASOL(R), IMOD (Interference Modulation) Element , electrowetting element, piezoelectric ceramic display, carbon nanotube In addition to these, the device has at least one electric or magnetic display element. The display medium has contrast, brightness, reflectance, transmittance, etc. that change due to electrochemical effects. An example of a display device using an EL element is an EL display. An example of a display device using electron-emitting elements is a field emission display ( FED) or SED type flat panel display (SED: Surface-conductive Liquid crystal elements An example of a display device using the liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, LCD display, reflective LCD display, direct-view LCD display, projection LCD display Examples of display devices using electronic ink or electrophoretic elements include Examples include electronic paper.

[0473] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0474] (Embodiment 8) In this embodiment, a display module to which a semiconductor device of one embodiment of the present invention is applied will be described with reference to FIG. The explanation will be given using 50.

[0475] <Display module> The display module 6000 shown in FIG. 50 is made up of an upper cover 6001 and a lower cover 6002. In between, touch panel 6004 connected to FPC 6003 and touch panel 6005 connected to FPC 6005 Display panel 6006, backlight unit 6007, frame 6009, printed circuit board 6010 and a battery 6011. In some cases, the read / write head 6011, the touch panel 6004, etc. may not be provided.

[0476] The semiconductor device of one embodiment of the present invention is, for example, a display panel 6006 or a printed circuit board. The present invention can be used in integrated circuits implemented in a semiconductor device.

[0477] The upper cover 6001 and the lower cover 6002 are connected to the touch panel 6004 and the display panel. The shape and dimensions can be changed appropriately to match the size of the cable 6006.

[0478] The touch panel 6004 is a resistive or capacitive touch panel. 6006. In addition, the opposing substrate (sealing substrate) of the display panel 6006 It is also possible to provide the display panel 6 with a touch panel function. It is also possible to add an optical sensor to each pixel of the 006 to add an optical touch panel function. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 6006, and a capacitance method is used. It is also possible to add a touch panel function.

[0479] The backlight unit 6007 includes a light source 6008. It may be provided at the end of the unit 6007 and may be configured to use a light diffusion plate.

[0480] The frame 6009 has a function of protecting the display panel 6006 and also a function of preventing heat generation from the printed circuit board 6010. The frame 600 also functions as an electromagnetic shield to block electromagnetic waves generated by the 9 may also function as a heat sink.

[0481] The printed circuit board 6010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, a battery 6011 may be provided separately. In this case, the battery 6011 can be omitted.

[0482] In addition, the display module 6000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0483] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0484] (Embodiment 9) In this embodiment, an example of use of a semiconductor device according to one embodiment of the present invention will be described.

[0485] <Package using lead frame type interposer> Figure 51(A) shows the cross-sectional structure of a package using a lead frame type interposer. The package shown in FIG. 51(A) is a perspective view of a semiconductor device according to one embodiment of the present invention. A corresponding chip 2751 is attached to the interposer 2750 by wire bonding. The terminal 2752 is connected to the chip 27 of the interposer 2750. 51 is mounted on the surface. The chip 2751 is then molded in resin. 2753, but the sealing is performed with a part of each terminal 2752 exposed. Make sure that it is done.

[0486] The module configuration of an electronic device (mobile phone) in which a package is mounted on a circuit board is shown in Fig. The mobile phone module shown in FIG. 51(B) includes a printed wiring board 28 28. The display device 2801 includes a package 2802 and a battery 2804. A printed wiring board 2801 is connected to a panel 2800 having a child by an FPC 2803. It has been implemented.

[0487] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0488] (Embodiment 10) In this embodiment, electronic devices and lighting devices according to one embodiment of the present invention will be described with reference to drawings. do.

[0489] <Electronic equipment> Using the semiconductor device of one embodiment of the present invention, an electronic device or a lighting device can be manufactured. By using the semiconductor device of one embodiment of the present invention, highly reliable electronic devices and lighting devices can be manufactured. The semiconductor device according to one embodiment of the present invention is used in an electronic device or a lighting device in which the detection sensitivity of a touch sensor is improved. You can create devices.

[0490] The electronic device may be, for example, a television device (also called a television or television receiver). (c) Computer monitors, digital cameras, digital video cameras and other cameras , digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable games Examples include gaming machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. .

[0491] In addition, when the electronic device or lighting device of one embodiment of the present invention is flexible, it can be attached to the inner wall of a house or a building. Or it can be installed along the curved surface of an exterior wall or the interior or exterior of a car. do.

[0492] Further, the electronic device of one embodiment of the present invention may include a secondary battery and may be configured to use non-contact power transmission. It is preferable that the secondary battery can be charged.

[0493] As the secondary battery, for example, a lithium polymer battery (lithium ion battery) using a gel electrolyte is used. Lithium-ion secondary batteries such as lithium-ion polymer batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic These include nickel-zinc batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries. .

[0494] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. If present, the antenna may be used for contactless power transfer.

[0495] FIG. 52A shows a portable game machine. The portable game machine includes a housing 7101, a housing 7102, a display portion 7103, Display unit 7104, microphone 7105, speaker 7106, operation keys 7107, stylus The semiconductor device according to one embodiment of the present invention is built in the housing 7101. The display portion 7103 or the display portion 7104 can be used for an integrated circuit, a CPU, etc. By using a display device according to one embodiment of the present invention, the user experience is excellent and deterioration of quality is prevented. It is possible to provide a portable game machine in which the above-mentioned problem is unlikely to occur. The portable game machine has two display units 7103 and 7104. The number of display units that the device has is not limited to this.

[0496] FIG. 52B shows a smart watch. The smart watch includes a housing 7302, a display unit 7304, and operation buttons. 7311, 7312, a connection terminal 7313, a band 7321, a clasp 7322, etc. The semiconductor device according to one embodiment of the present invention includes a memory, a CPU, and the like built in the housing 7302. can be used.

[0497] FIG. 52C shows a portable information terminal. In addition to a display portion 7502 incorporated in a housing 7501, , operation button 7503, external connection port 7504, speaker 7505, microphone 7506 The semiconductor device according to one embodiment of the present invention is built in a housing 7501. The display unit 7502 can be used for a mobile memory, a CPU, and the like. It can be made to be high definition, so it can be used in full HD, 4k, or 8K despite being small to medium sized. k, and a variety of other displays can be performed, resulting in extremely clear images.

[0498] FIG. 52D shows a video camera, which includes a first housing 7701, a second housing 7702, and a display unit 77 03, operation keys 7704, a lens 7705, a connection part 7706, etc. 4 and a lens 7705 are provided in a first housing 7701, and a display unit 7703 is provided in a second housing. The first housing 7701 and the second housing 7702 are connected to each other. The first housing 7701 and the second housing 7702 are connected by a connector 7706. The angle between the first housing 7701 and the second housing 7702 is The connection portion 7706 can change the image on the display portion 7703. 6, the switch is configured according to the angle between the first housing 7701 and the second housing 7702. The imaging device of one embodiment of the present invention may be provided at the focal position of the lens 7705. In the semiconductor device according to one embodiment of the present invention, the semiconductor device is integrated in the first housing 7701. It can be used in integrated circuits, CPUs, etc.

[0499] FIG. 52E shows a digital signage. The display unit 7922 is installed on a utility pole 7921. The semiconductor device according to one embodiment of the present invention is used for a control circuit of the display portion 7922. It is possible.

[0500] FIG. 53A shows a notebook personal computer, which includes a housing 8121 and a display unit 8122. , a keyboard 8123, a pointing device 8124, etc. Such a semiconductor device can be applied to a CPU or a memory built in the housing 8121. Since the display portion 8122 can have a very high resolution, it can be used in small and medium-sized devices. It is possible to display 8K images while using a smartphone, resulting in extremely clear images.

[0501] FIG. 53(B) shows the exterior of the automobile 9700. FIG. 53(C) shows the driver's seat of the automobile 9700. The automobile 9700 includes a body 9701, wheels 9702, a dashboard 9703, and a lighter. The semiconductor device of one embodiment of the present invention includes a display portion of the automobile 9700 and For example, the display portion 9710 shown in FIG. The display device or the semiconductor device of one embodiment of the present invention can be provided in the display portion 9715. do.

[0502] The display portion 9710 and the display portion 9711 are a display device provided on a windshield of an automobile, The display device or the input / output device according to one embodiment of the present invention is a display device or By forming the electrodes of the input / output device from a light-transmitting conductive material, The device is a so-called see-through display device or input / output device that allows the opposite side to be seen through. If it is a see-through display device or an input / output device, the operation of the car 9700 can be Therefore, the display device or input / output device according to one embodiment of the present invention can be used without obstructing the view even when the display device is turned on. The display device can be installed on the windshield of the automobile 9700. A display device or an input / output device is provided with transistors for driving the display device or the input / output device. In this case, organic transistors using organic semiconductor materials and transistors using oxide semiconductors are used. For example, a light-transmitting transistor such as a transistor having a light-transmitting property may be used.

[0503] The display unit 9712 is a display device provided on a pillar part. By displaying an image from the imaging means on the display unit 9712, the view blocked by the pillars can be compensated for. The display unit 9713 is a display device provided in the dashboard. For example, an image captured by an imaging means provided on the vehicle body is displayed on the display unit 9713. This can complement the view obstructed by the dashboard. By projecting images from a fixed imaging device, blind spots can be filled and safety can be improved. In addition, by projecting an image that complements the invisible parts, it is possible to create a more natural and unnatural appearance. Safety checks can be carried out quickly.

[0504] FIG. 53(D) shows the interior of a car with bench seats for the driver and passenger. The display unit 9721 is a display device or an input / output device provided in the door section. For example, the driver can view the vehicle by displaying an image captured by an imaging means provided on the vehicle body on the display unit 9721. The display unit 9722 can complement the view blocked by the steering wheel. The display unit 9723 is a display device provided in the center of the seat surface of the bench seat. The display device is installed on the seat or backrest, and the display device is The heat generated by the display device can also be used as a seat heater.

[0505] The display unit 9714, the display unit 9715, or the display unit 9722 displays navigation information, odometer, tachometer, mileage, fuel level, gear status, air conditioning settings, etc. It is possible to provide various information. In addition, the display items and layout displayed on the display unit can be The above information can be displayed on the display unit 9. 710 to 9713, the display unit 9721, and the display unit 9723. In addition, the display units 9710 to 9715 and the display units 9721 to 9723 are illuminated. The display units 9710 to 9715 and the display unit The display portion 9721 to the display portion 9723 can also be used as a heating device.

[0506] 54(A) shows the external appearance of the camera 8000. The camera 8000 has a housing 8001. , a display unit 8002, an operation button 8003, a shutter button 8004, a connection unit 8005, etc. In addition, a lens 8006 can be attached to the camera 8000.

[0507] The coupling section 8005 has electrodes and is connected to the finder 8100 (to be described later) as well as a strobe device, etc. can be connected.

[0508] In this example, a camera 8000 is used, and a lens 8006 is removed from a housing 8001 and replaced. However, the lens 8006 and the housing 8001 may be integrated together.

[0509] An image can be captured by pressing the shutter button 8004. The display unit 8002 has a function as a touch panel, and an image is captured by touching the display unit 8002. It is also possible.

[0510] The display device or semiconductor device of one embodiment of the present invention can be applied to the display portion 8002. do.

[0511] FIG. 54(B) shows an example in which a finder 8100 is attached to a camera 8000. is.

[0512] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0513] The housing 8101 has a coupling portion that engages with the coupling portion 8005 of the camera 8000. The finder 8100 can be attached to the camera 8000. The display unit 8102 displays images received from the camera 8000 via the electrodes. It can be done.

[0514] The button 8103 functions as a power button. The display of 102 can be switched on and off.

[0515] The semiconductor device of one embodiment of the present invention is applied to an integrated circuit and an image sensor in a housing 8101. It can be used.

[0516] In addition, in FIG. 54(A) and (B), the camera 8000 and the finder 8100 are separate electronic devices. The camera 8000 is provided with a housing 8001 that is detachable. A finder having a display device or an input / output device according to an embodiment may be built in.

[0517] FIG. 54(C) shows the external appearance of the head mounted display 8200.

[0518] The head mounted display 8200 includes a mounting part 8201, a lens 8202, and a main body 820. 3, a display unit 8204, a cable 8205, etc. It has a built-in Teri 8206.

[0519] A cable 8205 supplies power from a battery 8206 to the main body 8203. The reference numeral 3 is provided with a wireless receiver and displays image information such as received image data on a display unit 8204. In addition, the movement of the user's eyeballs and eyelids can be recorded by a camera installed on the main body 8203. Capture it and calculate the coordinates of the user's perspective based on the information, so that the user's perspective can be input and used as a force means.

[0520] In addition, a plurality of electrodes may be provided at positions where the wearer is touched on the wearing part 8201. The main body 8203 may have a function of recognizing the user's perspective by detecting the current flowing through the electrodes as the user's eyeballs move. Further, by detecting the current flowing through the electrodes, it may also have a function of monitoring the user's pulse. In addition, the wearing part 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display part 8204. Further, the movement of the user's head etc. may be detected, and the video displayed on the display part 8204 may be changed according to the movement.

[0521] The semiconductor device according to one aspect of the present invention can be applied to the integrated circuit inside the main body 8203 .

[0522] Note that this embodiment can be appropriately combined with other embodiments shown in this specification .

[0523] (Embodiment 11) In this embodiment, a usage example of an RF tag using the semiconductor device according to one aspect of the present invention will be described with reference to FIG. 55.

[0524] <Usage Example of RF Tag> The applications of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, certificates documents (driver's licenses, resident cards, etc., see FIG. 55(A)), vehicles (bicycles, etc., FIG. 55(B) See Figure 55(C), packaging containers (wrapping paper, bottles, etc., see Figure 55(C)), recording media (DVDs and videos Deotape, etc. (see Figure 55(D)), personal belongings (bags, glasses, etc.), food, plants, animals objects, human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices (liquid crystal display devices , EL display devices, television devices, or mobile phones) or It can be attached to luggage tags (see Figures 55(E) and 55(F)) and used.

[0525] The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of an object. For example, in a book, the sensor is embedded in the paper, and in a package made of organic resin, the sensor is embedded in the paper. For example, the RF tag is embedded in the organic resin and fixed to each article. The 4000 is small, thin, and lightweight, and even after it is attached to an object, it does not change the design of the object. In addition, the security of banknotes, coins, securities, bearer bonds, or certificates is not lost. By providing an RF tag 4000 according to one aspect of the present invention to a product or the like, an authentication function can be provided. This authentication function can be used to prevent counterfeiting. The present invention can be applied to various items, such as items of clothing, recording media, personal belongings, food, clothing, household goods, and electronic devices. By attaching RF tags related to the above, the efficiency of systems such as inspection systems can be improved. In addition, even in the case of vehicles, the RF tag according to one embodiment of the present invention can be attached. This can improve security against theft and the like.

[0526] As described above, an RF tag using a semiconductor device according to one embodiment of the present invention is By using these for each of the above applications, it is possible to reduce the power consumption during operation, including writing and reading information. Therefore, it is possible to extend the maximum communication distance. Since the data can be stored for an extremely long period of time, it is also suitable for applications where writing and reading are performed infrequently. It can be suitably used.

[0527] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0528] 10. Transistor 11 Transistor 12 Transistor 20 Display device 21 Display area 22 Peripheral circuits 24 Light emitting device 60 Capacitive element 70 Light emitting element 80 Liquid crystal element 100 Substrates 103 Polarizing plate 105 Protection Board 110 Insulating layer 120 Semiconductor layer 121 Insulators 121a Insulating film 122 Semiconductor layer 122a Semiconductor film 123 Insulator 123a Insulating film 130 Source electrode layer 130a Conductive film 130b Conductive layer 140 Drain electrode layer 150 Gate insulation layer 150a Insulating film 160 Gate electrode layer 160a Conductive film 165 Conductive Layer 166 Conductive Layer 167 Conductive Layer 170 Insulating layer 170a Insulating film 171 Mixed layer 171b Insulating layer 172 Oxygen 173 Insulating Layer 173a Insulating film 174 Groove 175 Insulating Layer 175a Insulating film 175b Insulating layer 176 Resist Mask 177 Insulating Layer 177a Insulating film 190 Conductive Layer 195 Conductive Layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel section 211 pixels 212 subpixels 212B subpixel 212G subpixel 212R subpixel 220 Photoelectric conversion element 230 Pixel Circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 light 257 Wiring 260 Peripheral Circuits 270 Peripheral Circuits 280 Peripheral Circuits 290 Peripheral Circuits 291 Light source 300 Silicon substrate 310 layers 320 layers 330 layers 340 layers 351 Transistor 352 Transistor 353 Transistor 360 Photodiode 361 Anode 362 Cathode 363 Low resistance region 365 Photodiode 366 Semiconductor Layer 367 Semiconductor Layer 368 Semiconductor Layer 370 Plug 371 Wiring 372 Wiring 373 Wiring 374 Wiring 400 Substrates 402 Protection Board 403 Polarizing Plate 410 Conductive layer 418 Light blocking layer 420 Insulating layer 430 Insulating layer 440 Spacer 450 EL layer 460 Colored layer 470 Adhesive layer 473 Adhesive layer 474 Adhesive layer 475 Adhesive layer 476 Adhesive layer 480 Conductive Layer 490 Liquid crystal layer 510 Anisotropic conductive layer 530 Optical adjustment layer 601 Precursor 602 Precursor 700 Substrates 701 Pixel section 702 Scanning line driver circuit 703 Scanning line driver circuit 704 Signal Line Driver Circuit 710 Capacitance wiring 712 scan lines 713 scan lines 714 Signal Line 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 pixels 721 Switching Transistors 722 Driving Transistor 723 Capacitive element 724 Light emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 1700 Substrate to be coated 1701 Chamber 1702 Road Room 1703 Pre-treatment room 1704 Chamber 1705 Chamber 1706 Unloading Room 1711a Raw material supply section 1711b Raw material supply section 1712a High Speed ​​Valve 1712b High Speed ​​Valve 1713a Raw material inlet 1713b Raw material inlet 1714 Raw material discharge port 1715 Exhaust system 1716 PCB Holder 1720 Delivery Room 2100 Transistor 2200 Transistor 2201 Insulators 2202 Wiring 2203 Plug 2204 Insulators 2205 Wiring 2207 Insulators 2211 Semiconductor substrate 2212 Insulators 2213 Gate electrode 2214 Gate insulator 2215 Source and drain regions 2750 Interposer 2751 chips 2752 Terminal 2753 Molding resin 2800 Panel 2801 Printed wiring board 2802 Package 2803 FPC 2804 Battery 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 4000 RF tags 5100 pellets 5120 PCB 5161 area 6000 Display Module 6001 Top cover 6002 Lower cover 6003 FPC 6004 Touch Panel 6005 FPC 6006 Display Panel 6007 Backlight unit 6008 Light source 6009 Frame 6010 Printed Circuit Board 6011 Battery 7101 Case 7102 Case 7103 Display section 7104 Display section 7105 Microphone 7106 Speaker 7107 Operation key 7108 Stylus 7302 Case 7304 Display section 7311 Operation button 7312 Operation button 7313 Connection terminal 7321 Band 7322 Clasp 7501 Case 7502 Display section 7503 Operation button 7504 External connection port 7505 Speaker 7506 Microphone 7701 Case 7702 Case 7703 Display section 7704 Operation key 7705 Lens 7706 Connection 7921 Electric pole 7922 Display section 8000 Camera 8001 Case 8002 Display section 8003 Operation button 8004 Shutter button 8005 Joint 8006 Lens 8100 Finder 8101 Case 8102 Display section 8103 Button 8121 Case 8122 Display section 8123 Keyboard 8124 Pointing Device 8200 Head Mounted Display 8201 Mounting part 8202 Lens 8203 Main unit 8204 Display section 8205 Cable 8206 Battery 9700 Automobiles 9701 Body 9702 wheels 9703 Dashboard 9704 Light 9710 Display section 9711 Display section 9712 Display section 9713 Display section 9714 Display section 9715 Display section 9721 Display section 9722 Display section 9723 Display section< / cpu>

Claims

[Claim 1] A first insulating layer; an oxide semiconductor layer having a region above the first insulating layer and having a channel formation region; a first conductive layer having a region above the oxide semiconductor layer and functioning as a source electrode; a second conductive layer having a region above the oxide semiconductor layer and functioning as a drain electrode; a second insulating layer having a region in contact with a side surface of the first insulating layer and a region in contact with a side surface of the oxide semiconductor layer; a third insulating layer having a region above the first conductive layer and a region above the second conductive layer, the third insulating layer having a groove; a fourth insulating layer having an area above the third insulating layer and having a groove; a fifth insulating layer having a region that functions as a gate insulating layer formed along an inner wall of the groove; a third conductive layer having a region that is in contact with the fifth insulating layer inside the groove and that functions as a gate electrode; an inner wall of the groove is aligned with a side surface of the first conductive layer and a side surface of the second conductive layer; A semiconductor device, wherein an upper surface of the second insulating layer, an upper surface of the fourth insulating layer, an upper surface of the fifth insulating layer, and an upper surface of the third conductive layer are on the same plane.

Images