Grasping Pose Determination for Objects in Clutter

Abstract

To provide improved grasp determination methods.SOLUTION: Apparatuses, systems, and techniques provided herein determine a set of grasp poses that would allow a robot to successfully grasp an object proximate to at least one additional object. In at least one embodiment, the set of grasp poses is modified based on determination that at least one of the grasp poses in the set of grasp poses would interfere with at least one additional object proximate to the object.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 934,946, filed November 13, 2019, entitled "6-DOF GRASPING FOR TARGET-DRIVE OBJECT MANIPULATION IN CLUTTER," the entire contents of which are incorporated herein by reference.

[0002] FIELD OF THE INVENTION

[0002] Embodiments described herein generally relate to the field of robotic control. In at least one embodiment, a grasp decision is made for an object associated with a group of objects proximate to the object, such as an object within a clutter of objects. In at least one embodiment, a robot may use the grasp decision to manipulate the object associated with the group of objects proximate to the object. [Background technology]

[0003] Robotic automation, at least in one implementation, is an important field that enables improved productivity, safety, and economy when performing tasks. For robots that manipulate objects, generating a grasp pose is often a critical component of the task. In one example, a robot observes an object and determines where its gripper should be positioned (3D position and orientation, also called pose) so that the robot can pick up the object. The stability of an individual grasp can depend on the shape of the object and gripper, the object's mass distribution, and surface friction. The shape around the object can impose further constraints by limiting the grasp points that a robotic manipulator can reach in a scene without colliding with other objects. In some examples, this issue is addressed by shape-inspired heuristics for selecting promising grasp points around the object, sometimes followed by a more detailed shape analysis of the stability and reachability of sampled grasps. Many of these approaches rely on the availability of a complete 3D model of the object, which can be a severe limitation in realistic scenarios, for example, when a robot only observes a scene through a noisy camera. Thus, there is a need for improved methods of grasp determination, particularly when a target object is associated with other objects in proximity to the target object in various implementations. [Brief explanation of the drawings]

[0004] [Figure 1] 1A-1C illustrate examples of a robotic system for grasping various objects, according to one embodiment. [Figure 2] FIG. 1 illustrates an example of an object that can be grasped by a robotic system, according to one embodiment. [Figure 3] FIG. 10 illustrates an example of a binary mask containing image data of a graspable object, according to one embodiment. [Figure 4] FIG. 1 illustrates a point cloud generated from image data of a graspable object, according to one embodiment. [Figure 5]FIG. 1 illustrates a cropped point cloud generated from image data of a graspable object, according to one embodiment. [Figure 6] FIG. 1 illustrates a point cloud of a detached object generated from image data of a graspable object, according to one embodiment. [Figure 7] FIG. 10 illustrates a set of grasps and a point cloud for a detached object, with point clouds for other objects combined with the detached object point cloud, according to one embodiment. [Figure 8] 1 is a table summarizing results according to one embodiment. [Figure 9] FIG. 10 illustrates an example process for generating a set of grip poses, according to one embodiment. [Figure 10A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 10B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 11] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 12] FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 13A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 13B] 13B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 13A, according to at least one embodiment. [Figure 13C] FIG. 13B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 13A, according to at least one embodiment. [Figure 13D] FIG. 13B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 13A, according to at least one embodiment. [Figure 14] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 15] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 16] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 18A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 18B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 18C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 18D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 18E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 18F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 19] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 20A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 20B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 21A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 21B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 22] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 23A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 23B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 23C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 23D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 24] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 25] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 26] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 27] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 28] FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor, according to at least one embodiment. [Figure 29] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 30] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 31] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 32] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment. [Figure 33] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 34A] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 34B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 35]FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 36] FIG. 1 illustrates a general purpose processing cluster (“GPC”), according to at least one embodiment. [Figure 37] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 38] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. [Figure 39] FIG. 1 is an example data flow diagram for an advanced computing pipeline, according to at least one embodiment. [Figure 40] FIG. 1 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment. [Figure 41] A diagram including an example of an advanced computing pipeline 4010A for processing imaging data, according to at least one embodiment. [Figure 42A] FIG. 10 is a diagram including an example data flow of a virtual instrument supporting an ultrasound device, according to at least one embodiment. [Figure 42B] FIG. 10 is a diagram including an example data flow of a virtual instrument supporting a CT scanner, according to at least one embodiment. [Figure 43A] FIG. 1 is a data flow diagram of a process for training a machine learning model, according to at least one embodiment. [Figure 43B] FIG. 1 illustrates an example client-server architecture for extending annotation tools with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] Techniques are described for generating a set of grasps for an object among multiple objects (e.g., a clutter of objects). In at least one embodiment, the set of grasps includes grasps for the object, where the grasps in the set of grasps are determined to avoid interference with or contact with at least one object proximate the object when the robot executes the grasp.

[0006] In at least one embodiment, the technique provides a six-degree-of-freedom (6DOF) grasp for any target object in a cluttered scene from a partial point cloud observation, such as a variety of 3D point cloud observations. In various embodiments, the technique achieves a grasp success rate of at least 80.3%, outperforming a baseline approach by 17.6% while clearing nine cluttered scenes (containing a total of 23 unknown objects and 51 possible picks) on a robotic platform. In at least one embodiment, the technique can further infer effective grasp sequences for retrieving objects that are not directly accessible.

[0007] In at least one embodiment, image data of a plurality of objects, such as image data from a depth image, is acquired. The image data may include target objects to be grasped by the robot. In at least one embodiment, the depth image may include a binary mask. The binary mask may include sets of points, each set of points corresponding to at least one object among the plurality of objects. In at least one embodiment, the set of points in the binary mask represent an inner contour and an outer contour of one object among the plurality of objects. In at least one embodiment, the set of points in the binary mask represent at least an outer contour of a target object associated with the plurality of objects. Thus, in at least one embodiment, the binary mask may be used to separate each object among the plurality of objects. In at least one embodiment, the binary mask is used to identify the target object. For example, the binary mask may be used by a robot or a human to identify a target object for which a set of grasp poses is to be generated.

[0008] In at least one embodiment, a 3D point cloud is generated from image data of a plurality of objects. In at least one embodiment, the 3D point cloud is generated from a depth image including a binary mask. In at least one embodiment, the size of the 3D point cloud is reduced. For example, the 3D point cloud may be cropped to achieve the size reduction. In at least one embodiment, a bounding volume is used as a basis for reducing the size of the 3D point cloud. For example, the bounding volume may be applied to the 3D point cloud. In some implementations, image data outside the bounding volume is cropped from the 3D point cloud to generate a modified 3D point cloud. In some implementations, the bounding volume is a bounding box having a predetermined volume. In at least one embodiment, the 3D point cloud and the modified 3D point cloud include image data representing a target object. In some implementations, the 3D point cloud and the modified 3D point cloud include image data representing the target object and additional objects proximate to the target object.

[0009] In at least one embodiment, image data of the target object is disjointed from image data associated with other objects proximate the target object. In at least one embodiment, the disjointed image data of the target object is in a 3D point cloud or a rectified 3D point cloud. In at least one embodiment, disjointing the image data of the target object from image data associated with other objects proximate the target object results in a 3D point cloud generated from the 3D point cloud or the rectified 3D point cloud that is limited to the image data of the target object.

[0010] In at least one embodiment, a set of grip poses is generated for a target object. In at least one embodiment, the set of grip poses is generated using image data associated with the target object. In at least one embodiment, the image data associated with the target object is a three-dimensional point cloud. 3D point clouds may be limited to those that include image data associated with the target object. In at least one embodiment, the three-dimensional point cloud that includes image data of the target object is a modified three-dimensional point cloud based on a three-dimensional point cloud that includes image data of one or more other objects. In at least one embodiment, the other objects are within a collection of objects that includes the target object.

[0011] In at least one embodiment, the set of grasp poses includes one or more predicted grasps. In at least one embodiment, the one or more predicted grasps are generated based on image data processing and computer-aided simulation. In at least one embodiment, the one or more predicted grasps are generated by a robot. In at least one embodiment, the set of grasp poses for the target object is included in a three-dimensional point cloud. For example, the three-dimensional point cloud may include a set of grasp poses including successful grasp poses for the target object.

[0012] In at least one embodiment, image data of other objects proximate the target object is included in the three-dimensional point cloud. In some implementations, the three-dimensional point cloud including the image data of the other objects is combined with a three-dimensional point cloud including a set of grip poses including successful grip poses for the target object. In some implementations, the process of combining the three-dimensional point clouds generates a combined three-dimensional point cloud including the image data of the other objects and the set of grip poses including successful grip poses for the target object. In at least one embodiment, the combined three-dimensional point cloud is subjected to computer-assisted processing to identify one or more grip poses that, when performed by the robot, would interfere with or contact one or more of the other objects. In at least one embodiment, the identified one or more interfering grip poses are excluded from the set of grip poses including successful grip poses for the target object. In at least one embodiment, the three-dimensional point cloud including the set of grip poses including successful grip poses for the target object is modified to remove image data associated with the identified one or more interfering grip poses. In at least one embodiment, the modified set of grasp poses includes successful grasp poses for the target object based on image data of other objects proximate to the target object, In at least one embodiment, the modified set of grasp poses includes successful grasp poses that enable the robot to grasp the target object while avoiding other objects proximate to the target object.

[0013] In at least one embodiment, a combined 3D point cloud including image data of the other objects and a set of grip poses including successful grip poses for the target object is combined with a 3D point cloud including image data of the target object. The resulting 3D point cloud includes image data of the target object, image data of the other objects, and the set of grip poses including successful grip poses for the target object. In at least one embodiment, the combined 3D point cloud is subjected to computer-assisted processing to identify one or more grip poses that, when performed by the robot, would interfere with or contact one or more of the other objects. In at least one embodiment, the identified one or more interfering grip poses are removed from the set of grip poses including successful grip poses for the target object. In at least one embodiment, the 3D point cloud including the set of grip poses including successful grip poses for the target object is modified to remove image data associated with the identified one or more interfering grip poses. In at least one embodiment, the modified set of grip poses includes successful grip poses for the target object based on image data of the other objects proximate to the target object. In at least one embodiment, the modified set of grasping poses includes successful grasping poses that allow the robot to grasp the target object while avoiding other objects in the vicinity of the target object.

[0014] FIG. 1 illustrates a robotic system for grasping various objects, according to one embodiment. Grasp selection is a key issue in robotic manipulation. In at least one embodiment, a robot observes an object, and an associated control computer system determines where (3D position and 3D orientation) the robot's gripper should move to pick up the object. For example, FIG. 1 illustrates a robotic system for grasping various objects, according to one embodiment. In at least one embodiment, a robot 102 having a gripper 104 is controlled by a computer system that implements the techniques described herein. In at least one embodiment, the robot 102 can perform improved grasping on various objects, such as a cylinder 106, a box 108, or a bowl 110, even if the various objects are within a clutter of objects.

[0015] Grasp selection can be complex because grasp stability depends on the object and gripper geometry, the object's mass distribution, and surface friction. The geometry around an object can impose further constraints on which grasp points a robotic manipulator can reach in a scene without colliding with other objects.

[0016] Figure 2 shows an example of an object that can be grasped, according to one embodiment. In at least one embodiment, the object shown in Figure 2 is represented in an image, such as a depth image from a depth camera. In at least one embodiment, the image is an RGB-D image that includes image data for the object depicted in the image. Various embodiments are described and tested for a variety of objects, including a mug with a handle 202, a mustard bottle 204, a detergent bottle 206, a salt shaker 208, a small box 210, a large box 212, and a bowl 214.

[0017] In cluttered environments, i.e., cluttered environments containing various objects and occlusions, grasp synthesis can become very complex and challenging. It may be desirable to grasp a target object, such as a mustard bottle 204, without any unwanted collisions with surrounding objects or otherwise interfering with other objects in the environment. In a real-world application, a robot may be commanded to grasp a particular drink from a narrow cupboard cluttered with other items. Grasps sampled in a clutter-free environment may collide with the environment. In some instances, even if the gripper prior is collision-free, planning a collision-free, kinematically feasible path for the manipulator to achieve a gripper configuration can be challenging. In various embodiments, a diverse set of grasps may be generated because not all grasps are kinematically feasible to operate in the environment.

[0018] In object clutter, significant portions of a target object's shape may be occluded by other objects. In at least one embodiment, a technique uses a learning-based approach to achieve 6DOF grasp generation in structured clutter. The technique may utilize instance segmentation and point cloud observation from a single viewpoint. The technique may utilize a cascaded approach to grasp generation in clutter, which may include first inferring a grasp at the object level and then inspecting the clutter environment for collisions. The technique may utilize a trained collision checker that can evaluate a grasp for collisions from only a partial raw point cloud observation and can function under various degrees of occlusion.

[0019] In at least some embodiments, this technique enables a robotic system to grasp an object from a collection of multiple objects. The accessible workspace around a target object may be significantly limited and may include occlusions that can hinder perception. In at least some embodiments, the robotic system may operate against structured clutter. Structured clutter may be defined as a packed configuration of primarily large, heavy objects. Examples may include a cupboard or supermarket shelf. In structured clutter, the stable equilibrium of objects is low, and collisions and unintended contact can result in significant damage. In at least some embodiments, the robotic system can predict colliding grasp configurations and can do so despite occlusion. In structured clutter, spatial grasps may be unavoidable. The robotic system may use a learned grasp sampler that can predict full 6D grasp poses, capturing areas hidden by occlusion. In at least some embodiments, the robotic system may not require any object models; grasps may be planned based on depth images and / or point clouds. In at least some embodiments, the robotic system can be target-driven by utilizing instance segmentation to match the grasp to the object.

[0020] Shape-inspired heuristics may be used to select promising grasp points around the object, optionally followed by a more detailed shape analysis of the safety and reachability of the sampled grasps. Various approaches for selecting promising grasp points rely on the availability of a complete 3D model of the object, which can be a limitation in some realistic scenarios, for example, where the robot only observes the scene with a noisy depth camera. To overcome this limitation, some embodiments move the camera or perform shape completion to generate a complete object model, followed by a shape-based grasp analysis.

[0021] Deep learning techniques may be used to assess grasp quality from raw point cloud data. In at least one embodiment, a learning-based framework may be used to efficiently generate a diverse set of stable grasps for an unknown object. Various embodiments provide multiple network architectures for sampling, evaluating, and improving grasps. For example, a variational autoencoder (VAE) may be trained to map a partial point cloud of an observed object to a diverse set of grasps for the object. In at least one embodiment, the VAE provides a high degree of coverage of working grasps while generating a relatively small number of unsuccessful grasps. In some instances, a grasp classifier network may map the observed object and robot gripper point clouds to a quality assessment of the 6D gripper pose. The gradient of this network can be used to improve the grasp sample, for example, by moving the grasp sample to avoid collisions or to ensure that the gripper is well aligned with the object.

[0022] FIG. 3 illustrates a binary mask containing image data of graspable objects, according to one embodiment. In at least one embodiment, the binary mask illustrated in FIG. 3 is associated with an image, such as a depth image from a depth camera. In at least one embodiment, the binary mask is a portion of or derived from an RGB-D image containing image data of the objects depicted in the binary mask. In at least one embodiment, the binary mask includes a binary mask for a mug with handle 302, a binary mask for a mustard jar 304, a binary mask for a detergent bottle 306, a binary mask for a salt shaker 308, a binary mask for a small box 310, a binary mask for a large box 312, and a binary mask for a bowl 314. In at least one embodiment, the mustard jar 304 is selected to be grasped by the robot. In at least one embodiment, the binary mask containing image data of the objects is used to isolate target objects to be grasped by the robot. The target objects may be selected based on one or more segmentation algorithms. This selection is used to infer a possible successful grasp for the target object, ignoring clutter, which is then combined with the collision outcome provided by the collision determination system or process.

[0023] FIG. 4 illustrates a point cloud generated from image data of a graspable object, according to one embodiment. In at least one embodiment, the point cloud is a three-dimensional point cloud. The three-dimensional point cloud may be generated from an RGB-D image that includes image data of an object within clutter. In at least one embodiment, the three-dimensional point cloud is generated from the image data depicted in FIGS. 2 and / or 3. In at least one embodiment, the point cloud includes point cloud image data of a mug with a handle 402, a mustard bottle 404, a detergent bottle 406, a salt shaker 408, a small box 410, a large box 412, and a bowl 414. As depicted in FIG. 4, the point cloud generated from the image data of the object may be cropped using a bounding volume 416. In some embodiments, the bounding volume 416 is a bounding box.

[0024] FIG. 5 illustrates a cropped point cloud generated from image data of a graspable object, according to one embodiment. In at least one embodiment, the cropped point cloud is a cropped three-dimensional point cloud. The cropped three-dimensional point cloud may be generated from an RGB-D image that includes image data of an object within clutter. In at least one embodiment, the cropped point cloud is generated from the image data depicted in FIGS. 2, 3, and / or 4. In at least one embodiment, the cropped point cloud includes point cloud image data of a mug with handle 502, a mustard jar 504, a detergent bottle 506, a salt shaker 508, and a bowl 514.

[0025] In at least one embodiment, the technique may generate a 6DOF grasp for an object in clutter. As described, input to the system may be a depth image of the scene and a binary mask showing the target object, as shown in Figures 2 and 3, respectively. In at least one embodiment, one or more grasps may be defined as an open parallel yaw gripper pose ∈ SE(3), and when this gripper closes its fingers, a robust grasp may be generated. A posterior probability grasp distribution may be estimated, which may be defined as P(G*|X), where X may be the point cloud observation and G* may be the successful grasp of the object. In at least one embodiment, the point clouds shown in Figures 4 and / or 5 may be utilized.

[0026] The distribution of successful grasps can be complex, multimodal, and discontinuous. The number of modes may be unknown for a novel object and may be determined by the object's shape, size, and physical properties. Furthermore, slight perturbations of a robust grasp can lead to failure due to collisions or slippage caused by insufficient contact. Furthermore, cluttered scenes can significantly limit the robot's workspace. Even if parts of the object can be seen, grasping may be impossible for large objects (e.g., robots) where the gripper itself may collide with surrounding objects.

[0027] In at least one embodiment, the technique may factorize the estimation of P(G*|X) by separately learning the grasp distribution for a single, isolated object P(G*|X) and utilizing a discriminative model P(C|X, g), which may be called CollisionNet, that can capture collisions C between the gripper at pose g and clutter observed as X. The benefit of this factorization may be twofold. First, it allows for the inference of 6DOF grasp poses for a single, unknown object. Second, it allows for the inference of behavior beyond simple picking by explicitly exploring the reasons for grasp success (e.g., target object shape and collision-free / reachable gripper poses). The system may be used to infer which objects should be removed from the scene to maximize grasp success for the target object.

[0028] FIG. 6 illustrates a point cloud of a disjointed object generated from image data of a graspable object, according to one embodiment. In at least one embodiment, the point cloud is a three-dimensional point cloud derived from the point cloud illustrated in FIG. 5. The three-dimensional point cloud may be generated from an RGB-D image that includes image data of an object within clutter. In at least one embodiment, the point cloud is generated from the image data illustrated in FIGS. 2, 3, 4, and / or 5. In at least one embodiment, the point cloud includes point cloud image data of a mustard jar 604. FIG. 6 further illustrates a set of grasps 606. In at least one embodiment, grasp 602 in the set of grasps is a predicted successful or positive grasp for mustard jar 604, and this grasp may be performed by the robotic system.

[0029] In at least one embodiment, a generative model for grasps may be trained given a point cloud observation of a cluttered scene. This generative model may be trained from a reference set of positive grasps, but may not be entirely perfect due to various factors. A second module may be used to evaluate and further improve the generated grasps. Given the point cloud and the grasp, an evaluator may predict a quality score for the grasp. This information can also be used to incrementally refine the grasp. In various embodiments, object instance information may be used at all stages of the 6DOF grasp pipeline, from grasp generation to evaluation.

[0030] In at least one embodiment, the grasp sampler may be a conditional VAE, a deterministic function that predicts a grasp g given a point cloud X and latent variables z. P(z)=N(0,I) may be a known probability density function of the latent space. The likelihood of a grasp can be written as: P(G|X)=∫P(G|X,z)P(z)dz

[0031] Optimizing the above equation can be intractable, as it may require integrating all values ​​in the latent space. To make it tractable, an encoder Q(z|X,g) may be used to map each pair of point cloud X and grasp g to the latent space z, while a decoder may reconstruct the grasp given the sampled z. The KL divergence penalty between the distribution Q and a normal distribution N(0,1) is calculated to minimize the reconstruction loss L(g',g) between the ground truth grasp g∈G+ and the predicted grasp g'.

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[0032] To combine the orientation and translation losses, the reconstruction loss may be defined as:

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[0033] While instance information can provide strong prior knowledge about objects, it is not entirely accurate in practice. This is the case in clutter situations where objects are occluded or very close to each other, which can result in noisy under- or over-segmentation. When rendering the segmentation in a simulation, random salt-and-pepper noise may be added to object boundaries, randomly merging partially occluded objects with neighboring objects in image space to mimic imperfections in instance segmentation methods for real images.

[0034] In at least one embodiment, the grasp sampler may be trained only on positive grasps, but may include missed grasps that may need to be identified and filtered out.

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[0035] A significant proportion of the grasps rejected by the evaluator may be close to robust grasps. This knowledge may be exploited to perform a local search in the region of g to iteratively improve the evaluator score. In some instances, Δg may be sampled to increase the probability of success, e.g., to make P(S|Δg+g,X)>P(S|g,X). Refinement may be found using gradient descent. In various embodiments, computing the gradient may be complex. Metropolis-Hastings sampling may be used, where a random Δg is sampled and a probability

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[0036] FIG. 7 illustrates a point cloud and a set of grasps for a disjointed object, where point clouds for other objects are combined with the point cloud for the disjointed object, according to one embodiment. In at least one embodiment, the point cloud is a three-dimensional point cloud derived from the point clouds illustrated in FIGS. 5-6. The three-dimensional point cloud may be generated from an RGB-D image that includes image data for objects within the clutter. In at least one embodiment, the point cloud is generated from the image data illustrated in FIGS. 2, 3, 4, 5, and / or 6. In at least one embodiment, the point cloud includes point cloud image data for a mug with handle 702, a mustard bottle 704, a detergent bottle 706, a salt shaker 708, and a bowl 714. FIG. 7 also illustrates a set of grasps 716. In at least one embodiment, the grasps in the set of grasps 716 are predicted successful or positive grasps for the mustard bottle 604, which may be performed by the robotic system. In at least one embodiment, the grasps in the set of grasps 716 are pruned to exclude one or more grasps 718 that interfere with or collide with other objects in the collection of objects, such as grasps that collide with the detergent bottle 706, the mug with handle 702, the salt shaker 708, and / or the bowl 714.

[0037] CollisionNet may predict clutter-centered collision scores P(C|X,g) given full scene information X, such as the point cloud shown in FIG. 7 or other point clouds. The training data for CollisionNet is

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[0038] Training data may be generated by randomly arranging multiple objects in stable poses. Objects may be added to the scene with rejection sample poses to ensure they do not collide with existing clutter. Positive and negative grasps for each object may be combined to generate a grasp for the scene. From each scene, multiple 3D crops (including some noise) centered on the object may be used, along with possible grasps inside the crop. A cropped 3D box point cloud, such as that shown in Figure 5, may be downsampled to reduce the number of points (e.g., 4096). All samplers and VAEs may be based on an architecture such as the PointNet architecture, and the dimension of the latent space may be set to 2. Object instances may be segmented during inference to determine objects that collide with a determined successful grasp. The VAE sampler may generate a grasp given the point cloud of the target object by sampling a large number of latent values ​​(e.g., 200). The grasp may be further refined by multiple iterations (e.g., 25) of the Metropolis-Hastings algorithm. In various embodiments, the entire inference may take approximately 2.5 seconds.

[0039] In at least one embodiment, two metrics may be used to evaluate generated grasps: success rate and coverage. Success rate may be the percentage of grasps that successfully grasp an object without collision, and coverage may be the percentage of sampled ground truth grasps that are within a threshold (e.g., 2 centimeters) of any generated grasp. Ablation may be performed in simulation using a held-out test set of unknown objects. Synthetic point clouds may be rendered from clutter scenes generated with these test objects in random, stable poses. Physical interactions may be simulated using one or more simulation applications. The area under the curve of a success rate-coverage plot may be used to compare different variations of methods in ablation studies. The success rate-coverage curve may be calculated by ranking the grasp scores predicted by the grasp evaluator.

[0040] The effectiveness of CollisionNet may be compared to various conventional voxel-based heuristics (e.g., MoveIt!) for obstacle avoidance in unknown 3D environments. In some embodiments, a number of points (e.g., 100) may be sampled using farthest-point sampling. Each sampled point may be represented by a voxel cube of a certain size (e.g., 2 centimeters). Collision detection may be performed by examining the intersection of the gripper mesh with any voxel. CollisionNet may outperform other voxel-based heuristics in terms of accuracy and coverage. Voxel-based representations may fail to capture collisions when the gripper mesh intersects with occluded portions of an object or when depth information is missing. In cases where voxel-based collision detection fails, CollisionNet may have a high (89.7%) accuracy rate in accurately classifying collisions.

[0041] Traditional voxel-based methods may reject good grasps that may narrowly pass through voxels corresponding to points on the target object, resulting in some false negatives, because voxels expand the spatial region for collision detection. Not considering voxels on the target object for collisions slightly increases coverage, but at the cost of impaired grasp success, because grasps that may actually collide with the target object cannot be excluded. CollisionNet can be immune to these biases and can infer relative spatial information from partial point clouds.

[0042] In at least one embodiment, a single stage sampler and evaluator with object instance information may be used instead of a cascaded grasp generation approach. Once a grasp is sampled,

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[0043] In at least one embodiment, the VAE is better at learning grasps from object-centric observations than from scene-level information. Furthermore, a cascaded architecture may impose an abstraction between having a grasp evaluator, which may be solely good at inferring grasp robustness, and a CollisionNet, which may be better at predicting collisions.

[0044] The cascaded grasp sampling approach may be compared to an instance-unaware baseline. Without instance information, the baseline can be a single-stage grasp planner that may use the scene point cloud. The cascaded grasp sampler (which uses instance information and CollisionNet) can have an AUC of 0.07, outperforming the object-instance-unaware baseline, which can have an AUC of 0.001, in terms of both success rate and coverage. A common failure mode of instance-unaware models is that the variational sampler may not be able to determine which object in the scene should be grasped, potentially mapping the latent space to grasps for multiple objects, resulting in poor overall grasp quality for all objects.

[0045] In at least one embodiment, the cascaded grasp synthesis approach can have competitive performance for target-driven grasping in real cluttered scenes, outperforming a baseline method that uses a clutter-aware 6DOF system, which may be called GraspNet. Conventional clutter-aware 6DOF uses instance segmentation and voxel-based collision detection.

[0046] In at least one embodiment, the physical configuration may include a robot and a gripper. In some embodiments, the physical configuration may include a Franka Panda robot with a parallel-jaw gripper. The gripper may be replaced with a clamp, a scalpel, a needle, scissors, or a laser. A camera mounted on the gripper's wrist may be utilized for perception. In some embodiments, an Intel Realsense D415 RGB-D camera mounted on the gripper's wrist may be used for perception. A set of common household and kitchen objects of various shapes, physical properties, and visual characteristics may be selected, including those from the YCB (Yale-CMU-Berkeley) dataset.

[0047] In at least one embodiment, the performance of the technique may be compared for various scenes with a fixed (randomly pre-computed) order of objects to be grasped. A grasp may be considered successful if the robot can grasp an object within two or fewer tries for the same scene. An order in which all target objects are fully visible may be determined. In some instances, half of the selected target objects may be occluded. To generate grasps, a batch size of a number of potential values ​​(e.g., 200) may be sampled, and grasps with scores below a threshold for each evaluator may be removed. From the remaining grasps, the one with the highest score is selected to be executed.

[0048] Results from at least one implementation are summarized in Figure 8, including Table 1. The described cascaded approach and technique can achieve a success rate of 80.3%, approximately 17.6% better than the baseline 6DOF GraspNet approach. Furthermore, without CollisionNet, model performance can be significantly degraded. Two failure cases can occur when grasps collide with objects, but the object-centric evaluator predicts high scores for those grasps. These grasps can be filtered out by CollisionNet. The second failure mode relates to the fact that the voxel-based representation cannot capture all collisions.

[0049] In at least one embodiment, the target object may be occluded by other objects, making all sampled grasps kinematically infeasible. In at least one embodiment, the technique may be required to generate potential grasps for a target object even if the target object is physically unreachable (e.g., determined at least based on a low score obtained from CollisionNet). Given the potential grasps, objects that interfere with the generated grasps for the target object may be identified. An occluding object j may be removed when the corresponding object point is removed from the point cloud of the scene, e.g.,

number

number

[0050] In at least one embodiment, a technique is developed for a learning-based framework to synthesize 6DOF grasps for novel objects in structured clutter environments. In various embodiments, collision avoidance may be essential due to occlusion. In some embodiments, the technique can achieve high grasp accuracy (e.g., 80.3%) when grasping novel objects in clutter on a real robotic platform, despite only being trained in simulation. In at least one embodiment, the technique may only consider collisions of the gripper's pre-shape by design, and motion planning may still require further processing of the generated grasp. Trajectory generation in grasp generation may be considered and utilized in task planning applications.

[0051] Figure 9 shows an example process 900 for generating a set of grasp poses, according to one embodiment. In at least one embodiment, one or more computer systems, such as one or more of the computer systems described and illustrated in Figures 10-43, execute instructions stored in a computer-readable memory that cause the computer system to perform the operations shown and described in Figure 9. In at least one embodiment, the computer system is a robotic system, such as the robotic system shown in Figure 1. The robotic system can incorporate one or more of the computer systems described and illustrated herein.

[0052] In at least one embodiment, the process begins at block 902, where a computer system obtains image data for a plurality of objects. In at least one embodiment, each of the process blocks described below may be performed by a single computer system or may be performed by multiple distributed computer systems. In at least one embodiment, the image data is obtained from a depth image. An example depth image including image data is shown in FIG. 2. The image data may include target objects to be grasped by the robot. In at least one embodiment, the depth image may include a binary mask. An example binary mask is shown in FIG. 3. The binary mask may include sets of points, each set of points corresponding to at least one object of the plurality of objects. In at least one embodiment, the set of points of the binary mask represent an inner contour and an outer contour of one object of the plurality of objects. In at least one embodiment, the set of points of the binary mask represent at least an outer contour of a target object associated with the plurality of objects. Thus, in at least one embodiment, the binary mask may be used to isolate each object of the plurality of objects. In at least one embodiment, the binary mask is used to identify the target object. For example, a binary mask may be used by a robot or a human to identify a target object for which to generate a set of grasp poses.

[0053] In at least one embodiment, the image data is acquired from one or more depth cameras. In at least one embodiment, the image data may be collected using various 3D imaging devices, such as a RADAR, LIDAR, CT scanner, MRI imager, ultrasound, or x-ray machine. In at least one embodiment, the device used to collect the image data generates one or more point clouds. In other instances, the image data generated by the 3D imaging device is converted into one or more point clouds. In at least one embodiment, other types of 3D imaged data may be used directly by the generation and evaluation network to generate and evaluate grasp poses.

[0054] In at least one embodiment, a 3D point cloud is generated from the image data of the plurality of objects in block 904. In at least one embodiment, the 3D point cloud is generated from a depth image that includes a binary mask. An example 3D point cloud is shown in FIG.

[0055] In at least one embodiment, the size of the 3D point cloud is reduced in block 906. For example, the 3D point cloud may be cropped to achieve the size reduction. In at least one embodiment, a bounding volume is used as a basis for reducing the size of the 3D point cloud. An example bounding volume is shown in FIG. 4. In at least one embodiment, the bounding volume may be applied to the 3D point cloud. In some implementations, image data outside the bounding volume is cropped from the 3D point cloud to generate a modified 3D point cloud. In at least one embodiment, the modified 3D point cloud is shown in FIG. 5. In some implementations, the bounding volume is a bounding box having a predetermined volume. In at least one embodiment, the 3D point cloud and the modified 3D point cloud include image data representing a target object. In some implementations, the 3D point cloud and the modified 3D point cloud include image data representing the target object and additional objects proximate to the target object.

[0056] In at least one embodiment, in block 908, image data of the target object is separated from image data associated with other objects proximate the target object. In at least one embodiment, the separated image data of the target object is in a 3D point cloud or a rectified 3D point cloud. In at least one embodiment, separating the image data of the target object from image data associated with other objects proximate the target object results in a 3D point cloud generated from the 3D point cloud or the rectified 3D point cloud that is limited to the image data of the target object. An example 3D point cloud including separated image data of the target object is shown in FIG. 6.

[0057] In at least one embodiment, in block 910, a set of grip poses is generated for the target object. An example set of grip poses for the target object is shown in FIG. 6. In at least one embodiment, the set of grip poses is generated using image data associated with the target object. In at least one embodiment, the image data associated with the target object is in a three-dimensional point cloud. The three-dimensional point cloud may be limited to those that include image data associated with the target object. In at least one embodiment, the three-dimensional point cloud that includes image data of the target object is a modified three-dimensional point cloud based on a three-dimensional point cloud that includes image data of one or more other objects, such as the three-dimensional point cloud shown in FIG. 5. In at least one embodiment, the other objects are in a collection of objects that includes the target object.

[0058] In at least one embodiment, the set of grasp poses generated in block 910 includes one or more predicted grasps. In at least one embodiment, the one or more predicted grasps are generated based on processing of image data and computer-aided simulation. In at least one embodiment, the one or more predicted grasps are generated by a robot. In at least one embodiment, the set of grasp poses for the target object is included in a three-dimensional point cloud. For example, the three-dimensional point cloud may include a set of grasp poses that include successful grasp poses for the target object. An example three-dimensional point cloud of a set of grasp poses is shown in FIG. 6.

[0059] In at least one embodiment, image data of other objects proximate the target object is included in the 3D point cloud. In some implementations, in block 912, the 3D point cloud including the image data of the other objects is combined with a 3D point cloud including a set of grip poses including successful grip poses for the target object. In some implementations, the process of combining the 3D point clouds generates a combined 3D point cloud including the image data of the other objects and the set of grip poses including successful grip poses for the target object. An example 3D point cloud including the image data of the other objects and the set of grip poses including successful grip poses for the target object is shown in FIG. 7. The 3D point cloud shown in FIG. 7 includes point cloud image data of the target object. However, as shown, in at least one embodiment, the 3D point cloud may exclude the target object.

[0060] In at least one embodiment, the combined three-dimensional point cloud is subjected to computer-assisted processing to identify one or more gripping poses that, when performed by the robot, will interfere with or contact one or more of the other objects. In at least one embodiment, in block 914, the identified one or more interfering gripping poses are removed from a set of gripping poses including successful gripping poses for the target object. In at least one embodiment, the three-dimensional point cloud including the set of gripping poses including successful gripping poses for the target object is modified to remove image data associated with the identified one or more interfering gripping poses. In at least one embodiment, the modified set of gripping poses includes successful gripping poses for the target object based on image data of other objects proximate to the target object. In at least one embodiment, the modified set of gripping poses includes successful gripping poses that enable the robot to grasp the target object while avoiding other objects proximate to the target object.

[0061] In at least one embodiment, a combined 3D point cloud including image data of the other objects and a set of grip poses including successful grip poses for the target object is combined with a 3D point cloud including image data of the target object. The resulting 3D point cloud includes image data of the target object, image data of the other objects, and the set of grip poses including successful grip poses for the target object. In at least one embodiment, the combined 3D point cloud is subjected to computer-assisted processing to identify one or more grip poses that, when performed by the robot, would interfere with or contact one or more of the other objects. In at least one embodiment, the identified one or more interfering grip poses are removed from the set of grip poses including successful grip poses for the target object. In at least one embodiment, the 3D point cloud including the set of grip poses including successful grip poses for the target object is modified to remove image data associated with the identified one or more interfering grip poses. In at least one embodiment, the modified set of grip poses includes successful grip poses for the target object based on image data of the other objects proximate to the target object. In at least one embodiment, the modified set of grasping poses includes successful grasping poses that allow the robot to grasp the target object while avoiding other objects in the vicinity of the target object.

[0062] Logic of inference and training Figure 10A illustrates inference and / or training logic 1015 used to perform inference and / or training operations for one or more embodiments. More details regarding inference and / or training logic 1015 are provided below in conjunction with Figures 10A and / or 10B.

[0063] In at least one embodiment, the inference and / or training logic 1015 may include, without limitation, code and / or data storage 1001 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that is trained and / or used to infer in one or more embodiments. In at least one embodiment, the training logic 1015 may include or be coupled to code and / or data storage 1001 for storing graph code or other software for controlling the timing and / or sequence of logic loaded with weights and / or other parameter information, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 1001 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1001 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache, or system memory.

[0064] In at least one embodiment, any portion of code and / or data storage 1001 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1001 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1001 is internal or external to a processor, for example, or whether it includes DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0065] In at least one embodiment, the inference and / or training logic 1015 may include, without limitation, code and / or data storage 1005 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with one or more aspects of the embodiment. In at least one embodiment, the code and / or data storage 1005 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while backpropagating input / output data and / or weight parameters during training and / or inference using one or more aspects of the embodiment. In at least one embodiment, training logic 1015 may include or be coupled to code and / or data storage 1005 for storing graph code or other software for controlling timing and / or ordering, and into which weights and / or other parameter information are loaded to configure logic including integer and / or floating point units (collectively, arithmetic logic units (ALUs)).

[0066] In at least one embodiment, code, such as graph code, loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 1005 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1005 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1005 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 1005 is internal or external to the processor, for example, or whether it comprises DRAM, SRAM, flash memory, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or any combination of these factors.

[0067] In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be separate storage structures. In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be combined storage structures. In at least one embodiment, code and / or data storage 1001 and code and / or data storage 1005 may be partially combined and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 1001 and code and / or data storage 1005 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0068] In at least one embodiment, the inference and / or training logic 1015 may include one or more arithmetic logic units (“ALUs”) 1010, including, without limitation, integer and / or floating point units, for performing logical and / or mathematical operations based at least in part on or indicated by the training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 1020, which are functions of input / output and / or weight parameter data stored in code and / or data storage 1001 and / or code and / or data storage 1005. In at least one embodiment, the activations stored in activation storage 1020 are generated according to linear algebra or matrix-based calculations performed by ALU 1010 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 1005 and / or data storage 1001 are used as operands along with other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 1005, or code and / or data storage 1001, or in another storage, on-chip or off-chip.

[0069] In at least one embodiment, ALU 1010 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU 1010 may be external to the processors or other hardware logic devices or circuits (e.g., coprocessors) that use it. In at least one embodiment, ALU 1010 may be included within an execution unit of a processor or may otherwise be included within an ALU bank accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1001, code and / or data storage 1005, and activation storage 1020 may share the same processor or other hardware logic device or circuit, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or some combination of the same processor or other hardware logic device or circuit and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1020 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache, or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0070] In at least one embodiment, activation storage 1020 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 1020 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 1020 is internal or external to a processor, for example, or whether it comprises DRAM, SRAM, flash memory, or some other type of storage, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inference and / or training of the neural network, or any combination of these factors.

[0071] In at least one embodiment, the inference and / or training logic 1015 shown in Figure 10A may be used in conjunction with an application specific integrated circuit ("ASIC") such as Google's TensorFlow® processing unit, Graphcore™'s inference processing unit (IPU), or Intel Corp's Nervana® (e.g., "Lake Crest") processor. In at least one embodiment, the inference and / or training logic 1015 shown in Figure 10A may be used in conjunction with other hardware such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or field programmable gate arrays ("FPGAs").

[0072] FIG. 10B illustrates inference and / or training logic 1015, according to at least one embodiment. In at least one embodiment, the inference and / or training logic 1015 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 1015 illustrated in FIG. 10B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 1015 illustrated in FIG. 10B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit (“GPU”) hardware, or a field-programmable gate array (FPGA). In at least one embodiment, inference and / or training logic 1015 may include, without limitation, code and / or data storage 1001 and code and / or data storage 1005, which may be used to store code (e.g., graph code), weight and / or bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 10B , code and / or data storage 1001 and code and / or data storage 1005 are each associated with dedicated computational resources, such as computation hardware 1002 and computation hardware 1006, respectively. In at least one embodiment, computation hardware 1002 and computation hardware 1006 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in code and / or data storage 1001 and code and / or data storage 1005, respectively, with the results stored in activation storage 1020.

[0073] In at least one embodiment, each of the code and / or data storage 1001 and 1005 and corresponding computational hardware 1002 and 1006 corresponds to a different layer of a neural network, whereby activations resulting from one storage / computation pair 1001 / 1002, between the code and / or data storage 1001 and computational hardware 1002, are provided as input to the next storage / computation pair 1005 / 1006, between the code and / or data storage 1005 and computational hardware 1006, to reflect the conceptual organization of the neural network. In at least one embodiment, the storage / computation pairs 1001 / 1002 and 1005 / 1006 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in inference and / or training logic 1015 after or in parallel with storage / computation pairs 1001 / 1002 and 1005 / 1006.

[0074] Neural network training and deployment FIG. 11 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 1106 is trained using a training data set 1102. In at least one embodiment, the training framework 1104 is the PyTorch framework, while in other embodiments, the training framework 1104 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 and enables it to be trained using processing resources described herein to generate a trained neural network 1108. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0075] In at least one embodiment, the untrained neural network 1106 is trained using supervised learning, where the training data set 1102 includes inputs paired with desired outputs for those inputs, or the training data set 1102 includes inputs with known outputs, and the outputs of the neural network 1106 are manually scored. In at least one embodiment, the untrained neural network 1106 is trained in a supervised manner, processing inputs from the training data set 1102 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 1106. In at least one embodiment, the training framework 1104 adjusts the weights that control the untrained neural network 1106. In at least one embodiment, the training framework 1104 includes tools for monitoring how well the untrained neural network 1106 is converging toward a model, such as the trained neural network 1108, that is suitable for generating correct answers, such as in the results 1114, based on input data, such as the new data set 1112. In at least one embodiment, the training framework 1104 iteratively trains the untrained neural network 1106 while adjusting weights to refine the output of the untrained neural network 1106 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 1104 trains the untrained neural network 1106 until it reaches a desired accuracy. In at least one embodiment, the trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0076] In at least one embodiment, the untrained neural network 1106 is trained using unsupervised learning, where the untrained neural network 1106 attempts to train itself using unlabeled data. In at least one embodiment, the training data set 1102 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 1106 can learn groupings within the training data set 1102 and determine how individual inputs relate to the untrained data set 1102. In at least one embodiment, unsupervised training can be used within the trained neural network 1108 to generate self-organizing maps, which can perform operations useful for reducing the dimensionality of the new data set 1112. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new data set 1112 that deviate from the normal patterns of the new data set 1112.

[0077] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training data set 1102. In at least one embodiment, the training framework 1104 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 1108 to adapt to a new data set 1112 without forgetting the knowledge instilled in the trained neural network 1108 during initial training.

[0078] Data Center 12 illustrates an exemplary data center 1200 in which at least one embodiment may be used. In at least one embodiment, data center 1200 includes a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0079] As shown in FIG. 12 , in at least one embodiment, data center infrastructure layer 1210 may include a resource orchestrator 1212, grouped computing resources 1214, and node computing resources (“node CRs”) 1216(1) through 1216(N), where “N” represents a positive integer (although “N” may be a different integer than that used in other figures). In at least one embodiment, nodes CR 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1218(1)-1218(N) (e.g., dynamic read-only memory, solid-state storage drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules. In at least one embodiment, one or more of nodes CR 1216(1)-1216(N) may be a server having one or more of the computing resources described above.

[0080] In at least one embodiment, grouped computing resources 1214 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). In at least one embodiment, separate groups of node CRs within grouped computing resources 1214 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0081] In at least one embodiment, resource orchestrator 1212 may configure or otherwise control one or more nodes CR 1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource orchestrator 1212 may include a software design infrastructure (“SDI”) management entity for data center 1200. In at least one embodiment, resource orchestrator 1212 may include hardware, software, or some combination thereof.

[0082] In at least one embodiment shown in FIG. 12 , framework layer 1220 includes job scheduler 1222, configuration manager 1224, resource manager 1226, and distributed file system 1228. In at least one embodiment, framework layer 1220 may include frameworks to support software 1232 in software layer 1230 and / or one or more applications 1242 in application layer 1240. In at least one embodiment, software 1232 or applications 1242 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1220 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark® (hereinafter “Spark”), which can use distributed file system 1228 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1232 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 1200. In at least one embodiment, configuration manager 1224 may be capable of configuring different tiers, such as software tier 1230 and framework tier 1220, which includes Spark and distributed file system 1228 to support large-scale data processing. In at least one embodiment, resource manager 1226 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 1228 and job scheduler 1222. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1214 in data center infrastructure tier 1210.In at least one embodiment, resource manager 1226 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 1212.

[0083] In at least one embodiment, software 1232 included in software layer 1230 may include software used by nodes CR 1216(1)-1216(N), grouped computing resources 1214, and / or at least a portion of distributed file system 1228 of framework layer 1220. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0084] In at least one embodiment, applications 1242 included in application layer 1240 may include one or more types of applications used by at least a portion of nodes CR 1216(1)-1216(N), grouped computing resources 1214, and / or distributed file system 1228 of framework layer 1220. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and applications including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and machine learning applications, or other machine learning applications used in conjunction with one or more embodiments.

[0085] In at least one embodiment, any of configuration manager 1224, resource manager 1226, and resource orchestrator 1212 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable a data center operator of data center 1200 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0086] In at least one embodiment, data center 1200 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1200. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1200 by using weight parameters calculated by one or more techniques described herein.

[0087] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0088] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with FIG. 10A and / or FIG. 10B . In at least one embodiment, the inference and / or training logic 1015 may be used in the system of FIG. 12 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. In at least one embodiment, a system for determining a set of grasp poses based on one or more point clouds can be constructed using a computer system as shown and described above.

[0089] Autonomous Vehicles 13A illustrates an example of an autonomous vehicle 1300 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1300 (alternatively referred to herein as “vehicle 1300”) may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, the vehicle 1300 may be a semi-tractor trailer truck for hauling cargo. In at least one embodiment, the vehicle 1300 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0090] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In at least one embodiment, vehicle 1300 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1300 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0091] In at least one embodiment, vehicle 1300 may include components such as, without limitation, a chassis, a vehicle body, wheels (2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1300 may include a propulsion system 1350 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1350 may be coupled to a drive train of vehicle 1300, which may include, without limitation, a transmission to enable propulsion of vehicle 1300. In at least one embodiment, propulsion system 1350 may be controlled in response to receiving a signal from throttle / accelerator 1352.

[0092] In at least one embodiment, steering system 1354, which may include without limitation a steering wheel, is used to steer vehicle 1300 (e.g., along a desired path or route) when propulsion system 1350 is operating (e.g., when vehicle 1300 is moving). In at least one embodiment, steering system 1354 may receive signals from steering actuator 1356. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1346 may be used to operate vehicle brakes in response to receiving signals from brake actuator 1348 and / or brake sensor.

[0093] In at least one embodiment, controller 1336, which may include, without limitation, one or more systems on a chip (“SoC”) (not shown in FIG. 13A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1300. For example, in at least one embodiment, controller 1336 may send signals to operate vehicle brakes via brake actuator 1348, to operate steering system 1354 via steering actuator 1356, and to operate propulsion system 1350 via throttle / accelerator 1352. In at least one embodiment, controller 1336 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1300. In at least one embodiment, controller 1336 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or some combination thereof.

[0094] In at least one embodiment, controller 1336 provides signals to control one or more components and / or systems of vehicle 1300 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system (“GNSS”) sensors 1358 (e.g., global positioning system sensors), RADAR sensors 1360, ultrasonic sensors 1362, LIDAR sensors 1364, inertial measurement units (“IMUs”), and the like. The vehicle 1300 vehicle information may be received from sensors 1366 (e.g., accelerometers, gyroscopes, magnetic compasses, magnetometers, etc.), microphones 1396, stereo cameras 1368, wide-angle cameras 1370 (e.g., fisheye cameras), infrared cameras 1372, ambient cameras 1374 (e.g., 360-degree cameras), long-range cameras (not shown in FIG. 13A ), mid-range cameras (not shown in FIG. 13A ), speed sensors 1344 (e.g., for measuring the speed of the vehicle 1300), vibration sensors 1342, steering sensors 1340, brake sensors (e.g., as part of brake sensor system 1346), and / or other types of sensors.

[0095] In at least one embodiment, one or more of the controllers 1336 may receive input (e.g., represented by input data) from the instrument cluster 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1334, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1300. In at least one embodiment, the output may include information such as vehicle speed, speeding, time, map data (e.g., a high definition map (not shown in FIG. 13A )), location data (e.g., the location of the vehicle 1300 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object conditions sensed by the controller 1336, etc. For example, in at least one embodiment, the HMI display 1334 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0096] In at least one embodiment, vehicle 1300 further includes network interface 1324, which may use a wireless antenna 1326 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 1324 may be capable of communicating over a Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA multi-carrier ("CDMA2000") network, etc. Additionally, in at least one embodiment, wireless antenna 1326 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide-area networks ("LPWAN") such as LoRaWAN, SigFox, etc.

[0097] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with FIG. 10A and / or FIG. 10B . In at least one embodiment, the inference and / or training logic 1015 may be used in the system of FIG. 13A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein. For example, for an electric vehicle, a robotic arm may be used to connect and charge the vehicle using techniques described herein. A successful grasp may be determined as a successful charging connection.

[0098] 13B illustrates example camera locations and fields of view for autonomous vehicle 1300 of FIG. 13A according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are exemplary examples and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on vehicle 1300.

[0099] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1300. In at least one embodiment, the camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0100] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0101] In at least one embodiment, one or more cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from inside the vehicle 1300 (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to a door mirror mounting assembly, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate conforms to the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. In at least one embodiment, for side view cameras, the cameras may again be integrated into the four pillars at each corner of the cabin.

[0102] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of the vehicle 1300 may be used for a surroundings view to facilitate identification of the path and obstacles ahead and, in conjunction with the controller 1336 and / or one or more of the control SoCs, may assist in providing information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the ADAS functions similar to LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0103] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1370 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While FIG. 13B shows only one wide-angle camera 1370, in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1300. In at least one embodiment, any number of long-range cameras 1398 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera 1398 may also be used for object detection and classification, as well as basic object tracking.

[0104] In at least one embodiment, any number of stereo cameras 1368 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 1368 may include an integrated control unit with a scalable processing unit, which may provide a programmable gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1300 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1368 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 1300 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1368 may be used in addition to or instead of those described herein.

[0105] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of vehicle 1300 (e.g., side view cameras) may be used for the surroundings view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 1374 (e.g., four surrounding cameras as shown in FIG. 13B ) may be disposed on vehicle 1300. In at least one embodiment, surrounding cameras 1374 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or the like. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of vehicle 1300. In at least one embodiment, vehicle 1300 may use three surrounding cameras 1374 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0106] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1300 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras also suitable as front cameras described herein (e.g., long-range camera 1398, and / or mid-range camera 1376, stereo camera 1368, infrared camera 1372, etc.).

[0107] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the system of Figure 13B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0108] FIG. 13C is a block diagram illustrating an example system architecture for the autonomous vehicle 1300 of FIG. 13A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1300 of FIG. 13C is shown as connected via a bus 1302. In at least one embodiment, the bus 1302 may include, without limitation, a CAN data interface (alternatively referred to herein as a (CAN bus)). In at least one embodiment, the CAN may be a network internal to the vehicle 1300 used to assist in controlling various features and functions of the vehicle 1300, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1302 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1302 may be read to determine steering wheel angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1302 may be an ASIL B compliant CAN bus.

[0109] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1302, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or to provide redundancy. For example, a first bus may be used for collision avoidance functions and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1302 may communicate with one of the components of vehicle 1300, and two or more of buses of bus 1302 may communicate with corresponding components. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1304 (e.g., SoC 1304(A) and SoC 1304(B)), each of the controllers 1336, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 1300) and may be connected to a common bus, such as a CAN bus.

[0110] In at least one embodiment, vehicle 1300 may include one or more controllers 1336, such as those described herein with respect to FIG. 13A . In at least one embodiment, controller 1336 may be used for a variety of functions. In at least one embodiment, controller 1336 may be coupled to any of a variety of other components and systems of vehicle 1300 and may be used to control vehicle 1300, artificial intelligence of vehicle 1300, infotainment and / or other functions of vehicle 1300.

[0111] In at least one embodiment, vehicle 1300 may include any number of SoCs 1304. In at least one embodiment, each of SoCs 1304 may include, without limitation, a central processing unit ("CPU") 1306, a graphics processing unit ("GPU") 1308, a processor 1310, a cache 1312, an accelerator 1314, a data store 1316, and / or other components and features not shown. In at least one embodiment, SoC 1304 may be used to control vehicle 1300 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1304 may be incorporated into a system (e.g., that of vehicle 1300) having a high definition ("HD") map 1322 that can obtain map refreshes and / or updates via a network interface 1324 from one or more servers (not shown in FIG. 13C ).

[0112] In at least one embodiment, CPU 1306 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 1306 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 1306 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1306 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). In at least one embodiment, CPU 1306 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 1306 to be active at any given time.

[0113] In at least one embodiment, one or more of the CPUs 1306 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPU 1306 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines what the best power state for cores, clusters, and CCPLEXes to enter is. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0114] In at least one embodiment, GPU 1308 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1308 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1308 may use an extended tensor instruction set. In at least one embodiment, GPU 1308 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1308 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1308 may use a compute application programming interface (API). In at least one embodiment, the GPU 1308 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA model).

[0115] In at least one embodiment, one or more of the GPUs 1308 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPUs 1308 may be fabricated on fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0116] In at least one embodiment, one or more of GPUs 1308 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, providing, in some examples, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or in place of the HBM memory.

[0117] In at least one embodiment, the GPU 1308 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow the GPU 1308 to directly access the page tables of the CPU 1306. In at least one embodiment, when the GPU 1308 memory management unit (“MMU”) experiences a GPU miss, an address translation request may be sent to the CPU 1306. In at least one embodiment, in response, two of the CPUs 1306 may look up the virtual-to-physical address mapping in their own page tables and send the translation back to the GPU 1308. In at least one embodiment, the unified memory technology allows for a single, unified virtual address space for both the CPU 1306 and the GPU 1308 memory, thereby simplifying programming the GPU 1308 and porting applications to the GPU 1308.

[0118] In at least one embodiment, GPU 1308 may include any number of access counters that can record the frequency of GPU 1308's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0119] In at least one embodiment, one or more of the SoCs 1304 may include any number of caches 1312, including those described herein. For example, in at least one embodiment, the caches 1312 may include a level 3 (“L3”) cache available to both the CPU 1306 and the GPU 1308 (e.g., connected to both the CPU 1306 and the GPU 1308). In at least one embodiment, the caches 1312 may include a write-back cache that can record line state using a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may also be used.

[0120] In at least one embodiment, one or more of the SoCs 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1304 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1308 and offload some of the GPU 1308's tasks (e.g., freeing up more cycles for the GPU 1308 to perform other tasks). In at least one embodiment, accelerator 1314 may be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0121] In at least one embodiment, accelerator 1314 (e.g., a hardware-accelerated cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, the DLAs may include, without limitation, one or more tensor processing units (“TPUs”), which may be further configured to provide tens of trillions of operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized for performing image processing functions (e.g., CNN, RCNN, etc.). In at least one embodiment, the DLAs may be further optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the design of the DLAs allows for improved performance per millimeter over typical general-purpose GPUs, typically greatly exceeding the performance of a CPU. In at least one embodiment, the TPU may execute several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, CNNs for object identification and detection using data from a camera sensor, CNNs for distance estimation using data from a camera sensor, CNNs for emergency vehicle detection and identification using data from a microphone, CNNs for face recognition and vehicle owner identification using data from a camera sensor, and / or CNNs for security and / or safety events.

[0122] In at least one embodiment, the DLA may perform any function of the GPU 1308, and a designer may target either the DLA or the GPU 1308 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 1308 and / or other accelerators 1314.

[0123] In at least one embodiment, accelerator 1314 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1338, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0124] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0125] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 1306. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0126] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0127] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0128] In at least one embodiment, the accelerator 1314 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 1314. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM including eight field-configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0129] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0130] In at least one embodiment, one or more of the SoCs 1304 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0131] In at least one embodiment, the accelerator 1314 can have diverse uses for autonomous driving. In at least one embodiment, the PVA can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA works well for semi-dense or dense regular computations that may require low-latency, low-power, and predictable run times, even with small data sets. In at least one embodiment, the PVA can be designed to run traditional computer vision algorithms, such as in the vehicle 1300, because they can be useful for object detection and integer arithmetic.

[0132] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0133] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0134] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence measure allows the system to make further decisions regarding which detections should be considered positive detections rather than false detections. In at least one embodiment, the system may set a threshold for confidence and consider only detections above the threshold to be positive detections. In embodiments where automatic emergency braking (“AEB”) is used, a false detection may cause the vehicle to automatically apply the emergency brakes, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from an IMU sensor 1366 correlated with the orientation of the vehicle 1300, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 1364 or a RADAR sensor 1360), among others.

[0135] In at least one embodiment, one or more of the SoCs 1304 may include a data store 1316 (e.g., memory). In at least one embodiment, the data store 1316 may be on-chip memory of the SoC 1304, which may store neural networks running on the GPU 1308 and / or DLA. In at least one embodiment, the capacity of the data store 1316 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1316 may comprise an L2 or L3 cache.

[0136] In at least one embodiment, one or more of the SoCs 1304 may include any number of processors 1310 (e.g., embedded processors). In at least one embodiment, the processors 1310 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and related security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1304 and may provide run-time power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 1304, and / or manage the power state of the SoC 1304. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1304 may use the ring oscillator to detect the temperature of the CPU 1306, the GPU 1308, and / or the accelerator 1314. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 1304 in a low power state, and / or place the vehicle 1300 in a driver-safety shutdown mode (e.g., bring the vehicle 1300 to a safety shutdown).

[0137] In at least one embodiment, processor 1310 may further include a set of embedded processors that can act as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that includes a digital signal processor with dedicated RAM.

[0138] In at least one embodiment, processor 1310 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0139] In at least one embodiment, the processor 1310 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operation. In at least one embodiment, the processor 1310 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to handling real-time camera management. In at least one embodiment, the processor 1310 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0140] In at least one embodiment, processor 1310 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 1370, surrounding camera 1374, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 1304 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, without limitation, activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0141] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0142] In at least one embodiment, the video image combiner may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image combiner may also be used to combine user interfaces when the operating system desktop is in use, eliminating the need for the GPU 1308 to continually render new surfaces. In at least one embodiment, the video image combiner may be used to offload the GPU 1308 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0143] In at least one embodiment, one or more of the SoCs 1304 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1304 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0144] In at least one embodiment, one or more of the SoCs 1304 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. In at least one embodiment, the SoC 1304 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and an Ethernet channel), data from sensors (e.g., a LIDAR sensor 1364, a RADAR sensor 1360, etc., which may be connected via an Ethernet channel), data from the bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), data from a GNSS sensor 1358 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1304 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 1306.

[0145] In at least one embodiment, the SoC 1304 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC 1304 is faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 1314, when combined with the CPU 1306, GPU 1308, and data store 1316, can provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0146] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language such as C to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0147] Embodiments described herein may enable multiple neural networks to run simultaneously and / or sequentially, with the results combined to enable Levels 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN running on the DLA or a separate GPU (e.g., GPU1320) may include text and word recognition to enable the neural network to read and understand traffic signs, including signs for which it was not specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0148] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Indicates Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Indicates Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 1308.

[0149] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from a camera sensor to identify the presence of an authorized driver and / or owner of vehicle 1300. In at least one embodiment, an always-on sensor processing engine may be used to unlock a vehicle and turn on lights when an owner approaches the driver's door, and to disable such vehicle in security mode when the owner leaves such vehicle. In this way, SoC 1304 provides security against theft and / or carjacking.

[0150] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1396 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1304 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1358. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when operating in North America, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program to execute an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 1362 until the emergency vehicle has passed.

[0151] In at least one embodiment, vehicle 1300 may include a CPU 1318 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 1304 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 1318 may include, for example, an X86 processor. CPU 1318 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 1304 and / or monitoring the status and health of controller 1336 and / or infotainment system on a chip (“infotainment SoC”) 1330.

[0152] In at least one embodiment, vehicle 1300 may include GPU 1320 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 1304 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU 1320 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1300.

[0153] In at least one embodiment, vehicle 1300 may further include a network interface 1324, which may include, without limitation, a wireless antenna 1326 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1324 may be used to enable wireless connections to Internet cloud services (e.g., servers and / or other network devices) with other vehicles and / or computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1300 and the other vehicles and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1300 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1300). In at least one embodiment, these aforementioned features may be part of a cooperative adaptive cruise control feature of the vehicle 1300.

[0154] In at least one embodiment, network interface 1324 may include an SoC that provides modulation and demodulation functionality and enables controller 1336 to communicate over a wireless network. In at least one embodiment, network interface 1324 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, radio frequency front-end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0155] In at least one embodiment, vehicle 1300 may further include a data store 1328, which may include, without limitation, off-chip (e.g., not on SoC 1304) storage. In at least one embodiment, data store 1328 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0156] In at least one embodiment, vehicle 1300 may further include GNSS sensors 1358 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1358 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0157] In at least one embodiment, vehicle 1300 may further include a RADAR sensor 1360. In at least one embodiment, RADAR sensor 1360 may be used by vehicle 1300 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, RADAR sensor 1360 may use a CAN bus and / or bus 1302 for control (e.g., to transmit data generated by RADAR sensor 1360) and to access object tracking data, and in some examples, may have access to an Ethernet channel to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 1360 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 1360 are pulse-Doppler RADAR sensors.

[0158] In at least one embodiment, the RADAR sensor 1360 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 m (meter) range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1360 may help distinguish between static and moving objects and may be used by the ADAS system 1338 to provide emergency braking assistance and forward collision warning. In at least one embodiment, the sensors 1360 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1300 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting vehicle 1300's lane.

[0159] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1360 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1338 to provide blind spot detection and / or lane change assistance.

[0160] In at least one embodiment, vehicle 1300 may further include ultrasonic sensors 1362. In at least one embodiment, ultrasonic sensors 1362 may be located at the front, rear, and / or sides of vehicle 1300 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1362 may be used, and different ultrasonic sensors 1362 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 1362 may operate at functional safety level ASIL B.

[0161] In at least one embodiment, vehicle 1300 may include a LIDAR sensor 1364. In at least one embodiment, LIDAR sensor 1364 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor 1364 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1300 may include multiple LIDAR sensors 1364 (e.g., two, four, six, etc.), which may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0162] In at least one embodiment, the LIDAR sensor 1364 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1364 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor 1364 may include a small device that can be integrated into the front, rear, side, and / or corner positions of the vehicle 1300. In at least one embodiment, the LIDAR sensor 1364 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1364 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0163] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. In at least one embodiment, the 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1300 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1300 to the object. In at least one embodiment, the flash LIDAR allows a highly accurate, undistorted image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 1300. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0164] In at least one embodiment, vehicle 1300 may further include an IMU sensor 1366. In at least one embodiment, IMU sensor 1366 may be positioned at the center of the rear axle of vehicle 1300. In at least one embodiment, IMU sensor 1366 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, multiple magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, IMU sensor 1366 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, IMU sensor 1366 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0165] In at least one embodiment, the IMU sensor 1366 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1366 enables the vehicle 1300 to estimate its heading by directly observing velocity changes and correlating them from the GPS to the IMU sensor 1366 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 1366 and the GNSS sensor 1358 may be combined into a single integrated unit.

[0166] In at least one embodiment, vehicle 1300 may include microphones 1396 located in and / or around vehicle 1300. In at least one embodiment, microphones 1396 may be used for, among other things, detection and identification of emergency vehicles.

[0167] In at least one embodiment, vehicle 1300 may further include any number of camera types, including stereo cameras 1368, wide-angle cameras 1370, infrared cameras 1372, perimeter cameras 1374, long-range cameras 1398, mid-range cameras 1376, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of vehicle 1300. In at least one embodiment, the types of cameras used vary depending on vehicle 1300. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1300. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1300 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be as described in further detail herein above with respect to Figures 13A and 13B.

[0168] In at least one embodiment, vehicle 1300 may further include a vibration sensor 1342. In at least one embodiment, vibration sensor 1342 may measure vibration of a component of vehicle 1300, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 1342 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0169] In at least one embodiment, vehicle 1300 may include an ADAS system 1338. In at least one embodiment, ADAS system 1338 may include, in some examples, without limitation, an SoC. In at least one embodiment, the ADAS systems 1338 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0170] In at least one embodiment, the ACC system may use a RADAR sensor 1360, a LIDAR sensor 1364, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle directly in front of the vehicle 1300 and automatically adjusts the speed of the vehicle 1300 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 1300 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0171] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by network interface 1324 and / or wireless antenna 1326 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, V2V communication provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of vehicle 1300 and in the same lane), while I2V communication provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 1300 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0172] In at least one embodiment, the FCW system is designed to alert drivers to hazards so that they can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0173] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0174] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 1300 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering input or brake control to correct the vehicle 1300 if the vehicle 1300 begins to drift out of its lane.

[0175] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 1360 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0176] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1300. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components.

[0177] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1300 itself determines whether to follow the results from a primary computer (e.g., a first controller of the controller 1336) or a secondary computer (e.g., a second controller of the controller 1336). For example, in at least one embodiment, the ADAS system 1338 may be a backup and / or secondary computer for transmitting perceptual information to a rationality module of the backup computer. In at least one embodiment, a rationality monitor of the backup computer may run redundant software on various hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 1338 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0178] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0179] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary computer and the secondary computer. In at least one embodiment, the neural network of the monitoring MCU may learn when the output of the secondary computer may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the neural network of the monitoring MCU may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the neural network of the monitoring MCU may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC 1304.

[0180] In at least one embodiment, the ADAS system 1338 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides overall consistent results, the supervisory MCU may have greater confidence that the overall results are correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0181] In at least one embodiment, the output of the ADAS system 1338 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1338 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained, as described herein, thus reducing the risk of false positives.

[0182] In at least one embodiment, vehicle 1300 may further include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 1330 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 1330 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, rear park assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 1300. For example, infotainment SoC 1330 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 1334, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1330 may also be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1300, such as information from ADAS system 1338, autonomous driving information such as vehicle maneuver plans and trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0183] In at least one embodiment, infotainment SoC 1330 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1330 may communicate with other devices, systems, and / or components of vehicle 1300 via bus 1302. In at least one embodiment, infotainment SoC 1330 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 1336 (e.g., vehicle 1300's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1330 may place vehicle 1300 in a driver-safety shutdown mode, as described herein.

[0184] In at least one embodiment, vehicle 1300 may further include an instrument cluster 1332 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1332 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 1332 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1330 and instrument cluster 1332. In at least one embodiment, instrument cluster 1332 may be included as part of infotainment SoC 1330, or vice versa.

[0185] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the system of Figure 13C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0186] 13D is a diagram of a system 1376 for communicating between a cloud-based server and the autonomous vehicle 1300 of FIG. 13A , according to at least one embodiment. In at least one embodiment, the system 1376 may include any number and type of vehicles, including, without limitation, a server 1378, a network 1390, and the vehicle 1300. In at least one embodiment, the server 1378 may include, without limitation, multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPUs 1384), PCIe switches 1382(A)-1382(D) (collectively referred to herein as PCIe switches 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPUs 1380). In at least one embodiment, the GPUs 1384, CPUs 1380, and PCIe switches 1382 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 1388 developed by NVIDIA, and / or a PCIe connection 1386. In at least one embodiment, the GPUs 1384 are connected to each other via an NVLink and / or NVS switch SoC, and the GPUs 1384 and PCIe switches 1382 are connected via a PCIe interconnect. While eight GPUs 1384, two CPUs 1380, and four PCIe switches 1382 are illustrated, this is not intended to be limiting. In at least one embodiment, each of the servers 1378 may include any number of GPUs 1384, CPUs 1380, and / or PCIe switches 1382 in any combination, without limitation. For example, in at least one embodiment, the servers 1378 may each include 8, 16, 32, and / or more GPUs 1384.

[0187] In at least one embodiment, server 1378 may receive image data from a vehicle over network 1390 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1378 may transmit updated or unupdated neural network 1392 and / or map information 1394, including, without limitation, information about traffic and road conditions, to the vehicle over network 1390. In at least one embodiment, updates to map information 1394 may include, without limitation, updates to HD map 1322, such as information about construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 1392 and / or map information 1394 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1378 and / or other servers).

[0188] In at least one embodiment, server 1378 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 1390) and / or used by server 1378 to remotely monitor the vehicle.

[0189] In at least one embodiment, server 1378 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 1378 may include a deep learning supercomputer and / or dedicated AI computer powered by a GPU 1384, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1378 may also include a deep learning infrastructure using a CPU-powered data center.

[0190] In at least one embodiment, the deep learning infrastructure of server 1378 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1300. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1300, such as a series of images and / or objects that vehicle 1300 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 1300; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1300 has failed, server 1378 may send a signal to vehicle 1300 instructing the fail-safe computer of vehicle 1300 to take control, notify the occupants, and complete a safe stopping maneuver.

[0191] In at least one embodiment, server 1378 may include a GPU 1384 and one or more programmable inference accelerators (e.g., NVIDIA TensorRT3 devices). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 1015 is used to execute one or more embodiments. Details regarding hardware structure 1015 are provided herein in conjunction with FIG. 10A and / or FIG. 10B.

[0192] Computer Systems 14 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof, formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1400 may include components such as, without limitation, processor 1402 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1400 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1400 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0193] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0194] In at least one embodiment, computer system 1400 may include, without limitation, a processor 1402, which may include one or more execution units 1408 for performing training and / or inference of machine learning models according to the techniques described herein. In at least one embodiment, computer system 1400 is a single-processor desktop or server system, while in other embodiments, computer system 1400 may be a multiprocessor system. In at least one embodiment, processor 1402 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1402 may be coupled to a processor bus 1410, which may transmit digital signals between processor 1402 and other components within computer system 1400.

[0195] In at least one embodiment, processor 1402 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1402. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1406 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0196] In at least one embodiment, processor 1402 also includes an execution unit 1408, including, without limitation, logic for performing integer and floating-point operations. In at least one embodiment, processor 1402 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1408 may include logic for a packed instruction set 1409. In at least one embodiment, including packed instruction set 1409, along with associated circuitry for executing the instructions, in a general-purpose processor's instruction set allows operations used by many multimedia applications to be performed using packed data in processor 1402. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0197] In at least one embodiment, execution unit 1408 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1400 may include, without limitation, memory 1420. In at least one embodiment, memory 1420 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that may be executed by processor 1402.

[0198] In at least one embodiment, a system logic chip may be coupled to the processor bus 1410 and the memory 1420. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1416, and the processor 1402 may communicate with the MCH 1416 via the processor bus 1410. In at least one embodiment, the MCH 1416 may provide a high-bandwidth memory path 1418 to the memory 1420 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1416 may route data signals between the processor 1402, the memory 1420, and other components of the computer system 1400, and may bridge data signals between the processor bus 1410, the memory 1420, and the system I / O interface 1422. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1416 may be coupled to memory 1420 via a high-bandwidth memory path 1418, and the graphics / video card 1412 may be coupled to the MCH 1416 via an Accelerated Graphics Port (“AGP”) interconnect 1414.

[0199] In at least one embodiment, computer system 1400 may use system I / O interface 1422 as a proprietary hub interface bus to couple MCH 1416 to I / O controller hub (“ICH”) 1430. In at least one embodiment, ICH 1430 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1420, a chipset, and processor 1402. Examples may include, without limitation, an audio controller 1429, a firmware hub ("flash BIOS") 1428, a wireless transceiver 1426, data storage 1424, a legacy I / O controller 1423 including a user input and keyboard interface 1425, a serial expansion port 1427 such as a Universal Serial Bus ("USB") port, and a network controller 1434. In at least one embodiment, data storage 1424 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0200] In at least one embodiment, Figure 14 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 14 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Figure 14 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1400 may be interconnected using a compute express link (CXL) interconnect.

[0201] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the system of Figure 14 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0202] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above, hi at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein.

[0203] 15 is a block diagram illustrating an electronic device 1500 for utilizing a processor 1510, according to at least one embodiment. In at least one embodiment, electronic device 1500 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0204] In at least one embodiment, electronic device 1500 may include, without limitation, a processor 1510 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2The devices may be coupled using a bus or interface such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 15 illustrates a system including interconnected hardware devices or “chips,” while in other embodiments, FIG. 15 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 15 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 15 may be interconnected using a Compute Express Link (CXL) interconnect.

[0205] In at least one embodiment, FIG. 15 illustrates a display 1524, a touch screen 1525, a touch pad 1530, a Near Field Communications unit ("NFC") 1545, a sensor hub 1540, a thermal sensor 1546, an Express Chipset ("EC") 1535, a Trusted Platform Module ("TPM") 1538, a BIOS / firmware / flash memory ("BIOS,FW flash") 1522, a DSP 1560, a drive 1520, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") 1550, a Bluetooth unit 1552, a wireless wide area network unit ("WWAN") 1554, a Bluetooth module 1554, a wireless local area network unit ("WLAN") 1556, a Bluetooth module 1558, a wireless wide area network unit ("WWAN") 1558, a Bluetooth module 1558, a Bluetooth module 1559, a Bluetooth module 1560, a Bluetooth module 1561, a Bluetooth module 1562, a Bluetooth module 1563, a Bluetooth module 1564, a Bluetooth module 1565, a Bluetooth module 1566, a Bluetooth module 1567, a Bluetooth module 1568, a Bluetooth module 1569, a Bluetooth module 1570, a Bluetooth module 1571, a Bluetooth module 1572, a Bluetooth module 1573, a Bluetooth module 1574, a Bluetooth module 1575, a Bluetooth module 1576, a Bluetooth module 1578, a Bluetooth module 1579, a Bluetooth module 1580, a Bluetooth module 1581, a Bluetooth module 1582, a Bluetooth module 1583, a Bluetooth module 1584, a Bluetooth module 1585, a Bluetooth module 1586 The memory may include a memory controller (RAM) 1556, a Global Positioning System (GPS) unit 1555, a camera such as a USB 3.0 camera ("USB 3.0 camera") 1554, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1515, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0206] In at least one embodiment, other components may be communicatively coupled to the processor 1510 via the components described above. In at least one embodiment, an accelerometer 1541, an ambient light sensor (“ALS”) 1542, a compass 1543, and a gyroscope 1544 may be communicatively coupled to the sensor hub 1540. In at least one embodiment, a thermal sensor 1539, a fan 1537, a keyboard 1536, and a touchpad 1530 may be communicatively coupled to the EC 1535. In at least one embodiment, a speaker 1563, headphones 1564, and a microphone (“mic”) 1565 may be communicatively coupled to an audio unit (audio codec and class D amplifier) ​​1562, which may be communicatively coupled to the DSP 1560. In at least one embodiment, the audio unit 1562 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1557 may be communicatively coupled to the WWAN unit 1556. In at least one embodiment, components such as the WLAN unit 1550 and Bluetooth unit 1552, and the WWAN 1556 may be implemented in a Next Generation Form Factor (“NGFF”).

[0207] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the system of Figure 15 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0208] In at least one embodiment, a system for determining a grasp pose can be constructed using a computer system as shown and described above, in at least one embodiment, a processor of the computer system executes executable instructions that cause the computer system to determine and refine a grasp pose as described herein.

[0209] 16 illustrates, according to at least one embodiment, a computer system 1600. In at least one embodiment, the computer system 1600 is configured to implement the various processes and methods described throughout this disclosure.

[0210] In at least one embodiment, computer system 1600 includes at least one central processing unit ("CPU") 1602 connected to a communication bus 1610 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1600 includes main memory 1604 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1604, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1622 provides an interface with other computing devices and networks for receiving data from other systems comprising computer system 1600 and transmitting data to other systems comprising computer system 1600.

[0211] In at least one embodiment, computer system 1600 includes, without limitation, input device(s) 1608, a parallel processing system 1612, and a display device 1606, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light emitting diode ("LED") display, a plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1608, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0212] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the training logic 1015 may be used in the system of Figure 16 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0213] In at least one embodiment, a system for determining a grip pose can be constructed using a computer system as shown and described above. In at least one embodiment, a processor of the computer system executes executable instructions that cause the processor to determine and refine a grip pose as described herein. In at least one embodiment, the executable instructions may be stored on a USB stick, as described above.

[0214] 17 illustrates a computer system 1700 according to at least one embodiment. In at least one embodiment, computer system 1700 may include, without limitation, a computer 1710 and a USB stick 1720. In at least one embodiment, computer system 1710 may include, without limitation, any number and type of processor (not shown) and memory. In at least one embodiment, computer 1710 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0215] In at least one embodiment, USB stick 1720 includes, without limitation, a processing unit 1730, a USB interface 1740, and USB interface logic 1750. In at least one embodiment, processing unit 1730 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1730 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1730 comprises an application specific integrated circuit (“ASIC”) optimized to perform any quantity and type of operations related to machine learning. For example, in at least one embodiment, processing unit 1730 is a tensor processing unit (“TPC”) optimized to perform machine vision and machine learning inference operations. In at least one embodiment, processing unit 1730 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0216] In at least one embodiment, USB interface 1740 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1740 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1740 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1750 may include any amount and type of logic that enables processing unit 1730 to interface with a device (e.g., computer 1710) via USB connector 1740.

[0217] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the system of Figure 17 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0218] In at least one embodiment, a system for determining a grip pose can be constructed using a computer system as shown and described above. In at least one embodiment, a processor of the computer system executes executable instructions that cause the processor to determine and refine a grip pose as described herein. In at least one embodiment, the executable instructions may be stored on a USB stick, as described above.

[0219] FIG. 18A illustrates an exemplary architecture in which multiple GPUs 1810(1)-1810(N) are communicatively coupled to multiple multi-core processors 1805(1)-1805(M) via high-speed links 1840(1)-1840(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1840(1)-1840(N) support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or more. Various interconnect protocols may be used with 1840(1)-1840(N), including, but not limited to, PCIe 4.0 or 5.0, and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure.

[0220] Additionally, in at least one embodiment, two or more of the GPUs 1810 are interconnected via high-speed links 1829(1)-1829(2), which may be implemented using similar or different protocols / links as used for high-speed links 1840(1)-1840(N). Similarly, two or more of the multi-core processors 1805 may be connected via high-speed link 1828, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 18A may be achieved using similar protocols / links (e.g., via a common interconnect fabric).

[0221] In at least one embodiment, each multi-core processor 1805 is communicatively coupled to processor memory 1801(1)-1801(M) via memory interconnect 1826(1)-1826(M), respectively, and each GPU 1810(1)-1810(N) is communicatively coupled to GPU memory 1820(1)-1820(N) via GPU memory interconnect 1850(1)-1850(N), respectively. In at least one embodiment, memory interconnects 1826 and 1850 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memory 1801(1)-1801(M) and GPU memory 1820 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of processor memory 1801 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0222] As described herein, various multi-core processors 1805 and GPUs 1810 may each be physically coupled to specific memories 1801, 1820, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among various physical memories. For example, processor memories 1801(1) through 1801(M) may each have 64 GB of system memory address space, and GPU memories 1820(1) through 1820(N) may each have 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values ​​for N and M are contemplated.

[0223] 18B shows further details of the interconnection between multi-core processor 1807 and graphics acceleration module 1846 according to one example embodiment. In at least one embodiment, graphics acceleration module 1846 may include one or more GPU chips integrated on a line card that is coupled to processor 1807 via a high-speed link 1840 (e.g., a PCIe bus, an NVLink, etc.). Alternatively, in at least one embodiment, graphics acceleration module 1846 may be integrated into the package or chip that includes processor 1807.

[0224] In at least one embodiment, the processor 1807 includes multiple cores 1860A-1860D, each having a translation lookaside buffer (“TLB”) 1861A-1861D and one or more caches 1862A-1862D. In at least one embodiment, the cores 1860A-1860D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1862A-1862D may comprise level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1856 may be included in the caches 1862A-1862D and shared by the set of cores 1860A-1860D. For example, one embodiment of the processor 1807 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1807 and graphics acceleration module 1846 are coupled to system memory 1814, which may include processor memories 1801(1) through 1801(M) of FIG. 18A.

[0225] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1862A-1862D, 1856, and system memory 1814 through inter-core communication via a coherence bus 1864. In at least one embodiment, for example, each cache may have associated cache coherence logic / circuitry for communicating via the coherence bus 1864 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the coherence bus 1864 to monitor cache accesses.

[0226] In at least one embodiment, proxy circuit 1825 communicatively couples graphics acceleration module 1846 to coherence bus 1864 to enable graphics acceleration module 1846 to participate in cache coherence protocols as a peer of cores 1860A-1860D. In particular, in at least one embodiment, interface 1835 provides a connection to proxy circuit 1825 via high-speed link 1840, and interface 1837 connects graphics acceleration module 1846 to high-speed link 1840.

[0227] In at least one embodiment, the accelerator integrated circuit 1836 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 1831(1)-1831(N) of the graphics acceleration module 1846. In at least one embodiment, the graphics processing engines 1831(1)-1831(N) may each comprise a separate graphics processing unit (GPU). Alternatively, in at least one embodiment, the graphics processing engines 1831(1)-1831(N) may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, graphics acceleration module 1846 may be a GPU having multiple graphics processing engines 1831(1)-1831(N), or the graphics processing engines 1831(1)-1831(N) may be individual GPUs integrated into a common package, line card, or chip.

[0228] In at least one embodiment, accelerator integrated circuitry 1836 includes a memory management unit (MMU) 1839 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1814. In at least one embodiment, MMU 1839 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1838 may store commands and data for efficient access by graphics processing engines 1831(1)-1831(N). In at least one embodiment, data stored in cache 1838 and graphics memory 1833(1)-1833(M) is kept coherent with core caches 1862A-1862D, 1856, and system memory 1814, possibly using fetch unit 1844. As noted, this may be accomplished via proxy circuitry 1825 (e.g., sending updates to cache 1838 regarding modifications / accesses of cache lines in processor caches 1862A-1862D, 1856, and receiving updates from cache 1838) on behalf of cache 1838 and memory 1833(1)-1833(M).

[0229] In at least one embodiment, a set of registers 1845 stores context data for threads executed by the graphics processing engines 1831(1)-1831(N), and a context management circuit 1848 manages thread contexts. For example, the context management circuit 1848 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1848 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 1848 may restore the register values. In at least one embodiment, the interrupt management circuit 1847 receives and processes interrupts received from system devices.

[0230] In at least one embodiment, virtual / effective addresses from the graphics processing engine 1831 are translated to real / physical addresses in the system memory 1814 by the MMU 1839. In at least one embodiment, one embodiment of the accelerator integrated circuit 1836 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1846 and / or other accelerator devices. In at least one embodiment, the graphics accelerator modules 1846 may be dedicated to a single application executing on the processor 1807 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1831(1)-1831(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into “slices,” which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0231] In at least one embodiment, the accelerator integrated circuitry 1836 acts as a bridge to the system for the graphics acceleration module 1846 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuitry 1836 may provide a virtualization facility for a host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1831(1)-1831(N).

[0232] In at least one embodiment, the hardware resources of graphics processing engines 1831(1)-1831(N) are explicitly mapped into the real address space seen by host processor 1807, allowing any host processor to directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1836 is to physically separate graphics processing engines 1831(1)-1831(N) so that they appear to the system as independent units.

[0233] In at least one embodiment, one or more graphics memories 1833(1) through 1833(M) are each coupled to a respective one of the graphics processing engines 1831(1) through 1831(N), where N = M. In at least one embodiment, the graphics memories 1833(1) through 1833(M) store instructions and data to be processed by the respective graphics processing engines 1831(1) through 1831(N). In at least one embodiment, the graphics memories 1833(1) through 1833(M) may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0234] In at least one embodiment, to reduce data traffic over high-speed link 1840, biasing techniques may be used to ensure that the data stored in graphics memory 1833(1)-1833(M) is data that will be most frequently used by graphics processing engines 1831(1)-1831(N), and preferably is data that is not used (or at least not frequently used) by cores 1860A-1860D. Similarly, in at least one embodiment, biasing mechanisms attempt to keep data needed by the cores (and thus preferably not needed by graphics processing engines 1831(1)-1831(N)) in the cores' caches 1862A-1862D, 1856, and system memory 1814.

[0235] 18C shows another exemplary embodiment in which accelerator integration circuitry 1836 is integrated within processor 1807. In at least this embodiment, graphics processing engines 1831(1)-1831(N) communicate directly with accelerator integration circuitry 1836 via high-speed link 1840 (which again may be any form of bus or interface protocol) via interface 1837 and interface 1835. In at least one embodiment, accelerator integration circuitry 1836 may perform operations similar to those described with respect to FIG. 18B, but may potentially operate at a higher throughput given its proximity to coherence bus 1864 and caches 1862A-1862D, 1856. In at least one embodiment, the accelerator integrated circuitry supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuitry 1836 and a programming model controlled by the graphics acceleration module 1846.

[0236] In at least one embodiment, graphics processing engines 1831(1)-1831(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1831(1)-1831(N) to achieve virtualization within a VM / partition.

[0237] In at least one embodiment, graphics processing engines 1831(1)-1831(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1831(1)-1831(N) to allow access by each operating system. In at least one embodiment, in a single-partition system without a hypervisor, graphics processing engines 1831(1)-1831(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1831(1)-1831(N) to provide access to each process or application.

[0238] In at least one embodiment, the graphics acceleration module 1846 or an individual graphics processing engine 1831(1)-1831(N) selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1814 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engine 1831(1)-1831(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0239] FIG. 18D illustrates an exemplary accelerator integration slice 1890. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of accelerator integration circuitry 1836. In at least one embodiment, application effective address space 1882 in system memory 1814 stores process elements 1883. In at least one embodiment, process elements 1883 are stored in response to GPU calls 1881 from applications 1880 executing on processor 1807. In at least one embodiment, process elements 1883 contain the process state of the corresponding applications 1880. In at least one embodiment, work descriptors (WDs) 1884 contained in process elements 1883 can be single jobs requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WDs 1884 are pointers to a job request queue in the application's effective address space 1882.

[0240] In at least one embodiment, graphics acceleration module 1846 and / or individual graphics processing engines 1831(1)-1831(N) may be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD 1884 to graphics acceleration module 1846 to start a job in a virtualized environment.

[0241] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1846 or an individual graphics processing engine 1831. In at least one embodiment, when the graphics acceleration module 1846 is owned by a single process, the hypervisor initializes the accelerator integration circuitry 1836 for the owning partition when the graphics acceleration module 1846 is allocated, and the operating system initializes the accelerator integration circuitry 1836 for the owning process.

[0242] In at least one embodiment, during operation, a WD fetch unit 1891 in the accelerator integrated slice 1890 fetches the next WD 1884, which contains an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module. In at least one embodiment, as shown, data from the WD 1884 may be stored in registers 1845 and used by the MMU 1839, the interrupt management circuit 1847, and / or the context management circuit 1848. For example, one embodiment of the MMU 1839 includes segment / page walk circuitry for accessing a segment / page table 1886 within the OS virtual address space 1885. In at least one embodiment, the interrupt management circuit 1847 may process interrupt events 1892 received from the graphics acceleration module 1846. In at least one embodiment, when performing graphics operations, effective addresses 1893 generated by the graphics processing engines 1831(1)-1831(N) are translated into real addresses by the MMU 1839.

[0243] In at least one embodiment, registers 1845 may be replicated for each graphics processing engine 1831(1)-1831(N) and / or graphics acceleration module 1846 and initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in accelerator integration slice 1890. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. [Table 1]

[0244] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0245] In at least one embodiment, each WD 1884 is specific to a particular graphics acceleration module 1846 and / or graphics processing engine 1831(1)-1831(N). In at least one embodiment, WD 1884 may contain all the information that graphics processing engine 1831(1)-1831(N) needs to do its work, or may be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0246] 18E shows further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1898 in which a process element list 1899 is stored. In at least one embodiment, the hypervisor real address space 1898 is accessible through a hypervisor 1896 that virtualizes the graphics acceleration module engine of the operating system 1895.

[0247] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1846. In at least one embodiment, there are two programming models in which the graphics acceleration module 1846 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0248] In at least one embodiment, in this model, the system hypervisor 1896 owns the graphics acceleration module 1846 and makes its functionality available to all operating systems 1895. In at least one embodiment, in order for the graphics acceleration module 1846 to support virtualization by the system hypervisor 1896, the graphics acceleration module 1846 may comply with several requirements, such as: 1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs) or the graphics acceleration module 1846 must provide a mechanism for saving and restoring context, 2) the application's job requests must be guaranteed by the graphics acceleration module 1846 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 1846 must provide the ability to preempt the processing of jobs, and 3) the graphics acceleration module 1846 must ensure fairness between processes when operating in a specified shared programming model.

[0249] In at least one embodiment, the application 1880 must make a system call to the operating system 1895 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1846 and may be in the form of graphics acceleration module 1846 commands, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by the graphics acceleration module 1846.

[0250] In at least one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1836 (not shown) and the graphics acceleration module 1846 does not support a User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. In at least one embodiment, the hypervisor 1896 may optionally apply the current Authorization Mask Override Register (AMOR) value before placing the AMR in the process element 1883. In at least one embodiment, the CSRP is one of the registers 1845 that contains the effective address of an area in the application's effective address space 1882 for the graphics acceleration module 1846 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0251] Upon receiving the system call, the operating system 1895 may verify that the application 1880 is registered and authorized to use the graphics acceleration module 1846. In at least one embodiment, the operating system 1895 then calls the hypervisor 1896 with the information shown in Table 3. [Table 3]

[0252] In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1896 verifies that the operating system 1895 is registered and authorized to use the graphics acceleration module 1846. In at least one embodiment, the hypervisor 1896 then places the process element 1883 into a process element linked list of the corresponding graphics acceleration module 1846 type. In at least one embodiment, the process element may include the information shown in Table 4. [Table 4]

[0253] In at least one embodiment, the hypervisor initializes registers 1845 of multiple accelerator integrated slices 1890.

[0254] As shown in FIG. 18F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memory 1801(1)-1801(N) and GPU memory 1820(1)-1820(N). In this implementation, operations performed on GPUs 1810(1)-1810(N) utilize the same virtual / effective memory address space as those used to access processor memory 1801(1)-1801(N), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1801(1), a second portion is allocated to second processor memory 1801(N), a third portion is allocated to GPU memory 1820(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memory 1801 and GPU memory 1820, allowing either processor or GPU to access either physical memory, with virtual addresses mapped to physical memory.

[0255] In at least one embodiment, bias / coherence management circuits 1894A-1894E in one or more of the MMUs 1839A-1839E ensure cache coherence between the caches of one or more host processors (e.g., 1805) and the caches of the GPU 1810 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, multiple instances of bias / coherence management circuits 1894A-1894E are shown in FIG. 18F, although the bias / coherence circuits may be implemented within the MMUs of one or more host processors 1805 and / or within the accelerator integration circuit 1836.

[0256] One embodiment enables GPU memory 1820 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, having GPU memory 1820 accessible as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this configuration enables host processor 1805 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access GPU memory 1820 without cache coherence overhead can be essential to the execution time of offloaded computations. In at least one embodiment, for example, in cases where there is significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1810. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can be useful in determining the effectiveness of GPU offloading.

[0257] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (e.g., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1820, with or without a bias cache in the GPU 1810 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the bias table may be maintained entirely within the GPU.

[0258] In at least one embodiment, a bias table entry associated with each access to GPU-biased memory 1820 is accessed prior to the actual access to the GPU memory, resulting in the following actions: In at least one embodiment, a local request from the GPU 1810 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1820. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to the processor 1805 (e.g., via the high-speed link described above). In at least one embodiment, a request from the processor 1805 to find the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 1810. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, simply a hardware-based mechanism.

[0259] In at least one embodiment, one mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1805 bias to GPU bias, but not for transitions in the opposite direction.

[0260] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 1805. In at least one embodiment, to access these pages, the processor 1805 may request access from the GPU 1810, which may or may not immediately grant the access. Thus, in at least one embodiment, to reduce communication between the processor 1805 and the GPU 1810, it is beneficial for GPU-biased pages to be requested by the GPU but not by the host processor 1805, or vice versa.

[0261] To implement one or more embodiments, a hardware structure 1015 is used, details regarding the hardware structure 1015 may be provided herein in conjunction with Figures 10A and / or 10B.

[0262] 19 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0263] 19 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1900 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1900 includes one or more application processors 1905 (e.g., CPUs), at least one graphics processor 1910, and may further include an image processor 1915 and / or a video processor 1920, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1900 includes a USB controller 1925, a UART controller 1930, an SPI / SDIO controller 1935, and an I / O controller 1940. 2 2S / I 2 The integrated circuit 1900 may include peripheral or bus logic including a HDMI™ controller 1940. In at least one embodiment, the integrated circuit 1900 may include a display device 1945 coupled to one or more of a High-Definition Multimedia Interface (HDMI™) controller 1950 and a Mobile Industry Processor Interface (MIPI) display interface 1955. In at least one embodiment, storage may be provided by a flash memory subsystem 1960 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1965 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 1970.

[0264] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the integrated circuit 1900 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0265] In at least one embodiment, a system for determining a grasp pose can be implemented using a processor as shown and described above. In at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein. In at least one embodiment, the processor is a graphics processor, GPU, video processor, or application processor as described herein.

[0266] 20A-20B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0267] 20A and 20B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 20A illustrates an exemplary graphics processor 2010 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. FIG. 20B illustrates a further exemplary graphics processor 2040 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 2010 of FIG. 20A is a low-power graphics processor core. In at least one embodiment, the graphics processor 2040 of FIG. 20B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 2010, 2040 can be a variation of the graphics processor 1910 of FIG. 19.

[0268] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D-2015N-1, and 2015N). In at least one embodiment, the graphics processor 2010 can execute different shader programs through separate logic, such that the vertex processor 2005 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2005 executes the vertex processing stage of a 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processors 2015A-2015N generate a frame buffer that is displayed on a display device using the primitive and vertex data generated by the vertex processor 2005. In at least one embodiment, the fragment processors 2015A-2015N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0269] In at least one embodiment, the graphics processor 2010 further includes one or more memory management units (MMUs) 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B. In at least one embodiment, the one or more MMUs 2020A-2020B provide virtual-to-physical address mapping for the graphics processor 2010, including the vertex processor 2005 and / or fragment processors 2015A-2015N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 2025A-2025B. In at least one embodiment, one or more MMUs 2020A-2020B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1905, image processor 1915, and / or video processor 1920 of Figure 19, allowing each processor 1905-1920 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable the graphics processor 2010 to interface with other IP cores in the SoC via the SoC's internal bus or via a direct connection.

[0270] In at least one embodiment, as shown in FIG. 20B, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F-2055N-1, and 2055N), where a single core, or type, or cores provide a unified shader core architecture capable of executing all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 2040 includes an inter-core task manager 2045 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2055A-2055N, and a tiling unit 2058 for accelerating tiling operations for tile-based rendering, where scene rendering operations are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0271] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1015 are provided herein in conjunction with FIG. 10A and / or FIG. 10B. In at least one embodiment, inference and / or training logic 1015 may be used in integrated circuit 20A and / or 20B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0272] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above. In at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein. In at least one embodiment, the processor is a vertex processor as described herein.

[0273] 21A-21B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 21A illustrates a graphics core 2100, which, in at least one embodiment, may be included in graphics processor 1910 of Figure 19, or, in at least one embodiment, may be integrated shader cores 2055A-2055N, as in Figure 20B. Figure 21B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU") 2130 suitable for incorporation into a multi-chip module in at least one embodiment.

[0274] In at least one embodiment, graphics core 2100 includes a shared instruction cache 2102, a texture unit 2118, and a cache / shared memory 2120, which are common to execution resources within graphics core 2100. In at least one embodiment, graphics core 2100 may include multiple slices 2101A-2101N, or partitions per core, and a graphics processor may include multiple instances of graphics core 2100. In at least one embodiment, slices 2101A-2101N may include supporting logic, including local instruction caches 2104A-2104N, thread schedulers 2106A-2106N, thread dispatchers 2108A-2108N, and sets of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional functional units (AFUs 2112A-2112N), floating-point units (FPUs 2114A-2114N), integer arithmetic logic units (ALUs 2116-2116N), address calculation units (ACUs 2113A-2113N), double-precision floating-point units (DPFPUs 2115A-2115N), and matrix processing units (MPUs 2117A-2117N).

[0275] In at least one embodiment, the FPUs 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 2115A-2115N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 2117A-2117N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support general matrix-matrix multiplication (GEMM) acceleration. In at least one embodiment, the AFUs 2112A-2112N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0276] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1015 are provided herein in conjunction with FIG. 10A and / or FIG. 10B. In at least one embodiment, inference and / or training logic 1015 may be used in graphics core 2100 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0277] In at least one embodiment, a system for determining a grasp pose can be implemented using a processor as shown and described above. In at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein. In at least one embodiment, the processor is a graphics core as described herein.

[0278] FIG. 21B illustrates a general-purpose processing unit (GPGPU) 2130, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 2130 can be directly linked to other instances of the GPGPU 2130 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 2130 includes a host interface 2132 for enabling connection to a host processor. In at least one embodiment, the host interface 2132 is a PCI Express interface. In at least one embodiment, the host interface 2132 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 2130 receives commands from the host processor and, using a global scheduler 2134, distributes execution threads associated with these commands to a set of compute clusters 2136A-2136H. In at least one embodiment, the compute clusters 2136A-2136H share a cache memory 2138. In at least one embodiment, the cache memory 2138 can act as a higher level cache for the cache memories within the compute clusters 2136A-2136H.

[0279] In at least one embodiment, GPGPU 2130 includes memory 2144A-2144B coupled to compute clusters 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, memory 2144A-2144B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0280] In at least one embodiment, compute clusters 2136A-2136H each include a set of graphics cores, such as graphics core 2100 of FIG. 21A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0281] In at least one embodiment, multiple instances of GPGPU 2130 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2136A-2136H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 2130 communicate through host interface 2132. In at least one embodiment, GPGPU 2130 includes I / O hub 2139, which couples GPGPU 2130 to GPU link 2140, which enables direct connection to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2130 are located in separate data processing systems and communicate via a network device accessible via host interface 2132. In at least one embodiment, GPU link 2140 can be configured to allow connection to a host processor in addition to, or instead of, host interface 2132.

[0282] In at least one embodiment, the GPGPU 2130 can be configured to train a neural network. In at least one embodiment, the GPGPU 2130 can be used within an inference platform. In at least one embodiment, when the GPGPU 2130 is used for inference, the GPGPU 2130 may include fewer compute clusters 2136A-2136H than when the GPGPU 2130 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2144A-2144B may be different for the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2130 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0283] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the GPGPU 2130 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0284] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above. In at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein. In at least one embodiment, the processor is a GPGPU as described herein.

[0285] 22 is a block diagram illustrating a computing system 2200 according to at least one embodiment. In at least one embodiment, computing system 2200 includes a processing subsystem 2201 having one or more processors 2202 and system memory 2204 that communicate via an interconnection path that may include a memory hub 2205. In at least one embodiment, memory hub 2205 may be a separate component within a chipset component or may be integrated within one or more processors 2202. In at least one embodiment, memory hub 2205 is coupled to an I / O subsystem 2211 via a communication link 2206. In at least one embodiment, I / O subsystem 2211 includes an I / O hub 2207 that can enable computing system 2200 to receive input from one or more input devices 2208. In at least one embodiment, I / O hub 2207 can enable a display controller, which may be included in one or more processors 2202 and provide output to one or more display devices 2210A. In at least one embodiment, the one or more display devices 2210A coupled to I / O hub 2207 can include local, internal, or embedded display devices.

[0286] In at least one embodiment, the processing subsystem 2201 includes one or more parallel processors 2212 coupled to a memory hub 2205 via a bus or other communication link 2213. In at least one embodiment, the communication link 2213 may use one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, the one or more parallel processors 2212 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of the parallel processors 2212 form a graphics processing subsystem that can output pixels to one of one or more display devices 2210A coupled via the I / O hub 2207. In at least one embodiment, the parallel processor 2212 also includes a display controller and display interface (not shown) that allows for direct connection to one or more display devices 2210B.

[0287] In at least one embodiment, system storage unit 2214 may be connected to I / O hub 2207 to provide a storage mechanism for computing system 2200. In at least one embodiment, I / O switch 2216 may be used to provide an interface mechanism to enable communication between I / O hub 2207 and other components, such as network adapter 2218 and / or wireless network adapter 2219, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 2220. In at least one embodiment, network adapter 2218 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2219 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0288] In at least one embodiment, computing system 2200 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2207. In at least one embodiment, the communication paths interconnecting the various components of FIG. 22 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface, such as an NV-Link high-speed interconnect, or other interconnection protocol.

[0289] In at least one embodiment, parallel processor 2212 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, parallel processor 2212 incorporates circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 2200 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor 2212, memory hub 2205, processor 2202, and I / O hub 2207 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2200 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2200 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0290] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the system of Figure 2200 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0291] Processor 23A illustrates a parallel processor 2300 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2300 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2300 is a variation of one or more parallel processors 2212 shown in FIG. 22 according to an example embodiment.

[0292] In at least one embodiment, parallel processor 2300 includes parallel processing units 2302. In at least one embodiment, parallel processing units 2302 include I / O units 2304 that enable communication with other devices, including other instances of parallel processing units 2302. In at least one embodiment, I / O units 2304 may be directly connected to other devices. In at least one embodiment, I / O units 2304 are connected to other devices through the use of a hub or switch interface, such as memory hub 2305. In at least one embodiment, the connection between memory hub 2305 and I / O units 2304 forms communication link 2313. In at least one embodiment, I / O units 2304 are connected to host interface 2306 and memory crossbar 2316, where host interface 2306 receives commands directed to the execution of processing operations and memory crossbar 2316 receives commands directed to the execution of memory operations.

[0293] In at least one embodiment, when host interface 2306 receives command buffers via I / O unit 2304, host interface 2306 can direct work operations to front end 2308 to execute these commands. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to distribute commands or other work items to processing cluster array 2312. In at least one embodiment, scheduler 2310 ensures that processing cluster array 2312 is properly configured and in a valid state before tasks are distributed to clusters in processing cluster array 2312. In at least one embodiment, scheduler 2310 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2310 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularities, enabling rapid preemption and context switching of threads executing in processing array 2312. In at least one embodiment, host software can initiate scheduling workloads across processing cluster array 2312 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed across processing cluster array 2312 by scheduler 2310 logic within a microcontroller that includes scheduler 2310.

[0294] In at least one embodiment, processing cluster array 2312 can include up to “N” processing clusters (e.g., cluster 2314A, cluster 2314B through cluster 2314N), where “N” represents a positive integer (although “N” may be a different integer than used in other figures). In at least one embodiment, each cluster 2314A through 2314N of processing cluster array 2312 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2310 can allocate work to clusters 2314A through 2314N of processing cluster array 2312 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2310 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 2312. In at least one embodiment, different clusters 2314A-2314N of processing cluster array 2312 may be allocated to process different types of programs or perform different types of calculations.

[0295] In at least one embodiment, processing cluster array 2312 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2312 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2312 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0296] In at least one embodiment, the processing cluster array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2312 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2312 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2302 may transfer data from system memory via the I / O unit 2304 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) during processing and then written back to system memory.

[0297] In at least one embodiment, when graphics processing is performed using parallel processing unit 2302, scheduler 2310 can be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 2314A-2314N of processing cluster array 2312. In at least one embodiment, portions of processing cluster array 2312 can be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2314A-2314N may be stored in a buffer so that the intermediate data can be transmitted between clusters 2314A-2314N for further processing.

[0298] In at least one embodiment, the processing cluster array 2312 can receive processing tasks to be performed via a scheduler 2310, which receives commands defining the processing tasks from the front end 2308. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 2310 can be configured to fetch the index corresponding to the task or can receive the index from the front end 2308. In at least one embodiment, the front end 2308 can be configured to ensure that the processing cluster array 2312 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0299] In at least one embodiment, each of one or more instances of parallel processing unit 2302 can be coupled to parallel processor memory 2322. In at least one embodiment, parallel processor memory 2322 can be accessed via memory crossbar 2316, which can receive memory requests from processing cluster array 2312 as well as I / O unit 2304. In at least one embodiment, memory crossbar 2316 can access parallel processor memory 2322 via memory interface 2318. In at least one embodiment, memory interface 2318 can include multiple partition units (e.g., partition unit 2320A, partition unit 2320B through partition unit 2320N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 2322. In at least one embodiment, the number of partition units 2320A-2320N is configured to be equal to the number of memory units, such that a first partition unit 2320A has a corresponding first memory unit 2324A, a second partition unit 2320B has a corresponding memory unit 2324B, and an Nth partition unit 2320N has a corresponding Nth memory unit 2324N. In at least one embodiment, the number of partition units 2320A-2320N does not have to be equal to the number of memory devices.

[0300] In at least one embodiment, the memory units 2324A-2324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2324A-2324N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2322, render targets, such as frame buffers or texture maps, may be stored across the memory units 2324A-2324N, allowing the partition units 2320A-2320N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2322 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0301] In at least one embodiment, any one of the clusters 2314A-2314N in the processing cluster array 2312 can process data that is to be written to any one of the memory units 2324A-2324N in the parallel processor memory 2322. In at least one embodiment, the memory crossbar 2316 can be configured to forward the output of each cluster 2314A-2314N to any partition unit 2320A-2320N or to another cluster 2314A-2314N that can perform further processing operations on the output. In at least one embodiment, each cluster 2314A-2314N can communicate with a memory interface 2318 through the memory crossbar 2316 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2316 has connections to memory interface 2318 for communicating with I / O unit 2304, as well as connections to local instances of parallel processor memory 2322, allowing processing units in different processing clusters 2314A-2314N to communicate with system memory or other memory not local to parallel processing unit 2302. In at least one embodiment, memory crossbar 2316 can use virtual channels to separate traffic streams between clusters 2314A-2314N and partition units 2320A-2320N.

[0302] In at least one embodiment, multiple instances of parallel processing unit 2302 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2302 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2302 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2302 or parallel processor 2300 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0303] FIG. 23B is a block diagram of a partition unit 2320 according to at least one embodiment. In at least one embodiment, the partition unit 2320 is an instance of one of the partition units 2320A-2320N of FIG. 23A. In at least one embodiment, the partition unit 2320 includes an L2 cache 2321, a frame buffer interface 2325, and a raster operations unit (ROP) 2326. In at least one embodiment, the L2 cache 2321 is a read / write cache configured to execute load and store operations received from the memory crossbar 2316 and the ROP 2326. In at least one embodiment, read misses and urgent writeback requests are output by the L2 cache 2321 to the frame buffer interface 2325 for processing. In at least one embodiment, updates are also sent to the frame via the frame buffer interface 2325 for processing. In at least one embodiment, frame buffer interface 2325 interfaces with one of the memory units of a parallel processor memory, such as memory units 2324A-2324N (eg, in parallel processor memory 2322) of FIG.

[0304] In at least one embodiment, ROP2326 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP2326 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2326 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a number of compression algorithms. In at least one embodiment, the type of compression performed by ROP2326 may be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0305] In at least one embodiment, ROP 2326 is included within each processing cluster (e.g., clusters 2314A-2314N of FIG. 23A ) rather than within partition unit 2320. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2316. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 2210 of FIG. 22 , may be routed for further processing by processor 2202, or may be routed for further processing by one of the processing entities in parallel processor 2300 of FIG. 23A .

[0306] FIG. 23C is a block diagram of a processing cluster 2314 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 2314A-2314N of FIG. 23A. In at least one embodiment, the processing cluster 2314 may be configured to execute multiple threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0307] In at least one embodiment, operation of the processing cluster 2314 may be controlled via a pipeline manager 2332, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2332 receives instructions from the scheduler 2310 of FIG. 23A and manages the execution of those instructions via the graphics multiprocessor 2334 and / or the texture unit 2336. In at least one embodiment, the graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2314. In at least one embodiment, one or more instances of the graphics multiprocessor 2334 may be included within the processing cluster 2314. In at least one embodiment, the graphics multiprocessor 2334 may process data, and a data crossbar 2340 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2332 can facilitate distribution of processed data by specifying destinations for the processed data to be distributed through data crossbar 2340.

[0308] In at least one embodiment, each graphics multiprocessor 2334 in a processing cluster 2314 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0309] In at least one embodiment, instructions sent to a processing cluster 2314 constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread groups execute a common program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 2334. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 2334. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in the graphics multiprocessor 2334. In at least one embodiment, if a thread group includes more threads than the number of processing engines in the graphics multiprocessor 2334, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 2334.

[0310] In at least one embodiment, the graphics multiprocessor 2334 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2334 can forgo the internal cache and use cache memory (e.g., L1 cache 2348) within the processing cluster 2314. In at least one embodiment, each graphics multiprocessor 2334 can also access an L2 cache within a partition unit (e.g., partition units 2320A-2320N in FIG. 23A ), which may be shared among all processing clusters 2314 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2334 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2302 may be used as global memory. In at least one embodiment, processing cluster 2314 may include multiple instances of graphics multiprocessor 2334 and share common instructions and data, which may be stored in L1 cache 2348.

[0311] In at least one embodiment, each processing cluster 2314 may include an MMU 2345 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2345 may reside within memory interface 2318 of FIG. 23A . In at least one embodiment, MMU 2345 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally cache line indices. In at least one embodiment, MMU 2345 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 2334 or L1 2348 cache, or processing cluster 2314. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0312] In at least one embodiment, processing cluster 2314 may be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2334 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2334 outputs processed tasks to data crossbar 2340 to provide the processed tasks to another processing cluster 2314 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2316. In at least one embodiment, a pre-ROP 2342 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2334 and direct the data to the ROP units, which may be located within partition units (e.g., partition units 2320A-2320N in FIG. 23A ) as described herein. In at least one embodiment, the pre-ROP 2342 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0313] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with FIG. 10A and / or FIG. 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in graphics processing cluster 2314 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0314] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above, hi at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein.

[0315] 23D illustrates a graphics multiprocessor 2334 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2334 couples with a pipeline manager 2332 of a processing cluster 2314. In at least one embodiment, the graphics multiprocessor 2334 has an execution pipeline including, but not limited to, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more general-purpose graphics processing unit (GPGPU) cores 2362, and one or more load / store units 2366. In at least one embodiment, the GPGPU cores 2362 and the load / store units 2366 are coupled to a cache memory 2372 and a shared memory 2370 via a memory and cache interconnect 2368.

[0316] In at least one embodiment, instruction cache 2352 receives a stream of instructions to execute from pipeline manager 2332. In at least one embodiment, instructions are cached in instruction cache 2352 and dispatched for execution by instruction unit 2354. In at least one embodiment, instruction unit 2354 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group being assigned to a different execution unit within GPGPU core 2362. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 2356 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 2366.

[0317] In at least one embodiment, register file 2358 provides a set of registers to the functional units of graphics multiprocessor 2334. In at least one embodiment, register file 2358 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2362, load / store unit 2366) of graphics multiprocessor 2334. In at least one embodiment, register file 2358 is partitioned among the respective functional units, with each functional unit allocated a dedicated portion of register file 2358. In one embodiment, register file 2358 is partitioned among the different warps being executed by graphics multiprocessor 2334.

[0318] In at least one embodiment, the GPGPU cores 2362 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for the graphics multiprocessor 2334. In at least one embodiment, the GPGPU cores 2362 may have similar or different architectures. In at least one embodiment, a first portion of the GPGPU core 2362 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement IEEE 754-2008 standard floating-point arithmetic or may enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2334 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangular copy or pixel-blending operations. In at least one embodiment, one or more of the GPGPU cores 2362 may also include fixed or special-function logic.

[0319] In at least one embodiment, GPGPU core 2362 includes SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 2362 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can execute in parallel via a single SIMD8 logical unit.

[0320] In at least one embodiment, memory and cache interconnect 2368 is an interconnect network connecting each functional unit of graphics multiprocessor 2334 to register file 2358 and shared memory 2370. In at least one embodiment, memory and cache interconnect 2368 is a crossbar interconnect that allows load / store unit 2366 to implement load and store operations between shared memory 2370 and register file 2358. In at least one embodiment, register file 2358 can operate at the same frequency as GPGPU cores 2362, and therefore data transfers between GPGPU cores 2362 and register file 2358 can have very low latency. In at least one embodiment, shared memory 2370 can be used to enable communication between threads executing in functional units within graphics multiprocessor 2334. In at least one embodiment, cache memory 2372 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 2336. In at least one embodiment, shared memory 2370 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 2362 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 2372.

[0321] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into a package or chip as a core, or may be communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to such GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0322] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in graphics multiprocessor 2334 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0323] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above, hi at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein.

[0324] FIG. 24 illustrates a multi-GPU computing system 2400, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2400 may include a processor 2402 coupled to multiple general-purpose graphics processing units (GPGPUs) 2406A-D via a host interface switch 2404. In at least one embodiment, the host interface switch 2404 is a PCI Express switch device that couples the processor 2402 to a PCI Express bus, via which the processor 2402 can communicate with the GPGPUs 2406A-D. In at least one embodiment, the GPGPUs 2406A-D may be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2416. In at least one embodiment, the GPU-to-GPU links 2416 are connected to each of the GPGPUs 2406A-D via dedicated GPU links. In at least one embodiment, the P2P GPU link 2416 allows direct communication between each of the GPGPUs 2406A-D without requiring communication through the host interface bus 2404 to which the processor 2402 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to the P2P GPU link 2416, the host interface bus 2404 remains available for access to system memory or for communication with other instances of the multi-GPU computing system 2400, for example, via one or more network devices. In at least one embodiment, the GPGPUs 2406A-D are connected to the processor 2402 through the host interface switch 2404, and in at least one embodiment, the processor 2402 includes direct support for the P2P GPU link 2416 and can be directly connected to the GPGPUs 2406A-D.

[0325] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in the multi-GPU computing system 2400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0326] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above, hi at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein.

[0327] 25 is a block diagram of a graphics processor 2500 according to at least one embodiment. In at least one embodiment, graphics processor 2500 includes a ring interconnect 2502, a pipeline front end 2504, a media engine 2537, and graphics cores 2580A-2580N. In at least one embodiment, ring interconnect 2502 couples graphics processor 2500 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2500 is one of multiple processors integrated within a multi-core processing system.

[0328] In at least one embodiment, graphics processor 2500 receives batches of commands via ring interconnect 2502. In at least one embodiment, the incoming commands are interpreted by command streamer 2503 of pipeline front end 2504. In at least one embodiment, graphics processor 2500 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2580A-2580N. In at least one embodiment, for 3D geometry processing commands, command streamer 2503 supplies the commands to geometry pipeline 2536. In at least one embodiment, for at least some media processing commands, command streamer 2503 supplies the commands to video front end 2534, which is coupled to media engine 2537. In at least one embodiment, the media engine 2537 includes a Video Quality Engine (VQE) 2530 for video and image post-processing and a Multi-Format Encode / Decode (MFX) 2533 engine that provides hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2536 and the media engine 2537 each spawn execution threads for thread execution resources provided by at least one graphics core 2580.

[0329] In at least one embodiment, graphics processor 2500 includes scalable thread execution resources characterized by graphics cores 2580A-2580N (which may be modular and sometimes referred to as core slices), each of which has multiple sub-cores 2550A-2580N, 2560A-2560N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2500 can have any number of graphics cores 2580A. In at least one embodiment, graphics processor 2500 includes graphics core 2580A having at least a first sub-core 2550A and a second sub-core 2560A. In at least one embodiment, graphics processor 2500 is a low-power processor having a single sub-core (e.g., 2550A). In at least one embodiment, graphics processor 2500 includes multiple graphics cores 2580A-2580N, each including a set of first sub-cores 2550A-2550N and a set of second sub-cores 2560A-2560N. In at least one embodiment, each of first sub-cores 2550A-2550N includes at least a first set of execution units 2552A-2552N and media / texture samplers 2554A-2554N. In at least one embodiment, each of second sub-cores 2560A-2560N includes at least a second set of execution units 2562A-2562N and samplers 2564A-2564N. In at least one embodiment, each sub-core 2550A-2550N, 2560A-2560N shares a set of shared resources 2570A-2570N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0330] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with Figures 10A and / or 10B. In at least one embodiment, the inference and / or training logic 1015 may be used in graphics processor 2500 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0331] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above, hi at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein.

[0332] FIG. 26 is a block diagram illustrating the micro-architecture of a processor 2600 that may include logic circuits for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2600 may execute instructions, including x86 instructions, AMR instructions, special instructions for application-specific integrated circuits (ASICs), and the like. In at least one embodiment, the processor 2600 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processor 2600 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0333] In at least one embodiment, processor 2600 includes an in-order front end (“front end”) 2601 that fetches instructions to be executed and prepares the instructions for later use in the processor pipeline. In at least one embodiment, front end 2601 may include several units. In at least one embodiment, an instruction prefetcher 2626 fetches instructions from memory and provides the instructions to an instruction decoder 2628, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2628 decodes received instructions into one or more operations, called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”), that the machine can execute. In at least one embodiment, instruction decoder 2628 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2630 may assemble the decoded uops into program-order sequences, or traces, in uop queue 2634 for execution. In at least one embodiment, when trace cache 2630 encounters a complex instruction, microcode ROM 2632 provides the uops necessary to complete the operation.

[0334] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 2628 may access the microcode ROM 2632 to execute the instruction. In at least one embodiment, the instruction may be decoded into a smaller number of micro-ops for processing in the instruction decoder 2628. In at least one embodiment, if a large number of micro-ops are required to complete such an operation, the instruction may be stored in the microcode ROM 2632. In at least one embodiment, the trace cache 2630 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2632, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2632 has finished sequencing micro-ops for an instruction, the machine front end 2601 may resume fetching micro-ops from the trace cache 2630.

[0335] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2603 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions to optimize performance as instructions are scheduled for execution down the pipeline. In at least one embodiment, out-of-order execution engine 2603 includes, without limitation, allocator / register renamer 2640, memory uop queue 2642, integer / floating point uop queue 2644, memory scheduler 2646, fast scheduler 2602, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2604, and simple floating point scheduler ("simple FP scheduler") 2606. In at least one embodiment, fast scheduler 2602, slow / general purpose floating point scheduler 2604, and simple floating point scheduler 2606 are also collectively referred to herein as "uop schedulers 2602, 2604, 2606." In at least one embodiment, allocator / register renamer 2640 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2640 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2640 also allocates each uop's entry to one of two uop queues—memory uop queue 2642 for memory operations and integer / floating point uop queue 2644 for non-memory operations—before memory scheduler 2646 and uop schedulers 2602, 2604, 2606. In at least one embodiment, uop schedulers 2602, 2604, 2606 determine when uops are ready to execute based on the readiness of the sources of their dependent input register operands and the availability of the execution resources required by the uop to complete their operations.In at least one embodiment, the fast scheduler 2602 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 2604 and simple floating point scheduler 2606 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2602, 2604, 2606 arbitrate for dispatch ports to schedule uops for execution.

[0336] In at least one embodiment, execution block 2611 includes, without limitation, integer register file / bypass network 2608, floating point register file / bypass network (“FP register file / bypass network”) 2610, address generation units (“AGUs”) 2612 and 2614, fast arithmetic logic units (ALUs) (“fast ALUs”) 2616 and 2618, slower arithmetic logic unit (“slower ALU”) 2620, floating point ALU (“FP”) 2622, and floating point move unit (“FP move”) 2624. In at least one embodiment, integer register file / bypass network 2608 and floating point register file / bypass network 2610 are also referred to herein as “register files 2608, 2610.” In at least one embodiment, AGUs 2612 and 2614, fast ALUs 2616 and 2618, slow ALU 2620, floating-point ALU 2622, and floating-point move unit 2624 are also referred to herein as "execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624." In at least one embodiment, execution block 2611 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units, in any combination, without limitation.

[0337] In at least one embodiment, register networks 2608, 2610 may be disposed between uop schedulers 2602, 2604, 2606 and execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624. In at least one embodiment, integer register file / bypass network 2608 performs integer operations. In at least one embodiment, floating point register file / bypass network 2610 performs floating point operations. In at least one embodiment, each of register networks 2608, 2610 may include, without limitation, a bypass network, which may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register networks 2608, 2610 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2608 may include, without limitation, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, so floating-point register file / bypass network 2610 may include, without limitation, 128-bit wide entries.

[0338] In at least one embodiment, execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624 may execute instructions. In at least one embodiment, register networks 2608 and 2610 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 2600 may include any number and combination of execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624, without limitation. In at least one embodiment, floating-point ALU 2622 and floating-point move unit 2624 may execute floating-point, MMX, SIMD, AVX, and other operations, including SEE, or special machine learning instructions. In at least one embodiment, the floating-point ALU 2622 may include, without limitation, a 64-bit floating-point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 2616, 2618. In at least one embodiment, the high-speed ALUs 2616, 2618 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 2620 may include, without limitation, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branching, so most complex integer operations proceed to the low-speed ALU 2620. In at least one embodiment, memory load / store operations may be performed by the ALUs 2612, 2614. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc.In at least one embodiment, floating-point ALU 2622 and floating-point move unit 2624 may be implemented to support wide operands having various bit widths, such as 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0339] In at least one embodiment, the uop schedulers 2602, 2604, 2606 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2600, the processor 2600 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0340] In at least one embodiment, a "register" may refer to a storage location in an on-board processor that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, or perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0341] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with FIG. 10A and / or FIG. 10B . In at least one embodiment, some or all of the inference and / or training logic 1015 may be incorporated into the execution block 2611 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the execution block 2611. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution block 2611 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0342] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above, hi at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein.

[0343] 27 illustrates a deep learning application processor 2700 according to at least one embodiment. In at least one embodiment, the deep learning application processor 2700 uses instructions that, when executed by the deep learning application processor 2700, cause the deep learning application processor 2700 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2700 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2700 performs a matrix multiplication operation, both "hard-wired" in hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2700 includes, without limitation, processing clusters 2710(1)-2710(12), inter-chip links (“ICLs”) 2720(1)-2720(12), inter-chip controllers (“ICCs”) 2730(1)-2730(2), high-bandwidth memory second generation (“HBM2”) 2740(1)-2740(4), memory controllers (“Mem Ctrlrs”) 2742(1)-2742(4), high-bandwidth memory physical layers (“HBM 2744(1)-2744(4), a management-controller central processing unit ("management-controller CPU") 2750, a serial peripheral interface, inter-integrated circuit, and general-purpose input / output block ("SPI, I2C, GPIO") 2760, a peripheral component interconnect express controller and direct memory access block ("PCIe controller and DMA") 2770, and a 16-lane peripheral component interconnect express port ("PCI Express x16") 2780.

[0344] In at least one embodiment, the processing clusters 2710 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2710 may include any number and types of processors, without limitation. In at least one embodiment, the deep learning application processor 2700 may include any number and types of processing clusters 2700. In at least one embodiment, the inter-chip link 2720 is bidirectional. In at least one embodiment, the inter-chip link 2720 and the inter-chip controller 2730 enable multiple deep learning application processors 2700 to exchange information, including activation information resulting from the execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2700 may include any number and types (including zero) of ICLs 2720 and ICCs 2730.

[0345] In at least one embodiment, the HBM2 2740 provides a total of 32 Gigabytes (GB) of memory. In at least one embodiment, an HBM2 2740(i) is associated with both a memory controller 2742(i) and an HBM PHY 2744(i), where “i” is any integer. In at least one embodiment, any number of HBM2s 2740 may provide any type and total amount of high-bandwidth memory and may be associated with any number and types of memory controllers 2742 and HBM PHYs 2744 (including zero). In at least one embodiment, the SPI, I2C, GPIO 2760, PCIe controller and DMA 2770, and / or PCIe 2780 may be replaced with any number and types of blocks enabling any number and types of communication standards in any technically feasible manner.

[0346] Inference and / or training logic 1015 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1015 are provided herein in conjunction with FIG. 10A and / or FIG. 10B . In at least one embodiment, the deep learning application processor 2700 is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 2700. In at least one embodiment, the deep learning application processor 2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2700. In at least one embodiment, the processor 2700 may be used to perform one or more neural network use cases described herein.

[0347] In at least one embodiment, a system for determining a grasp pose can be constructed using a processor as shown and described above, hi at least one embodiment, the processor executes executable instructions that cause the processor to determine and refine a grasp pose as described herein.

[0348] FIG. 28 is a block diagram of a neuromorphic processor 2800, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2800 receives one or more inputs from sources external to the neuromorphic processor 2800. In at least one embodiment, these inputs may be sent to one or more neurons 2802 within the neuromorphic processor 2800. In at least one embodiment, the neurons 2802 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2800 may include, without limitation, thousands or millions of instances of neurons 2802, although any suitable number of neurons 2802 may be used. In at least one embodiment, each instance of a neuron 2802 may include a neuron input 2804 and a neuron output 2806. In at least one embodiment, the neuron 2802 may generate an output, which may be sent to an input of another instance of the neuron 2802. For example, in at least one embodiment, neuron input 2804 and neuron output 2806 may be interconnected via synapse 2808 .

[0349] In at least one embodiment, neurons 2802 and synapses 2808 may be interconnected such that neuromorphic processor 2800 operates to process or analyze information received by neuromorphic processor 2800. In at least one embodiment, neuron 2802 may send an output pulse (or "fire" or "spike") when input received via neuron input 2804 exceeds a threshold. In at least one embodiment, neuron 2802 may sum or integrate signals received at neuron input 2804. For example, in at least one embodiment, neuron 2802 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 2802 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 2804 into a membrane potential and may apply a decay factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 2804 quickly enough to exceed a threshold (i.e., before the membrane potential decays too little to cause firing). In at least one embodiment, neuron 2802 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 2802 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron 2806 when the result of applying the transfer function to neuron 2804 exceeds a threshold. In at least one embodiment, neuron 2802 may ignore previously received input information, for example, by resetting the membrane potential to 0 or another suitable default value, once it fires.In at least one embodiment, once the membrane potential is reset to zero, neuron 2802 may resume normal operation after a suitable period (or refractory period).

[0350] In at least one embodiment, neurons 2802 may be interconnected through synapses 2808. In at least one embodiment, synapses 2808 may operate to transmit a signal from an output of a first neuron 2802 to an input of a second neuron 2802. In at least one embodiment, neurons 2802 may transmit information through two or more instances of synapses 2808. In at least one embodiment, one or more instances of neuron output 2806 may be connected to an instance of neuron input 2804 of the same neuron 2802 through an instance of synapse 2808. In at least one embodiment, an instance of neuron 2802 that generates an output to be transmitted through an instance of synapse 2808 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 2808. ...

Claims

1. 1. A computer system comprising: one or more processors; and a program that, when executed by said one or more processors, causes said computer system to have at least: acquiring image data of the object and at least one further object; generating a point cloud from the image data, the point cloud including image information of the object and image information of the at least one further object; generating a modified point cloud from the point cloud that is free of the image information of the at least one other object; generating a plurality of grip poses for the object from the modified point cloud, each grip pose of the plurality of grip poses being associated with a robot for grasping the object, and wherein the plurality of grip poses having the grip score higher than a first threshold are selected by a first neural network trained to predict a grip score for each grip pose; combining the point cloud with the plurality of gripping poses to determine whether the plurality of gripping poses cause the robot to contact the at least one other object based on determining whether each gripping pose has the collision score higher than a second threshold by a second neural network trained to predict a collision score for each gripping pose; generating a set of gripping poses by excluding from the plurality of gripping poses at least one gripping pose that causes the at least one other object to be in contact with the gripping object; and providing said set of gripping poses to said robot; a computer readable memory storing executable instructions for causing the A computer system comprising:

2. The executable instructions, when executed by the one or more processors, further result in the computer system having: The computer system of claim 1 , further comprising: acquiring said image data from a depth camera.

3. The executable instructions, when executed by the one or more processors, further result in the computer system having: obtaining a binary mask comprising segmented image information of the object and segmented image information of the at least one further object; The computer system of claim 1 , wherein the modified point cloud is generated using the binary mask.

4. The executable instructions, when executed by the one or more processors, further result in the computer system having: The computer system of claim 1 , further comprising: cropping the point cloud to generate the modified point cloud.

5. The executable instructions, when executed by the one or more processors, further result in the computer system having: applying a three-dimensional bounding volume to the cloud of points; The computer system of claim 4 , wherein generating the modified point cloud comprises cropping the point cloud to remove image information outside the three-dimensional bounding volume.

6. 2. The computer system of claim 1, wherein the first neural network comprises a variational autoencoder including a deterministic function for predicting each grasp pose based on the modified point cloud and latent variables, the latent variables defining a predetermined latent space used to at least partially generate each grasp pose predicted by the deterministic function.

7. generating a three-dimensional point cloud of the object and at least one further object using image data generated by the depth camera; generating a corrected 3D point cloud for the object separated from the 3D point cloud; acquiring a plurality of grip poses for the object using the corrected 3D point cloud, wherein the plurality of grip poses having the grip score above a first threshold are selected by a first neural network trained to predict a grip score for each grip pose; combining the three-dimensional point cloud with the plurality of gripping poses to determine interference information associated with at least one gripping pose of the plurality of gripping poses that interferes with the at least one other object based on determining whether each gripping pose has the collision score higher than a second threshold by a second neural network trained to predict a collision score for each gripping pose; removing the at least one gripping pose from the plurality of gripping poses based on determining the interference information associated with the at least one gripping pose to generate a set of refined gripping poses; having a robot use the refined set of gripping poses; 23. A computer-implemented method comprising:

8. 8. The computer-implemented method of claim 7, wherein determining the interference information associated with the at least one gripping pose comprises determining that the at least one gripping pose causes the robot to contact the at least one other object.

9. The computer-implemented method of claim 7 , further comprising cropping the three-dimensional point cloud to generate the modified three-dimensional point cloud.

10. applying a 3D bounding box to the 3D point cloud; cropping the 3D point cloud based on the 3D bounding box to generate the modified 3D point cloud; The computer-implemented method of claim 7 , further comprising:

11. obtaining a binary mask containing segmented image information of the object; separating the modified 3D point cloud from the 3D point cloud using the binary mask; The computer-implemented method of claim 7 , further comprising:

12. 8. The computer-implemented method of claim 7, wherein obtaining the plurality of grasp poses uses a variational autoencoder included in the first neural network, the variational autoencoder including a deterministic function for predicting each grasp pose based on the corrected 3D point cloud and latent variables, the latent variables defining a predetermined latent space used to at least partially generate each grasp pose predicted by the deterministic function.

13. When executed by one or more processors, the one or more processors are caused to perform at least acquiring image data of the object and at least one further object; generating a point cloud from the image data, the point cloud including image information of the object and image information of the at least one further object; generating a modified point cloud from the point cloud that is free of the image information of the at least one other object; generating a plurality of grip poses for the object from the modified point cloud, each grip pose of the plurality of grip poses being associated with a robot for gripping the object, and a first neural network trained to predict a grip score for each grip pose selecting the plurality of grip poses having the grip score higher than a first threshold; combining the point cloud with the plurality of gripping poses to determine whether the plurality of gripping poses cause the robot to contact the at least one other object based on determining whether each gripping pose has the collision score higher than a second threshold by a second neural network trained to predict a collision score for each gripping pose; excluding at least one gripping posture from the plurality of gripping postures based on determining that the at least one gripping posture among the plurality of gripping postures causes the robot to contact the at least one other object; A machine-readable medium having stored thereon a set of instructions that cause a

14. The set of instructions, when executed by the one or more processors, further causes the one or more processors to: The machine-readable medium of claim 13 , further comprising: acquiring the image data from a depth camera.

15. The set of instructions, when executed by the one or more processors, further causes the one or more processors to: obtaining a binary mask comprising segmented image information of the object and segmented image information of the at least one further object; The machine-readable medium of claim 13 , wherein the modified point cloud is generated using the binary mask.

16. The set of instructions, when executed by the one or more processors, further causes the one or more processors to: The machine-readable medium of claim 13 , further comprising: cropping the point cloud to generate the modified point cloud.

17. The set of instructions, when executed by the one or more processors, further causes the one or more processors to: applying a three-dimensional bounding volume to the cloud of points; The machine-readable medium of claim 13 , wherein generating the modified point cloud comprises cropping the point cloud to remove image information outside the three-dimensional bounding volume.

18. The machine-readable medium of claim 17 , wherein the three-dimensional bounding volume is a three-dimensional bounding box.

19. A robot, and one or more processors, the one or more processors being executed to cause the robot to: acquiring image data of the object and at least one further object; generating a point cloud from the image data, the point cloud including image information of the object and image information of the at least one further object; generating a modified point cloud from the point cloud that is free of the image information of the at least one other object; generating a plurality of grasp poses for the object from the modified point cloud, wherein the plurality of grasp poses having the grasp score above a first threshold are selected by a first neural network trained to predict a grasp score for each grasp pose; combining the point cloud with the plurality of gripping poses to determine whether each gripping pose has the collision score higher than a second threshold by a second neural network trained to predict a collision score for each gripping pose, and determining that at least one gripping pose of the plurality of gripping poses that interferes with the at least one other object has associated interference data; and removing the at least one gripping pose from the plurality of gripping poses based on determining that the at least one gripping pose of the plurality of gripping poses has the associated interference data; a memory storing executable instructions for causing the A robot equipped with

20. The executable instructions, when executed by the one or more processors, further cause the robot to: Applying a three-dimensional bounding box to the point cloud; 20. The robot of claim 19, wherein generating the modified point cloud includes cropping the point cloud to remove image information outside the three-dimensional bounding box.

21. The executable instructions, when executed by the one or more processors, further cause the robot to: obtaining a binary mask including segmented image information of the object; The robot of claim 19 , wherein the modified point cloud is generated using the binary mask.

22. The robot of claim 19 , wherein the associated interference data indicates that the at least one grasp pose contacts the at least one other object.

23. 20. The robot of claim 19, wherein the robot comprises at least one of a clamp, a scalpel, a gripper, a needle, scissors, or a laser.

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