Wiring board and manufacturing method thereof

Abstract

A wiring board according to the present disclosure comprises: an insulating layer; a groove located in an upper surface of the insulating layer; a recess located in the upper surface of the insulating layer and having a width greater than that of the groove; an underlying metal layer located on an inner surface of the groove and on an inner surface of the recess; a first wiring conductor located on the underlying metal layer and filling the groove; and a second wiring conductor located on the underlying metal layer and filling the recess, the second wiring conductor having a width greater than that of the first wiring conductor. The second wiring conductor includes a first portion and a second portion integrally located adjacent to the first portion. A plurality of gaps are located at a boundary between the first portion and the second portion.

Description

[Technical field]

[0001] The present invention relates to a wiring board and a manufacturing method thereof. [Background technology]

[0002] Conventionally, a semi-additive method has been used as a method for forming wiring conductors in wiring boards. The semi-additive method is a method for forming wiring conductors in the following procedure. First, a thin base metal layer is formed on the exposed surface of an insulating layer by electroless plating, sputtering, or the like. Next, a plating resist layer having openings corresponding to the pattern of the wiring conductor is formed on this base metal layer. Next, an electrolytic plating layer is formed on the base metal layer exposed in the openings of the plating resist layer. Next, the plating resist layer is peeled off and removed, and finally, the base metal layer in the portion not covered by the electrolytic plating layer is etched away.

[0003] Meanwhile, in wiring boards, the wiring conductors are becoming finer. For example, there is a demand for the width of the wiring conductor to be 15 μm or less, and for the distance between adjacent wiring conductors to be 15 μm or less. When the width of the wiring conductor is narrow, for example, 15 μm or less, the bonding area between the insulating layer and the wiring conductor via the underlying metal layer becomes small, and the wiring conductor is easily peeled off from the insulating layer. Furthermore, the electrical insulation reliability between adjacent wiring conductors is reduced.

[0004] Therefore, as described in Patent Document 1, a method for forming a wiring conductor consisting of an undercoat metal layer and an electrolytic plating layer remaining in the groove has been proposed. First, a groove corresponding to the pattern of the wiring conductor is formed to a predetermined depth on the surface of the insulating layer by laser processing. Next, a thin undercoat metal layer is formed on the surface of the insulating layer including the inner wall of the groove by electroless plating or sputtering. Next, an electrolytic plating layer is formed on this undercoat metal layer to a thickness that fills the groove. Finally, the undercoat metal layer and the electrolytic plating layer on the insulating layer are polished and removed by chemical mechanical polishing.

[0005] According to this method, a groove for a wiring conductor having a relatively narrow width (for example, 15 μm or less) is filled well with the electrolytic plating layer. However, a groove for a wiring conductor having a relatively wide width (for example, 150 μm or more) is difficult to fill well with the electrolytic plating layer. As a result, in a wide wiring conductor, the upper surface of the wiring conductor is greatly recessed and the flatness is poor. If the thickness of the electrolytic plating layer is further increased to eliminate this recess, the stress generated when forming this electrolytic plating layer becomes large. Therefore, the stress acts largely between the inner wall of the groove for the wide wiring conductor via the base metal layer, and the wide wiring conductor is easily peeled off. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2004-149926 A Summary of the Invention [Means for solving the problem]

[0007] The wiring board according to the present disclosure includes an insulating layer, a groove located on the upper surface of the insulating layer, a recess located on the upper surface of the insulating layer and having a width wider than the groove, an underlying metal layer located on the inner surface of the groove and the inner surface of the recess, a first wiring conductor located on the underlying metal layer filling the groove, and a second wiring conductor located on the underlying metal layer filling the recess and having a width wider than the first wiring conductor. The second wiring conductor has a first portion and a second portion located integrally adjacent to the first portion. A plurality of voids are located at the boundary between the first portion and the second portion.

[0008] A method for manufacturing a wiring board according to the present disclosure includes the steps of: forming a groove and a recess having a width wider than the groove on an upper surface of an insulating layer; forming a base metal layer on the upper surface of the insulating layer, the inner surface of the groove, and the inner surface of the recess; forming at least one plating resist having a width narrower than the width of the recess on the base metal layer in the recess; forming a first electrolytic plating layer on the base metal layer exposed from the plating resist; removing the plating resist from the base metal layer; forming a second electrolytic plating layer on the first electrolytic plating layer and on the base metal layer; and removing the first electrolytic plating layer, the second electrolytic plating layer, and a portion of the base metal layer to form a first wiring conductor made of the first electrolytic plating metal derived from the first electrolytic plating layer or the second electrolytic plating metal derived from the second electrolytic plating layer that fills the groove, and a second wiring conductor made of the first electrolytic plating metal and the second electrolytic plating metal derived from the second electrolytic plating layer that fills the recess. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is an explanatory diagram illustrating a cross section of a wiring board according to an embodiment of the present disclosure. [Diagram 2] 2 is an electron microscope photograph of region X shown in FIG. 1. [Diagram 3] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 4] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Diagram 5] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 6] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 7] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 8]5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 9] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 10] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 11] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 12] 5A to 5C are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a manufacturing method for a wiring board according to an embodiment of the present disclosure. [Figure 13] 13A and 13B are explanatory diagrams showing modified examples of the second wiring conductor. [Figure 14] 13A and 13B are explanatory diagrams showing modified examples of the second wiring conductor. [Figure 15] 13A and 13B are explanatory diagrams showing modified examples of the second wiring conductor. [Figure 16] 13A and 13B are explanatory diagrams showing modified examples of the second wiring conductor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] As described above, in the conventional method of forming a wiring conductor consisting of an undercoat metal layer and an electrolytic plating layer remaining in the groove, a large stress acts between the undercoat metal layer and the inner wall of the groove for the wide wiring conductor, and the wide wiring conductor is likely to peel off. Therefore, there is a demand for a wiring board in which the wide wiring conductor is less likely to peel off.

[0011] According to the wiring board of the present disclosure, the wide second wiring conductor has a first portion and a second portion that is adjacent to and integral with the first portion, and a plurality of voids are located at the boundary between the first portion and the second portion. Therefore, stress generated between the second wiring conductor and the insulating layer and stress generated within the second wiring conductor are dispersed and mitigated at the boundary between the first portion and the second portion where the voids are located. As a result, the wiring board of the present disclosure can reduce peeling of the second wiring conductor.

[0012] Furthermore, according to the method for manufacturing a wiring board of the present disclosure, the above steps disperse stress during the formation of the first electrolytic plating layer and the formation of the second electrolytic plating layer, resulting in a wiring board in which peeling of the second wiring conductor formed in the recess is reduced.

[0013] The wiring board of the present disclosure will be described with reference to Figs. 1 and 2. Fig. 1 is an explanatory diagram showing a cross section of a wiring board according to an embodiment of the present disclosure. A wiring board 10 according to an embodiment includes insulating layers 1 (11, 12), a first wiring conductor 5, and a second wiring conductor 6. In the wiring board 10 according to an embodiment, the insulating layer 1 (11) corresponds to a core insulating layer 11, and the insulating layer 1 (12) corresponds to a build-up insulating layer 12. In the wiring board 10 according to an embodiment, a form in which the build-up insulating layer 12 includes the first wiring conductor 5 and the second wiring conductor 6 will be described.

[0014] The core insulating layer 11 is formed of a resin such as an epoxy resin, a bismaleimide-triazine resin, a polyimide resin, a polyphenylene ether resin, or a liquid crystal polymer. These resins may be used alone or in combination of two or more. The core insulating layer 11 may contain a reinforcing material such as glass cloth, and may further have insulating particles dispersed therein. The insulating particles are not limited, and examples thereof include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. The thickness of the core insulating layer 11 is not limited, and is, for example, 0.1 mm or more and 2.0 mm or less if it is a core insulating layer.

[0015] The core insulating layer 11 has a through-hole conductor 11a for electrically connecting the conductor layers 11b on the upper and lower surfaces of the core insulating layer 11. The through-hole conductor 11a is located in a through-hole penetrating the upper and lower surfaces of the core insulating layer 11. The through-hole conductor 11a is formed of a conductor made of metal plating such as copper plating. The through-hole conductor 11a is connected to the conductor layers 11b on both sides of the core insulating layer 11. The through-hole conductor 11a may be formed only on the inner wall surface of the through-hole, or may be filled in the through-hole.

[0016] Like the core insulating layer 11, the build-up insulating layer 12 is formed of a resin such as an epoxy resin, a bismaleimide-triazine resin, a polyimide resin, a polyphenylene ether resin, or a liquid crystal polymer. These resins may be used alone or in combination of two or more. The core insulating layer 11 and the build-up insulating layer 12 may be formed of the same resin or different resins. The build-up insulating layer 12 may contain a reinforcing material such as glass cloth, and may further have insulating particles dispersed therein. The insulating particles are not limited, and examples thereof include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. The thickness of the build-up insulating layer 12 is not limited, and is, for example, 10 μm or more and 50 μm or less.

[0017] The build-up insulating layer 12 has a via-hole conductor 12a for electrically connecting the conductor layers located on the upper and lower surfaces of the build-up insulating layer 12. The via-hole conductor 12a is located in a via hole penetrating the upper and lower surfaces of the build-up insulating layer 12. The via-hole conductor 12a is formed, for example, at the same time as forming the first wiring conductor 5 and the second wiring conductor 6. The via-hole conductor 12a may be formed only on the inner wall surface of the via hole, or may be filled in the via hole.

[0018] A groove 2 and a recess 3 are located on the upper surface of the build-up insulating layer 12. A base metal layer 4 is located on the inner surface of the groove 2 and the recess 3. The base metal layer 4 is a part that serves as a base for the first wiring conductor 5 and the second wiring conductor 6. The base metal layer 4 is formed of a metal such as copper. The base metal layer 4 has a thickness of, for example, 0.1 μm or more and 0.5 μm or less. The presence of the base metal layer 4 improves the adhesion of the first wiring conductor 5 and the second wiring conductor 6.

[0019] The groove 2 is filled with a first wiring conductor 5. The width of the first wiring conductor 5 may be relatively narrow, for example, 15 μm or less. Such a first wiring conductor 5 functions, for example, as a signal wiring conductor. The width of the groove 2 is appropriately set according to the width of the first wiring conductor 5. The depth of the groove 2 is not limited as long as it does not penetrate the build-up insulating layer 12. The depth of the groove 2 is preferably, for example, 10% to 50% of the thickness of the build-up insulating layer 12. The first wiring conductor being filled in the groove 2 includes cases where there is a gap in the groove 2 due to air being trapped during manufacturing, and a gap due to the base metal layer 4 or the first wiring conductor not being attached to a narrow portion.

[0020] The arithmetic mean roughness Ra of the inner surface of the groove 2 is not limited, and may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the inner surface of the groove 2 is 50 nm or more and 100 nm or less, the base metal layer 4 is more firmly adhered, and peeling of the base metal layer 4 can be further reduced. Furthermore, the arithmetic mean roughness Ra of the surface of the base metal layer 4 located in the groove 2 is not limited, and may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the surface of the base metal layer 4 located in the groove 2 is 50 nm or more and 100 nm or less, the first wiring conductor 5 is firmly adhered to the base metal layer 4, and peeling of the first wiring conductor 5 can be further reduced.

[0021] The first wiring conductor 5 may have a surface roughness with an arithmetic mean roughness Ra of 50 nm or more and 100 nm or less, corresponding to the arithmetic mean roughness Ra of the surface of the underlying metal layer 4. This roughness is smaller than the side roughness of the second wiring conductor 6, and when a high-frequency signal is transmitted to the first wiring conductor 5, the transmission loss can be further reduced.

[0022] The recess 3 has a width wider than the groove 2. The recess 3 is filled with a second wiring conductor 6. The width of the second wiring conductor 6 is wider than the width of the first wiring conductor 5, and may be, for example, 150 μm or more. Such a second wiring conductor 6 functions, for example, as a ground conductor layer. The width of the recess 3 is appropriately set according to the width of the second wiring conductor 6. The depth of the recess 3 is not limited as long as it does not penetrate the build-up insulating layer 12. The depth of the recess 3 is preferably, for example, 10% to 50% of the thickness of the build-up insulating layer 12. The second wiring conductor being filled in the recess 3 includes cases in which there is a gap in the recess 3 due to air being entrained during manufacturing, and a gap due to a narrow portion not being covered with the base metal layer 4 or the second wiring conductor.

[0023] The second wiring conductor 6 includes a first portion 61 and a second portion 62, and the second portion 62 is located adjacent to and integral with the first portion 61. The first portion 61 is formed of, for example, a first electrolytic plating metal, such as copper. On the other hand, the second portion 62 is formed of, for example, a second electrolytic plating metal, such as copper. Even if the first portion 61 and the second portion 62 are formed of the same metal (for example, copper), they are treated as separate portions in this specification.

[0024] 1 shows a boundary 63 between a first portion 61 and a second portion 62 for convenience, but in an actual second wiring conductor 6, such a clear boundary 63 does not exist, and a plurality of voids 64 are located at the boundary 63 as shown in Fig. 2. The voids 64 distinguish the first portion 61 from the second portion 62. Fig. 2 is an electron microscope photograph of region X shown in Fig. 1.

[0025] In this manner, the second wiring conductor 6 has a first portion 61 and a second portion 62, and a plurality of voids 64 are located at the boundary 63 between the first portion 61 and the second portion 62, so that stress generated between the second wiring conductor 6 and the insulating layer 1 and stress generated within the second wiring conductor 6 are dispersed and alleviated at the boundary 63 between the first portion 61 and the second portion 62 where the voids 64 are located. As a result, the wiring board according to one embodiment can reduce peeling of the second wiring conductor 6.

[0026] The size of the void 64 is not limited, and may be, for example, a maximum length of 50 nm or more and 1 μm or less. In this specification, the "maximum length" refers to the length of the longest linear distance between the peripheries of the void 64. If the maximum length of the void 64 is 50 nm or more and 1 μm or less, the above-mentioned stress can be sufficiently dispersed and alleviated without affecting the bonding strength between the first portion 61 and the second portion 62.

[0027] At least a portion of first portion 61 and second portion 62 located on either side of boundary 63 contains continuous crystals. Continuous crystals means that the crystal orientations of the first electrolytically plated metal constituting first portion 61 and the second electrolytically plated metal constituting the second portion match on either side of boundary 63.

[0028] There is no limitation on the arithmetic mean roughness Ra of the inner surface of the recess 3, and it may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the inner surface of the recess 3 is 50 nm or more and 100 nm or less, the base metal layer 4 is more firmly adhered to the recess 3, and peeling of the base metal layer 4 can be further reduced.

[0029] The arithmetic mean roughness Ra of the surface of the base metal layer 4 located in the recess 3 is not limited and may be, for example, 50 nm or more and 100 nm or less. If the arithmetic mean roughness Ra of the surface of the base metal layer 4 located in the recess 3 is 50 nm or more and 100 nm or less, the second wiring conductor 6 is firmly attached to the base metal layer 4, and peeling of the second wiring conductor 6 can be further reduced. The second wiring conductor 6 may have a surface roughness with an arithmetic mean roughness Ra of 50 nm or more and 100 nm or less corresponding to the arithmetic mean roughness Ra of the surface of the base metal layer 4.

[0030] The wiring board 10 according to an embodiment may have a solder resist 7 located on the outermost layer. The solder resist 7 is formed of, for example, an acrylic modified epoxy resin. The solder resist 7 has a function of protecting the conductor layers (the first wiring conductor 5 and the second wiring conductor 6) from solder, for example, when mounting electronic components or connecting to a motherboard. The solder resist 7 has an opening for exposing a part of the first wiring conductor 5 or the second wiring conductor 6 located directly below it. The part of the first wiring conductor 5 or the second wiring conductor 6 exposed from this opening functions as a pad when mounting a semiconductor element or the like.

[0031] Next, a method for manufacturing a wiring board according to the present disclosure will be described with reference to Figs. 3 to 12. Figs. 3 to 12 are explanatory views showing manufacturing steps of a first wiring conductor and a second wiring conductor in a method for manufacturing a wiring board according to an embodiment of the present disclosure. The method for manufacturing a wiring board according to the present disclosure includes the following steps (a) to (g). (a) forming a groove and a recess having a width greater than that of the groove on an upper surface of an insulating layer; (b) forming a base metal layer on the upper surface of the insulating layer, the inner surface of the groove, and the inner surface of the recess; (c) forming at least one plating resist on the underlying metal layer within the recess, the plating resist having a width narrower than the width of the recess; (d) forming a first electrolytic plating layer on the underlying metal layer exposed from the plating resist; (e) A step of removing the plating resist from the base metal layer. (f) forming a second electrolytically plated layer on the first electrolytically plated layer and on the base metal layer; (g) a process of removing the first electrolytic plating layer, the second electrolytic plating layer, and a portion of the base metal layer to form a first wiring conductor made of a first electrolytic plating metal derived from the first electrolytic plating layer or a second electrolytic plating metal derived from the second electrolytic plating layer that fills the grooves, and a second wiring conductor made of the first electrolytic plating metal derived from the first electrolytic plating layer and the second electrolytic plating metal derived from the second electrolytic plating layer that fills the recesses.

[0032] First, as shown in FIG. 3, an insulating layer 1 (core insulating layer 11) is prepared. A conductor layer 11b is formed on the upper surface of the core insulating layer 11, and a through-hole conductor 11a is formed in the core insulating layer 11. The through-hole conductor 11a is connected to a part of the conductor layer 11b formed on the upper surface of the core insulating layer 11. The core insulating layer 11, the through-hole conductor 11a, and the conductor layer 11b are as described above, and detailed description will be omitted. The diagram shown at the bottom of FIG. 3 is a cross-sectional view taken along line AA in the diagram shown at the top. Below, the diagrams shown at the bottom of FIGS. 4 to 12 are cross-sectional views taken along line AA in the diagrams shown at the top, respectively.

[0033] 4, the insulating layer 1 (build-up insulating layer 12) is laminated so as to cover the core insulating layer 11 and the conductor layer 11b. The build-up insulating layer 12 is as described above, and a detailed description thereof will be omitted.

[0034] Next, as shown in FIG. 5, a groove 2 and a recess 3 having a width wider than that of the groove 2 are formed on the upper surface of the insulating layer 1 (build-up insulating layer 12) (step (a)). As shown in FIG. 5, the groove 2 may be formed at a position where the first wiring conductor 5 is to be formed. There is no limitation on the method for forming the groove 2, and it may be formed by laser processing using an excimer laser, a CO2 laser, a UV-YAG laser, or the like. It is preferable to employ an excimer laser since it is easy to form grooves 2 of a uniform depth. The depth of the groove 2 is as described above, and a detailed description thereof will be omitted.

[0035] There is no limitation on the arithmetic mean roughness Ra of the inner surface of the groove 2. If necessary, the inner surface of the groove 2 may be subjected to a roughening treatment so that the arithmetic mean roughness Ra of the inner surface of the groove 2 is, for example, 50 nm or more and 100 nm or less. A detailed description is as described above and will be omitted.

[0036] The recesses 3 may be formed at positions where the second wiring conductors 6 are to be formed. There are no limitations on the method for forming the recesses 3, and they may be formed by laser processing using an excimer laser, a CO2 laser, a UV-YAG laser, or the like. It is preferable to use an excimer laser because it is easy to form recesses 3 of uniform depth. The depth of the recesses 3 is as described above, and a detailed description thereof will be omitted.

[0037] There is no limitation on the arithmetic mean roughness Ra of the inner surface of the recess 3. If necessary, the inner surface of the recess 3 may be subjected to a roughening treatment so that the arithmetic mean roughness Ra of the inner surface of the recess 3 is, for example, 50 nm or more and 100 nm or less. A detailed description is as described above and will be omitted.

[0038] 6, a via hole 12a' is formed in the build-up insulating layer 12. The via hole 12a' is formed by laser processing using an excimer laser, a CO2 laser, a UV-YAG laser, or the like.

[0039] 7, a base metal layer 4 is formed on the upper surface of the insulating layer 1, the inner surface of the groove 2, and the inner surface of the recess 3 (step (b)). The base metal layer 4 is formed, for example, by depositing a metal such as copper by electroless plating. Palladium may be used as a catalyst when performing the electroless plating. The base metal layer 4 has a thickness of, for example, 0.1 μm or more and 0.5 μm or less.

[0040] There is no limitation on the arithmetic mean roughness Ra of the surface of the metal base layer 4 located in the grooves 2. If necessary, the surface of the metal base layer 4 located in the grooves 2 may be subjected to a roughening treatment so that the arithmetic mean roughness Ra of the surface of the metal base layer 4 located in the grooves 2 is, for example, 50 nm or more and 100 nm or less. A detailed description is as described above and will be omitted.

[0041] There is no limitation on the arithmetic mean roughness Ra of the surface of the metal base layer 4 located in the recess 3. If necessary, the surface of the metal base layer 4 located in the recess 3 may be subjected to a roughening treatment so that the arithmetic mean roughness Ra of the surface of the metal base layer 4 located in the recess 3 is, for example, 50 nm or more and 100 nm or less. A detailed description is as described above and will be omitted.

[0042] Next, as shown in Fig. 8, at least one plating resist 8 having a width W narrower than the width of the recess 3 is formed on the base metal layer 4 in the recess 3 (step (c)). The width W of the plating resist 8 is not limited as long as it is narrower than the width of the recess 3, and may be, for example, 50 µm or more and 100 µm or less. If the plating resist 8 having a width W narrower than the width of the recess 3 is formed in the recess 3, the plating resist 8 may be formed so as to cover other parts such as the groove 2. The plating resist 8 is formed of, for example, a resin such as an acrylic resin or a methacrylic resin.

[0043] 9, a first electrolytic plating layer P1 is formed on the base metal layer 4 exposed from the plating resist 8 (step (d)). The first electrolytic plating layer P1 is formed, for example, by precipitating a metal such as copper by electrolytic plating.

[0044] 10, the plating resist 8 is removed from the metal base layer 4 (step (e)). By removing the plating resist 8, the metal base layer 4 is exposed in the recess 3 except for the portion where the first electrolytic plating layer P1 is located.

[0045] 11, a second electrolytic plated layer P2 is formed on the first electrolytic plated layer P1 and on the base metal layer 4 (step (f)). Specifically, the second electrolytic plated layer P2 is formed on the first electrolytic plated layer P1 formed in the recess 3, and in the groove 2 and the recess 3, in a portion where the base metal layer 4 is exposed by removing the plating resist 8. The second electrolytic plated layer P2 is formed, for example, by precipitating a metal such as copper by electrolytic plating. The second electrolytic plated layer P2 is formed, for example, so that the recess 3 is filled with a metal such as copper.

[0046] Next, as shown in FIG. 12, the first electrolytic plating layer P1, the second electrolytic plating layer P2 and a portion of the base metal layer 4 are removed to form a first wiring conductor 5 made of a second electrolytic plating metal derived from the second electrolytic plating layer P2 that fills the grooves 2, and a second wiring conductor 6 made of the first electrolytic plating metal derived from the first electrolytic plating layer P1 and the second electrolytic plating metal derived from the second electrolytic plating layer P2 that fills the recesses 3 (step (g)).

[0047] An example of a method for removing the first electrolytically plated layer P1, the second electrolytically plated layer P2, and part of the base metal layer 4 is chemical mechanical polishing. By removing the first electrolytically plated layer P1, the second electrolytically plated layer P2, and part of the base metal layer 4, the surface of the first wiring conductor 5 and the surface of the second wiring conductor 6 are made to be substantially flush with each other. In the second wiring conductor 6, the first electrolytically plated metal corresponds to the first portion 61, and the second electrolytically plated metal corresponds to the second portion 62.

[0048] 12, for the sake of convenience, the first portion 61 and the second portion 62 are clearly distinguished from each other. However, in reality, as described above, there is no clear boundary between the first portion 61 and the second portion 62, and a plurality of voids 64 are located at the boundary 63 as shown in FIG. 2. The first portion 61 and the second portion 62 are distinguished from each other by the voids 64.

[0049] In this manner, the first wiring conductor 5 and the second wiring conductor 6 are formed on the insulating layer 1, such as a core insulating layer or a build-up insulating layer, to obtain the wiring board according to the present disclosure. When the insulating layer 1 is a build-up insulating layer, the steps (a) to (g) can be repeated to form a build-up layer having a desired number of layers. Furthermore, in the wiring board according to the present disclosure, a solder resist 7 may be located on the outermost layer. The solder resist 7 is as described above, and a detailed description thereof will be omitted.

[0050] In the method for manufacturing a wiring board according to the embodiment described above, in step (c), plating resist 8 is formed on base metal layer 4 in recess 3 so as to have a lattice shape when viewed from above. However, plating resist 8 formed on base metal layer 4 in recess 3 is not limited to a lattice shape.

[0051] Although the plating resist may be formed on the base metal layer in the recess so as to cut out a circle instead of a square when viewed from above, similar to the lattice shape shown in Fig. 8. When the plating resist is formed so as to cut out a circle in this way, a second wiring conductor 6a having a first portion 61a and a second portion 62a as shown in Fig. 13 is formed.

[0052] Alternatively, the structure may be the opposite of the lattice structure, in which the plating resist remains in the rectangular or circular cutout portions when viewed from above, and the plating resist does not exist in the lattice portion (so-called sea-island structure). When the plating resist exists in the sea-island structure, the first portions 61, 61a and the second portions 62, 62a of the second wiring conductors 6, 6a are reversed in FIGS. 12 and 13.

[0053] Furthermore, the plating resist does not need to be crossed vertically and horizontally when viewed from above, but may be linear. When the plating resist formed on the base metal layer in the recess is linear, a second wiring conductor 6b having a first portion 61b and a second portion 62b as shown in FIG.

[0054] Alternatively, the plating resist formed on the base metal layer in the recess may be in a straight line shape or a bent line shape such as a mountain shape or a curved shape such as a wave shape when viewed from above. When the plating resist formed on the base metal layer in the recess is in a mountain shape, a second wiring conductor 6c having a first portion 61c and a second portion 62c as shown in Fig. 15 is formed. When the plating resist formed on the base metal layer in the recess is in a wave shape, a second wiring conductor 6d having a first portion 61d and a second portion 62d as shown in Fig. 16 is formed.

[0055] As shown in Fig. 8, in the above-described embodiment, plating resist 8 is formed in areas other than recessed portion 3. Specifically, in Fig. 8, plating resist 8 is formed so as to cover groove 2 as well. However, plating resist 8 may be formed only in recessed portion 3. In this case, the groove is filled with the first electrolytic plating layer, and the first wiring conductor is formed by the first electrolytic plating metal derived from the first electrolytic plating layer. [Explanation of symbols]

[0056] 1. Insulation layer 11 Core insulation layer 11a Through hole conductor 11b Conductive layer 12 Build-up insulation layer 12a Via hole conductor 12a' Beer Hall 2 grooves 3. Recess 4. Undercoat metal layer 5 First wiring conductor 6 Second wiring conductor 61 Part 1 62 Part 2 63 Boundary 64 void 7 Solder Resist 8 Plating resist 10 Wiring board P1 First electrolytic plating layer P2 Second electrolytic plating layer

Claims

1. An insulating layer; a groove located on an upper surface of the insulating layer and having a width of 15 μm or less; a recess located on an upper surface of the insulating layer and having a width of 150 μm or more; a base metal layer located on an inner wall surface of the groove and an inner wall surface of the recess; a first wiring conductor located on the base metal layer so as to fill the groove and having a width of 15 μm or less; a second wiring conductor located on the base metal layer so as to fill the recess and having a width of 150 μm or more; Including, the second wiring conductor has a first portion and a second portion adjacent to the first portion and integrally located therewith, and a plurality of voids having a maximum length of 50 nm or more and 1 μm or less are located at the boundary between the first portion and the second portion; Wiring board.

2. 2. The wiring board according to claim 1, wherein the first portion is a first electrolytically plated metal and the second portion is a second electrolytically plated metal.

3. The wiring board according to claim 1 , wherein at least a part of the first portion and the second portion located on either side of the boundary includes a continuous crystal.

4. forming a groove having a width of 15 μm or less and a recess having a width of 150 μm or more on an upper surface of an insulating layer; forming a base metal layer on an upper surface of the insulating layer, an inner wall surface of the groove, and an inner wall surface of the recess; forming at least one plating resist having a width narrower than a width of the recess on the underlying metal layer within the recess; forming a first electrolytic plating layer on the base metal layer exposed from the plating resist; removing the plating resist from above the base metal layer; forming a second electrolytic plating layer on the first electrolytic plating layer and on the base metal layer such that a plurality of voids having a maximum length of 50 nm or more and 1 μm or less are located at the boundary with the first electrolytic plating layer; removing a portion of the first electrolytic plating layer, the second electrolytic plating layer, and the base metal layer to form a first wiring conductor having a width of 15 μm or less, which is made of a first electrolytic plating metal derived from the first electrolytic plating layer or a second electrolytic plating metal derived from the second electrolytic plating layer and which fills the groove, and a second wiring conductor having a width of 150 μm or more, which is made of the first electrolytic plating metal and the second electrolytic plating metal derived from the second electrolytic plating layer and which fills the recess; A method for manufacturing a wiring board comprising the steps of:

5. The method for manufacturing a wiring board according to claim 4 , wherein the plating resist has a width of 50 μm or more and 100 μm or less.

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