Imaging device and electronic device

Abstract

To provide an imaging device that has high imaging quality and can be manufactured at low cost.SOLUTION: A first circuit including a first transistor and a second transistor, and a second circuit including a second transistor and a photodiode are provided. The first transistor is provided on a first surface of a silicon substrate. The second transistor is provided over the first surface of the silicon substrate with a first insulating layer interposed therebetween. The silicon substrate includes a second insulating layer. The second insulating layer is provided so as to surround a side surface of the photodiode. The first transistor is a p-channel type transistor having an active region in the silicon substrate. The second transistor is an n-channel type transistor using an oxide semiconductor layer as an active layer. The photodiode has, as a light-receiving surface, a surface on the opposite side to the first surface of the silicon substrate.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to an imaging device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention disclosed in this specification includes semiconductor devices, display devices, and their driving An example of the present invention is a method for producing the same.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. Display devices, imaging devices, and electronic devices each include a semiconductor device. [Background technology]

[0004] A technology to construct transistors using semiconductor thin films formed on substrates with insulating surfaces The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). Semiconductors that can be used in transistors are widely used in electronic devices such as Silicon-based semiconductor materials are widely known as conductive thin films, but other materials include oxides. Semiconductors are attracting attention.

[0005] For example, zinc oxide or In-Ga-Zn oxide semiconductors are used as oxide semiconductors. Techniques for fabricating transistors have been disclosed (see Patent Documents 1 and 2).

[0006] In addition, Patent Document 3 discloses a transistor that includes an oxide semiconductor and has an extremely low off-state current. At least part of the pixel circuit is made of CMOS (Complementary Metal Oxide Semiconductor) It has silicon semiconductors on which circuits can be fabricated. By using transistors in the peripheral circuits, it is possible to create high-speed, low-power image sensors. It is disclosed that: [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-119711 A Summary of the Invention [Problem to be solved by the invention]

[0008] Imaging devices are expected to be used in a variety of environments, so they are required to capture images in low-light environments and when moving objects are the subject. Even in such a case, high image quality is required. Therefore, there is a demand for an imaging device that can be manufactured at lower cost.

[0009] Therefore, one embodiment of the present invention provides an imaging device capable of imaging under low illuminance. Another object of the present invention is to provide an imaging device with a wide dynamic range. Another object of the present invention is to provide an imaging device with high resolution. Another object of the present invention is to provide an imaging device having a high degree of integration. Another object of the present invention is to provide an imaging device that can be used in a wide range of applications. Another object of the present invention is to provide an imaging device that is suitable for use in a wide range of applications. Another object of the present invention is to provide an imaging device with a high aperture ratio. Another object of the present invention is to provide a low-cost imaging device. One of the objects is to provide a highly reliable imaging device.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One embodiment of the present invention is a pixel circuit including a transistor formed using an oxide semiconductor; A photoelectric conversion element formed using silicon and a transistor formed using an oxide semiconductor An imaging device including a peripheral circuit having a transistor formed using a silicon Regarding.

[0012] One embodiment of the present invention is an imaging device having a first circuit and a second circuit, The second circuit has a first transistor and a second transistor, and the second circuit has a third transistor and The first transistor is provided on a first surface of a silicon substrate, and The photodiode is provided on the silicon substrate, and the second transistor is a The silicon substrate has a first insulating layer, and the first insulating layer is a photodiode. The first transistor is a p-ch type transistor, and the first The transistor has an active region in a silicon substrate, and includes a second transistor and a third transistor. The transistor is an n-ch type transistor, and the second transistor and the third transistor The active layer of the photodiode has an oxide semiconductor, and the light receiving surface of the photodiode is a first surface of the silicon substrate. It is characterized in that it is provided on the surface opposite to the surface.

[0013] The first transistor and the second transistor may form a CMOS circuit. .

[0014] The second circuit further includes fourth to sixth transistors, The active layers of the fourth to sixth transistors are made of oxide semiconductor. The third transistor has a source or a drain connected to the anode of the photodiode. a source or drain of a third transistor electrically connected to the node or cathode; The other of the first and second transistors is electrically connected to one of the source and drain of the fourth transistor, and the third transistor The other of the source and drain of the transistor is electrically connected to the gate of the fifth transistor. The source or drain of the fifth transistor is connected to the source of the sixth transistor. The gate may be electrically connected to either the source or the drain.

[0015] The oxide semiconductor layer is made of In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La , Ce, Nd or Hf).

[0016] In addition, the crystal plane orientation on the first surface of the silicon substrate is preferably a (110) plane. . Effect of the Invention

[0017] According to one embodiment of the present invention, an imaging device capable of imaging under low illuminance can be provided. Alternatively, it is possible to provide an imaging device with a wide dynamic range. Alternatively, it is possible to provide a highly integrated imaging device. Alternatively, it is possible to provide an imaging device that can be used in a wide temperature range. Alternatively, it is possible to provide an imaging device suitable for high-speed operation. Alternatively, an imaging device with a high aperture ratio can be provided. Alternatively, a low-cost imaging device can be provided. Alternatively, a highly reliable imaging device can be provided. can be provided.

[0018] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0019] [Figure 1] 1A and 1B are a cross-sectional view and a circuit diagram illustrating an imaging device. [Diagram 2] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Diagram 3] FIG. 1 is a diagram illustrating a configuration of an imaging apparatus. [Figure 4] FIG. 2 is a diagram illustrating a driver circuit of the imaging device. [Diagram 5] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 6] 4 is a timing chart illustrating the operation of the pixel circuit. [Figure 7] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 8]FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 9] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 10] FIG. 13 is a diagram for explaining an integrating circuit. [Figure 11] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 12] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 13] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 14] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 15] FIG. 2 is a diagram illustrating the configuration of a pixel circuit. [Figure 16] 4 is a timing chart illustrating the operation of a global shutter system and a rolling shutter system. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 18] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 20] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 23] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 24] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Diagram 25] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 26] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 28] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 29] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 30] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 31] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 32] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 33] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 34] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 35] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Diagram 36] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 37] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel length direction. [Figure 38] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 39] FIG. 1 is a top view illustrating a transistor. [Diagram 40] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 41] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 42] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 43] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 44] 1A to 1C are cross-sectional views of a transistor and diagrams illustrating band structures thereof; [Diagram 45] FIG. 1 is a diagram for explaining a computational model. [Diagram 46] FIG. 1 is a diagram for explaining an initial state and a final state. [Figure 47] FIG. 1 is a diagram illustrating the activation barrier. [Figure 48] FIG. 1 is a diagram for explaining an initial state and a final state. [Figure 49] FIG. 1 is a diagram illustrating the activation barrier. [Figure 50] A diagram explaining VoH transition levels. [Figure 51] 1A to 1C are diagrams illustrating electronic devices. [Figure 52]1 is a cross-sectional view illustrating a transistor. [Figure 53] 1 is a cross-sectional view illustrating a transistor. [Figure 54] 1 is a cross-sectional view illustrating a transistor. [Figure 55] FIG. 2 is a diagram for explaining an image processing engine of the imaging apparatus. [Figure 56] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 57] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 58] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 59] FIG. [Figure 60] FIG. [Figure 61] FIG. 1 is a cross-sectional view illustrating an imaging apparatus. [Figure 62] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0021] In this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes the case where X and Y are directly connected. Here, X and Y are objects (e.g. For example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc. In this case, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence, but may be applied to any other connection relationship shown in a drawing or a sentence. This also includes connections other than those shown in the text.

[0022] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. It has the function of switching between these modes.

[0023] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if

[0024] In addition, when it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (That is, there is another element or circuit between X and Y.) X and Y are functionally connected (i.e., there is another circuit between X and Y) When X and Y are functionally connected through a wire, and when X and Y are directly connected (i.e. , when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it should simply be "" is the same as if it were expressly stated that the

[0025] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0026] For example, if the source (or the first terminal, etc.) of the transistor is connected to the ), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through (or without) Z2, or the transistor The source (or first terminal, etc.) of Z1 is directly connected to a part of Z1 and another part of Z1. is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to In the case where a part of Z1 is directly connected to Y and another part of Z2 is directly connected to Y, It can be expressed as follows.

[0027] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc., of the transistor are electrically connected to each other, and X, the source of the transistor (or (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and then Y. "The source of the transistor is electrically connected to the (or the first terminal, etc.) is electrically connected to X, and the drain (or The second terminal, etc.) is electrically connected to Y, and the source (or first terminal) of the transistor, The transistor's drain (or second terminal, etc.), and Y are electrically connected in that order. "X is connected to the source ( or the first terminal, etc.) and the drain (or the second terminal, etc.) X is the source (or first terminal, etc.) of the transistor, and The second terminal (or terminal 2, etc.), Y, is provided in this connection order. Using the same expressions as these examples, the order of connections in a circuit configuration can be regulated. By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal. The above expression methods are merely examples, and the present invention is not limited to these expression methods. Z2 is the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) Let's say there is.

[0028] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0029] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging device according to one embodiment of the present invention. The device includes a transistor 51 having an active region on a silicon substrate 40, an oxide semiconductor layer as the active region, A transistor 52 and a transistor 53 are provided on the silicon substrate 40. Each transistor and photodiode 60 is provided with an insulating layer. The photodiode has electrical connections to the conductors 70 embedded in the photodiode and to the wiring layers. The anode 61 of the electrode 60 has an electrical connection with the conductor 70 through the low resistance region 63. .

[0030] The low resistance region 63 may be formed of a p-type region in which impurities are added to the silicon substrate 40. However, as shown in FIG. 58(A), metal may be used instead. As shown in FIG. 1, a metal may be provided so as to penetrate the p-type region.

[0031] The above-mentioned electrical connection configuration of the elements is an example. Alternatively, wirings and electrodes provided in the same process are designated by the same reference numerals, and only representative portions are designated by the same reference numerals. The conductors 70 embedded in the insulating layer are given the same reference numerals throughout. In the drawings, each wiring, each electrode, and the conductor 70 are represented as individual elements. Although they are illustrated as separate elements, those that are electrically connected are treated as the same element. In some cases, a committee may be established.

[0032] The imaging device also includes a transistor 51 and a photodiode disposed on a silicon substrate 40. A first layer 1100 having a gate 60 and a light control layer 64, a wiring layer 71 and an insulating layer 81 , 82, and a second layer 1200 having transistors 52, 53 and an insulating layer. A third layer 1300 having a wiring layer 72, a wiring layer 73 and insulating layers 84 and 85. The first layer 1100, the second layer 1200, the third layer 1100, and the fourth layer 1400 are connected to each other. 300, and the fourth layer 1400 are laminated in that order.

[0033] In addition, there may be cases where some of the above-mentioned wirings are not provided, or where wirings, transistors, etc. other than those described above are provided. Each layer may contain the above-mentioned layers. Also, layers other than those mentioned above may be contained in the laminate structure. In addition, some of the above layers may not be included. It functions as an insulating film.

[0034] The side surface of the photodiode 60 in the first layer 1100 is surrounded by a light control layer 64. The light control layer 64 also acts as an isolation layer between adjacent photodiodes. The light incident on the side of the photodiode 60 from the light receiving surface is reflected by the light control layer 64. Therefore, the photodiode 60 of the adjacent pixel can be attenuated. This makes it possible to prevent light from entering the device, thereby making it possible to obtain images with less noise.

[0035] It is preferable to use a material having a refractive index lower than that of silicon for the light control layer 64. For example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, dioxide tantalum oxide, such as ruthenium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide. Insulators can be used. Organic materials such as acrylic resin and polyimide can also be used. By using a material with a lower refractive index than silicon, the side surface of the photodiode 60 In addition, air, nitrogen, oxygen, and aluminum can be used instead of the above materials. Gases such as argon, helium, etc. may be used, and in this case, the pressure may be lower than atmospheric pressure. stomach.

[0036] The light control layer 64 may be made of a material that easily absorbs light. For example, carbon black. Carbon-based black pigments such as black carbon, titanium-based black pigments such as titanium black, iron oxides, copper and chromium oxide, copper, chromium and zinc oxide, etc. Resins and the like can be used.

[0037] As shown in FIG. 58(C), a part of the side surface of the photodiode 60 is covered with the light control layer 64. In this embodiment, the low resistance region 63 is made of tungsten, tantalum, titanium, or aluminum. By using metals such as aluminum, incident light can be reflected, allowing it to function as a light control layer. Alternatively, a metal with low reflectance, such as molybdenum or chromium, may be used.

[0038] Also, as shown in FIG. 58(D), a metal may be provided so as to penetrate the light control layer 64. A part of the metal in the light control layer 64 is electrically connected to the anode 61 of the photodiode 60. It can be connected.

[0039] In addition, the depth direction of the portion (photodiode portion) indicated by the dashed line A1-A2 in FIG. The top view is, for example, as shown in Figure 59(A), (B), (C), (D), (E), and (F). The above-mentioned form may be adopted.

[0040] FIG. 59(A) shows that the upper surface shape of the light receiving portion 60p of the photodiode 60 is substantially rectangular. A light control layer 64 is provided around the periphery.

[0041] FIG. 59(B) shows a light receiving portion 60p having a substantially rectangular upper surface shape, and a light control layer 64 is provided. The light receiving portion 60p in FIG. 59(A) and (B) is shown as a substantially square shape. However, it may be substantially rectangular, substantially trapezoidal, or the like.

[0042] FIG. 59(C) is an example of a top view of a photodiode portion in the configuration of FIG. 58(C). .

[0043] In FIG. 59(D), the upper surface shape of the light receiving portion 60p is substantially hexagonal, and a light control layer 64 is provided around the periphery. It is being done.

[0044] FIG. 59(E) shows a light receiving portion 60p having a substantially triangular upper surface shape and a light control layer 64 provided around the light receiving portion 60p. It is being done.

[0045] In FIG. 59(F), the upper surface shape of the light receiving portion 60p is substantially circular, and a light control layer 64 is provided around the periphery. It is being done.

[0046] In the configurations shown in FIGS. 59(C) to 59(F), the light control layer 64 is provided in a fragmentary manner. The light receiving portion 60p may have a polygonal or elliptical shape other than the above. good.

[0047] Also, the low resistance region 63 can be replaced with a structure having a metal as shown in FIG. Also, the light control layer 64 can be replaced with a structure having a metal, as shown in FIG. It can be replaced.

[0048] As described above, since the side surface of the photodiode is covered with the light control layer 64, etc., The light incident on the side of the photodiode 60 from the opposite direction is reflected back into the photodiode 60. It can be projected or attenuated.

[0049] In addition, the low resistance region 63 can be shared by multiple photodiodes (multiple pixels). By sharing the low resistance region 63, the number of wirings can be reduced. For example, in FIG. When the upper surface shape of the light receiving portion 60p is substantially rectangular as shown in FIG. As shown, the low resistance region 63 can be shared by four photodiodes.

[0050] In addition, when the upper surface shape of the light receiving portion 60p is substantially hexagonal as shown in FIG. As shown in FIG. 0(B), the low resistance region 63 can be shared by three photodiodes. do.

[0051] In addition, when the upper surface shape of the light receiving portion 60p is substantially triangular as shown in FIG. As shown in FIG. 0(C), six photodiodes can share the low resistance region 63. do.

[0052] The silicon substrate 40 is not limited to a bulk silicon substrate, but may be an SOI substrate. In addition, instead of the silicon substrate 40, germanium, silicon germanium, silicon carbide, etc. , gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors Body-based substrates may also be used.

[0053] In the above laminated structure, a first layer having a transistor 51 and a photodiode 60 1100 and a third layer 1300 having transistors 52 and 53. An insulating layer 80 is provided.

[0054] Hydrogen in the insulating layer provided near the active region of the transistor 51 causes dangling of silicon. Therefore, the hydrogen has the effect of improving the reliability of the transistor 51. On the other hand, the active layers of the transistors 52 and 53 are oxide semiconductors. Hydrogen in the insulating layer provided near the oxide semiconductor layer is one of the factors that generate carriers in the oxide semiconductor. Therefore, the hydrogen reduces the reliability of the transistors 52 and 53. Therefore, transistors using silicon-based semiconductor materials One layer having a transistor using an oxide semiconductor is stacked on the other layer having a transistor using an oxide semiconductor. In this case, it is preferable to provide an insulating layer 80 between them, which has the function of preventing the diffusion of hydrogen. The insulating layer 80 confines hydrogen to one layer, improving the reliability of the transistor 51. In addition, the diffusion of hydrogen from one layer to the other layer is suppressed. Therefore, the reliability of the transistors 52 and 53 can be improved at the same time. .

[0055] The insulating layer 80 may be, for example, aluminum oxide, aluminum oxynitride, gallium oxide, Gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxynitride Hafnium oxide, yttria stabilized zirconia (YSZ), etc. can be used.

[0056] The transistor 52 and the photodiode 60 form a circuit 91. 1 and transistor 53 form a circuit 92. Circuit 91 functions as a pixel circuit. The circuit 92 can function as a driving circuit for driving the circuit 91. can be done.

[0057] The circuit 91 can have a configuration as shown in the circuit diagram of FIG. Either the source or drain of the transistor 52 and the cathode 62 of the photodiode 60 are electrically connected. The other of the source or drain of the transistor 52 is connected to the transistor 54 (FIG. 1(A)) and the gate of transistor 55 (not shown in FIG. 1(A)). Either the source or the drain is electrically connected to the charge storage section (FD).

[0058] The charge storage portion is specifically the source of the transistor 52 or the source of the transistor 53. is composed of the drain depletion layer capacitance, the gate capacitance of transistor 54, and the wiring capacitance, etc. will be done.

[0059] Here, the transistor 52 is a charge storage section (FD) in response to the output of the photodiode 60. The transistor can function as a transfer transistor for controlling the potential of the transistor. The transistor 54 is an amplifying transistor that outputs a signal according to the potential of the charge storage section (FD). The transistor 55 can function as a charge storage unit (FD). It can have a function as a reset transistor that initializes a potential.

[0060] The circuit 92 includes a CMOS inverter as shown in the circuit diagram of FIG. The gates of the transistors 51 and 53 are electrically connected to each other. In addition, one of the source and drain of the transistor 51 is connected to the source of the transistor 53. The source or drain of both transistors is electrically connected to the The other of the drains is electrically connected to separate wiring. A transistor 51 having an active region in an oxide semiconductor layer and a transistor 53 having an active layer in an oxide semiconductor layer. This forms a CMOS circuit.

[0061] In the above-mentioned image pickup device, a transistor 51 having an active region in a silicon substrate 40 is The transistors 52 to 55 each have an h-type oxide semiconductor layer as an active layer. It is of type ch.

[0062] In the circuit 91, all the transistors included in the circuit 91 are formed in the third layer 1300. By doing so, the electrical connection can be easily established, and the manufacturing process can be simplified. can.

[0063] In addition, a transistor including an oxide semiconductor has extremely low off-state current characteristics; The dynamic range of the photodiode can be expanded. When the intensity of light incident on the diode 60 is high, the potential of the charge storage section (FD) is low. Since a transistor using an oxide semiconductor has an extremely low off-state current, Even if the gate potential is very small, a current corresponding to the gate potential can be accurately output. Therefore, the range of illuminance that can be detected, i.e. the dynamic range, can be expanded. It is possible.

[0064] In addition, the low off-current characteristics of the transistors 52 and 55 reduce the charge storage (FD) can hold a charge for an extremely long period of time. Global shutter performs charge accumulation operation simultaneously on all pixels without complicating the operation method Therefore, even if the subject is moving, it is possible to easily capture an image with little distortion. In addition, the global shutter method makes it possible to shorten the exposure time (the charge accumulation operation Since the period during which the image is captured can be extended, this method is also suitable for capturing images in low-light environments.

[0065] In addition, a transistor using an oxide semiconductor has a higher electrical conductivity than a transistor using silicon. The temperature dependency of the characteristic fluctuation is small, so it can be used in an extremely wide temperature range. Therefore, an imaging device and a semiconductor device including a transistor using an oxide semiconductor can be used for automatic It is also suitable for installation in cars, airplanes, spacecraft, etc.

[0066] In addition, a transistor 52 and a transistor The transistors with low noise, such as 55, are preferable. The transistor with the conductor layer has a buried channel, which makes it highly resistant to noise. Therefore, by using this transistor, it is possible to obtain an image with less noise. can.

[0067] In the circuit 91, the photodiode 60 provided in the first layer 1100 and the Since the transistors in the 1300 can be formed to overlap each other, pixel integration is possible. In other words, the resolution of the imaging device can be increased. In circuit 91, no transistor is formed on the silicon substrate, so the photodiode Therefore, images with less noise can be obtained even in low-light environments. can be obtained.

[0068] In the circuit 92, an n-ch type transistor having an active region in the silicon substrate 40 is This eliminates the need for the step of forming p-wells and n-type impurity regions. This allows for a significant reduction in the number of processes. The transistors can be fabricated at the same time as the transistors included in the circuit 91 described above.

[0069] The imaging device shown in FIG. 1 has a surface of a silicon substrate 40 on which a transistor 51 is formed and a The light receiving surface of the photodiode 60 is on the opposite side of the substrate. This allows the optical path to be secured without being affected by wiring, making it possible to form pixels with a high aperture ratio. In addition, the light receiving surface of the photodiode 60 can be made the same as the surface on which the transistor 51 is formed. It can also be done like this.

[0070] In addition, the structure of the transistor and the photodiode included in the imaging device according to the present embodiment Therefore, for example, the circuit 91 is formed in an active region or active layer using silicon or the like. The circuit 92 may be configured with a transistor having an oxide semiconductor layer as an active layer. The photodiode 60 may be made of a transistor having an amorphous silicon. The silicon layer can be configured as a photoelectric conversion layer. The transistor 51 having the above configuration may be an n-ch type.

[0071] FIG. 2(A) is a cross-sectional view of an example of an embodiment in which a color filter or the like is added to the imaging device shown in FIG. 1(A). The cross-sectional view shows an area having a circuit 91 for three pixels (area 91a, area 91b , region 91c), and region 92a having a portion of circuitry 92. An insulating layer 1500 is formed on the photodiode 60 formed at 1500. For the 00, a silicon oxide film or the like having high transparency to visible light can be used. A silicon nitride film may be laminated as the ionization film. Alternatively, a dielectric film such as hafnium oxide may be laminated. 15), a configuration may be adopted in which the insulating layer 1500 is not provided.

[0072] A light-shielding layer 1510 is formed on the insulating layer 1500. The light-shielding layer 1510 is formed by The filter has a function of preventing the mixing of colors of light passing through it. 510 is a graph showing the characteristic change caused by light irradiation of a transistor having an active region on a silicon substrate 40. The light-shielding layer 1510 is a metal layer such as aluminum or tungsten. Alternatively, the metal layer and a dielectric film having a function as an anti-reflection film may be laminated. As shown in FIG. 56(B), the light-shielding layer 1510 may not be provided. Cut.

[0073] An organic resin layer 1520 is formed as a planarizing film on the insulating layer 1500 and the light-shielding layer 1510. The color filters 153 are disposed on the regions 91a, 91b, and 91c, respectively. 0a, color filter 1530b and color filter 1530c are formed in pairs. The color filter 1530a, the color filter 1530b, and the color filter 1530c are The 530c can be assigned colors such as R (red), G (green), and B (blue) As shown in FIG. 56(C), the organic resin layer 152 Alternatively, the insulating layer 150 may be omitted. 0, the light-shielding layer 1510 and the organic resin layer 1520 may not be provided. Although not shown, any two of the insulating layer 1500, the light-shielding layer 1510, and the organic resin layer 1520 may be used. It is also possible to adopt a configuration in which this is not provided.

[0074] Color filter 1530a, color filter 1530b, and color filter 1530c A microlens array 1540 is provided on the top. The light passing through each lens of 1540 passes through the color filter directly below and is emitted by the photodiode. The light will then be irradiated onto the

[0075] As shown in FIG. 57(A), a light-shielding layer 1510 is provided between each of the color filters. It is okay.

[0076] As shown in FIG. 57B, the boundaries of the lenses in the microlens array 1540 A light-shielding layer 1510 may be provided to cover the field.

[0077] Also, as shown in FIG. 57(C), the light shielding layer 1510 is omitted and the light control layer 64 is It may also be configured to extend between the color filters.

[0078] Also, as shown in FIG. 57(D), the light shielding layer 1510 is omitted and the light control layer 64 is a micro-layer. The optical filter 152 may extend between the lenses in the lens array 1540 .

[0079] As shown in FIG. 61(A), the light control layer 64 is formed over the entire depth of the photodiode 60. Instead, the side of the photodiode 60 is covered in part on the side closer to the light receiving surface. Also, as shown in FIG. 61(B), in a part on the side far from the light receiving surface, The region 66 may be formed so as to cover the side surface of the photodiode 60. It may be a part of the contact substrate 40 and may be a part of the configuration of the photodiode 60.

[0080] FIG. 62(A) shows a top view of the photodiode 60 and the light control layer 64. FIG. 62(B) shows a top view of the light-shielding layer 1510. FIG. 62(C) shows the top view of the color filter 1530. FIG. 62(D) shows the circuit diagram of FIG. 62(A), (B), (C) and the circuit 91. The transistor 50 included in the circuit 91 is shown overlapping. Since it can be formed overlapping the photodiode 60, the aperture ratio of the photodiode 60 is can be increased.

[0081] A support substrate 1600 is provided in contact with the fourth layer 1400. The support substrate 1600 is , semiconductor substrates such as silicon substrates, glass substrates, metal substrates, ceramic substrates and other hard substrates A bonding layer may be provided between the fourth layer 1400 and the support substrate 1600. Inorganic insulating layers and organic resin layers may be formed.

[0082] The circuit 91 and the circuit 92, as well as an external power supply circuit, a control circuit, and the like, are arranged on the fourth layer 1400. The connection can be made using the wiring layer 72 or the wiring layer 73 in the above.

[0083] In the configuration of the imaging device, the color filters 1530a, 1530b, and In addition, an optical conversion layer 1550 (see FIG. 2B) is used instead of the color filter 1530c. This makes it possible to provide an imaging device capable of obtaining images in various wavelength regions.

[0084] For example, if a filter that blocks light with wavelengths shorter than visible light is used for the optical conversion layer 1550, infrared The optical conversion layer 1550 can be used as an imaging device. If a filter having such a structure is used, a far-infrared imaging device can be obtained. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0085] In the case of an infrared imaging device, the band gap of the photoelectric conversion layer of the photodiode 60 is Germanium may be added to narrow the gap and improve sensitivity to infrared light. In addition, when an ultraviolet imaging device is used, a wide band gap oxide semiconductor layer is used as a photoelectric conversion layer. It may be used in a conversion layer to improve sensitivity to ultraviolet light.

[0086] In addition, if a scintillator is used for the optical conversion layer 1550, it is possible to use a radiation detector such as an X-ray imaging device. It is possible to make an imaging device that can obtain an image that visualizes the strength of lines. When radiation strikes a scintillator, it emits a large amount of light due to a phenomenon called photoluminescence. The light is converted into visible light, ultraviolet light, or other light (fluorescence). The light is then input to a photodiode 6. Image data is obtained by detecting the radiation at 0. An imaging device may also be used.

[0087] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy and It is made of a substance that emits visible or ultraviolet light or a material that contains such a substance. For example, Gd2O 2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, C Materials such as sI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, and their It is known to be dispersed in resins and ceramics.

[0088] FIG. 3 is a conceptual diagram showing the configuration of an imaging device. Circuit 1730 and circuit 1740 are arranged on the side. Circuit 1730 is, for example, a reset circuit. In this case, the circuit 1730 and the circuit 1731 shown in FIG. 1(B) is electrically connected to the transistor 55 in the circuit 1740. In this case, the circuit 1740 can function as a driver circuit for the transfer transistor. The transistor 52 in FIG. 1B is electrically connected to the circuit 17 in FIG. Although the configuration in which the circuit 130 and the circuit 1740 are arranged separately is shown in the figure, the circuit 1 730 and circuit 1740 may be arranged together.

[0089] A circuit 1750 is connected to the pixel matrix 1700. The circuit 1750 includes, for example, The transistor 54 functions as a driver for selecting a vertical output line electrically connected thereto. It is possible.

[0090] A circuit 1760 may also be connected to the pixel matrix 1700. The circuit 1760 includes: For example, the circuit 1750 may have a function such as a divided circuit, a power supply circuit, or a memory circuit. Note that a configuration in which the circuit 1760 is not provided is also possible.

[0091] An example of the specific positional relationship of the above circuits is shown in FIG. Each of circuit 1740, circuit 1750, and circuit 1760 is provided in, for example, four regions. The positions and areas of the circuits are not limited to those shown in the figures. A pixel matrix 1700 is provided inside the region in which the circuits 1730, The circuit 1740, the circuit 1750, the circuit 1760 and the pixels included in the pixel matrix 1700 Signal lines and power lines connected to the respective circuits are formed on the silicon substrate 40. The wiring is electrically connected to the terminal 1 formed around the silicon substrate 40. The terminal 1770 formed on the silicon substrate 40 is electrically connected to the wire bond 770. The device can be electrically connected to an external circuit via a wiring or the like.

[0092] The circuit 1730 and the circuit 1740 are drive circuits for binary output of "Low" or "High." Therefore, as shown in FIG. 4(A), a shift register 1800 and a buffer circuit It can be driven in 1900 combinations.

[0093] In addition, the circuit 1750 includes a shift register 1810 and a buffer circuit as shown in FIG. Each vertical output line 21 can be configured by a signal line 2100 and an analog switch 2100. 10 is selected by the analog switch 2100, and the potential of the selected vertical output line 2110 The analog switch 2100 is connected to the shift register 1810. The buffer circuit 1910 selects the corresponding bits in sequence.

[0094] In one embodiment of the present invention, all or a portion of circuit 1730, circuit 1740, and circuit 1750 In other words, the shift register 1800, the buffer circuit 1900, a shift register 1810, a buffer circuit 1910, and an analog switch 2 All or any of 100 is a p-ch type transistor having an active region in a silicon substrate 40. A CMOS circuit consisting of n-channel transistors with an oxide semiconductor layer as the active layer and has.

[0095] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. For example, although an example in which the present invention is applied to an imaging device has been shown as one embodiment of the present invention, One aspect of the present invention is not limited to this. The present invention may be applied to a device other than an imaging device. The present invention may be applied to a semiconductor device.

[0096] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0097] (Embodiment 2) In this embodiment mode, the circuit 91 described in Embodiment Mode 1 will be described.

[0098] FIG. 5A shows the details of the circuit 91 shown in FIG. 1B and the connection between various wirings. The circuit shown in (A) includes a photodiode 60, a transistor 52, a transistor 54, and a transistor The configuration includes a transistor 55 and a transistor 56 .

[0099] The anode of the photodiode 60 is connected to the wiring 316, and the cathode is connected to the transistor 52. The source or drain of the transistor 52 is connected to The other end is connected to the charge storage unit (FD), and the gate is connected to the wiring 312 (TX). Either the source or the drain of the transistor 54 is connected to the wiring 314 (GND). The other of the source and drain of the transistor 55 is connected to the source or drain of the transistor 56. The gate is connected to the charge storage portion (FD). One end is connected to the charge storage unit (FD), and the other end of the source or drain is connected to the wiring 317. The source or drain of the transistor 56 is connected to the wiring 311 (RS). The other input is connected to the wiring 315 (OUT), and the gate is connected to the wiring 313 (SE). All of the above connections are electrical connections.

[0100] The wiring 314 may be supplied with a potential such as GND, VSS, or VDD. Here, potential and voltage are relative. Therefore, the magnitude of the GND potential is not necessarily , is not necessarily 0 volts.

[0101] The photodiode 60 is a light receiving element that generates a current according to the light incident on the pixel circuit. The transistor 52 can function as a charge storage by the photodiode 60. The transistor 54 can have a function of controlling charge accumulation in the FD. It can have a function of outputting a signal according to the potential of the charge storage portion (FD). The transistor 55 has a function of resetting the potential of the charge storage unit (FD). The transistor 56 operates to control the selection of the pixel circuit during readout. It can have a function.

[0102] The charge storage section (FD) is a charge holding node, and the charge stored in the charge storage section (FD) is stored in the charge storage node (FD) when the photodiode 60 receives light. The charge held by the charger varies depending on the amount of

[0103] The transistor 54 and the transistor 56 are directly connected between the wiring 315 and the wiring 314. The wiring 314, the transistor 54, the transistor 56, the wiring 3 Alternatively, the wiring 314, the transistor 56, the transistor 54, the wiring 315, They may be arranged in the order of 15.

[0104] The wiring 311 (RS) functions as a signal line for controlling the transistor 55. The wiring 312 (TX) can be used as a signal line for controlling the transistor 52. The wiring 313 (SE) can have a function of controlling the transistor 56. The wiring 314 (GND) can function as a reference potential (for example, For example, the wiring 315 (OUT) can function as a signal line for setting a ground potential (GND). has a function as a signal line for reading out the signal output from the transistor 54. The wiring 316 is connected to the charge storage unit (FD) via the photodiode 60. In the circuit of FIG. 5(A), The wiring 317 is a signal for resetting the potential of the charge storage unit (FD). It can function as a signal line, and is a high-potential line in the circuit of FIG.

[0105] The circuit 91 may have a structure shown in FIG. The circuit and components shown in FIG. 5(A) are the same, but the anode of the photodiode 60 is turned on. The photodiode 60 is electrically connected to one of the source and drain of the phototransistor 52. The difference is that the cathode of the photodiode is electrically connected to the wiring 316. In this case, the wiring 316 is It functions as a signal line for supplying charge to the charge storage unit (FD) via the charge diode 60. 5B, the wiring 317 is a low potential line. become.

[0106] Next, the configuration of each element shown in FIGS. 5(A) and 5(B) will be described.

[0107] The photodiode 60 has a pn-type or pin-type junction formed on a silicon substrate. The element can be used.

[0108] Transistor 52, transistor 54, transistor 55, and transistor 56 are Silicon semiconductors such as amorphous silicon, microcrystalline silicon, polycrystalline silicon, and single crystal silicon However, it is possible to form the transistor using an oxide semiconductor. A transistor in which a channel formation region is formed using an oxide semiconductor is extremely It has the characteristic of exhibiting low leakage current.

[0109] In particular, the transistors 52 and 55 connected to the charge storage unit (FD) If the leakage current is large, the charge stored in the charge storage section (FD) cannot be held for a sufficient period of time. Therefore, at least two of the transistors are made of an oxide semiconductor. By using a transistor, unnecessary charge leakage from the charge storage section (FD) is prevented. can be done.

[0110] In addition, when the leakage current of the transistor 54 and the transistor 56 is large, the arrangement Since unnecessary charge is output to the line 314 or the wiring 315, these transistors and It is preferable to use a transistor in which a channel formation region is formed using an oxide semiconductor. .

[0111] An example of the operation of the circuit in FIG. 5A will be described with reference to the timing chart in FIG. 6A. Reveal.

[0112] For ease of explanation, the potential of each wiring is given as a signal that changes into two values ​​in FIG. However, since each potential is an analog signal, in reality it can be any value, not just two, depending on the situation. In addition, the signal 701 shown in the figure is the potential of the wiring 311 (RS), and the signal 702 is the potential of the wiring 312 (TX), signal 703 is the potential of wiring 313 (SE), and signal 704 is the charge accumulation The potential of the portion (FD) and the signal 705 correspond to the potential of the wiring 315 (OUT). The potential of the wiring 16 is always "Low", and the potential of the wiring 317 is always "High".

[0113] At time A, the potential of the wiring 311 (signal 701) is set to “High” and the potential of the wiring 312 ( When the signal 702) is set to "High", the potential of the charge storage section (FD) (signal 704) The potential of the wiring 317 is initialized to “High” and the reset operation is started. The potential of 15 (signal 705) is precharged to "High".

[0114] At time B, when the potential of the wiring 311 (signal 701) is set to “Low”, a reset operation is performed. At this point, a reverse bias is applied to the photodiode 60. As a result, the potential (signal 704) of the charge storage section (FD) begins to decrease due to a reverse current. When light is irradiated, the reverse current of the photodiode 60 increases. The rate at which the potential (signal 704) of the charge storage section (FD) drops varies depending on the amount of light received. That is, the source and drain of transistor 54 are turned on and off depending on the amount of light incident on photodiode 60. The channel resistance between the drains changes.

[0115] At time C, when the potential of the wiring 312 (signal 702) is set to “Low”, the accumulation operation ends. The electric potential (signal 704) of the charge storage section (FD) is constant. It is determined by the amount of charge generated by the photodiode 60 during operation. The amount of light incident on the transistor 52 and the transistor 60 changes depending on the amount of light incident on the transistor 52. The transistor 55 has a channel formation region formed of an oxide semiconductor layer and has an extremely low off-state current. Since it is composed of transistors, charge is stored until the subsequent selection operation (read operation) is performed. It is possible to keep the potential of the portion (FD) constant.

[0116] When the potential of the wiring 312 (signal 702) is set to “Low”, the wiring 312 and the charge accumulation The potential of the charge storage section (FD) changes due to the parasitic capacitance between the charge storage section (FD) and the If the change in the potential is large, the photodiode 60 generates a charge during the accumulation operation. In order to reduce the amount of change in the potential, The gate-source (or gate-drain) capacitance of the transistor 52 is reduced. Measures such as increasing the gate capacitance of the gate electrode 54 and providing a storage capacitance in the charge storage section (FD) In this embodiment, these measures are effective in making the change in potential negligible. It is intended to be.

[0117] At time D, when the potential of the wiring 313 (signal 703) is set to “High”, the transistor 56 The wiring 314 and the wiring 315 are connected to the transistor 54 and the transistor Then, the potential of the wiring 315 (signal 705) drops. The precharging of the wiring 315 should be completed before time D. The rate at which the potential of the wiring 315 (signal 705) drops depends on the source and drain of the transistor 54. That is, the current that is irradiated onto the photodiode 60 during the accumulation operation depends on the Changes depending on the amount of light.

[0118] At time E, when the potential of the wiring 313 (signal 703) is set to “Low”, the transistor 56 is cut off, the selection operation ends, and the potential of the wiring 315 (signal 705) becomes constant. The value changes depending on the amount of light that is irradiated onto the photodiode 60. By acquiring the potential of the wiring 315, the light irradiated to the photodiode 60 during the accumulation operation can be You can see the amount of light.

[0119] More specifically, when the light irradiating the photodiode 60 is strong, the charge storage unit (FD ), i.e., the gate voltage of transistor 54, drops. The current flowing between the source and drain of 54 becomes smaller, and the potential of the wiring 315 (signal 705) Therefore, a relatively high potential can be read out from the wiring 315. can.

[0120] Conversely, when the light irradiated to the photodiode 60 is weak, the potential of the charge storage section (FD) That is, the gate voltage of the transistor 54 becomes high. The current flowing between the source and drain becomes large, and the potential of the wiring 315 (signal 705) drops quickly. Therefore, a relatively low potential can be read out from the wiring 315.

[0121] Next, an example of the operation of the circuit in FIG. 5B will be described with reference to the timing chart in FIG. 6B. The potential of the wiring 316 is always “High”, and the potential of the wiring 317 is always “L”. ow”.

[0122] At time A, the potential of the wiring 311 (signal 701) is set to “High” and the potential of the wiring 312 ( When the signal 702) is set to "High", the potential of the charge storage section (FD) (signal 704) The potential of the wiring 317 is initialized to "Low" and the reset operation is started. The potential of 5 (signal 705) is precharged to "High".

[0123] At time B, when the potential of the wiring 311 (signal 701) is set to “Low”, a reset operation is performed. At this point, a reverse bias is applied to the photodiode 60. As a result, the potential (signal 704) of the charge storage section (FD) begins to rise due to a reverse current. Can.

[0124] For the operation after time C, refer to the explanation of the timing chart in FIG. 6(A). At time E, the potential of the wiring 315 is acquired, so that the photodiode 60 This allows you to know the amount of light that was being irradiated onto the object.

[0125] The circuit 91 may have a configuration shown in FIGS.

[0126] The circuit shown in FIG. 7A is the same as the circuit shown in FIG. 6 and wiring 317 are omitted, and wiring 311 (RS) is The other components are the same as those of the circuit shown in FIG.

[0127] The circuit shown in FIG. 7(B) has the same components as the circuit shown in FIG. 7(A), but the photodiode The anode of the electrode 60 is electrically connected to either the source or the drain of the transistor 52. At the point where the cathode of the photodiode 60 is electrically connected to the wiring 311 (RS), different.

[0128] The circuit of FIG. 7(A) is similar to the circuit of FIG. 5(A) in the timing chart shown in FIG. 6(A). It can be made to work.

[0129] At time A, the potential of the wiring 311 (signal 701) is set to “High” and the potential of the wiring 312 ( When the signal 702) is set to "High", a forward bias is applied to the photodiode 60. As a result, the potential (signal 704) of the charge storage unit (FD) becomes “High”. The potential of the integrated circuit (FD) is initialized to the potential ("High") of the wiring 311 (RS). This is the start of the reset operation. ) is precharged to "High".

[0130] At time B, when the potential of the wiring 311 (signal 701) is set to “Low”, a reset operation is performed. At this point, a reverse bias is applied to the photodiode 60. As a result, the potential (signal 704) of the charge storage section (FD) begins to decrease due to a reverse current. Can.

[0131] For the operation after time C, refer to the explanation of the circuit operation in FIG. 5(A). By acquiring the potential of the wiring 315, the light irradiated to the photodiode 60 during the accumulation operation is You can see the amount of light being received.

[0132] The circuit in FIG. 7B can be operated according to the timing chart shown in FIG. 6C.

[0133] At time A, the potential of the wiring 311 (signal 701) is set to “Low” and the potential of the wiring 312 (signal When the signal 702) is set to "High", a forward bias is applied to the photodiode 60. Then, the electric potential (signal 704) of the charge storage unit (FD) is reset to "Low". This is the start of the reset operation. Note that the potential of the wiring 315 (signal 705) is set to "High". Precharge it.

[0134] At time B, when the potential of the wiring 311 (signal 701) is set to “High”, a reset operation is performed. Then, the accumulation operation is started. At this point, the photodiode 60 is reverse biased. As a result, the potential (signal 704) of the charge storage section (FD) rises due to the reverse current. start.

[0135] For the operation after time C, refer to the explanation of the circuit operation in FIG. 5(A). By acquiring the potential of the wiring 315, the light irradiated to the photodiode 60 during the accumulation operation is You can see the amount of light being received.

[0136] In addition, in FIGS. 5(A), (B) and 7(A), (B), a transistor 52 is provided. 8A and 8B, an example in which the ion exchange layer 14 is formed is shown, but one embodiment of the present invention is not limited to this. It is also possible to omit transistor 52, as shown in FIG.

[0137] The transistor used in the circuit 91 is, as shown in FIG. A structure in which the transistor 52, the transistor 54, and the transistor 56 are provided with back gates. FIG. 9(A) shows a configuration in which a constant potential is applied to the back gate, and the threshold In addition, the back gate is at the same potential as the front gate in Figure 9(B). This is a configuration in which the voltage is applied to the terminal, and the on-current can be increased. In the above example, the back gate is electrically connected to the wiring 314 (GND). Alternatively, the electrode may be electrically connected to another wiring to which a constant potential is supplied. B) shows an example in which a back gate is provided to a transistor in the circuit shown in FIG. The same configuration is also applicable to the circuits shown in Figs. 5(A), (B), 7(B), 8(A), and (B). In addition, a front gate can be used for the transistors included in one circuit. a structure in which the same potential as that of the back gate is applied to the back gate, a structure in which a constant potential is applied to the back gate, or Alternatively, a circuit configuration may be used in which a back gate is not provided or a configuration in which a back gate is not provided is combined as necessary. stomach.

[0138] In the above-described circuit example, the wiring 315 (OUT) is An integrating circuit as shown in C) may be connected. The S / N ratio can be increased, and weaker light can be detected. This can increase the sensitivity of the device.

[0139] FIG. 10(A) shows an integrator circuit using an operational amplifier circuit (also called an OP amp). The inverting input terminal of the width circuit is connected to the wiring 315 (OUT) via a resistor element R. The non-inverting input terminal of the amplifier circuit is connected to the ground potential. The output terminal of the operational amplifier circuit is connected to the capacitance It is connected to the inverting input terminal of the operational amplifier circuit via element C.

[0140] FIG. 10B shows an integrating circuit using an operational amplifier circuit having a different configuration from that shown in FIG. 10A. The inverting input terminal of the operational amplifier circuit is connected to the wiring 315 (OUT The non-inverting input terminal of the operational amplifier circuit is connected to the ground potential. The output terminal of the path is connected to the inverting input terminal of the operational amplifier circuit via a capacitive element C2.

[0141] FIG. 10(C) shows a configuration of an operational amplifier circuit different from that shown in FIG. 10(A) and FIG. 10(B). The non-inverting input terminal of the operational amplifier circuit is connected to the wiring 315 ( The output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier. The resistor R and the capacitor C constitute a CR integrator circuit. The path constitutes a unity gain buffer.

[0142] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0143] (Embodiment 3) In this embodiment, a transistor for initializing the potential of the charge storage unit (FD), FD) and each wiring (signal line) between pixels ( The circuit configuration when the circuit 91 is used for both purposes will be described.

[0144] The pixel circuit shown in FIG. 11 includes a transistor 52 (transfer transistor) similar to the circuit shown in FIG. transistor 53 (functions as an amplifier transistor); transistor 54 (functions as an amplifier transistor); 55 (functions as a reset transistor), transistor 56 (functions as a selection transistor Each pixel has a photodiode 60 and a wiring 311 (transistor). 3, a wiring 312 (functioning as a signal line for controlling the transistor 52) and a wiring 313 (functioning as a signal line for controlling the transistor 55). wiring 313 (functioning as a signal line for controlling transistor 56); 313 (functions as a high-voltage line), wiring 314 (functions as a high-voltage line), wiring 315 (transistor 54 315 (functions as a signal line for reading out a signal output from the A pixel circuit (functioning as a neutral density pixel) is electrically connected to the pixel circuit.

[0145] In the circuit shown in FIG. 5A, the wiring 314 is a GND line and the wiring 317 is a high potential line. In the pixel circuit, the wiring 314 is a high-potential line (for example, VDD), and the wiring The other of the source and drain of the transistor 56 is connected to the wiring 314. Also, the wiring 315 (OUT) is reset to a low potential.

[0146] Between the pixel circuits on the first line and the pixel circuits on the second line, wiring 3 is provided as shown below. 14, wiring 315, and wiring 316 can be shared, and depending on the operation method, wiring 31 can be used. 1 can also be shared.

[0147] FIG. 12 shows four pixels in the first to fourth lines adjacent in the vertical direction, each of which has a transistor 5 4. A vertical 4-pixel shared transistor 55, a transistor 56, and a wiring 311 The figure shows the structure of the type. The reduction in the pixel area due to the reduction in transistors and wiring This allows for miniaturization and improved yield. The other of the source or drain of the transistor 52 and the source or drain of the transistor 55 One of the inputs and the gate of the transistor 54 are electrically connected to the charge storage section (FD). The transistor 52 of each pixel is operated in sequence, and the accumulation operation and the readout operation are repeated. This allows data to be obtained from all pixels.

[0148] FIG. 13 shows the transistors 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 8 A vertical / horizontal 4-channel transistor 55, a vertical / horizontal 4-channel transistor 56, a wiring 313, and a wiring 311 are used in combination. The pixel sharing type configuration is shown. As with the vertical 4-pixel sharing type, the transistors and wiring are By reducing the number of pixels, it is possible to reduce the pixel area and improve the yield. and the sources or drains of the transistors 52 in the four vertically adjacent pixels. the other terminal of the transistor 54, the source or drain terminal of the transistor 55, and the gate terminal of the transistor 54. The gate is electrically connected to the charge storage unit (FD). By repeating the accumulation and readout operations, data can be obtained from all pixels. This can be done.

[0149] FIG. 14 shows the transistors 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 8 A transistor 55, a transistor 56, a wiring 311, and a structure in which wirings 312 and 314 are used together This is a circuit in which the wiring 312 is further shared in the above-mentioned vertical and horizontal four-pixel shared type. Four pixels adjacent in the horizontal and vertical directions (the first row is two pixels adjacent in the horizontal direction) The other of the source or drain of the transistor 52 in Alternatively, one of the drains and the gate of the transistor 54 are electrically connected to the charge storage portion (FD). This circuit configuration also uses two vertically positioned transfer transistors. (Transistor 52) share the wiring 312, so that It is characterized by having transistors that operate in both directions simultaneously.

[0150] Although it is different from the above-mentioned form of sharing the transistor and the signal line, a photodiode It is also possible to configure the pixel circuit to have a plurality of gates.

[0151] For example, in the pixel circuit shown in FIG. or between one of the drains of the photodiodes 60a, 60b, and 60c and the transistor. The transistors 58a, 58b, and 58c are As switches for selecting the photodiodes 60a, 60b, and 60c connected to the respective In FIG. 15, the photodiode and the switch functions are Although the number of combinations of transistors is three in the above example, the present invention is not limited to this. For example, as shown in FIG. 15(B), it is possible to use two. Of course, it is also possible to use four or more. That's fine too.

[0152] As an example, the photodiodes 60a, 60b, and 60c each have a sensitivity to illuminance. can be used for various environments from low light to high light. For example, a photodiode for high illumination has a characteristic that is suitable for imaging in high illumination. A combination of neutral density filters can be used so that the output has linearity. It should be noted that a plurality of photodiodes may be selected and operated.

[0153] In addition, the photodiodes 60a, 60b, and 60c each have a different sensitivity to a wavelength. It is possible to use materials that have the characteristics of being able to emit light with a wide wavelength range, from ultraviolet light to far infrared light. For example, a filter that transmits the wavelength range to be detected and a photo By combining diodes, imaging using ultraviolet light, visible light, and infrared light can be performed. It is possible to switch between different modes such as imaging.

[0154] In addition, the pixel circuit uses multiple photodiodes with different light receiving area. In a configuration having two photodiodes, for example, the light receiving area is 1:10 or 1: 100, etc. In a photodiode, the series resistor The output current value may become saturated due to the influence of the load. In this case, according to Ohm's law, The smaller the current value, the better the linearity with respect to the illuminance. Therefore, the sensitivity is usually high. In high-illumination environments, the area of ​​the light-receiving part of the photodiode is large, so that the light receiving area is large. This allows for high sensitivity and This makes it possible to provide an imaging device with a wide dynamic range.

[0155] In addition, in the case of a pixel configuration having photodiodes with different light receiving area, As shown in FIG. 1C, one pixel 90 has photodiodes 60a and 60b with different areas. In addition to the above, as shown in FIG. 15(D), a photodiode 6 having a different area for each pixel 90 may be used. 0a and 60b may be arranged alternately.

[0156] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0157] (Embodiment 4) In this embodiment, an example of a method for driving a pixel circuit will be described.

[0158] As described in the second embodiment, the operation of the pixel circuit is a reset operation, a storage operation, and a selection operation. The image capturing method that controls the entire pixel matrix is ​​called the global The shutter type and the rolling shutter type are known.

[0159] FIG. 16A is a timing chart in the global shutter system. 16(A) has a plurality of pixel circuits arranged in a matrix, and the pixel circuits are provided with the circuit shown in FIG. As an example of an imaging device having the above-mentioned configuration, the pixel circuits in the first row to the nth row (n is a natural number of 3 or more) are The following operation description is based on Figs. 5(B), 7(A), and ), and also the circuits shown in FIGS. 8(A) and (B).

[0160] In FIG. 16A, signals 501, 502, and 503 are in the first row, the second row, This is a signal input to the wiring 311 (RS) connected to each pixel circuit in the nth row. Signals 504, 505, and 506 are supplied to the pixel circuits in the first, second, and n-th rows. Signals 507 and 508 are signals input to the connected wiring 312 (TX). The signal 509 is applied to the wiring 313 ( This is the signal input to the NI 8110.

[0161] A period 510 is a period required for one image capture. A period 511 is a period required for the pixels in each row. The period 520 is a period in which the circuits are simultaneously performing a reset operation. The selection operation is performed sequentially in the pixel circuits of each row. As an example, a period 531 is a period during which the pixel circuits in the first row are performing a selection operation. In this way, in the global shutter method, the reset operation is performed almost simultaneously in all pixel circuits. After this, accumulation operations are performed almost simultaneously in all pixel circuits, and readout operations are performed sequentially for each row. can be.

[0162] In other words, in the global shutter method, accumulation operations are performed in all pixel circuits at approximately the same time. Since the pixel circuits in each row are aligned in parallel, the image pickup is performed simultaneously. Even if the object is moving, an image with little distortion can be obtained.

[0163] On the other hand, FIG. 16B is a timing chart when the rolling shutter method is used. For the signals 501 to 509, see the explanation of FIG. 16(A). 10 is the period required for one image capture. , the first row, the second row, and the nth row. , and period 623 are accumulation operation periods for the first row, the second row, and the nth row, respectively. A period 631 is a period during which the pixel circuits in the first row are performing a selection operation. In the ring shutter method, the accumulation operation is not performed simultaneously in all pixel circuits, but sequentially for each row. Therefore, the image pickup in the pixel circuits of each row cannot be performed simultaneously. Since the timing of capturing images is different between the first and last lines, images with large distortion may be captured if the subject is moving. It becomes a statue.

[0164] To realize the global shutter system, the signal readout from each pixel must be completed sequentially. The electric potential of the charge storage section (FD) must be maintained for a long time until the electric potential of the charge storage section (FD) The long-term retention of the transistor 52 and the like is achieved by forming a channel formation region using an oxide semiconductor. This can be achieved by using a transistor with extremely low off-state current. When a transistor with a channel formation region made of silicon or the like is used, Because the current is high, the potential of the charge storage section (FD) cannot be maintained for a long time, and the global shutter method It becomes difficult to use the formula.

[0165] As described above, a transistor in which a channel formation region is formed using an oxide semiconductor is used for a pixel circuit. This makes it easy to realize the global shutter method.

[0166] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0167] (Embodiment 5) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be given with reference to the drawings. Note that, in the drawings in this embodiment, the For ease of illustration, some elements may be enlarged, reduced, or omitted.

[0168] 17A and 17B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. The cross section taken along the dashed line B1-B2 in FIG. 17(A) corresponds to FIG. 17(B). In addition, the cross section taken along the dashed line B3-B4 shown in FIG. , the dashed line B1-B2 direction is the channel length direction, and the dashed line B3-B4 direction is the channel width direction. It may be referred to as.

[0169] The transistor 101 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; layer 150, the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 1 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. In addition, an insulating layer 190 (flattening film) that contacts the insulating layer 180 may be formed as necessary. It may have.

[0170] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0171] In addition, a region 231 shown in FIG. 17B is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are conductive regions. The conductive layers 140 and 150 are in contact with each other. If a conductive material that easily bonds with oxygen is used as the electrode, the resistance of the region 231 and the region 232 can be reduced. It is possible.

[0172] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The n-type of the resistor.

[0173] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. In addition, the term "electrode layer" can be replaced with "wiring." can.

[0174] In addition, the conductive layer 170 is illustrated as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0175] In addition, although the conductive layer 140 and the conductive layer 150 are illustrated as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may be applied to other transistors described in this embodiment. can.

[0176] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 18A is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 18(B). Also, the dashed line C3 shown in FIG. The cross section in the -C4 direction corresponds to FIG. 23(B). The direction of the dashed dotted line C3-C4 may be referred to as the channel length direction, and the direction of the dashed dotted line C3-C4 may be referred to as the channel width direction.

[0177] The transistor 102 is formed by connecting the end of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the ends of the conductive layer 170 acting as a gate electrode are not aligned with each other. The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layer 140, the conductive layer 150, and the conductive layer 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0178] The transistor 101 and the transistor 102 are formed by a conductive layer 170, a conductive layer 140, and a conductive The top gate structure has a region where the gate insulating layer 150 overlaps the gate insulating layer 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce parasitic capacitance. On the other hand, since no offset region is formed in the oxide semiconductor layer 130, a transistor with a high on-current is formed. It is easy to form a transistor.

[0179] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 19A is a top view of the transistor 103. The cross section in the 1-D2 direction corresponds to FIG. 19(B). The cross section in the -D4 direction corresponds to FIG. 23(A). The direction of the dashed dotted line D3-D4 may be referred to as the channel length direction, and the direction of the dashed dotted line D3-D4 may be referred to as the channel width direction.

[0180] The transistor 103 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. An edge layer 175, an insulating layer 180 in contact with the insulating layer 175, and a layer including the insulating layer 175 and the insulating layer 180. A conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. In addition, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer 190 (planarizing film) in contact with 150 may also be provided.

[0181] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0182] In addition, a region 231 shown in FIG. 19B is a source region, a region 232 is a drain region, and a region 2 Region 231 and region 232 are insulators. If an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0183] Specifically, the process up to the formation of the insulating layer 175 generates a thin film in the region 231 and the region 232. The oxygen vacancies caused by the oxygen vacancies interact with hydrogen diffusing from the insulating layer 175 into the regions 231 and 232. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, a silicon nitride film or an aluminum nitride film can be used.

[0184] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 20A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 20(B). Also, the dashed line E3 shown in FIG. The cross section in the -E4 direction corresponds to FIG. 23(A). The direction of the dashed dotted line E3-E4 may be referred to as the channel length direction, and the direction of the dashed dotted line E3-E4 may be referred to as the channel width direction.

[0185] In the transistor 104, the conductive layer 140 and the conductive layer 150 are disposed at the end of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0186] In addition, the regions 331 and 334 shown in FIG. 20B are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. Regions 331 and 332 correspond to regions 231 and 232 in transistor 101. The resistance can be reduced in the same manner as in the case of the transistor 2. The resistance can be reduced in the same manner as in the region 231 and the region 232 in the capacitor 103. The length of the region 334 and the region 335 in the channel length direction is preferably 100 nm or less. For a thickness of 50 nm or less, the on-current does not decrease significantly due to the contribution of the gate electric field. Alternatively, the above-mentioned resistance reduction may not be performed.

[0187] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. This makes it suitable for high-speed operation.

[0188] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 21A is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 21(B). Also, the dashed line F3 shown in FIG. The cross section in the -F4 direction corresponds to FIG. 23(A). The dashed line F1-F2 direction corresponds to the channel length The direction indicated by the dashed dotted line F3-F4 may be referred to as the channel width direction.

[0189] The transistor 105 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151; The conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175 in contact with insulating layer 175; The insulating layer 175 and the insulating layer 180 are electrically conductive through openings provided in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer 190 (planarizing film) may be provided.

[0190] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0191] The transistor 105 includes a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening provided in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0192] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 22A is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 22(B). The cross section in the -G4 direction corresponds to FIG. 23(A). The direction of the dashed dotted line G3-G4 may be referred to as the channel length direction, and the direction of the dashed dotted line G3-G4 may be referred to as the channel width direction.

[0193] The transistor 106 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; a conductive layer 151, an insulating layer 160 in contact with the oxide semiconductor layer 130, and a conductive layer 162 in contact with the insulating layer 160; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. The conductive layer 141 and the conductive layer 142 are formed through the openings provided in the insulating layer 175 and the insulating layer 180. The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, the insulating layer 180, the conductive layer 142, and the insulating layer 190 (flat) in contact with the conductive layer 152 are The substrate may have a support film, etc.

[0194] Here, the conductive layer 141 and the conductive layer 151 are in contact with the upper surface of the oxide semiconductor layer 130 and The structure is such that it does not come into contact with

[0195] The transistor 106 has the same structure as the transistor 106 except that it has a conductive layer 141 and a conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has a structure similar to that of the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 15 2) can act as a drain electrode layer.

[0196] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 Since the insulating layer 120 is not in contact with the conductive layer 140, the oxygen in the insulating layer 120 is The oxide semiconductor layer 130 is less likely to be deprived of oxygen by the conductive layer 150. This makes it easier to supply the raw material.

[0197] In addition, the region 231 and the region 232 in the transistor 103, the transistor 104, In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed and the conductor is formed. Impurities that cause oxygen vacancies in the oxide semiconductor layer may be added. Examples of the elements include phosphorus, arsenic, antimony, boron, aluminum, silicon, and nitrogen. , helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium One or more selected from the group consisting of titanium, zinc, and carbon can be used. Methods for adding impurities include plasma treatment, ion implantation, ion doping, and plasma A Zumai immersion ion implantation method or the like can be used.

[0198] When the above-mentioned element is added to the oxide semiconductor layer as an impurity element, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes an oxide The conductivity of the semiconductor layer can be increased.

[0199] When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed by the addition of an impurity element, Hydrogen enters the oxygen vacancy site and a donor level is formed near the conduction band. Note that the oxide semiconductor that has been made a conductor can be called an oxide conductor. It is called an electric body.

[0200] An oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a gate electrode is an ohmic contact. In addition, the contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer can be reduced.

[0201] In addition, the transistor according to one embodiment of the present invention is shown in FIG. The cross-sectional views in the channel length direction shown in Figs. 26(A), (B), and (C) and the cross-sectional views in Figs. 26(A) and (B) are shown. As shown in the cross-sectional view in the channel width direction in FIG. The conductive layer 173 may be a second gate electrode layer (back gate). By using it as a gate, it is possible to further increase the on-current and control the threshold voltage. In addition, the cross sections shown in Figures 24(A), (B), (C) and Figures 25(A), (B), (C) In the figure, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. The width of the conductive layer 173 may be smaller than the width of the conductive layer 170 .

[0202] In order to increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and a double In order to control the threshold voltage, the MOSFET is driven as a gate transistor. A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 may be electrically connected via a contact hole.

[0203] In addition, in the transistors 101 to 106 in FIG. Although an example in which the oxide semiconductor layer 130 is a single layer is illustrated, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 is 28. Alternatively, it can be replaced with the oxide semiconductor layer 130 shown in FIG.

[0204] 27A, 27B, and 27C are top views of an oxide semiconductor layer 130 having a two-layer structure. The cross section taken along the dashed line A1-A2 shown in FIG. 27(A) corresponds to FIG. 27(B). In addition, the cross section along the dashed line A3-A4 shown in FIG. 27(A) corresponds to FIG. 27(C). do.

[0205] 28A, 28B, and 28C are top views of the oxide semiconductor layer 130 having a three-layer structure. 28(A) is a cross-sectional view taken along the dashed line A1-A2 in FIG. In addition, the cross section along the dashed line A3-A4 shown in FIG. 28(A) corresponds to FIG. 28(C). Equivalent.

[0206] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers having different compositions can be used.

[0207] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 29A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 29(B). Also, the dashed line H3 shown in FIG. The cross section in the -H4 direction corresponds to FIG. 35(A). The longitudinal direction, the direction of the dashed dotted line H3-H4, may be referred to as the channel width direction.

[0208] The transistor 107 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 140 and the conductive layer 150 connected to each other, 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170; and an insulating layer 180 in contact with the insulating layer 180. (flattening film) or the like.

[0209] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The conductive layer 140 and the conductive layer 150 are the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 101 .

[0210] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 30A is a top view of the transistor 108. The cross section in the 1-I2 direction corresponds to FIG. 30(B). Also, the dashed line I3 shown in FIG. The cross section in the -I4 direction corresponds to FIG. 35(B). The longitudinal direction, the direction of the dashed dotted line I3-I4, may be referred to as the channel width direction.

[0211] In the transistor 108, the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the end of 0.

[0212] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 31A is a top view of the transistor 109. The cross section in the 1-J2 direction corresponds to FIG. 31(B). The cross section in the -J4 direction corresponds to FIG. 35(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, may be referred to as the channel width direction.

[0213] The transistor 109 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. a second insulating layer 160 in contact with the oxide semiconductor layer 130c; 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covers the conductive layer 170, an insulating layer 180 contacts the insulating layer 175, and the insulating layer 175 is and a conductive layer 14 electrically connected to the stack through an opening in the insulating layer 180. 0 and conductive layer 150. Also, as required, insulating layer 180, conductive layer 140 and An insulating layer 190 (planarizing film) in contact with the conductive layer 150 may be provided.

[0214] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 103 has a similar structure to the transistor 103, except that the transistor 103 has a second insulating layer 130c.

[0215] The transistor of one embodiment of the present invention may have a structure shown in FIGS. FIG. 32A is a top view of the transistor 110. The cross section in the 1-K2 direction corresponds to FIG. 32(B). Also, the dashed line K3 shown in FIG. The cross section in the -K4 direction corresponds to FIG. 35(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, may be referred to as the channel width direction.

[0216] The transistor 110 has two oxide semiconductor layers 130 in the regions 331 and 332. In the region 333, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide The transistor 104 has a similar structure to the transistor 104, except that the transistor 104 has a second insulating layer 130c.

[0217] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 33A is a top view of the transistor 111. The cross section in the 1-L2 direction corresponds to FIG. 33(B). Also, the dashed line L3 shown in FIG. The cross section in the -L4 direction corresponds to FIG. 35(A). The longitudinal direction, the direction of the dashed dotted line L3-L4, may be referred to as the channel width direction.

[0218] The transistor 111 includes an insulating layer 120 in contact with a substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of an organic semiconductor layer 130a and an oxide semiconductor layer 130b, and The conductive layer 141 and the conductive layer 151 connected to each other, and the laminate, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the laminate, the conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 in contact with the insulating layer 175 and the openings provided in the insulating layer 175 and the insulating layer 180 are Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 may also include an insulating layer 180, a conductive layer 142, and a conductive layer 153. It may also have an insulating layer 190 (planarization film) in contact with 52.

[0219] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a first oxide semiconductor layer 130b. The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide and the conductive layer 141 and the conductive layer 151 and the insulating layer 160. Except for the fact that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between It has a similar configuration to the transistor 105 .

[0220] Further, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 34A is a top view of the transistor 112. The cross section in the 1-M2 direction corresponds to FIG. 34(B). Also, the dashed line M3 shown in FIG. The cross section in the -M4 direction corresponds to FIG. 35(A). Also, the direction of the dashed line M1-M2 is the channel The longitudinal direction, the direction of the dashed dotted line M3-M4, may be referred to as the channel width direction.

[0221] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (the oxide semiconductor layer 130a, the oxide 130a and 130b, and an oxide semiconductor layer 130c). They have a similar configuration.

[0222] In addition, the transistor according to one embodiment of the present invention is shown in FIG. The cross-sectional views in the channel length direction shown in Figs. 38(A), (B), and (C) and Figs. 38(A) and (B) show the As shown in the cross-sectional view in the channel width direction in FIG. The conductive layer may be a layer 173 serving as a second gate electrode layer (back gate). By using this, it is possible to further increase the on-current and control the threshold voltage. In the cross-sectional views shown in Figs. 36(A), (B), (C) and Figs. 37(A), (B), (C), In addition, the width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. The width of 173 may be smaller than the width of the conductive layer 170 .

[0223] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) has a structure as shown in the top view of FIGS. 39(A) and (B). 39A and 39B, the oxide semiconductor layer 130 and the conductive layer 140 As shown in FIG. 39(A), only the conductive layer 140 and the conductive layer 150 are shown. and the width (W SD ) is the width of the oxide semiconductor layer (W OS ) has been formed for longer than Also, as shown in FIG. SD W OS It is formed shorter than It is okay. OS ≧W SD (W SD W OS (below) the gate electric field is reduced by This makes it easier to apply the metal to the entire conductor layer 130, thereby improving the electrical characteristics of the transistor. do.

[0224] In the transistors of one embodiment of the present invention (transistors 101 to 112), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction via the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel transistor. This is called the (s-channel) structure.

[0225] In addition, a transistor having an oxide semiconductor layer 130b and an oxide semiconductor layer 130c, etc. In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In the transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By passing a current through the conductor layer 130b, the device is less susceptible to the effects of interface scattering and a high on-current can be obtained. In addition, by increasing the thickness of the oxide semiconductor layer 130b, the on-current can be improved. For example, the thickness of the oxide semiconductor layer 130b can be set to 100 nm to 200 nm. Good too.

[0226] By using a transistor having the above structure, good electrical characteristics are imparted to a semiconductor device. It is possible.

[0227] Note that in this specification, the channel length refers to, for example, the length of a semiconductor device when viewed from above in a top view of a transistor. A conductor (or the part of the semiconductor through which current flows when the transistor is on) and a gate The source (or source region) in the region where the electrode overlaps or the region where the channel is formed This refers to the distance between the source electrode (or drain region) and the drain (drain electrode). In addition, the channel length of a single transistor does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions in which the channel is formed. The value may be a maximum, minimum or average value.

[0228] The channel width is, for example, the width of the semiconductor (or the semiconductor when the transistor is in the on-state). The region where the gate electrode overlaps with the current-carrying part of the gate electrode, or the region where the channel is formed. This refers to the length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0229] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, When the gate electrode covers the side of the semiconductor, the effective channel width becomes larger than the apparent channel width. For example, when the gate electrode is In transistors where the side of the semiconductor is covered, the percentage of the channel area that is formed on the top surface of the semiconductor In contrast, the proportion of the channel region formed on the side of the semiconductor may be large. In this case, the effective channel width is larger than the apparent channel width.

[0230] In such a case, it may be difficult to estimate the effective channel width through actual measurement. For example, to estimate the effective channel width from the design value, the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known precisely, the effective It is difficult to measure channel width accurately.

[0231] Therefore, in this specification, the apparent channel width is defined as the "surrounding channel width (SCW)". In addition, in this specification, So, when we simply write "channel width," it means the enclosed channel width or the apparent channel width. In this specification, when the term "channel width" is used, it refers to the actual In addition, the channel length, channel width, and effective channel The width, apparent channel width, and enclosed channel width were determined by analyzing cross-sectional TEM images. The value can be determined by the following.

[0232] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0233] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0234] (Embodiment 6) In this embodiment, components of the transistor shown in the fifth embodiment will be described in detail. do.

[0235] The substrate 115 is a silicon substrate on which transistors and photodiodes are formed, and A conductor having functions as an insulating layer, wiring, and contact plug is formed on the silicon substrate. 1A and corresponds to the first layer 1100 and the second layer 1200 in FIG. When forming a p-ch transistor on a silicon substrate, n - Conductivity type It is preferable to use a silicon substrate having a thickness of 100 nm or less. - It has a type or i-type silicon layer. The substrate may be a SOI substrate. The surface orientation of the surface is preferably a (110) surface. By forming a star, the mobility can be increased.

[0236] The insulating layer 120 serves to prevent the diffusion of impurities from the elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The edge layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. For example, the surface temperature of the film is 100° C. or more and 700° C. or less. In the TDS method, which is preferably performed by heat treatment at 100°C to 500°C, The converted oxygen release rate is 1.0 x 10 19 atoms / cm 3 The film is the same as above. The edge layer 120 also functions as an interlayer insulating film, and is formed by CMP (chemical mechanical polishing) to make the surface flat. Even if flattening is performed using methods such as MIP, good.

[0237] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or other oxide insulating films. , silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. A laminate of the above materials can be used. It is also possible.

[0238] In this embodiment, the oxide semiconductor layer 130 of the transistor is an oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are The details will be mainly explained for the case where the layers are stacked in order.

[0239] Note that in the case where the oxide semiconductor layer 130 is a single layer, Simply use the layer corresponding to 0b.

[0240] In addition, when the oxide semiconductor layer 130 has two layers, the oxide semiconductor layer 13 shown in this embodiment is 0b and a layer corresponding to the oxide semiconductor layer 130c are formed in this order from the insulating layer 120 side. In this structure, the oxide semiconductor layer 130b and the oxide semiconductor layer It can also be replaced with 130c.

[0241] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having a three-layer structure. can be done.

[0242] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide layer 130c has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band). The electron affinity is the energy difference between the vacuum level and the top of the valence band (ionic The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the value of

[0243] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum of the oxide semiconductor layer 13 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be made of a thin oxide semiconductor.

[0244] In such a structure, when an electric field is applied to the conductive layer 170, That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. do.

[0245] The oxide semiconductor layer 130a contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface state may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a can reduce the threshold voltage. As a result, variations in electrical characteristics such as the threshold voltage of the transistors can be reduced. In addition, the reliability of the transistor can be improved.

[0246] The oxide semiconductor layer 130c contains at least one metal element constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0247] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may include, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf is a material having a higher atomic number than the oxide semiconductor layer 130b. Specifically, a material containing the atomic ratio of 1.5 times or more of the atomic ratio can be used. The amount is preferably at least two times, and more preferably at least three times. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from being generated. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0248] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also installed. It is preferred that it includes

[0249] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and Gd. , Tb, Dy, Ho, Er, Tm, Yb, Lu, etc.

[0250] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg Oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0251] In addition, for example, In-Ga-Zn oxide is a material with In, Ga, and Zn as the main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0252] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metal element or elements. Also, In2SnO5(ZnO) n(n>0, and and n is an integer) may be used.

[0253] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are At least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La When the oxide semiconductor layer 1 is an In-M-Zn oxide containing a metal such as Ce or Hf, The oxide semiconductor layer 130a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is I n:M:Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Z If n=x3:y3:z3 [atomic ratio], then y1 / x1 and y3 / x3 are y2 / x2 It is preferable that y1 / x1 and y3 / x3 are 1.0 times greater than y2 / x2. The thickness is set to 5 times or more, preferably 2 times or more, and more preferably 3 times or more. In the conductor layer 130b, when y2 is equal to or larger than x2, the electrical characteristics of the transistor are stabilized. However, if y2 is three times or more larger than x2, the field effect mobility of the transistor Therefore, it is preferable that y2 is less than three times x2.

[0254] When Zn and O are excluded from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0255] The oxide semiconductor layer 130b is a semiconductor layer including the oxide semiconductor layer 130a and the oxide semiconductor layer 130. It is preferable to have a higher indium content than c. In oxide semiconductors, the s orbital of heavy metals is the The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are formed. Because the paths overlap, oxides with more In than M are compared with oxides with the same or less In than M. Therefore, the oxide semiconductor layer 130b has a high indium content. By using an oxide, a transistor with high field effect mobility can be realized.

[0256] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 5 The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 10 nm or more and 150 nm or less. More preferably, the thickness of the oxide semiconductor layer 130c is set to 15 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. It is preferable that the thickness of the oxide semiconductor layer 30a is larger than that of the oxide semiconductor layer 130c.

[0257] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic (i-type) or It is effective to make the oxide semiconductor layer substantially intrinsic. Rear density is 1×10 15 / cm 3 Less than 1 × 10 13 / cm3 Less than And 8 x 10 11 / cm 3 Less than or equal to 1 × 10 8 / cm 3 Less than or equal to 1×10 -9 / cm 3 This is as above.

[0258] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in layer 130c and at each interface.

[0259] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) The silicon concentration estimated by y-Ion Mass Spectrometry (YMS) analysis was 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 Controlled to have an area less than In addition, the hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5×10 1 9 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm3 The following is further Preferably 5 x 10 18 atoms / cm 3 The control is performed so as to have a region where: The nitrogen concentration may vary depending on the depth of the oxide semiconductor layer or the thickness of the oxide semiconductor layer. In a region of the layer, 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Further details are below. Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0260] When silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer may be reduced. In order not to deteriorate the crystallinity of the oxide semiconductor layer, the silicon concentration is set to, for example, 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than, even more preferred Or 1×10 18 atoms / cm 3 The control is performed so that the area is less than Carbon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 have an area less than Control it as follows.

[0261] In addition, a transistor using the purified oxide semiconductor film as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several y It is possible to reduce the distortion to a level of A / μm to several zA / μm.

[0262] In addition, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not contact the gate insulating film like a gate insulating film is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carriers are scattered at the interface. This leads to a decrease in the field effect mobility of the transistor. It is preferable to separate the region of the conductor layer that becomes the channel from the gate insulating film.

[0263] Therefore, the oxide semiconductor layer 130 is divided into an oxide semiconductor layer 130a and an oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel is formed in the oxide semiconductor layer 130b. Thus, a transistor having high field effect mobility and stable electrical characteristics can be formed. It is possible to form a

[0264] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers having different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0265] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) The layers are fabricated so that a well structure (U Shape Well) is formed. There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. If impurities are mixed between the stacked oxide semiconductor layers, When the interface is in a non-uniform state, the continuity of the energy band is lost, and carriers are trapped or recombined at the interface. It will disappear when combined.

[0266] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxide with an atomic ratio of 9:6 can be used. The compound semiconductor layer 130b has a composition of In:Ga:Zn=1:1:1, 2:1:3, 5:5:6, or Alternatively, an In-Ga-Zn oxide having an atomic ratio of 3:1:2 or the like can be used. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The atomic ratios of c each include a variation of ±20% of the above atomic ratios as an error. nothing.

[0267] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and The oxide semiconductor layer 130 is formed in the oxide semiconductor layer 130b. Because the energy changes continuously, it can also be called a U-shaped well. A channel formed in this manner can also be called a buried channel.

[0268] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a method of forming a silicon oxide film or the like. In the vicinity of the interface with the insulating layer, trap levels due to impurities or defects may be formed. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c makes it possible to form the oxide semiconductor layer 13 This makes it possible to keep 0b away from the trap level.

[0269] However, the energy minimum of the conduction band of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the conduction band minimum of the oxide semiconductor layer 130b and the energy of the oxide semiconductor layer 130c is small, Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap levels, negative charges are generated at the interface of the insulating layer, causing the transistor to turn off. The threshold voltage of the transistor is shifted in the positive direction.

[0270] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, the transistor It is possible to give stable electrical properties to the crystals. In addition, the crystals oriented along the c-axis are resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0271] A conductive layer 140 acts as a source electrode layer and a conductive layer 141 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Representative examples include Ti, which is particularly susceptible to bonding with oxygen, and the fact that the subsequent process temperature can be relatively high. For these reasons, it is more preferable to use W, which has a high melting point. In addition, Cu and Cu-M, which have low resistance, are also preferable. A laminate of an alloy such as n and the above material may be used. In the transistors 106, 111, and 112, for example, the conductive layer 14 The conductive layers 142 and 152 are laminated films of Ti and Al. etc. can be used.

[0272] The above material has a property of extracting oxygen from the oxide semiconductor layer. In some regions of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies combine with the small amount of hydrogen contained in the layer, turning the region into an n-type region. Therefore, the n-type region is used as the source or drain of a transistor. It can be used.

[0273] The insulating layer 160 acting as a gate insulating film may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing at least one of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. It may contain r and the like as impurities.

[0274] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is, for example, , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0275] Hafnium oxide and aluminum oxide are comparatively more effective than silicon oxide and silicon oxynitride. The dielectric constant is high. Therefore, the film thickness can be made larger than that of silicon oxide, and the tunnel current In other words, a transistor with a small off-state current can be used. Furthermore, hafnium oxide having a crystalline structure can be easily obtained by the method described above. It has a higher dielectric constant than hafnium oxide, which is used for transistors with low off-state current. To make the material a dissipative material, it is preferable to use hafnium oxide having a crystalline structure. Examples of the structure include monoclinic and cubic. However, one embodiment of the present invention is Not limited to these.

[0276] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface state may function as a trap center. When silicon is placed close to the channel region of a transistor, the interface states cause the transistor to Therefore, in order to reduce the influence of the interface state, The channel region of the transistor is isolated from the hafnium oxide by placing another film between the transistor and the hafnium oxide. It is preferable to separate the insulating layer from the insulating layer. This film has a buffer function. The film may be a film included in the oxide semiconductor film 160. Examples of films with a buffer function include silicon oxide, silicon oxynitride, and oxide semiconductors. The film having the buffer function may be, for example, a film having a channel region. Use a semiconductor or insulator with a larger energy gap than the semiconductor. The film having the function includes, for example, a semiconductor having a smaller electron affinity than the semiconductor that is to be the channel region. Alternatively, the film having a buffer function may be, for example, a film having a channel region and In this case, a semiconductor or insulator having a larger ionization energy than the semiconductor is used.

[0277] On the other hand, the interface states (trap By trapping charge in the charge center, it may be possible to control the threshold voltage of a transistor. In order to make the charge exist stably, for example, the channel region and hafnium oxide A semiconductor or insulator with a larger energy gap than hafnium oxide is placed between the hafnium and the Alternatively, a semiconductor or insulator with a smaller electron affinity than hafnium oxide may be used. Alternatively, the film with a buffer function may be made of ionized ions rather than hafnium oxide. A semiconductor or insulator with high energy can be placed in the By using this, the charges trapped in the interface state are less likely to be released, and the This allows the charge to be held.

[0278] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges in the interface states in the layer 160, the gate voltage from the oxide semiconductor layer 130 must be The electrons can be moved toward the polar layer (conductive layer 170). temperature (for example, 125°C to 450°C, typically 150°C to 300°C) The potential of the gate electrode layer (conductive layer 170) is set higher than the potential of the source electrode and drain electrode. It is sufficient to maintain the temperature at this temperature for at least one second, typically at least one minute.

[0279] In this way, a transistor in which a desired amount of electrons are trapped in the interface state of the insulating layer 160, etc., The threshold voltage is shifted to the positive side. By adjusting the application time, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. If the charges can be trapped, the charges can be trapped not in the insulating layer 160 but in the A laminated film having a similar structure may be used for other insulating layers.

[0280] In addition, in the insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130, nitrogen The semiconductor device may have a region having a low density of oxide-induced states. As the oxide insulating layer, a silicon oxynitride film or a nitrogen oxide film having a low nitrogen oxide emission amount is used. An aluminum oxynitride film or the like that releases less substances can be used.

[0281] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, was analyzed by thermal desorption spectrometry (TDS). (Thermal Desorption Spectroscopy) This is a membrane that releases more ammonia than elemental oxide, and is typically The amount is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is ammonia. The amount of release is determined when the surface temperature of the film is 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower. This is the amount released by the heat treatment below.

[0282] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0283] The conductive layer 170 acting as a gate electrode layer may be, for example, Al, Ti, Cr, Co, or Ni. Conductive films of Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W In addition, alloys of the above materials and conductive nitrides of the above materials may be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are Typically, the material may be a laminate of tungsten or tungsten and titanium nitride. For example, a laminate of tungsten and tantalum nitride can be used. Alternatively, alloys such as Cu-Mn or laminations of the above materials with Cu or alloys such as Cu-Mn may be used. In this embodiment, tantalum nitride is used for the conductive layer 171 and tungsten is used for the conductive layer 172. This is used to form the conductive layer 170 .

[0284] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor In transistor 106, transistor 109, transistor 110, and transistor 112, By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer is made n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0285] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In the transistors 107, 108, and 111, the insulating layer 175 is formed of an oxide layer. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Aluminum oxide has a high barrier effect of preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. Prevents oxygen from being mixed into the oxide semiconductor layer 130, prevents oxygen from being released from the oxide semiconductor layer, and prevents the insulating layer 1 It is suitable for use as a protective film having the effect of preventing unnecessary release of oxygen from 20. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0286] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0287] Here, the insulating layer 180, like the insulating layer 120, has more oxygen than the stoichiometric composition. It is preferable that oxygen released from the insulating layer 180 is transported through the insulating layer 160 to the oxide semiconductor Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, resulting in a stable transistor. The electrical properties can be obtained.

[0288] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the ON current is reduced, the ON current decreases.

[0289] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and the on-state voltage of the transistor is The flow can be increased.

[0290] In the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from the perpendicular direction. That is, the electric field is applied to the channel forming layer. The gate electric field is applied, expanding the effective channel width, which further increases the on-current. It can be seen.

[0291] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. First, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. In addition, the oxidation of the oxide film according to one embodiment of the present invention has an effect of making it difficult for an interface state to be formed. In a transistor having a three-layer structure of the oxide semiconductor layer 130, the oxide semiconductor layer 130b is disposed in the middle of the three-layer structure. By placing the layer in the position above the object, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor, the threshold voltage is stabilized. It is possible to reduce the S value (subthreshold value). t (current when the gate voltage VG is 0V) can be lowered, which reduces power consumption. In addition, the threshold voltage of the transistor is stabilized, which improves the long-term reliability of the semiconductor device. In addition, the transistor of one embodiment of the present invention can be miniaturized. Since the deterioration of electrical characteristics is suppressed, it is suitable for forming highly integrated semiconductor devices. It can be said that.

[0292] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0293] (Embodiment 7) In this embodiment, the transistor 101 and the transistor 102 described in the fifth embodiment are This explains how to make 07.

[0294] First, an example of a method for manufacturing a silicon transistor included in the substrate 115 will be described. As for the n substrate, - A single crystal silicon substrate is used, and an insulating layer (field oxide film) is applied to the surface. The element isolation region is formed by the LOCOS method ( Local Oxidation of Silicon (STI) and Shallow Trench Isolation, etc. can be used.

[0295] Here, the substrate is not limited to a single crystal silicon substrate, but may be SOI (Silicon on Insul A substrate such as a photodiode may also be used.

[0296] Next, a gate insulating film is formed so as to cover the element formation region. The surface of the deposition region is oxidized to form a silicon oxide film. After the formation of the silicon oxide film, a nitriding treatment may be performed to nitride the surface of the silicon oxide film.

[0297] Next, a conductive film is formed to cover the gate insulating film. The conductive film may be made of Ta, W, Ti, Elements selected from Mo, Al, Cu, Cr, Nb, etc. or containing these elements as the main components The material can be an alloy or a compound material. It can also be made of a metal nitride film. In addition, it can be made of a polycrystalline film doped with impurity elements such as phosphorus. It can also be formed from a semiconductor material such as silicon.

[0298] Next, the conductive film is selectively etched to form a gate electrode layer on the gate insulating film. Form.

[0299] Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed so as to cover the gate electrode layer. Then, etch-back is performed to form sidewalls on the side surfaces of the gate electrode layer.

[0300] Next, a resist mask is selectively formed so as to cover areas other than the element formation area. By introducing impurity elements using the mask and gate electrode layer, p + Type Impurity In this case, to form a p-channel transistor, the impurity element and As the dopant, B, Ga, or the like, which is an impurity element that imparts p-type conductivity, can be used.

[0301] Next, a resist mask is selectively formed to fabricate a photodiode. A photodiode is formed on the same surface of the single crystal silicon substrate as the transistor. To form the cathode of the anode, impurity elements such as phosphorus (P) and arsenic ( By introducing As), + A shallow impurity region is formed. A p-type anode for electrical connection to the wiring + Forming deep impurity regions In addition, the anode of the photodiode (p + The shallow impurity region will be formed in a later process. A single crystal silicon substrate is formed on the opposite side to the side on which the photodiode cathode is formed. Complete.

[0302] As shown in FIG. 1(A), the area in contact with the side of the photodiode is etched. An opening is formed, and an insulating layer is provided in the opening. The insulating layer may be a silicon oxide layer, a silicon nitride layer, or the like. A layer of cellulose can be used, and CVD (Chemical Vapor Deposition) The thin film can be formed by a film formation method such as a precipitation method or a thermal oxidation method.

[0303] The above results show that a p-ch type transistor and a photodiode with an active region on a silicon substrate can be fabricated. The transistor is then covered with a passivation film such as silicon nitride. It is preferred to form a film.

[0304] Next, an interlayer insulating film such as a silicon oxide film is formed on the silicon substrate on which the transistors are formed. As described in the first embodiment, the hydrogen An insulating layer such as aluminum oxide is formed to prevent diffusion. A silicon substrate on which a transistor and a photodiode are formed, The insulating layer, the wiring layer, the conductor, and the like are formed on the insulating layer.

[0305] Next, a manufacturing method of the transistor 102 will be described with reference to FIGS. The left side of the drawing shows a cross section of the transistor in the channel length direction, and the right side shows a cross section in the channel width direction. The cross section is shown. The drawing in the channel width direction is an enlarged view, so the apparent film thickness of each element is shown on the left. It is different in the drawing on the right.

[0306] The oxide semiconductor layer 130 includes an oxide semiconductor layer 130a, an oxide semiconductor layer 130b, and an oxide semiconductor layer 130c. The oxide semiconductor layer 130 has a three-layer structure. In this case, a two-layer structure including the oxide semiconductor layer 130a and the oxide semiconductor layer 130b may be used. In addition, when the oxide semiconductor layer 130 has a single-layer structure, the oxide semiconductor layer 130b is formed as a single layer. Good.

[0307] First, an insulating layer 120 is formed on a substrate 115. The type of substrate 115 and the insulating layer 120 For the material, the description of the sixth embodiment can be referred to. The insulating layer 120 is formed by sputtering. , CVD method, MBE (Molecular Beam Epitaxy) method, etc. It can be formed.

[0308] In addition, the insulating layer 120 is subjected to ion implantation, ion doping, plasma immersion ion implantation, etc. Oxygen may be added by implantation, plasma treatment, or the like. By adding the oxygen, the supply of oxygen from the insulating layer 120 to the oxide semiconductor layer 130 is further facilitated. It can be made easier.

[0309] Note that the surface of the substrate 115 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no effect of scattering, the insulating layer 120 may be omitted.

[0310] Next, an oxide semiconductor film 130A that will become the oxide semiconductor layer 130a is formed on the insulating layer 120. The oxide semiconductor film 130B which becomes the semiconductor layer 130b and the oxide semiconductor film 130c which becomes the oxide semiconductor layer 130c are The oxide semiconductor film 130C is formed by sputtering, CVD, MBE, or the like (FIG. 4 0(A)).

[0311] When the oxide semiconductor layer 130 has a stacked structure, the oxide semiconductor film is Using a multi-chamber deposition device (e.g., a sputtering device), each layer is exposed to the atmosphere. It is preferable to laminate the layers continuously without causing any damage to the sputtering device. In order to remove as much water and other impurities as possible from semiconductors, a cryopump is used. High vacuum evacuation (5×10) using a suction type vacuum pump -7 Pa~1×10 -4 Pa level and capable of heating the substrate to 100°C or higher, preferably 500°C or higher. It is preferable to use a turbo molecular pump and a cold trap to separate the gas from the exhaust system. It is preferable to prevent gas containing carbon components, moisture, etc. from flowing back into the bar. An exhaust system combining a polymer pump and a cryopump may be used.

[0312] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is preferable to use highly purified sputtering gas. The dew point of the gas is -40°C or less, preferably -80°C or less, more preferably -100°C or less. By purifying the oxide semiconductor film to the bottom, it is possible to prevent moisture and other substances from being absorbed into the oxide semiconductor film as much as possible. It is possible to do so.

[0313] The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C are The material described in the sixth embodiment can be used. The film can be formed by using the material described in the sixth embodiment as a target.

[0314] However, as described in detail in the sixth embodiment, the oxide semiconductor film 130B contains an oxide semiconductor A material having a larger electron affinity than the oxide semiconductor film 130A and the oxide semiconductor film 130C is used.

[0315] Note that the oxide semiconductor film is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0316] After the oxide semiconductor film 130C is formed, a first heat treatment may be performed. , at a temperature of 250°C or more and 650°C or less, preferably 300°C or more and 500°C or less, The reaction may be carried out in a nitrogen atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The atmosphere for the heat treatment in 1 was an inert gas atmosphere, and then the oxygen removed was replaced with In order to prevent this, the first heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more. The oxide semiconductor film 130A, the oxide semiconductor film 130B, and the oxide semiconductor film 130C The crystallinity is improved, and the insulating layer 120, the oxide semiconductor film 130A, the oxide semiconductor film 130B, Furthermore, impurities such as hydrogen and water can be removed from the oxide semiconductor film 130C. In the first heat treatment, the oxide semiconductor layers 130a, 130b, and This may be performed after the etching for forming the oxide semiconductor layer 130c.

[0317] Next, a first conductive layer is formed on the oxide semiconductor film 130A. The first conductive layer may be, for example, It can be formed using the following method.

[0318] First, a first conductive film is formed on the oxide semiconductor film 130A. l, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc, and related metallic materials A single layer or a laminate of materials selected from the alloys above may be used.

[0319] Next, a resist film is formed on the first conductive film, and the resist film is exposed to an electron beam. The first resist is exposed using a method such as immersion exposure or EUV exposure, and then developed. A mask is formed. An organic coating film is placed between the first conductive film and the resist film as an adhesive. It is preferable to form the first resist by using a nanoimprint lithography method. A mask may be formed.

[0320] Next, the first conductive film is selectively etched using the first resist mask to form a first resist. The resist mask is then ashed to form a conductive layer.

[0321] Next, the conductive layer is used as a hard mask to form an oxide semiconductor film 130A. 130B and the oxide semiconductor film 130C are selectively etched to remove the conductive layer. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c The oxide semiconductor layer 130 is formed by stacking the above-mentioned conductive layers (see FIG. 40B). The oxide semiconductor layer 130 may be formed using the first resist mask without forming a layer. Here, oxygen ions may be implanted into the oxide semiconductor layer 130.

[0322] Next, a second conductive film is formed so as to cover the oxide semiconductor layer 130. The material that can be used for the conductive layer 140 and the conductive layer 150 described in the sixth embodiment The second conductive film can be formed by a method such as sputtering, CVD, or MBE. There can be.

[0323] Next, a second resist mask is formed on the portions that will become the source and drain regions. Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150. (See Figure 40(C)).

[0324] Next, a layer to become a gate insulating film is formed on the oxide semiconductor layer 130, the conductive layer 140, and the conductive layer 150. An insulating film 160A is formed. The insulating film 160A is formed by forming the insulating layer 160 described in the sixth embodiment. The insulating film 160A may be formed of a material that can be used for the insulating film 160A. The VD method, MBE method, etc. can be used.

[0325] Next, a second heat treatment may be performed under the same conditions as the first heat treatment. By the second heat treatment, the oxygen injected into the oxide semiconductor layer 130 is converted into oxygen. The second heat treatment can be omitted. The above effect may be obtained by a third heat treatment.

[0326] Next, a third conductive film 171A and a fourth conductive film 172A, which will become the conductive layer 170, are formed on the insulating film 160A. The third conductive film 171A and the fourth conductive film 172A are formed as in the embodiment. The conductive layer 171 and the conductive layer 172 may be formed of a material that can be used for the conductive layer 171 and the conductive layer 172 described in 6. The third conductive film 171A and the fourth conductive film 172A may be formed by a sputtering method, a CVD method, or the like. The deposition method, MBE method, etc. can be used.

[0327] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 41(A) Then, the third conductive film 171A and the fourth conductive film 171B are formed using the third resist mask 156. The conductive film 172A and the insulating film 160A are selectively etched to form the conductive layer 171 and the conductive A conductive layer 170 made of a layer 172 and an insulating layer 160 are formed (see FIG. 41(B)).

[0328] Next, the oxide semiconductor layer 130, the conductive layer 140, the conductive layer 150, the insulating layer 160 and the conductive layer An insulating layer 175 is formed on the insulating layer 170. For the material of the insulating layer 175, see the description of the sixth embodiment. In the case of the transistor 101, an aluminum oxide film is preferably used. The insulating layer 175 can be formed by a sputtering method, a CVD method, an MBE method, or the like. .

[0329] Next, the insulating layer 180 is formed on the insulating layer 175 (see FIG. 41(C)). For the material, the explanation of the sixth embodiment can be referred to. In addition, the insulating layer 180 is formed by sputtering. The method may be the CVD method, MBE method, or the like.

[0330] In addition, the insulating layer 175 and / or the insulating layer 180 may be subjected to ion implantation, ion doping, Using plasma immersion ion implantation and plasma treatment methods, etc. By adding oxygen, the insulating layer 175 and / or the insulating layer 1 This makes it easier to supply oxygen from the electrode 80 to the oxide semiconductor layer 130 .

[0331] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed by removing the insulating layer 120, the insulating layer 175, and the insulating layer 18. 0, excess oxygen is easily released, and oxygen vacancies in the oxide semiconductor layer 130 are reduced. can be done.

[0332] Next, a method for manufacturing the transistor 107 will be described. Detailed explanation of the steps overlapping with the manufacturing method of 01 will be omitted.

[0333] An insulating layer 120 is formed on a substrate 115, and an oxide semiconductor layer 130a is formed on the insulating layer. The oxide semiconductor film 130A which will become the oxide semiconductor layer 130b is The film is formed by using a method such as sputtering, CVD, or MBE (see FIG. 42(A)).

[0334] Next, a first conductive film is formed on the oxide semiconductor film 130B, and the first A conductive layer is formed using a resist mask. Then, the conductive layer is subjected to an acid treatment using the resist mask as a hard mask. The conductive semiconductor film 130A and the oxide semiconductor film 130B are selectively etched to form the conductive layer 130A. The layers are removed to form a stack of oxide semiconductor layers 130a and 130b. (See FIG. 42(B)). Note that a hard mask is not formed, and the first resist mask is used. Here, oxygen ions may be added to the oxide semiconductor layer 130 to form the stack. may be injected.

[0335] Next, a second conductive film is formed so as to cover the stacked layer. A second resist mask is formed on the portion to be the gate region, and the second resist mask is used to Then, a part of the second conductive film is etched to form the conductive layer 140 and the conductive layer 150 ( See Figure 42(C).

[0336] Next, a conductive layer is formed on the stack of the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. 140 and the conductive layer 150, an oxide semiconductor film 130C which becomes an oxide semiconductor layer 130c is formed. Further, an insulating film 160A which becomes a gate insulating film is formed on the oxide semiconductor film 130C. Then, a third conductive film 171A and a fourth conductive film 172A which will become the conductive layer 170 are formed.

[0337] Next, a third resist mask 156 is formed on the fourth conductive film 172A (FIG. 43(A) Then, the third conductive film 171A and the fourth conductive film 171B are formed by using the resist mask. 72A, the insulating film 160A, and the oxide semiconductor film 130C are selectively etched to form a conductive A conductive layer 170 consisting of a layer 171 and a conductive layer 172, an insulating layer 160, and an oxide semiconductor The insulating film 160A and the oxide semiconductor layer 130c are formed (see FIG. 43B). The film 130C is etched using a fourth resist mask to form the transistor 108. can be produced.

[0338] Next, the insulating layer 120, the oxide semiconductor layer 130 (the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, oxide semiconductor layer 130c), conductive layer 140, conductive layer 150, insulating layer 160, and An insulating layer 175 and an insulating layer 180 are formed over the conductive layer 170 (see FIG. 43(C)).

[0339] Through the above steps, the transistor 107 can be manufactured.

[0340] The various films described in this embodiment, such as a metal film, a semiconductor film, and an inorganic insulating film, are typically The can be formed by sputtering or plasma CVD, but other methods, such as thermal The insulating layer may be formed by a CVD method. An example of a thermal CVD method is MOCVD (Metal O Organic Chemical Vapor Deposition (ALD) method These include the Atomic Layer Deposition (ALD) method.

[0341] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that the

[0342] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the inside of the chamber is By reacting near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0343] In the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is introduced into the chamber. The film is formed by repeatedly introducing and reacting the raw material gas into the inert gas ( For example, two or more kinds of gases (argon, nitrogen, etc.) may be introduced as a carrier gas. The source gases may be supplied to the chamber in sequence. In this case, multiple source gases are not mixed. In this manner, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is exhausted by evacuation, and then the second source gas is introduced. The first source gas may be adsorbed and reacted with the surface of the substrate to form a first layer. The second source gas is introduced later and adsorbed and reacted with the second layer, which is then formed on the first layer. The gas introduction sequence is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is injected. This is suitable for fabricating miniaturized FETs.

[0344] The thermal CVD method such as the MOCVD method or the ALD method may be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a -Zn-O film, trimethylindium (In(CH3)3), trime Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and triethyl gallium may be used instead of trimethyl gallium. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0345] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursors (hafnium alkoxides and tetrakisdimethylamide hafnium Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide The raw material gas is made by vaporizing hafnium (such as hafnium amide) and ozone ( Two types of gases are used:

[0346] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas made by vaporizing ethanol, etc., and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, and aluminium. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0347] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0348] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The tungsten film is formed by sequentially introducing the two gases. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0349] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced in sequence to form a GaO layer, and Then, Zn(CH3)2 and O3 gases are introduced in sequence to form a ZnO layer. The order of layers is not limited to this example. Using these gases, In-Ga-O layers and In-Zn-O layers can be formed. A layer of a mixed compound such as a Ga-Zn-O layer may be formed. H2O gas obtained by bubbling with an inert gas such as HO may be used, but it should not contain H. It is preferable to use O3 gas.

[0350] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0351] (Embodiment 8) A structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described below. .

[0352] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0353] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0354] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0355] First, we will explain the CAAC-OS film.

[0356] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0357] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0358] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0359] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0360] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0361] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0362] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities in the oxide semiconductor film may cause the atomic arrangement to be disturbed, which may result in a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0363] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0364] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0365] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0366] Next, a microcrystalline oxide semiconductor film will be described.

[0367] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0368] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. In some cases, spots distributed in a circular pattern may be observed. When performing nanobeam electron diffraction, multiple spots may be observed within a ring-shaped region. do.

[0369] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0370] Next, the amorphous oxide semiconductor film will be described.

[0371] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0372] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0373] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0374] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Ox The resulting film is called an ide semiconductor membrane.

[0375] The amorphous-like OS membrane appears as voids in high-resolution TEM images. In addition, crystals may be clearly observed in high-resolution TEM images. There are areas where crystals can be seen and areas where crystals cannot be seen. The phos-like OS film is formed by irradiating a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, if the nc-OS film is of good quality, However, crystallization due to minute amounts of electron irradiation, such as that observed by TEM, is hardly observed.

[0376] The size of the crystals in the amorphous-like OS film and the nc-OS film was calculated. Measurements can be performed using high-resolution TEM images. For example, the crystals of InGaZnO4 It has a layered structure, with two Ga-Zn-O layers between In-O layers. InGaZnO4 The unit cell of this crystal has three In-O layers and six Ga-Zn-O layers, for a total of nine layers. The layers are stacked in the c-axis direction. Therefore, the spacing between adjacent layers is is approximately the same as the lattice spacing (also called the d value) of the (009) plane, and crystal structure analysis has revealed that The value is expected to be 0.29 nm. Therefore, we focus on the lattice fringes in the high-resolution TEM image. In the area where the lattice spacing is 0.28 nm or more and 0.30 nm or less, The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0377] The oxide semiconductor film is, for example, an amorphous oxide semiconductor film. e. A stacked film including two or more of an OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. may be also possible.

[0378] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0379] (Embodiment 9) The band structure of a transistor of one embodiment of the present invention will be described below.

[0380] FIG. 44A is a cross-sectional view of a transistor including an oxide semiconductor layer according to one embodiment of the present invention. be.

[0381] The transistor shown in FIG. 44A includes an insulating layer 401 on a substrate 400 and a A conductive layer 404a, a conductive layer 404b on the conductive layer 404a, and a conductive layer 404b on the insulating layer 401. 4a and the insulating layer 402a on the conductive layer 404b, and the insulating layer 402b on the insulating layer 402a. A semiconductor layer 406a on the insulating layer 402b, and a semiconductor layer 406b on the semiconductor layer 406a. , an insulating layer 412 on the semiconductor layer 406b, a conductive layer 414a on the insulating layer 412, and a conductive layer 4 14a, the conductive layer 414b on the insulating layer 402b, the semiconductor layer 406a, and the semiconductor layer 406 b, insulating layer 412, conductive layer 414a, and conductive layer 414b; An insulating layer 418 on the edge layer 408, and a conductive layer 416a1 and a conductive layer 416 on the insulating layer 418. b1, and conductive layers 416a2 and 416b1 on the conductive layers 416a1 and 416b1, respectively. and the conductive layer 416b2, on the insulating layer 418, on the conductive layer 416a2, and on the conductive layer 416b2. and an insulating layer 428.

[0382] The insulating layer 401 prevents impurities such as copper from entering the channel formation region of the transistor. The device may have a function to control the amount of the noise generated.

[0383] The stack of the conductive layer 404a and the conductive layer 404b is collectively referred to as the conductive layer 404. The conductive layer 404 functions as a gate electrode of the transistor. The light shading function may be provided for the channel forming region of the photoresist.

[0384] The insulating layer 402a and the insulating layer 402b are collectively referred to as the insulating layer 402. The insulating layer 402a functions as a gate insulating layer of the transistor. The insulating layer 12 may have a function of suppressing the intrusion of impurities such as copper into the channel formation region of the transistor.

[0385] The semiconductor layer 406a and the semiconductor layer 406b are collectively referred to as the semiconductor layer 406. The semiconductor layer 406 functions as a channel formation region of a transistor. a is the oxide semiconductor layer 130b shown in the above embodiment, and the semiconductor layer 406b is the oxide semiconductor layer 130b shown in the above embodiment. This corresponds to the oxide semiconductor layer 130c shown in the embodiment.

[0386] Note that the semiconductor layer 406a does not overlap with the insulating layer 412, the conductive layer 414a, and the conductive layer 414b. The semiconductor layer 406b has a region 407a1 and a region 407b1. 12, the conductive layer 414a, the region 407a2 not overlapping the conductive layer 414b, and the region 407b The region 407a1 and the region 407b1 are formed by insulating layer 412 of the semiconductor layer 406a. 4, which is a region having a lower resistance than the region overlapping with the conductive layer 414a and the conductive layer 414b. The region 407a2 and the region 407b2 are formed by the insulating layer 412 and the conductive layer 414 of the semiconductor layer 406b. a is a region having a lower resistance than the region overlapping with the conductive layer 414b. , they can also be called regions of high carrier density.

[0387] The area 407a1 and the area 407a2 are collectively referred to as the area 407a. Area 407b1 and area 407b2 are collectively referred to as area 407b. 07b functions as the source and drain regions of a transistor.

[0388] The conductive layer 414a and the conductive layer 414b are collectively referred to as a conductive layer 414. The conductive layer 414 functions as a gate electrode of a transistor. The insulating film may have a function of blocking light from a channel forming region, etc.

[0389] The insulating layer 412 functions as a gate insulating layer of the transistor.

[0390] The insulating layer 408 is formed by removing impurities such as copper contained in the conductive layers 416a2 and 416b2. The insulating film may have a function of preventing substances from entering a channel formation region of a transistor.

[0391] The insulating layer 418 may function as an interlayer insulating layer of the transistor. The parasitic capacitance between the wirings of the transistors can be reduced.

[0392] The conductive layer 416a1 and the conductive layer 416a2 are collectively referred to as the conductive layer 416a. The conductive layer 416b1 and the conductive layer 416b2 are collectively referred to as the conductive layer 416b. The conductive layer 416b functions as a source electrode and a drain electrode of a transistor. do.

[0393] The insulating layer 428 has a function of preventing impurities from entering a channel formation region of the transistor. It may also have the ability.

[0394] FIG. 44B shows a cross section taken along the line P1-P2 including the channel formation region of the transistor. The semiconductor layer 406a has a larger energy gap than the semiconductor layer 406b. In addition, the insulating layer 402a, the insulating layer 402b, and the insulating layer 412 are The energy gap of the semiconductor layer 406 is sufficiently larger than that of the semiconductor layer 406a and the semiconductor layer 406b. In addition, the semiconductor layer 406a, the semiconductor layer 406b, the insulating layer 402a, the insulating layer 402b, and The Fermi level (Ef) of the insulating layer 412 is the intrinsic Fermi level (denoted as Ei). The work functions of the conductive layers 404 and 414 are is set to the same position as the Fermi level.

[0395] When the gate voltage is set to be equal to or higher than the threshold voltage of the transistor, the semiconductor layer 406a and the semiconductor layer Due to the difference in energy between the conduction band minimum and the semiconductor layer 406b, electrons preferentially pass through the semiconductor layer 406a. In other words, it can be assumed that electrons are embedded in the semiconductor layer 406a. The energy at the bottom of the conduction band is denoted as Ec, and the energy at the top of the valence band is denoted as Ev. .

[0396] Therefore, the transistor according to one embodiment of the present invention can suppress the interface scattering by embedding electrons. Therefore, the transistor according to one embodiment of the present invention has a low channel resistance. is small.

[0397] Next, in FIG. 44(C), a transistor Q1-Q2 including a source region or a drain region is shown. The band structure in the cross section is shown in FIG. 2 and the region 407b2 are in a degenerated state. The Fermi level of 406a is approximately equal to the energy of the bottom of the conduction band. In 2, the Fermi level of the semiconductor layer 406b is set to be approximately equal to the energy of the bottom of the conduction band. The same is true for area 407a1 and area 407a2.

[0398] At this time, the conductive layer 416b having a function as a source electrode or a drain electrode and the region The energy barrier between 407b2 and 407b2 is small enough that they form an ohmic contact. The region 407b2 and the region 407b1 are in ohmic contact. The conductive layer 416a having a function as a drain electrode and the region 407a2 are connected to each other through an energy The barrier is small enough to provide an ohmic contact. Therefore, the conductive layer 416a and the conductive layer 416b are in ohmic contact with each other. Electrons are smoothly exchanged between the semiconductor layer 406a and the semiconductor layer 406b. It can be seen that.

[0399] As described above, the transistor according to one embodiment of the present invention has a source electrode and a drain electrode. Electrons are exchanged smoothly between the electrode and the channel formation region, resulting in low channel resistance. In other words, it has excellent switching characteristics. It can be seen that this is a transistor.

[0400] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0401] (Embodiment 10) In this embodiment, the effect of oxygen vacancies in an oxide semiconductor layer and hydrogen bound to the oxygen vacancies is described. The results will be explained.

[0402] <(1). V o Formation and stability of H> When the oxide semiconductor film (hereinafter referred to as IGZO) is a perfect crystal, H is preferentially During heat treatment at 450°C, H diffuses along the ab plane and In this study, oxygen vacancies in IGZO are o If there is In this case, H is oxygen deficiency V o Here, we will explain whether it is easy to enter the oxygen vacancy V o Medium The state where there is H in V o It is written as H.

[0403] For the calculation, the InGaZnO4 crystal model shown in Figure 45 was used. Here, V o H in H V o The activation barrier (E a ) to NEB (Nudg The calculation conditions are shown in Table 1.

[0404] [Table 1]

[0405] In addition, in the InGaZnO4 crystal model, the metal elements to which oxygen atoms are bonded and their number Due to the difference in the oxygen atoms, there are four types of oxygen atoms, 1 to 4, as shown in FIG. Oxygen deficiency V o The calculations were performed for oxygen atoms 1 and 2, which are likely to form

[0406] First, calculations were performed for oxygen atom 1 bonded to three In atoms and one Zn atom.

[0407] The model of the initial state is shown in FIG. 46(A), and the model of the final state is shown in FIG. 46(B). , the calculated activation barrier (E a ) is shown in Figure 47. The initial state here is the oxygen vacancy V that occurs when oxygen atom 1 is removed. o There are hydrogen atoms in State (V o H), and the final state is oxygen deficiency V o A hydrogen atom is transferred from It is in a bonded state (HO) with an oxygen atom bonded to Ga and two Zn.

[0408] As a result of the calculation, oxygen deficiency V o It takes about 1.5 for a hydrogen atom in the molecule to move and bond with another oxygen atom. 2 eV of energy is required, whereas a hydrogen atom bonded to an oxygen atom creates an oxygen vacancy V o An energy of about 0.46 eV was required for the transfer into

[0409] Here, the calculated activation barrier (E a ) and Equation 1 to calculate the reaction frequency (Γ) In addition, in the formula 1, k B is the Boltzmann constant and T is the absolute temperature.

[0410]

number

[0411] Frequency factor ν=10 13 The reaction frequency at 350°C was calculated assuming a reaction rate of 1 / sec. The frequency of hydrogen atom transfer from the model shown in Figure 46(A) to the model shown in Figure 46(B) is 5 .52×10 0 [1 / sec]. Also, from the model shown in Figure 46(B), The frequency of hydrogen atom transfer to the model shown in A is 1.82 × 10 9 [1 / sec] From this, it can be seen that hydrogen atoms diffusing in IGZO are V o It is easy to form H, and once V o H When oxygen vacancies are formed, V o It can be said that it is difficult to separate from the

[0412] Next, calculations were performed for oxygen atom 2 bonded to one Ga and two Zn.

[0413] The model of the initial state is shown in FIG. 48(A), and the model of the final state is shown in FIG. 48(B). , the calculated activation barrier (E a ) is shown in Figure 49. The initial state here is the oxygen vacancy V that occurs when oxygen atom 2 is removed. o There is a hydrogen atom in Status(V o H), and the final state is oxygen deficiency V o A hydrogen atom is transferred from and bound to an oxygen atom (HO) which is bound to two Zn atoms.

[0414] As a result of the calculation, oxygen deficiency V o It takes about 1.7 for a hydrogen atom in the molecule to move and bond with another oxygen atom. 5 eV of energy is required, whereas a hydrogen atom bonded to an oxygen atom creates an oxygen vacancy V o An energy of about 0.35 eV was required for the transfer into

[0415] In addition, the calculated activation barrier (E a ) and the above formula 1 to calculate the reaction frequency (Γ) I put it out.

[0416] Frequency factor ν=10 13 The reaction frequency at 350°C was calculated assuming a reaction rate of 1 / sec. The frequency of hydrogen atom transfer from the model shown in Figure 48(A) to the model shown in Figure 48(B) is 7 .53×10 -2 [1 / sec]. Also, from the model shown in FIG. 48(B), The frequency of hydrogen atom transfer to the model shown in (A) is 1.44 × 10 10 [1 / sec] For this reason, V o H forms oxygen vacancy V o Hydrogen atoms are difficult to remove from It can be said that.

[0417] From the above, hydrogen atoms in IGZO are easily diffused during annealing, and oxygen vacancies V o There is In the case of oxygen deficiency V o Captured in the V o It was found that it is likely to become H.

[0418] <(2). V o H transition level > Oxygen vacancy in IGZO V o When hydrogen is present, the above calculation using the NEB method shows that hydrogen The atom is stable V o Therefore, V o H is involved in career trap To find out whether V o The transition levels of H were calculated.

[0419] The calculation used an InGaZnO4 crystal model (112 atoms). The oxygen site shown in Figure 45 1 and V for oxygen site 2 o The H model was created and the transition level was calculated. The conditions are shown in Table 2.

[0420] [Table 2]

[0421] By adjusting the mixing ratio of the exchange terms to obtain a band gap close to the experimental value, The band gap of the InGaZnO4 crystal model is 3.08 eV, which is lower than the experimental value of 3.15. The result was close to eV.

[0422] The transition level (ε(q / q')) of the model with defect D is calculated by the following formula 2: In addition, ΔE(D q ) is the formation energy of defect D at charge q, calculated using Eq. will be done.

[0423]

number

[0424]

number

[0425] In Formula 2 and Formula 3, E tot (D q ) is the charge q of the model including the defect D. Total energy, E tot (bulk) is the total energy of a defect-free model (perfect crystal), Δn i is the increase or decrease in the number of atoms i related to the defect, μ i is the chemical potential of atom i, ε VBM Missing The energy of the top of the valence band in the defect-free model, ΔV q is related to the electrostatic potential Correction term, E F is the Fermi energy.

[0426] Calculated V o The transition levels of H are shown in Figure 50. The numbers in Figure 50 indicate the depth from the bottom of the conduction band. From Figure 50, V for 1 oxygen atom o The transition level of H is 0.05e below the conduction band edge. V for 2 oxygen atoms o The transition level of H is located 0.11 eV below the conduction band edge. Therefore, each V o H will participate in electron trapping. That is, V o H It was revealed that V acts as a donor. o IGZO containing H is conductive It was revealed that it has.

[0427] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0428] (Embodiment 11)

[0429] The imaging device according to one embodiment of the present invention and a semiconductor device including the imaging device are and image reproducing devices equipped with recording media (typically DVD: Digital A disc that can play recording media such as Versatile Discs and display the images. In addition, the imaging device according to one embodiment of the present invention can be used in a display device. Examples of electronic devices that can use the semiconductor device including the imaging device include a mobile phone, Game consoles including portable ones, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras, goggle-type displays (head-mounted displays), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (ATMs) , vending machines, etc. Specific examples of these electronic devices are shown in Figure 51.

[0430] FIG. 51A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904. 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. and a display unit 904, the number of display units that the portable game machine has is not limited to this. The imaging device of one embodiment of the present invention can be used as the camera 909.

[0431] FIG. 51B shows a portable data terminal, which includes a first housing 911, a display unit 912, a camera 919, etc. The display unit 912 has a touch panel function that allows input and output of information. The imaging device of one embodiment of the present invention can be used as the camera 919.

[0432] FIG. 51C shows a digital camera, which includes a housing 921, a shutter button 922, and a microphone 9 23, a light emitting unit 927, a lens 925, etc. The imaging device according to the present invention may include an imaging device according to the present invention.

[0433] FIG. 51D shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, and a wristband 9 The display unit 932 may be a touch panel. The imaging device according to one embodiment of the present invention can be used for the laser 939.

[0434] FIG. 51(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2. The focal point of the lens 945 may be set to the position shown in FIG. can be equipped with an imaging device according to one aspect of the present invention.

[0435] FIG. 51(F) shows a mobile phone. A housing 951 includes a display unit 952, a microphone 957, and a speaker. The device includes a display 954, a camera 959, an input / output terminal 956, and an operation button 955. The imaging device of one embodiment of the present invention can be used for 959.

[0436] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0437] (Embodiment 12) Here, modifications of the transistor described in the above embodiment will be described with reference to FIGS. The transistor shown in FIG. 52 is formed on an insulating layer 824 on a substrate 821. The oxide semiconductor layer 828 is connected to an insulating layer 837. and a conductive layer 840 which is in contact with the insulating layer 7 and overlaps with the oxide semiconductor layer 828. The conductive layer 837 functions as a gate insulating film. The conductive layer 840 functions as a gate electrode layer. It has the function of

[0438] In addition, the insulating layer 846 in contact with the oxide semiconductor layer 828 and the insulating layer The transistor is provided with an insulating layer 847. At the end, the conductive layers 856 and 857 in contact with the oxide semiconductor layer 828 are Note that the conductive layers 856 and 857 are formed as a source electrode layer and a drain electrode layer. It has the function of

[0439] Note that the conductive layer, the oxide semiconductor layer, and the insulating For the layer, those shown in the above embodiment can be used as appropriate.

[0440] In the transistor illustrated in FIG. 52A, the oxide semiconductor layer 828 overlaps with the conductive layer 840. and a region 828a formed in the region including the impurity element and sandwiching the region 828a. The conductive layers 856 and 857 have regions 828b and 828c. The region 828a functions as a channel region. The regions 828b and 828c are Regions 828b and 828c have a lower resistivity than region 828a. It functions as a rain area.

[0441] Alternatively, as in the transistor illustrated in FIG. 52B, The regions 828d and 828e in contact with the conductive layers 856 and 857 are not doped with impurity elements. In this case, the regions 828d and 828e in contact with the conductive layers 856 and 857 and the region 82 Between the region 828 and the region 828a, there are regions 828b and 828c having an impurity element. d and 828e become conductive when a voltage is applied to the conductive layers 856 and 857. It functions as a source region and a drain region.

[0442] In the transistor shown in FIG. 52B, after the conductive layers 856 and 857 are formed, An impurity element is added to the oxide semiconductor layer by using the conductive layers 856 and 857 as a mask. By doing so, it can be formed.

[0443] The conductive layer 840 may have a tapered end. The angle θ1 between the surface where the conductive layer 840 and the conductive layer 840 are in contact with each other is 90°. or 10° to 85° or 15° to 85° or 30° to 8 It may be 5° or less, or between 45° and 85°, or between 60° and 85°. This improves the coverage of the insulating layer 846 on the side surfaces of the insulating layer 837 and the conductive layer 840. It is possible to do so.

[0444] Next, modified examples of the regions 828b and 828c will be described. 52(F) is an enlarged view of the oxide semiconductor layer 828 and its vicinity shown in FIG. In the above, the channel length L is the distance between the regions containing a pair of impurity elements.

[0445] As shown in FIG. 52C, in the cross section in the channel length direction, the region 828a and the region The boundaries of the regions 828b and 828c are aligned with or are spaced apart from the ends of the conductive layer 840 via the insulating layer 837. That is, in terms of the top surface shape, the area 828a and the area 828b are the same as the area 828a. The boundary of 8 c coincides or approximately coincides with the edge of the conductive layer 840 .

[0446] Alternatively, as shown in FIG. 52D, in the cross section in the channel length direction, a region 828a However, there is an area that does not overlap with the end of the conductive layer 840. This area functions as an offset area. The length of the offset region in the channel length direction is L off In addition, If there are multiple offset areas, the length of each offset area is L off That is. The L region is included in the channel region. off is less than 20% of the channel length L, Or less than 10%, or less than 5%, or less than 2%.

[0447] Alternatively, as shown in FIG. 52(E), in the cross section in the channel length direction, a region 828b , 828c has a region overlapping with the conductive layer 840 through the insulating layer 837. The overlap region in the channel length direction functions as a Length L ov L ov is less than 20% of the channel length L, or less than 10%, or Less than 5% or less than 2%.

[0448] Alternatively, as shown in FIG. 52(F), in the cross section in the channel length direction, a region 828a and region 828b, and region 828c. The regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, regions 828f and 828g overlap with insulating layer 837. , may overlap insulating layer 837 and conductive layer 840.

[0449] 52C to 52F, the transistor shown in FIG. As described above, the transistor shown in FIG. 52B may also have the same characteristics as those shown in FIG. ) structure can be applied as appropriate.

[0450] In the transistor shown in FIG. 53A, the end of the insulating layer 837 is located outside the end of the conductive layer 840. That is, the insulating layer 837 is located on the side of the conductive layer 840. Since the insulating layer 846 can be separated from the insulating layer 828a, the nitrogen contained in the insulating layer 846 can be Therefore, it is possible to suppress the intrusion of hydrogen, hydrogen, etc. into the region 828a that functions as a channel region. can.

[0451] In the transistor shown in FIG. 53B, the insulating layer 837 and the conductive layer 840 have a tapered shape. In other words, the insulating layer 837 and the conductive layer 840 have different taper angles. The angle θ1 between the contact surface and the side surface of the conductive layer 840, the oxide semiconductor layer 828 and the insulating layer The angle θ2 between the surface where the insulating layer 837 is in contact and the side surface of the insulating layer 837 is different. The angle θ2 is , or less than 90°, or between 30° and 85°, or between 45° and 70°. For example, when the angle θ2 is smaller than the angle θ1, the coverage of the insulating layer 846 is improved. When angle θ2 is greater than angle θ1, insulating layer 846 can be moved away from region 828a. Therefore, nitrogen, hydrogen, etc. contained in the insulating layer 846 form a region that functions as a channel region. It is possible to suppress the intrusion of 828a.

[0452] Next, regarding the modified examples of the regions 828b and 828c, FIG. 53(C) to FIG. 53(F) are used. 53C to 53F show the oxide semiconductor An enlarged view of layer 828 and its vicinity.

[0453] As shown in FIG. 53C, in the cross section in the channel length direction, the region 828a and the region The boundaries of the regions 828b and 828c are aligned with the ends of the conductive layer 840 through the insulating layer 837. That is, in terms of the top surface shape, the area 828a and the area 828b are the same as each other. The boundary of 28c coincides or nearly coincides with the edge of the conductive layer 840.

[0454] Alternatively, as shown in FIG. 53D, in the cross section in the channel length direction, a region 828a However, there is an area that does not overlap with the conductive layer 840. This area functions as an offset area. That is, in the top view, the ends of the regions 828b and 828c are aligned with the ends of the insulating layer 837. , and does not overlap the ends of the conductive layer 840.

[0455] Alternatively, as shown in FIG. 53E, in the cross section in the channel length direction, a region 828b , 828c has a region overlapping with the conductive layer 840 via the insulating layer 837. In other words, in the top view, the ends of the regions 828b and 828c are It overlaps with conductive layer 840 .

[0456] Alternatively, as shown in FIG. 53(F), in the cross section in the channel length direction, a region 828a and region 828b, and region 828c. The regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, regions 828f and 828g overlap with insulating layer 837. , may overlap insulating layer 837 and conductive layer 840.

[0457] 53(C) to 53(F), the description of the transistor shown in FIG. As described above, the transistor shown in FIG. 53B may also have the same characteristics as those shown in FIG. ) can be appropriately applied.

[0458] In the transistor shown in FIG. 54A, the conductive layer 840 has a stacked structure and is in contact with the insulating layer 837. The conductive layer 840a is in contact with the conductive layer 840a, and the conductive layer 840b is in contact with the conductive layer 840a. The end of the conductive layer 840a is located outside the end of the conductive layer 840b. a has a shape protruding from the conductive layer 840b.

[0459] Next, modified examples of the regions 828b and 828c will be described. 54(E) is an enlarged view of the oxide semiconductor layer 828 and its vicinity shown in FIG. 54(A).

[0460] As shown in FIG. 54B, in the cross section in the channel length direction, the region 828a and the region The boundary between the regions 828b and 828c is the end of the conductive layer 840a included in the conductive layer 840 and the insulating The layers 837 are aligned or substantially aligned with each other. The boundaries of the regions 828b and 828c coincide or nearly coincide with the ends of the conductive layer 840. There are.

[0461] Alternatively, as shown in FIG. 54C, in the cross section in the channel length direction, a region 828a However, there is an area that does not overlap with the conductive layer 840. This area functions as an offset area. That is, in the top view, the ends of the regions 828b and 828c are the ends of the conductive layer 840. Doesn't overlap.

[0462] Alternatively, as shown in FIG. 54(D), in the cross section in the channel length direction, a region 828b , 828c has an area overlapping with the conductive layer 840, here the conductive layer 840a. This is called the overlap region. In other words, in the top view, the ends of the regions 828b and 828c are , overlapping conductive layer 840a.

[0463] Alternatively, as shown in FIG. 54E, in the cross section in the channel length direction, a region 828a and region 828b, and region 828c. The impurity element is doped into the regions 828f and 828g through the conductive layer 840a. Therefore, the regions 828f and 828g have a higher concentration of impurity elements than the regions 828b and 828c. Here, the regions 828f and 828g are connected to the conductive layer 840a and the conductive layer 840b, and have a low resistance. It overlaps, but may overlap with conductive layer 840a and conductive layer 840b.

[0464] The end of the insulating layer 837 may be located outside the end of the conductive layer 840a.

[0465] Alternatively, the sides of the insulating layer 837 may be curved.

[0466] Alternatively, the insulating layer 837 may have a tapered shape. The angle between the surface of the insulating layer 837 and the side of the insulating layer 837 is less than 90°, preferably 3 It may be greater than or equal to 0° and less than 90°.

[0467] As shown in FIG. 54E, the oxide semiconductor layer 828 is more inhomogeneous than the regions 828b and 828c. By having regions 828f and 828g with low concentration of pure elements and high resistivity, Therefore, the electric field in the drain region can be reduced. It is possible to reduce degradation such as fluctuation in threshold voltage.

[0468] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0469] (Embodiment 13) In this embodiment, an example of an image processing engine of an imaging device (image sensor) is shown in FIG. This will be explained using 55.

[0470] The imaging device includes an imaging unit 4000, an analog memory unit 4010, an image processing engine unit 4020, The imaging unit 4000 is made up of a plurality of pixels arranged in a matrix. The pixel includes a number of pixels, a driver circuit 4001, and a readout circuit 4002. The analog memory section 4010 is made up of a plurality of photodiodes and transistors. Each analog memory 4011 includes an image pickup unit 40 The number of memory cells is equal to or greater than the number of pixels in the 00. The memory 4011 can store one frame of the imaging data 4005 acquired by the imaging unit 4000. do.

[0471] The operation of the imaging device will be described below. In the first step, each pixel captures one frame. The first image data 4005 is acquired as the first image data. The first imaging data 4005 is read out. A so-called rolling shutter method may be used. A so-called global shutter method may be used in which the image data 4005 is sequentially read out by exposing the image data 4005 at once. .

[0472] By using the rolling shutter method, the image data 4005 of a certain row of pixels is read out. When the pixel is being illuminated, other rows of pixels can be exposed, allowing the frame rate of the image to be increased. In addition, by using the global shutter method, it is possible to capture images with a moving subject without any problems. Even if the object is not photographed, it is possible to obtain a captured image with little distortion.

[0473] In the second step, the first imaging data 4005 acquired by each pixel is read out and output to the read circuit 40. The image is stored in the first analog memory 4011 via the image sensor 402. The first image pickup data 4005 is stored as analog data in the first analog memory 4011. In other words, since analog-to-digital conversion processing is not required, It is easy to increase the frame frequency of imaging.

[0474] After that, the first step and the second step are repeated n times. However, in the nth repetition, In this case, the n-th image data 4005 acquired by each pixel is read out via a circuit 4002. The signal is stored in the nth analog memory 4011 .

[0475] As a third step, the image processing engine 4020 reads a plurality of analog memories 4 Using the first imaging data 4005 to the n-th imaging data 4005 stored in Desired image processing is performed, and post-image-processing captured data 4025 is obtained.

[0476] In the fourth step, the image-processed captured data 4025 is converted into a digital signal by an A / D converter 4030. , analog-to-digital conversion is performed to obtain image data 4035.

[0477] As one of the image processing methods, a processed image without focus blur is obtained from multiple captured image data 4005. Acquire imaging data 4025. In order to acquire the post-image-processing imaging data 4025, The sharpness of each image data 4005 is calculated, and the image data 4005 with the highest sharpness is selected as the image data 4005. It is possible to obtain the processed image data 4025. 5, areas with high sharpness are extracted and stitched together to produce image data 4 after image processing. 025.

[0478] In addition, one of the different image processing methods is to select an image with optimal brightness from multiple image data 4005. The post-image-processing captured image data 4025 is obtained. In order to do this, the maximum brightness of each image data 4005 is calculated, and the maximum brightness reaches the saturation value. After removing the image data 4005, the image data 4025 is extracted from the image data 4005. It is possible to configure it to obtain.

[0479] In addition, the minimum brightness of each image data 4005 is calculated, and the image data in which the minimum brightness reaches the saturation value is selected. The image processing image data 4025 is obtained from the image data 4005 from which the image processing image data 4005 has been removed. It is possible to configure it in this way.

[0480] In addition, the first and second steps are performed in accordance with the lighting of the flash light for imaging. When the camera is rotated, the image data 4005 corresponding to the timing when the optimal amount of light is irradiated is It is possible to obtain

[0481] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0482] 40 Silicon Substrate 50 Transistors 51 Transistor 52 Transistor 53 Transistor 54 Transistor 55 Transistor 56 Transistor 58a Transistor 58b Transistor 58c transistor 60 Photodiode 60a photodiode 60b Photodiode 60c Photodiode 60p light receiving section 61 Anode 62 Cathode 63 Low resistance region 64 Light Control Layer 66 areas 70 Conductors 71 Wiring layer 72 wiring layer 73 Wiring layer 80 Insulating layer 81 Insulating layer 82 Insulating layer 83 Insulating Layer 84 Insulating Layer 85 Insulating Layer 90 pixels 91 Circuit 91a area 91b area 91c area 92 Circuit 92a area 101 Transistor 102 Transistor 103 Transistor 104 Transistor 105 Transistor 106 Transistor 107 Transistor 108 Transistor 109 Transistor 110 Transistor 111 Transistor 112 Transistor 115 Substrate 120 Insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130A Oxide semiconductor film 130b Oxide semiconductor layer 130B Oxide semiconductor film 130c Oxide semiconductor layer 130C Oxide semiconductor film 140 Conductive layer 141 Conductive layer 142 Conductive Layer 150 Conductive layer 151 Conductive layer 152 Conductive layer 156 Resist Mask 160 Insulating layer 160A Insulating film 170 Conductive Layer 171 Conductive Layer 171A Conductive film 172 Conductive Layer 172A Conductive film 173 Conductive Layer 175 Insulating Layer 180 Insulating layer 190 Insulating Layer 231 areas 232 areas 233 areas 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 316 Wiring 317 Wiring 331 areas 332 areas 333 areas 334 areas 335 areas 400 Substrates 401 Insulating layer 402 Insulating layer 402a Insulating layer 402b Insulating layer 404 Conductive layer 404a Conductive layer 404b conductive layer 406 Semiconductor Layer 406a Semiconductor layer 406b Semiconductor layer 407a area 407a1 area 407a2 area 407b area 407b1 area 407b2 area 408 Insulating layer 408a Insulating layer 412 Insulating layer 414 Conductive layer 414a conductive layer 414b Conductive layer 416a conductive layer 416a1 conductive layer 416a2 conductive layer 416b Conductive layer 416b1 Conductive layer 416b2 Conductive layer 418 Insulating layer 428 Insulating Layer 501 signal 502 signal 503 signal 504 signal 505 signal 506 signal 507 signal 508 signal 509 signal 510 period 511 period 520 period 531 period 610 period 611 period 612 period 621 period 622 period 623 period 631 period 701 signal 702 signal 703 Signal 704 signal 705 signal 821 Substrate 824 Insulating layer 828 Oxide semiconductor layer 828a area 828b area 828c area 828d area 828e area 828f area 828g area 828h area 828i area 837 Insulating layer 840 Conductive Layer 840a Conductive layer 840b conductive layer 846 Insulating Layer 847 Insulating layer 856 Conductive layer 857 Conductive layer 901 Case 902 Case 903 Display section 904 Display section 905 Mike 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 Case 912 Display section 919 Camera 921 Case 922 Shutter button 923 Mike 925 Lens 927 Light emitting part 931 Case 932 Display section 933 Wristband 939 Camera 941 Case 942 Case 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Case 952 Display section 954 Speaker 955 Button 956 Input / output terminal 957 Mike 959 Camera 1100 layers 1200 layers 1300 layers 1400 layers 1500 Insulation layer 1510 Light blocking layer 1520 Organic resin layer 1530 Color Filter 1530a Color Filter 1530b Color Filter 1530c Color Filter 1540 Microlens Array 1550 Optical conversion layer 1600 Support Board 1700 pixel matrix 1730 Circuit 1740 Circuit 1750 circuits 1760 Circuit 1770 Terminal 1800 Shift Register 1810 Shift Register 1900 Buffer circuit 1910 Buffer circuit 2100 Analog Switch 2110 Vertical output line 2200 output line 4000 Imaging unit 4002 Circuit 4005 Imaging data 4010 Analog memory section 4011 Analog Memory 4020 Image Processing Engine 4025 Image processing image data 4030 A / D conversion section 4035 Image data

Claims

1. A back-illuminated imaging device having a silicon substrate, a contact plug, and a wiring layer, a channel formation region of a transistor and first to fifth photodiodes are provided in the silicon substrate; the light receiving surfaces of the first to fifth photodiodes are disposed on a back surface side of the silicon substrate, the channel formation region is disposed on a front surface of the silicon substrate, the front surface being opposite to a back surface of the silicon substrate; the first photodiode has a substantially rectangular shape in a plan view of the back surface side, the second photodiode is disposed adjacent to the first photodiode at a position corresponding to a first side of the substantially rectangular shape, the third photodiode is disposed adjacent to the first photodiode at a position corresponding to a second side of the substantially rectangular shape, the fourth photodiode is disposed adjacent to the first photodiode at a position corresponding to a third side of the substantially rectangular shape, the fifth photodiode is disposed adjacent to the first photodiode at a position corresponding to a fourth side of the substantially rectangular shape, a first hollow portion is provided between the first photodiode and the second photodiode; a second hollow portion is provided between the first photodiode and the third photodiode; a third hollow portion is provided between the first photodiode and the fourth photodiode; a fourth hollow portion is provided between the first photodiode and the fifth photodiode; The first hollow portion to the fourth hollow portion are arranged to be spaced apart from each other, In a plan view, the first hollow portion has a size in a direction along the first side larger than a size in a direction perpendicular to the first side, In a plan view, the second hollow portion has a size in a direction along the second side larger than a size in a direction perpendicular to the second side, The third hollow portion has a size in a direction along the third side larger than a size in a direction perpendicular to the third side in a plan view, The fourth hollow portion has a size in a direction along the fourth side greater than a size in a direction perpendicular to the fourth side in a plan view, the back surface of the silicon substrate is defined as an upper side and the front surface of the silicon substrate is defined as a lower side, the contact plug has a region that is disposed above the wiring layer and below the silicon substrate, the contact plug is connected to an anode of the first photodiode via a contact region where the contact plug and the silicon substrate are in contact; the contact plug is connected to the wiring layer; The wiring layer has a function of supplying a potential to an anode of the first photodiode.

2. A back-illuminated imaging device having a silicon substrate, a contact plug, and a wiring layer, a channel formation region of a transistor and first to fifth photodiodes are provided in the silicon substrate; the light receiving surfaces of the first to fifth photodiodes are disposed on a back surface side of the silicon substrate, the channel formation region is disposed on a front surface of the silicon substrate, the front surface being opposite to a back surface of the silicon substrate; the first photodiode has a substantially rectangular shape in a plan view of the back surface side, the second photodiode is disposed adjacent to the first photodiode at a position corresponding to a first side of the substantially rectangular shape, the third photodiode is disposed adjacent to the first photodiode at a position corresponding to a second side of the substantially rectangular shape, the fourth photodiode is disposed adjacent to the first photodiode at a position corresponding to a third side of the substantially rectangular shape, the fifth photodiode is disposed adjacent to the first photodiode at a position corresponding to a fourth side of the substantially rectangular shape, a first hollow portion is provided between the first photodiode and the second photodiode; a second hollow portion is provided between the first photodiode and the third photodiode; a third hollow portion is provided between the first photodiode and the fourth photodiode; a fourth hollow portion is provided between the first photodiode and the fifth photodiode; The first hollow portion to the fourth hollow portion are arranged to be spaced apart from each other, The first hollow portion has a shape extending along the first side in a plan view, The second hollow portion has a shape extending along the second side in a plan view, The third hollow portion has a shape extending along the third side in a plan view, The fourth hollow portion has a shape extending along the fourth side in a plan view, the back surface of the silicon substrate is defined as an upper side and the front surface of the silicon substrate is defined as a lower side, the contact plug has a region that is disposed above the wiring layer and below the silicon substrate, the contact plug is connected to an anode of the first photodiode via a contact region where the contact plug and the silicon substrate are in contact; the contact plug is connected to the wiring layer; The wiring layer has a function of supplying a potential to an anode of the first photodiode.

3. In claim 1 or 2, The contact region is disposed so as not to overlap with the first to fourth hollow portions in a plan view.

4. 4. An electronic device comprising: the imaging device according to claim 1; and a display unit.

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