Power-Based Adaptive SRAM Allocation

Abstract

Techniques for processing computer instructions are provided that include obtaining instruction state memory entry information for an instruction, identifying a slot in the instruction state memory having a selectably powered row and block for the instruction state memory entry based on a clustering criterion, and placing the instruction state memory entry in the identified slot.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. patent application Ser. No. 16 / 556,139, filed Aug. 29, 2019, entitled “ADAPTABLE ALLOCATION OF SRAM BASED POWER,” the entire contents of which are incorporated herein by reference. [Background technology]

[0002] In a computer system, volatile memory, such as static random access memory, consumes power when powered on. Techniques are constantly being developed to improve the power consumption of volatile memory.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram of an example device capable of implementing one or more features of the disclosure. [Diagram 2] FIG. 2 illustrates details of the device of FIG. 1, according to an example. [Diagram 3] 1 is a block diagram of an instruction dispatch unit, according to an example. [Figure 4] FIG. 2 is a block diagram of an instruction status memory, according to an example. [Diagram 5] FIG. 1 illustrates an entry insertion operation for an instruction state memory, according to an example. [Figure 6] FIG. 2 is a block diagram of an exemplary embodiment of an instruction state memory. [Figure 7] 1 is a flow chart of a method for placing entries in an instruction status memory, according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] Techniques are provided for processing a computer instruction that include obtaining information about an instruction state memory entry for the instruction, identifying a slot in the instruction state memory having a selectably powered row and block for the instruction state memory entry based on a clustering criterion, and placing the instruction state memory entry in the identified slot.

[0006] 1 is a block diagram of an example device 100 capable of implementing one or more features of the disclosure. The device 100 may be, for example, but not limited to, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, a tablet computer, or any other computing device. The device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. The device 100 also includes one or more input drivers 112 and one or more output drivers 114. Any input driver 112 may be embodied as hardware, a combination of hardware and software, or software, and serves the purpose of controlling (e.g., controlling the operation of, receiving input from, and providing input to) the input device 108. Similarly, any output driver 114 may be embodied as hardware, a combination of hardware and software, or software, and serves the purpose of controlling (e.g., controlling the operation of, receiving input from, and providing input to) the output device 110. It will be understood that device 100 may include additional components not shown in FIG.

[0007] In various alternatives, the processor 102 may include a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, the memory 104 may be located on the same die as the processor 102 or may be separate from the processor 102. The memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0008] The storage devices 106 include fixed or removable storage devices, such as, but not limited to, a hard disk drive, a solid state drive, an optical disk, or a flash drive. The input devices 108 include, but are not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). The output devices 110 include, but are not limited to, a display, a speaker, a printer, a haptic feedback device, one or more lights, an antenna, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0009] The input driver 112 and the output driver 114 include one or more hardware, software, and / or firmware components configured to interface with and drive the input device 108 and the output device 110, respectively. The input driver 112 communicates with the processor 102 and the input device 108, enabling the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, enabling the processor 102 to send output to the output device 110. The output driver 114 includes an accelerated processing device (APD) 116 coupled to a display device, which in some examples is a physical display device or a simulated device that uses a remote display protocol to show output. The APD 116 is configured to accept computational commands and graphic rendering commands from the processor 102 for processing the commands and provide pixel output to the display device 118 for display. As described in further detail below, the APD 116 includes one or more parallel processing units configured to perform computations according to a single instruction, multiple data (SIMD) paradigm. Thus, although various functions are described herein as being performed by or in conjunction with the APD 116, in various examples, the functions described as being performed by the APD 116 may additionally or instead be performed by other computing devices having similar functionality that are not driven by a host processor (e.g., processor 102) and configured to provide graphical output to a display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm may be configured to perform the functions described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to the SIMD paradigm may perform the functions described herein.

[0010] 2 illustrates details of device 100 and APD 116, according to an example. Processor 102 (FIG. 1) executes operating system 120, drivers 122, and applications 126, and may alternatively or additionally execute other software. Operating system 120 controls various aspects of device 100, such as managing hardware resources, handling service requests, scheduling and controlling the execution of processes, and performing other operations. APD driver 122 controls the operation of APD 116 and sends tasks or other work, such as graphic rendering tasks, to APD 116 for processing. In some embodiments, APD driver 122 includes a just-in-time compiler that compiles programs for execution by processing components of APD 116 (such as SIMD unit 138, described in more detail below).

[0011] The APD 116 executes commands and programs for selected functions, such as graphic and non-graphic operations that may be suitable for parallel processing. The APD 116 may be used to perform graphics pipeline operations, such as pixel operations, geometry calculations, and rendering images to a display device, based on commands received from the processor 102. The APD 116 also performs computational operations not directly related to graphic operations, such as video-related operations, physics simulations, computational fluid dynamics, or other tasks, based on commands received from the processor 102.

[0012] The APD 116 includes a computation unit 132 that includes one or more SIMD units 138 (or another unit) configured to execute operations at the request of the processor 102 in a parallel manner according to the SIMD paradigm. The SIMD paradigm is where multiple processing elements share a single program control flow unit and program counter, thus executing the same program, except that they may execute the program with different data. In one example, each SIMD unit 138 includes 16 lanes, each lane executes the same instruction simultaneously with other lanes in the SIMD unit 138, except that they may execute the instruction with different data. If not all lanes need to execute a given instruction, the lane may be switched off by predication. Predication may also be used to execute programs with branching control flows. More specifically, for programs with conditional branches or other instructions where the control flow is based on the calculations performed by the individual lanes, the predication of the lane corresponding to the control flow path is not currently being executed, and serial execution of the different control flow paths allows for arbitrary control flow.

[0013] The APD 116 includes one or more caches 142 accessible to the compute units 132. The caches 142 implement a cache coherency protocol to allow data stored in any individual cache 142 to be accessible to any of the compute units 132.

[0014] The parallelism provided by the computation units 132 is suitable for graphics-related operations such as pixel value calculations, vertex transformations, and other graphics operations. Thus, in some instances, a graphics pipeline 134, which accepts graphics processing commands from the processor 102 (or another entity), provides computational tasks to the computation units 132 for execution in parallel.

[0015] Computation units 132 are also used to perform non-graphics related computational tasks, or computational tasks that are not performed as part of the "normal" operations of graphics pipeline 134 (e.g., custom operations performed to supplement the processing performed for the operations of graphics pipeline 134). Applications 126 or other software executing on processor 102 send programs (kernels) defining such computational tasks to APD 116 for execution.

[0016] The basic unit of execution in the compute units 132 is a work item. Each work item represents a single instantiation of a program (sometimes referred to as a "kernel") that is to be executed in parallel within a particular lane. Work items may be executed simultaneously (or partially simultaneously and partially serially) as a "wavefront" on a single SIMD processing unit 138. One or more wavefronts are included in a "workgroup" that includes a collection of work items designed to execute the same program. A workgroup may be executed by executing each of the wavefronts that make up the workgroup. In alternative examples, a wavefront executes on a single SIMD unit 138 or on different SIMD units 138. The APD scheduler 136 is configured to perform operations related to scheduling the various workgroups and wavefronts on the compute units 132 and SIMD units 138. In a use case, the application 126 indicates to the APD 116 a scheme for executing a kernel in terms of the "size" of the execution of the kernel, where "size" indicates the number of work items. In some modes of operation, the application 126 determines how work items are divided into workgroups. In other modes of operation, the APD 116 and / or the driver 122 determine how work items are divided into workgroups. The size of the kernel execution and the number of work items to be executed per workgroup determine how many workgroups will be executed for a given kernel execution. Those workgroups are executed by the APD 116. The APD scheduler 136 assigns workgroups to compute units 132 for execution based on the availability of computing resources (e.g., how many workgroups are assigned to a particular compute unit 132 and whether other resources such as memory, registers, or other resources are available).

[0017] 3 is a block diagram of an example instruction dispatch unit 300. Instruction dispatch unit 300 may be included in a processor, such as SIMD unit 138, processor 102, or another processor not described herein.

[0018] The instruction dispatch unit 300 includes an instruction fetch block 302, a decode block (decoder) 304, and an instruction status memory 310. The instruction dispatch unit 300 also includes a low latency block 306 and a high latency block 308. The low latency block provides low latency data to the instruction status memory 310 at the request of the decode unit 304. Low latency data is data required for the execution of an instruction whose latency to be fetched is lower than the latency to be fetched of high latency data. The high latency block provides high latency data to the instruction status memory 310 at the request of the decode unit 304. Generally, low latency data is data that can be retrieved from a structure that is close to the decode unit 304 in terms of signal propagation latency. One example of such a structure includes a custom computation circuit that receives operations to calculate certain values ​​from the decode unit 304, calculates those values, and provides those values ​​to the instruction status memory 310. Another example of a low latency structure includes memories that are "close" to the decode unit 304 and the instruction status memory 310, so that the access latency to those memories is less than the fastest access latency for any memory in the high latency data unit 308. The low latency data block 306 includes any collection of structures, including processing circuits or low latency memories, etc., that provide such low latency data. High latency data is data retrieved from a structure that has a latency greater than the longest latency of the low latency data unit 306. Examples of high latency data structures include caches (including the lowest level caches, such as level 0 caches), system memory, non-volatile storage, or other structures. The high latency data block 308 includes all such structures, or, if such structures are physically external to the instruction dispatch unit 300, interfaces within the instruction dispatch unit 300 to such structures (i.e., hardware circuits that send requests for high latency data and receive high latency data in response).

[0019] During operation, instruction fetch unit 302 fetches instructions to be executed and provides them to decode unit 304. Decode unit 304 analyzes the instructions to generate micro-ops for execution by functional units not shown in detail. A functional unit may be any of a variety of units that perform operations on instructions, such as an arithmetic logic unit (ALU), a load / store unit that reads from or writes to memory, or other units. Virtually all processors that execute programs composed of instructions selected from an instruction set architecture have a decode unit and functional units.

[0020] Instructions to be executed consume either or both low latency and high latency data. Various processors have instruction sets that include some instructions that consume low latency data but not high latency data, some instructions that consume high latency data but not low latency data, some instructions that consume both high latency and low latency data, and some instructions that consume neither high latency data nor low latency data.

[0021] After the decode unit 304 decodes an instruction, if the instruction requires low latency data, the decode unit 304 fetches the low latency data from the low latency data block 306. Once the low latency data is obtained, the decode unit 304 places an entry in the instruction status memory 310 containing the micro-ops and the low latency data for the instruction. The decode unit 304 also triggers the fetching of high latency data from the high latency data block 308. Once the high latency data is retrieved from the high latency data block 308, the instruction is ready for execution and the instruction status memory 310 sends the instruction to the functional units. A single instruction set architecture instruction may result in multiple entries in the instruction status memory 310. In other words, the decode unit 304 may generate multiple micro-ops for each instruction set architecture instruction and generate an entry for each micro-op in the instruction status memory 310.

[0022] In addition to sending micro-ops and low latency data to the instruction state memory 310, the decode unit 304 also sends information about power control to the instruction state memory 310. The instruction state memory 310 includes a number of individually powerable blocks that power on and off depending on the contents of the instruction state memory 310 and on the power control information received from the decode unit 304.

[0023] FIG. 4 is a detailed block diagram of an instruction state memory 310, according to one example. The instruction state memory 310 includes multiple blocks 402 organized into multiple rows 404. Each row 404 includes one or more entries. Within a row 404, each block 402 stores a different type of data than the other blocks 402. In particular, a block 402 stores "core instruction state," which is data that identifies the micro-operation that the entry is for, or low latency data of a particular type. Each block 402 may be powered on or off separately from each other block. The term "power on or power off" collectively refers to performing either clock gating (suspending or resuming the clock to preserve data in the memory elements, but preventing reads or writes) or power gating (switching power on or off to the block 402). Each row 404 may also be powered on or off individually. The controller 401 powers rows on and off depending on the contents of the memory 400, whether an entry is placed in or removed from a particular row 404, and depending on information about power control received from the decoding unit 204.

[0024] In FIG. 4 , blocks 402 in the same position within each row store the same type of data. In one example, the blocks 402 for state 1 store the same type of data, all of the blocks 402 for state 2 store the same type of data, and so on. A particular instruction may require any subset of the types of data that can be stored in a row 404. More specifically, one type of instruction may require data stored in a block for state 1 and data stored in a block for state 3, but may not require data stored in other blocks, such as a block for state 2. Thus, an entry in the instruction state memory 310 for that instruction stores data in a block for state 1 and a block for state 2, but not in other blocks.

[0025] In some circumstances, the controller 401 powers off a block in a row if no entry in the row stores data of the type of block 402. After detecting that the last entry in the row 404 using data for a particular block 402 has been removed from the row 404, the controller immediately powers down the block 402. In some embodiments, after detecting that the last entry in the row 404 using data for a particular block 402 has been removed from the row 404, the controller transitions to a waiting period. During the waiting period, if the controller 401 determines that another entry will be placed in the row 404 using data associated with the block 402, the controller 401 does not power down the block 402. During the waiting period, if the controller 401 determines that no entry will be placed in the row 404 using data associated with the block 402, the controller 401 powers down the block 402.

[0026] The wait period for powering down the block 402 may be determined in any technically feasible manner. The wait period may be constant regardless of the state of the instruction state memory 310, or may be variable depending on the state of the instruction state memory 310 and / or the state of the instructions decoded by the decode unit 304. In some embodiments, the wait period for powering down the block 402 is based on a comparison between the power consumed by leaving the block 402 powered on during an idle period and the power saved by turning the block 402 off and then on again during an idle period. The idle period is the number of cycles between when the block 402 becomes empty and when a new entry is placed in the block 402. In some examples, the idle period is known from the state of the instruction dispatch unit 300. In particular, if there are instructions being processed in the instruction dispatch unit 300 when a block 402 becomes empty for which an entry using the block 402 has not yet been generated in the instruction state memory 310 (e.g., low latency data has been fetched), but it is known that the instruction will require an entry in the block 402 within a certain number of cycles after the block 402 becomes empty, then the certain number of cycles is the duration of the idle period. If there are no instructions in the instruction dispatch unit 300, the idle period is a default idle period, which in some embodiments is the minimum number of cycles between when the instruction dispatch unit receives an instruction that requires space in the block 402 and when the instruction will actually occupy that block 402. In some embodiments, the amount of power consumed by leaving the block 402 powered on during the idle period versus the amount of power consumed by powering the block 402 off and then powering it on during the idle period is predetermined by the designer.In that situation, the instruction state memory 310 is configured to be powered off and powered on again if the idle duration is above a threshold, and to remain powered on if the idle duration is equal to or less than the threshold, the threshold being a crossover point where it becomes more costly to keep block 402 powered on instead of powering block 402 off and then powering block 402 on. In some examples, the threshold is programmable, for example, via a configuration register.

[0027] In some situations, if a row does not store an entry, the controller 401 powers off the row 404. In some embodiments, after detecting that the last entry in the row 404 has been removed from the row 404, the controller immediately powers down the row 404. In some embodiments, after detecting that the last entry in the row 404 has been removed from the row 404, the controller transitions to a waiting period. If the controller 401 determines that another entry will be placed in the row 404 during the waiting period, the controller 401 does not power down the row 404. If the controller determines that another entry will not be placed in the row 404 during the waiting period, the controller 401 powers down the row 404.

[0028] The wait period for powering down a row 404 may be determined in any technically feasible manner. The wait period may be constant regardless of the state of the instruction status memory 310, or may be variable depending on the state of the instruction status memory 310 and / or the state of the instructions decoded by the decode unit 304. In some embodiments, the wait period for powering down a row 404 is based on the number of rows 404 that are powered on. In particular, the more rows that are powered on, the shorter the delay 404. In some embodiments, the wait period for powering down a row 404 is based on the number of freed entries in other rows 404 that are powered on. The more freed entries that exist in other rows 404 that are powered on, the shorter the delay. In some embodiments, the wait period is based on how many entries are needed for the in-flight instructions. In some embodiments, the instruction status memory 310 determines how to power down a row 404 in a manner similar to that described above, regardless of whether or not it powers down a block 402, with "row 404" being replaced with "block 402."

[0029] 5 illustrates an operation for placing a new entry in the command state memory 310, according to one example. The controller 401 attempts to cluster entries together within a row 404 to maximize the number of rows 404 that can be turned off. In particular, when the controller 401 receives a new entry to place in the command state memory 310, the controller 401 determines which row 404 has the fewest empty entry slots and still has at least one empty entry slot, and places the new entry in one of the empty entry slots within the identified row 404. In one example, if two rows 404 have the same number of empty entries, the controller 401 selects the row 404 with the most recent entry. Selecting the row 404 with the fewest number of empty entry slots to receive the new entry reduces the total number of active rows 404, allowing a greater number of rows 404 to be powered down.

[0030] In some situations, upon determining that a new entry requires a particular type of low latency data and therefore requires that a particular block 402 within the row 404 in which the entry is to be placed needs to be powered on, the controller 401 selects the row 404 with the block 402 already powered on instead of the row 404 with that block 402 powered off. In some embodiments, if two rows 404 have the same number of empty entries, but one has the block 402 required by the new entry powered on and one does not have that block 402 powered on, the controller 401 selects the row 404 with the required block 402 powered on. In some embodiments, the controller 401 selects the row 404 with the required block 402 powered on even if that row 404 has more empty entries than another row 404, so long as the selected row 404 is the row 404 with the minimum number of empty entries that have the required block 402 powered on. In some embodiments, the controller 401 selects a row 404 with a required block 402 that is powered on if the row has more empty entries than another row 404 with a required block 402 that is powered off, as long as the number of empty entries in the row 404 to be selected is within a threshold number or a threshold percentage of the number of empty entries in the row 404 with the required block 402 that is powered off.

[0031] 6 is a block diagram of an exemplary embodiment of the instruction state memory 310, a SIMD unit instruction state memory 600. The SIMD unit instruction state memory 600 includes a block 602 for core instruction state, a block 604 for filtering weights, and a block 606 for reference data.

[0032] As described above, the SIMD unit 138 executes a shader program that includes a sequence of instructions. The instruction dispatch unit 300, which includes an instruction state memory 310, fetches and decodes instructions and places the decoded instructions and state data in the instruction state memory 310.

[0033] The core instruction state is information that identifies the operation that needs to be performed for the instruction to be executed. In one example, the instruction is an add instruction and the core instruction state indicates that an add operation needs to be performed. The block for filtering weights 604 stores filtering weights for texture instructions. More specifically, some instructions require manipulation of texture data by application of a filter. The filters may include weights determined based on the instruction identifier, and those weights may be applied to operands such as texels. In this example, the filter weights are low latency data and the texels are high latency data. The filter weights are placed in the block for filtering weights 604 in response to being retrieved from the low latency data block 306.

[0034] The block 606 for reference data stores reference data to be used by the instruction. Reference data is data to be compared to another value, such as an item of high latency data. In one example, the block 606 for reference data stores a depth value for a pixel to be used for Z-testing (sometimes also referred to as a depth test). In some examples, a pixel shader program performs a depth test against a value stored in a depth buffer. In particular, the pixel shader compares the depth value of the pixel being processed with the value in the depth buffer and may discard the pixel and / or modify the depth buffer as a result. The reference data is the depth value for the pixel, and the operand is the value retrieved from the depth buffer.

[0035] An instruction typically uses block 602 for core instruction state. Thus, in some embodiments, when row 404 is powered on, block 602 for core instruction state is not powered off. An instruction may use either block 604 for filtering weights or block 606 for reference data, or both, depending on the identifier of the instruction. Thus, when an instruction is in a particular row 404, the blocks for low latency data used by that instruction are switched on. In various embodiments, if controller 401 determines that an instruction using either filtering weights or reference data or both will be placed in row 404 with those blocks powered off, controller 401 powers on those blocks.

[0036] 7 is a flow chart of a method 700 for placing entries in instruction status memory 310, according to one example. Although described with respect to the systems of FIGS. 1-6, one skilled in the art will understand that any system configured to perform the steps of method 700 in any technically feasible order is within the scope of the present disclosure.

[0037] Method 700 begins at step 702, where controller 401 of instruction state memory 310 receives information about an instruction state memory entry for an instruction. This information is received from decoder 304 and indicates what type of low latency data is used by the instruction associated with the instruction state memory entry. If the instruction requires low latency data to be fetched, decoder 304 requests that information from low latency data block 306. Decoder 304 also requests high latency data from high latency data block 308. Note that decoder 304 may expand an instruction into multiple micro-ops, and each micro-op may require an instruction state memory entry. In this case, aspects of method 700 (such as steps 704 and 706), or all of method 700, are repeated for each micro-op generated from the instruction. In some embodiments, the clustering criteria considers the total number of slots required for the instruction, instead of only one slot.

[0038] In step 704, the controller 401 identifies slots in the instruction state memory 310 based on a clustering criterion. The clustering criterion exists to cluster more entries in fewer rows 404, allowing more rows 404 to be powered off. In some embodiments, the clustering criterion clusters entries in rows 404 that have the same block 402 powered on and the same block 402 powered off.

[0039] In some embodiments, the clustering criterion is as follows: The controller 401 attempts to place a new entry in the row 404 with the smallest, non-zero number of empty entries. This action results in a concentration of entries in the row 404.

[0040] In some embodiments, the clustering criteria takes into account the powered-on blocks 402 within the rows 404 used. In one example, if there are multiple rows 404 with the minimum number of entries (i.e., if two or more rows 404 have the same number of empty entries that are also the minimum number of empty entries), the controller 401 selects the row 404 that results in the minimum number of blocks 402 being powered on. For example, if a new entry for an instruction requires low latency data for block 2, and one row 404 with the minimum number of entries has block 2 powered on and one row 404 with the minimum number of entries has block 2 powered off, the controller 401 selects the row 404 with block 2 powered on to place the new entry. In some embodiments, the rows 404 do not have to have the same number of empty entries, and if a row 404 has a number of empty entries within a threshold number or within a threshold percentage of the minimum number of empty entries in the row 404, and the row 404 has a needed block powered on, but the row 404 with the fewer empty entries does not have a needed block powered on, the controller 401 selects the row 404 with the needed block powered on instead of the row 404 with the fewer empty entries. In some embodiments, the controller 401 keeps one row 404 powered on for each possible combination of blocks 402 that can be powered on, or for a subset of the combinations of blocks 402 that can be powered on. In this embodiment, for a new entry, the controller 401 selects the row 404 with the minimum number of entries that also has a needed block 402 on it, or for which a minimum number of blocks 402 need to be powered on. If there is no row 404 with an empty entry, the controller 401 powers on the row 404. Similarly, if the row 404 does not have a powered-on block 402 required for the entry, the controller 401 powers on at least one block 402.In step 706, the controller 401 places the command status memory entry in the identified slot.

[0041] When all high latency data for an instruction is in the instruction status memory 310, the instruction status memory 310 sends the instruction to the functional units. Furthermore, if the instruction was the last instruction in the row 404 or the last instruction in the row 404 that uses a particular block 402, the controller 401 powers down the row 404 or the block 402. The power down may occur after a delay as described elsewhere herein. Also, if during the delay a new instruction comes in that requires the row 404 or the block 402, the power down is not performed. Furthermore, in some embodiments, when information about an instruction is sent to the functional units for execution, only the blocks 402 that are actually powered on for the instruction are read, so no power is consumed to read from unpowered blocks.

[0042] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element may be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0043] The various functional units illustrated in the figures and / or described herein (including, but not limited to, the processor 102, the input driver 112, the input device 108, the output driver 114, the output device 110, the accelerated processing device 116, the scheduler 136, the graphics processing pipeline 134, the computation unit 132, the SIMD unit 138, the instruction dispatch unit 300, the instruction fetch unit 302, the decode unit 304, the low latency data unit 306, the high latency data unit 308, the instruction status memory 310, or the controller 401) may be implemented as a general purpose computer, processor, or processor core, or as a program, software, or firmware stored on a non-transitory computer-readable storage medium or another medium executable by the general purpose computer, processor, or processor core. The methods provided may be implemented in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, general purpose processors, special purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors in conjunction with a DSP core, controllers, microcontrollers, application specific integrated circuits (ASICs), field programmable gate array (FPGA) circuits, other types of integrated circuits (ICs), and / or state machines. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data (instructions that may be stored on a computer readable medium), including a netlist. The results of such processing may be a mask work, which is used in a semiconductor manufacturing process to manufacture a processor implementing the disclosed features.

[0044] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method for processing computer instructions, comprising: Obtaining information in an instruction status memory entry relating to an instruction; identifying a slot in an instruction state memory having a selectably powered row and block for said instruction state memory entry based on a clustering criterion; placing the instruction status memory entry in the identified slot. method.

2. the information in the instruction status memory entry includes one or more operations related to the instruction; 2. The method of claim 1.

3. and upon receiving the high latency data of the instruction status memory entry, transmitting the data in the instruction status memory entry and the high latency data to one or more functional units for execution; the high latency data having a higher access latency than the low latency data stored in the instruction state memory entry.

2. The method of claim 1.

4. determining that after transmitting the data in the instruction status memory entry to the one or more functional units for execution, there are no occupied slots in the row to which the data was transmitted; powering down the row. The method of claim 3.

5. The power down occurs after a waiting period. The method of claim 4.

6. Identifying slots in the instruction state memory based on the clustering criteria includes: identifying a row in said instruction status memory having a minimum non-zero number of free slots; identifying a free slot in the identified row as a slot for said instruction status memory entry; 2. The method of claim 1.

7. the instruction state memory entry includes an item of a first type of data; in the instruction state memory, a first powered-on row includes a first block of data of the first type, the first block being powered on, and a second powered-on row includes a second block of data of the first type, the second block being powered off; identifying the slot includes identifying a slot in the first powered-on row.

2. The method of claim 1.

8. the second powered-on row includes more free slots than the first powered-on row. The method of claim 7.

9. Identifying the slot comprises: determining that a powered on row has no free slots; powering on the powered off rows.

2. The method of claim 1.

10. an instruction state memory, a plurality of selectably powered rows, each row having a plurality of selectably powered blocks; A controller, The controller: Obtaining information in an instruction status memory entry relating to an instruction; identifying a slot in an instruction state memory having a selectably powered row and block for said instruction state memory entry based on a clustering criterion; placing said instruction status memory entry in the identified slot; 4. The method of claim 3, Instruction state memory.

11. the information in the instruction status memory entry includes one or more operations related to the instruction; The instruction state memory of claim 10.

12. The controller: configured, upon receiving the high latency data of the instruction status memory entry, to transmit the data in the instruction status memory entry and the high latency data to one or more functional units for execution; the high latency data having a higher access latency than the low latency data stored in the instruction state memory entry. The instruction state memory of claim 10.

13. The controller: determining that after transmitting the data in the instruction status memory entry to the one or more functional units for execution, there are no occupied slots in the row to which the data was transmitted; powering down said row; 4. The method of claim 3, 13. The instruction state memory of claim 12.

14. The power down occurs after a waiting period.

14. The instruction state memory of claim 13.

15. Identifying slots in the instruction state memory based on the clustering criteria includes: identifying a row in said instruction status memory having a minimum non-zero number of free slots; identifying a free slot in the identified row as a slot for said instruction status memory entry; The instruction state memory of claim 10.

16. the instruction state memory entry includes an item of a first type of data; in the instruction state memory, a first powered-on row includes a first block of data of the first type, the first block being powered on, and a second powered-on row includes a second block of data of the first type, the second block being powered off; identifying the slot includes identifying a slot in the first powered-on row. The instruction state memory of claim 10.

17. the second powered-on row includes more free slots than the first powered-on row.

17. The instruction state memory of claim 16.

18. Identifying the slot comprises: determining that a powered on row has no free slots; powering on the powered off rows. The instruction state memory of claim 10.

19. an instruction state memory; A functional unit; A processor comprising: The instruction state memory includes: a plurality of selectably powered rows, each row having a plurality of selectably powered blocks; A controller, The controller: Obtaining information in an instruction status memory entry relating to an instruction; identifying a slot in an instruction state memory having a selectably powered row and block for said instruction state memory entry based on a clustering criterion; placing said instruction status memory entry in the identified slot; The device is configured to: The functional unit comprises: configured to execute the instructions; Processor.

20. The controller: configured, after receiving the high latency data of the instruction status memory entry, to transmit the data in the instruction status memory entry and the high latency data to the functional unit for execution; the high latency data having a higher access latency than the low latency data stored in the instruction state memory entry.

20. The processor of claim 19.

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