Grip posture prediction

Abstract

To provide a device, system, and technique for generating and selecting gripping proposals.SOLUTION: In at least one exemplary embodiment, a gripping proposal is generated and selected using one or more neural networks on the basis of, for example, a latent code corresponding to an object.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 411,486, entitled "GRASP POSE PREDICTION," filed September 29, 2022, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] This relates to a grasping proposal for a bot to grasp an object. Summary of the Invention [Means for solving the problem]

[0003] At least one embodiment relates to generating a grasping proposal for a robot to grasp an object, for example, by various novel techniques described herein.

[0004] Generating a grasping proposal for a robot to grasp an object is an important task in a variety of contexts. Generating a grasping proposal can involve the use of significant computing resources, especially for complex objects. The amount of memory, time, or computing resources used to generate a grasping proposal can be improved. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is an illustration of an example system for generating a grasping proposal, according to at least one embodiment. [Figure 2] FIG. 1 is an illustration of an example robot and object, according to at least one embodiment. [Figure 3] FIG. 1 is an illustration of an example of an overview of a robotic object manipulation system, according to at least one embodiment. [Figure 4]10A-10C are diagrams of examples of generating a grasp pose, according to at least one embodiment. [Figure 5] 1 is an illustration of an example process for generating a grasping proposal, according to at least one embodiment. [Figure 6] FIG. 1 is a diagram of an example processor, according to at least one embodiment. [Figure 7A] FIG. 1 illustrates logic according to at least one embodiment. [Figure 7B] FIG. 1 illustrates logic according to at least one embodiment. [Figure 8] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 9] FIG. 1 illustrates an example data center system, according to at least one embodiment. [Figure 10A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 10B] FIG. 10B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 10C] FIG. 10B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 10D] FIG. 10B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 10A, according to at least one embodiment. [Figure 11] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 12] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 13] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 14] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15B]FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 15E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 15F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 16] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 17A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 17B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 18A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 18B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 19] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 20A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 20B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 20C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 20D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 21]FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 22] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 23] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 24] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 25] FIG. 1 is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment. [Figure 26] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 27] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 28] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 29] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment. [Figure 30] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 31A] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 31B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 32] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 33]FIG. 1 illustrates a general processing cluster (“GPC”), according to at least one embodiment. [Figure 34] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 35] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. [Figure 36] FIG. 1 is an example data flow diagram for an advanced computing pipeline, according to at least one embodiment. [Figure 37] FIG. 1 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment. [Figure 38] A diagram including an example of an advanced computing pipeline 3710A for processing imaging data, according to at least one embodiment. [Figure 39A] FIG. 10 includes an example data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment. [Figure 39B] FIG. 10 includes an example data flow diagram of a virtual instrument supporting a CT scanner, according to at least one embodiment. [Figure 40A] FIG. 1 is a data flow diagram of a process for training a machine learning model, according to at least one embodiment. [Figure 40B] FIG. 1 illustrates an example client-server architecture for extending annotation tools with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] In one embodiment, the system utilizes representations for object rendering, 3D reconstruction, and grasp pose prediction that can be inferred from a single image. The system can utilize diverse neural radiance fields (NeRFs) and can utilize category-level priors and fine-tuning for novel objects with minimal data and time. The system can utilize compact shape representations from which additional information, such as grasp poses, can be extracted. The system can directly retrieve grasp poses from NeRF-based representations using a single viewpoint (e.g., RGB only). The system can utilize representations that can be applied to a variety of tasks, such as object reconstruction and regressing grasp poses from a single RGB observation.

[0007] In one embodiment, a system, also referred to as a Neural Field System for Robotic Object Manipulation (NiFR), when used in conjunction with one or more other systems, such as a robotic system, takes as input a single image with basic object annotations (e.g., object pose and volume) and computes a latent code for an object that can be used to recompile the scene (e.g., render a view obscured from the object) and retrieve a grasp pose for that object. In one embodiment, NeRF is a neural network parameterized function that maps coordinates and direction vectors in Euclidean space to two scalar quantities, color and density. NeRF can be queried by coordinates along a ray to render an image of the scene from any viewpoint. The system can represent a scene by assigning each object a latent code, which can be computed through various optimization processes, such as those described herein. The system can generate grasps directly from the object latent codes.

[0008] The system can utilize a representation that can be used to re-render the scene and generate grasp poses. In one embodiment, given object poses, volumes, and learned latent codes, the system renders the scene in a novel configuration and annotates each object with a grasp pose. To generate grasps, the system can utilize a grid sampling technique that covers each object volume. The system can predict grasp orientations and scores using a decoder. The system can utilize the grasp point that results in the highest confidence score.

[0009] FIG. 1 illustrates an example system 100 for generating grasping proposals, according to at least one embodiment. The system may be in accordance with systems described herein. The system may include an inverse renderer 104 and a grasping decoder 110, which may utilize a luminance field decoder, as well as various other components that may not be illustrated in FIG. 1. The system may process input images 102 to generate grasping proposals 112. The system may select a grasping proposal from the grasping proposals 112 and utilize the grasping proposal in connection with various processes.

[0010] In at least one embodiment, the system is a collection of hardware and / or software computing resources with instructions that, when executed, cause one or more processes, such as those described in connection with FIGS. 1-6 to be performed. In at least one embodiment, the system is part of any suitable system and / or collection of systems, such as systems related to robotics systems, computer vision systems, and / or variations thereof. In at least one embodiment, the system is a software program, application, or module that can be executed on computer hardware. In one embodiment, the system performs one or more processes, such as those described herein, by at least causing the instructions to be executed by one or more system and / or processing units.

[0011] In at least one embodiment, one or more processes of the system are executed by any suitable system and / or collection of systems, such as systems of one or more programming models, such as the Compute Unified Device Architecture (CUDA) model, the Heterogeneous Compute Interface for Portability (HIP) model, the oneAPI model, various hardware accelerator programming models, and / or variations thereof. In at least one embodiment, one or more processes of the system are executed in connection with any suitable machine learning and / or neural network framework, such as TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, and / or variations thereof. In at least one embodiment, one or more processes of the system are executed using any suitable processing unit and / or combination of processing units, such as one or more central processing units (CPUs), parallel processing units (PPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), and / or any suitable processing units. In at least one embodiment, the system is implemented in association with a processor and / or multiple processors such as those described in connection with Figure 6. In some instances, the system is implemented in association with one or more circuits for performing one or more processes of the system.

[0012] The system may obtain an input image 102. The input image 102 may be obtained from any suitable system and / or collection of systems, such as a computer vision system, a robotic system, an image and / or video capture system, and / or variations thereof. The input image 102 may be a frame of video. The input image 102 may be a synthetically generated image. The input image 102 may be implemented in association with any suitable file format or representation. The input image 102 may depict one or more objects in an environment, also referred to as a scene. In some instances, the system is associated with a robot, where the system obtains the input image 102 from an image and / or video capture system associated with a scene that may include the robot and / or one or more objects. The robot may include robotic components, such as a gripper, that may be utilized to grasp one or more objects. The system processes the input image 102 in association with an inverse renderer 104 to compute an object latent code 106.

[0013] The inverse renderer 104 may be a component of a system that may be utilized to compute or generate one or more latent codes. In one embodiment, the inverse renderer 104 is a software program, application, system, or module that is part of or otherwise associated with the system. One or more processes of the inverse renderer 104, such as those described herein, may be executed by the system in any suitable manner and in association with any suitable processing unit. In some instances, the inverse renderer 104 may be implemented as a set of instructions and is a set of processes that may be executed or otherwise utilized by the system. The inverse renderer 104 may process the input image 102 to generate the object latent code 106. The inverse renderer 104 may utilize a luminance field decoder, which may be any suitable machine learning model component that may be utilized to generate an image. The luminance field decoder may be implemented in any suitable manner, such as through one or more data structures that encode the structure, configuration, and / or other information of the luminance field decoder. In one embodiment, the luminance field decoder is a software program, application, system, or module that is part of or otherwise associated with the system. The luminance field decoder may utilize object latent codes. An object latent code as described herein may be a set of values, such as one or more vectors, or any suitable representation of one or more values ​​that may correspond to or otherwise indicate an object depicted in an image. The luminance field decoder may itself be utilized to generate one or more object latent codes. In one embodiment, the luminance field decoder is used in an inverse rendering process (e.g., by the inverse renderer 104) to generate one or more object latent codes.

[0014] The luminance field decoder, also referred to as a neural luminance field decoder, can obtain the object latent code from one or more systems capable of generating the object latent code. The inverse renderer 104 can generate the object latent code. The object latent code may be generated randomly, based on other object latent codes, based on previously processed object latent codes, and / or variations thereof. The luminance field decoder can process at least the object latent code, one or more coordinates (e.g., corresponding to an object and / or location in the scene), and a view direction, and can output one or more predictions of density and / or color at one or more coordinates relative to the view direction. Coordinates or coordinate values ​​as described herein may refer to any suitable one or more coordinate values, such as three-dimensional (3D) coordinate values, two-dimensional (2D) coordinate values, and / or variations thereof, which may be referenced to any suitable 3D or 2D coordinates or a reference plane of the image and / or scene.

[0015] The inverse renderer 104 may use one or more predictions of density and / or color to generate the image. As an illustrative example, the inverse renderer 104 generates pixels for the image based at least in part on one or more predictions of density and / or color and any suitable rendering equations and / or formulas, such as volumetric rendering equations. The inverse renderer 104 may compare the image to the input image 102 via one or more functions to update the object latent code. The inverse renderer 104 may compare the image to the input image 102 to calculate the difference between the image and the input image 102 and may update the object latent code based at least in part on the difference via one or more processes as described herein. The difference may be calculated via one or more functions as described herein. The inverse renderer 104 may process the object latent codes with or otherwise use a luminance field decoder to generate images, and may update the object latent codes based, at least in part, on the images generated over any suitable number of iterations, which may be a predetermined number, and the input images 102, or based on any suitable function or metrics.

[0016] The inverse renderer 104, in conjunction with the luminance field decoder, can calculate or otherwise determine the object latent codes 106. The object latent codes 106 may be the object latent codes described herein that have been updated through one or more processes in conjunction with the luminance field decoder and / or the inverse renderer 104. The object latent codes 106 may correspond to particular objects depicted in the input image 102, or may represent or otherwise indicate such objects. In one embodiment, the system calculates each of the M objects in the scene S as a tuple o=(P o ,V o ,f o ) is used to express the o is the 6D object pose, and V o is the 3D object bounding volume, and f ois the learned object latent code (e.g., object latent code 106). In one embodiment, f o encodes the object's shape, appearance, and gripping pose, and V o is a simple volume, such as a sphere or oriented box, that supports fast ray-volume intersection checking. Objects can form a flat scene graph using a single world node, which allows direct control over individual object poses to support visualization and reasoning about the scene during object repositioning, and can be used in conjunction with a variety of computer vision systems for a variety of object detection and tracking tasks.

[0017] The system can input the object latent code 106 into a neural network-based decoder to perform various tasks, such as volumetric rendering and predicting 6DOF grasps for robotic manipulation. For volumetric rendering, the system can utilize a neural intensity field decoder, which can be denoted as Ψ. To predict grasps, the system can utilize a grasp decoder 110, which can be denoted as Φ. The two decoders can share parameters from their first two layers. The system can then predict a potential object o=(P o ,V o ,f o ) can be utilized to predict stable grasps. The grasp prediction process can include a grasp proposal step and a filtering step. In one embodiment, the grasp proposal step is performed in conjunction with a neural network Φ (e.g., the grasp decoder 110) that processes the scene representation directly, and the filtering step is performed in conjunction with the output of the luminance field decoder Ψ.

[0018] The grasp decoder 110 can be any suitable machine learning model component capable of generating a grasp proposal. The grasp decoder 110 may be implemented in any suitable manner, such as through one or more data structures that encode the structure, configuration, and / or other information of the grasp decoder 110. In one embodiment, the grasp decoder 110 is a software program, application, system, or module that is part of or otherwise associated with a system. The grasp decoder 110 can generate a grasp proposal. A grasp proposal as described herein can refer to data that indicates a particular grasp configuration or orientation of a robotic part, such as a gripper, where the robotic part can be configured or oriented (e.g., by one or more systems associated with the robotic part) according to the particular grasp configuration or orientation to grasp an object. A grasping proposal may indicate or be otherwise associated with a value, also referred to as a grasp score, that indicates the probability that a particular grasp configuration or orientation indicated by the grasp proposal, when utilized in conjunction with a robotic part that grasps the object, will result in a successful or stable grasp of the object. A grasping proposal may indicate or be otherwise associated with one or more coordinate values ​​(e.g., corresponding to the location of the object). A grasping proposal may be implemented in association with any suitable data, data structures, and / or variations thereof.

[0019] The system can generate coordinates 108, which can be data indicating one or more coordinate values ​​corresponding to one or more locations of a particular object depicted in the input image 102. The one or more locations can be any suitable locations on or near the particular object that can be utilized to grasp the particular object (e.g., by a robotic component). In one embodiment, the system receives as input to a grasp decoder 110Φ the 3D coordinates

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[0020] The system can have or otherwise use the grasping decoder 110 to process at least the object latent code 106 and the coordinates 108 to generate a grasping proposal 112. The system can have or otherwise use the grasping decoder 110 to process 6D object poses and / or 3D object bounding volumes corresponding to the objects in the input images 102. The system can obtain or otherwise generate the 6D object poses and / or 3D object bounding volumes in connection with one or more computer vision systems, functions, algorithms, and / or any suitable systems, functions, and / or algorithms. The grasping proposal 112 can be a collection of one or more grasping proposals. The grasping proposal 112 can include one or more grasping proposals, each corresponding to a respective coordinate value in the coordinates 108.

[0021] A grasping proposal can be any suitable data that indicates or otherwise represents a particular grasping configuration or orientation and / or probability value. A grasping proposal is represented by at least a grasping score S g and / or rotation matrix R g As an illustrative example, a grasping proposal corresponding to particular coordinate values ​​(e.g., of an object) may be represented or otherwise implemented via a rotation matrix R (e.g., which may be implemented or otherwise represented via any suitable data and / or data structure). g a grasp score S (which may be implemented or otherwise represented through any suitable data and / or data structure, for example) when utilized in association with a robot part at a particular grasp configuration or orientation and an object location indicated by particular coordinate values; g , .times. ...

[0022] To predict a grasp on an object o, the system uses a set of coordinates

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[0023] The system may perform one or more filtering processes, as described herein, in connection with the grasping proposals 112. The system may determine one or more of the grasping proposals 112 that include a certain number of the highest or maximum scoring grasping proposals (e.g., as indicated by a grasp score), which may be any suitable value, and may delete or otherwise remove the remaining grasping proposals from the grasping proposals 112. The system may calculate those of the grasping proposals 112 that have a grasp score above a certain threshold, which may be any suitable value, and may delete or otherwise remove other grasping proposals from the grasping proposals 112. The system may calculate those of the grasping proposals 112 that, when utilized in connection with a robot part, result in a grasp in which an open grasp configuration does not collide with an object but a closed grasp configuration does collide with an object, and may delete or otherwise remove other grasping proposals from the grasping proposals 112.

[0024] The system may generate a representation of the robot part, such as a point cloud, or other suitable representation. For each grasp proposal in grasp proposals 112, the system may deform (e.g., by configuring or orienting) the representation to conform to a particular grasp configuration or orientation indicated by the grasp proposal. The system may then input at least one or more 3D coordinates into a brightness field decoder corresponding to the representation deformed to the open and / or closed grasp configuration to calculate whether the grasp proposal would not result in a collision with an object when utilized in connection with a robot part in an open grasp configuration and / or whether the grasp proposal would result in a collision with an object when utilized in connection with a robot part in a closed grasp configuration. If either or both conditions are not met (e.g., the grasping proposal results in a collision with an object when utilized in association with a robot part in an open grasping configuration and / or the grasping proposal does not result in a collision with an object when utilized in association with a robot part in a closed grasping configuration), the system may not utilize the grasping proposal and may remove or otherwise delete the grasping proposal from grasping proposals 112. The one or more 3D coordinates may correspond to locations or points on the deformed representation, which may be referenced to any suitable coordinate plane. An open grasping configuration may refer to a configuration of a robot part in which the robot part is capable of grasping an object (e.g., if the robot part is a gripper, an open grasping configuration may be the gripper open). A closed grasping configuration may refer to a configuration of a robot part in which the robot part is capable of grasping an object (e.g., if the robot part is a gripper, a closed grasping configuration may be the gripper closed to grasp an object).

[0025] As an illustrative example, the system configures or otherwise orients a representation of a robot part according to a particular grasp proposal. Continuing the example, the particular grasp proposal, when utilized in association with a robot part in an open grasp configuration, results in no collision with an object at one or more 3D coordinates of the configured or otherwise oriented representation in the open grasp configuration, and when processed in association with a luminance field decoder, yields one or more predicted density values ​​below a particular threshold, which may be any suitable value, that may indicate a possible absence of a collision with an object at the one or more 3D coordinates. Continuing the example, the particular grasp proposal, when utilized in association with a robot part in a closed grasp configuration, results in a collision with an object at one or more 3D coordinates of the configured or otherwise oriented representation in the closed grasp configuration, and when processed in association with a luminance field decoder, yields one or more predicted density values ​​above a particular threshold, which may be any suitable value, that may indicate a possible collision with an object at the one or more 3D coordinates.

[0026] The system can provide the grasping proposals 112 to one or more systems associated with the robot. The system can utilize the grasping proposals 112 in association with the robot and robot parts (e.g., grippers). The system can provide one or more grasping proposals from the grasping proposals 112 to one or more systems associated with the robot so that the robot can utilize the one or more grasping proposals in association with the robot parts to grasp an object. In some instances, the system selects a grasping proposal from the grasping proposals 112 (e.g., the grasping proposal with the highest grasp score) and causes the robot part to grasp the object using the grasping proposal. More information regarding robots and grasping proposals can be found in the description of FIG. 2.

[0027] One or more components of the system (e.g., the luminance field decoder and / or the grasping decoder 110) may be trained in connection with any suitable system or framework, such as a system or framework related to TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, and / or variations thereof. In one embodiment, one or more components of the system (e.g., the luminance field decoder and / or the grasping decoder 110) may be trained in connection with N scenes It may be trained in association with a dataset D of scenes, and this N scenes In Scenes, each scene consists of a ground truth scene graph (e.g., with object volumes V and poses P), N objects rendered from random camera poses, and views Ground truth images, as well as the grip position p g , orientation

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[0028] One or more systems can jointly optimize the NeRF reconstruction and the grasping loss. In one embodiment, the reconstruction loss L rgbis the pixel-wise mean squared error between the reconstructed image and the ground truth image. In one embodiment, the grasping loss is calculated as two terms: the grasping score loss L gscore and rotation loss L grot In this case, the predicted grasp score and rotation S g , R g =Φ(p g ,f o ), the grasping score loss is

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[0029] In one embodiment, given a universal decoder (e.g., the luminance field decoder and / or the grasp decoder 110) trained through one or more processes as described herein, when the system encounters a previously unseen object, it can compute a new latent code to represent the object. In one embodiment, the system can initialize a random latent code f and optimize it using gradient descent while keeping the decoders Φ and Ψ frozen. The system does not need to assume any grasp annotations during testing. The system calculates the image reconstruction loss L for a single image (e.g., the input image 102). rgb By at least optimizing

[0030] FIG. 2 illustrates an example robot and object 200, according to at least one embodiment. The robot 202, object 204, input image 206, robotic object manipulation system 208, and grasping proposal 210 may be in accordance with the respective descriptions provided in connection with FIG. 1 . The robot 202 and object 204 may be present in a scene. The scene may be any suitable environment, such as a real-world environment, a simulated environment, and / or variations thereof. The robot 202 may include any suitable robotic component, such as a gripper, that may be utilized to grasp one or more objects. As an illustrative example, referring to FIG. 2 , the robot 202 includes a robotic component that is a gripper that may be utilized to grasp the object 204. The object 204 may be any suitable object of any suitable structure having a variety of physical properties. As an illustrative example, referring to FIG. 2 , the object 204 is a bottle-like object.

[0031] Robotic object manipulation system 208, also referred to as a neural field system for robotic object manipulation, may be the system described in connection with FIG. 1. Robotic object manipulation system 208 may be part of robot 202 or may be otherwise associated with robot 202. In at least one embodiment, robotic object manipulation system 208 is a software program, application, or module that can be executed on computer hardware. Robotic object manipulation system 208 may be any suitable collection of hardware and / or software that can be utilized to process input image 206 through various processes as described herein to generate grasp proposal 210.

[0032] The robotic object manipulation system 208 can obtain an input image 206. The input image 206 can be obtained from any suitable system and / or collection of systems, such as a computer vision system, a robotic system, an image and / or video capture system, and / or variations thereof, which can be associated with the robot 202, the scene, and / or the robotic object manipulation system 208. The input image 206 can be a frame of video. The computer vision system, the robotic system, the image and / or video capture system, and / or variations thereof can process the scene to generate or otherwise capture the input image 206. The input image 206 can depict the robot 202 and / or the object 204 at a particular time.

[0033] A robotic object manipulation system 208 can process the input image 206 to generate a grasping proposal 210. The robotic object manipulation system 208 can include, or be otherwise implemented with, a brightness field decoder, such as described in connection with FIG. 1, which can be utilized to calculate a latent code corresponding to the object 204. The robotic object manipulation system 208 can include, or be otherwise implemented with a grasping decoder, such as described in connection with FIG. 1, which can be utilized to process the latent code and generate the grasping proposal 210. More information regarding the generation of the grasping proposal can be found in the description of FIG. 1.

[0034] Robotic object manipulation system 208 can perform one or more filtering processes, as described herein, in connection with grasping proposal 210. Robotic object manipulation system 208 can calculate grasping proposals from grasping proposal 210 that, when used in connection with robotic components of robot 202, result in a grasp that does not collide with object 204 in an open grasping configuration but does collide with object 204 in a closed grasping configuration, and can delete or otherwise filter out other grasping proposals from grasping proposal 210. Robotic object manipulation system 208 can delete or otherwise filter out grasping proposals from grasping proposal 210 that, when used in connection with robotic components of robot 202 in an open grasping configuration, result in a grasp that does not result in a collision with object 204. Further information regarding filtering of grasping proposals can be found in the description of FIG.

[0035] Robotic object manipulation system 208 can provide grasping proposal 210 to robot 202 and / or one or more systems associated with robot 202. Robot 202 and / or one or more systems associated with robot 202 can use the grasping proposal in grasping proposal 210 to cause a robot component to grasp object 204. In some instances, robotic object manipulation system 208 uses the grasping proposal to cause a robot component to grasp object 204. The grasping proposal may be the grasping proposal associated with the highest grasping score among the grasping scores of grasping proposals 210. The grasping proposal may be randomly selected from grasping proposals 210. The grasping proposal may be any suitable grasping proposal among the remaining grasping proposals among grasping proposals 210. The robotic parts can grasp the object 204 using the grasp proposals by at least utilizing the particular grasp configurations or orientations indicated by the grasp proposals to grasp the object 204. As an illustrative example, the robotic parts can be configured or otherwise oriented according to the particular grasp configurations or orientations indicated by the grasp proposals to grasp the object 204. In some examples, the robotic parts of the robot 202 can attempt or otherwise perform one or more grasps of the object 204 using one or more grasp proposals of the grasp proposals 210, which can be any suitable grasp proposal of the grasp proposals 210.

[0036] Figure 3 illustrates an example overview 300 of a robotic object manipulation system, according to at least one embodiment. The robotic object manipulation system can be in accordance with systems described herein, such as those described herein in connection with Figures 1 and 2, can include one or more components and / or processes as depicted in Figure 3, or can be otherwise implemented. The robotic object manipulation system can be utilized in connection with a robot such as those described herein. The robotic object manipulation system can take as input a single image with basic object annotations (e.g., object pose and volume) and can compute a latent code for the object that can be utilized to recompile the scene (e.g., render an unseen view of the object) and retrieve a grasp pose for that object.

[0037] A robotic object manipulation system can utilize the representation to re-render the scene and generate a grasp pose. As an illustrative example, referring to FIG. 3, given an object pose (e.g., depicted in the upper left), a volume (e.g., depicted in the upper left), and a learned latent code (e.g., depicted in the lower left), the robotic object manipulation system renders the scene in a novel configuration and annotates each object with a grasp pose (e.g., depicted on the right). Continuing the example, to generate grasps, the robotic object manipulation system can utilize a grid sampling technique that covers each object volume. Grasp orientations and scores can be predicted using a decoder that may be partially shared with the volumetric rendering process. The robotic object manipulation system can utilize the grasp point that yields the highest confidence score (e.g., grasp score). In one example, referring to FIG. 3, "FC" refers to a fully connected layer or any suitable neural network layer.

[0038] The robotic object manipulation system may be trained in conjunction with any suitable framework, such as the WISP framework, which may be built on PyTorch with suitable CUDA acceleration. The robotic object manipulation system may utilize various CUDA ray tracing accelerated processes. Training one or more components of the robotic object manipulation system may run in conjunction with any suitable processing unit for any suitable time, such as approximately 12 hours, using eight NVIDIA v100 GPUs. The robotic object manipulation system may be utilized in conjunction with any suitable processing unit and / or imaging hardware, such as an NVIDIA Titan Xp with a RealSense camera. In one embodiment, the learned object latent code is 32-dimensional, and the MLP decoder has two hidden layers of dimension 128 in a shared backbone and two additional layers in each of the decoding heads, although these values ​​may be any suitable values.

[0039] A robotic object manipulation system can be trained in association with a training dataset generated in association with one or more systems. The dataset can include images of diverse scenes of multiple objects within a class or category (e.g., shoes, or any suitable class / category of objects), positioned without self-intersections, and viewed from multiple angles. The training dataset can utilize 3D models from any suitable dataset. In one embodiment, one or more systems can utilize a ray-traced renderer such as NViSII, or any suitable renderer, to render pixel images at 800x800 or any suitable resolution with 2000 samples per pixel, or any suitable number of samples. As an illustrative example, for each shoe in the dataset, one or more systems render 400 random views sampled from a 360-view sphere at a fixed distance from the origin, although these values ​​can be any suitable values. Continuing the example, accompanying these renderings, one or more systems generate 32 scenes showing three to five shoes lying on a table, although these values ​​can be any suitable values. For each of these scenes, one or more systems can randomly select 400 or any suitable number of views from a hemisphere at a fixed distance from the scene's origin.

[0040] In one example, for each shoe in the dataset, one or more systems include grasp poses for a 6-8 cm wide gripper, or any suitable gripper, along with a quality score. The one or more systems can sample grasp positions uniformly across the training object point cloud using a collision-free, outside-in achievable technique. In one example, the grasp quality score S gTo identify ∈[0,1], for each grasp g, the one or more systems perform N attempts (e.g., N=50, or any suitable number) and calculate the number of successes in Pybullet or any suitable physics engine or simulator. In one embodiment, success is calculated by determining whether the grasp pose

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[0041] FIG. 4 illustrates an example 400 of generating a grasp pose, according to at least one embodiment. In one example, with reference to FIG. 4, "NiFR" may represent a robotic object manipulation system described herein, such as the system described in connection with FIGS. 1-3. The system can process images calibrated for the robot. The system can utilize object poses and dimensions from the images, which can be calculated using any suitable system or algorithm, such as CenterPose and / or variations thereof. To be able to reconstruct the object (e.g., a shoe), the system can utilize a masking algorithm, such as ViLD, and / or any suitable algorithm. The system can utilize the masked RGB image, object pose, and volume. The system can perform inverse rendering through one or more processes, such as those described herein, to optimize a suitable latent code for the object. In one example, the system can reconstruct the object in different poses to generate a valid 3D reconstruction and find a grasp pose (e.g., FIG. 4 depicts a Baxter gripper with reference to it, but any suitable gripper or robot part can be utilized).

[0042] The system can be utilized in conjunction with a variety of real-world robotic systems, such as those depicted in conjunction with Figure 4. The system o and Volume V o Any suitable system or algorithm, such as CenterPose and / or variations thereof, can be utilized to compute from a single RGB image. The system can compute instance segmentation masks for objects using an open-vocabulary object detector, such as ViLD, and / or any suitable system or algorithm to mask out rays that do not intersect with any objects. The system calculates a latent code f for each object o. oFine-tuning may be performed through one or more processes as described herein to optimize or otherwise compute σ to obtain a complete scene representation S. The system may utilize a variety of CUDA-accelerated processes. In one embodiment, as an illustrative example, in connection with a system, a Baxter robot may be able to successfully grasp multiple diverse objects from a single RGB image, such as sneakers (e.g., as depicted in connection with FIG. 4), heeled boots, and / or variations thereof, within two or fewer grasp attempts, although any suitable robot and / or robotic system may be utilized.

[0043] FIG. 5 illustrates an example process 500 for generating a grasping proposal, according to at least one embodiment. In at least one embodiment, some or all of process 500 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) collectively executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program including a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to perform process 500 are not stored using only transitory signals (e.g., propagating transitory electrical or electromagnetic transmissions). In at least one embodiment, non-transitory computer-readable media does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transitory signal.

[0044] In at least one embodiment, process 500 is performed by one or more systems such as those described in this disclosure. In at least one embodiment, process 500 is performed by a system such as those described in connection with FIGS. 1-4. In at least one embodiment, process 500 is performed by a system of one or more programming models (e.g., CUDA, HIP, oneAPI, and / or variations thereof). In at least one embodiment, one or more processes of process 500 are performed in any suitable order, including sequentially, in parallel, and / or variations thereof, by any suitable system such as those described herein, and using any suitable processing unit, such as a CPU, GPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, process 500 is performed by one or more systems such as those described in connection with FIGS. 7-40.

[0045] In at least one embodiment, a system that performs at least a portion of process 500 includes executable code for at least obtaining 502 an image depicting an object. The image may be referred to as an input image. The image may be obtained from any suitable system and / or collection of systems, such as a computer vision system, a robotic system, an image and / or video capture system, and / or variations thereof. The image may be obtained from one or more systems in or otherwise associated with a scene, which may refer to any suitable environment, such as a real-world environment or a simulated environment. The image may be a frame of a video. The image may depict an object in the scene. The object may be any suitable object that may be present in the scene and that may be grasped by a robot. The robot may include a robotic part, such as a gripper, that may be utilized by the robot to grasp the object in the scene. In some embodiments, the object in the image is a first category of object, in which the first neural network and the second neural network are trained with respect to images depicting at least objects of the first category.

[0046] In at least one embodiment, a system performing at least a portion of process 500 includes executable code for at least generating 504 a first set of images by at least using a first neural network to process latent codes corresponding to objects. The latent codes, also referred to as object latent codes, may be any suitable collection of values, such as one or more vectors, or any suitable representation of one or more values ​​that may correspond to, represent, or otherwise indicate objects depicted in the images. The first neural network may be a luminance field decoder, such as described in connection with FIGS. 1-2 and elsewhere in this disclosure. The system may generate the latent codes or obtain the latent codes from one or more systems. The latent codes may be generated randomly, based on other known latent codes, based on previously generated latent codes, and / or in any suitable manner.

[0047] The system can process at least the latent code using a first neural network to generate a first set of density and / or color predictions, and can generate a first image of the first set of images based on the first set of density and / or color predictions. The system can use the first neural network by at least processing the latent code using the first neural network and calculating an output of the first neural network, which output can be the first set of density and / or color predictions. Further information regarding generating images in conjunction with a luminance field decoder can be found in the description of FIG. 1. The system can utilize volumetric rendering equations to process the density and / or color predictions of the first set of density and / or color predictions to generate the first image.

[0048] In at least one embodiment, a system performing at least a portion of process 500 includes executable code for at least updating 506 the latent code based at least in part on the first set of images and the images. The system can compare the first image to the images via one or more functions to update the latent code. The system can compare the first image to the images to calculate a difference between the first image and the images, and update the latent code based at least in part on the difference via one or more processes as described herein. The difference can be calculated via one or more functions as described herein. In one embodiment, the system calculates the difference via at least an image reconstruction loss as described herein. The system can process the first image and the images via one or more image reconstruction loss functions, or any suitable loss function, to calculate the difference between the first image and the images. The difference can be calculated or otherwise expressed as one or more values ​​indicating the difference or level of difference between the first image and the images. The system can update the latent code to minimize the calculated difference via any suitable process as described herein. The system may update, determine, or otherwise compute the latent code through one or more gradient descent processes.

[0049] In some instances, the system may then utilize the updated latent code to generate a second image of the first set of images according to one or more processes described in connection with process 504, and then update the updated latent code based on the second image according to one or more processes described in connection with process 506. The system may continuously perform the process of generating images of the first set of images based on the latent code according to one or more processes described in connection with process 504 and / or the process of updating the latent code based on the images according to one or more processes described in connection with process 506 until the calculated difference between the generated image and the image falls below a defined threshold, up to a defined number of iterations, and / or based on any suitable function or metric.

[0050] In at least one embodiment, a system that performs at least a portion of process 500 includes executable code for at least employing 508 a second neural network to process at least the latent code to generate a set of grasp proposals. The second neural network may be a grasp decoder as described in connection with FIGS. 1-2 and elsewhere herein. The first neural network and the second neural network may utilize the same set of parameters (e.g., one or more layers of the first neural network include the same weights and / or other suitable parameters as one or more layers of the second neural network). The system may use the second neural network to process the latent code and one or more coordinates to generate a set of grasp proposals. The system may use the second neural network by at least processing the latent code using the second neural network and calculating an output of the second neural network, which may be a set of grasp proposals. The one or more coordinates may correspond to one or more specific locations on the object and may be referenced to any suitable coordinate plane or reference frame of the image and / or scene. A grasping proposal as described herein may refer to data indicative of a particular grasping configuration or orientation of a robotic part, which may be configured or oriented (e.g., by one or more systems associated with the robotic part) according to a particular grasping configuration or orientation for attempting to grasp or otherwise grasping an object. A grasping proposal may indicate or be otherwise associated with a value, also referred to as a grasp score, that indicates the probability that a particular grasping configuration or orientation indicated by the grasping proposal will result in a successful or stable grasp of the object when utilized in connection with a robotic part to grasp an object at a specific location that may also be indicated by or otherwise associated with the grasping proposal. A grasping proposal may be associated with at least a score (e.g.,

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[0051] In at least one embodiment, a system performing at least a portion of process 500 includes executable code for at least selecting 510 one or more grasping proposals from a set of grasping proposals based at least in part on a first neural network and a latent code. The system can use the first neural network and the latent code to perform one or more filtering processes, such as those described in connection with FIG. 1, to select or otherwise determine one or more grasping proposals, which may be referred to as a subset of grasping proposals. The system can determine a grasping proposal from the set of grasping proposals that includes a certain number of highest- or maximum-scoring grasping proposals (e.g., as indicated by a grasping score), which may be any suitable value, and can delete or otherwise remove the remaining grasping proposals from the set of grasping proposals. The system can calculate a grasping proposal from the set of grasping proposals that has a grasping score above a certain threshold, which may be any suitable value, and can delete or otherwise remove other grasping proposals from the set of grasping proposals. The system can use a first neural network to process the latent code and use various coordinates associated with the set of grasp proposals to select one or more grasp proposals. The system can use the first neural network and the latent code to calculate grasp proposals from the set of grasp proposals that, when utilized in connection with the robotic part, result in grasps in which open grasp configurations do not collide with the object but closed grasp configurations do collide with the object, and can delete or otherwise remove other grasp proposals from the set of grasp proposals.

[0052] The system can select one or more grasping proposals from the set of grasping proposals based at least in part on the first neural network and the latent code by performing at least various processes as described herein using the first neural network and the latent code. The system can generate a representation of the robot part, such as a point cloud, or other suitable representation. For each grasping proposal in the set of grasping proposals, the system can configure or otherwise orient the representation to conform to a particular grasping configuration or orientation indicated by the grasping proposal. The system can then input at least one or more 3D coordinates and the latent code into a first neural network, where the one or more 3D coordinates may correspond to a representation configured or otherwise oriented in an open and / or closed grasping configuration, to calculate whether the grasping proposal would not result in a collision with an object when utilized in association with the robot part in an open grasping configuration and / or whether the grasping proposal would result in a collision with an object when utilized in association with the robot part in a closed grasping configuration. If either or both conditions are not satisfied (e.g., the grasping proposal results in a collision with an object when utilized in association with a robot part in an open grasping configuration, and / or the grasping proposal does not result in a collision with an object when utilized in association with a robot part in a closed grasping configuration), the system may not utilize the grasping proposal and may remove or otherwise delete the grasping proposal from the set of grasping proposals. The one or more 3D coordinates may correspond to any suitable location or point on the representation, which may be referenced to any suitable coordinate plane.

[0053] As an illustrative example, the grasp proposal, when utilized in conjunction with a robot part in an open grasp configuration, results in one or more 3D coordinates of the configured or otherwise oriented representation in the open grasp configuration resulting in no collision with an object, and when processed in conjunction with the first neural network and latent code, results in one or more density values ​​(e.g., predicted by the first neural network or otherwise generated) below a particular threshold, which may be any suitable value, that may indicate no collision with an object at the one or more 3D coordinates. Continuing the example, the grasp proposal, when utilized in conjunction with a robot part in a closed grasp configuration, results in one or more 3D coordinates of the configured or otherwise oriented representation in the closed grasp configuration resulting in one or more density values ​​(e.g., predicted by the first neural network or otherwise generated) above a particular threshold, which may be any suitable value, that may indicate a collision with an object at the one or more 3D coordinates.

[0054] The system can select one or more grasping proposals to be the remaining grasping proposals from the set of grasping proposals. In some instances, the system performs one or more processes as described herein to calculate certain grasping proposals to remove from the set of grasping proposals, designates or otherwise classifies such certain grasping proposals for removal as erroneous grasping proposals, and selects one or more grasping proposals to include one or more grasping proposals from the set of grasping proposals that were not designated or otherwise classified as erroneous. The system can select one or more grasping proposals from the set of grasping proposals to be any suitable grasping proposals, which can be based on any suitable filtering process as described herein.

[0055] The system can provide one or more grasping proposals to one or more systems associated with the robot and / or robotic component. The system can utilize one or more grasping proposals in association with the robot and robotic component (e.g., gripper). The system can provide one or more grasping proposals to one or more systems associated with the robot such that the robot can utilize the one or more grasping proposals in association with the robotic component to grasp the object. The system can cause the robot and / or robotic component to grasp the object using the one or more grasping proposals. As an illustrative example, the system or other suitable system can cause the robot and / or robotic component to be configured or otherwise oriented according to one of the one or more grasping proposals, and then in this state the system or other suitable system can cause the robot and / or robotic component to grasp the object. Further information regarding robots and grasping proposals can be found in the description of FIG. 2.

[0056] The first neural network and / or the second neural network may be trained in connection with any suitable system or framework, such as, for example, a system or framework related to TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, and / or variations thereof. In one embodiment, the first neural network and / or the second neural network are trained in connection with N scenes may be trained in association with a dataset D of scenes, and N scenes In Scenes, each scene consists of a ground truth scene graph (e.g., with object volumes V and poses P), N objects rendered from random camera poses, and views Ground truth images, as well as the grip position p g , orientation

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[0057] In one embodiment, the system utilizes a representation for object rendering, 3D reconstruction, and grasp pose prediction that can be inferred from a single image, where the representation may be a latent code as described herein. The system can utilize a compact shape representation (e.g., a latent code) from which additional information, such as grasp poses, can be extracted in the form of grasp proposals. The system can directly retrieve grasp poses from a NeRF-based representation (e.g., a latent code) using a single viewpoint (e.g., an RGB-only image). The system can utilize the latent code in connection with a variety of tasks, such as object reconstruction and regressing grasp poses from a single RGB observation.

[0058] In one embodiment, the functionality of the system, the first neural network, and / or the second neural network can be accessed through one or more application programming interfaces (APIs) as described herein. Input to the APIs associated with the system, the first neural network, and / or the second neural network can include an image of an object, as described in connection with FIGS. 1-5. The input can also include authentication information associated with the entity calling or otherwise using the API. The API response can include a set of grasping proposals as described herein. When using the APIs, one or more systems can cause the system to process the image through one or more processes as described herein in connection with the first neural network and / or the second neural network to generate a set of grasping proposals. The system can also perform various filtering processes as described herein in connection with the set of grasping proposals, where the API response can include one or more grasping proposals determined at least in part based on the filtering process.

[0059] 6 illustrates an example processor 600, according to at least one embodiment. In at least one embodiment, the processor 602 performs one or more processes as described herein to generate one or more grasping proposals. In at least one embodiment, the processor 602 implements one or more processes of the system, luminance field decoder, and / or grasping decoder described in connection with FIGS. 1 and 2. In at least one embodiment, the processor 602 performs one or more processes as described in connection with FIGS. 1-5.

[0060] In at least one embodiment, processor 602 includes one or more processors such as those described in connection with FIGS. 20-35. In at least one embodiment, processor 602 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof. In at least one embodiment, processor 602 includes a system module 604, a luminance field decoder module 606, and a grasping decoder module 608. In at least one embodiment, system module 604, luminance field decoder module 606, and / or grasping decoder module 608 are part of processor 602 and / or one or more other processors. In at least one embodiment, system module 604, luminance field decoder module 606, and / or grasping decoder module 608 are distributed among multiple processors communicating over a bus, a network, by writing to a shared memory, and / or by any suitable communication process as described herein.

[0061] In at least one embodiment, when used in any implementation described herein, unless otherwise clear from the context or explicitly stated to the contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to implement the functionality described herein. In at least one embodiment, software can be embodied as a software package, code, and / or an instruction set or instructions, and "hardware," when used in any implementation described herein, can include, for example, single or any combination of hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by the programmable circuitry. In at least one embodiment, modules, collectively or individually, may be embodied as circuitry that forms part of a larger system, such as, for example, an integrated circuit (IC), a system on chip (SoC), etc. In at least one embodiment, a module executes one or more processes in association with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variations thereof.

[0062] In at least one embodiment, the system module 604 is a module that performs various processes in association with the luminance field decoder module 606 and / or the grasping decoder module 608. In at least one embodiment, the system module 604 performs one or more processes as described herein by at least including or otherwise encoding instructions that can be utilized to cause the execution of the one or more processes (e.g., by the processor 602) or otherwise perform such processes. The system module 604 can obtain images depicting an object and generate one or more grasping proposals in association with the luminance field decoder module 606 and / or the grasping decoder module 608. The system module 604 can perform one or more training processes as described herein in association with the luminance field decoder module 606 and / or the grasping decoder module 608. The system module 604 can perform one or more processes of the system described in association with FIGS. 1-2. The system module 604 can perform one or more processes as described in association with FIG. 6.

[0063] In at least one embodiment, the luminance field decoder module 606 is a module that performs various processes based at least in part on the latent code. In at least one embodiment, the luminance field decoder module 606 performs one or more processes as described herein by including or otherwise encoding at least instructions that can be utilized to cause the execution of the one or more processes (e.g., by the processor 602) or otherwise perform such processes. The luminance field decoder module 606 can obtain at least a latent code (e.g., corresponding to an object depicted in an image), one or more coordinates (e.g., corresponding to a location on the object), and a view direction, and can generate one or more predictions of density and / or color at the one or more coordinates relative to the view direction. The luminance field decoder module 606 can implement or otherwise perform the luminance field decoder process described in connection with FIG. 1 and elsewhere herein. The luminance field decoder module 606 performs one or more processes as described in connection with FIG. 6.

[0064] In at least one embodiment, the grasping decoder module 608 is a module that generates grasping proposals based at least in part on the latent code. In at least one embodiment, the grasping decoder module 608 performs one or more processes as described herein by including or otherwise encoding at least instructions that can be utilized to cause the execution of the one or more processes (e.g., by the processor 602) or otherwise perform such processes. The grasping decoder module 608 can obtain at least the latent code (e.g., corresponding to an object depicted in an image) and one or more coordinates (e.g., corresponding to a location on the object) and can generate one or more grasping proposals. The grasping decoder module 608 can implement or otherwise perform the grasping decoder process described in connection with FIG. 1 and elsewhere herein. The grasping decoder module 608 can perform one or more processes as described in connection with FIG. 6.

[0065] logic FIG. 7A illustrates logic 715, described in connection with elsewhere herein, that may be used in one or more devices to perform operations as discussed herein, according to at least one embodiment. In at least one embodiment, logic 715 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is inference and / or training logic. More details regarding logic 715 are provided below in conjunction with FIG. 7A and / or FIG. 7B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operations described herein, and logic may be embodied, collectively or individually, as circuitry that forms part of a larger system, such as an integrated circuit (IC), a system-on-chip (SoC), or one or more processors (e.g., CPU, GPU).

[0066] In at least one embodiment, logic 715 may include, without limitation, code and / or data storage 701 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used to infer in one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 701 for storing graph code or other software for timing and / or sequencing control, where the code and / or data storage 701 is loaded with weights and / or other parameter information to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 701 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache, or system memory.

[0067] In at least one embodiment, any portion of code and / or data storage 701 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 701 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or code and / or data storage 701 is internal or external to a processor, or whether it includes DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0068] In at least one embodiment, logic 715 may include, without limitation, code and / or data storage 705 for storing back and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in accordance with one or more embodiments. In at least one embodiment, code and / or data storage 705 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while backpropagating input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software for controlling the timing and / or order into which weights and / or other parameter information are loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0069] In at least one embodiment, code, such as graph code, loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 705 is internal or external to the processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or any combination of these factors.

[0070] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be combined storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0071] In at least one embodiment, logic 715 may include one or more arithmetic logic units (“ALUs”) 710, including, without limitation, integer and / or floating point units, for performing logical and / or arithmetic operations based at least in part on or indicated by training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 720, which are functions of input / output and / or weight parameter data stored in code and / or data storage 701 and / or code and / or data storage 705. In at least one embodiment, the activations stored in activation storage 720 are generated according to linear algebra and / or matrix-based calculations performed by ALU 710 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 705 and / or data storage 701 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 705, or code and / or data storage 701, or in another storage, on-chip or off-chip.

[0072] In at least one embodiment, ALU 710 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU 710 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 710 may be included within an execution unit of a processor, or may be included within an ALU bank that is otherwise accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 701, code and / or data storage 705, and activation storage 720 may share processors or other hardware logic devices or circuits, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same processor or other hardware logic devices or circuits and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 720 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0073] In at least one embodiment, activation storage 720 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 720 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 720 is internal or external to a processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other type of storage, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inference and / or training of neural networks, or any combination of these factors.

[0074] In at least one embodiment, the logic 715 illustrated in Figure 7A may be used in conjunction with an application-specific integrated circuit ("ASIC") such as a TensorFlow® Processing Unit by Google, an inference processing unit (IPU) by Graphcore™, or a Nervana® (e.g., "Lake Crest") processor by Intel Corp. In at least one embodiment, the logic 715 illustrated in Figure 7A may be used in conjunction with other hardware such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0075] FIG. 7B illustrates logic 715, according to at least one embodiment. In at least one embodiment, logic 715 is inference and / or training logic. In at least one embodiment, logic 715 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, logic 715 illustrated in FIG. 7B may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a TensorFlow® Processing Unit by Google, an Inference Processing Unit (IPU) by Graphcore™, or a Nervana® (e.g., "Lake Crest") processor by Intel Corp. In at least one embodiment, logic 715 illustrated in FIG. 7B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or a field-programmable gate array (FPGA). In at least one embodiment, logic 715 includes, without limitation, code and / or data storage 701 and code and / or data storage 705, which may be used to store code (e.g., graph code), weight and / or bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment illustrated in FIG. 7B , each of code and / or data storage 701 and code and / or data storage 705 is associated with dedicated computational resources, such as computation hardware 702 and computation hardware 706, respectively. In at least one embodiment, computation hardware 702 and computation hardware 706 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in code and / or data storage 701 and code and / or data storage 705, respectively, with the results stored in activation storage 720.

[0076] In at least one embodiment, each of code and / or data storage 701 and 705 and corresponding computational hardware 702 and 706 corresponds to a different layer of a neural network, such that activations resulting from one storage / computation pair 701 / 702, between code and / or data storage 701 and computational hardware 702, are provided as input to a storage / computation pair 705 / 706, between the next code and / or data storage 705 and computational hardware 706, to reflect the conceptual organization of the neural network. In at least one embodiment, each of storage / computation pairs 701 / 702 and 705 / 706 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in logic 715 after or in parallel with storage / computation pairs 701 / 702 and 705 / 706.

[0077] In at least one embodiment, one or more systems depicted in Figures 7A-7B are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figures 7A-7B are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figures 7A-7B are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0078] Neural network training and deployment FIG. 8 illustrates the training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 806 is trained using a training dataset 802. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and enables it to be trained using processing resources described herein to generate a trained neural network 808. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0079] In at least one embodiment, the untrained neural network 806 is trained using supervised learning, where the training dataset 802 includes inputs paired with desired outputs, or the training dataset 802 includes inputs with known outputs, and the outputs of the neural network 806 are manually scored. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner, processing inputs from the training dataset 802 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts the weights that control the untrained neural network 806. In at least one embodiment, the training framework 804 includes tools to monitor how well the untrained neural network 806 is converging toward a model, such as the trained neural network 808, that is suitable for generating correct answers, such as in the results 814, based on input data, such as the new dataset 812. In at least one embodiment, training framework 804 iteratively trains untrained neural network 806 while adjusting weights using a loss function and a tuning algorithm, such as stochastic gradient descent, to refine the output of untrained neural network 806. In at least one embodiment, training framework 804 trains untrained neural network 806 until untrained neural network 806 reaches a desired accuracy. In at least one embodiment, trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0080] In at least one embodiment, the untrained neural network 806 is trained using unsupervised learning, where the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the training dataset 802 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training dataset 802 and determine how individual inputs relate to the untrained dataset 802. In at least one embodiment, unsupervised training can be used within the trained neural network 808 to generate self-organizing maps, which can perform operations useful for reducing the dimensionality of the new dataset 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new dataset 812 that deviate from the normal patterns of the new dataset 812.

[0081] In at least one embodiment, semi-supervised learning may be used, which is a technique in which the training dataset 802 includes a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 804 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 808 to adapt to a new dataset 812 without forgetting knowledge instilled in the trained neural network 808 during initial training.

[0082] In at least one embodiment, training framework 804 is a framework operated in conjunction with a software development toolkit, such as the OpenVINO (Open Visual Inference and Neural network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit, such as a toolkit developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes or uses logic 715 to perform the operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0083] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for a variety of tasks and operations, such as human vision emulation, speech recognition, natural language processing, suggestion systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports a variety of software libraries, such as OpenCV, OpenCL, and / or variations thereof.

[0084] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, including classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., human and / or object), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or transformations thereof.

[0085] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of neural network models. In at least one embodiment, the model optimizer optimizes neural network models for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers of the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying inputs to the model (e.g., resizing inputs to the model), modifying the size of inputs to the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalizing, standardizing, quantizing (e.g., converting model weights from a first representation, such as a decimal point, to a second representation, such as an integer), and / or transforming thereof.

[0086] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or a library in any suitable programming language. In at least one embodiment, the inference engine is utilized to infer input data. In at least one embodiment, the inference engine implements various classes to infer the input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process the intermediate representation, set input and / or output formats, and / or execute the model on one or more devices.

[0087] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, for executing a first portion of code on a CPU and a second portion of the code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions for executing one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0088] In at least one embodiment, OpenVINO includes various functionality similar to functionality associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are executed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0089] In at least one embodiment, one or more systems depicted in Figure 8 are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figure 8 are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figure 8 are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0090] Data Center 9 illustrates an example data center 900 in which at least one embodiment may be used. In at least one embodiment, the data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0091] 9 , in at least one embodiment, data center infrastructure layer 910 may include a resource orchestrator 912, grouped computing resources 914, and node computing resources (“node CRs”) 916(1) through 916(N), where “N” represents a positive integer (although “N” may be a different integer than used in other figures). In at least one embodiment, node CRs 916(1) through 916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 918(1) through 918(N) (e.g., dynamic read-only memory, solid-state storage drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules. In at least one embodiment, one or more of the nodes CR from among the nodes CR 916(1)-916(N) may be a server having one or more of the computing resources mentioned above.

[0092] In at least one embodiment, the grouped computing resources 914 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various geographic locations (also not shown). In at least one embodiment, the separate groups of node CRs within the grouped computing resources 914 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0093] In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource orchestrator 712 may include hardware, software, or some combination thereof.

[0094] As shown in FIG. 9 , in at least one embodiment, framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, framework layer 920 may include frameworks to support software 932 in software layer 930 and / or one or more applications 942 in application layer 940. In at least one embodiment, software 932 or applications 942 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 920 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark® (hereinafter “Spark”), which can use distributed file system 928 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 922 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 900. In at least one embodiment, configuration manager 924 may be capable of configuring different tiers, such as software tier 930, as well as framework tier 920, which includes Spark and distributed file system 928 to support large-scale data processing. In at least one embodiment, resource manager 926 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 928 and job scheduler 922. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 914 in data center infrastructure tier 910.In at least one embodiment, resource manager 926 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 912.

[0095] In at least one embodiment, software 932 included in software layer 930 may include software used by nodes CR 916(1)-916(N), grouped computing resources 914, and / or at least a portion of distributed file system 928 of framework layer 920. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0096] In at least one embodiment, applications 942 included in application layer 940 may include one or more types of applications used by at least a portion of nodes CR 916(1)-916(N), grouped computing resources 914, and / or distributed file system 928 of framework layer 920. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and applications including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and machine learning applications, or other machine learning applications used in conjunction with one or more embodiments.

[0097] In at least one embodiment, any of configuration manager 924, resource manager 926, and resource orchestrator 912 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may prevent data center operators of data center 900 from making potentially poor configuration decisions and from potentially avoiding underutilized and / or poorly performing portions of the data center.

[0098] In at least one embodiment, data center 900 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 900. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 900 by using weight parameters calculated by one or more techniques described herein.

[0099] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0100] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in data center 900 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0101] In at least one embodiment, one or more systems depicted in Figure 9 are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figure 9 are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figure 9 are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0102] Autonomous Vehicles 10A illustrates an example of an autonomous vehicle 1000 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1000 (alternatively referred to herein as "vehicle 1000") may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, the vehicle 1000 may be a semi-tractor trailer truck used for hauling cargo. In at least one embodiment, the vehicle 1000 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0103] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In at least one embodiment, vehicle 1000 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1000 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0104] In at least one embodiment, vehicle 1000 may include components such as, without limitation, a chassis, a vehicle body, wheels (2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1000 may include a propulsion system 1050 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be coupled to a drive train of vehicle 1000, which may include, without limitation, a transmission to enable propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving a signal from a throttle / accelerator 1052.

[0105] In at least one embodiment, a steering system 1054, which may include without limitation a steering wheel, is used to steer the vehicle 1000 (e.g., along a desired path or route) when the propulsion system 1050 is operating (e.g., when the vehicle 1000 is moving). In at least one embodiment, the steering system 1054 may receive signals from a steering actuator 1056. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 1046 may be used to operate the vehicle brakes in response to receiving signals from a brake actuator 1048 and / or brake sensor.

[0106] In at least one embodiment, controller 1036, which may include, without limitation, one or more systems on a chip (“SoC”) (not shown in FIG. 10A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1000. For example, in at least one embodiment, controller 1036 may send signals to operate vehicle brakes via brake actuator 1048, to operate steering system 1054 via steering actuator 1056, and to operate propulsion system 1050 via throttle / accelerator 1052. In at least one embodiment, controller 1036 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1000. In at least one embodiment, controller 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or some combination thereof.

[0107] In at least one embodiment, controller 1036 provides signals to control one or more components and / or systems of vehicle 1000 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system ("GNSS") sensors 1058 (e.g., global positioning system sensors), RADAR sensors 1060, ultrasonic sensors 1062, LIDAR sensors 1064, inertial measurement units ("IMUs"). 10A ), a speed sensor 1044 (e.g., for measuring the speed of the vehicle 1000), a vibration sensor 1042, a steering sensor 1040, a brake sensor (e.g., as part of a brake sensor system 1046), and / or other types of sensors.

[0108] In at least one embodiment, one or more of the controllers 1036 may receive input (e.g., represented by input data) from the instrument cluster 1032 of the vehicle 1000 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., a high-definition map (not shown in FIG. 10A )), location data (e.g., the location of the vehicle 1000 on a map, etc.), direction, locations of other vehicles (e.g., occupancy grid), information about objects and object conditions sensed by the controller 1036, etc. For example, in at least one embodiment, the HMI display 1034 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver the vehicle has performed, is performing, or will perform (e.g., currently changing lanes, leaving exit 34B in 2 miles, etc.).

[0109] In at least one embodiment, vehicle 1000 further includes network interface 1024, which may use a wireless antenna 1026 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 1024 may be capable of communicating over a Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") network, etc. Additionally, in at least one embodiment, wireless antenna 1026 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area network protocols such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide-area network ("LPWAN") protocols such as LoRaWAN, SigFox, etc.

[0110] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in vehicle 1000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0111] 10B illustrates example camera locations and fields of view for the autonomous vehicle 1000 of FIG. 10A according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on the vehicle 1000.

[0112] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1000. In at least one embodiment, the camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor ("RGGB") color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0113] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0114] In at least one embodiment, one or more cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from within the vehicle 1000 (e.g., reflections reflected from the dashboard onto the windshield mirror) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate matches the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. In at least one embodiment, for side view cameras, the cameras may also be integrated into the four pillars at each corner of the cabin.

[0115] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of vehicle 1000 may be used for a surroundings view to facilitate identification of the forward path and obstacles, and may be used in conjunction with controller 1036 and / or one or more of the control SoCs to assist in providing information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many ADAS functions similar to LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0116] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1070 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While only one wide-angle camera 1070 is shown in FIG. 10B , in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1000. In at least one embodiment, any number of long-range cameras 1098 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 1098 may also be used for object detection and classification, as well as basic object tracking.

[0117] In at least one embodiment, any number of stereo cameras 1068 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 1068 may include an integrated control unit with a scalable processing unit, which may provide a programmable gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1000 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1068 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 1000 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1068 may be used in addition to or instead of those described herein.

[0118] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of the vehicle 1000 (e.g., side view cameras) may be used for the surroundings view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 1074 (e.g., four surrounding cameras as shown in FIG. 10B ) may be disposed on the vehicle 1000. In at least one embodiment, the surrounding cameras 1074 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or the like. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of the vehicle 1000. In at least one embodiment, the vehicle 1000 may use three surrounding cameras 1074 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0119] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1000 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras that are also suitable as front cameras as described herein (e.g., long-range camera 1098, and / or mid-range camera 1076, stereo camera 1068, infrared camera 1072, etc.).

[0120] FIG. 10C is a block diagram illustrating an example system architecture of the autonomous vehicle 1000 of FIG. 10A , according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1000 of FIG. 10C is illustrated as being connected via a bus 1002. In at least one embodiment, the bus 1002 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, the CAN may be a network internal to the vehicle 1000 used to help control various features and functions of the vehicle 1000, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1002 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1002 may be read to find steering angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1002 may be an ASIL B compliant CAN bus.

[0121] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1002, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or provide redundancy. For example, a first bus may be used for collision avoidance functions and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1002 may communicate with one of the components of vehicle 1000, and two or more of buses of bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1004 (e.g., SoC 1004(A) and SoC 1004(B)), each of the controllers 1036, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 1000) and may be connected to a common bus, such as a CAN bus.

[0122] In at least one embodiment, vehicle 1000 may include one or more controllers 1036, such as those described herein with respect to FIG. 10A . In at least one embodiment, controller 1036 may be used for a variety of functions. In at least one embodiment, controller 1036 may be coupled to any of a variety of other components and systems of vehicle 1000 and may be used to control vehicle 1000, artificial intelligence of vehicle 1000, infotainment and / or other functions of vehicle 1000.

[0123] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of SoCs 1004 may include, without limitation, a central processing unit ("CPU") 1006, a graphics processing unit ("GPU") 1008, a processor 1010, a cache 1012, an accelerator 1014, a data store 1016, and / or other components and features not shown. In at least one embodiment, SoCs 1004 may be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1004 may be incorporated into a system (e.g., the system of vehicle 1000) having a high definition ("HD") map 1022 that can obtain map refreshes and / or updates via a network interface 1024 from one or more servers (not shown in FIG. 10C ).

[0124] In at least one embodiment, CPU 1006 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 1006 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 1006 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1006 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). In at least one embodiment, CPU 1006 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 1006 to be active at any given time.

[0125] In at least one embodiment, one or more of the CPUs 1006 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPU 1006 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines what the best power state for cores, clusters, and CCPLEXes to enter is. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0126] In at least one embodiment, GPU 1008 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1008 may use an extended tensor instruction set. In at least one embodiment, GPU 1008 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1008 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1008 may use a compute application programming interface (API). In at least one embodiment, the GPU 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0127] In at least one embodiment, one or more of the GPUs 1008 may be power-optimized for best performance in automotive and embedded use cases. For example, in at least one embodiment, the GPUs 1008 may be fabricated on Fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a scheduler (e.g., warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0128] In at least one embodiment, one or more of the GPUs 1008 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, providing, in some instances, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or in place of the HBM memory.

[0129] In at least one embodiment, the GPU 1008 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU 1008 to directly access the page tables of the CPU 1006. In at least one embodiment, when the GPU 1008 memory management unit ("MMU") experiences a GPU miss, an address translation request may be sent to the CPU 1006. In at least one embodiment, in response, two of the CPUs 1006 may look up the virtual-to-physical address mapping in their own page tables and send the translation back to the GPU 1008. In at least one embodiment, the unified memory technology may enable a single, unified virtual address space for both the CPU 1006 and the GPU 1008 memory, thereby simplifying programming the GPU 1008 and porting applications to the GPU 1008.

[0130] In at least one embodiment, GPU 1008 may include any number of access counters that can record the frequency of GPU 1008's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0131] In at least one embodiment, one or more of the SoCs 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, the caches 1012 may include a level 3 (“L3”) cache available to both the CPU 1006 and the GPU 1008 (e.g., connected to the CPU 1006 and the GPU 1008). In at least one embodiment, the caches 1012 may include a write-back cache that can record line state by using a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may also be used.

[0132] In at least one embodiment, one or more of the SoCs 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1008 and offload some of the GPU 1008's tasks (e.g., freeing up more cycles for the GPU 1008 to perform other tasks). In at least one embodiment, the accelerators 1014 may be used for targeted workloads that are stable enough to accept acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNN may include a region-based, i.e., regional convolutional neural network (“RCNN”), and Faster RCNN (e.g., used for object detection), or other types of CNN.

[0133] In at least one embodiment, accelerator 1014 (e.g., a hardware-accelerated cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, the DLAs may include, without limitation, one or more tensor processing units (“TPUs”), which may be further configured to provide tens of trillions of operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized for performing image processing functions (e.g., CNN, RCNN, etc.). In at least one embodiment, the DLAs may be further optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the design of the DLAs allows for improved performance per millimeter over typical general-purpose GPUs, typically greatly exceeding the performance of a CPU. In at least one embodiment, the TPU may perform several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, the DLA may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, CNNs for object identification and detection using data from a camera sensor, CNNs for distance estimation using data from a camera sensor, CNNs for emergency vehicle detection and identification using data from a microphone, CNNs for face recognition and vehicle owner identification using data from a camera sensor, and / or CNNs for security and / or safety events.

[0134] In at least one embodiment, the DLA may perform any function of the GPU 1008, and a designer may target either the DLA or the GPU 1008 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 1008 and / or accelerator 1014.

[0135] In at least one embodiment, the accelerator 1014 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0136] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0137] In at least one embodiment, the DMA may allow components of the PVA to access system memory independently of the CPU 1006. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0138] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0139] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0140] In at least one embodiment, the accelerator 1014 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 1014. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM including eight field-configurable memory blocks, which may be accessible by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0141] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals, addresses, or data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals, addresses, and data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0142] In at least one embodiment, one or more of the SoCs 1004 may include a real-time ray tracing hardware accelerator that may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0143] In at least one embodiment, the accelerator 1014 can have a variety of uses for autonomous driving. In at least one embodiment, the PVA can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA performs well even with small data sets for semi-dense or dense regular computations that may require low-latency, low-power, and predictable runtimes. In at least one embodiment, the PVA can be designed to run classic computer vision algorithms, such as in the vehicle 1000, because they can be effective for object detection and integer arithmetic.

[0144] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some instances, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0145] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0146] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence measure may further enable the system to make decisions regarding which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system may set a threshold for confidence and consider only detections above the threshold to be true positive detections. In embodiments where an automatic emergency braking (“AEB”) system is used, a false positive detection may cause the vehicle to automatically apply emergency braking, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered an AEB trigger. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as, among others, the bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from the IMU sensor 1066 that correlates with the orientation of the vehicle 1000, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., the LIDAR sensor 1064 or the RADAR sensor 1060).

[0147] In at least one embodiment, one or more of the SoCs 1004 may include a data store 1016 (e.g., memory). In at least one embodiment, the data store 1016 may be on-chip memory of the SoC 1004, which may store neural networks running on the GPU 1008 and / or DLA. In at least one embodiment, the capacity of the data store 1016 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1016 may comprise an L2 or L3 cache.

[0148] In at least one embodiment, one or more of the SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, the processors 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1004 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 1004, and / or manage the power state of the SoC 1004. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1004 may use the ring oscillator to detect the temperature of the CPU 1006, GPU 1008, and / or accelerator 1014. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 1004 in a low power state, and / or place the vehicle 1000 in a driver-safety shutdown mode (e.g., bring the vehicle 1000 to a safety shutdown).

[0149] In at least one embodiment, processor 1010 may further include a set of embedded processors capable of acting as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0150] In at least one embodiment, processor 1010 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0151] In at least one embodiment, the processor 1010 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to addressing safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor 1010 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to addressing real-time camera management. In at least one embodiment, the processor 1010 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0152] In at least one embodiment, the processor 1010 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for the wide-angle camera 1070, the surrounding camera 1074, and / or the in-cabin surveillance camera sensor. In at least one embodiment, the in-cabin surveillance camera sensor is preferably monitored by a neural network running on a separate instance of the SoC 1004 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, without limitation, activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0153] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0154] In at least one embodiment, the video image compositor may also be configured to perform stereo correction on the input stereo lens frames. In at least one embodiment, the video image compositor may also be used for user interface compositing when the operating system desktop is in use, eliminating the need for the GPU 1008 to continually render new surfaces. In at least one embodiment, the video image compositor may be used to offload the GPU 1008 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0155] In at least one embodiment, one or more of the SoCs 1004 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1004 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0156] In at least one embodiment, one or more of the SoCs 1004 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. In at least one embodiment, the SoC 1004 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and an Ethernet channel), sensors (e.g., a LIDAR sensor 1064, a RADAR sensor 1060, etc., which may be connected via an Ethernet channel), data from the bus 1002 (e.g., vehicle 1000 speed, steering wheel position, etc.), data from a GNSS sensor 1058 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1004 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from the CPU 1006.

[0157] In at least one embodiment, the SoC 1004 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and providing a flexible and reliable driving software stack platform along with deep learning tools. In at least one embodiment, the SoC 1004 may be faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 1014, when combined with the CPU 1006, GPU 1008, and data store 1016, may provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0158] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language such as C to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0159] Embodiments described herein may enable multiple neural networks to run simultaneously and / or sequentially, with the results combined together to enable Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN running on the DLA or a separate GPU (e.g., GPU1020) may include text and word recognition, allowing the neural network to read and understand traffic signs, including signs for which it was not specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a path planning module running on the CPU complex.

[0160] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 1008.

[0161] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1000. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves the vehicle. In this way, the SoC 1004 provides security against theft and / or carjacking.

[0162] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1096 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1004 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1058. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when operating in North America, the CNN attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program for executing an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or allow a vehicle assisted by ultrasonic sensor 1062 to idle until the emergency vehicle has passed.

[0163] In at least one embodiment, the vehicle 1000 may include a CPU 1018 (e.g., a discrete CPU or dCPU), which may be coupled to the SoC 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU 1018 may include, for example, an X86 processor. The CPU 1018 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between the ADAS sensors and the SoC 1004 and / or monitoring the status and health of the controller 1036 and / or infotainment system on a chip (“infotainment SoC”) 1030. In at least one embodiment, the SoC 1004 includes one or more interconnects, which may include Peripheral Component Interconnect Express (PCIe).

[0164] In at least one embodiment, vehicle 1000 may include GPU 1020 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU 1020 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors in vehicle 1000.

[0165] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, without limitation, a wireless antenna 1026 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1024 may be used to enable wireless connections to Internet cloud services (e.g., servers and / or other network devices) with other vehicles and / or computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1000 and the other vehicles and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1000). In at least one embodiment, these aforementioned features may be part of a cooperative adaptive cruise control feature of the vehicle 1000.

[0166] In at least one embodiment, the network interface 1024 may include an SoC that provides modulation and demodulation functionality, enabling the controller 1036 to communicate over a wireless network. In at least one embodiment, the network interface 1024 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0167] In at least one embodiment, vehicle 1000 may further include a data store 1028, which may include, without limitation, off-chip (e.g., not on SoC 1004) storage. In at least one embodiment, data store 1028 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0168] In at least one embodiment, vehicle 1000 may further include GNSS sensors 1058 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0169] In at least one embodiment, vehicle 1000 may further include a RADAR sensor 1060. In at least one embodiment, RADAR sensor 1060 may be used by vehicle 1000 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, RADAR sensor 1060 may use a CAN bus and / or bus 1002 for control (e.g., to transmit data generated by RADAR sensor 1060) and to access object tracking data, and in some examples, may have access to an Ethernet channel to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 1060 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 1060 are pulse-Doppler RADAR sensors.

[0170] In at least one embodiment, the RADAR sensor 1060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 m (meter) range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1060 may help distinguish between static and moving objects and may be used by the ADAS system 1038 to provide emergency braking assistance and forward collision warning. In at least one embodiment, the sensors 1060 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1000 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting the lane of vehicle 1000.

[0171] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1060 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1038 to provide blind spot detection and / or lane change assistance.

[0172] In at least one embodiment, vehicle 1000 may further include ultrasonic sensors 1062. In at least one embodiment, ultrasonic sensors 1062 may be located at the front, rear, and / or sides of vehicle 1000 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 1062 may operate at functional safety level ASIL B.

[0173] In at least one embodiment, vehicle 1000 may include a LIDAR sensor 1064. In at least one embodiment, LIDAR sensor 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor 1064 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 1000 may include multiple LIDAR sensors 1064 (e.g., two, four, six, etc.), which may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0174] In at least one embodiment, the LIDAR sensor 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1064 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor 1064 may include a small device that can be integrated into the front, rear, side, and / or corner positions of the vehicle 1000. In at least one embodiment, the LIDAR sensor 1064 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1064 may be configured for a horizontal field of view of 45 degrees to 135 degrees.

[0175] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1000 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1000 to the object. In at least one embodiment, flash LIDAR may enable a highly accurate, undistorted image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be installed, one on each side of the vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0176] In at least one embodiment, vehicle 1000 may further include an IMU sensor 1066. In at least one embodiment, IMU sensor 1066 may be positioned at the center of a rear axle of vehicle 1000. In at least one embodiment, IMU sensor 1066 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, multiple magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, IMU sensor 1066 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, IMU sensor 1066 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0177] In at least one embodiment, the IMU sensor 1066 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1066 enables the vehicle 1000 to estimate its heading by directly observing velocity changes and correlating them from the GPS to the IMU sensor 1066 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 1066 and the GNSS sensor 1058 may be combined into a single integrated unit.

[0178] In at least one embodiment, vehicle 1000 may include microphones 1096 located in and / or around vehicle 1000. In at least one embodiment, microphones 1096 may be used for, among other things, emergency vehicle detection and identification.

[0179] In at least one embodiment, vehicle 1000 may further include any number of camera types, including stereo cameras 1068, wide-angle cameras 1070, infrared cameras 1072, perimeter cameras 1074, long-range cameras 1098, mid-range cameras 1076, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of vehicle 1000. In at least one embodiment, the types of cameras used vary depending on vehicle 1000. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1000. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1000 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be as described in further detail herein above with respect to Figures 10A and 10B.

[0180] In at least one embodiment, vehicle 1000 may further include a vibration sensor 1042. In at least one embodiment, vibration sensor 1042 may measure vibration of a component of vehicle 1000, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 1042 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0181] In at least one embodiment, vehicle 1000 may include an ADAS system 1038. In at least one embodiment, ADAS system 1038 may include, in some examples, without limitation, an SoC. In at least one embodiment, the ADAS systems 1038 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0182] In at least one embodiment, the ACC system may use a RADAR sensor 1060, a LIDAR sensor 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle directly in front of the vehicle 1000 and automatically adjusts the speed of the vehicle 1000 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 1000 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0183] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by the network interface 1024 and / or wireless antenna 1026 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, V2V communication provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of and in the same lane as vehicle 1000), while I2V communication provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 1000 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0184] In at least one embodiment, the FCW system is designed to alert drivers to hazards so that they can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide a warning, such as in the form of an audible, visual warning, vibration, and / or quick brake pulse.

[0185] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0186] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 1000 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering input or brake control to correct the vehicle 1000 if the vehicle 1000 begins to stray from its lane.

[0187] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 1060 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0188] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1000. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components.

[0189] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1000 itself determines whether to follow the results from the primary computer or the secondary computer (e.g., the first controller or the second controller of the controller 1036). For example, in at least one embodiment, the ADAS system 1038 may be a backup and / or secondary computer for providing perception information to a rationality module of the backup computer. In at least one embodiment, the rationality monitor of the backup computer may run redundant software on various hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 1038 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0190] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0191] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary computer and the secondary computer. In at least one embodiment, the neural network of the monitoring MCU may learn when the output of the secondary computer may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the neural network of the monitoring MCU may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the neural network of the monitoring MCU may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC 1004.

[0192] In at least one embodiment, the ADAS system 1038 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use classical computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the overall system more error-tolerant, particularly to errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides overall consistent results, the supervisory MCU may have greater confidence that the overall results are correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0193] In at least one embodiment, the output of the ADAS system 1038 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network pre-trained as described herein, thus reducing the risk of false positives.

[0194] In at least one embodiment, vehicle 1000 may further include an infotainment SoC 1030 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 1030 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 1030 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, reverse parking assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 1000. For example, infotainment SoC 1030 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 1034, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1030 may also be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1000, such as information from ADAS system 1038, autonomous driving information such as vehicle maneuver plans, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0195] In at least one embodiment, infotainment SoC 1030 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1030 may communicate with other devices, systems, and / or components of vehicle 1000 via bus 1002. In at least one embodiment, infotainment SoC 1030 may be coupled to a supervisory MCU, such that the infotainment system's GPU may perform some self-driving functions when primary controller 1036 (e.g., vehicle 1000's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1030 may place vehicle 1000 in a driver-safety shutdown mode, as described herein.

[0196] In at least one embodiment, vehicle 1000 may further include an instrument cluster 1032 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1032 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 1032 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1030 and instrument cluster 1032. In at least one embodiment, instrument cluster 1032 may be included as part of infotainment SoC 1030, or vice versa.

[0197] 10D is a diagram of a system for communicating between a cloud-based server and the autonomous vehicle 1000 of FIG. 10A , according to at least one embodiment. In at least one embodiment, the system may include any number and type of vehicles, including, without limitation, a server 1078, a network 1090, and the vehicle 1000. In at least one embodiment, the server 1078 may include, without limitation, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPUs 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switches 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPUs 1080). In at least one embodiment, the GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 1088 developed by NVIDIA, and / or a PCIe connection 1086. In at least one embodiment, the GPUs 1084 are connected to each other via an NVLink and / or NVS switch SoC, and the GPUs 1084 and PCIe switches 1082 are connected via a PCIe interconnect. While eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are illustrated, this is not intended to be limiting. In at least one embodiment, each of the servers 1078 may include any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination, without limitation. For example, in at least one embodiment, the servers 1078 may each include 8, 16, 32, and / or more GPUs 1084.

[0198] In at least one embodiment, server 1078 may receive image data from a vehicle over network 1090 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1078 may transmit updated or unupdated neural network 1092 and / or map information 1094, including, without limitation, information about traffic and road conditions, to the vehicle over network 1090. In at least one embodiment, updates to map information 1094 may include, without limitation, updates to HD map 1022, such as information about construction sites, potholes, detours, floods, and / or other obstacles. In at least one embodiment, neural network 1092 and / or map information 1094 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1078 and / or other servers).

[0199] In at least one embodiment, server 1078 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., sent to the vehicle via network 1090) and / or used by server 1078 to remotely monitor the vehicle.

[0200] In at least one embodiment, server 1078 may receive data from vehicles and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, server 1078 may include a deep learning supercomputer and / or dedicated AI computer powered by a GPU 1084, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1078 may also include a deep learning infrastructure using a CPU-powered data center.

[0201] In at least one embodiment, the deep learning infrastructure of server 1078 may be capable of fast, real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as a series of images and / or objects that vehicle 1000 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 1000; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1000 has failed, server 1078 may send a signal to vehicle 1000 instructing the vehicle's 1000 fail-safe computer to take control, notify the occupants, and complete a safe stopping maneuver.

[0202] In at least one embodiment, server 1078 may include a GPU 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3 devices). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 715 is used to execute one or more embodiments. Details regarding hardware structure 715 are provided herein in conjunction with FIG. 7A and / or FIG. 7B.

[0203] In at least one embodiment, one or more systems depicted in Figures 10A-10D are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figures 10A-10D are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figures 10A-10D are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0204] Computer Systems 11 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof, formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1100 may include components such as, without limitation, processor 1102 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1100 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1100 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0205] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0206] In at least one embodiment, computer system 1100 may include, without limitation, a processor 1102, which may include one or more execution units 1108 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, while in other embodiments, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, without limitation, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to a processor bus 1110, which may transmit digital signals between processor 1102 and other components within computer system 1100.

[0207] In at least one embodiment, processor 1102 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1102. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1106 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0208] In at least one embodiment, processor 1102 also includes an execution unit 1108, including, without limitation, logic for performing integer and floating-point operations. In at least one embodiment, processor 1102 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1108 may include logic for a packed instruction set 1109. In at least one embodiment, including a packed instruction set 1109, along with associated circuitry for executing the instructions, in a general-purpose processor's instruction set allows operations used by many multimedia applications to be performed using packed data in processor 1102. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0209] In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, without limitation, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0210] In at least one embodiment, a system logic chip may be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1116, and the processor 1102 may communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 may provide a high-bandwidth memory path 1118 to the memory 1120 for instruction and data storage, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1116 may route data signals between the processor 1102, the memory 1120, and other components of the computer system 1100, and may bridge data signals between the processor bus 1110, the memory 1120, and a system I / O interface 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to memory 1120 via a high-bandwidth memory path 1118, and the graphics / video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (“AGP”) interconnect 1114.

[0211] In at least one embodiment, computer system 1100 may use system I / O interface 1122 as a proprietary hub interface bus to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1120, a chipset, and processor 1102. Examples may include, without limitation, an audio controller 1129, a firmware hub ("flash BIOS") 1128, a wireless transceiver 1126, data storage 1124, a legacy I / O controller 1123 including a user input and keyboard interface 1125, a serial expansion port 1127 such as a Universal Serial Bus ("USB") port, and a network controller 1134. In at least one embodiment, data storage 1124 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0212] In at least one embodiment, Figure 11 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 11 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Figure 11 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1100 may be interconnected using a compute express link (CXL) interconnect.

[0213] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in computer system 1100 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0214] In at least one embodiment, one or more systems depicted in Figure 11 are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figure 11 are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figure 11 are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0215] 12 is a block diagram illustrating an electronic device 1200 for utilizing a processor 1210, according to at least one embodiment. In at least one embodiment, electronic device 1200 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0216] In at least one embodiment, electronic device 1200 may include, without limitation, a processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2The devices may be coupled using a bus or interface such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 12 illustrates a system including interconnected hardware devices or “chips,” while in other embodiments, FIG. 12 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 12 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 12 may be interconnected using a Compute Express Link (CXL) interconnect.

[0217] In at least one embodiment, FIG. 12 illustrates a display 1224, a touch screen 1225, a touch pad 1230, a Near Field Communications unit ("NFC") 1245, a sensor hub 1240, a thermal sensor 1246, an Express Chipset ("EC") 1235, a Trusted Platform Module ("TPM") 1238, a BIOS / firmware / flash memory ("BIOS,FW flash") 1222, a DSP 1260, a drive 1220, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") 1250, a Bluetooth unit 1252, a wireless wide area network unit ("WWAN") 1254, a Bluetooth module 1254, a Bluetooth-enabled device ("Bluetooth") 1256, a Bluetooth-enabled device ("Bluetooth") 1258, a Bluetooth-enabled device ("Bluetooth") 1260, a Bluetooth-enabled device ("Bluetooth") 1262, a Bluetooth-enabled device ("Bluetooth") 1264, a Bluetooth-enabled device ("Bluetooth") 1266, a Bluetooth-enabled device ("Bluetooth") 1268 ... The memory may include a memory controller (RAM) 1256, a Global Positioning System (GPS) unit 1255, a camera such as a USB 3.0 camera ("USB 3.0 camera") 1254, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1215, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0218] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components described herein. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, headphones 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and class D amplifier”) 1262, which may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, without limitation, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, SIM card ("SIM") 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250 and Bluetooth unit 1252, as well as WWAN unit 1256, may be implemented in a Next Generation Form Factor ("NGFF").

[0219] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in electronic device 1200 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0220] In at least one embodiment, one or more systems depicted in Figure 12 are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figure 12 are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figure 12 are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0221] 13 illustrates a computer system 1300, according to at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement the various processes and methods described throughout this disclosure.

[0222] In at least one embodiment, computer system 1300 includes at least one central processing unit ("CPU") 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1300 includes main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1304, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1322 provides an interface with other computing devices and networks to receive data from other systems comprising computer system 1300 and to transmit data to other systems comprising computer system 1300.

[0223] In at least one embodiment, computer system 1300 includes, without limitation, input device(s) 1308, parallel processing system 1312, and display device 1306, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED") display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1308, such as a keyboard, mouse, touch pad, microphone, etc. In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0224] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in computer system 1300 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0225] In at least one embodiment, one or more systems depicted in Figure 13 are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figure 13 are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figure 13 are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0226] 14 illustrates a computer system 1400, according to at least one embodiment. In at least one embodiment, computer system 1400 may include, without limitation, a computer 1410 and a USB stick 1420. In at least one embodiment, computer 1410 may include, without limitation, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 1410 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0227] In at least one embodiment, USB stick 1420 includes, without limitation, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, processing unit 1430 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1430 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1430 comprises an application specific integrated circuit (“ASIC”) optimized to perform any quantity and type of operations associated with machine learning. For example, in at least one embodiment, processing unit 1430 is a tensor processing unit (“TPC”) optimized to perform machine vision and machine learning inference operations. In at least one embodiment, processing unit 1430 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0228] In at least one embodiment, USB interface 1440 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1440 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1450 may include any amount and type of logic that enables processing unit 1430 to interface with a device (e.g., computer 1410) via USB connector 1440.

[0229] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in computer system 1400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0230] In at least one embodiment, one or more systems depicted in Figure 14 are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figure 14 are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figure 14 are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0231] FIG. 15A illustrates an exemplary architecture in which multiple GPUs 1510(1)-1510(N) are communicatively coupled to multiple multi-core processors 1505(1)-1505(M) via high-speed links 1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1540(1)-1540(N) support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. 18A and 18B, one or more of the plurality of GPUs 1510(1)-1510(N) includes one or more graphics cores (also referred to simply as "cores") 1800. In at least one embodiment, one or more graphics cores 1800 may also be referred to as streaming multiprocessors ("SM"), stream processors ("SP"), stream processing units ("SPU"), compute units ("CU"), execution units ("EU"), and / or slices, and in this context, a slice may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0232] Additionally, in at least one embodiment, two or more of the GPUs 1510 are interconnected via high-speed links 1529(1)-1529(2), which may be implemented using similar or different protocols / links as used for high-speed links 1540(1)-1540(N). Similarly, two or more of the multi-core processors 1505 may be connected via high-speed link 1528, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 15A may be achieved using similar protocols / links (e.g., via a common interconnect fabric).

[0233] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to processor memory 1501(1)-1501(M) via memory interconnect 1526(1)-1526(M), respectively, and each GPU 1510(1)-1510(N) is communicatively coupled to GPU memory 1520(1)-1520(N) via GPU memory interconnect 1550(1)-1550(N), respectively. In at least one embodiment, memory interconnects 1526 and 1550 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memory 1501(1)-1501(M) and GPU memory 1520 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of processor memory 1501 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0234] As described herein, various multi-core processors 1505 and GPUs 1510 may each be physically coupled to specific memories 1501, 1520, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address" space) is distributed among various physical memories. For example, processor memories 1501(1) through 1501(M) may each have 64 GB of system memory address space, and GPU memories 1520(1) through 1520(N) may each have 32 GB of system memory address space, resulting in a total of 256 GB of addressable memory when M=2 and N=4. Other values ​​for N and M are contemplated.

[0235] 15B illustrates further details of the interconnection between multi-core processor 1507 and graphics acceleration module 1546 according to one example embodiment. In at least one embodiment, graphics acceleration module 1546 may include one or more GPU chips integrated on a line card that is coupled to processor 1507 via high-speed link 1540 (e.g., PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, graphics acceleration module 1546 may be integrated into the package or chip with processor 1507.

[0236] In at least one embodiment, the processor 1507 includes multiple cores 1560A-1560D (which may also be referred to as "execution units"), each having a translation lookaside buffer (TLB) 1561A-1561D and one or more caches 1562A-1562D. In at least one embodiment, the cores 1560A-1560D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1562A-1562D may comprise a level 1 (L1) and a level 2 (L2) cache. Additionally, one or more shared caches 1556 may be included in the caches 1562A-1562D and shared by the set of cores 1560A-1560D. For example, one embodiment of processor 1507 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more of the L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1507 and graphics acceleration module 1546 are coupled to system memory 1514, which may include processor memories 1501(1)-1501(M) of FIG. 15A.

[0237] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1562A-1562D, 1556, and system memory 1514 through inter-core communication via coherence bus 1564. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith for communicating via coherence bus 1564 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via coherence bus 1564 to monitor cache accesses.

[0238] In at least one embodiment, proxy circuit 1525 communicatively couples graphics acceleration module 1546 to coherence bus 1564 to enable graphics acceleration module 1546 to participate in cache coherence protocols as a peer of cores 1560A-1560D. In particular, in at least one embodiment, interface 1535 provides a connection to proxy circuit 1525 over high-speed link 1540, and interface 1537 connects graphics acceleration module 1546 to high-speed link 1540.

[0239] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546 include one or more graphics cores 1800, as discussed in connection with FIGs. 18A and 18B. Alternatively, in at least one embodiment, the graphics processing engines 1531(1)-1531(N) may comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having multiple graphics processing engines 1531(1)-1531(N), or the graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated into a common package, line card, or chip.

[0240] In at least one embodiment, accelerator integrated circuitry 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1514. In at least one embodiment, MMU 1539 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1538 may store commands and data for efficient access by graphics processing engines 1531(1)-1531(N). In at least one embodiment, data stored in cache 1538 and graphics memory 1533(1)-1533(M) is kept coherent with core caches 1562A-1562D, 1556, and system memory 1514, possibly using fetch unit 1544. As noted, this may be accomplished via proxy circuitry 1525 (e.g., sending updates to cache 1538 regarding modifications / accesses of cache lines in processor caches 1562A-1562D, 1556, and receiving updates from cache 1538) on behalf of cache 1538 and memory 1533(1)-1533(M).

[0241] In at least one embodiment, a set of registers 1545 stores context data for threads executed by graphics processing engines 1531(1)-1531(N), and a context management circuit 1548 manages thread contexts. For example, the context management circuit 1548 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1548 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 1548 may restore the register values. In at least one embodiment, the interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0242] In at least one embodiment, virtual / effective addresses from the graphics processing engine 1531 are translated to real / physical addresses in the system memory 1514 by the MMU 1539. In at least one embodiment, the accelerator integration circuit 1536 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator modules 1546 may be dedicated to a single application running on the processor 1507 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1531(1)-1531(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0243] In at least one embodiment, the accelerator integrated circuit 1536 performs as a bridge to the system for the graphics acceleration module 1546, providing address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 may provide a virtualization facility for a host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1531(1)-1531(N).

[0244] In at least one embodiment, the hardware resources of graphics processing engines 1531(1)-1531(N) are explicitly mapped into the real address space seen by host processor 1507, so that any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1536 is to physically separate graphics processing engines 1531(1)-1531(N) so that they appear to the system as independent units.

[0245] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are each coupled to a respective one of the graphics processing engines 1531(1)-1531(N), where N=M. In at least one embodiment, the graphics processing memories 1533(1)-1533(M) can store instructions and data to be processed by each of the graphics processing engines 1531(1)-1531(N). In at least one embodiment, the graphics memories 1533(1)-1533(M) can be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory such as 3D XPoint or Nano-Ram.

[0246] In at least one embodiment, to reduce data traffic over high-speed link 1540, biasing techniques can be used to ensure that the data stored in graphics memory 1533(1)-1533(M) is data that will be used most frequently by graphics processing engines 1531(1)-1531(N), and preferably is data that is not used (or at least not frequently) by cores 1560A-1560D. Similarly, in at least one embodiment, biasing mechanisms attempt to keep data needed by the cores (and thus preferably not by graphics processing engines 1531(1)-1531(N)) in caches 1562A-1562D, 1556, and system memory 1514.

[0247] FIG. 15C illustrates another exemplary embodiment in which accelerator integration circuitry 1536 is integrated within processor 1507. In this embodiment, graphics processing engines 1531(1)-1531(N) communicate directly with accelerator integration circuitry 1536 via high-speed link 1540 (which again may be any form of bus or interface protocol) via interface 1537 and interface 1535. In at least one embodiment, accelerator integration circuitry 1536 may perform operations similar to those described with respect to FIG. 15B, but potentially at a higher throughput given its proximity to coherence bus 1564 and caches 1562A-1562D, 1556. In at least one embodiment, the accelerator integrated circuitry supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuitry 1536 and a programming model controlled by the graphics acceleration module 1546.

[0248] In at least one embodiment, graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can route other application requests to graphics processing engines 1531(1)-1531(N), achieving virtualization within a VM / partition.

[0249] In at least one embodiment, graphics processing engines 1531(1)-1531(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1531(1)-1531(N) to allow access by each operating system. In at least one embodiment, in a single-partition system without a hypervisor, graphics processing engines 1531(1)-1531(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0250] In at least one embodiment, graphics acceleration module 1546 or individual graphics processing engines 1531(1)-1531(N) selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1514 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with graphics processing engines 1531(1)-1531(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0251] FIG. 15D illustrates an exemplary accelerator integration slice 1590. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of accelerator integration circuitry 1536. In at least one embodiment, application effective address space 1582 in system memory 1514 stores process element 1583. In at least one embodiment, process element 1583 is stored in response to a GPU call 1581 from an application 1580 executing on processor 1507. In at least one embodiment, process element 1583 contains the process state of the corresponding application 1580. In at least one embodiment, work descriptor (WD) 1584 contained in process element 1583 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1584 is a pointer to a job request queue in application effective address space 1582.

[0252] In at least one embodiment, graphics acceleration module 1546 and / or individual graphics processing engines 1531(1)-1531(N) may be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD 1584 to graphics acceleration module 1546 to start a job in a virtualized environment.

[0253] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integration circuitry 1536 for the owning partition when the graphics acceleration module 1546 is allocated, and the operating system initializes the accelerator integration circuitry 1536 for the owning process.

[0254] In at least one embodiment, in operation, WD fetch unit 1591 in accelerator integrated slice 1590 fetches the next WD 1584, which contains an indication of work to be performed by one or more graphics processing engines of graphics acceleration module 1546. In at least one embodiment, as shown, data from WD 1584 may be stored in register 1545 and used by MMU 1539, interrupt management circuit 1547, and / or context management circuit 1548. For example, one embodiment of MMU 1539 includes segment / page walk circuitry for accessing segment / page table 1586 within OS virtual address space 1585. In at least one embodiment, interrupt management circuit 1547 may process interrupt events 1592 received from graphics acceleration module 1546. In at least one embodiment, when performing graphics operations, effective addresses 1593 generated by graphics processing engines 1531(1)-1531(N) are translated into real addresses by MMU 1539.

[0255] In at least one embodiment, registers 1545 may be replicated for each graphics processing engine 1531(1)-1531(N) and / or graphics acceleration module 1546 and initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in accelerator integration slice 1590. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. [Table 1]

[0256] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0257] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, WD 1584 may contain all the information that graphics processing engine 1531(1)-1531(N) needs to do its work, or may be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0258] 15E illustrates further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1598 in which a process element list 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 is accessible through a hypervisor 1596 that virtualizes the graphics acceleration module engine of the operating system 1595.

[0259] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0260] In at least one embodiment, in this model, system hypervisor 1596 owns graphics acceleration module 1546 and makes its functionality available to all operating systems 1595. In at least one embodiment, in order for graphics acceleration module 1546 to support virtualization by system hypervisor 1596, graphics acceleration module 1546 may comply with several requirements, such as: (1) application job requests must be autonomous (i.e., no state needs to be maintained between jobs) or graphics acceleration module 1546 must provide a mechanism for saving and restoring context; (2) application job requests must be guaranteed by graphics acceleration module 1546 to complete in a specified amount of time, including any translation errors, or graphics acceleration module 1546 must provide the ability to preempt job processing; and (3) graphics acceleration module 1546 must ensure fairness between processes when operating in a specified shared programming model.

[0261] In at least one embodiment, application 1580 must make a system call to operating system 1595 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for graphics acceleration module 1546 and may be in the form of a graphics acceleration module 1546 command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by graphics acceleration module 1546.

[0262] In at least one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1536 (not shown) and the graphics acceleration module 1546 does not support a User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. In at least one embodiment, the hypervisor 1596 may optionally apply the current Authorization Mask Override Register (AMOR) value before placing the AMR in the process element 1583. In at least one embodiment, the CSRP is one of the registers 1545 that contains the effective address of an area in the application's effective address space 1582 for the graphics acceleration module 1546 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0263] Upon receiving the system call, operating system 1595 may verify that application 1580 is registered and authorized to use graphics acceleration module 1546. In at least one embodiment, operating system 1595 then calls hypervisor 1596 with the information shown in Table 3. [Table 3]

[0264] In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1596 verifies that the operating system 1595 is registered and authorized to use the graphics acceleration module 1546. In at least one embodiment, the hypervisor 1596 then places the process element 1583 into a process element linked list of the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4. [Table 4]

[0265] In at least one embodiment, the hypervisor initializes registers 1545 of multiple accelerator integrated slices 1590.

[0266] As shown in FIG. 15F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memories 1501(1)-1501(N) and GPU memories 1520(1)-1520(N). In this implementation, operations performed on GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space as those used to access processor memories 1501(1)-1501(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion is allocated to second processor memory 1501(N), a third portion is allocated to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memory 1501 and GPU memory 1520, allowing any processor or GPU to access any physical memory, with virtual addresses mapped to physical memory.

[0267] In at least one embodiment, bias / coherence management circuits 1594A-1594E in one or more of MMUs 1539A-1539E ensure cache coherence between caches of one or more host processors (e.g., 1505) and caches of GPU 1510 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, multiple instances of bias / coherence management circuits 1594A-1594E are illustrated in FIG. 15F, although bias / coherence circuits may be implemented within the MMUs of one or more host processors 1505 and / or within accelerator integration circuit 1536.

[0268] One embodiment enables GPU memory 1520 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, having GPU memory 1520 accessible as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this configuration enables host processor 1505 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access GPU memory 1520 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the presence of significant streaming write memory traffic, cache coherence overhead may significantly reduce the effective write bandwidth seen by the GPU 1510. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may be useful in determining the effectiveness of GPU offloading.

[0269] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (e.g., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1520, with or without a bias cache in GPU 1510 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the bias table may be maintained entirely within the GPU.

[0270] In at least one embodiment, a bias table entry associated with each access to GPU-biased memory 1520 is accessed prior to the actual access to the GPU memory, resulting in the following actions: In at least one embodiment, a local request from the GPU 1510 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1520. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to the processor 1505 (e.g., via the high-speed link described above). In at least one embodiment, a request from the processor 1505 to find the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 1510. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, simply a hardware-based mechanism.

[0271] In at least one embodiment, one mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1505 bias to GPU bias, but not for transitions in the opposite direction.

[0272] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages uncacheable by the host processor 1505. In at least one embodiment, to access these pages, the processor 1505 may request access from the GPU 1510, which may or may not immediately grant the access. Thus, in at least one embodiment, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial to ensure that GPU-biased pages are requested by the GPU but not by the host processor 1505, or vice versa.

[0273] To implement one or more embodiments, a hardware structure 715 is used, details regarding the hardware structure 715 may be provided herein in conjunction with Figures 7A and / or 7B.

[0274] In at least one embodiment, one or more systems depicted in Figures 15A-15F are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figures 15A-15F are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figures 15A-15F are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0275] 16 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral device interface controllers, or general-purpose processor cores.

[0276] 16 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1600 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1600 includes one or more application processors 1605 (e.g., a CPU), at least one graphics processor 1610, and may further include an image processor 1615 and / or a video processor 1620, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1600 includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I / O controller 1640. 2 2S / I 2The integrated circuit 1600 includes peripheral or bus logic including a HDMI™ controller 1640. In at least one embodiment, the integrated circuit 1600 may include a display device 1645 coupled to one or more of a high-definition multimedia interface (HDMI™) controller 1650 and a mobile industry processor interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 1670.

[0277] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in integrated circuit 1600 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0278] In at least one embodiment, one or more systems depicted in Figure 16 are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figure 16 are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figure 16 are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0279] 17A-17B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0280] 17A-17B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 17A illustrates an exemplary graphics processor 1710 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. FIG. 17B illustrates a further exemplary graphics processor 1740 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1710 of FIG. 17A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1740 of FIG. 17B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 1710, 1740 can be a variation of the graphics processor 1610 of FIG. 16.

[0281] In at least one embodiment, graphics processor 1710 includes vertex processor 1705 and one or more fragment processors 1715A-1715N (e.g., 1715A, 1715B, 1715C, 1715D-1715N-1, and 1715N). In at least one embodiment, graphics processor 1710 can execute different shader programs through separate logic, such that vertex processor 1705 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1715A-1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1705 executes the vertex processing stage of a 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processors 1715A-1715N use the primitive and vertex data generated by vertex processor 1705 to generate a frame buffer that is displayed on a display device. In at least one embodiment, fragment processors 1715A-1715N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0282] In at least one embodiment, graphics processor 1710 further includes one or more memory management units (MMUs) 1720A-1720B, caches 1725A-1725B, and circuit interconnects 1730A-1730B. In at least one embodiment, one or more MMUs 1720A-1720B provide virtual-to-physical address mapping for graphics processor 1710, including vertex processor 1705 and / or fragment processors 1715A-1715N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1725A-1725B. In at least one embodiment, one or more MMUs 1720A-1720B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1605, image processor 1615, and / or video processor 1620 of Figure 16, allowing each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1730A-1730B allow graphics processor 1710 to interface with other IP cores in the SoC via an internal bus of the SoC or via a direct connection.

[0283] 17B, ​​graphics processor 1740 includes one or more shader cores 1755A-1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F-1755N-1, and 1755N), which provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 1740 includes an inter-core task manager 1745 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1755A-1755N, and a tiling unit 1758 for accelerating tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0284] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in graphics processors 1710 and 1740 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0285] In at least one embodiment, one or more systems depicted in Figures 17A-17B are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figures 17A-17B are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figures 17A-17B are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0286] 18A-18B illustrate further exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, the components illustrated and described in connection with FIGS. 18A-18B are integrated into a single system, such as a graphics processing unit (GPU), SoC, or other type of processor. FIG. 18A illustrates a graphics core 1800, which, in at least one embodiment, may be included in the graphics processor 1610 of FIG. 16 or, in at least one embodiment, may be integrated shader cores 1755A-1755N, as in FIG. 17B. FIG. 18B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU," which may also be referred to as a "graphics processing unit") 1830 suitable for deployment in a multi-chip module in at least one embodiment. In at least one embodiment, the graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 1600 includes graphics core 1800, e.g., forming an integrated circuit, and / or such integrated circuit and / or SoC forming an SoC that performs the operations described herein.

[0287] In at least one embodiment, graphics core 1800 includes a shared instruction cache 1802, a texture unit 1818, and cache / shared memory 1820 (e.g., including L1, L2, L3, last level cache, or other caches) that are common to execution resources within graphics core 1800. In at least one embodiment, graphics core 1800 may include multiple slices 1801A-1801N, or partitions per core, and a graphics processor may include multiple instances of graphics core 1800. In at least one embodiment, each slice 1801A-1801N refers to graphics core 1800. In at least one embodiment, slices 1801A-1801N have sub-slices that are part of slices 1801A-1801N. In at least one embodiment, slices 1801A-1801N may be independent of other slices or may be dependent on other slices. In at least one embodiment, slices 1801A-1801N may include support logic including local instruction caches 1804A-1804N, thread schedulers (sequencers) 1806A-1806N, thread dispatchers 1808A-1808N, and sets of registers 1810A-1810N. In at least one embodiment, slices 1801A-1801N may include a set of additional functional units (AFUs 1812A-1812N), floating point units (FPUs 1814A-1814N), integer arithmetic logic units (ALUs 1816A-1816N), address calculation units (ACUs 1813A-1813N), double precision floating point units (DPFPUs 1815A-1815N), and matrix processing units (MPUs 1817A-1817N). In at least one embodiment, MPUs 1817A-1817N are referred to as matrix engines.

[0288] In at least one embodiment, each slice 1801A-1801N includes one or more engines for floating-point and integer vector operations, as well as one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1801A-1801N include one or more vector engines for computing vectors (e.g., computing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64"). In at least one embodiment, one or more slices 1801A-1801N include 16 vector engines paired with 16 matrix math units for computing matrix / tensor operations, where the vector engines and math units are exposed via matrix expansion. In at least one embodiment, a slice is a designated portion of a processing unit's processing resources, e.g., 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for the processor. In at least one embodiment, graphics core 1800 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0289] In at least one embodiment, one or more slices 1801A-1801N include one or more ray tracing units (e.g., 16 ray tracing units per slice 1801A-1801N) for computing ray tracing operations. In at least one embodiment, the ray tracing units compute ray traversal, triangle intersection, bounding box intersection, or other ray tracing operations.

[0290] In at least one embodiment, one or more slices 1801A-1801N include media slices that encode, decode, and / or transcode data; scale and / or format convert data; and / or perform video quality operations on video data.

[0291] In at least one embodiment, one or more slices 1801A-1801N are linked to an L2 cache and memory fabric, link connectors, a high-bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1801A-1801N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1801A-1801N have one or more L1 caches. In at least one embodiment, one or more slices 1801A-1801N include: one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g., data corresponding to instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in a geometry pipeline and / or applying geometric transforms to vertices or polygons; one or more rasterizers for describing images in a vector graphics format (e.g., shapes) and converting them into raster images (e.g., a series of pixels, dots, or lines that, when displayed together, create the image represented by the shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, slices 1801A-1801N include a memory fabric, such as an L2 cache.

[0292] In at least one embodiment, the FPUs 1814A-1814N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1815A-1815N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1816A-1816N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1817A-1817N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 1817A-1817N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support acceleration of general matrix-to-matrix multiplication (GEMM). In at least one embodiment, AFUs 1812A-1812N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0293] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with FIG. 7A and / or FIG. 7B. In at least one embodiment, logic 715 may be used in graphics core 1800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0294] In at least one embodiment, the graphics core 1800 includes an interconnect and link fabric sublayer attached to a switch, and a GPU-GPU bridge that allows multiple graphics processors 1800 (e.g., 8) to be inter-linked using load / store units (LSUs), data transfer units, and synchronization semantics without gluing together across multiple graphics processors 1800. In at least one embodiment, the interconnect includes a standard interconnect (e.g., PCIe) or some combination thereof.

[0295] In at least one embodiment, graphics core 1800 includes multiple tiles. In at least one embodiment, tiles are individual dies or one or more dies where the individual dies may be connected by an interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 1800 includes compute tiles, memory tiles (e.g., where memory tiles may be exclusively accessed by different tiles or different chipsets, such as Rambo tiles), substrate tiles, base tiles, HMB tiles, link tiles, and EMIB tiles, all packaged together within graphics core 1800 as part of a GPU. In at least one embodiment, graphics core 1800 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile may include eight graphics cores 1800 and an L1 cache. The base tile can have host interfaces such as PCIe 5.0, HBM2e, MDFI, and EMIB, and the link tile can have eight links and eight ports with an embedded switch. In at least one embodiment, the tiles are connected through fine-pitch, 36-micron microbumps (e.g., copper pillars) with face-to-face (F2F) chip-on-chip bonding. In at least one embodiment, the graphics core 1800 includes a memory fabric, which includes memory and is accessible by multiple tiles. In at least one embodiment, the graphics core 1800 stores, accesses, or loads its own hardware context from memory, where the hardware context is a set of data loaded from registers before a process resumes, and the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0296] In at least one embodiment, graphics core 1800 includes serializer / deserializer (SERDES) circuitry that converts serial data streams to parallel data streams or converts parallel data streams to serial data streams.

[0297] In at least one embodiment, graphics core 1800 includes a high-speed, coherent integrated fabric (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected through an embedded switch, where the GPU-GPU bridges are controlled by a controller.

[0298] In at least one embodiment, graphics core 1800 executes an API that abstracts the hardware of graphics core 1800 and uses instructions to access libraries to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, collective communication, thread building blocks, video processing, data analytics libraries, and / or ray tracing operations.

[0299] FIG. 18B illustrates a GPGPU 1830, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 to enable connection with a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 (which may also be referred to as a thread sequencer and / or asynchronous compute engine) to distribute execution threads associated with those commands to a set of compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H share cache memory 1838. In at least one embodiment, cache memory 1838 can act as a higher-level cache for cache memories within compute clusters 1836A-1836H. In at least one embodiment, compute clusters 1836A-1836H include slices or are referred to as "slices." In at least one embodiment, GPGPU 1830 is part of an SoC, such as part of integrated circuit 1600 (FIG. 16).

[0300] In at least one embodiment, GPGPU 1830 includes memory 1844A-1844B coupled to compute clusters 1836A-1836H via a set of memory controllers 1842A-1842B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1844A-1844B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as graphics double data rate (GDDR) memory, and synchronous graphics random access memory (SGRAM).

[0301] In at least one embodiment, compute clusters 1836A-1836H each include a set of graphics cores, such as graphics core 1800 of FIG. 18A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1836A-1836H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0302] In at least one embodiment, multiple instances of GPGPU 1830 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1836A-1836H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 1830 communicate through host interface 1832. In at least one embodiment, GPGPU 1830 includes an I / O hub 1839 that couples GPGPU 1830 to GPU links 1840 that enable direct connections to other instances of GPGPU 1830. In at least one embodiment, GPU links 1840 are coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1830. In at least one embodiment, GPU links 1840 are coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1830 are located in separate data processing systems and communicate via a network device accessible via host interface 1832. In at least one embodiment, GPU link 1840 can be configured to allow connection to a host processor in addition to, or instead of, host interface 1832.

[0303] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment, when the GPGPU 1830 is used for inference, the GPGPU 1830 may include fewer compute clusters 1836A-1836H than when the GPGPU 1830 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A-1844B may differ between the inference configuration and the training configuration, with higher-bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0304] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in GPGPU 1830 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0305] In at least one embodiment, one or more systems depicted in Figures 18A-18B are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figures 18A-18B are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figures 18A-18B are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0306] 19 is a block diagram illustrating a computing system 1900 according to at least one embodiment. In at least one embodiment, the computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and system memory 1904 that communicate via an interconnection path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset component or may be integrated within the one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that can enable the computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, I / O hub 1907 can enable a display controller, which may be included in one or more processors 1902 and provide output to one or more display devices 1910A. In at least one embodiment, the one or more display devices 1910A coupled to I / O hub 1907 can include local, internal, or embedded display devices.

[0307] In at least one embodiment, processing subsystem 1901 includes one or more parallel processors 1912 coupled to memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, communication link 1913 may use one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 1912 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of parallel processors 1912 form a graphics processing subsystem that can output pixels to one of one or more display devices 1910A coupled via I / O hub 1907. In at least one embodiment, parallel processor 1912 also includes a display controller and display interface (not shown) that allows direct connection to one or more display devices 1910B. In at least one embodiment, parallel processor 1912 includes one or more cores, such as graphics core 1800 discussed herein.

[0308] In at least one embodiment, a system storage unit 1914 may be connected to an I / O hub 1907 to provide a storage mechanism for the computing system 1900. In at least one embodiment, an I / O switch 1916 may be used to provide an interface mechanism to enable communication between the I / O hub 1907 and other components, such as a network adapter 1918 and / or a wireless network adapter 1919, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0309] In at least one embodiment, computing system 1900 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1907. In at least one embodiment, the communication paths interconnecting the various components of FIG. 19 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface and / or protocol, such as an NV-Link high-speed interconnect, or interconnection protocol.

[0310] In at least one embodiment, parallel processor 1912 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU), e.g., parallel processor 1912 includes graphics core 1800. In at least one embodiment, parallel processor 1912 incorporates circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor 1912, memory hub 1905, processor 1902, and I / O hub 1907 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1900 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0311] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in computing system 1900 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0312] In at least one embodiment, one or more systems depicted in Figure 19 are utilized to perform operations discussed herein, such as generating a set of grasping proposals. In at least one embodiment, one or more systems depicted in Figure 19 are utilized to perform operations discussed herein, such as operations of a luminance field decoder and / or a grasping decoder. In at least one embodiment, one or more systems depicted in Figure 19 are utilized to implement one or more systems, techniques, and / or processes, such as those described in connection with Figures 1-6.

[0313] Processor 20A illustrates a parallel processor 2000 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2000 is a variation of the one or more parallel processors 1912 shown in FIG. 19 according to an example embodiment. In at least one embodiment, the parallel processor 2000 includes one or more graphics cores 1800.

[0314] In at least one embodiment, parallel processor 2000 includes parallel processing units 2002. In at least one embodiment, parallel processing units 2002 include I / O units 2004 that enable communication with other devices, including other instances of parallel processing units 2002. In at least one embodiment, I / O units 2004 may be directly connected to other devices. In at least one embodiment, I / O units 2004 are connected to other devices through the use of a hub or switch interface, such as memory hub 2005. In at least one embodiment, the connection between memory hub 2005 and I / O units 2004 forms communication link 2013. In at least one embodiment, I / O units 2004 are connected to host interface 2006 and memory crossbar 2016, where host interface 2006 receives commands directed to the execution of processing operations and memory crossbar 2016 receives commands directed to the execution of memory operations.

[0315] In at least one embodiment, when host interface 2006 receives command buffers via I / O unit 2004, host interface 2006 can direct work operations to execute these commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010 (which may also be referred to as a sequencer), which is configured to distribute commands or other work items to processing cluster array 2012. In at least one embodiment, scheduler 2010 ensures that processing cluster array 2012 is properly configured and in a valid state before tasks are distributed to clusters in processing cluster array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularity, allowing for rapid preemption and context switching of threads executing in the processing array 2012. In at least one embodiment, host software can direct scheduling workloads in the processing cluster array 2012 through one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed across the processing array cluster 2012 by scheduler 2010 logic in the microcontroller that includes the scheduler 2010.

[0316] In at least one embodiment, processing cluster array 2012 can include up to “N” processing clusters (e.g., cluster 2014A, cluster 2014B through cluster 2014N), where “N” represents a positive integer (although “N” may be a different integer than used in other figures). In at least one embodiment, each cluster 2014A through 2014N of processing cluster array 2012 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2010 can allocate work to clusters 2014A through 2014N of processing cluster array 2012 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2010 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 2012. In at least one embodiment, different clusters 2014A-2014N of processing cluster array 2012 may be allocated to process different types of programs or perform different types of calculations.

[0317] In at least one embodiment, the processing cluster array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, the processing cluster array 2012 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0318] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via the I / O unit 2004 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to system memory.

[0319] In at least one embodiment, when graphics processing is performed using parallel processing unit 2002, scheduler 2010 can be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 2014A-2014N of processing cluster array 2012. In at least one embodiment, portions of processing cluster array 2012 can be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2014A-2014N may be stored in a buffer so that the intermediate data can be transmitted between clusters 2014A-2014N for further processing.

[0320] In at least one embodiment, the processing cluster array 2012 can receive processing tasks to be performed via a scheduler 2010, which receives commands defining the processing tasks from the front end 2008. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 2010 can be configured to fetch the index corresponding to the task or can receive the index from the front end 2008. In at least one embodiment, the front end 2008 can be configured to ensure that the processing cluster array 2012 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0321] In at least one embodiment, each of one or more instances of parallel processing unit 2002 may be coupled to parallel processor memory 2022. In at least one embodiment, parallel processor memory 2022 may be accessed via memory crossbar 2016, which may receive memory requests from processing cluster array 2012 as well as I / O unit 2004. In at least one embodiment, memory crossbar 2016 may access parallel processor memory 2022 via memory interface 2018. In at least one embodiment, memory interface 2018 may include multiple partition units (e.g., partition unit 2020A, partition unit 2020B through partition unit 2020N), each of which may be coupled to a portion (e.g., a memory unit) of parallel processor memory 2022. In at least one embodiment, the number of partition units 2020A-2020N is configured to be equal to the number of memory units, such that a first partition unit 2020A has a corresponding first memory unit 2024A, a second partition unit 2020B has a corresponding memory unit 2024B, and an Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N does not have to be equal to the number of memory units.

[0322] In at least one embodiment, memory units 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2024A-2024N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM), HBM2e, or HDM3. In at least one embodiment, to efficiently use the available bandwidth of parallel processor memory 2022, render targets, such as frame buffers or texture maps, may be stored across memory units 2024A-2024N, allowing partition units 2020A-2020N to write portions of each render target in parallel. In at least one embodiment, the local instance of parallel processor memory 2022 may be omitted in favor of a unified memory design that uses both system memory and local cache memory.

[0323] In at least one embodiment, any one of the clusters 2014A-2014N of the processing cluster array 2012 can process data that is to be written to any one of the memory units 2024A-2024N in the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 can be configured to forward the output of each cluster 2014A-2014N to any partition unit 2020A-2020N or to another cluster 2014A-2014N that can perform further processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with a memory interface 2018 through the memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2016 has connections to a memory interface 2018 for communicating with the I / O units 2004, as well as connections to local instances of parallel processor memory 2022, allowing processing units in different processing clusters 2014A-2014N to communicate with system memory or other memory not local to the parallel processing units 2002. In at least one embodiment, the memory crossbar 2016 can use virtual channels to separate traffic streams between the clusters 2014A-2014N and the partition units 2020A-2020N.

[0324] In at least one embodiment, multiple instances of parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2002 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2002 may include a higher precision floating-point unit than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2002 or parallel processor 2000 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0325] FIG. 20B is a block diagram of a partition unit 2020 according to at least one embodiment. In at least one embodiment, the partition unit 2020 is an instance of one of the partition units 2020A-2020N of FIG. 20A. In at least one embodiment, the partition unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a raster operations unit (ROP) 2026. In at least one embodiment, the L2 cache 2021 is a read / write cache configured to execute load and store operations received from the memory crossbar 2016 and the ROP 2026. In at least one embodiment, read misses and urgent writeback requests are output by the L2 cache 2021 to the frame buffer interface 2025 for processing. In at least one embodiment, updates can also be sent to the frame via the frame buffer interface 2025 for processing. In at least one embodiment, frame buffer interface 2025 interfaces with one of the memory units of a parallel processor memory, such as memory units 2024A-2024N (eg, in parallel processor memory 2022) of FIG. 20A.

[0326] In at least one embodiment, ROP2026 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP2026 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2026 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a number of compression algorithms. In at least one embodiment, the type of compression performed by ROP2026 can be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0327] In at least one embodiment, ROP 2026 is included within each processing cluster (e.g., clusters 2014A-2014N of FIG. 20A ) instead of within partition unit 2020. In at least one embodiment, read and write requests for pixel data, instead of pixel fragment data, are transmitted through memory crossbar 2016. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 1910 of FIG. 19 , may be routed for further processing by processor 1902, or may be routed for further processing by one of the processing entities in parallel processor 2000 of FIG. 20A .

[0328] FIG. 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 2014A-2014N of FIG. 20A. In at least one embodiment, the processing cluster 2014 may be configured to execute multiple threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0329] In at least one embodiment, operation of the processing cluster 2014 may be controlled via a pipeline manager 2032, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032 receives instructions from the scheduler 2010 of FIG. 20A and manages the execution of those instructions via the graphics multiprocessor 2034 and / or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included within the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and a data crossbar 2040 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through the data crossbar 2040.

[0330] In at least one embodiment, each graphics multiprocessor 2034 in a processing cluster 2014 may include an identical set of function execution logic (e.g., arithmetic logic units, load store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0331] In at least one embodiment, an instruction sent to a processing cluster 2014 constitutes a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread groups execute a common program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 2034. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in the graphics multiprocessor 2034. In at least one embodiment, if a thread group includes more threads than the number of processing engines in the graphics multiprocessor 2034, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 2034.

[0332] In at least one embodiment, the graphics multiprocessor 2034 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 can forgo the internal cache and use cache memory (e.g., L1 cache 2048) within the processing cluster 2014. In at least one embodiment, each graphics multiprocessor 2034 can also access an L2 cache within a partition unit (e.g., partition units 2020A-2020N in FIG. 20A ), which may be shared among all processing clusters 2014 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2002 may be used as global memory. In at least one embodiment, the processing cluster 2014 may include multiple instances of the graphics multiprocessor 2034 and share common instructions and data, which may be stored in the L1 cache 2048.

[0333] In at least one embodiment, each processing cluster 2014 may include an MMU 2045 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2045 may reside within memory interface 2018 of FIG. 20A. In at least one embodiment, MMU 2045 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally cache line indexes. In at least one embodiment, MMU 2045 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 2034 or L1 2048 cache, or processing cluster 2014. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a cache line request is a hit or a miss.

[0334] In at least one embodiment, the processing clusters 2014 may be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034 and, as needed, fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs processed tasks to the data crossbar 2040 to provide the processed tasks to another processing cluster 2014 for further processing, or stores the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 2016. In at least one embodiment, a pre-ROP 2042 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2034 and direct the data to the ROP units, which may be located in partition units (e.g., partition units 2020A-2020N in FIG. 20A ) as described herein. In at least one embodiment, the pre-ROP 2042 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0335] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding logic 715 are provided herein in conjunction with Figures 7A and / or 7B. In at least one embodiment, logic 715 may be used in graphics processing cluster 2014 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0336] FIG. 20D illustrates a graphics multiprocessor 2034 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 couples with a pipeline manager 2032 of a processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline including, but not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066, where the one or more load / store units 2066 can perform load / store operations to load / store instructions corresponding to execution of the operations. In at least one embodiment, the GPGPU cores 2062 and the load / store units 2066 are coupled to a cache memory 2072 and a shared memory 2070 via a memory and cache interconnect 2068. In at least one embodiment, the GPGPU core 2062 is part of an SoC, such as part of the integrated circuit 1600 of FIG.

[0337] In at least one embodiment, instruction cache 2052 receives a stream of instructions to execute from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched for execution by instruction unit 2054. In at least one embodiment, instruction unit 2054 can dispatch instructions as thread groups (e.g., warps, wavefronts, waves), with each thread of a thread group assigned to a different execution unit within GPGPU core 2062. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 2056 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 2066.

[0338] In at least one embodiment, register file 2058 provides a set of registers to the functional units of graphics multiprocessor 2034. In at least one embodiment, register file 2058 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2062, load / store unit 2066) of graphics multiprocessor 2034. In at least one embodiment, register file 2058 is partitioned among the respective functional units, with each functional unit allocated a dedicated portion of register file 2058. In at least one embodiment, register file 2058 is partitioned among the different warps (which may also be referred to as wavefronts and / or waves) being executed by graphics multiprocessor 2034.

[0339] In at least one embodiment, the GPGPU cores 2062 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for the graphics multiprocessor 2034. In at least one embodiment, the GPGPU cores 2062 may have similar or different architectures. In at least one embodiment, a first portion of the GPGPU cores 2062 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU cores includes a double-precision FPU. In at least one embodiment, the FPUs may implement IEEE 754-2008 standard floating-point arithmetic or may enable variable-precision floating-point ...

Claims

1. 1. A system comprising: At least one processor; In response to execution by the at least one processor, the system Obtaining an input image depicting an object; generating a first set of images by at least using a first neural network with a decoder to process latent codes corresponding to the objects; updating the latent code based at least in part on the first set of images and the input image; using a second neural network to generate a set of grasping proposals based at least in part on the latent codes; selecting one or more grasping proposals from the set of grasping proposals based at least in part on the first neural network and the latent code; and at least one memory containing instructions to cause A system comprising:

2. The at least one memory, in response to execution by the at least one processor, and causing the robot to grasp the object based at least in part on the one or more grasping proposals. The system of claim 1 further comprising instructions.

3. The at least one memory, in response to execution by the at least one processor, using the first neural network to generate predictions of one or more of color and density based at least in part on the latent code; generating the first set of images using the predictions of at least one of color and density; The system of claim 1 , further comprising instructions to:

4. The at least one memory, in response to execution by the at least one processor, generating one or more predictions of densities associated with the set of grasping proposals using the first neural network and the latent code; selecting the one or more grasping proposals based at least in part on the one or more predictions of density; The system of claim 1 , further comprising instructions to:

5. 1. A method comprising: Obtaining an input image depicting an object; computing a latent code through one or more gradient descent processes based at least in part on a first set of images generated in association with a first neural network and the input image; using a second neural network to process at least the latent codes to generate a plurality of grasping proposals; determining one or more grasping proposals among the plurality of grasping proposals by at least using the first neural network to process the latent codes and sets of coordinates associated with the plurality of grasping proposals; A method comprising:

6. providing the one or more grasping proposals to a robot associated with an environment including the object; causing the robot to grasp the object in the environment based at least in part on an orientation indicated by the one or more grasping proposals; and The method of claim 5 further comprising:

7. calculating the set of coordinates based at least in part on the point cloud and the plurality of grasping proposals; processing at least said set of coordinates using said first neural network to calculate a set of density values; determining the one or more grasping proposals based at least in part on the set of density values; and The method of claim 5 further comprising:

8. the object in the input image is an object of a first category; The method of claim 5 , wherein the first neural network and the second neural network are trained in association with one or more images depicting objects of one or more categories.

9. determining the one or more grasping proposals based at least in part on one or more density values ​​associated with the plurality of grasping proposals and a threshold value; The method of claim 5 further comprising:

10. A non-transitory computer-readable medium that, when executed by at least one processor of a computing device, causes the computing device to determining a latent code based at least in part on the first neural network and an image depicting the object; using a second neural network to process at least the latent codes to generate a set of grasping proposals; selecting a subset of grasping proposals from the set of grasping proposals based at least in part on the first neural network and a set of coordinates associated with the set of grasping proposals; including an instruction to A non-transitory computer-readable medium, wherein a first grasping proposal of the set of grasping proposals includes at least a score and a rotation matrix.

11. When executed by at least one processor of the computing device, the computing device is provided with at least Calculating one or more coordinates of the set of coordinates by at least transforming a point cloud associated with the robot based at least in part on a grasping proposal of the set of grasping proposals.

11. The non-transitory computer readable medium of claim 10 further comprising instructions for causing the computer to:

12. When executed by at least one processor of the computing device, the computing device is provided with at least and causing the robotic part to grasp the object based at least in part on a grasping proposal of the subset of grasping proposals.

11. The non-transitory computer readable medium of claim 10, further comprising instructions to:

13. When executed by at least one processor of the computing device, the computing device is provided with at least selecting the subset of grasping proposals from the set of grasping proposals based at least in part on one or more scores indicative of a probability of a stable grasp; 11. The non-transitory computer readable medium of claim 10, further comprising instructions to:

14. When executed by at least one processor of the computing device, the computing device is provided with at least generating one or more images using the first neural network and the latent code; and updating the latent code by calculating at least a loss based at least in part on the image and the one or more images depicting the object; 11. The non-transitory computer readable medium of claim 10, further comprising instructions to:

15. When executed by at least one processor of the computing device, the computing device is provided with at least generating said set of grasping proposals using one or more graphics processing units (GPUs); 11. The non-transitory computer readable medium of claim 10, further comprising instructions to:

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