Silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of reducing hole density by extracting a current reaching a p-type base layer and suppressing injection of holes into a drift layer.SOLUTION: A silicon carbide semiconductor device 70 includes a first conductivity type silicon carbide semiconductor substrate 1, a first conductivity type first semiconductor layer 2, a second conductivity type second semiconductor layer 6, a first conductivity type first semiconductor region 7, a second conductivity type second semiconductor region 8, a second conductivity type third semiconductor region 20 having a higher impurity concentration than the second semiconductor layer 6 provided at a position opposite to the first semiconductor region 7 in the depth direction, a trench 16, a gate insulating film 9, a gate electrode 10, and a third electrode 23 provided on the surface of the second semiconductor layer 6 where the third semiconductor region 20 is not provided and making a Schottky junction with the second semiconductor layer 6.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to silicon carbide semiconductor devices. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a next-generation semiconductor material to replace silicon (Si). Compared to conventional semiconductor elements that use silicon carbide as a semiconductor material, semiconductor elements that use silicon carbide as a semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the element in the on-state to one-hundredth of that of conventional semiconductor elements that use silicon as a semiconductor material, and the ability to be used in higher temperature environments (200°C or higher). This is due to the characteristics of the material itself, namely, that the band gap of silicon is about three times larger than that of silicon, and that the dielectric breakdown field strength is nearly one order of magnitude larger than that of silicon.

[0003] Silicon carbide semiconductor devices that have been commercially available to date include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) having a planar gate structure or a trench gate structure.

[0004] The planar gate structure is a MOS gate structure in which a MOS gate is provided in a flat plate shape on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. Therefore, compared to a planar gate structure in which a channel is formed along the front surface of a semiconductor substrate, the unit cell (element constituent unit) density per unit area can be increased, and the current density per unit area can be increased, which is advantageous in terms of cost.

[0005] 17 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The structure of the conventional silicon carbide semiconductor device will be described by taking a trench MOSFET 170 as an example. In the trench MOSFET 170, n + The front surface of the silicon carbide substrate 101 is - A silicon carbide epitaxial layer 102 is deposited. - The n-type silicon carbide epitaxial layer 102 + On the surface side opposite to the silicon carbide substrate 101 side, an n-type high concentration region 105 is provided. In the n-type high concentration region 105, a first p + A mold base region 103 is optionally provided.

[0006] The MOS gate of the trench gate structure includes a p-type base layer 106, a n + Type source region 107, p + The p-type contact region 108, the trench 116, the gate insulating film 109, and the gate electrode 110 are included. + The contact region 108 may not be provided. + A silicon carbide substrate 101 and an n - The silicon carbide epitaxial layer 102 , the n-type high concentration region 105 and the p-type base layer 106 together constitute a silicon carbide semiconductor substrate 118 .

[0007] An interlayer insulating film 111 is provided on the gate electrode 110, and an n + type source region 107 and p + A source electrode 112 is provided in contact with the contact region 108. + A back surface electrode 113 serving as a drain electrode is provided on the back surface of the silicon carbide substrate 101 .

[0008] In order to adjust the threshold voltage (Vth), the trench MOSFET 170 having such a structure performs ion implantation (hereinafter referred to as channel implantation) on the portion of the p-type base layer 106 where the channel is to be formed. This forms a channel implantation portion 120 with a higher impurity concentration than the p-type base layer 106. In a MOSFET, the higher the threshold voltage, the lower the possibility of erroneous turn-on due to electromagnetic noise, etc., so this channel implantation makes it difficult for electron current to pass through, thereby raising the threshold voltage (channel inversion voltage).

[0009] Also, a semiconductor device is known that achieves faster diode switching speed, reduced low current oscillation, and reduced recovery loss without lifetime control by adjusting the carrier concentration (see, for example, Patent Document 1 below).

[0010] Also, in order to improve the avalanche resistance of a MOSFET, a semiconductor device is known in which a first stopper region having an impurity concentration of p-type impurity that is between 2 and 100 times that of the first channel region is provided adjacent to the first channel region (see, for example, Patent Document 2 below).

[0011] In addition, a semiconductor device is known that can improve the breakdown voltage of the gate insulating layer by providing a high-concentration p region in the p-well region, thereby almost completely suppressing the intrusion of equipotential lines from the drift region into the p-well region (see, for example, Patent Document 3 below). [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2014-187320 A [Patent Document 2] Patent No. 6416143 [Patent Document 3] Patent No. 6710589 Summary of the Invention [Problem to be solved by the invention]

[0013] In the conventional trench MOSFET 170, channel implantation is performed over the entire surface from the upper surface side (source electrode 12 side) of the silicon carbide semiconductor substrate 118. As a result, channel implantation is also performed in regions away from the channel, and a channel implantation portion 120 with a high impurity concentration is provided over the entire surface in the p-type base layer 106. Here, during reverse conduction, which is operated by applying a high potential to the source electrode 112, the p + The p-type contact region 108 and the n-type base layer 106 - The n-type silicon carbide epitaxial layer 102 is + A current flows in a direction toward the silicon carbide substrate 101 .

[0014] At this time, the channel implantation portion 120 makes it difficult for the electron current to penetrate the p-type base layer 106, reducing the ratio of the electron current to the total current, and increasing the amount of holes stored in the drift layer at the same current density. When the amount of holes increases in the drift layer, recombination of electrons and holes occurs more easily in the drift layer. At this time, n + If there is a defect in the crystal of the silicon carbide substrate 101, the recombination energy (3 eV) corresponding to the band gap is generated, and + Basal plane dislocations (BPDs), a type of crystal defect present in the silicon carbide substrate 101, move, and single Shockley stacking faults (1SSFs) sandwiched between two basal plane dislocations expand. When the stacking faults expand, the stacking faults make it difficult for current to flow, and the on-resistance of the MOSFET and the forward voltage of the built-in diode increase. In this way, there is a problem that bipolar degradation occurs in the trench MOSFET 170 due to the channel implantation.

[0015] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device capable of drawing out a current reaching a p-type base layer, suppressing hole injection into a drift layer, and reducing hole density. [Means for solving the problem]

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A first semiconductor region of a first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A second semiconductor region of a second conductivity type in contact with the first semiconductor region is selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate. A third semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer is provided in a position of the second semiconductor layer facing the first semiconductor region in a depth direction. A trench is provided penetrating the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer. A gate electrode is provided inside the trench via a gate insulating film. An interlayer insulating film is provided on the gate electrode. A first electrode is provided on the first semiconductor region and a surface of the first semiconductor region. A second electrode is provided on a back surface of the silicon carbide semiconductor substrate. A third electrode is provided on a surface of the second semiconductor layer where the third semiconductor region is not provided, forming a Schottky junction with the second semiconductor layer. The third electrode and the third semiconductor region do not overlap in a plan view.

[0017] Moreover, the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, further comprises a fourth semiconductor region of a second conductivity type selectively provided in a surface layer of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, and a fifth semiconductor region of a second conductivity type selectively provided at a position facing the trench in the depth direction of the first semiconductor layer, wherein the second semiconductor region and the fourth semiconductor region are provided at a position facing the third electrode in the depth direction.

[0018] In addition, in the silicon carbide semiconductor device according to the present invention described above, a width of the third electrode is wider than a distance between the fourth semiconductor region and the fifth semiconductor region.

[0019] In addition, in the silicon carbide semiconductor device according to the present invention as described above, a width of the third semiconductor region is wider than a width of the first semiconductor region.

[0020] In addition, in the silicon carbide semiconductor device according to the present invention described above, the third electrode is provided on a surface of the second semiconductor layer sandwiched between the second semiconductor regions.

[0021] According to the above-mentioned invention, the channel implantation portion is formed only in the vicinity of the sidewall of the trench in which the channel is formed. This makes it easier for the electron current to penetrate the p-type base layer (second semiconductor layer of the second conductivity type) during reverse conduction, and electrons that reach the p-type base layer can be extracted. This increases the ratio of the electron current to the total current, reduces the amount of accumulated holes at the same current density, and suppresses bipolar degradation of the silicon carbide MOSFET.

[0022] In addition, a Schottky metal (third electrode) that forms a Schottky junction with the p-type base layer is provided on the p-type base layer in the portion where channel implantation is not performed. This allows the electrode that the electron current reaches to be the Schottky metal, suppressing leakage current during reverse bias and maintaining the breakdown voltage. Effect of the Invention

[0023] ADVANTAGEOUS EFFECTS OF THE PRESENT DISCLOSURE The silicon carbide semiconductor device according to the present invention has the effect of drawing out the current reaching the p-type base layer and suppressing hole injection into the drift layer, thereby reducing the hole density. [Brief description of the drawings]

[0024] [Figure 1] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device in accordance with a first embodiment. [Diagram 2] 1 is a cross-sectional view showing an impurity profile of a conventional silicon carbide semiconductor device in which channel implantation is performed over the entire surface. [Diagram 3] FIG. 1 is a cross-sectional view showing an impurity profile of a conventional silicon carbide semiconductor device in which channel implantation is not performed. [Figure 4] 1 is a cross-sectional view showing an impurity profile of the silicon carbide semiconductor device in accordance with the first embodiment. [Diagram 5] 1 is a cross-sectional view showing an electron current path during reverse conduction in a conventional silicon carbide semiconductor device in which channel implantation is performed over the entire surface. [Figure 6] 1 is a cross-sectional view showing an electron current path during reverse conduction in a conventional silicon carbide semiconductor device not subjected to channel implantation. [Figure 7] 2 is a cross-sectional view showing an electron current path during reverse conduction in the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 8] 4 is a graph showing hole densities in drift layers of the silicon carbide semiconductor device according to the first embodiment and a conventional silicon carbide semiconductor device. [Figure 9] 4 is a graph showing the breakdown voltage of the silicon carbide semiconductor device according to the first embodiment. [Figure 10] 1 is a cross-sectional view (part 1) showing a state during manufacture of a silicon carbide semiconductor device according to a first embodiment. [Figure 11] FIG. 2 is a cross-sectional view (part 2) showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 12] 5 is a cross-sectional view (part 3) showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 13] FIG. 4 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment (part 4). [Figure 14] FIG. 5 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment (part 5). [Figure 15] FIG. 6 is a cross-sectional view showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment (part 6). [Figure 16]FIG. 11 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 17] FIG. 1 is a cross-sectional view showing a structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] A preferred embodiment of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in a layer or region prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - attached to n or p respectively mean that the impurity concentration is higher and lower than that of a layer or region not prefixed with n or p. Note that in the following description of the embodiment and the accompanying drawings, the same reference numerals are attached to similar configurations, and duplicated explanations are omitted. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before the index represents a negative index. In addition, the description of "same" or "equivalent" should include up to 5% in consideration of manufacturing variations.

[0026] (Embodiment 1) The semiconductor device according to the present invention is configured using a wide band gap semiconductor. In the first embodiment, a silicon carbide semiconductor device fabricated (manufactured) using, for example, silicon carbide (SiC) as a wide band gap semiconductor will be described by taking a trench-type MOSFET 70 as an example. Fig. 1 is a cross-sectional view showing a structure of the silicon carbide semiconductor device according to the first embodiment. Fig. 1 shows only an active region of the trench-type MOSFET 70 through which a main current flows.

[0027] As shown in FIG. 1, the silicon carbide semiconductor device according to the first embodiment has n + A first main surface (front surface) of a silicon carbide substrate (a silicon carbide semiconductor substrate of a first conductivity type) 1, for example, a (0001) surface (Si surface), is provided with an n - A silicon carbide epitaxial layer (first semiconductor layer of a first conductivity type) 2 is deposited on the semiconductor substrate.

[0028] n + The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - The silicon carbide epitaxial layer 2 is + The impurity concentration is lower than that of the n-type silicon carbide substrate 1, and is, for example, a low-concentration n-type drift layer. - The n-type silicon carbide epitaxial layer 2 + An n-type high concentration region 5 may be provided on the surface opposite to the silicon carbide substrate 1 side. + Lower n than silicon carbide substrate 1 - The n-type high concentration drift layer has an impurity concentration higher than that of silicon carbide epitaxial layer 2.

[0029] n - The n-type silicon carbide epitaxial layer 2 + On the surface opposite to the n-type silicon carbide substrate 1 side, a p-type base layer (a second semiconductor layer of a second conductivity type) 6 is provided. + A silicon carbide substrate 1 and an n - The silicon carbide epitaxial layer 2, the n-type high concentration region 5, and the p-type base layer 6 are combined to form a silicon carbide semiconductor base (semiconductor substrate made of silicon carbide) 18.

[0030] n + A drain electrode serving as a back surface electrode 13 is provided on a second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base 18) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the back surface electrode 13.

[0031] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate 18. Specifically, the trench 16 is formed in the n-type + The n-type high concentration region 5 (or the n-type high concentration region 5 when the n-type high concentration region 5 is not provided) is formed by penetrating the p-type base layer 6 from the surface opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor base 18). -The n-type silicon carbide epitaxial layer 2 (hereinafter simply referred to as (2)) is formed along the inner wall of the trench 16. A gate insulating film 9 is formed on the bottom and side walls of the trench 16, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 16. The gate electrode 10 is insulated from the n-type high concentration region 5 (2) and the p-type base layer 6 by the gate insulating film 9. A part of the gate electrode 10 may protrude from above the trench 16 (the side where a source electrode 12 described later is provided) toward the source electrode 12.

[0032] n-type high concentration region 5(2) + In the surface layer on the opposite side to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor base 18), a first p + A second p-type base region (a fourth semiconductor region of a second conductivity type) 3 is provided in the n-type high concentration region 5 (2). + A second p-type base region (a fifth semiconductor region of a second conductivity type) 4 is provided. + The second base region 4 is provided at a position facing the bottom of the trench 16 in the depth direction (the direction from the source electrode 12 to the drain electrode 13). + The width of the mold base region 4 is equal to or greater than the width of the trench 16. The bottom of the trench 16 is the second p + The p-type base region 4 may be connected to the p-type base layer 6 and the second p + It may be located within the n-type high concentration region 5 ( 2 ) sandwiched between the n-type base regions 4 .

[0033] Inside the p-type base layer 6, an n-type + A p-type source region (first semiconductor region of a first conductivity type) 7 and + A contact region (a second semiconductor region of a second conductivity type) 8 is selectively provided. + Type source region 7 and p + The mold contact regions 8 abut each other.

[0034] Here, in order to adjust the threshold voltage (Vth), ion implantation (hereinafter referred to as channel implantation) is performed on a portion where a channel is to be formed in the p-type base layer 6. As a result, a channel implantation portion (third semiconductor region of the second conductivity type) 20 having a higher impurity concentration than the p-type base layer 6 is formed.

[0035] In the first embodiment, the channel implantation is not performed in a region away from the MOS channel, but only in a shallow region near the MOS channel. Therefore, the channel implantation portion 20 is formed only near the sidewall of the trench 16 in which the channel is formed. Specifically, the channel implantation portion 20 is in contact with the sidewall of the trench 16 and is formed in a region near the sidewall of the trench 16. + The channel implantation portion 20 is provided at a position corresponding to the depth direction (direction from the source electrode 12 to the back surface electrode 13) of the type source region 7. The width w0 of the channel implantation portion 20 is n + 1. The n-type source region 7 has a width w1 larger than the n-type source region 7. + Type source region 7 and p + It is preferable that the width is narrower than the width w2 of the mold contact region 8.

[0036] Here, Fig. 2 is a cross-sectional view showing an impurity profile of a conventional silicon carbide semiconductor device in which channel implantation is performed on the entire surface, Fig. 3 is a cross-sectional view showing an impurity profile of a conventional silicon carbide semiconductor device in which channel implantation is not performed, and Fig. 4 is a cross-sectional view showing an impurity profile of the silicon carbide semiconductor device according to the first embodiment.

[0037] As shown in FIG. 2, in a conventional silicon carbide semiconductor device in which channel implantation is performed on the entire surface, a channel implantation portion 120 having a high impurity concentration is + type source region 107 and p + The n-type contact region 108 is disposed below the n-type contact region 108. As shown in FIG. + type source region 107 and p +The impurity concentration in the lower part of the n-type contact region 108 is lower than that in a conventional silicon carbide semiconductor device in which channel implantation is performed over the entire surface. + The p + The impurity concentration in the lower part of the contact region 8 is lower than that of a conventional silicon carbide semiconductor device in which channel implantation is performed over the entire surface.

[0038] In this way, by providing the channel implantation portion 20 only in the vicinity of the MOS channel, the impurity concentration of the p-type base layer 6 is reduced in the portion away from the MOS channel, making it easier for electron current to pass through. + The contact region 8 is connected to the p-type base layer 6 and the n - via the silicon carbide epitaxial layer 2 and + A current flows in a direction toward the p-type silicon carbide substrate 1. At this time, since the impurity concentration of the p-type base layer 6 is reduced in a portion away from the MOS channel, the electronic current easily passes through the p-type base layer 6, and electrons that reach the p-type base layer 6 can be extracted.

[0039] Fig. 5 is a cross-sectional view showing an electron current path during reverse conduction in a conventional silicon carbide semiconductor device in which channel implantation is performed over the entire surface. Fig. 6 is a cross-sectional view showing an electron current path during reverse conduction in a conventional silicon carbide semiconductor device in which channel implantation is not performed. Fig. 7 is a cross-sectional view showing an electron current path during reverse conduction in the silicon carbide semiconductor device according to the first embodiment.

[0040] 5 and 6, in the conventional silicon carbide semiconductor device, during reverse conduction, the region with the highest electron density (the darkly hatched region in FIG. 5 and FIG. 6) does not reach p-type base layer 106, making it difficult for the electronic current to penetrate p-type base layer 106. On the other hand, as shown in FIG 7, the region with the highest electron density (the darkly hatched region in FIG. 7) reaches p-type base layer 6, making it easier for the electronic current to penetrate p-type base layer 6 in the silicon carbide semiconductor device according to the first embodiment.

[0041] 8 is a graph showing hole densities in the drift layers of the silicon carbide semiconductor device according to the first embodiment and the conventional silicon carbide semiconductor device, in which the vertical axis represents hole density in units of / cm 3 8. The horizontal axis indicates the depth from the surface of the drift layer (the interface with the p-type base layer 6, 106) in μm. In FIG. 8, the dotted line indicates the hole density in the drift layer of a conventional silicon carbide semiconductor device in which channel implantation is performed over the entire surface, the thin line indicates the hole density in the drift layer of a conventional silicon carbide semiconductor device in which channel implantation is not performed, and the thick line indicates the hole density in the drift layer of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 8, in the silicon carbide semiconductor device according to the first embodiment, the channel implantation 20 is performed partially, so that the electron current flows vertically, the ratio of the electron current to the total current increases, and the amount of accumulated holes at the same current density can be reduced.

[0042] As described above, in the silicon carbide MOSFET according to the first embodiment, hole injection into the drift layer can be suppressed, and the occurrence of recombination of electrons and holes in the drift layer can be reduced, and the expansion of stacking faults can be suppressed, thereby suppressing bipolar degradation of the silicon carbide MOSFET.

[0043] In the first embodiment, a Schottky metal (third electrode) 23 is provided on the p-type base layer 6 in a portion where the channel implantation is not performed, and the Schottky metal 23 forms a Schottky junction with the p-type base layer 6. For example, as shown in FIG. +It is preferable to provide a Schottky metal 23 in the region between the p-type contact regions 8. + Type contact region 8 and n + Even in a configuration in which the p-type source region 7 and the p-type source region 8 are alternately provided in the depth direction of the trench 16, + It is preferable to provide a Schottky metal 23 in the region between the mold contact regions 8. The Schottky metal 23 is not necessary in all the regions between the trenches 16, and it is preferable to provide the Schottky metal 23 in at least a part of the regions between the trenches 16.

[0044] FIG. 9 is a graph showing the breakdown voltage of the silicon carbide semiconductor device according to the first embodiment. In FIG. 9, the vertical axis indicates the drain current in A. The horizontal axis indicates the drain voltage in V. FIG. 9 shows the case where the barrier height of Schottky metal 23 is 3 V (solid line in FIG. 9) and 1 V (dotted line in FIG. 9). As shown in FIG. 9, it can be seen that the breakdown voltage of the silicon carbide semiconductor device according to the first embodiment is about 1800 V. In this way, by providing Schottky metal 23, the electrode to which the electron current reaches can be made to be Schottky metal 23, and the leakage current during reverse bias can be suppressed and the breakdown voltage can be maintained.

[0045] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate 18 so as to cover the gate electrode 10 embedded in the trench 16. The source electrode 12 is connected to the n-type + The p-type source region 7 and the p-type base layer 6 are in contact with each other. + When the n-type contact region 8 is provided, the source electrode 12 is + The p-type source region 7, the p-type base layer 6 and the p + The source electrode 12 is in contact with the type contact region 8. The source electrode 12 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. A barrier metal 14 may be provided between the source electrode 12 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 12 to the gate electrode 10 side, for example.

[0046] (Method of Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment) Next, a description will be given of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figures 10 to 15 are cross-sectional views showing states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0047] First, n-type silicon carbide + A type silicon carbide substrate 1 is prepared. + A lower n-type silicon carbide layer is formed on a first main surface of the silicon carbide substrate 1 while doping the lower n-type silicon carbide layer with n-type impurities, for example, nitrogen atoms (N). - The silicon carbide epitaxial layer 2a is epitaxially grown to a thickness of, for example, about 30 μm. The state up to this point is shown in FIG.

[0048] Next, an ion implantation mask having a predetermined opening is formed, for example, from an oxide film by photolithography. Then, p-type impurities such as aluminum are implanted into the opening of the oxide film to form a lower first p-type region having a depth of about 0.5 μm. + The base region 3a and the second p + A mold base region 4 is formed.

[0049] Next, a part of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening, forming a lower n - A lower n-type high concentration region 5a having a depth of, for example, about 0.5 μm may be formed in a part of the surface region of the silicon carbide epitaxial layer 2a. The impurity concentration of the lower n-type high concentration region 5a is, for example, 1×10 17 / cm 3 The state up to this point is shown in Figure 11.

[0050] Next, the bottom n - An upper n-type epitaxial layer 2a is formed on the surface of the silicon carbide epitaxial layer 2a. The upper n-type epitaxial layer 2a is doped with n-type impurities such as nitrogen. - The upper n-type silicon carbide epitaxial layer 2b is formed to a thickness of about 0.5 μm. - The impurity concentration of the silicon carbide epitaxial layer 2b is 3×10 15 / cm 3 The lower n - The silicon carbide epitaxial layer 2a and the upper n - The silicon carbide epitaxial layer 2b is formed of n - This results in a silicon carbide epitaxial layer 2 .

[0051] Next, the top n - An ion implantation mask having a predetermined opening is formed on the surface of the silicon carbide epitaxial layer 2b by photolithography, for example, using an oxide film. Then, p-type impurities such as aluminum are implanted into the opening of the oxide film to form an upper first p-type impurity layer having a depth of about 0.5 μm. + The mold base region 3b is a lower first p + The lower portion 1p is formed so as to overlap the mold base region 3a. + The mold base region 3a and the upper portion 1p + The base region 3b forms a continuous region, and the first p + This forms the mold base region 3. + The impurity concentration of the base region 3b is set to, for example, 5×10 18 / cm 3 Set it so that it is about the same.

[0052] Next, a part of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening. - An upper n-type high concentration region 5b having a depth of, for example, about 0.5 μm may be formed in a part of the surface region of the silicon carbide epitaxial layer 2. The impurity concentration of the upper n-type high concentration region 5b is, for example, 1×10 17 / cm 3 The upper n-type heavily doped region 5b and the lower n-type heavily doped region 5a are formed so that at least a portion of them are in contact with each other to form the n-type heavily doped region 5. However, there are cases where the n-type heavily doped region 5 is formed over the entire surface of the substrate, and cases where it is formed in the active region through which the main current flows but not on the periphery of the active region. The state up to this point is shown in FIG.

[0053] Next, n -On the surface of the silicon carbide epitaxial layer 2, a p-type base layer 6 is formed by epitaxial growth to a thickness of about 1.1 μm. The impurity concentration of the p-type base layer 6 is 5×10 15 / cm 3 ~5×10 16 / cm 3 Set it to a certain extent.

[0054] Next, an ion implantation mask 21 having a predetermined opening is formed by photolithography on the surface of the p-type base layer 6. The ion implantation mask 21 is made of, for example, an oxide film. + The region where the p-type source region 7 is formed is defined as an opening. + An ion implantation mask 21 is formed on the region where the type contact region 8 and the Schottky metal 23 are to be formed. Then, p-type impurities such as aluminum are implanted 22 into the openings of the ion implantation mask 21 to form a channel implantation portion 20 inside the p-type base layer 6. This allows the channel implantation portion 20 to be provided only in the vicinity of the MOS channel. The impurity concentration of the channel implantation portion 20 is 1×10 17 / cm 3 The state up to this point is shown in FIG.

[0055] Next, a predetermined region constituting a MOS gate is formed on the first main surface layer (surface layer of the p-type base layer 6) of the silicon carbide semiconductor substrate 18. Specifically, an ion implantation mask having a predetermined opening is formed on the surface of the p-type base layer 6 by photolithography, for example, from an oxide film. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into this opening, and n-type impurities are implanted into a portion of the surface of the p-type base layer 6. + Next, the n-type source region 7 is formed. + The ion implantation mask used for forming the p-type source region 7 is removed, and a mask for ion implantation having a predetermined opening is formed in the same manner, and p-type impurities such as boron are ion-implanted into a part of the surface of the p-type base layer 6 to form p + A contact region 8 may be formed. + The impurity concentration of the p-type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6.

[0056] Next, a heat treatment (activation anneal) is performed to activate the entire region formed by ion implantation. For example, the heat treatment (anneal) is performed in an inert gas atmosphere at about 1700° C. to form the first p + Mold base region 3, second p + Type base region 4, n + Type source region 7, p + An activation process is then carried out on the mold contact region 8. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or the heat treatment may be carried out each time an ion implantation is performed. The state up to this point is shown in FIG.

[0057] Next, a trench forming mask having a predetermined opening is formed by photolithography on the surface of the p-type base layer 6, for example, using an oxide film. Next, a trench 16 is formed by dry etching, penetrating the p-type base layer 6 and reaching the n-type high concentration region 5(2). The bottom of the trench 16 is connected to the second p-type high concentration region 5(2) formed in the n-type high concentration region 5(2). + The mask may reach the mold base region 4. Next, the trench formation mask is removed. Next, the front surface of the silicon carbide semiconductor substrate 18 is subjected to, for example, RCA cleaning (wet cleaning using a strong acid and strong base solution).

[0058] Next, n + A gate insulating film 9 is formed on the surface of the source region 7 and along the bottom and sidewalls of the trench 16. First, an oxide film is deposited in the trench by a chemical reaction (chemical vapor deposition method) such as thermal oxidation or high temperature oxidation (High Temperature Oxide: HTO) at a temperature of about 1000° C. in an oxygen atmosphere.

[0059] Next, sacrificial oxidation may be performed to round the corners of the bottom of the trench and the opening of the trench. Next, annealing is performed on the oxide film. When the oxide film is formed by thermal oxidation, the interface state density at the interface between the oxide film and the semiconductor part may be reduced by heat treatment (POA (Post Oxidation Anneal) treatment). When the oxide film is formed by a deposition method such as HTO, nitrogen (N 2 For example, at a temperature of 1300°C, NO10% / N 2 The NO annealing is performed for about 30 minutes using gas. This forms the gate insulating film 9. The state up to this point is shown in FIG.

[0060] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 16. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 16 to form the gate electrode 10.

[0061] Next, for example, by physical vapor deposition (PVD) such as sputtering, a titanium film (not shown) is formed all over the surface up to the front surface of the silicon carbide semiconductor substrate 18. The thickness of the titanium film may be, for example, about 100 nm.

[0062] Next, the titanium film is sintered by heat treatment at a temperature of about 500° C. for about 10 minutes. This heat treatment forms a Schottky junction between the titanium film and the p-type base layer 6. Next, the titanium film is selectively removed by photolithography and etching to form the Schottky metal 23. Here, the Schottky metal 23 may be a metal other than Ti as long as it forms a Schottky junction with SiC, and may be formed of, for example, nickel (Ni).

[0063] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the Schottky metal 23, the gate insulating film 9, and the gate electrode 10, forming the interlayer insulating film 11. Next, a barrier metal 14 made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography. + Type source region 7 and p + A contact hole is formed exposing the mold contact region 8. Thereafter, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11.

[0064] Next, the interlayer insulating film 11 is selectively removed, and a nickel (Ni) or Ti film is formed on the surface of the silicon carbide semiconductor substrate 18. Next, the surface is protected and n + A Ni or Ti film is formed on the back side of the silicon carbide substrate 1. Next, a heat treatment at about 1000° C. is performed to bond the front side of the silicon carbide semiconductor base 18 and the n-type silicon carbide substrate 1. + An ohmic electrode is formed on the rear surface side of the silicon carbide substrate 1 .

[0065] Next, a conductive film that will become the source electrode 12 is provided on the interlayer insulating film 11 so as to contact the ohmic electrode portion formed in the contact hole, and n + Type source region 7 and p + The contact region 8 is brought into contact with a source electrode 12 .

[0066] Next, n + A back electrode 13 made of, for example, a nickel (Ni) film is formed on the second main surface of the silicon carbide substrate 1. Then, a heat treatment is performed at a temperature of, for example, about 970° C. to form an n-type silicon carbide substrate. + The silicon carbide substrate 1 and the back surface electrode 13 are connected to each other by ohmic contact.

[0067] Next, an electrode pad to become a source electrode pad (not shown) is deposited on the source electrode 12 on the front surface of the silicon carbide semiconductor substrate 18 and in the opening of the interlayer insulating film 11 by, for example, a sputtering method. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5 μm. The electrode pad may be made of, for example, aluminum containing 1% silicon (Al-Si). Next, the source electrode pad is selectively removed.

[0068] Next, for example, titanium (Ti), nickel (Ni) and gold (Au) are deposited in this order as a drain electrode pad (not shown) on the surface of the back electrode 13. In this manner, the semiconductor device shown in FIG.

[0069] As described above, according to the first embodiment, the channel implantation portion is formed only in the vicinity of the sidewall of the trench in which the channel is formed. This makes it easier for the electron current to penetrate the p-type base layer during reverse conduction, and electrons that reach the p-type base layer can be extracted. This increases the ratio of the electron current to the total current, reduces the amount of accumulated holes at the same current density, and suppresses bipolar degradation of the silicon carbide MOSFET.

[0070] In addition, a Schottky metal that forms a Schottky junction with the p-type base layer is provided on the p-type base layer in the portion where channel implantation is not performed. This allows the electrode that the electron current reaches to be the Schottky metal, suppressing the leakage current during reverse bias and maintaining the breakdown voltage.

[0071] (Embodiment 2) 16 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to the second embodiment. As shown in FIG. 16, in the silicon carbide semiconductor device according to the second embodiment, a Schottky portion p + The contact region 8a and the Schottky portion 1p + This differs from the silicon carbide semiconductor device according to the first embodiment in that a type base region 3c is provided.

[0072] Schottky part + The p-type contact region 8a is provided in the surface layer of the p-type base layer 6 and has a Schottky portion 1p + The Schottky portion p + The contact region 8a and the Schottky portion 1p + By providing the type base region 3c, the electric field strength can be reduced even in the region below the Schottky metal 23, and application of a high electric field to the gate insulating film 9 along the bottom surface of the trench 18 can be prevented.

[0073] In addition, if the width d1 of the Schottky metal 23 is large, the electric field becomes high in the region below the Schottky metal 23. + The base region 3c and the Schottky portion p + For example, the width d1 of the Schottky metal 23 is set to be smaller than the first p + Type base region 3 and second p + When the distance between the first Schottky portion and the base region 4 is greater than the distance d2, + The base region 3c and the Schottky portion p + It is preferred to provide a mold contact region 8a.

[0074] In addition, the silicon carbide semiconductor device according to the second embodiment includes a first p + Type base region 3 and p + In the same manner as in the contact region 8, the Schottky portion 1p + The base region 3c and the Schottky portion p + By forming the contact region 8a, the silicon carbide semiconductor device can be manufactured in a manner similar to that of the first embodiment.

[0075] As described above, according to the second embodiment, the Schottky portion p is provided at a position corresponding to the depth direction of the Schottky metal. + Type contact region and Schottky portion 1p +The base region is provided so that the electric field strength can be reduced even in the region below the Schottky metal, and it is possible to prevent a high electric field from being applied to the gate insulating film along the bottom surface of the trench.

[0076] In the above, the present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-mentioned embodiments, for example, the dimensions and impurity concentrations of each part are variously set according to the required specifications, etc. Also, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is similarly valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0077] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and automobile igniters. [Explanation of symbols]

[0078] 1, 101 n + Silicon carbide substrate 2, 102 n - Silicon carbide epitaxial layer 2a bottom n - Silicon carbide epitaxial layer 2b top n - Silicon carbide epitaxial layer 3, 103 1st p. + Type-based regions 3a Lower 1st p. + Type-based regions 3b Upper 1st p. + Type-based regions 3c Schottky part 1p + Type-based regions 4, 104 2nd p. + Type-based regions 5, 105 n-type high concentration region 5a Lower n-type high concentration region 5b Upper n-type high concentration region 6, 106 p-type base layer 7, 107 n + Type Source Area 8, 108 p. + Mold Contact Area 8a Schottky part p + Mold Contact Area 9, 109 Gate insulating film 10, 110 Gate electrode 11, 111 Interlayer insulating film 12, 112 Source electrode 13, 113 Back electrode 16, 116 Trench 18, 118 Silicon carbide semiconductor substrate 20, 120 channel implantation section 21 Ion implantation mask 22 Injection 23 Schottky Metal 70, 170 Trench MOSFET

Claims

1. a first conductivity type silicon carbide semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a second semiconductor layer of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type selectively provided in a surface layer of the second semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a second semiconductor region of a second conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side and in contact with the first semiconductor region; a third semiconductor region of a second conductivity type having a higher impurity concentration than the second semiconductor layer, the third semiconductor region being provided at a position facing the first semiconductor region of the second semiconductor layer in a depth direction; a trench passing through the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer; a gate electrode provided inside the trench via a gate insulating film; an interlayer insulating film provided on the gate electrode; a first electrode provided on the first semiconductor region and a surface of the first semiconductor region; A second electrode provided on a back surface of the silicon carbide semiconductor substrate; a third electrode provided on a surface of the second semiconductor layer where the third semiconductor region is not provided, the third electrode forming a Schottky junction with the second semiconductor layer; Equipped with the third electrode and the third semiconductor region do not overlap in a plan view.

2. a fourth semiconductor region of a second conductivity type selectively provided in a surface layer of the first semiconductor layer on a side opposite to the silicon carbide semiconductor substrate; a fifth semiconductor region of a second conductivity type selectively provided at a position facing the trench in a depth direction of the first semiconductor layer; Equipped with The silicon carbide semiconductor device according to claim 1 , wherein the second semiconductor region and the fourth semiconductor region are provided at positions opposing the third electrode in a depth direction.

3. 3 . The silicon carbide semiconductor device according to claim 2 , wherein a width of the third electrode is greater than a distance between the fourth semiconductor region and the fifth semiconductor region.

4. 4. The silicon carbide semiconductor device according to claim 1, wherein a width of the third semiconductor region is wider than a width of the first semiconductor region.

5. 5. The silicon carbide semiconductor device according to claim 1, wherein the third electrode is provided on a surface of the second semiconductor layer sandwiched between the second semiconductor regions.

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