Semiconductor Device

Abstract

To provide a semiconductor device capable of mitigating electric field concentration applied to an end part of a gate electrode and thereby suppressing reduction in withstanding voltage by including a Schottky barrier diode with a trench structure.SOLUTION: In a semiconductor device, an anode electrode is buried in a groove formed in a drift region and electrically connected with a source electrode, forming a Schottky junction with the drift region and configuring a unipolar-type diode with the drift region. A distance between the anode electrode and an end part closest to the anode electrode among end parts of a planar part included in a gate electrode is smaller than a distance between the end part and a well region adjacent to the drift region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A SiC power MISFET is known that includes a Schottky barrier diode consisting of a Schottky junction between an n-type current diffusion layer and a JFET (junction field effect transistor) region and a metal layer (see Patent Document 1). In a SiC power MISFET that includes a gate electrode embedded in a trench via a gate insulating film, the reliability and performance are improved by having a metal layer that forms a Schottky junction with the upper surface of an N-type current diffusion layer adjacent to the trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-125760 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, when a gate-off voltage is applied to the gate electrode to turn off the SiC power MISFET, the electric field is most intense at the end of the gate electrode, which makes the electric field more likely to concentrate, lowering the withstand voltage at that location and possibly destroying the gate insulating film.

[0005] The present invention has been made in consideration of the above-mentioned circumstances, and has an object to provide a semiconductor device in which a Schottky barrier diode has a trench structure, thereby alleviating electric field concentration at the end of a gate electrode and suppressing a decrease in breakdown voltage. [Means for solving the problem]

[0006] In order to achieve the above object, in a semiconductor device according to one aspect of the present invention, an anode electrode is embedded in a groove formed in the drift region, is electrically connected to the source electrode, forms a Schottky junction with the drift region, and forms a unipolar diode with the drift region, and a distance between the anode electrode and an end of a planar portion of a gate electrode that is closest to the anode electrode is smaller than a distance between the end and a well region adjacent to the drift region. Effect of the Invention

[0007] According to one aspect of the present invention, a semiconductor device can be provided in which a Schottky barrier diode has a trench structure, thereby alleviating electric field concentration at an end of a gate electrode and suppressing a decrease in breakdown voltage. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to this embodiment. [Diagram 2] 2A to 2C are cross-sectional views (part 1) illustrating steps of a method for manufacturing the semiconductor device shown in FIG. [Diagram 3] 3A to 3C are cross-sectional views (part 2) illustrating steps of the method for manufacturing the semiconductor device shown in FIG. [Figure 4] 4A to 4C are cross-sectional views (part 3) illustrating steps of the method for manufacturing the semiconductor device shown in FIG. [Figure 5A] FIG. 5A is a schematic overhead view showing the configuration of another semiconductor device according to this embodiment, and is an overhead view with the upper surface of the gate electrode 4 as the reference. [Figure 5B] FIG. 5B is a cross-sectional view taken along the line AA shown in FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view taken along line BB shown in FIG. 5A. [Figure 5D] FIG. 5D is a cross-sectional view taken along line CC shown in FIG. 5A. [Figure 6] FIG. 6 is a cross-sectional view (part 1) showing a process of a method for manufacturing the semiconductor device shown in FIG. 5B and FIG. 5C. [Figure 7] FIG. 7 is a cross-sectional view (part 2) showing the steps of the method for manufacturing the semiconductor device shown in FIGS. 5B and 5C. [Figure 8A] FIG. 8A is a cross-sectional view (part 3) showing a process of the method for manufacturing the semiconductor device shown in FIG. 5B. [Figure 8B] FIG. 8B is a cross-sectional view (part 3) showing a process of the method for manufacturing the semiconductor device shown in FIG. 5C. [Figure 9A] FIG. 9A is a cross-sectional view (part 4) showing a process of the method for manufacturing the semiconductor device shown in FIG. 5B. [Figure 9B] FIG. 9B is a cross-sectional view (part 4) showing a process of the method for manufacturing the semiconductor device shown in FIG. 5C. [Figure 10A] FIG. 10A is a cross-sectional view (part 5) showing a process of the method for manufacturing the semiconductor device shown in FIG. 5B. [Figure 10B] FIG. 10B is a cross-sectional view (part 5) showing a process of the method for manufacturing the semiconductor device shown in FIG. 5C. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. In the description of the drawings, the same parts are given the same reference numerals and the description will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, and the like include parts that differ from the actual ones. In addition, there are parts where the dimensional relationships and ratios differ between the drawings.

[0010] In addition, in this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables transmission and reception of an electrical signal between the connection objects. For example, "something having some electrical action" includes an electrode, a wiring, a switching element, a resistive element, an inductor, a capacitive element, and other elements having various functions.

[0011] (First embodiment) The configuration of the semiconductor device according to this embodiment will be described with reference to FIG. 1. The semiconductor device according to this embodiment includes a substrate 1. The substrate 1 has a main surface 1A and a main surface 1B opposite to the main surface 1A. Inside the substrate 1, a drift region 5 of a first conductivity type, part of which is exposed to the main surface 1A, a well region 6 of a second conductivity type adjacent to the drift region 5 and part of which is exposed to the main surface 1A, and a drain region 8 of a first conductivity type, part of which is exposed to the main surface 1B, are formed. Inside the well region 6, a source region 7 of a first conductivity type, part of which is exposed to the main surface 1A, is formed. The first conductivity type and the second conductivity type are mutually different conductivity types. That is, if the first conductivity type is P type, the second conductivity type is N type, and if the first conductivity type is N type, the second conductivity type is P type. Below, a case where the first conductivity type is N type and the second conductivity type is P type will be described.

[0012] A groove 9 is formed in the drift region 5, and an anode electrode 10 is embedded in the groove 9. The anode electrode 10 is electrically connected to a source electrode 11, forms a Schottky junction with the drift region 5, and forms a unipolar diode with the drift region 5. The source electrode 11 is in ohmic contact with the source region 7 and the well region 6. The drain electrode 12 is in ohmic contact with the drain region 8. Since the source electrode 11 and the drain electrode 12 are formed on different main surfaces of the substrate 1, the distance between the source electrode 11 and the drain electrode 12 is increased, and the breakdown voltage between the source electrode 11 and the drain electrode 12 is improved.

[0013] Further, a trench 2 is formed across the source region 7, the well region 6, and the drift region 5, and a part of the gate insulating film 3 and a part of the gate electrode 4 may be embedded in the trench 2. That is, the gate electrode 4 is in contact with the source region 7, the well region 6, and the drift region 5 via the gate insulating film 3. The gate insulating film 3 and the gate electrode 4 may be covered with an interlayer insulating film 13. In this way, a channel is formed on the side surface of the trench 2, and the channel width can be expanded, and the channel resistance can be reduced.

[0014] The gate electrode 4 has a planar portion 16 disposed above the main surface 1A. The surface of the planar portion 16 does not have to be completely flat. The distance between the end 17 of the planar portion 16 closest to the anode electrode 10 and the anode electrode 10 is preferably smaller than the distance between the end 17 and the well region 6, and also smaller than X represented by the following formula. In this specification and the like, the term "end" refers to the part furthest from the center of the patterned object in each single direction.

[0015]

number

[0016] In the above equation, q is the elementary charge [C], N is the impurity concentration in the drift region [ / cm 3 ], ε s is the dielectric constant of the drift region [F / m], V bi is the built-in potential between the drift region and the anode electrode [eV], V dsmax represents the maximum applied voltage between the source electrode and the drift electrode [eV]. X represents the width of the depletion layer that spreads between the anode electrode and the drift region when the maximum applied voltage is applied between the source electrode and the drift electrode.

[0017] 1, by making the distance between end 17 and anode electrode 10 smaller than the distance between end 17 and well region 6, the interface between anode electrode 10 and drift region 5 becomes closer to end 17 than the interface between well region 6 and drift region 5, so that the depletion layer extending from anode electrode 10 mitigates the electric field concentration that occurs at end 17 when a voltage is applied in the reverse direction of the built-in diode, improving the breakdown voltage between drain electrode 12 and gate electrode 4. As a result, a semiconductor device with good breakdown voltage can be obtained.

[0018] Furthermore, by making the distance between the end 17 and the anode electrode 10 smaller than X in the above formula, the end 17 is placed inside the depletion layer, and the electric field concentration generated at the end 17 is alleviated by the depletion layer, which is preferable because it improves the withstand voltage between the drain electrode 12 and the gate electrode 4.

[0019] If the depth of groove 9 is shallower than the depth of well region 6, the depth of anode electrode 10 is shallower than the depth of well region 6. Therefore, when a voltage is applied in the reverse direction of the built-in diode, a depletion layer extending from the interface between well region 6 and drift region 5 covers the end portion of anode electrode 10 in the depth direction, thereby mitigating electric field concentration at the end portion of anode electrode 10 in the depth direction in the electric field generated between drain region 8 and anode electrode 10. This is preferable because it improves the withstand voltage between drain electrode 12 and anode electrode 10.

[0020] Furthermore, if the depth of groove 2 is shallower than the depth of groove 9, when a voltage is applied in the reverse direction to the built-in diode, a depletion layer extending from anode electrode 10 covers the end portion of gate electrode 4 in the depth direction, thereby alleviating electric field concentration at the end portion and improving the breakdown voltage between drain electrode 12 and gate electrode 4, which is preferable.

[0021] Furthermore, the anode electrode 10 is formed shallower than the depth of the drift region 5, so that a current flows through the drift region 5 directly below the anode electrode 10. An electric field relaxation region 14 of the second conductivity type may be formed at the bottom of the anode electrode 10. The electric field relaxation region 14 is preferable because it can relax the electric field concentration at the end of the anode electrode 10 in the depth direction in the electric field generated between the drain electrode 12 and the anode electrode 10, and improve the withstand voltage between the drain electrode 12 and the anode electrode 10.

[0022] Next, an example of a basic operation of the semiconductor device according to this embodiment will be described.

[0023] 1 functions as a transistor by controlling the potential of the gate electrode 4 with a positive potential applied to the drain electrode 12 with the potential of the source electrode 11 taken as a reference. That is, when the voltage between the gate electrode 4 and the source electrode 11 is made equal to or higher than a predetermined threshold voltage, an inversion layer is formed in the channel portion of the well region 6 on the side of the gate electrode 4, turning the device into an on-state and allowing a current to flow from the drain electrode 12 to the source electrode 11. At this time, by forming the gate electrode 4 so as to be embedded inside the trench 2, an inversion layer is also formed on the side of the trench 2, making it possible to reduce the channel resistance.

[0024] On the other hand, when the voltage between the gate electrode 4 and the source electrode 11 is reduced to a predetermined threshold voltage or less, the inversion layer disappears, the device enters an off state, and the current is cut off.

[0025] The operation (current flow) of the semiconductor device according to this embodiment when it is off will be described. When a positive voltage is applied to the source electrode 11 and a negative voltage is applied to the drain electrode 12 (when the MOSFET is off), a depletion layer extends from the pn interface between the well region 6 and the drift region 5 and the interface between the anode electrode 10 and the drift region 5. At this time, an electric field is generated in the gate insulating film 3 due to the potential difference between the drain electrode 12 and the gate electrode 4, and the electric field is concentrated at the end of the gate insulating film 3 on the drift region 5. When the end of the gate insulating film 3 is close to the interface between the well region 6 and the drift region 5, the depletion layer extending from the pn interface can alleviate the electric field concentration, but in this case, the current resistance between the channel and the drift region 5 during the on operation becomes large. By bringing the end 17 of the planar portion 16 of the gate electrode 4 close to the anode electrode 10, which is sufficiently away from the pn interface, the electric field concentration at the end 17 can be alleviated without increasing the electric resistance. Since the anode electrode 10 is formed in a groove shape near the end 17 toward the drain region 8, the electric field relaxation effect is greater than when the anode electrode 10 is formed on the surface. In addition, by making the distance between the end 17 and the anode electrode 10 smaller than the above-mentioned X, the electric field relaxation effect can be increased.

[0026] Furthermore, the depth of the groove 2 in which the gate electrode 4 is embedded is formed shallower than the depth of the well region 6, and compared to a case in which the groove 2 is formed deeper than the well region 6, the electric field concentration at the bottom of the gate electrode 4 resulting from the potential difference between the drain electrode 12 and the gate electrode 4 is alleviated, improving the breakdown voltage. Furthermore, the electric field relaxation region 14 formed so as to cover the bottom of the anode electrode 10 is a region doped with a P-type impurity different from that of the drift region 5, and when a negative voltage is applied to the anode electrode 10 and a positive voltage is applied to the drain electrode 12, a depletion layer spreads between the electric field relaxation region 14 and the drift region 5. This relieves the electric field concentration at the bottom of the anode electrode 10, improving the breakdown voltage.

[0027] Furthermore, when the semiconductor device according to this embodiment is on, a current flows from the source electrode 11 side to the drain electrode 12 side via the parasitic Schottky diode formed on the side wall of the trench 2, not via the parasitic pn diode formed by the well region 6 and the drift region 5. That is, when the semiconductor device is on, only the parasitic Schottky diode of the body diode formed in the substrate 1 operates, and the parasitic pn diode does not operate. Therefore, deterioration over time caused by the parasitic pn diode being on and operating as a bipolar transistor does not occur.

[0028] Next, an example of a method for manufacturing a semiconductor device according to this embodiment will be described with reference to the drawings.

[0029] First, a substrate 1 to which an N-type impurity is highly doped is prepared. Next, as shown in FIG. 2, an N-type drift region 5 is formed by epitaxial growth. The impurity concentration of the drift region 5 is, for example, 1×10 15 / cm 3 ~1×10 19 / cm 3 When drift region 5 is formed, a region of substrate 1 to which N-type impurities are added at a higher concentration than drift region 5 (a region on main surface 1B side of substrate 1) becomes drain region 8.

[0030] A semi-insulating substrate or an insulating substrate can be used for the substrate 1. This can reduce leakage current from the main surface 1A to the main surface 1B. Here, a semi-insulating substrate refers to a substrate having a resistivity of several kΩ·cm or more.

[0031] For example, a silicon carbide substrate (SiC substrate) can be used for the substrate 1. SiC is a wide band gap semiconductor and has a small number of intrinsic carriers, so that it is easy to obtain high insulation properties and a semiconductor device with high withstand voltage can be realized. There are several polytypes (crystal polymorphism) of SiC, and a typical 4H SiC substrate can be used for the substrate 1. By using a SiC substrate for the substrate 1, the insulation properties and thermal conductivity of the substrate 1 can be increased. By using a wide band gap SiC substrate, the withstand voltage between the drain electrode 12 and the source 11 is improved.

[0032] Furthermore, the substrate 1 is not limited to a SiC substrate, and may be a semiconductor substrate made of a semiconductor material having a wide band gap, such as GaN, diamond, ZnO, or AlGaN.

[0033] Next, the mask material formed on the main surface 1A of the substrate 1 is patterned, and a P-type well region 6 and a high-concentration N-type source region 7 are formed inside the substrate 1 by ion implantation. At this time, the impurity concentrations of the drift region 5 and the well region 6 are, for example, 1×10 15 / cm 3 ~1×10 19 / cm 3 A typical mask material is silicon oxide film, and a deposition method can be thermal CVD or plasma CVD. A patterning method can be photolithography.

[0034] In this embodiment, for example, nitrogen (N) can be used as the N-type impurity, and for example, aluminum (Al) or boron (B) can be used as the P-type impurity. By implanting ions while the substrate 1 is heated to a temperature of about 600° C., it is possible to suppress the occurrence of crystal defects in the ion-implanted region.

[0035] The implanted impurities can be activated by heat treatment, for example at about 1700° C. in an argon or nitrogen atmosphere.

[0036] Next, as shown in FIG. 3, the source region 7, the well region 6, and the drift region 5 are etched using a mask material formed on the main surface 1A of the substrate 1 to form a groove 2. As an etching method, for example, wet etching using hydrofluoric acid or dry etching such as reactive ion etching is used. Next, a gate insulating film 3 and a gate electrode 4 are formed so as to be embedded in the groove 2. The gate electrode 4 is in contact with the source region 7, the well region 6, and the drift region 5 via the gate insulating film 3. The gate insulating film 3 can be formed by, for example, a thermal oxidation method or a deposition method. As an example, in the case of thermal oxidation, a silicon oxide film is formed in all parts of the substrate 1 that are in contact with oxygen by heating the substrate 1 to about 1100° C. in an oxygen atmosphere.

[0037] After the gate insulating film 3 is formed, annealing may be performed at about 1000°C in an atmosphere of nitrogen, argon, N2O, or the like in order to reduce the interface state at the interface between the well region 6 and the gate insulating film 3. Direct thermal oxidation in an NO or N2O atmosphere is also possible. In this case, the temperature is preferably 1100°C to 1400°C. The thickness of the gate insulating film 3 is about several tens of nm.

[0038] The gate electrode 4 is formed by being deposited inside the trench 2. The material of the gate electrode 4 may be, for example, polysilicon. In this embodiment, a case where a polysilicon film is used for the gate electrode 4 will be described. A low pressure CVD method or the like may be used as a method for depositing the polysilicon film. For example, the thickness of the polysilicon film to be deposited is set to a value greater than half the width of the trench 2, and the trench 2 is completely filled with the polysilicon film. Since the polysilicon film is formed from the inner wall surface of the trench 2, the trench 2 can be filled with the polysilicon film by setting the thickness of the polysilicon film as described above. For example, when the width of the trench 2 is 2 μm, the polysilicon film is formed so that the film thickness is greater than 1 μm. In addition, after the polysilicon film is deposited, an annealing process is performed at 950° C. in phosphorus oxychloride (POCl3) to form an N-type polysilicon film, which gives conductivity to the gate electrode 4.

[0039] Next, as shown in FIG. 4, the interlayer insulating film 13 is formed. For example, a silicon oxide film can be used as the interlayer insulating film 13. The silicon oxide film can be deposited by a thermal CVD method or a plasma CVD method. Alternatively, a silicon nitride film can be used as the interlayer insulating film 13.

[0040] Next, using the patterned resist material 15 as a mask, the interlayer insulating film 13 is etched to expose the drift region 5 (main surface 1A), and the drift region 5 (main surface 1A) is further etched to form the groove 9. The description of the groove 2 can be used as the etching method.

[0041] Next, a contact is formed as an interface between the anode electrode 10 and the drift region 5. A metal material that will become the anode electrode 10 is deposited on the main surface 1A of the substrate 1. The metal material is deposited on the main surface 1A while leaving the resist material 15 used for etching the interlayer insulating film 13. Next, the substrate 1 is immersed in, for example, acetone, and a lift-off process is performed to remove the metal material on the resist material 15 together with the resist material 15. For the anode electrode 10, for example, titanium, molybdenum, nickel, etc. can be used. Then, a contact of the source electrode 11 is formed by patterning with the resist material 15 and dry etching. Next, a metal material made of, for example, aluminum is deposited on the main surface 1A so as to fill the inside of the groove 9 and the contact of the source electrode 11, and the anode electrode 10 and the source electrode 11 are formed by patterning. The metal material may be titanium, nickel, or molybdenum. A laminated film such as titanium / nickel / silver (Ti / Ni / Ag) may be used for the anode electrode 10 and the source electrode 11. Next, the drain electrode 12 is formed on the main surface 1B of the substrate 1. For the drain electrode 12, the material used for the source electrode 11 can be used.

[0042] Through the above steps, the semiconductor device shown in FIG. 1 can be manufactured.

[0043] Second embodiment The configuration of the semiconductor device according to this embodiment will be described with reference to Fig. 5 (Figs. 5A to 5D). Fig. 5A is an overhead view based on the upper surface of the gate electrode 4. Fig. 5B is a cross-sectional view taken along line AA shown in Fig. 5A. Fig. 5C is a cross-sectional view taken along line BB shown in Fig. 5A. Fig. 5D is a cross-sectional view taken along line CC shown in Fig. 5A. In this embodiment, the above description is used for points common to the first embodiment, and differences will be described below.

[0044] The semiconductor device according to this embodiment includes a substrate 1. The substrate 1 has a main surface 1A. Formed inside the substrate 1 are a first conductivity type drift region 5 partially exposed to the main surface 1A, a second conductivity type well region 6 adjacent to the drift region 5 and partially exposed to the main surface 1A, and a first conductivity type drain region 8 partially exposed to the main surface 1A. Formed inside the well region 6 is a first conductivity type source region 7 partially exposed to the main surface 1A.

[0045] Since the source electrode 11 and the drain electrode 12 are formed on the main surface 1A of the substrate 1, it is not necessary to form electrodes on other main surfaces, and the electrode extraction structure in the semiconductor device can be simplified.

[0046] Furthermore, when the anode electrode 10 is made of a material, such as polysilicon, that has heat resistance to the heat treatment that is performed when the gate electrode 4 is formed in a later step, it is preferable that the end 17 of the planar portion 16 of the gate electrode 4 is located directly above the anode electrode 10 via the gate insulating film 3, since this prevents electric field concentration resulting from the potential difference between the drain electrode 12 and the gate electrode 4. Furthermore, the use of the anode electrode 10 or gate electrode 4 made of polysilicon improves the embedding (coverage) ability into the trench 2 or trench 9, making it possible to suppress deterioration in yield due to poor embedding into the trench.

[0047] If the depth of the groove 2 is deeper than the depth of the well region 6, the depth of the gate electrode 4 is deeper than the depth of the well region 6, and therefore the end of the gate electrode 4 in the depth direction is covered with a semi-insulating region (semi-insulating substrate), which alleviates electric field concentration at the end of the gate electrode 4 in the depth direction and improves the breakdown voltage between the drain electrode 12 and the gate electrode 4, which is preferable.

[0048] The well region 6 is formed deeper than the drift region 5, and electric field concentration at the end of the substrate 1 in the depth direction can be alleviated when a voltage is applied in the reverse direction to the built-in diode.

[0049] Next, an example of a basic operation of the semiconductor device according to this embodiment will be described.

[0050] The operation (current flow) of the semiconductor device according to this embodiment when it is off will be described. When a positive voltage is applied to the source electrode 11 and a negative voltage is applied to the drain electrode 12 (when the MOSFET is off), a depletion layer extends from the pn interface between the well region 6 and the drift region 5 and the interface between the anode electrode 10 and the drift region 5. At this time, an electric field is generated in the gate insulating film 3 due to the potential difference between the drain electrode 12 and the gate electrode 4. However, since the end 17 of the planar portion 16 of the gate electrode 4 is directly above the anode electrode 10 via the gate insulating film 3, no electric field concentration occurs and the breakdown voltage is improved. The description of the first embodiment can be used to explain the semiconductor device according to this embodiment when it is on.

[0051] Next, an example of a method for manufacturing a semiconductor device according to this embodiment will be described with reference to the drawings.

[0052] First, a low-impurity-concentration substrate 1 is prepared. Next, as shown in Fig. 6, a mask material formed on a main surface 1A of the substrate 1 is patterned, and a P-type well region 6, an N-type drift region 5, a high-concentration N-type source region 7, and a high-concentration N-type source region 8 are formed inside the substrate 1 by ion implantation.

[0053] 7, a mask material formed on the main surface 1A of the substrate 1 is used to etch the drift region 5 to form a groove 9. Next, an anode electrode 10 made of a material having heat resistance against a heat treatment when forming the gate electrode 4 formed in a later step, such as polysilicon, is formed inside the groove 9. In this embodiment, a case where a polysilicon film is used for the anode electrode 10 will be described. The description of the gate electrode 4 in the first embodiment can be used for the method of depositing the polysilicon film, etc.

[0054] Next, the polysilicon film on the main surface 1A of the substrate 1 is removed by anisotropic etching so that the polysilicon film remains only inside the grooves 9.

[0055] 8A and 8B, the source region 7, the well region 6, and the drift region 5 are etched using a mask material formed on the main surface 1A of the substrate 1 to form a trench 2. Next, a gate insulating film 3 and a gate electrode 4 are formed so as to be embedded in the trench 2. The description of the first embodiment can be applied to the method of forming the trench 2, the gate insulating film 3, and the gate electrode 4, etc.

[0056] 9A and 9B, the gate insulating film 3 and the gate electrode 4 are patterned by dry etching using a mask material formed on the gate electrode 4. An end 17 of a planar portion 16 of the gate electrode 4 is located directly above the anode electrode 10 with the gate insulating film 3 interposed therebetween.

[0057] 10A and 10B, an interlayer insulating film 13 is formed. Next, using a patterned resist material 15 as a mask, the interlayer insulating film 13 is etched to form contact holes for connecting the source region 7, the anode electrode 10, and the drain region 8 to each electrode.

[0058] Next, with the resist material 15 remaining, a metal material is deposited on the main surface 1A and patterned to form the source electrode 1 and the drain electrode 12. The source electrode 11 is electrically connected to the anode electrode 10 via a contact hole.

[0059] Through the above steps, the semiconductor device shown in FIG. 5 can be manufactured.

[0060] According to the above-described embodiment, the anode electrode is embedded in a groove formed in the drift region, and the distance between the anode electrode and an end of the planar portion of the gate electrode that is closest to the anode electrode is made smaller than the distance between the end and the well region adjacent to the drift region. This makes it possible to alleviate electric field concentration that occurs at the end when a voltage is applied in the reverse direction of the built-in diode, by the depletion layer extending from the anode electrode, and to improve the breakdown voltage of the semiconductor device.

[0061] (Other embodiments) The above-described embodiment is an example of a form for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and it goes without saying that various modifications are possible depending on the design and the like, even if the embodiment is other than the above, as long as the modifications do not deviate from the technical idea of ​​the present invention.

[0062] Thus, it goes without saying that the present invention includes various embodiments that are not described here. [Explanation of symbols]

[0063] 1 Board 1A, 1B main surface 2, 9 grooves 3. Gate insulating film 4. Gate electrode 5. Drift Region 6 Well Area 7 Source Area 8 Drain Region 10 Anode electrode 11 Source electrode 12 Drain electrode 13 Interlayer insulating film 14 Charge relaxation region 15 Resist material 16 Planar section 17 End

Claims

1. a substrate having a first main surface and a second main surface opposite to the first main surface; a drift region of a first conductivity type formed inside the substrate and partly exposed to the first main surface; a well region of a second conductivity type formed adjacent to the drift region inside the substrate and a portion of the well region exposed to the first main surface; a first conductivity type source region formed within the well region and a portion of the source region exposed to the first main surface; a source electrode in ohmic contact with the source region; a drain region of a first conductivity type formed within the substrate adjacent to the drift region; a drain electrode in ohmic contact with the drain region; a gate electrode in contact with the source region, the well region, and the drift region via an insulating film; an anode electrode embedded in a first groove formed in the drift region from the first main surface, the anode electrode being electrically connected to the source electrode, forming a Schottky junction with the drift region, and forming a unipolar diode with the drift region; the gate electrode has a planar portion disposed above the first major surface; a distance between the end of the planar portion closest to the anode electrode and the anode electrode is smaller than a distance between the end and the well region; Semiconductor device.

2. the gate electrode is embedded in a second trench formed in the source region, the well region, and the drift region from the first main surface through the insulating film; The semiconductor device according to claim 1 .

3. The substrate is conductive, the drain electrode is formed on the second principal surface; The semiconductor device according to claim 1 .

4. The depth of the first trench is shallower than the depth of the well region. The semiconductor device according to any one of claims 1 to 3.

5. The depth of the second groove is shallower than the depth of the first groove. The semiconductor device according to claim 2 .

6. an electric field relaxation region formed in the drift region facing a bottom of the first trench; The semiconductor device according to any one of claims 1 to 5.

7. A portion of the drain region is exposed to the first main surface of the substrate. The semiconductor device according to claim 1 .

8. the anode electrode is made of polysilicon, the end is above the anode electrode; The semiconductor device according to claim 1 , 2 , or 7 .

9. The depth of the second trench is greater than the depth of the well region. The semiconductor device according to claim 2 .

10. The distance between the end and the first groove is smaller than X defined by the following formula: The semiconductor device according to any one of claims 1 to 9. [0010] (In the above formula, q is an elementary charge. [C], N is the impurity concentration in the drift region [ / cm ３ ], εs is the dielectric constant of the drift region [F / m], Vbi is the built-in potential generated between the drift region and the anode electrode [eV], V ｄｓｍａｘ represents the maximum applied voltage [eV] between the source electrode and the drift region.)

11. The substrate is a semi-insulating substrate or an insulating substrate; The semiconductor device according to any one of claims 1 to 10.

12. The substrate is made of silicon carbide. The semiconductor device according to any one of claims 1 to 11.

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