Multilayer Ceramic Capacitor

Abstract

To prevent the deterioration of electric field characteristics due to cross talk.SOLUTION: According to an embodiment of the present invention, a multilayer ceramic capacitor includes: a body including a dielectric layer and first and second internal electrodes with different sizes to each other, and having first and second surfaces opposing each other in a stacking direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces, and opposing each other; and first and second external electrodes in contact with the first and second internal electrodes on the fifth surface and the sixth surface of the body, respectively. A ratio (a / b) of a margin (a) of the second internal electrode in a longitudinal direction to a margin (b) of the first internal electrode in the longitudinal direction is 0.33 or more and 0.67 or less, or a ratio (c / d) of a margin (c) of the second internal electrode in a width direction to a margin (d) of the first internal electrode in the width direction is 0.33 or more and 0.67 or less, and an average thickness of the first and second internal electrodes is 0.4 μm or less.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Multi-layer ceramic capacitors (MLCCs) are passive components that control electrical signals in circuits. Multi-layer ceramic capacitors mainly store electric charges in their electrodes and act as filters that block direct current (DC) signals and pass alternating current (AC) signals. In other words, multi-layer ceramic capacitors can be said to play a role in stabilizing IC operation by diverting and removing AC noise from power lines.

[0003] In such MLCC devices, the closer the electromagnetic distance between each layer, the more likely it is that crosstalk will cause degradation of characteristics. In particular, compared to simply connecting individual devices in parallel, using a single merged chip increases the possibility of degradation of electric field characteristics. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to prevent degradation of electric field characteristics due to crosstalk.

[0005] Another object of the present invention is to minimize the effects of fringe electric fields on the internal electrodes.

[0006] It is yet another object of the present invention to reduce noise due to unwanted electric field signals. [Means for solving the problem]

[0007] According to an embodiment of the present invention, there may be provided a multilayer ceramic capacitor including a dielectric layer and first and second internal electrodes having different sizes, the body including first and second surfaces facing each other in a lamination direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces and facing each other, and first and second external electrodes, wherein a ratio (a / b) of a margin a in a length direction of the second internal electrodes to a margin b in a length direction of the first internal electrodes is 0.33 or more (where a>0, b>0), where a margin b in a length direction of the first internal electrodes is b and a margin a in a length direction of the second internal electrodes is a.

[0008] According to another embodiment of the present invention, there may be provided a multilayer ceramic capacitor including a dielectric layer and first and second internal electrodes having different sizes, the body including first and second surfaces facing each other in a lamination direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces and facing each other, and first and second external electrodes, wherein a ratio (c / d) of the width direction margin c of the second internal electrodes to the width direction margin d of the first internal electrodes is 0.33 or more (where c>0, d>0), where d is a width direction margin of the first internal electrodes and c is a width direction margin of the second internal electrodes. Effect of the Invention

[0009] According to an embodiment of the present invention, it is possible to prevent deterioration of electric field characteristics due to crosstalk.

[0010] According to another embodiment of the present invention, the effect of the fringe electric field applied to the ends of the internal electrodes can be minimized.

[0011] According to yet another embodiment of the present invention, a multilayer ceramic capacitor capable of reducing noise caused by unwanted electric field signals can be provided.

[0012] However, the various beneficial advantages and effects of the present invention are not limited to the above, and can be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0013] [Figure 1] 1 is a perspective view illustrating a multilayer ceramic capacitor according to an embodiment of the present invention; [Diagram 2] 2 is a perspective view showing a schematic view of a main body of the multilayer ceramic capacitor shown in FIG. [Diagram 3] 2A to 2C are plan views respectively showing first and second internal electrodes applied to the multilayer ceramic capacitor of FIG. [Figure 4] 2A to 2C are plan views respectively showing first and second internal electrodes applied to the multilayer ceramic capacitor of FIG. [Diagram 5] 2 is a plan view showing first and second internal electrodes applied to the multilayer ceramic capacitor of FIG. 1, overlapping each other. FIG. [Figure 6] 1 is a perspective view illustrating a multilayer ceramic capacitor according to another embodiment of the present invention; [Figure 7] 7 is a perspective view showing a schematic view of a main body of the multilayer ceramic capacitor shown in FIG. 6. [Figure 8] 7 is a plan view showing first and second internal electrodes applied to the multilayer ceramic capacitor of FIG. 6, overlapping each other. FIG. [Figure 9] 11 is a perspective view illustrating a multilayer ceramic capacitor according to another embodiment of the present invention; FIG. [Figure 10] 11 is a perspective view illustrating a multilayer ceramic capacitor according to another embodiment of the present invention; FIG. [Figure 11] 11 is a perspective view illustrating a main body of the multilayer ceramic capacitor of FIG. 9 and FIG. 10. [Figure 12] 11 is a plan view showing first and second internal electrodes overlapping each other according to an embodiment that can be applied to the multilayer ceramic capacitors of FIGS. 9 and 10. FIG. [Figure 13] 11 is a plan view showing first and second internal electrodes overlapping each other in another embodiment that can be applied to the multilayer ceramic capacitors of FIGS. 9 and 10. FIG. [Figure 14] 11 is a plan view showing a second internal electrode applied to the multilayer ceramic capacitor of FIG. 9 and FIG. 10. [Figure 15] 11 is a plan view showing first and second internal electrodes overlapping each other according to still another embodiment that can be applied to the multilayer ceramic capacitors of FIGS. 9 and 10. FIG. [Figure 16] 1 is a graph showing a crosstalk level (S21-parameter) according to a margin ratio in a length direction and / or a width direction of a multilayer ceramic capacitor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those having average knowledge in the art. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0015] In order to clearly explain the present invention, parts not relevant to the description are omitted in the drawings, thicknesses are enlarged to clearly show multiple layers and regions, and components having the same function within the same concept are described using the same reference numerals. Furthermore, throughout the specification, when a part "includes" a certain component, it does not mean that other components are excluded, but that the part may further include other components, unless otherwise specified.

[0016] Hereinafter, to clearly describe the embodiments of the present invention, the directions of the capacitor body 110 will be defined as follows: X, Y, and Z shown in the drawings respectively indicate the length direction (second direction), width direction (third direction), and thickness direction (first direction) of the capacitor body 110. In addition, in this embodiment, the Z direction may be used in the same concept as the stacking direction in which the dielectric layers 111, 211, 311, and 411 are stacked.

[0017] FIG. 1 is a perspective view illustrating a multilayer ceramic capacitor according to an embodiment of the present invention, FIGS. 3 and 4 are plan views illustrating first and second internal electrodes, respectively, applied to the multilayer ceramic capacitor of FIG. 1, and FIG. 5 is a plan view illustrating the first and second internal electrodes, which are overlapped, applied to the multilayer ceramic capacitor of FIG. 1.

[0018] 1 to 5, a multilayer ceramic capacitor 100 according to an embodiment of the present invention may include a dielectric layer 111 and first and second internal electrodes 121, 122 having different sizes. The multilayer ceramic capacitor may include a body 110 including first and second surfaces S1, S2 facing each other in a lamination direction of the first and second internal electrodes 121, 122, third and fourth surfaces S3, S4 connected to the first and second surfaces S1, S2 and facing each other, fifth and sixth surfaces S5, S6 connected to the first and second surfaces S1, S2 and connected to the third and fourth surfaces S3, S4 and facing each other, and first and second external electrodes 131, 132.

[0019] In this case, when the lengthwise margin of the first internal electrode 121 is b and the lengthwise margin of the second internal electrode 122 is a, the ratio (a / b) of the lengthwise margin a of the second internal electrode 122 to the lengthwise margin b of the first internal electrode 121 can satisfy a range of 0.33 or more (where a>0, b>0).

[0020] In the multilayer ceramic capacitor according to the present invention, when the lengthwise margin ratio (a / b) and / or the widthwise margin ratio (c / d) are within a predetermined range, crosstalk that may occur due to the fringing effect can be prevented, as described below, and deterioration of the electric field characteristics can be prevented. The fringing effect refers to an effect caused by electric field lines that diverge and converge in a circular shape at the electrode ends of a parallel plate capacitor, and crosstalk can occur when an unwanted electric field signal is transferred to another port. This phenomenon is likely to occur when multiple small chips are mounted in a small area or multiple components are combined into one chip. The multilayer ceramic capacitor according to the present invention can solve this problem, and multiple internal electrodes act as compensation patterns for each other, thereby reducing the magnitude of the fringing electric field, and thereby preventing deterioration of the electric field characteristics and noise generation.

[0021] In this specification, the term "margin" may refer to the difference in size between the dielectric layer and the internal electrode, and may refer to the distance between the end of the internal electrode and the end of the dielectric layer. In addition, in this specification, the term "lengthwise margin" may refer to the shortest distance and / or vertical distance from the end of the internal electrode in the lengthwise direction (second direction, X direction) to the end of the dielectric layer in the lengthwise direction (second direction, X direction), and may refer to the shortest distance and / or vertical distance to the third surface S3 or the fourth surface S4 of the main body. In addition, in this specification, the term "widthwise margin" may refer to the distance from the end of the internal electrode in the widthwise direction (third direction, Y direction) to the end of the dielectric layer in the widthwise direction (third direction, Y direction), and may refer to the shortest distance and / or vertical distance to the fifth surface S5 or the sixth surface S6 of the main body.

[0022] 12 is a cross-sectional view of a multilayer ceramic capacitor in which a first internal electrode 321 and a second internal electrode 322 are arranged. Referring to FIG. 12, a margin b in the length direction of the first internal electrode 321 is JPEG0007662123000001.jpg431 JPEG0007662123000002.jpg433, and the margin a in the length direction of the second internal electrode 322 is JPEG0007662123000003.jpg432 JPEG0007662123000004.jpg433. Moreover, the widthwise margin d of the first internal electrode 321 means the shortest vertical distance from the position w1 to the position w3, and the widthwise margin c of the second internal electrode 322 means the shortest vertical distance from the position w2 to the position w3.

[0023] The capacitor body 110 is formed by stacking a plurality of dielectric layers 111 in the Z direction and then firing them, and the boundaries between adjacent dielectric layers 111 of the capacitor body 110 can be so integrated that they are difficult to confirm without using a scanning electron microscope (SEM).

[0024] The specific shape of the body is not particularly limited, but as shown in the figure, the body may be a hexahedron or a similar shape. Due to shrinkage of the ceramic powder contained in the body during the firing process, the body may not be a hexahedron having perfect straight lines, but may be substantially a hexahedron. In addition, the shape and dimensions of the capacitor body 110 and the number of layers of the dielectric layers 111 are not limited to those shown in the drawings of this embodiment.

[0025] In this embodiment, for ease of explanation, both sides of the capacitor body 110 facing each other in the Z direction are defined as first and second surfaces S1, S2, and the first and second surfaces S1, S2, both sides facing each other in the X direction are defined as third and fourth surfaces S3, S4, and the first and second surfaces S1, S2 and the third and fourth surfaces S3, S4, and both sides facing each other in the Y direction are defined as fifth and sixth surfaces S5, S6.

[0026] According to an embodiment of the present invention, the raw material for forming the dielectric layer 111 is not particularly limited as long as it can obtain a sufficient capacitance. For example, a barium titanate-based material, a lead complex perovskite-based material, or a strontium titanate-based material can be used.

[0027] In addition, the material forming the dielectric layer 111 may be a powder such as barium titanate (BaTiO3) to which various ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. may be added according to the purpose of the present invention.

[0028] The ceramic additive may be, for example, a transition metal oxide or transition metal carbide, a rare earth element, magnesium (Mg), or aluminum (Al).

[0029] In one embodiment of the present invention, a plurality of internal electrodes 121, 122 having different sizes may be alternately arranged with the dielectric layer 111 interposed therebetween. In this case, the first and second internal electrodes 121, 122 may be electrically separated from each other by the dielectric layer 111 arranged therebetween.

[0030] The material for forming the first and second internal electrodes 121 and 122 is not particularly limited, and may be formed using a conductive paste containing at least one of silver (Ag), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), palladium (Pd), titanium (Ti), and alloys thereof. The conductive paste may be printed using a screen printing method or a gravure printing method, but the present invention is not limited thereto.

[0031] The average thickness of the first and second internal electrodes 121 and 122 may be 0.4 um or less. The average thickness of the internal electrodes may be an average of values ​​measured at five different positions of the fired internal electrodes. The lower limit of the average thickness of the first and second internal electrodes is not particularly limited, but may be, for example, 0.01 um or more.

[0032] In an embodiment of the present invention, a ratio (a / b) of a margin a in the length direction of the second internal electrode 122 to a margin b in the length direction of the first internal electrode 121 may be 0.33 or more. When the ratio (a / b) of a margin a in the length direction of the second internal electrode 122 to a margin b in the length direction of the first internal electrode 121 is in a range of 0.33 or more, the second internal electrode can fully function as a compensation pattern to reduce crosstalk, and when the ratio (a / b) is less than 0.33, a short circuit may occur due to an excessively close distance to an external electrode.

[0033] In one example of the present invention, the upper limit of the ratio (a / b) of the margin a in the length direction of the second internal electrode 122 to the margin b in the length direction of the first internal electrode 121 is not particularly limited, but may be, for example, less than 1. If the ratio (a / b) is 1, the second internal electrode 122 cannot function as a compensation pattern. The ratio (a / b) of the margin a in the length direction of the second internal electrode to the margin b in the length direction of the first internal electrode may be less than 1, 0.95 or less, 0.90 or less, 0.85 or less, 0.80 or less, 0.75 or less, 0.70 or less, or 0.67 or less. By making the ratio (a / b) of the margin a in the length direction of the second internal electrode to the margin b in the length direction of the first internal electrode satisfy the above range, the influence of the fringe electric field applied to the end of the internal electrode can be minimized, and crosstalk can be minimized.

[0034] In one embodiment of the present invention, a difference (ba) between a margin b in the length direction of the first internal electrode and a margin a in the length direction of the second internal electrode may be 10 um or more. The difference (ba) between the margin b in the length direction of the first internal electrode and the margin a in the length direction of the second internal electrode may mean a difference between the length of the margin b in the length direction of the first internal electrode and the length of the margin a in the length direction of the second internal electrode, and may mean a difference in length in the X direction. By making the difference (ba) between the margin b in the length direction of the first internal electrode and the margin a in the length direction of the second internal electrode 10 um or more, noise of the multilayer ceramic capacitor can be effectively reduced.

[0035] The difference (ba) between the margin b in the length direction of the first internal electrode and the margin a in the length direction of the second internal electrode may be, for example, 10 um or more, 14 um or more, 18 um or more, 22 um or more, 26 um or more, or 30 um or more, and the upper limit is not particularly limited, but may be, for example, 500 um or less. When the difference (ba) between the margin b in the length direction of the first internal electrode and the margin a in the length direction of the second internal electrode satisfies the above range, the noise removal effect can be maximized.

[0036] In another embodiment of the present invention, when a margin in a width direction of the first internal electrode is d and a margin in a width direction of the second internal electrode is c, a ratio (c / d) of the margin in a width direction of the second internal electrode to the margin in a width direction of the first internal electrode d may be 0.33 or more (where c>0, d>0). When the ratio (c / d) of the margin in a width direction of the second internal electrode to the margin in a width direction of the first internal electrode d is in a range of 0.33 or more, crosstalk can be reduced, and when the ratio (c / d) is less than 0.33, a short circuit may occur due to an excessively close distance to an external electrode.

[0037] In one example of the present invention, the upper limit of the ratio (c / d) of the width direction margin c of the second internal electrode to the width direction margin d of the first internal electrode is not particularly limited, but may be, for example, less than 1. If the ratio (c / d) is 1, the second internal electrode cannot function as a compensation pattern. The ratio (c / d) of the width direction margin c of the second internal electrode to the width direction margin d of the first internal electrode may be less than 1, 0.95 or less, 0.90 or less, 0.85 or less, 0.80 or less, 0.75 or less, 0.70 or less, or 0.67 or less. By making the ratio (c / d) of the width direction margin c of the second internal electrode to the width direction margin d of the first internal electrode satisfy the above range, the influence of the fringe electric field applied to the end of the internal electrode can be minimized, and crosstalk can be minimized.

[0038] In one embodiment of the present invention, a difference (dc) between a widthwise margin d of the first internal electrode and a widthwise margin c of the second internal electrode may be 10 um or more. The difference (dc) between the widthwise margin d of the first internal electrode and the widthwise margin c of the second internal electrode may mean a difference between a width of the widthwise margin d of the first internal electrode and a width of the widthwise margin c of the second internal electrode, and may mean a difference in width in the Y direction. By making the difference (dc) between the widthwise margin d of the first internal electrode and the widthwise margin c of the second internal electrode 10 um or more, noise of the multilayer ceramic capacitor can be effectively reduced.

[0039] The difference (dc) between the widthwise margin d of the first internal electrode and the widthwise margin c of the second internal electrode may be, for example, 10 um or more, 14 um or more, 18 um or more, 22 um or more, 26 um or more, or 30 um or more, and the upper limit is not particularly limited, but may be, for example, 500 um or less. When the difference (dc) between the widthwise margin d of the first internal electrode and the widthwise margin c of the second internal electrode satisfies the above range, the noise removal effect can be maximized.

[0040] The first and second external electrodes 131 and 132 may be disposed in contact with the first and second internal electrodes, respectively. The first and second external electrodes being in contact with the first and second internal electrodes, respectively, may mean that the first internal electrode is electrically connected to the first external electrode through a portion exposed to the outside of the body, and may mean that the second internal electrode is electrically connected to the second external electrode through a portion exposed to the outside of the body. The first and second external electrodes 131 and 132 may be disposed extending to a portion of four faces in contact with the faces to which the first and second internal electrodes are exposed.

[0041] The method of forming the first and second external electrodes 131, 132 does not need to be particularly limited, and for example, they can be formed by dipping the body into a paste containing a conductive metal and glass, or by transferring a dried film made by drying a metal paste onto the body.

[0042] In one embodiment according to the present invention, the first and second external electrodes 131, 132 may be made of one or more of silver (Ag), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), tin (Sn), tungsten (W), palladium (Pd), titanium (Ti), and alloys thereof. Also, a plating layer may be formed on the first and second external electrodes 131, 132 to improve mountability with a substrate.

[0043] In an embodiment of the present invention, the first and second internal electrodes may be arranged to be exposed to a third surface and a fourth surface of the main body, respectively. That the first and second internal electrodes are exposed to the third and fourth surfaces of the main body may mean that the first and second internal electrodes are arranged to face each other in the X direction, or that the first and second internal electrodes are arranged in the length direction. In this case, the first external electrode 131 and the second external electrode 132 may be arranged on the third and fourth surfaces of the main body, respectively, to be in contact with the first internal electrode 121 and the second internal electrode 122.

[0044] 1 to 5 show the multilayer ceramic capacitor according to the embodiment. Referring to FIG. 1 to FIG. 5, in the multilayer ceramic capacitor 100 according to the present embodiment, a first internal electrode 121 and a second internal electrode 122 facing each other in an X direction (length direction, second direction) may be disposed on a third surface S3 and a fourth surface S4 of a body 110, respectively. Also, a first external electrode 131 and a second external electrode 132 may be disposed on a third surface S3 and a fourth surface S4 of the body 110, respectively, and may be electrically connected to the first internal electrode 121 and the second internal electrode 122, respectively. When the multilayer ceramic capacitor according to the present embodiment has the above structure, it has an appearance similar to that of a typical MLCC.

[0045] In another embodiment of the present invention, the first and second internal electrodes may be arranged to be exposed to a fifth surface and a sixth surface of the main body. The first and second internal electrodes being exposed to the fifth and sixth surfaces of the main body may mean that the first and second internal electrodes are arranged to face each other in the Y direction, and may mean that the first and second internal electrodes are arranged in the width direction. In this case, the first and second external electrodes may be arranged on the fifth and sixth surfaces of the main body, respectively. Also, the first and second external electrodes may be arranged on the fifth and sixth surfaces of the main body, respectively, to be in contact with the first and second internal electrodes.

[0046] 6 to 8 show the multilayer ceramic capacitor according to the embodiment. Referring to FIG. 6 to FIG. 8, in the multilayer ceramic capacitor 200 according to the embodiment, a first internal electrode 221 and a second internal electrode 222 facing each other in a Y direction (width direction, third direction) may be disposed on a fifth surface S5 and a sixth surface S6 of the body 210, respectively. Also, a first external electrode 231 and a second external electrode 232 may be disposed on a fifth surface S5 and a sixth surface S6 of the body 210, respectively, and may be electrically connected to the first internal electrode 221 and the second internal electrode 222, respectively. When the multilayer ceramic capacitor according to the embodiment has the above structure, it has an appearance similar to that of a LICC (Low Inductance Chip Capacitor).

[0047] In yet another embodiment of the present invention, the multilayer ceramic capacitor of the present invention may further include a third external electrode, the first internal electrode may be exposed to a third or fourth surface of the body, and the second internal electrode may be exposed to a fifth and sixth surface of the body. In this case, the first external electrode may be disposed on the third surface of the body, the second external electrode may be disposed on the fourth surface of the body, and the third external electrode may be electrically connected to the second internal electrode and disposed on the first, second, fifth and sixth surfaces of the body.

[0048] 9 to 14 show the multilayer ceramic capacitor according to the present embodiment. Referring to FIG. 9 to FIG. 13, in the multilayer ceramic capacitor 300 according to the present embodiment, the first internal electrode 321 may be exposed to the third surface S3 or the fourth surface S4 of the body 310, and the second internal electrode 322 may be exposed to the fifth surface S5 and the sixth surface S6 of the body 310. Also, the first external electrode 331 and the second external electrode 332 may be disposed on the third surface S3 and the fourth surface S4 of the body 310, respectively, and may be electrically connected to the first internal electrode 321. And, the third external electrode 333 may be disposed on the first surface S1, the second surface S2, the fifth surface S5 and the sixth surface S6 of the body 310. At this time, the second internal electrode 322 disposed to be exposed to the fifth surface S5 and the sixth surface S6 of the body 310 may have a shape as shown in FIG. 13, for example, a + shape.

[0049] The third external electrode 333 may be arranged to connect the first surface S1, the second surface S2, the fifth surface S5 and the sixth surface S6 of the body 310 as shown in FIG. 9, and may include discontinuous portions on the first surface S1 and the second surface S2 as shown in FIG. 10, or may not be arranged on the first surface S1 and the second surface S2 of the body 310, but is not limited thereto.

[0050] In one embodiment of the present invention, the multilayer ceramic capacitor according to the present invention may further include a third internal electrode, in which the first internal electrode is exposed to a third surface of the body and arranged to contact the first external electrode, and the third internal electrode is exposed to a fourth surface of the body and arranged to contact the second external electrode.

[0051] 9 to 14, in the case of the above embodiment, the multilayer ceramic capacitor 310 may have a multi-layer structure depending on the positions of the first internal electrode 321 and the third internal electrode 323. For example, the multilayer ceramic capacitor 310 according to the present embodiment may have a structure in which the first internal electrodes 321 and the second internal electrodes 322 are alternately laminated in a plurality of layers as shown in Fig. 12, and the second internal electrodes 322 and the third internal electrodes 323 are laminated in a plurality of layers on the above laminated structure as shown in Fig. 13. In this case, the number of layers in the structure of Fig. 12 and the number of layers in the structure of Fig. 13 may be appropriately adjusted depending on the purpose of the capacitor.

[0052] In the above embodiment, the laminated structure of the first internal electrode 321 in Fig. 12 is disposed at the bottom, and the laminated structure of the third internal electrode 323 in Fig. 13 is disposed at the top, but the above embodiment also includes a structure in which the laminated structure of the first internal electrode 321 in Fig. 12 is disposed at the top, and the laminated structure of the third internal electrode 323 in Fig. 13 is disposed at the bottom. When the multilayer ceramic capacitor according to the present embodiment has the above structure, it may have the shape of a three-terminal capacitor, and one of the external electrodes may function as a ground electrode.

[0053] In yet another embodiment of the present invention, the multilayer ceramic capacitor according to the present invention may further include a third external electrode, and the first internal electrode may be exposed to a third surface and a fourth surface of the body, and the second internal electrode may be exposed to a fifth surface and a sixth surface of the body. In this case, the first external electrode may be disposed on the third surface of the body, the second external electrode may be disposed on the fourth surface of the body, and the third external electrode may be electrically connected to the second internal electrode and may be disposed on the first, second, fifth and sixth surfaces of the body.

[0054] 15 is a cross-sectional view of the multilayer ceramic capacitor according to the embodiment. Referring to FIG 15, the first internal electrode 421 may be exposed to the third surface S3 and the fourth surface S4 of the body and may be in contact with the first external electrode 431 and the second external electrode 432. The second internal electrode 422 may be exposed to the fifth surface S5 and the sixth surface S6 of the body and may be in contact with the third external electrode 433.

[0055] When the multilayer ceramic capacitor includes a third internal electrode and a third external electrode, the thickness and forming method of the third internal electrode and the third external electrode are the same as those of the first and second internal electrodes and the first and second external electrodes described above, and therefore will not be described here.

[0056] Table 1 below and FIG. 16 show the scattering coefficient (S21-parameter) according to the ratio of a / b or the ratio of c / d.

[0057] [Table 1]

[0058] Referring to Table 1, it can be seen that when the ratio of a / b or c / d is 1, the same result is obtained as when the compensation pattern is not applied, and that the reduction rate tends to increase as the ratio (a / b or c / d) decreases. In particular, it can be seen that a sharp change in the values ​​is observed around 0.667. It can also be seen that when the ratio (a / b or c / d) is 0.33, a very high reduction rate is observed.

[0059] From Table 1 above, it can be seen that the multilayer ceramic capacitor according to the present invention can minimize the influence of the fringe electric field applied to the ends of the internal electrodes by using the second internal electrodes as a compensation pattern, can prevent deterioration of the electric field characteristics due to crosstalk, and can reduce noise due to undesired electric field signals.

[0060] Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that the scope of the present invention is not limited thereto, and that various modifications and variations are possible within the scope of the technical idea of ​​the present invention described in the claims. [Other possible items] [Item 1] a main body including a dielectric layer and first and second internal electrodes having different sizes, the main body including first and second surfaces facing each other in a lamination direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces and facing each other, and first and second external electrodes; When the margin in the length direction of the first internal electrode is b and the margin in the length direction of the second internal electrode is a, A multilayer ceramic capacitor, wherein a ratio (a / b) of a margin a in the length direction of the second internal electrode to a margin b in the length direction of the first internal electrode is 0.33 or more (where a>0, b>0). [Item 2] 2. The multilayer ceramic capacitor according to claim 1, wherein the ratio (a / b) is less than 1. [Item 3] 2. The multilayer ceramic capacitor according to claim 1, wherein the ratio (a / b) is 0.67 or less. [Item 4] 4. The multilayer ceramic capacitor according to claim 1, wherein a difference (ba) between a margin b in the length direction of the first internal electrode and a margin a in the length direction of the second internal electrode is 10 μm or more. [Item 5] a main body including a dielectric layer and first and second internal electrodes having different sizes, the main body including first and second surfaces facing each other in a lamination direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces and facing each other, and first and second external electrodes; When the margin in the width direction of the first internal electrode is d and the margin in the width direction of the second internal electrode is c, A multilayer ceramic capacitor, wherein a ratio (c / d) of a margin c in the width direction of the second internal electrode to a margin d in the width direction of the first internal electrode is 0.33 or more (where c>0, d>0). [Item 6] 6. The multilayer ceramic capacitor according to claim 5, wherein the ratio (c / d) is less than 1. [Item 7] 6. The multilayer ceramic capacitor according to claim 5, wherein the ratio (c / d) is 0.67 or less. [Item 8] 8. The multilayer ceramic capacitor according to claim 5, wherein a difference (dc) between a margin d in the width direction of the first internal electrodes and a margin c in the width direction of the second internal electrodes is 10 um or more. [Item 9] 9. The multilayer ceramic capacitor according to claim 1, wherein the first and second internal electrodes have an average thickness of 0.4 um or less. [Item 10] the first and second internal electrodes are exposed to a third surface and a fourth surface of the body, respectively; 10. The multilayer ceramic capacitor according to claim 1, wherein the first and second external electrodes are disposed on a third surface and a fourth surface of the body so as to be in contact with the first and second internal electrodes, respectively. [Item 11] the first and second internal electrodes are exposed to a fifth surface and a sixth surface of the body, respectively; 11. The multilayer ceramic capacitor according to claim 1, wherein the first and second external electrodes are disposed on a fifth surface and a sixth surface of the body so as to be in contact with the first and second internal electrodes, respectively. [Item 12] Further comprising a third external electrode; the first internal electrode is exposed to a third or fourth surface of the body; the second internal electrode is disposed so as to be exposed to a fifth surface and a sixth surface of the main body; the first external electrode is disposed on a third surface of the body; the second external electrode is disposed on a fourth surface of the body; 12. The multilayer ceramic capacitor according to claim 1, wherein the third external electrodes are electrically connected to the second internal electrodes and are disposed on the first surface, the second surface, the fifth surface and the sixth surface of the body. [Item 13] Further comprising a third internal electrode, the first internal electrode is exposed to a third surface of the body and is disposed so as to be in contact with the first external electrode; 13. The multilayer ceramic capacitor according to claim 12, wherein the third internal electrode is exposed to a fourth surface of the body and is disposed so as to be in contact with the second external electrode. [Item 14] Further comprising a third external electrode; the first internal electrode is exposed to a third surface and a fourth surface of the body; the second internal electrode is disposed so as to be exposed to a fifth surface and a sixth surface of the main body; the first and second external electrodes are disposed on a third surface and a fourth surface of the body, respectively, and electrically connected to the first internal electrode; 12. The multilayer ceramic capacitor according to claim 1, wherein the third external electrodes are electrically connected to the second internal electrodes and are disposed on the first surface, the second surface, the fifth surface and the sixth surface of the body. [Explanation of symbols]

[0061] 100, 200, 300 Multilayer ceramic capacitors 110, 210, 310 Main unit 111, 211, 311, 411 Dielectric layers 121, 221, 321, 421 1st internal electrode 122, 222, 322, 422 2nd internal electrode 323 3rd internal electrode 131, 231, 331, 431 1st external electrode 132, 232, 332, 432 second external electrode 333, 433 Third external electrode

Claims

1. a body including a dielectric layer and first and second internal electrodes having different sizes, the body including first and second surfaces facing each other in a lamination direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces and facing each other, and first and second external electrodes; Further comprising a third external electrode; the first internal electrode is exposed to a third surface or a fourth surface of the body; the second internal electrode is disposed so as to be exposed to a fifth surface and a sixth surface of the main body; the first external electrode is disposed on a third surface of the body; the second external electrode is disposed on a fourth surface of the body; the third external electrode is electrically connected to the second internal electrode and is disposed on the first surface, the second surface, the fifth surface, and the sixth surface of the body; a direction in which the fifth surface and the sixth surface face each other is defined as a width direction, and a shortest distance and / or a vertical distance from an end of the first internal electrode or the second internal electrode in the width direction to an end of the dielectric layer in the width direction is defined as a width direction margin, When the margin in the width direction of the first internal electrode is d and the margin in the width direction of the second internal electrode is c, a ratio (c / d) of a margin c in the width direction of the second internal electrode to a margin d in the width direction of the first internal electrode is 0.33 or more and 0.67 or less (c>0, d>0); The average thickness of the first and second internal electrodes is 0.4 um or less; a multilayer ceramic capacitor, wherein the second internal electrode is exposed to a fifth surface and a sixth surface of the body via a first lead portion and a second lead portion, respectively, and a length from the second internal electrode of the first lead portion to the fifth surface of the body and a length from the second internal electrode of the second lead portion to the sixth surface of the body are smaller than a widthwise margin of the first internal electrode.

2. a direction in which the third surface and the fourth surface face each other is defined as a length direction, and a shortest distance and / or a perpendicular distance from an end of the first internal electrode or the second internal electrode in the length direction to an end of the dielectric layer in the length direction is defined as a length direction margin, When the margin in the longitudinal direction of the first internal electrode is defined as b and the margin in the longitudinal direction of the second internal electrode is defined as a, 2. The multilayer ceramic capacitor according to claim 1, wherein a ratio (a / b) of a margin a in a length direction of the second internal electrode to a margin b in a length direction of the first internal electrode is 0.33 to 0.67 (where a>0, b>0).

3. Further comprising a third internal electrode, the first internal electrode is exposed to a third surface of the body and is disposed so as to be in contact with the first external electrode; The multilayer ceramic capacitor according to claim 1 , wherein the third internal electrode is exposed to a fourth surface of the body and is disposed so as to be in contact with the second external electrode.

4. The multilayer ceramic capacitor according to claim 3 , wherein a margin in the width direction of the third internal electrodes is larger than a margin in the width direction of the second internal electrodes.

5. The multilayer ceramic capacitor according to claim 4 , wherein a margin in the length direction of the third internal electrodes is larger than a margin in the length direction of the second internal electrodes.

6. a body including a dielectric layer and first and second internal electrodes having different sizes, the body including first and second surfaces facing each other in a lamination direction of the first and second internal electrodes, third and fourth surfaces connected to the first and second surfaces and facing each other, and fifth and sixth surfaces connected to the first and second surfaces and connected to the third and fourth surfaces and facing each other, and first and second external electrodes; Further comprising a third external electrode; the first internal electrode is exposed to a third surface and a fourth surface of the body; the second internal electrode is disposed so as to be exposed to a fifth surface and a sixth surface of the main body; the first and second external electrodes are disposed on a third surface and a fourth surface of the body, respectively, and electrically connected to the first internal electrode; the third external electrode is electrically connected to the second internal electrode and is disposed on the first surface, the second surface, the fifth surface, and the sixth surface of the body; a direction in which the fifth surface and the sixth surface face each other is defined as a width direction, and a shortest distance and / or a vertical distance from an end of the first internal electrode or the second internal electrode in the width direction to an end of the dielectric layer in the width direction is defined as a width direction margin, When the margin in the width direction of the first internal electrode is d and the margin in the width direction of the second internal electrode is c, a ratio (c / d) of a margin c in the width direction of the second internal electrode to a margin d in the width direction of the first internal electrode is 0.33 or more and 0.67 or less (c>0, d>0); The average thickness of the first and second internal electrodes is 0.4 um or less; a multilayer ceramic capacitor, wherein the second internal electrode is exposed to a fifth surface and a sixth surface of the body via a first lead portion and a second lead portion, respectively, and a length from the second internal electrode of the first lead portion to the fifth surface of the body and a length from the second internal electrode of the second lead portion to the sixth surface of the body are smaller than a widthwise margin of the first internal electrode.

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