Three-dimensional (3D) memory devices

Abstract

To provide embodiments of through array contact structures of a 3D memory device and a fabricating method thereof.SOLUTION: A 3D NAND memory device includes a substrate including a peripheral circuit, and an alternating layer stack disposed on the substrate. The alternating layer stack includes a first region including an alternating dielectric stack, a second region including an alternating conductor / dielectric stack, and a third region including staircase structures on edges of the alternating conductor / dielectric layer stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region or the third region, a plurality of channel structures and a plurality of slit structures each extending vertically through the alternating conductor / dielectric stack, and a plurality of through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one of the through array contacts is electrically connected with the peripheral circuit.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to Chinese Patent Application No. 201710135654.9, filed on March 8, 2017, and Chinese Patent Application No. 201710135329.2, filed on March 8, 2017, which are incorporated by reference herein in their entireties.

[0002] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods for manufacturing the same. [Background technology]

[0003] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as memory cell feature sizes approach lower limits, planar processes and manufacturing techniques become difficult and expensive. As a result, memory density for planar memory cells is approaching an upper limit.

[0004] 3D memory architectures can address the density limitations of planar memory cells and include a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention [Means for solving the problem]

[0005] Disclosed herein are embodiments of a through array contact (TAC) structure for a 3D memory device and methods for fabricating the same.

[0006] A three-dimensional (3D) NAND memory device is disclosed that includes a substrate having at least one peripheral circuit and an alternating layer stack disposed on the substrate. The alternating layer stack includes a first region including an alternating dielectric stack including a plurality of dielectric layer pairs, a second region including an alternating conductor / dielectric stack having a plurality of conductor / dielectric layer pairs, and a third region including a staircase structure on an edge of the alternating conductor / dielectric layer stack in a word line direction. The memory device further includes a barrier structure extending vertically through the alternating layer stack for laterally isolating the first region from the second region or the third region. A plurality of channel structures and a plurality of slit structures each extending vertically through the alternating conductor / dielectric stack, and a plurality of through array contacts in the first region each extending vertically through the alternating dielectric stack are included. At least one of the plurality of through array contacts is electrically connected to at least one peripheral circuit.

[0007] The barrier structure may be silicon oxide and silicon nitride. Each of the plurality of dielectric layer pairs may include a silicon oxide layer and a silicon nitride layer, and each of the plurality of conductor / dielectric layer pairs includes a metal layer and a silicon oxide layer. The number of the plurality of dielectric layer pairs is at least 32. The number of the plurality of conductor / dielectric layer pairs is at least 32.

[0008] A number of slit structures extend laterally along the wordline direction to divide the alternating conductor / dielectric stacks into a number of memory fingers.

[0009] In some embodiments, the barrier structure extends laterally along the word line direction, and the first region is separated from the second region by the barrier structure and sandwiched between two adjacent slit structures.

[0010] In some embodiments, the barrier structure extends laterally along a bit line direction that is different from the word line direction and laterally separates the first region from the second region. The bit line direction may be perpendicular to the word line direction.

[0011] The width of the first region surrounded by the barrier structure in the bit line direction may be greater than the distance between two adjacent slit structures. The first region surrounded by the barrier structure is sandwiched between two upper selective gate staircase regions in the word line direction. At least the top two layers of the alternating conductor / dielectric stack in each upper selective gate staircase region have a staircase structure. At least one conductive layer is on the staircase structure in the upper selective gate staircase region and configured to interconnect upper select gates on both sides of the first region surrounded by the barrier structure in the word line direction above the alternating conductor / dielectric stack in the second region. In some embodiments, at least two first regions are surrounded by corresponding barrier structures, and each first region extends in parallel along the bit line direction.

[0012] In some embodiments, a plurality of barrier structures for enclosing a plurality of first regions from a second region, the plurality of first regions being aligned in a bit line direction. Each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction. In some embodiments, the plurality of first regions are aligned in at least two columns in the bit line direction. At least one slit structure sandwiched by two adjacent barrier structures in the bit line direction includes a gap and is configured to interconnect word lines of adjacent memory fingers.

[0013] In some embodiments, the first region is separated from the third region by a barrier structure. The opening of the barrier structure is at an edge of the alternating layer stack in the word line direction. In some embodiments, the width of the first region in the bit line direction is greater than the distance between two adjacent slit structures. In some other embodiments, the width of the first region in the bit line direction is less than the maximum distance between two adjacent slit structures in the third region.

[0014] The memory device further includes a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack.

[0015] Also disclosed is a method for forming a three-dimensional (3D) NAND memory device. The method includes forming a substrate including at least one peripheral circuit, forming an alternating dielectric stack on the substrate including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs including a first dielectric layer and a second dielectric layer different from the first dielectric layer, forming a staircase structure at an edge of the alternating dielectric stack, and forming a plurality of channel structures and at least one barrier structure, each extending vertically through the alternating dielectric stack. The at least one barrier structure separates the alternating dielectric stack into at least one first region and a second region laterally bounded by at least the barrier structure. The method further includes forming a plurality of slits and replacing the first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer through the slits to form an alternating conductor / dielectric stack including a plurality of conductor / dielectric layer pairs; depositing a conductive material into the slits to form a plurality of slit structures; and forming a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack to electrically connect at least one of the plurality of through array contacts to at least one peripheral circuit.

[0016] The step of forming the substrate includes the steps of forming at least one peripheral circuit on the base substrate, forming at least one interconnect structure to electrically connect at least one of the plurality of through array contacts to the at least one peripheral circuit, and forming an epitaxial substrate above the at least one peripheral circuit.

[0017] In some embodiments, the method further includes, prior to the step of forming the slits, forming a plurality of doped regions in the epitaxial substrate such that each slit structure is in contact with a corresponding doped region.

[0018] In some embodiments, the method further includes forming at least one opening in the epitaxial substrate corresponding to the at least one first region to expose the interconnect structure for electronically connecting with at least one peripheral circuit, and filling the at least one opening with a dielectric material.

[0019] In some embodiments, the method further includes forming at least one barrier structure using silicon oxide and silicon nitride, forming at least 32 pairs of dielectric layer pairs using silicon oxide and silicon nitride layers, and forming at least 32 pairs of conductor / dielectric layer pairs using metal layers and silicon oxide layers.

[0020] In some embodiments, the method further includes forming a plurality of slit structures extending laterally along the wordline direction to divide the alternating conductor / dielectric stacks into a plurality of memory fingers.

[0021] In some embodiments, the method further includes forming two parallel barrier structures extending laterally along the word line direction such that the first region is separated from the second region by the two parallel barrier structures and is sandwiched between two adjacent slit structures.

[0022] In some embodiments, the method further includes forming a barrier structure extending laterally along a bit line direction different from the word line direction to laterally separate the first region from the second region. In some embodiments, the method further includes forming a barrier structure extending laterally along a bit line direction perpendicular to the word line direction.

[0023] In some embodiments, the method further includes forming the barrier structure such that a width of a first region surrounded by the barrier structure in the bit line direction is wider than a distance between two adjacent slit structures.

[0024] In some embodiments, the method further includes forming a second staircase structure in the alternating dielectric stack adjacent to the barrier structure, and forming at least one conductive layer on the staircase structure adjacent to the barrier structure to interconnect upper select gates on either side of the first region surrounded by the barrier structure in the wordline direction above the alternating conductor / dielectric stack in the second region.

[0025] In some embodiments, the method further includes forming at least two barrier structures to surround the at least two first regions extending in parallel along the bitline direction.

[0026] In some embodiments, the method further includes forming a plurality of barrier structures to surround the plurality of first regions from the second region, and the plurality of first regions are aligned in the bit line direction such that each of the plurality of first regions is sandwiched between two adjacent slit structures in the bit line direction.

[0027] In some embodiments, the method further includes forming the plurality of barrier structures such that the plurality of first regions surrounded by the plurality of barrier structures are aligned in at least two rows in a bit line direction.

[0028] In some embodiments, the method further includes forming a gap in at least one slit structure sandwiched by two adjacent barrier structures in a bitline direction for interconnecting wordlines of adjacent memory fingers.

[0029] In some embodiments, the method further includes forming a barrier structure to separate the first region in the staircase structure at an edge of the alternating stack, the opening of the barrier structure being at the edge of the alternating layer stack in the word line direction.

[0030] In some embodiments, the method further comprises forming the barrier structure such that a width of the first region in a bit line direction is greater than a distance between two adjacent slit structures. In some embodiments, the method further comprises forming the barrier structure such that a width of the first region in a bit line direction is less than a maximum distance between two adjacent slit structures in the third region.

[0031] In some embodiments, the method further includes forming a plurality of dummy channel structures adjacent to the barrier structure, each dummy channel structure extending vertically through the alternating conductor / dielectric stack.

[0032] Other aspects of the present disclosure will be apparent to those skilled in the art in light of the description, claims, and drawings of the present disclosure.

[0033] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0034] [Figure 1] 1 is a schematic diagram illustrating an example 3D memory device in a plan view, in accordance with some embodiments of the present disclosure. [Diagram 2] 1 is a schematic expanded plan view illustrating a region of a 3D memory device including an exemplary bitline through array contact region in accordance with some embodiments of the present disclosure. [Figure 3A] 1 is a schematic expanded plan view illustrating a region of a 3D memory device including one exemplary word line through array contact region, according to some embodiments of the present disclosure. [Figure 3B] 1 is a schematic enlarged plan view illustrating a region of a 3D memory device including another example word line through array contact region in accordance with some embodiments of the present disclosure. [Figure 3C]1 is a schematic enlarged plan view illustrating a region of a 3D memory device including another example word line through array contact region in accordance with some embodiments of the present disclosure. [Figure 3D] 1 is a schematic enlarged plan view illustrating a region of a 3D memory device including another example word line through array contact region in accordance with some embodiments of the present disclosure. [Figure 4A] 1 is a schematic enlarged plan view illustrating an area of ​​a 3D memory device including one exemplary staircase-structured through-array contact area, according to some embodiments of the present disclosure. FIG. [Figure 4B] 1 is a schematic enlarged plan view illustrating a region of a 3D memory device including another exemplary staircase-structured through-array contact region, in accordance with some embodiments of the present disclosure. [Diagram 5] 1 is a schematic cross-sectional view illustrating an exemplary 3D memory device according to some embodiments of the present disclosure. [Figure 6] 1 is a flowchart of an exemplary method for forming a 3D memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0036] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. Those skilled in the art will appreciate that the present disclosure can also be employed in a variety of other applications.

[0037] It should be noted that references herein to "one embodiment," "one embodiment," "exemplary embodiment," "some embodiments," and the like, indicate that the described embodiment may include a particular feature, structure, or characteristic, but all embodiments may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described with respect to one embodiment, it will be within the knowledge of one of ordinary skill in the art to achieve such feature, structure, or characteristic with respect to other embodiments, whether or not explicitly described.

[0038] Generally, terms can be understood, at least in part, from usage in context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular sense, or can be used to describe a combination of features, structures, or characteristics in the plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey the singular usage or the plural usage, also depending at least in part on the context.

[0039] It should be readily understood that the meanings of "on", "above", and "over" in this disclosure are to be interpreted in the broadest sense, such that "on" not only means "directly on" something, but also includes the meaning "on" something with an intervening feature or layer therebetween, and that "above" and "over" not only means the meaning "above" or "over" something, but also can include the meaning "above" or "over" something without an intervening feature or layer therebetween (i.e., directly on something).

[0040] Additionally, spatial terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or to other orientations) and the spatial terms used herein may be similarly interpreted accordingly.

[0041] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are applied. The substrate itself can be patterned. The material applied on top of the substrate can be patterned or left unpatterned. Additionally, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made from an electrically non-conductive material, such as glass, plastic, or a sapphire wafer.

[0042] As used herein, the term "layer" refers to a portion of material that includes a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure and may have an extent that is less than the extent of the underlying or overlying structure. Additionally, a layer may be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer may be disposed between any pair of horizontal surfaces, between the top and bottom surfaces, or the top and bottom surfaces, of a continuous structure. A layer may extend along horizontal, vertical, and / or tapered surfaces. A substrate may be a layer and may include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0043] As used herein, the term "nominal / nominally" refers to a desired or target value of a characteristic value or parameter for a component or process operation that is set during the design phase of a product or process, as well as a range of values ​​above and / or below the desired value. The range of values ​​may result from slight variations or tolerances during the manufacturing process. As used herein, the term "about" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0044] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented columns of memory cell transistors (i.e., regions herein as "memory columns", such as NAND columns) on a laterally oriented substrate such that the memory columns extend in a direction perpendicular to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral plane of the substrate.

[0045] Various embodiments according to the present disclosure provide 3D memory devices having a through array contact (TAC) structure for a memory array (also referred to herein as an "array device"). The TAC structure allows contact between the memory and various peripheral circuits and / or devices (e.g., page buffers, latches, decoders, etc.) to be fabricated in a limited number of steps (e.g., in a single step or two steps), thereby reducing process complexity and manufacturing costs. The disclosed TAC is formed through a stack of alternating dielectric layers, which can be more easily etched to form through holes therein, as compared to a stack of alternating conductor and dielectric layers.

[0046] The TACs provide vertical interconnection between stacked array devices and peripheral devices (e.g., for power buses and metal wiring), thereby reducing metal steps and reducing die size. In some embodiments, the TACs can interconnect with various lines in the top and / or bottom conductor layers, which is suitable for 3D memory architectures in which array devices and peripheral devices formed on different substrates are coupled by hybrid bonding, either in sequence or face-to-face. In some embodiments, the TACs in the through array contact structures disclosed herein are formed through a stack of alternating dielectric layers that can be more easily etched to form through holes therein, compared to a stack of alternating conductor and dielectric layers, thereby reducing process complexity and manufacturing costs.

[0047] 1 illustrates a schematic diagram of an example 3D memory device 100 in a plan view in accordance with some embodiments of the present disclosure. The 3D memory device 100 can include multiple channel structure regions (e.g., memory planes, memory blocks, memory fingers, etc., described in detail with respect to various figures below), while one or more TAC structures can be formed between two adjacent channel structure regions.

[0048] As shown in Figure 1, the 3D memory device 100 can include four or more memory planes 110, each of which can include multiple memory blocks 115. It should be noted that the arrangement of the memory planes 110 in the 3D memory device 100 and the arrangement of the memory blocks 115 in each memory plane 110 illustrated in Figure 1 is used merely as an example and does not limit the scope of the present disclosure.

[0049] The TAC structure may include one or more bitline (BL) TAC regions 160 sandwiched between two adjacent memory blocks 115 in the bitline direction (labeled "BL" in the figures) of the 3D memory device and extending along the wordline direction (labeled "WL" in the figures) of the 3D memory device, one or more wordline (BL) TAC regions 160 sandwiched between two adjacent memory blocks 115 in the wordline direction (WL) and extending along the bitline direction (BL), and one or more staircase structure (SS) TAC regions 180 disposed at the edge of each memory plane 110.

[0050] In some embodiments, the 3D memory device 100 may include a number of contact pads 120 arranged in lines on the edges of the 3D memory device 100. The interconnect contacts may be used to electrically interconnect the 3D memory device 100 to any suitable device and / or interface for providing driving power, receiving control signals, transmitting response signals, etc.

[0051] Figure 2 depicts an expanded plan view of region 130 shown in Figure 1, including exemplary bit line (BL) TAC regions 160 of a 3D memory device. Figures 3A-3D depict expanded plan views of region 140 shown in Figure 1, including various exemplary word line (WL) TAC regions 170 of a 3D memory device. Figures 4A and 4B depict expanded plan views of region 150 shown in Figure 1, including various exemplary staircase structure (SS) TAC regions 180 of a 3D memory device.

[0052] 2, an expanded plan view of region 130 shown in FIG. 1 is illustrated, including an exemplary bitline (BL) TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 200 of the 3D memory device (i.e., region 130 as shown in FIG. 1) can include two channel structure regions 210 (e.g., adjacent memory blocks 115 in the BL direction) and a bitline (BL) TAC region 233 (e.g., BL TAC region 160 as shown in FIG. 1).

[0053] The channel structure region 210 can include an array of channel structures 212, each of which is a portion of a NAND string including multiple stacked memory cells. The channel structures 212 extend through multiple pairs of conductor and dielectric layers arranged along a direction perpendicular to the plane of the substrate of the 3D memory device (illustrated in cross section with respect to FIG. 5, described in detail below) and / or perpendicular to the plan view, also referred to as the "vertical direction."

[0054] The multiple conductor / dielectric layer pairs are also referred to herein as "alternating conductor / dielectric stacks." The number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack (e.g., 32, 64, or 96) can set the number of memory cells in the 3D memory device 100. The conductor and dielectric layers in the alternating conductor / dielectric stacks alternate vertically. In other words, each conductor layer can be bordered by two dielectric layers on either side, and each dielectric layer can be bordered by two conductor layers on either side, except for the one at the top or bottom of the alternating conductor / dielectric stack.

[0055] The conductor layer may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof. The dielectric layer may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layer includes a metal layer, such as W, and the dielectric layer includes silicon oxide.

[0056] In some embodiments, the BL TAC region 233 may be sandwiched by two adjacent channel structure regions 210 in the BL direction and may extend in the WL direction. The TAC region 233 may be defined by a barrier structure 224 together with the edges of the BL TAC region 233 of the 3D memory device. A plurality of TACs 226 may be formed in the BL TAC region 233, bounded laterally by the barrier structure 224 and the edges of the BL TAC region 233. In some embodiments, the plurality of TACs 226 in the BL TAC region 233 may penetrate the alternating dielectric stack for switch routing and to reduce bit line capacitance.

[0057] The alternating dielectric stack can include multiple dielectric layer pairs arranged along a vertical direction perpendicular to the plane of the substrate of the 3D memory device (illustrated in cross-section with respect to FIG. 5 described in detail below). Each dielectric layer pair includes a first dielectric layer and a second dielectric layer different from the first dielectric layer. In some embodiments, each of the first dielectric layer and the second dielectric layer includes silicon nitride and silicon oxide. The first dielectric layer in the alternating dielectric stack can be the same as the dielectric layer in the alternating conductor / dielectric stack described above. In some embodiments, the number of dielectric layer pairs in the alternating dielectric stack is the same as the number of conductor / dielectric layers in the alternating conductor / dielectric stack.

[0058] 2, each channel structure region 210 may include one or more slit structures 214, each extending in the WL direction. At least some of the slit structures 214 may function as a common source contact for the array of channel structures 212 in the channel structure region 210. The slit structures 214 may also divide the 3D memory device into a number of memory fingers 242 and / or dummy memory fingers 246. A top select gate cut 255 may be disposed in the middle of each memory finger 242 to divide the top select gate (TSG) of the memory finger into two parts. The top select gate cut 255 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0059] In some embodiments, dummy channel structures 222 are formed in portions of the channel structure region 210, such as in dummy memory fingers 246 adjacent to the BL TAC region 233, in the BL direction. The dummy channel structures 222 can provide mechanical support for the memory array structure. The dummy memory fingers 246 have no memory function, and therefore no bit lines and associated interconnect lines are formed in the dummy memory fingers 246.

[0060] 3A, an expanded plan view of region 140 shown in FIG. 1 is illustrated, including an example word line (WL) TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 300A of the 3D memory device (i.e., region 140 shown in FIG. 1) can include a channel structure region 320, a word line (WL) TAC region 372 (e.g., WL TAC region 170 shown in FIG. 1), and a top selective gate (TSG) staircase region 330.

[0061] 3A, the channel structure region 320 may include an array of channel structures 312, each including a plurality of stacked memory cells. The TSG staircase region 330 may be disposed adjacent to the WL TAC region 372 on the side of the channel structure region 320 in a plan view. That is, the WL TAC region 372 is sandwiched in the WL direction by the two TSG staircase regions 330. The WL TAC region 372 may be defined by a barrier structure 324. A plurality of TACs 326 used for switch routing and to reduce word line capacitance may be formed in the WL TAC region 372, laterally surrounded by the barrier structure 324.

[0062] In some embodiments, dummy channel structures 322 are formed outside of the WL TAC regions 372 to provide mechanical support for the memory array structure. It is understood that dummy channel structures 322 can be formed in any region other than the WL TAC regions 372, for example, in the TSG staircase region 330, along the edge of the channel structure region 320 adjacent to the TSG staircase region 330. It is noted that the channel structures 312 and dummy channel structures 322 pass through the alternating conductor / dielectric stacks, while the TAC 326 passes through the alternating dielectric stacks.

[0063] In some embodiments, a plurality of slit structures 314, each extending in the WL direction, can divide the 3D memory device into a plurality of memory fingers 342, 344. At least some of the slit structures 314 can function as a common source contact for the array of channel structures 312 in the channel structure region 320. The sidewalls of the slit structures 314 can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The fill material of the slit structures 314 can include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof.

[0064] An upper select gate cut 355 may be disposed midway between each memory finger 342, 344 to divide the upper select gate (TSG) of the memory finger into two portions. The upper select gate cut 355 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0065] It should be noted that the width of the WL TAC region 372 in the BL direction may be wider than the width of each memory finger 342 or 344. That is, in the BL direction, the barrier structure 324 can cross at least two adjacent slit structures 314. Therefore, the conductive layer in the channel structure region 320 in the memory finger 344 can be completely blocked by the barrier structure 324. Therefore, the upper selective gates of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 on both sides of the WL TAC region 372 are not interconnected by the upper conductor layer in the alternating conductor / dielectric stack.

[0066] To interconnect the upper selective gates of the channel structures 312 between the two channel structure regions 320 in the memory fingers 344 on either side of the WL TAC region 372, the TSG staircase region 330 may include one or more conductive lines (not shown in FIG. 3A ) formed in a staircase structure (e.g., within the top 2 to 4 steps) for electrically interconnecting the upper selective gates of the channel structures 312 between the two channel structure regions 320 in the memory fingers 344 separated by the WL TAC region 372.

[0067] For example, the slit structures 314 separated by the WL TAC regions 372 can extend into the TSG staircase region 330. The top two conductor layers in the alternating conductor / dielectric stack can have a one-sided staircase structure. One or more interconnect layers having contacts can be formed on the one-sided staircase structure to provide electrical interconnection between the top selectable gates of the channel structures 312 in the channel structure region 320 and those in the memory fingers 344 separated by the WL TAC regions 372.

[0068] Therefore, by introducing a TSG staircase region 330 that interconnects the top selectable gates on either side of the WL TAC region 372, the WL TAC region 372 can extend along the BL direction and be of a sufficient size to surround a desired number of TACs 326. Furthermore, each memory plane 110 shown in FIG. 1 can include multiple WL TAC regions 372 arranged in the WL direction. That is, multiple memory blocks 115 can be arranged in the WL direction in each memory plane 110.

[0069] 3B, an expanded plan view of region 140 shown in FIG. 1 is illustrated, including another exemplary word line (WL) TAC region of a 3D memory device according to some alternative embodiments of the present disclosure. Region 300B of the 3D memory device (i.e., region 140 shown in FIG. 1) can include a channel structure region 320, a dummy channel region 350 (e.g., WL TAC region 170 shown in FIG. 1) surrounding a word line (WL) TAC region 372.

[0070] 3B, the channel structure region 320 may include an array of channel structures 312, each including a plurality of stacked memory cells. A dummy channel region 350 is sandwiched in the WL direction by two channel structure regions 320. A WL TAC region 372 is surrounded by the dummy channel region 350. The WL TAC region 372 may be defined by a barrier structure 324. A plurality of TACs 326 may be formed in the WL TAC region 372 that is laterally surrounded by the barrier structure 324.

[0071] In some embodiments, dummy channel structures 322 are formed outside of the WL TAC regions 372 to provide mechanical support for the memory array structure. It is understood that dummy channel structures 322 can be formed in any region other than the WL TAC regions 372, for example, in the dummy channel region 350, along the edge of the channel structure region 320 adjacent to the dummy channel region 350. It is noted that the channel structures 312 and dummy channel structures 322 pass through the alternating conductor / dielectric stack, while the TAC 326 passes through the alternating dielectric stack.

[0072] In some embodiments, a number of slit structures 314, each extending in the WL direction, can divide the 3D memory device into a number of memory fingers 342, 344. A top select gate cut 355 can be disposed in the middle of each memory finger 342, 344 to divide the top select gate (TSG) of the memory finger into two parts.

[0073] It should be noted that the width of the WL TAC region 372 in the BL direction may be wider than the width of each memory finger 342 or 344. That is, in the BL direction, the barrier structure 324 can cross at least two adjacent slit structures 314. Therefore, the conductive layer in the channel structure region 320 in the memory finger 344 can be completely blocked by the barrier structure 324. Therefore, the upper selective gates of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 on both sides of the WL TAC region 372 are not interconnected by the upper conductor layer in the alternating conductor / dielectric stack.

[0074] Therefore, in some embodiments related to such a design of the WL TAC region 372, one memory plane 110 may include only two memory blocks 115 in the WL direction. The WL TAC region 372 is sandwiched by two memory blocks (i.e., the channel structure region 320 shown in FIG. 3B), while the outside of the channel structure region 320 in the WL direction may have a staircase structure (not shown in FIG. 3B). Thus, the upper selectable gates of the channel structure 312 between the two channel structure regions 320 in the memory fingers 344 on both sides of the WL TAC region 372 may be interconnected by using a staircase structure on the edge of the memory plane 110 of the 3D NAND device. Such a design may be suitable for zigzag word line decoder (X-DEC) routing.

[0075] 3C, an expanded plan view of the region 140 shown in FIG. 1 is illustrated, including another exemplary word line (WL) TAC region of a 3D memory device according to some alternative embodiments of the present disclosure. The region 300C of the 3D memory device (i.e., the region 140 shown in FIG. 1) can include a channel structure region 320, a dummy channel region 350 surrounding a plurality of word line (WL) TAC regions 376.

[0076] 3C , in some embodiments, a plurality of slit structures 314, each extending in the WL direction, can divide the 3D memory device into a plurality of memory fingers 342. A top select gate cut 355 can be disposed in the middle of each memory finger 342 to divide a top select gate (TSG) of the memory finger into two parts.

[0077] The channel structure region 320 may include an array of channel structures 312, each including a plurality of stacked memory cells. A dummy channel region 350 is sandwiched in the WL direction by two channel structure regions 320. A plurality of WL TAC regions 376 arranged in a row along the BL direction are surrounded by the dummy channel region 350. Each WL TAC region 376 may be defined by a barrier structure 324. A plurality of TACs 326 may be formed in each WL TAC region 376 that is laterally surrounded by the barrier structure 324.

[0078] In some embodiments, the width of each WL TAC region 376 in the BL direction may be narrower than the width of each memory finger 342. That is, the barrier structure 324 of each WL TAC region 376 may be disposed between two adjacent slit structures 314. Because the barrier structure 324 of each WL TAC region 376 does not completely block the conductive layer in the dummy channel region 350, the upper selective gates of the channel structures 312 between the two channel structure regions 320 in each memory finger 342 on either side of the WL TAC region 376 may be interconnected by an upper conductor layer in the alternating conductor / dielectric stack in the dummy channel region 350.

[0079] In some embodiments, dummy channel structures 322 are formed outside of the WL TAC regions 376 to provide mechanical support for the memory array structure. It is understood that dummy channel structures 322 can be formed in any region other than the WL TAC regions 376, for example, in the dummy channel region 350, along the edge of the channel structure region 320 adjacent to the dummy channel region 350. It is noted that the channel structures 312 and dummy channel structures 322 pass through the alternating conductor / dielectric stacks, while the TAC 326 passes through the alternating dielectric stacks.

[0080] Therefore, by disposing one WL TAC region 376 in each memory finger 342, the top conductor layer in the alternating conductor / dielectric stack may not be blocked by the WL TAC region 376. In this way, no additional structure is needed to further interconnect the top selectable gate of the channel structure 312 between the two channel structure regions 320 in each memory finger 342 on either side of the WL TAC region 376. Thus, multiple WL TAC regions 376 can be disposed in each memory finger 342 along the WL direction. That is, the memory 110 can include multiple memory blocks 115 in the WL direction.

[0081] 3D, an expanded plan view of region 140 shown in FIG. 1 is illustrated, including another exemplary word line (WL) TAC region of a 3D memory device, according to some alternative embodiments of the present disclosure. Region 300D of the 3D memory device (i.e., region 140 shown in FIG. 1) can include a channel structure region 320, a dummy channel region 350 surrounding a plurality of word line (WL) TAC regions 376.

[0082] As shown in FIG. 3D, in some embodiments, a plurality of slit structures 314, 316 each extending in the WL direction can divide the 3D memory device into a plurality of memory fingers 342. In some embodiments, the slit structure 314 can extend in the WL direction all the way through two or more channel structure regions 320 and one or more dummy channel regions 350. As shown in FIG. 3D, at least one slit structure 316 can include a gap 318 in the dummy channel region 350. An upper select gate cut 355 can be disposed in the middle of each memory finger 342 to divide the upper select gate (TSG) of the memory finger into two parts.

[0083] The channel structure region 320 may include an array of channel structures 312, each including a plurality of stacked memory cells. A dummy channel region 350 is sandwiched in the WL direction by two channel structure regions 320. A plurality of WL TAC regions 376 arranged in a row along the BL direction are surrounded by the dummy channel region 350. Each WL TAC region 376 may be defined by a barrier structure 324. A plurality of TACs 326 may be formed in each WL TAC region 376 that is laterally surrounded by the barrier structure 324.

[0084] In some embodiments, the width of each WL TAC region 376 in the BL direction may be narrower than the width of each memory finger 342. That is, the barrier structure 324 of each WL TAC region 376 may be disposed between two adjacent slit structures 314. Because the barrier structure 324 of each WL TAC region 376 does not completely block the conductive layer in the dummy channel region 350, the upper selective gates of the channel structures 312 between the two channel structure regions 320 in each memory finger 342 on either side of the WL TAC region 376 may be interconnected by an upper conductor layer in the alternating conductor / dielectric stack in the dummy channel region 350.

[0085] In some embodiments, dummy channel structures 322 are formed outside of the WL TAC regions 376 to provide mechanical support for the memory array structure. It is understood that dummy channel structures 322 can be formed in any region other than the WL TAC regions 376, for example, in the dummy channel region 350, along the edge of the channel structure region 320 adjacent to the dummy channel region 350. It is noted that the channel structures 312 and dummy channel structures 322 pass through the alternating conductor / dielectric stacks, while the TAC 326 passes through the alternating dielectric stacks.

[0086] In some embodiments, one or more slit structures 316 may include gaps 318 in the dummy channel regions 350. Word lines in adjacent memory fingers 342 may be interconnected by using conductive lines passing through the gaps 318. For example, as shown in FIG. 3D, the slit structures 314 at the edge of the memory block 115 may extend in the WL direction all the way through two or more channel structure regions 320 and one or more dummy channel regions 350, while the slit structures 316 inside each memory block 115 may each include one or more gaps 318 in the corresponding dummy channel region 350. Therefore, all the upper select gates and / or word lines in the same memory block 115 may be interconnected without additional structures.

[0087] Therefore, by disposing the WL TAC regions 376 in the memory fingers 342 and providing the gaps 318 in the slit structures 316, the upper conductor layer in the alternating conductor / dielectric stack may not be blocked by the WL TAC regions 376 and may interconnect the word lines in adjacent memory fingers 342. Thus, multiple WL TAC regions 376 may be disposed in each memory finger 342 along the WL direction. That is, the memory 110 may include multiple memory blocks 115 in the WL direction. Such a structure may have a high integration level and a simple layout that may be easily manufactured.

[0088] 4A, an expanded plan view of region 150 shown in FIG. 1 is illustrated, including an example staircase structure (SS) TAC region of a 3D memory device according to some embodiments of the present disclosure. Region 400A of the 3D memory device (i.e., region 150 shown in FIG. 1) can include a channel structure region 420, a staircase region 410, and a staircase structure (SS) TAC region 482.

[0089] The channel structure region 420 can include an array of channel structures 412, each including a plurality of stacked memory cells. The staircase region 410 can include an array of staircase structures and wordline contacts 432 formed on the staircase structures. In some embodiments, an SS TAC region 482 is in the staircase region 410. The SS TAC region 482 can be defined by the barrier structure 424 alone or in conjunction with an edge of the staircase region 410 of the 3D memory device. A plurality of TACs 426 can be formed in the SS TAC region 482 that is laterally bounded by at least the barrier structure 424.

[0090] 4A, in some embodiments, a plurality of slit structures 414, 416 each extending in the WL direction can divide the 3D memory device into a plurality of memory fingers 442, 444. In some embodiments, the slit structures 414 can extend in the WL direction into at least a portion of the staircase region 410. At least some of the slit structures 416 can include one or more gaps 418 in the staircase region 410. A top select gate cut 455 can be disposed in the middle of each memory finger 442, 444 to divide a top select gate (TSG) of the memory finger into two portions.

[0091] In some embodiments, one or more slit structures 416 may include gaps 418 in the staircase region 410. Word line contacts 432 in adjacent memory fingers 442 may be interconnected by using conductive lines passing through the gaps 418. For example, as shown in FIG. 4A, the slit structures 414 at the edge of the memory block 115 may extend in the WL direction all the way through the channel structure region 420 and the staircase region 410, while the slit structures 416 inside each memory block 115 may include one or more gaps 418 in the staircase region 410. Therefore, all word line contacts 432 in the same memory block 115 may be interconnected without additional structures.

[0092] It should be noted that the width of the SS TAC region 482 in the BL direction may be wider than the width of each memory finger 442, 444. That is, in the BL direction, the barrier structure 424 can cross at least two adjacent slit structures 414. Because the SS TAC region 482 occupies a portion of the area of ​​the staircase region 410 corresponding to the memory finger 444 that is completely blocked by the barrier structure 424, the staircase structure in the SS TAC region 482 is used to form the TAC 426 rather than to form the word line contact 432 for the memory finger 444. Thus, the staircase structure (not shown in FIG. 4B ) corresponding to the memory finger 444 on the other side of the memory plane 110 can be used to form the word line contact 432 rather than the SS TAC region 482.

[0093] Thus, in some embodiments related to such a design of the SS TAC regions 482, the SS TAC regions 482 on both sides of the memory plane 110 do not overlap in the WL direction. That is, one memory finger corresponds to at most one SS TAC region 482. Such a design may be suitable for zigzag word line decoder (X-DEC) routing. Furthermore, in some embodiments related to such a design of the SS TAC regions 482, similar to the WL TAC region 372 described above with respect to FIG. 3B, the SS TAC regions 482 and the WL TAC regions 372 do not overlap in the WL direction due to the same reasons. That is, one memory finger corresponds to at most one either one SS TAC region 482 or one WL TAC region 372.

[0094] 4B, an expanded plan view of region 150 shown in FIG. 1 is illustrated, including other exemplary staircase structure (SS) TAC regions of a 3D memory device according to some alternative embodiments of the present disclosure. Region 400B of the 3D memory device (i.e., region 150 shown in FIG. 1) can include a channel structure region 420, a staircase region 410, and multiple staircase structure (SS) TAC regions 484.

[0095] The channel structure region 420 can include an array of channel structures 412, each including a plurality of stacked memory cells. The staircase region 410 can include an array of staircase structures and wordline contacts 432 formed on the staircase structures. In some embodiments, SS TAC regions 484 are in the staircase region 410. Each SS TAC region 484 can be defined by the barrier structure 424 alone or in conjunction with an edge of the staircase region 410 of the 3D memory device. A plurality of TACs 426 can be formed in the SS TAC region 482 that is laterally bounded by at least the barrier structure 424.

[0096] As shown in FIG. 4B, in some embodiments, a plurality of slit structures 414 each extending in the WL direction in the channel structure region 420 can divide the 3D memory device into a plurality of memory fingers 442. A top select gate cut 455 can be disposed in the middle of each memory finger 442 to divide the top select gate (TSG) of the memory finger into two parts. In some embodiments, the slit structure 414 can extend in the WL direction into at least a portion of the staircase region 410. In some embodiments, the staircase region 410 can further include a plurality of slit structures 416 that are not aligned with the slit structure 414 in the WL direction. That is, the distance between adjacent slit structures in the staircase region 410 can be non-uniform. Some adjacent slit structure pairs can have a first distance that is longer than a second distance between other adjacent slit structure pairs.

[0097] In some embodiments, each SS TAC region 484 may be disposed between adjacent pairs of slit structures having a first distance. That is, the width of the SS TAC region 484 in the BL direction may be narrower than the first distance. Therefore, in addition to the space occupied by the SS TAC region 484, the staircase region 410 between such adjacent pairs of slit structures having the first distance may have extra space for forming the word line contact 432.

[0098] Referring to Figure 5, a schematic cross-sectional view of an exemplary 3D memory device 500 is illustrated in accordance with some embodiments of the present disclosure. The 3D memory device 500 may be part of a non-monolithic 3D memory device, the components of which (e.g., peripheral devices and array devices) may be formed separately on different substrates. For example, the 3D memory device 500 may be region 130, region 140, or region 150, described above with respect to Figure 1.

[0099] As shown in Figure 5, the 3D memory device 500 can include a substrate 570 and an array device on the substrate 570. Note that X and Y axes have been added to Figure 5 to further illustrate the spatial relationships of components in the 3D memory device 500. The substrate 570 includes two lateral surfaces (e.g., a top surface 572 and a bottom surface 574) that extend laterally in the X direction (horizontally, e.g., in the WL or BL direction).

[0100] As used herein, whether one component (e.g., a layer or device) is on, above, or below another component (e.g., a layer or device) of a semiconductor device (e.g., 3D memory device 500) is determined relative to a substrate (e.g., substrate 570) of the semiconductor device in the Y direction (vertical direction) when the substrate is located at the lowest surface of the semiconductor device in the Y direction. The cross-sectional view of the 3D memory device 500 shown in FIG. 5 is along the BL and Y direction planes. The same concepts for describing spatial relationships apply throughout this disclosure.

[0101] The substrate 570 may be used to support the array device and may include a circuit board 530 and an epitaxial substrate 540. The circuit board 530 may include a base substrate 510 and one or more peripheral circuits (not shown in FIG. 5) formed above the base substrate 510. The base substrate 510 may include any suitable semiconductor material, which may include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. In some embodiments, the base substrate 510 is a thinned substrate (e.g., a semiconductor layer) that has been thinned by polishing, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof.

[0102] The one or more peripheral circuits fabricated on the circuit board 530 can include any suitable digital, analog, and / or mixed-signal peripheral circuitry used to facilitate operation of the 3D memory device 500, such as page buffers, decoders, and latches (not shown in FIG. 5). In some embodiments, the circuit board 530 can further include one or more interconnect structures 532 for electrically connecting the one or more peripheral circuits to an array device above the substrate 570. The one or more interconnect structures 532 can include any suitable conductive structures, including, but not limited to, contacts, single / multi-layer vias, conductive layers, plugs, and the like.

[0103] The epitaxial substrate 540 can be formed on the circuit board 530 by using a deposition process including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The epitaxial substrate 540 can be a single layer substrate or a multilayer substrate, such as, for example, a single crystal single layer substrate, a polycrystalline silicon (polysilicon) single layer substrate, a polysilicon and metal multilayer substrate, and the like. Additionally, one or more openings 542 can be formed in an area of ​​the epitaxial substrate 540 corresponding to one or more through array contact (TAC) structures of an array device. The multiple TACs 526 can pass through the one or more openings 542 to electronically connect with one or more interconnect structures 532 in the circuit board 530.

[0104] In some embodiments, the 3D memory device 500 is a NAND type flash memory device in which memory cells are provided in an array of channel structures extending in the Y direction above a substrate 570 (not shown in FIG. 5). The array device may include multiple channel structures extending through an alternating conductor / dielectric stack 580 that includes multiple conductor layer 580A and dielectric layer 580B pairs. The number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack 580 (e.g., 32, 64, or 96) may set the number of memory cells in the 3D memory device 500.

[0105] The conductor layers 580A and the dielectric layers 580B in the alternating conductor / dielectric stack 580 alternate in the Y direction. In other words, except for the one at the top or bottom of the alternating conductor / dielectric stack 580, each conductor layer 580A can be bordered on both sides by two dielectric layers 580B, and each dielectric layer 580B can be bordered on both sides by two conductor layers 580A. The conductor layers 580A can each have the same thickness or have different thicknesses. Similarly, the dielectric layers 580B can each have the same thickness or have different thicknesses. The conductor layers 580A can include conductor materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof. The dielectric layers 580B can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductor layer 580A comprises a metal layer, such as W, and the dielectric layer 580B comprises silicon oxide.

[0106] In some embodiments, the array device further includes slit structures 514. Each slit structure 514 can extend in the Y direction through the alternating conductor / dielectric stack 580. The slit structures 514 can also extend laterally (i.e., parallel to the substrate) to separate the alternating conductor / dielectric stack 580 into multiple blocks. The slit structures 514 can include slits filled with a conductor material, including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. The slit structures 514 can further include a dielectric layer having any suitable dielectric material between the filled conductor material and the alternating conductor / dielectric stack 580 to electrically insulate the filled conductor material from the surrounding conductor layer 580A in the alternating conductor / dielectric stack 580. As a result, the slit structures 514 can separate the 3D memory device 500 into multiple memory fingers (e.g., as shown in FIG. 2, FIG. 3A-FIG. 3D, FIG. 4A-FIG. 4B in plan view).

[0107] In some embodiments, the slit structure 514 serves as a source contact for channel structures in the same memory finger that share the same array common source. The slit structure 514 can thus be referred to as a "common source contact" for multiple channel structures. In some embodiments, the epitaxial substrate 540 includes a doped region 544 (containing a p-type or n-type dopant at a desired doping level), and a bottom edge of the slit structure 514 contacts the doped region 544 of the epitaxial substrate 540.

[0108] In some embodiments, the alternating dielectric stack 560 can be disposed in a region laterally surrounded by the barrier structure 516 on the epitaxial substrate 540. The alternating dielectric stack 560 can include multiple dielectric layer pairs. For example, the alternating dielectric stack 560 is formed by an alternating stack of a first dielectric layer 560A and a second dielectric layer 560B that is different from the first dielectric layer 560A. In some embodiments, the first dielectric layer 560A comprises silicon nitride and the second dielectric layer 560B comprises silicon oxide. The second dielectric layer 560B in the alternating dielectric stack 560 can be the same as the dielectric layer 580B in the alternating conductor / dielectric stack 580. In some embodiments, the number of dielectric layer pairs in the alternating dielectric stack 560 is the same as the number of conductor / dielectric layer pairs in the alternating conductor / dielectric stack 580.

[0109] In some embodiments, the barrier structures 516 extending in the Y-direction laterally separate the alternating conductor / dielectric stacks 580 and the alternating dielectric stacks 560. That is, the barrier structures 516 may be a boundary between the alternating conductor / dielectric stacks 580 and the alternating dielectric stacks 560. The alternating dielectric stacks 560 may be laterally surrounded by at least the barrier structures 516. In some embodiments, the barrier structures 516 are closed shapes (e.g., rectangles, squares, circles, etc.) in plan view since they completely surround the alternating dielectric stacks 560. For example, as shown in Figures 3A-3D, the barrier structures 324 are rectangular shaped in plan view since they completely surround the alternating dielectric stacks in the WL TAC regions 372, 376. In some embodiments, the barrier structures 516 are not closed shapes in plan view but may surround the alternating dielectric stacks 560 along with one or more edges of the array device. For example, as shown in Figures 4A and 4B, a barrier structure 424 along with the edges of the 3D memory device surrounds the alternating dielectric stacks in the SS TAC regions 482, 484.

[0110] As shown in FIG. 5, the 3D memory device 500 further includes a plurality of TACs 526 each extending in the Y direction through the alternating dielectric stack 560. The TACs 526 can be formed only inside an area laterally surrounded by at least the barrier structure 516, including the plurality of dielectric layer pairs. That is, the TACs 526 can extend vertically through the dielectric layers (e.g., the first dielectric layer 560S and the second dielectric layer 560B), but not through any of the conductor layers (e.g., the conductor layer 580A). Each TAC 526 can extend through the entire thickness of the alternating dielectric stack 560 (e.g., all dielectric layer pairs in the Y direction). In some embodiments, the TACs 526 further penetrate the epitaxial substrate 540 through the openings 542 and electrically contact the interconnect structure 532.

[0111] The TACs 526 can carry electrical signals to and from the 3D memory device 500 in a shortened interconnect path, such as a portion of a power bus. In some embodiments, the TACs 526 can provide electrical connections between the array device and peripheral devices (not shown in FIG. 5 ) through one or more interconnect structures 532. The TACs 526 can also provide mechanical support for the alternating dielectric stacks 560. Each TAC 526 can include a vertical opening through the alternating dielectric stacks 560, which is filled with a conductive material, including, but not limited to, W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. In some embodiments, because the TACs 526 are formed in the alternating dielectric stacks 560 (surrounded by a dielectric layer), an additional dielectric layer between the TACs 526 and the alternating dielectric stacks 560 is not required for insulation purposes.

[0112] 6, a simplified flowchart of an exemplary method 600 for forming a 3D memory device is illustrated, in accordance with some embodiments of the present disclosure. It should be understood that the operations illustrated in method 600 are not exhaustive, and that other operations can be performed before, after, or between any of the operations described, as well.

[0113] 6, method 600 begins at operation 602, where a substrate is formed. In some embodiments, forming the substrate may include forming a base substrate, forming at least one peripheral circuit on the substrate, forming at least one interconnect structure in electronic contact with the at least one peripheral circuit, and forming an epitaxial substrate on the at least one peripheral circuit.

[0114] The base substrate can be formed by using any suitable semiconductor material, which can include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any suitable combination thereof. In some embodiments, forming the base substrate includes a thinning process including polishing, wet / dry etching, chemical mechanical polishing (CMP), or any combination thereof.

[0115] The one or more peripheral circuits may include any suitable digital, analog, and / or mixed-signal peripheral circuits, including, but not limited to, page buffers, decoders, and latches. In some embodiments, the one or more interconnect structures may include any suitable conductive structures, including, but not limited to, contacts, single / multi-layer vias, conductive layers, plugs, etc.

[0116] The epitaxial substrate may be formed above one or more peripheral circuits by using a deposition process including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The epitaxial substrate may be a single layer substrate or a multilayer substrate, such as, for example, a single crystal single layer substrate, a polycrystalline silicon (polysilicon) single layer substrate, a polysilicon and metal multilayer substrate, etc.

[0117] In some embodiments, forming the epitaxial substrate further includes forming one or more openings such that at least a portion of the one or more interconnect structures are exposed by the one or more openings. The one or more openings can correspond to one or more through array contact TAC structures (e.g., a word line (WL) TAC structure as shown in FIG. 2, a bit line (BL) TAC structure as shown in FIGS. 3A-3D, a staircase structure (SS) TAC structure as shown in FIGS. 4A-4B) to be formed in a subsequent process. The one or more openings can be filled with a dielectric material.

[0118] The method 600 proceeds to operation 604, where an alternating dielectric stack is formed on the substrate. In some embodiments, multiple pairs of first and second dielectric layers may be formed on the substrate to form the alternating dielectric stack. In some embodiments, each dielectric layer pair includes a layer of silicon nitride and a layer of silicon oxide. The alternating dielectric stack may be formed by one or more thin film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0119] The method 600 proceeds to operation 606, where a staircase structure is formed on one or more edges of the alternating dielectric stack. In some embodiments, a trim etch process may be performed on at least one side (laterally) of the alternating dielectric stack to form a staircase structure having multiple steps. Each step may include one or more dielectric layer pairs having alternating first and second dielectric layers.

[0120] The method 600 continues at operation 608 where a plurality of channel structures and one or more barrier structures are formed. Each channel structure and each barrier structure may extend vertically through the alternating dielectric stack.

[0121] In some embodiments, the fabrication process for forming the channel structure includes forming a channel hole that extends vertically through the alternating dielectric stack, for example, by wet etching and / or dry etching. In some embodiments, the fabrication process for forming the channel structure further includes forming a semiconductor channel and a memory film between the semiconductor channel and the pair of dielectric layers in the alternating dielectric stack. The semiconductor channel can include a semiconductor material such as polysilicon. The memory film can be a composite dielectric layer, such as a combination of a tunneling layer, a storage layer, and a blocking layer.

[0122] The tunneling layer may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Electrons or holes from the semiconductor channel may tunnel through the tunneling layer to the storage layer. The storage layer may include a material for storing charge for memory operations. Storage layer materials include, but are not limited to, silicon nitride, silicon oxynitride, a combination of silicon oxide and silicon nitride, or any combination thereof. The blocking layer may include a dielectric material including, but not limited to, silicon oxide or a combination of silicon oxide / silicon nitride / silicon oxide (ONO). The blocking layer may include a material such as aluminum oxide (Al 2 O 3 The semiconductor channel and memory films may further include a high-k dielectric layer, such as a SiO 2 layer. The semiconductor channel and memory films may be formed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or a combination thereof.

[0123] In some embodiments, the manufacturing process for forming the barrier structures is performed simultaneously as the manufacturing process for forming the channel structures, thereby reducing manufacturing complexity and cost, in some embodiments, the channel structures and the barrier structures are formed in different manufacturing steps such that the barrier structures can be filled with a different material than the material filling the channel structures.

[0124] In some embodiments, the fabrication process for forming the barrier structure includes forming trenches extending vertically through the alternating dielectric stack, for example by wet etching and / or dry etching. After the trenches are formed through the alternating dielectric stack, the alternating dielectric stack is then etched using a material such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon oxide / silicon nitride / silicon oxide (ONO), aluminum oxide (Al 2 O 3 One or more thin film deposition processes can be performed to fill the trench with a dielectric material including, for example, a SiO 2 thin film ...

[0125] By forming one or more barrier structures, the alternating dielectric stack can be separated into two types of regions: one or more inner regions, each laterally surrounded by at least a barrier structure (in some embodiments, along with the edges of the alternating dielectric stack), and outer regions in which a channel structure and / or word line contacts can be formed. Note that each inner region corresponds to an opening in the epitaxial substrate.

[0126] In some embodiments, at least one inner region may be used to form a BL TAC structure, as described above with respect to Figure 2. As such, a barrier structure surrounding such inner region may include two parallel barrier walls extending along the WL direction.

[0127] In some embodiments, at least one inner region may be used to form a BL TAC structure, as described above with respect to FIG. 3A or FIG. 3B. Therefore, the barrier structure surrounding such inner region may have a rectangular shape. The width of the barrier structure in the BL direction may be wider than the distance between two adjacent slit structures formed in a subsequent process.

[0128] In some embodiments, at least one inner region may be used to form a BL TAC structure, as described above with respect to FIG. 3C or FIG. 3D. Therefore, the barrier structure surrounding such inner region may have a rectangular shape. The width of the barrier structure in the BL direction may be narrower than the distance between two adjacent slit structures formed in a subsequent process.

[0129] In some embodiments, at least one inner region can be used to form the SS TAC structure, as described above with respect to FIG. 4A. Therefore, the barrier structure for separating such inner regions can have a rectangular shape with one open edge facing the edge of the staircase structure. The width of the barrier structure in the BL direction can be wider than the distance between two adjacent slit structures formed in the subsequent process.

[0130] In some embodiments, at least one inner region can be used to form the SS TAC structure, as described above with respect to FIG. 4B. Therefore, the barrier structure for separating such inner regions can have a rectangular shape with one open edge facing the edge of the staircase structure. The width of the barrier structure in the BL direction can be narrower than the maximum distance between two adjacent slit structures formed in the staircase region in the subsequent process.

[0131] In some embodiments, the dummy channel structure can be formed simultaneously with the channel structure. The dummy channel structure can extend vertically through the alternating layer stack and can be filled with the same material as in the channel structure. Unlike the channel structure, no contacts are formed on the dummy channel structure to realize electrical connection with other components of the 3D memory device. Thus, the dummy channel structure cannot be used to form memory cells in the 3D memory device.

[0132] Method 600 proceeds to operation 610, where a number of slits are formed through which a first dielectric layer in a portion of the alternating dielectric stack is replaced with a conductor layer. For example, a number of parallel slits extending in the WL direction may first be formed through the alternating dielectric stack in the outer region by wet and / or dry etching of the dielectric (e.g., silicon oxide and silicon nitride). In some embodiments, a doped region is then formed through the slits and in the epitaxial substrate below each slit, for example, by ion implantation and / or thermal diffusion. It is understood that according to some embodiments, the doped region may be formed at an earlier manufacturing stage, for example, before the formation of the slits.

[0133] In some embodiments, the formed slits are used for a gate replacement process (also known as a "word line replacement" process) to replace the first dielectric layer (e.g., silicon nitride) with a conductor layer (e.g., W) in the outer zone of the alternating dielectric stack. Note that the gate replacement occurs only in the outer zone of the alternating dielectric stack and not in the inner zone due to the formation of the barrier structure. The barrier structure can prevent etching of the first dielectric layer (e.g., silicon nitride) in the inner zone of the alternating dielectric stack because the barrier structure is filled with a material that cannot be etched in the etching step of the gate replacement process.

[0134] As a result, after the gate replacement process, the alternating dielectric stack in the outer region becomes an alternating conductor / dielectric stack. The replacement of the first dielectric layer with a conductor layer can be performed by wet etching the first dielectric layer (e.g., silicon nitride) selectively to the second dielectric layer (e.g., silicon oxide) and filling the structure with a conductor layer (e.g., W). The conductor layer can be filled by PVD, CVD, ALD, any other suitable process, or any combination thereof. The conductor layer can include conductor materials including, but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof.

[0135] Method 600 proceeds to operation 612, where a slit structure is formed by filling (e.g., depositing) a conductive material into the slit by PVD, CVD, ALD, any other suitable process, or any combination thereof. The slit structure may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, silicides, or any combination thereof. In some embodiments, for insulation purposes, a dielectric layer (e.g., a silicon oxide layer) is first formed between the conductive material of the slit structure and a conductive layer surrounding the slit structure in the alternating conductor / dielectric stack. The bottom edge of the slit structure may be in contact with the doped region.

[0136] The method 600 proceeds to operation 614, where multiple TACs are formed through the alternating dielectric stack. The TACs may be formed in one or more interior regions by first etching vertical openings (e.g., by wet and / or dry etching) and then filling the openings with a conductive material using ALD, CVD, PVD, any other suitable process, or any combination thereof. The conductive material used to fill the local contacts may include, but is not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. In some embodiments, other conductive materials are also used to fill the openings to act as barrier layers, adhesion layers, and / or seed layers.

[0137] The TAC can be formed by etching through the entire thickness of the alternating dielectric stack and the dielectric layers formed in the openings in the epitaxial substrate. Because the alternating dielectric stack includes alternating layers of dielectrics such as silicon oxide and silicon nitride, the openings in the TAC can be formed by deep etching of the dielectric material (e.g., by a deep reactive ion etching (DRIE) process or any suitable anisotropic etching process). In some embodiments, the TAC penetrates the epitaxial substrate through the openings in the epitaxial substrate. The bottom edge of the TAC can contact an interconnect structure in the substrate. Thus, the TAC can be electrically connected to peripheral devices formed in the substrate.

[0138] In some embodiments, the TAC is formed after gate replacement, but by leaving areas of the alternating dielectric stack unaffected (not turned into an alternating conductor / dielectric stack) by the gate replacement process, the TAC is still formed through the dielectric layers (without passing through any conductor layers), thereby simplifying the manufacturing process and reducing costs.

[0139] Various embodiments according to the present disclosure provide a 3D memory device having a through array contact structure for a memory array. The through array contact structure disclosed herein includes TAC to realize vertical interconnection between stacked array devices and peripheral devices (e.g., for power buses and metal wiring), thereby reducing metal steps and decreasing die size. In some embodiments, the TAC in the through array contact structure disclosed herein is formed through a stack of alternating dielectric layers, which can be more easily etched to form through holes therein, compared to a stack of alternating conductor and dielectric layers, thereby reducing process complexity and manufacturing costs.

[0140] Accordingly, one aspect of the present disclosure discloses a three-dimensional (3D) NAND memory device including a substrate including at least one peripheral circuit and an alternating layer stack disposed on the substrate. The alternating layer stack includes a first region including an alternating dielectric stack including a plurality of dielectric layer pairs, a second region including an alternating conductor / dielectric stack including a plurality of conductor / dielectric layer pairs, and a third region including a staircase structure on an edge of the alternating conductor / dielectric layer stack in a word line direction. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region or the third region, a plurality of channel structures and a plurality of slit structures each extending vertically through the alternating conductor / dielectric stack, and a plurality of through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one of the plurality of through array contacts is electrically connected to at least one peripheral circuit.

[0141] Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) NAND memory device. The method includes forming a substrate including at least one peripheral circuit, forming an alternating dielectric stack on the substrate including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs including a first dielectric layer and a second dielectric layer different from the first dielectric layer, forming a staircase structure at an edge of the alternating dielectric stack, and forming a plurality of channel structures and at least one barrier structure, each extending vertically through the alternating dielectric stack. The at least one barrier structure separates the alternating dielectric stack into at least one first region and a second region laterally bounded by at least the barrier structure. The method further includes forming a plurality of slits and replacing the first dielectric layer in a second portion of the alternating dielectric stack with a conductor layer through the slits to form an alternating conductor / dielectric stack including a plurality of conductor / dielectric layer pairs; depositing a conductive material into the slits to form a plurality of slit structures; and forming a plurality of through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack to electrically connect at least one of the plurality of through array contacts to at least one peripheral circuit.

[0142] The above description of the specific embodiments fully reveals the general nature of the present disclosure, so that others can easily modify and / or adapt such specific embodiments for various applications by applying the knowledge of those skilled in the art without departing from the general concept of the present disclosure and without undue experimentation. Therefore, based on the teaching and guidance presented herein, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments. It should be understood that the phraseology or terminology in this specification is for the purpose of description and not for the purpose of limitation, and therefore the phraseology or terminology in this specification should be interpreted by those skilled in the art in light of the teaching and guidance.

[0143] The embodiments of the present disclosure are described above using functional building blocks that illustrate implementations of specified functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for convenience of description. Alternative boundaries can be defined so long as the specified functions and their relationships are appropriately implemented.

[0144] The Summary and Abstract sections may describe one or more, but not all, exemplary embodiments of the present disclosure contemplated by the inventors, and are therefore not intended to limit the disclosure and the appended claims in any way.

[0145] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0146] 100 3D Memory Devices 110 Memory Plane 115 Memory Blocks 120 Contact Pad 130 areas 140 areas 150 areas 160 bit line (BL) TAC area, word line (BL) TAC area 170 Word Line (WL) TAC Area 180 Staircase structure (SS) TAC area 200 areas 210 Channel Structure Region 212 Channel Structure 214 Slit Structure 222 Dummy Channel Structure 224 Barrier Structure 226 TAC 233 Bit Line (BL) TAC Area 242 Memory Finger 246 Dummy Memory Finger 255 Upper selective gate cut 300A area 300B area 300C area 300D area 312 Channel Structure 314 Slit structure 316 Slit Structure 318 Gap 320 Channel Structure Region 322 Dummy Channel Structure 314 Barrier Structure 326 TAC 330 Top Selective Gate (TSG) Staircase Region 342 Memory Finger 344 Memory Finger 350 Dummy Channel Area 355 Upper selective gate cut 372 Word Line (WL) TAC Area 376 Word Line (WL) TAC Area 400A area 400B area 410 Stairs area 414 Slit structure 416 Slit Structure 418 Gap 420 Channel Structure Region 424 Barrier Structure 426 TAC 432 word line contact 442 Memory Finger 444 Memory Finger 455 Upper selective gate cut 482 Staircase structure (SS) TAC area 484 Staircase structure (SS) TAC area 500 3D memory devices 510 Base Board 514 Slit structure 516 Barrier Structure 526 TAC 530 Circuit Board 532 Interconnect Structure 540 Epitaxial Substrate 542 Aperture 544 Doped Region 560 Alternating Dielectric Stack 560A First Dielectric Layer 560B Second Dielectric Layer 560S First Dielectric Layer 570 Substrate 572 Top surface 574 Bottom 580 Alternating Conductor / Dielectric Stack 580A Conductor Layer 580B Dielectric layer 600 ways

Claims

1. a first stack comprising first and second vertically alternating dielectric layers; a second stack comprising the vertically alternating conductor layers and a third dielectric layer; a staircase region extending from the first stack and the second stack, the staircase region including a staircase structure defining a slope having an upper end and a lower end in the vertical direction; a contact penetrating the first stack in the staircase region; a barrier structure separating the first stack from the second stack along the top edge and terminating at a bottom edge of the staircase region without completely enclosing the first stack in the staircase region; a first slit structure and a second slit structure extending laterally through the second stack; Equipped with A three-dimensional (3D) memory device, wherein the first slit structure is misaligned with the second slit structure in the lateral direction.

2. a channel region having a channel structure penetrating the second stack in the vertical direction, the channel region and the step region being disposed in a lateral direction perpendicular to the vertical direction; The memory device of claim 1 , wherein the top edge is closer to the channel region than the bottom edge.

3. the barrier structure includes a first sub-barrier structure and two parallel second sub-barrier structures, the two parallel second sub-barrier structures extending along a lateral direction perpendicular to the vertical direction, the first stack being between the two parallel second sub-barrier structures; 2. The memory device of claim 1, wherein ends of the two parallel second sub-barrier structures are connected by the first sub-barrier structure and other ends of the two parallel second sub-barrier structures are not connected.

4. The memory device of claim 3 further comprising a contact area having said contact.

5. The memory device of claim 1 , wherein the staircase structure in the staircase region has wordline contacts.

6. 4. The memory device of claim 3, further comprising a dummy channel structure extending through the second stack, the dummy channel structure being located on either side of the two parallel second sub-barrier structures along a bit line direction, the bit line direction being perpendicular to the vertical direction.

7. The memory device of claim 1 , wherein at least one of the contacts is connected to at least one peripheral circuit.

8. the first dielectric layer and the second dielectric layer comprise different materials; The memory device of claim 1 , wherein the first dielectric layer and the third dielectric layer comprise the same material.

9. a first substrate having an interconnect structure; a second substrate disposed on the first substrate; Further equipped with The memory device of claim 1 , wherein at least one contact extends through the second substrate and connects to the interconnect structure.

10. The memory device of claim 1 , wherein the barrier structure comprises silicon oxide.

11. the first dielectric layer comprises a silicon oxide layer; the second dielectric layer comprises a silicon nitride layer; the conductor layer includes a metal layer; The memory device of claim 1 , wherein the third dielectric layer comprises a silicon oxide layer.

12. The memory device of claim 1, wherein the first and second slit structures divide the second stack into memory fingers.

13. The memory device of claim 12 , wherein the first and second slit structures comprise a conductive material.

14. At least one of the second slit structures is between two adjacent first slit structures; The memory device of claim 1 , wherein the barrier structure is between two adjacent first slit structures.

15. a first stack comprising first and second vertically alternating dielectric layers; a second stack comprising the vertically alternating conductor layers and a third dielectric layer; a contact passing through the first stack in the vertical direction; a barrier structure separating the first stack and the second stack; a slit structure extending laterally through the second stack, the slit structure dividing the second stack into memory fingers, the slit structure including a conductive material; and Equipped with the lateral direction is perpendicular to the vertical direction; the slit structure includes a first slit structure and a second slit structure, the first slit structure and the second slit structure extending vertically through the second stack and laterally along the lateral direction; the first slit structure is not aligned with the second slit structure in the lateral direction; A three-dimensional (3D) memory device, wherein at least one of the second slit structures is between two adjacent first slit structures, and the barrier structure is between the two adjacent first slit structures.

16. The memory device of claim 15 , wherein at least one of the contacts is connected to at least one peripheral circuit.

17. The memory device of claim 15 , wherein the first stack and the second stack are separated by two parallel second sub-barrier structures extending along the lateral direction.

18. the laterally disposed channel region and step region, a channel structure located in the channel region and extending through the second stack in the vertical direction; The memory device of claim 15 , wherein the first stack and the barrier structure are located in the staircase region.

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